text stringlengths 1 1.05M |
|---|
;
; ZX Spectrum specific routines
; by Stefano Bodrato, 28/06/2006
;
; Copy a variable to basic
;
; int __CALLEE__ zx_setfloat_callee(char *variable, float value);
;
; $Id: zx_setfloat_callee.asm,v 1.6 2016-06-10 20:02:04 dom Exp $
;
SECTION code_clib
PUBLIC zx_setfloat_callee
PUBLIC _zx_setfloat_callee
PUBLIC ASMDISP_zx_setfloat_CALLEE
EXTERN call_rom3
EXTERN zx_locatenum
EXTERN fa
zx_setfloat_callee:
_zx_setfloat_callee:
pop hl ; ret addr
pop de
pop de
pop de ; float value is already in FA
;pop de ; var name
ex (sp),hl ; ret addr <-> var name
; enter : (FA) = float value
; hl = char *variable
.asmentry
;push de
push hl
call zx_locatenum
jr nc,store
; variable not found: create space for a new one
pop hl
push hl
ld c,0
vlcount:
ld a,(hl)
inc c
and a
inc hl
jr nz,vlcount
dec c
ld a,5 ; 5 bytes + len of VAR name
add c
ld c,a
ld b,0
ld hl,($5c59) ; E_LINE
dec hl ; now HL points to end of VARS
IF FORts2068
call $12BB ; MAKE-ROOM
ELSE
call call_rom3
defw $1655 ; MAKE-ROOM
ENDIF
inc hl
pop de ; point to VAR name
cp 6
ld a,(de)
jr nz,morethan1
or 32 ; fall here if the variable name is
ld (hl),a ; only one char long
inc hl
jr store2
morethan1:
and 63 ; first letter of a long numeric variable name
or 160 ; has those odd bits added
ld (hl),a
lfloatlp:
inc de
ld a,(de) ; now we copy the body of the VAR name..
and a
jr z,endlfloat
or 32
inc hl
ld (hl),a
djnz lfloatlp
endlfloat:
ld a,(hl)
or 128 ; .. then we fix the last char
ld (hl),a
inc hl
jr store2
store:
pop bc ; so we keep HL pointing just after the VAR name
store2:
;pop de
; Store float value in VAR memory
ld de,fa+5
ex de,hl
ld b,5
.mvloop
ld a,(hl)
ld (de),a
dec hl
inc de
djnz mvloop
ret
DEFC ASMDISP_zx_setfloat_CALLEE = asmentry - zx_setfloat_callee
|
; A291506: a(n) = (n!)^8 * Sum_{i=1..n} 1/i^8.
; Submitted by Jon Maiga
; 0,1,257,1686433,110523752704,43173450975314176,72514862031522895036416,418033821374598847702425993216,7013444132843374500928464765799366656,301905779820559925981495987360836056017534976,30190578282735799739825404733506718906135347200000000,6471618607498128365036645493788914801138902020338483200000000,2782677551162542251042707355408185797339558389979597260403507200000000,2269915567891712644078442866450663138131769432588415726207450639184691200000000
mov $2,1
lpb $0
mov $1,$0
sub $0,1
pow $1,8
mul $3,$1
add $3,$2
mul $2,$1
lpe
mov $0,$3
|
; A066335: Binary string which equals n when 1's and 2's bits have negative weights.
; Submitted by Jon Maiga
; 0,111,110,101,100,1011,1010,1001,1000,1111,1110,1101,1100,10011,10010,10001,10000,10111,10110,10101,10100,11011,11010,11001,11000,11111,11110,11101,11100,100011,100010,100001,100000,100111,100110,100101
seq $0,120634 ; Decimal equivalent of A066335.
seq $0,7088 ; The binary numbers (or binary words, or binary vectors, or binary expansion of n): numbers written in base 2.
|
#include <algorithm>
#include <sstream>
#include "CSE.h"
#include "CodeGen_Internal.h"
#include "CodeGen_OpenCL_Dev.h"
#include "Debug.h"
#include "EliminateBoolVectors.h"
#include "EmulateFloat16Math.h"
#include "ExprUsesVar.h"
#include "IRMutator.h"
#include "IROperator.h"
#include "Simplify.h"
namespace Halide {
namespace Internal {
using std::ostringstream;
using std::sort;
using std::string;
using std::vector;
CodeGen_OpenCL_Dev::CodeGen_OpenCL_Dev(Target t)
: clc(src_stream, t) {
}
string CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::print_type(Type type, AppendSpaceIfNeeded space) {
ostringstream oss;
if (type.is_float()) {
if (type.bits() == 16) {
user_assert(target.has_feature(Target::CLHalf))
<< "OpenCL kernel uses half type, but CLHalf target flag not enabled\n";
oss << "half";
} else if (type.bits() == 32) {
oss << "float";
} else if (type.bits() == 64) {
oss << "double";
} else {
user_error << "Can't represent a float with this many bits in OpenCL C: " << type << "\n";
}
} else {
if (type.is_uint() && type.bits() > 1) oss << 'u';
switch (type.bits()) {
case 1:
internal_assert(type.lanes() == 1) << "Encountered vector of bool\n";
oss << "bool";
break;
case 8:
oss << "char";
break;
case 16:
oss << "short";
break;
case 32:
oss << "int";
break;
case 64:
oss << "long";
break;
default:
user_error << "Can't represent an integer with this many bits in OpenCL C: " << type << "\n";
}
}
if (type.lanes() != 1) {
switch (type.lanes()) {
case 2:
case 3:
case 4:
case 8:
case 16:
oss << type.lanes();
break;
default:
user_error << "Unsupported vector width in OpenCL C: " << type << "\n";
}
}
if (space == AppendSpace) {
oss << ' ';
}
return oss.str();
}
// These are built-in types in OpenCL
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::add_vector_typedefs(const std::set<Type> &vector_types) {
}
string CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::print_reinterpret(Type type, Expr e) {
ostringstream oss;
oss << "as_" << print_type(type) << "(" << print_expr(e) << ")";
return oss.str();
}
namespace {
string simt_intrinsic(const string &name) {
if (ends_with(name, ".__thread_id_x")) {
return "get_local_id(0)";
} else if (ends_with(name, ".__thread_id_y")) {
return "get_local_id(1)";
} else if (ends_with(name, ".__thread_id_z")) {
return "get_local_id(2)";
} else if (ends_with(name, ".__thread_id_w")) {
return "get_local_id(3)";
} else if (ends_with(name, ".__block_id_x")) {
return "get_group_id(0)";
} else if (ends_with(name, ".__block_id_y")) {
return "get_group_id(1)";
} else if (ends_with(name, ".__block_id_z")) {
return "get_group_id(2)";
} else if (ends_with(name, ".__block_id_w")) {
return "get_group_id(3)";
}
internal_error << "simt_intrinsic called on bad variable name: " << name << "\n";
return "";
}
} // namespace
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const For *loop) {
if (is_gpu_var(loop->name)) {
internal_assert((loop->for_type == ForType::GPUBlock) ||
(loop->for_type == ForType::GPUThread))
<< "kernel loop must be either gpu block or gpu thread\n";
internal_assert(is_zero(loop->min));
stream << get_indent() << print_type(Int(32)) << " " << print_name(loop->name)
<< " = " << simt_intrinsic(loop->name) << ";\n";
loop->body.accept(this);
} else {
user_assert(loop->for_type != ForType::Parallel) << "Cannot use parallel loops inside OpenCL kernel\n";
CodeGen_C::visit(loop);
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Ramp *op) {
string id_base = print_expr(op->base);
string id_stride = print_expr(op->stride);
ostringstream rhs;
rhs << id_base << " + " << id_stride << " * ("
<< print_type(op->type.with_lanes(op->lanes)) << ")(0";
// Note 0 written above.
for (int i = 1; i < op->lanes; ++i) {
rhs << ", " << i;
}
rhs << ")";
print_assignment(op->type.with_lanes(op->lanes), rhs.str());
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Broadcast *op) {
string id_value = print_expr(op->value);
print_assignment(op->type.with_lanes(op->lanes), id_value);
}
namespace {
// Mapping of integer vector indices to OpenCL ".s" syntax.
const char *vector_elements = "0123456789ABCDEF";
} // namespace
string CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::get_memory_space(const string &buf) {
return "__address_space_" + print_name(buf);
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Call *op) {
if (op->is_intrinsic(Call::bool_to_mask)) {
if (op->args[0].type().is_vector()) {
// The argument is already a mask of the right width. Just
// sign-extend to the expected type.
op->args[0].accept(this);
} else {
// The argument is a scalar bool. Casting it to an int
// produces zero or one. Convert it to -1 of the requested
// type.
Expr equiv = -Cast::make(op->type, op->args[0]);
equiv.accept(this);
}
} else if (op->is_intrinsic(Call::cast_mask)) {
// Sign-extension is fine
Expr equiv = Cast::make(op->type, op->args[0]);
equiv.accept(this);
} else if (op->is_intrinsic(Call::select_mask)) {
internal_assert(op->args.size() == 3);
string cond = print_expr(op->args[0]);
string true_val = print_expr(op->args[1]);
string false_val = print_expr(op->args[2]);
// Yes, you read this right. OpenCL's select function is declared
// 'select(false_case, true_case, condition)'.
ostringstream rhs;
rhs << "select(" << false_val << ", " << true_val << ", " << cond << ")";
print_assignment(op->type, rhs.str());
} else if (op->is_intrinsic(Call::abs)) {
if (op->type.is_float()) {
ostringstream rhs;
rhs << "abs_f" << op->type.bits() << "(" << print_expr(op->args[0]) << ")";
print_assignment(op->type, rhs.str());
} else {
ostringstream rhs;
rhs << "abs(" << print_expr(op->args[0]) << ")";
print_assignment(op->type, rhs.str());
}
} else if (op->is_intrinsic(Call::absd)) {
ostringstream rhs;
rhs << "abs_diff(" << print_expr(op->args[0]) << ", " << print_expr(op->args[1]) << ")";
print_assignment(op->type, rhs.str());
} else if (op->is_intrinsic(Call::gpu_thread_barrier)) {
stream << get_indent() << "barrier(CLK_LOCAL_MEM_FENCE);\n";
print_assignment(op->type, "0");
} else if (op->is_intrinsic(Call::shift_left) || op->is_intrinsic(Call::shift_right)) {
// Some OpenCL implementations forbid mixing signed-and-unsigned shift values;
// if the RHS is uint, quietly cast it back to int if the LHS is int
if (op->args[0].type().is_int() && op->args[1].type().is_uint()) {
Type t = op->args[0].type().with_code(halide_type_int);
Expr e = Call::make(op->type, op->name, {op->args[0], cast(t, op->args[1])}, op->call_type);
e.accept(this);
} else {
CodeGen_C::visit(op);
}
} else {
CodeGen_C::visit(op);
}
}
string CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::print_extern_call(const Call *op) {
internal_assert(!function_takes_user_context(op->name));
vector<string> args(op->args.size());
for (size_t i = 0; i < op->args.size(); i++) {
args[i] = print_expr(op->args[i]);
}
ostringstream rhs;
rhs << op->name << "(" << with_commas(args) << ")";
return rhs.str();
}
string CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::print_array_access(const string &name,
const Type &type,
const string &id_index) {
ostringstream rhs;
bool type_cast_needed = !(allocations.contains(name) &&
allocations.get(name).type == type);
if (type_cast_needed) {
rhs << "((" << get_memory_space(name) << " "
<< print_type(type) << " *)"
<< print_name(name)
<< ")";
} else {
rhs << print_name(name);
}
rhs << "[" << id_index << "]";
return rhs.str();
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Load *op) {
user_assert(is_one(op->predicate)) << "Predicated load is not supported inside OpenCL kernel.\n";
// If we're loading a contiguous ramp into a vector, use vload instead.
Expr ramp_base = strided_ramp_base(op->index);
if (ramp_base.defined()) {
internal_assert(op->type.is_vector());
ostringstream rhs;
if ((op->alignment.modulus % op->type.lanes() == 0) &&
(op->alignment.remainder % op->type.lanes() == 0)) {
// Get the rhs just for the cache.
string id_ramp_base = print_expr(ramp_base / op->type.lanes());
string array_indexing = print_array_access(op->name, op->type, id_ramp_base);
rhs << array_indexing;
} else {
string id_ramp_base = print_expr(ramp_base);
rhs << "vload" << op->type.lanes()
<< "(0, (" << get_memory_space(op->name) << " "
<< print_type(op->type.element_of()) << "*)"
<< print_name(op->name) << " + " << id_ramp_base << ")";
}
print_assignment(op->type, rhs.str());
return;
}
string id_index = print_expr(op->index);
// Get the rhs just for the cache.
string array_indexing = print_array_access(op->name, op->type, id_index);
std::map<string, string>::iterator cached = cache.find(array_indexing);
if (cached != cache.end()) {
id = cached->second;
return;
}
if (op->index.type().is_vector()) {
// If index is a vector, gather vector elements.
internal_assert(op->type.is_vector());
id = "_" + unique_name('V');
cache[array_indexing] = id;
stream << get_indent() << print_type(op->type)
<< " " << id << ";\n";
for (int i = 0; i < op->type.lanes(); ++i) {
stream << get_indent();
stream
<< id << ".s" << vector_elements[i]
<< " = ((" << get_memory_space(op->name) << " "
<< print_type(op->type.element_of()) << "*)"
<< print_name(op->name) << ")"
<< "[" << id_index << ".s" << vector_elements[i] << "];\n";
}
} else {
print_assignment(op->type, array_indexing);
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Store *op) {
user_assert(is_one(op->predicate)) << "Predicated store is not supported inside OpenCL kernel.\n";
if (emit_atomic_stores) {
// Currently only support scalar atomics.
user_assert(op->value.type().is_scalar()) << "OpenCL atomic store does not support vectorization.\n";
user_assert(op->value.type().bits() >= 32) << "OpenCL only support 32 and 64 bit atomics.\n";
if (op->value.type().bits() == 64) {
user_assert(target.has_feature(Target::CLAtomics64))
<< "Enable feature CLAtomics64 for 64-bit atomics in OpenCL.\n";
}
// Detect whether we can describe this as an atomic-read-modify-write,
// otherwise fallback to a compare-and-swap loop.
// Current only test for atomic add.
Expr val_expr = op->value;
Type t = val_expr.type();
Expr equiv_load = Load::make(t, op->name, op->index, Buffer<>(), op->param, op->predicate, op->alignment);
Expr delta = simplify(common_subexpression_elimination(op->value - equiv_load));
// For atomicAdd, we check if op->value - store[index] is independent of store.
// The atomicAdd operations in OpenCL only supports integers so we also check that.
bool is_atomic_add = t.is_int_or_uint() && !expr_uses_var(delta, op->name);
bool type_cast_needed = !(allocations.contains(op->name) &&
allocations.get(op->name).type == t);
auto print_store_var = [&]() {
if (type_cast_needed) {
stream << "(("
<< get_memory_space(op->name) << " "
<< print_type(t)
<< " *)"
<< print_name(op->name)
<< ")";
} else {
stream << print_name(op->name);
}
};
if (is_atomic_add) {
string id_index = print_expr(op->index);
string id_delta = print_expr(delta);
stream << get_indent();
// atomic_add(&x[i], delta);
if (t.bits() == 32) {
stream << "atomic_add(&";
} else {
stream << "atom_add(&";
}
print_store_var();
stream << "[" << id_index << "]";
stream << "," << id_delta << ");\n";
} else {
// CmpXchg loop
// {
// union {unsigned int i; float f;} old_val;
// union {unsigned int i; float f;} new_val;
// do {
// old_val.f = x[id_index];
// new_val.f = ...
// } while(atomic_cmpxchg((volatile address_space unsigned int*)&x[id_index], old_val.i, new_val.i) != old_val.i);
// }
stream << get_indent() << "{\n";
indent += 2;
string id_index = print_expr(op->index);
std::string int_type = t.bits() == 32 ? "int" : "long";
if (t.is_float() || t.is_uint()) {
int_type = "unsigned " + int_type;
}
if (t.is_float()) {
stream << get_indent() << "union {" << int_type << " i; " << print_type(t) << " f;} old_val;\n";
stream << get_indent() << "union {" << int_type << " i; " << print_type(t) << " f;} new_val;\n";
} else {
stream << get_indent() << int_type << " old_val;\n";
stream << get_indent() << int_type << " new_val;\n";
}
stream << get_indent() << "do {\n";
indent += 2;
stream << get_indent();
if (t.is_float()) {
stream << "old_val.f = ";
} else {
stream << "old_val = ";
}
print_store_var();
stream << "[" << id_index << "];\n";
string id_value = print_expr(op->value);
stream << get_indent();
if (t.is_float()) {
stream << "new_val.f = ";
} else {
stream << "new_val = ";
}
stream << id_value << ";\n";
indent -= 2;
std::string old_val = t.is_float() ? "old_val.i" : "old_val";
std::string new_val = t.is_float() ? "new_val.i" : "new_val";
stream << get_indent()
<< "} while(atomic_cmpxchg((volatile "
<< get_memory_space(op->name) << " " << int_type << "*)&"
<< print_name(op->name) << "[" << id_index << "], "
<< old_val << ", " << new_val << ") != " << old_val << ");\n"
<< get_indent() << "}\n";
indent -= 2;
}
cache.clear();
return;
}
string id_value = print_expr(op->value);
Type t = op->value.type();
// If we're writing a contiguous ramp, use vstore instead.
Expr ramp_base = strided_ramp_base(op->index);
if (ramp_base.defined()) {
internal_assert(op->value.type().is_vector());
if ((op->alignment.modulus % op->value.type().lanes() == 0) &&
(op->alignment.remainder % op->value.type().lanes() == 0)) {
string id_ramp_base = print_expr(ramp_base / op->value.type().lanes());
string array_indexing = print_array_access(op->name, t, id_ramp_base);
stream << get_indent() << array_indexing << " = " << id_value << ";\n";
} else {
string id_ramp_base = print_expr(ramp_base);
stream << get_indent() << "vstore" << t.lanes() << "("
<< id_value << ","
<< 0 << ", (" << get_memory_space(op->name) << " "
<< print_type(t.element_of()) << "*)"
<< print_name(op->name) << " + " << id_ramp_base
<< ");\n";
}
} else if (op->index.type().is_vector()) {
// If index is a vector, scatter vector elements.
internal_assert(t.is_vector());
string id_index = print_expr(op->index);
for (int i = 0; i < t.lanes(); ++i) {
stream << get_indent() << "((" << get_memory_space(op->name) << " "
<< print_type(t.element_of()) << " *)"
<< print_name(op->name)
<< ")["
<< id_index << ".s" << vector_elements[i] << "] = "
<< id_value << ".s" << vector_elements[i] << ";\n";
}
} else {
string id_index = print_expr(op->index);
stream << get_indent();
std::string array_indexing = print_array_access(op->name, t, id_index);
stream << array_indexing << " = " << id_value << ";\n";
}
cache.clear();
}
namespace {
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const EQ *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, "==");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const NE *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, "!=");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const LT *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, "<");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const LE *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, "<=");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const GT *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, ">");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const GE *op) {
visit_binop(eliminated_bool_type(op->type, op->a.type()), op->a, op->b, ">=");
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Cast *op) {
if (!target.has_feature(Target::CLHalf) &&
((op->type.is_float() && op->type.bits() < 32) ||
(op->value.type().is_float() && op->value.type().bits() < 32))) {
Expr equiv = lower_float16_cast(op);
equiv.accept(this);
return;
}
if (op->type.is_vector()) {
print_assignment(op->type, "convert_" + print_type(op->type) + "(" + print_expr(op->value) + ")");
} else {
CodeGen_C::visit(op);
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Select *op) {
if (!op->condition.type().is_scalar()) {
// A vector of bool was recursively introduced while
// performing codegen. Eliminate it.
Expr equiv = eliminate_bool_vectors(op);
equiv.accept(this);
return;
}
CodeGen_C::visit(op);
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Allocate *op) {
user_assert(!op->new_expr.defined()) << "Allocate node inside OpenCL kernel has custom new expression.\n"
<< "(Memoization is not supported inside GPU kernels at present.)\n";
if (op->name == "__shared") {
// Already handled
op->body.accept(this);
} else {
open_scope();
debug(2) << "Allocate " << op->name << " on device\n";
debug(3) << "Pushing allocation called " << op->name << " onto the symbol table\n";
// Allocation is not a shared memory allocation, just make a local declaration.
// It must have a constant size.
int32_t size = op->constant_allocation_size();
user_assert(size > 0)
<< "Allocation " << op->name << " has a dynamic size. "
<< "Only fixed-size allocations are supported on the gpu. "
<< "Try storing into shared memory instead.";
stream << get_indent() << print_type(op->type) << ' '
<< print_name(op->name) << "[" << size << "];\n";
stream << get_indent() << "#define " << get_memory_space(op->name) << " __private\n";
Allocation alloc;
alloc.type = op->type;
allocations.push(op->name, alloc);
op->body.accept(this);
// Should have been freed internally
internal_assert(!allocations.contains(op->name));
close_scope("alloc " + print_name(op->name));
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Free *op) {
if (op->name == "__shared") {
return;
} else {
// Should have been freed internally
internal_assert(allocations.contains(op->name));
allocations.pop(op->name);
stream << get_indent() << "#undef " << get_memory_space(op->name) << "\n";
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const AssertStmt *op) {
user_warning << "Ignoring assertion inside OpenCL kernel: " << op->condition << "\n";
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Shuffle *op) {
if (op->is_interleave()) {
int op_lanes = op->type.lanes();
internal_assert(!op->vectors.empty());
int arg_lanes = op->vectors[0].type().lanes();
if (op->vectors.size() == 1) {
// 1 argument, just do a simple assignment
internal_assert(op_lanes == arg_lanes);
print_assignment(op->type, print_expr(op->vectors[0]));
} else if (op->vectors.size() == 2) {
// 2 arguments, set the .even to the first arg and the
// .odd to the second arg
internal_assert(op->vectors[1].type().lanes() == arg_lanes);
internal_assert(op_lanes / 2 == arg_lanes);
string a1 = print_expr(op->vectors[0]);
string a2 = print_expr(op->vectors[1]);
id = unique_name('_');
stream << get_indent() << print_type(op->type) << " " << id << ";\n";
stream << get_indent() << id << ".even = " << a1 << ";\n";
stream << get_indent() << id << ".odd = " << a2 << ";\n";
} else {
// 3+ arguments, interleave via a vector literal
// selecting the appropriate elements of the vectors
int dest_lanes = op->type.lanes();
internal_assert(dest_lanes <= 16);
int num_vectors = op->vectors.size();
vector<string> arg_exprs(num_vectors);
for (int i = 0; i < num_vectors; i++) {
internal_assert(op->vectors[i].type().lanes() == arg_lanes);
arg_exprs[i] = print_expr(op->vectors[i]);
}
internal_assert(num_vectors * arg_lanes >= dest_lanes);
id = unique_name('_');
stream << get_indent() << print_type(op->type) << " " << id;
stream << " = (" << print_type(op->type) << ")(";
for (int i = 0; i < dest_lanes; i++) {
int arg = i % num_vectors;
int arg_idx = i / num_vectors;
internal_assert(arg_idx <= arg_lanes);
stream << arg_exprs[arg] << ".s" << vector_elements[arg_idx];
if (i != dest_lanes - 1) {
stream << ", ";
}
}
stream << ");\n";
}
} else {
internal_error << "Shuffle not implemented.\n";
}
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Max *op) {
print_expr(Call::make(op->type, "max", {op->a, op->b}, Call::Extern));
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Min *op) {
print_expr(Call::make(op->type, "min", {op->a, op->b}, Call::Extern));
}
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::visit(const Atomic *op) {
// Most GPUs require all the threads in a warp to perform the same operations,
// which means our mutex will lead to deadlock.
user_assert(op->mutex_name.empty())
<< "The atomic update requires a mutex lock, which is not supported in OpenCL.\n";
// Issue atomic stores.
ScopedValue<bool> old_emit_atomic_stores(emit_atomic_stores, true);
IRVisitor::visit(op);
}
void CodeGen_OpenCL_Dev::add_kernel(Stmt s,
const string &name,
const vector<DeviceArgument> &args) {
debug(2) << "CodeGen_OpenCL_Dev::compile " << name << "\n";
// TODO: do we have to uniquify these names, or can we trust that they are safe?
cur_kernel_name = name;
clc.add_kernel(s, name, args);
}
namespace {
struct BufferSize {
string name;
size_t size;
BufferSize()
: size(0) {
}
BufferSize(string name, size_t size)
: name(name), size(size) {
}
bool operator<(const BufferSize &r) const {
return size < r.size;
}
};
} // namespace
void CodeGen_OpenCL_Dev::CodeGen_OpenCL_C::add_kernel(Stmt s,
const string &name,
const vector<DeviceArgument> &args) {
debug(2) << "Adding OpenCL kernel " << name << "\n";
debug(2) << "Eliminating bool vectors\n";
s = eliminate_bool_vectors(s);
debug(2) << "After eliminating bool vectors:\n"
<< s << "\n";
// Figure out which arguments should be passed in __constant.
// Such arguments should be:
// - not written to,
// - loads are block-uniform,
// - constant size,
// - and all allocations together should be less than the max constant
// buffer size given by CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE.
// The last condition is handled via the preprocessor in the kernel
// declaration.
vector<BufferSize> constants;
for (size_t i = 0; i < args.size(); i++) {
if (args[i].is_buffer &&
CodeGen_GPU_Dev::is_buffer_constant(s, args[i].name) &&
args[i].size > 0) {
constants.push_back(BufferSize(args[i].name, args[i].size));
}
}
// Sort the constant candidates from smallest to largest. This will put
// as many of the constant allocations in __constant as possible.
// Ideally, we would prioritize constant buffers by how frequently they
// are accessed.
sort(constants.begin(), constants.end());
// Compute the cumulative sum of the constants.
for (size_t i = 1; i < constants.size(); i++) {
constants[i].size += constants[i - 1].size;
}
// Create preprocessor replacements for the address spaces of all our buffers.
stream << "// Address spaces for " << name << "\n";
for (size_t i = 0; i < args.size(); i++) {
if (args[i].is_buffer) {
vector<BufferSize>::iterator constant = constants.begin();
while (constant != constants.end() &&
constant->name != args[i].name) {
constant++;
}
if (constant != constants.end()) {
stream << "#if " << constant->size << " <= MAX_CONSTANT_BUFFER_SIZE && "
<< constant - constants.begin() << " < MAX_CONSTANT_ARGS\n";
stream << "#define " << get_memory_space(args[i].name) << " __constant\n";
stream << "#else\n";
stream << "#define " << get_memory_space(args[i].name) << " __global\n";
stream << "#endif\n";
} else {
stream << "#define " << get_memory_space(args[i].name) << " __global\n";
}
}
}
// Emit the function prototype.
stream << "__kernel void " << name << "(\n";
for (size_t i = 0; i < args.size(); i++) {
if (args[i].is_buffer) {
stream << " " << get_memory_space(args[i].name) << " ";
if (!args[i].write) stream << "const ";
stream << print_type(args[i].type) << " *"
<< "restrict "
<< print_name(args[i].name);
Allocation alloc;
alloc.type = args[i].type;
allocations.push(args[i].name, alloc);
} else {
Type t = args[i].type;
string name = args[i].name;
// Bools are passed as a uint8.
t = t.with_bits(t.bytes() * 8);
// float16 are passed as uints
if (t.is_float() && t.bits() < 32) {
t = t.with_code(halide_type_uint);
name += "_bits";
}
stream << " const "
<< print_type(t)
<< " "
<< print_name(name);
}
if (i < args.size() - 1) stream << ",\n";
}
stream << ",\n"
<< " __address_space___shared int16* __shared";
stream << ")\n";
open_scope();
// Reinterpret half args passed as uint16 back to half
for (size_t i = 0; i < args.size(); i++) {
if (!args[i].is_buffer &&
args[i].type.is_float() &&
args[i].type.bits() < 32) {
stream << " const " << print_type(args[i].type)
<< " " << print_name(args[i].name)
<< " = half_from_bits(" << print_name(args[i].name + "_bits") << ");\n";
}
}
print(s);
close_scope("kernel " + name);
for (size_t i = 0; i < args.size(); i++) {
// Remove buffer arguments from allocation scope
if (args[i].is_buffer) {
allocations.pop(args[i].name);
}
}
// Undef all the buffer address spaces, in case they're different in another kernel.
for (size_t i = 0; i < args.size(); i++) {
if (args[i].is_buffer) {
stream << "#undef " << get_memory_space(args[i].name) << "\n";
}
}
}
void CodeGen_OpenCL_Dev::init_module() {
debug(2) << "OpenCL device codegen init_module\n";
// wipe the internal kernel source
src_stream.str("");
src_stream.clear();
const Target &target = clc.get_target();
// This identifies the program as OpenCL C (as opposed to SPIR).
src_stream << "/*OpenCL C " << target.to_string() << "*/\n";
src_stream << "#pragma OPENCL FP_CONTRACT ON\n";
// Write out the Halide math functions.
src_stream << "inline float float_from_bits(unsigned int x) {return as_float(x);}\n"
<< "inline float nan_f32() { return NAN; }\n"
<< "inline float neg_inf_f32() { return -INFINITY; }\n"
<< "inline float inf_f32() { return INFINITY; }\n"
<< "inline bool is_nan_f32(float x) {return isnan(x); }\n"
<< "inline bool is_inf_f32(float x) {return isinf(x); }\n"
<< "inline bool is_finite_f32(float x) {return isfinite(x); }\n"
<< "#define sqrt_f32 sqrt \n"
<< "#define sin_f32 sin \n"
<< "#define cos_f32 cos \n"
<< "#define exp_f32 exp \n"
<< "#define log_f32 log \n"
<< "#define abs_f32 fabs \n"
<< "#define floor_f32 floor \n"
<< "#define ceil_f32 ceil \n"
<< "#define round_f32 round \n"
<< "#define trunc_f32 trunc \n"
<< "#define pow_f32 pow\n"
<< "#define asin_f32 asin \n"
<< "#define acos_f32 acos \n"
<< "#define tan_f32 tan \n"
<< "#define atan_f32 atan \n"
<< "#define atan2_f32 atan2\n"
<< "#define sinh_f32 sinh \n"
<< "#define asinh_f32 asinh \n"
<< "#define cosh_f32 cosh \n"
<< "#define acosh_f32 acosh \n"
<< "#define tanh_f32 tanh \n"
<< "#define atanh_f32 atanh \n"
<< "#define fast_inverse_f32 native_recip \n"
<< "#define fast_inverse_sqrt_f32 native_rsqrt \n";
// __shared always has address space __local.
src_stream << "#define __address_space___shared __local\n";
if (target.has_feature(Target::CLDoubles)) {
src_stream << "#pragma OPENCL EXTENSION cl_khr_fp64 : enable\n"
<< "inline bool is_nan_f64(double x) {return isnan(x); }\n"
<< "inline bool is_inf_f64(double x) {return isinf(x); }\n"
<< "inline bool is_finite_f64(double x) {return isfinite(x); }\n"
<< "#define sqrt_f64 sqrt\n"
<< "#define sin_f64 sin\n"
<< "#define cos_f64 cos\n"
<< "#define exp_f64 exp\n"
<< "#define log_f64 log\n"
<< "#define abs_f64 fabs\n"
<< "#define floor_f64 floor\n"
<< "#define ceil_f64 ceil\n"
<< "#define round_f64 round\n"
<< "#define trunc_f64 trunc\n"
<< "#define pow_f64 pow\n"
<< "#define asin_f64 asin\n"
<< "#define acos_f64 acos\n"
<< "#define tan_f64 tan\n"
<< "#define atan_f64 atan\n"
<< "#define atan2_f64 atan2\n"
<< "#define sinh_f64 sinh\n"
<< "#define asinh_f64 asinh\n"
<< "#define cosh_f64 cosh\n"
<< "#define acosh_f64 acosh\n"
<< "#define tanh_f64 tanh\n"
<< "#define atanh_f64 atanh\n";
}
if (target.has_feature(Target::CLHalf)) {
src_stream << "#pragma OPENCL EXTENSION cl_khr_fp16 : enable\n"
<< "inline half half_from_bits(unsigned short x) {return __builtin_astype(x, half);}\n"
<< "inline half nan_f16() { return half_from_bits(32767); }\n"
<< "inline half neg_inf_f16() { return half_from_bits(31744); }\n"
<< "inline half inf_f16() { return half_from_bits(64512); }\n"
<< "inline bool is_nan_f16(half x) {return isnan(x); }\n"
<< "inline bool is_inf_f16(half x) {return isinf(x); }\n"
<< "inline bool is_finite_f16(half x) {return isfinite(x); }\n"
<< "#define sqrt_f16 sqrt\n"
<< "#define sin_f16 sin\n"
<< "#define cos_f16 cos\n"
<< "#define exp_f16 exp\n"
<< "#define log_f16 log\n"
<< "#define abs_f16 fabs\n"
<< "#define floor_f16 floor\n"
<< "#define ceil_f16 ceil\n"
<< "#define round_f16 round\n"
<< "#define trunc_f16 trunc\n"
<< "#define pow_f16 pow\n"
<< "#define asin_f16 asin\n"
<< "#define acos_f16 acos\n"
<< "#define tan_f16 tan\n"
<< "#define atan_f16 atan\n"
<< "#define atan2_f16 atan2\n"
<< "#define sinh_f16 sinh\n"
<< "#define asinh_f16 asinh\n"
<< "#define cosh_f16 cosh\n"
<< "#define acosh_f16 acosh\n"
<< "#define tanh_f16 tanh\n"
<< "#define atanh_f16 atanh\n";
}
if (target.has_feature(Target::CLAtomics64)) {
src_stream << "#pragma OPENCL EXTENSION cl_khr_int64_base_atomics : enable\n";
src_stream << "#pragma OPENCL EXTENSION cl_khr_int64_extended_atomics : enable\n";
}
src_stream << '\n';
clc.add_common_macros(src_stream);
// Add at least one kernel to avoid errors on some implementations for functions
// without any GPU schedules.
src_stream << "__kernel void _at_least_one_kernel(int x) { }\n";
cur_kernel_name = "";
}
vector<char> CodeGen_OpenCL_Dev::compile_to_src() {
string str = src_stream.str();
debug(1) << "OpenCL kernel:\n"
<< str << "\n";
vector<char> buffer(str.begin(), str.end());
buffer.push_back(0);
return buffer;
}
string CodeGen_OpenCL_Dev::get_current_kernel_name() {
return cur_kernel_name;
}
void CodeGen_OpenCL_Dev::dump() {
std::cerr << src_stream.str() << std::endl;
}
std::string CodeGen_OpenCL_Dev::print_gpu_name(const std::string &name) {
return name;
}
} // namespace Internal
} // namespace Halide
|
; A101265: a(1) = 1, a(2) = 2, a(3) = 6; a(n) = 5*a(n-1) - 5*a(n-2) + a(n-3) for n>3.
; 1,2,6,21,77,286,1066,3977,14841,55386,206702,771421,2878981,10744502,40099026,149651601,558507377,2084377906,7779004246,29031639077,108347552061,404358569166,1509086724602,5631988329241,21018866592361,78443478040202,292755045568446,1092576704233581,4077551771365877,15217630381229926,56792969753553826,211954248632985377,791024024778387681,2952141850480565346,11017543377143873702,41118031658094929461,153454583255235844141,572700301362848447102,2137346622196157944266,7976686187421783329961
mov $1,1
lpb $0
sub $0,1
add $2,$1
add $1,$2
add $2,$1
sub $2,1
lpe
mov $0,$1
|
<%
from pwnlib.shellcraft.aarch64.linux import syscall
%>
<%page args="file, buf"/>
<%docstring>
Invokes the syscall stat. See 'man 2 stat' for more information.
Arguments:
file(char): file
buf(stat): buf
</%docstring>
${syscall('SYS_stat', file, buf)}
|
//////////////////////////////////////////////////////////////////////
//
// Crytek Source code
// Copyright (c) Crytek 2001-2004
//
// File: XNetwork.cpp
// Description: Network stuffs implementation.
//
// History:
// - August 6, 2001: Created by Alberto Demichelis
// - February 2005: Modified by Marco Corbetta for SDK release
//
//////////////////////////////////////////////////////////////////////////
#include "stdafx.h"
#include "XNetwork.h"
#include "Game.h"
//////////////////////////////////////////////////////////////////////////
// SXServerInfos implementation.
//////////////////////////////////////////////////////////////////////////
SXServerInfos::SXServerInfos()
{
strName = "@UnknownServer";
strMap = "@UnknownMap";
strGameType = "@UnknownGameType";
strMod = "@UnknownMod";
nPlayers = 0;
nMaxPlayers = 0;
nPort = DEFAULT_SERVERPORT;
nPing = 0;
nComputerType = 0;
nServerFlags = 0;
}
//////////////////////////////////////////////////////////////////////////
bool SXServerInfos::Read(const string &szInfoString)
{
if (szInfoString.empty() || szInfoString[0] != 'S')
{
return false;
}
const char *pBuf = szInfoString.c_str()+1; // skip the 'S'
// extract the port
nPort = *((int *)pBuf); pBuf+=4;
nComputerType = *pBuf++;
VersionInfo.Set(pBuf); pBuf += strlen(pBuf)+1;
strName = pBuf; pBuf += strName.size()+1;
strMod = pBuf; pBuf += strMod.size()+1;
strGameType = pBuf; pBuf += strGameType.size()+1;
strMap = pBuf; pBuf += strMap.size()+1;
nPlayers = *pBuf++;
nMaxPlayers = *pBuf++;
nServerFlags = 0;
if (*pBuf++)
nServerFlags |= SXServerInfos::FLAG_PASSWORD;
if (*pBuf++)
nServerFlags |= SXServerInfos::FLAG_CHEATS;
if (*pBuf++)
nServerFlags |= SXServerInfos::FLAG_NET;
if (*pBuf++)
nServerFlags |= SXServerInfos::FLAG_PUNKBUSTER;
return true;
}
//////////////////////////////////////////////////////////////////////////
// SXGameContext implementation.
//////////////////////////////////////////////////////////////////////////
SXGameContext::SXGameContext()
{
strMapFolder = "NoMapCtx"; // <<FIXME>> Use a better name for the final version...
bForceNonDevMode=false;
ucServerInfoVersion=SERVERINFO_FORMAT_VERSION;
bInternetServer=false;
// HI:CPUType
#ifdef AMD64
nComputerType=1; // AMD64
#else
nComputerType=0; // IntelCompatible
#endif
nComputerType<<=4;
// LO:OSType
#ifdef LIMUX
nComputerType|=1; // Linux
#else
nComputerType|=0; // Windows
#endif
}
//////////////////////////////////////////////////////////////////////////
const char *SXGameContext::GetCPUTarget() const
{
switch(nComputerType>>4)
{
case 0: return "IntelCompatible";
case 1: return "AMD64";
}
return 0;
}
//////////////////////////////////////////////////////////////////////////
const char *SXGameContext::GetOSTarget() const
{
switch(nComputerType&0xf)
{
case 0: return "Windows";
case 1: return "Linux";
}
return 0;
}
//////////////////////////////////////////////////////////////////////////
bool SXGameContext::Write(CStream &stm)
{
if(!stm.Write(ucServerInfoVersion))
return false;
if(!stm.Write(strMapFolder))
return false;
if(!stm.Write(strMod))
return false;
if(!stm.Write(strGameType))
return false;
if(!stm.Write((unsigned int)dwNetworkVersion))
return false;
if(!stm.Write(strMission))
return false;
if(!stm.Write(wLevelDataCheckSum))
return false;
if(!stm.Write(bForceNonDevMode))
return false;
if(!stm.Write(bInternetServer))
return false;
if(!stm.Write(nComputerType))
return false;
return true;
}
//////////////////////////////////////////////////////////////////////////
bool SXGameContext::IsVersionOk() const
{
return dwNetworkVersion==NETWORK_FORMAT_VERSION && ucServerInfoVersion==(unsigned char)SERVERINFO_FORMAT_VERSION;
}
//////////////////////////////////////////////////////////////////////////
bool SXGameContext::Read(CStream &stm)
{
if(!stm.Read(ucServerInfoVersion))
return false;
if(!stm.Read(strMapFolder))
return false;
if(!stm.Read(strMod))
return false;
if(!stm.Read(strGameType))
return false;
if(!stm.Read((unsigned int&)dwNetworkVersion))
return false;
if(!stm.Read(strMission))
return false;
if(!stm.Read(wLevelDataCheckSum))
return false;
if(!stm.Read(bForceNonDevMode))
return false;
if(!stm.Read(bInternetServer))
return false;
if(!stm.Read(nComputerType))
return false;
return true;
}
|
; A166466: Trisection a(n) = A000265(3n).
; 3,3,9,3,15,9,21,3,27,15,33,9,39,21,45,3,51,27,57,15,63,33,69,9,75,39,81,21,87,45,93,3,99,51,105,27,111,57,117,15,123,63,129,33,135,69,141,9,147,75,153,39,159,81,165,21,171,87,177,45,183,93,189,3,195,99,201,51
add $0,1
mov $1,$0
mul $1,3
mov $2,64
gcd $2,$1
div $1,$2
|
;
; Copyright (C) 2008-2020 Advanced Micro Devices, Inc. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
; are permitted provided that the following conditions are met:
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
;
; vrsapowxf.asm
;
; An array implementation of the powf libm function.
; This routine raises the x array to a constant y power.
;
; Prototype:
;
; void vrsa_powxf(int n, float *x, float y, float *z);
;
; Places the results into the supplied z array.
; Does not perform error handling, but does return C99 values for error
; inputs. Denormal results are truncated to 0.
;
;
CONST SEGMENT
__mask_sign DQ 08000000080000000h ; a sign bit mask
dq 08000000080000000h
__mask_nsign DQ 07FFFFFFF7FFFFFFFh ; a not sign bit mask
dq 07FFFFFFF7FFFFFFFh
; used by inty
__mask_127 DQ 00000007F0000007Fh ; EXPBIAS_SP32
dq 00000007F0000007Fh
__mask_mant DQ 0007FFFFF007FFFFFh ; mantissa bit mask
dq 0007FFFFF007FFFFFh
__mask_1 DQ 00000000100000001h ; 1
dq 00000000100000001h
__mask_2 DQ 00000000200000002h ; 2
dq 00000000200000002h
__mask_24 DQ 00000001800000018h ; 24
dq 00000001800000018h
__mask_23 DQ 00000001700000017h ; 23
dq 00000001700000017h
; used by special case checking
__float_one DQ 03f8000003f800000h ; one
dq 03f8000003f800000h
__mask_inf DQ 07f8000007F800000h ; inifinity
dq 07f8000007F800000h
__mask_ninf DQ 0ff800000fF800000h ; -inifinity
dq 0ff800000fF800000h
__mask_NaN DQ 07fC000007FC00000h ; NaN
dq 07fC000007FC00000h
__mask_sigbit DQ 00040000000400000h ; QNaN bit
dq 00040000000400000h
__mask_impbit DQ 00080000000800000h ; implicit bit
dq 00080000000800000h
__mask_ly DQ 04f0000004f000000h ; large y
dq 04f0000004f000000h
CONST ENDS
; define local variable storage offsets
p_temp equ 00h ; xmmword
p_negateres equ 10h ; qword
p_xexp equ 20h ; qword
save_rbx equ 030h ;qword
save_rsi equ 038h ;qword
save_rdi equ 040h ;qword
p_y equ 048h ; y value
p_ax equ 050h ; absolute x
p_sx equ 060h ; sign of x's
p_ay equ 070h ; absolute y
p_yexp equ 080h ; unbiased exponent of y
p_inty equ 090h ; integer y indicator
p_xptr equ 0a0h ; ptr to x values
p_zptr equ 0b0h ; ptr to z values
p_nv equ 0b8h ;qword
p_iter equ 0c0h ; qword storage for number of loop iterations
p2_temp equ 0d0h ;qword
p2_temp1 equ 0f0h ;qword
stack_size equ 0118h ; allocate 40h more than
; we need to avoid bank conflicts
EXTRN __amd_internal_vrd4_exp:NEAR
EXTRN __amd_internal_vrd4_log:NEAR
include fm.inc
FN_PROTOTYPE vrsa_powxf
TEXT SEGMENT page 'CODE'
; parameters are passed in by Microsoft C as:
; ecx - int n
; rdx - float *x
; xmm2 - float y, r8 - float * y
; r9 - float *z
PUBLIC fname
fname proc frame
sub rsp,stack_size
.ALLOCSTACK stack_size
; movd edx,xmm0 ; edx is ux
mov QWORD PTR [rsp+save_rbx],rbx ; save rbx
.SAVEREG rbx, save_rbx
mov QWORD PTR [rsp+save_rsi],rsi ; save rsi
.SAVEREG rsi, save_rsi
mov QWORD PTR [rsp+save_rdi],rdi ; save rdi
.SAVEREG rdi, save_rdi
.ENDPROLOG
movss DWORD PTR p_y[rsp],xmm2 ; save y
mov QWORD PTR p_xptr[rsp],rdx ; save pointer to x
mov QWORD PTR p_zptr[rsp],r9 ; save pointer to z
xor rax,rax
cmp rcx,0 ; just return if count is zero
jz __final_check
mov eax,ecx
mov rcx,rax
mov QWORD PTR [rsp+p_nv],rcx ; save number of values
;
; classify y
; vector 32 bit integer method
; /* See whether y is an integer.
; inty = 0 means not an integer.
; inty = 1 means odd integer.
; inty = 2 means even integer.
; */
; movdqa xmm4,XMMWORD PTR [rdx]
; get yexp
mov r8d,DWORD PTR p_y[rsp] ; r8 is uy
mov r9d,07fffffffh
and r9d,r8d ; r9 is ay
; if |y| == 0 then return 1
cmp r9d,0 ; is y a zero?
jz y_zero
mov eax,07f800000h ; EXPBITS_SP32
and eax,r9d ; y exp
xor edi,edi
shr eax,23 ;>> EXPSHIFTBITS_SP32
sub eax,126 ; - EXPBIAS_SP32 + 1 - eax is now the unbiased exponent
mov ebx,1
cmp eax,ebx ; if (yexp < 1)
cmovl ebx,edi
jl save_inty
mov ecx,24
cmp eax,ecx ; if (yexp >24)
jle @F
mov ebx,2
jmp save_inty
@@: ; else 1<=yexp<=24
sub ecx,eax ; build mask for mantissa
shl ebx,cl
dec ebx ; rbx = mask = (1 << (24 - yexp)) - 1
mov eax,r8d
and eax,ebx ; if ((uy & mask) != 0)
cmovnz ebx,edi ; inty = 0;
jnz save_inty
not ebx ; else if (((uy & ~mask) >> (24 - yexp)) & 0x00000001)
mov eax,r8d
and eax,ebx
shr eax,cl
inc edi
and eax,edi
mov ebx,edi ; inty = 1
jnz save_inty
inc ebx ; else inty = 2
save_inty:
mov DWORD PTR p_y[rsp+4],r8d ; save an extra copy of y
mov DWORD PTR p_inty[rsp],ebx ; save inty
mov rax,QWORD PTR [rsp+p_nv] ; get number of values
mov rcx,rax
; see if too few values to call the main loop
shr rax,2 ; get number of iterations
jz __vsa_cleanup ; jump if only single calls
; prepare the iteration counts
mov QWORD PTR [rsp+p_iter],rax ; save number of iterations
shl rax,2
sub rcx,rax ; compute number of extra single calls
mov QWORD PTR [rsp+p_nv],rcx ; save number of left over values
; process the array 4 values at a time.
__vsa_top:
; build the input _m128
; first get x
mov rsi,QWORD PTR [rsp+p_xptr] ; get x_array pointer
movups xmm0,XMMWORD PTR [rsi]
prefetch QWORD PTR [rsi+64]
movaps xmm2,xmm0
andps xmm0,XMMWORD PTR __mask_nsign ; get abs x
andps xmm2,XMMWORD PTR __mask_sign ; mask for the sign bits
movaps XMMWORD PTR p_ax[rsp],xmm0 ; save them
movaps XMMWORD PTR p_sx[rsp],xmm2 ; save them
; convert all four x's to double
cvtps2pd xmm0,QWORD PTR p_ax[rsp]
cvtps2pd xmm1,QWORD PTR p_ax+8[rsp]
;
; do x special case checking
;
; movdqa xmm5,xmm4
; pcmpeqd xmm5,xmm3 ; is y not an integer? ff's if so
; pand xmm5,XMMWORD PTR __mask_NaN ; these values will be NaNs, if x<0
pxor xmm3,xmm3
xor eax,eax
mov ecx,07FC00000h
cmp ebx,0 ; is y not an integer?
cmovz eax,ecx ; then set to return a NaN. else 0.
mov ecx,080000000h
cmp ebx,1 ; is y an odd integer?
cmovz eax,ecx ; maybe set sign bit if so
movd xmm5,eax
pshufd xmm5,xmm5,0
; shufps xmm5,xmm5,0
; movdqa xmm2,xmm4
; pcmpeqd xmm2,XMMWORD PTR __mask_1 ; is it odd? ff's if so
; pand xmm2,XMMWORD PTR __mask_sign ; these values might get their sign bit set
; por xmm5,xmm2
; cmpps xmm3,XMMWORD PTR p_sx[rsp],0 ; if the signs are set
pcmpeqd xmm3,XMMWORD PTR p_sx[rsp] ; if the signs are set
pandn xmm3,xmm5 ; then negateres gets the values as shown below
movdqa XMMWORD PTR p_negateres[rsp],xmm3 ; save negateres
; /* p_negateres now means the following.
; 7FC00000 means x<0, y not an integer, return NaN.
; 80000000 means x<0, y is odd integer, so set the sign bit.
; 0 means even integer, and/or x>=0.
; */
; **** Here starts the main calculations ****
; The algorithm used is x**y = exp(y*log(x))
; Extra precision is required in intermediate steps to meet the 1ulp requirement
;
; log(x) calculation
call __amd_internal_vrd4_log ; get the double precision log value
; for all four x's
; y* logx
cvtps2pd xmm2,QWORD PTR p_y[rsp] ;convert the two packed single y's to double
; /* just multiply by y */
mulpd xmm0,xmm2
mulpd xmm1,xmm2
; /* The following code computes r = exp(w) */
call __amd_internal_vrd4_exp ; get the double exp value
; for all four y*log(x)'s
;
; convert all four results to double
cvtpd2ps xmm0,xmm0
cvtpd2ps xmm1,xmm1
movlhps xmm0,xmm1
; perform special case and error checking on input values
; special case checking is done first in the scalar version since
; it allows for early fast returns. But for vectors, we consider them
; to be rare, so early returns are not necessary. So we first compute
; the x**y values, and then check for special cases.
; we do some of the checking in reverse order of the scalar version.
; apply the negate result flags
orps xmm0,XMMWORD PTR p_negateres[rsp] ; get negateres
; if y is infinite or so large that the result would overflow or underflow
mov edx,DWORD PTR p_y[rsp] ; get y
and edx,07fffffffh ; develop ay
; mov eax,04f000000h
cmp edx,04f000000h
ja y_large
rnsx3:
; if x is infinite
movdqa xmm4,XMMWORD PTR p_ax[rsp]
cmpps xmm4,XMMWORD PTR __mask_inf,0 ; equal to infinity, ffs if so.
movmskps edx,xmm4
test edx,0fh
jnz x_infinite
rnsx1:
; if x is zero
xorps xmm4,xmm4
cmpps xmm4,XMMWORD PTR p_ax[rsp],0 ; equal to zero, ffs if so.
movmskps edx,xmm4
test edx,0fh
jnz x_zero
rnsx2:
; if y is NAN
movss xmm4,DWORD PTR p_y[rsp] ; get y
ucomiss xmm4,xmm4 ; comparing y to itself should
; be true, unless y is a NaN. parity flag if NaN.
jp y_NaN
rnsx4:
; if x is NAN
movdqa xmm4,XMMWORD PTR p_ax[rsp] ; get x
cmpps xmm4,xmm4,4 ; a compare not equal of x to itself should
; be false, unless x is a NaN. ff's if NaN.
movmskps ecx,xmm4
test ecx,0fh
jnz x_NaN
rnsx5:
; if x == +1, return +1 for all x
movdqa xmm3,XMMWORD PTR __float_one ; one
mov rdx,QWORD PTR p_xptr[rsp] ; get pointer to x
movdqa xmm2,xmm3
movdqu xmm5,XMMWORD PTR [rdx]
cmpps xmm2,xmm5,4 ; not equal to +1.0?, ffs if not equal.
andps xmm0,xmm2 ; keep the others
andnps xmm2,xmm3 ; mask for ones
orps xmm0,xmm2
__vsa_bottom:
; update the x and y pointers
add rsi,16
mov QWORD PTR [rsp+p_xptr],rsi ; save x_array pointer
; store the result _m128d
mov rdi,QWORD PTR [rsp+p_zptr] ; get z_array pointer
movups XMMWORD PTR [rdi],xmm0
; prefetchw QWORD PTR [rdi+64]
prefetch QWORD PTR [rdi+64]
add rdi,16
mov QWORD PTR [rsp+p_zptr],rdi ; save z_array pointer
mov rax,QWORD PTR [rsp+p_iter] ; get number of iterations
sub rax,1
mov QWORD PTR [rsp+p_iter],rax ; save number of iterations
jnz __vsa_top
; see if we need to do any extras
mov rax,QWORD PTR [rsp+p_nv] ; get number of values
test rax,rax
jnz __vsa_cleanup
__final_check:
mov rbx,[rsp+save_rbx] ; restore rbx
mov rsi,[rsp+save_rsi] ; restore rsi
mov rdi,[rsp+save_rdi] ; restore rdi
add rsp,stack_size
ret
align 16
; we jump here when we have an odd number of calls to make at the
; end
__vsa_cleanup:
mov rsi,QWORD PTR [rsp+p_xptr]
mov r8d,DWORD PTR p_y[rsp] ; r8 is uy
; fill in a m128 with zeroes and the extra values and then make a recursive call.
xorps xmm0,xmm0
xor rax,rax
movaps XMMWORD PTR p2_temp[rsp],xmm0
movaps XMMWORD PTR p2_temp+16[rsp],xmm0
mov rax,p_nv[rsp] ; get number of values
mov ecx,[rsi] ; we know there's at least one
mov p2_temp[rsp],ecx
mov p2_temp+16[rsp],r8d
cmp rax,2
jl __vsacg
mov ecx,4[rsi] ; do the second value
mov p2_temp+4[rsp],ecx
mov p2_temp+20[rsp],r8d
cmp rax,3
jl __vsacg
mov ecx,8[rsi] ; do the third value
mov p2_temp+8[rsp],ecx
mov p2_temp+24[rsp],r8d
__vsacg:
mov rcx,4 ; parameter for N
lea rdx,p2_temp[rsp] ; &x parameter
movaps xmm0,p2_temp+16[rsp] ; y parameter
lea r9,p2_temp1[rsp] ; &z parameter
call fname ; call recursively to compute four values
; now copy the results to the destination array
mov rdi,p_zptr[rsp]
mov rax,p_nv[rsp] ; get number of values
mov ecx,p2_temp1[rsp]
mov [rdi],ecx ; we know there's at least one
cmp rax,2
jl __vsacgf
mov ecx,p2_temp1+4[rsp]
mov 4[rdi],ecx ; do the second value
cmp rax,3
jl __vsacgf
mov ecx,p2_temp1+8[rsp]
mov 8[rdi],ecx ; do the third value
__vsacgf:
jmp __final_check
align 16
y_zero:
; if |y| == 0 then return 1
mov ecx,03f800000h ; one
; fill all results with a one
mov r9,QWORD PTR p_zptr[rsp] ; &z parameter
mov rax,QWORD PTR [rsp+p_nv] ; get number of values
__yzt:
mov DWORD PTR [r9], ecx ; store a 1
add r9,4
sub rax,1
test rax,rax
jnz __yzt
jmp __final_check
; /* y is a NaN.
y_NaN:
mov r8d,DWORD PTR p_y[rsp]
or r8d,000400000h ; convert to QNaNs
movd xmm0,r8d ; propagate to all results
shufps xmm0,xmm0,0
jmp rnsx4
; x is a NaN.
x_NaN:
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
movdqu xmm4,XMMWORD PTR [rcx] ; get x
movdqa xmm3,xmm4
movdqa xmm5,xmm4
movdqa xmm2,XMMWORD PTR __mask_sigbit ; get the signalling bits
cmpps xmm4,xmm4,0 ; a compare equal of x to itself should
; be true, unless x is a NaN. 0's if NaN.
cmpps xmm3,xmm3,4 ; compare not equal, ff's if NaN.
andps xmm0,xmm4 ; keep the other results
andps xmm2,xmm3 ; get just the right signalling bits
andps xmm3,xmm5 ; mask for the NaNs
orps xmm3,xmm2 ; convert to QNaNs
orps xmm0,xmm3 ; combine
jmp rnsx5
; /* y is infinite or so large that the result would
; overflow or underflow.
y_large:
movdqa XMMWORD PTR p_temp[rsp],xmm0
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov eax,DWORD PTR [rcx]
mov ebx,DWORD PTR p_y[rsp]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special6 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp[rsp],eax
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov eax,DWORD PTR 4[rcx]
mov ebx,DWORD PTR p_y[rsp]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special6 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+4[rsp],eax
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov eax,DWORD PTR 8[rcx]
mov ebx,DWORD PTR p_y[rsp]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special6 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+8[rsp],eax
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov eax,DWORD PTR 12[rcx]
mov ebx,DWORD PTR p_y[rsp]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special6 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+12[rsp],eax
movdqa xmm0,XMMWORD PTR p_temp[rsp]
jmp rnsx3
; a subroutine to treat an individual x,y pair when y is large or infinity
; assumes x in eax, y in ebx.
; returns result in eax
np_special6:
; handle |x|==1 cases first
mov r8d,07FFFFFFFh
and r8d,eax
cmp r8d,03f800000h ; jump if |x| !=1
jnz nps6
mov eax,03f800000h ; return 1 for all |x|==1
jmp npx64
; cases where |x| !=1
nps6:
mov ecx,07f800000h
xor eax,eax ; assume 0 return
test ebx,080000000h
jnz nps62 ; jump if y negative
; y = +inf
cmp r8d,03f800000h
cmovg eax,ecx ; return inf if |x| < 1
jmp npx64
nps62:
; y = -inf
cmp r8d,03f800000h
cmovl eax,ecx ; return inf if |x| < 1
jmp npx64
npx64:
ret
; handle cases where x is +/- infinity. edx is the mask
align 16
x_infinite:
movdqa XMMWORD PTR p_temp[rsp],xmm0
test edx,1
jz xinfa
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov eax,DWORD PTR [rcx]
mov ebx,DWORD PTR p_y[rsp]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x1 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp[rsp],eax
xinfa:
test edx,2
jz xinfb
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 4[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x1 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+4[rsp],eax
xinfb:
test edx,4
jz xinfc
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 8[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x1 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+8[rsp],eax
xinfc:
test edx,8
jz xinfd
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 12[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x1 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+12[rsp],eax
xinfd:
movdqa xmm0,XMMWORD PTR p_temp[rsp]
jmp rnsx1
; a subroutine to treat an individual x,y pair when x is +/-infinity
; assumes x in eax,y in ebx, inty in ecx.
; returns result in eax
np_special_x1: ; x is infinite
test eax,080000000h ; is x positive
jnz nsx11 ; jump if not
test ebx,080000000h ; is y positive
jz nsx13 ; just return if so
xor eax,eax ; else return 0
jmp nsx13
nsx11:
cmp ecx,1 ; if inty ==1
jnz nsx12 ; jump if not
test ebx,080000000h ; is y positive
jz nsx13 ; just return if so
mov eax,080000000h ; else return -0
jmp nsx13
nsx12: ; inty <>1
and eax,07FFFFFFFh ; return -x (|x|) if y<0
test ebx,080000000h ; is y positive
jz nsx13 ;
xor eax,eax ; return 0 if y >=0
nsx13:
ret
; handle cases where x is +/- zero. edx is the mask of x,y pairs with |x|=0
align 16
x_zero:
movdqa XMMWORD PTR p_temp[rsp],xmm0
test edx,1
jz xzera
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR [rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x2 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp[rsp],eax
xzera:
test edx,2
jz xzerb
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 4[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x2 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+4[rsp],eax
xzerb:
test edx,4
jz xzerc
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 8[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x2 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+8[rsp],eax
xzerc:
test edx,8
jz xzerd
mov rcx,QWORD PTR p_xptr[rsp] ; get pointer to x
mov ebx,DWORD PTR p_y[rsp]
mov eax,DWORD PTR 12[rcx]
mov ecx,DWORD PTR p_inty[rsp]
sub rsp,8
call np_special_x2 ; call the handler for one value
add rsp,8
mov DWORD PTR p_temp+12[rsp],eax
xzerd:
movdqa xmm0,XMMWORD PTR p_temp[rsp]
jmp rnsx2
; a subroutine to treat an individual x,y pair when x is +/-0
; assumes x in eax,y in ebx, inty in ecx.
; returns result in eax
align 16
np_special_x2:
cmp ecx,1 ; if inty ==1
jz nsx21 ; jump if so
; handle cases of x=+/-0, y not integer
xor eax,eax
mov ecx,07f800000h
test ebx,080000000h ; is ypos
cmovnz eax,ecx
jmp nsx23
; y is an integer
nsx21:
xor r8d,r8d
mov ecx,07f800000h
test ebx,080000000h ; is ypos
cmovnz r8d,ecx ; set to infinity if not
and eax,080000000h ; pickup the sign of x
or eax,r8d ; and include it in the result
nsx23:
ret
fname endp
TEXT ENDS
END
|
; #########################################################################
TextFind proc lpBuffer:DWORD, len:DWORD
LOCAL tp :DWORD
LOCAL tl :DWORD
LOCAL sch:DWORD
LOCAL ft :FINDTEXT
LOCAL Cr :CHARRANGE
invoke SendMessage,hRichEd,WM_GETTEXTLENGTH,0,0
mov tl, eax
invoke SendMessage,hRichEd,EM_EXGETSEL,0,ADDR Cr
inc Cr.cpMin ; inc starting pos by 1 so not searching
; same position repeatedly
m2m ft.chrg.cpMin, Cr.cpMin ; start pos
m2m ft.chrg.cpMax, tl ; end of text
m2m ft.lpstrText, lpBuffer ; string to search for
; 0 = case insensitive
; 2 = FT_WHOLEWORD
; 4 = FT_MATCHCASE
; 6 = FT_WHOLEWORD or FT_MATCHCASE
mov sch, 0
.if CaseFlag == 1
or sch, 4
.endif
.if WholeWord == 1
or sch, 2
.endif
invoke SendMessage,hRichEd,EM_FINDTEXT,sch,ADDR ft
mov tp, eax
.if tp == -1
invoke MessageBox,hWnd,ADDR nomatch,ADDR szDisplayName,MB_OK
ret
.endif
m2m Cr.cpMin,tp ; put start pos into structure
dec len ; dec length for zero terminator
mov eax, len
add tp,eax ; add length to character pos
m2m Cr.cpMax,tp ; put end pos into structure
; ------------------------------------
; set the selection to the search word
; ------------------------------------
invoke SendMessage,hRichEd,EM_EXSETSEL,0,ADDR Cr
ret
TextFind endp
; #########################################################################
|
; A081866: a(n)=sigma_9(2n-1).
; 1,19684,1953126,40353608,387440173,2357947692,10604499374,38445332184,118587876498,322687697780,794320419872,1801152661464,3814699218751,7625984925160,14507145975870,26439622160672,46413842369328,78815680978608,129961739795078,208738965677816,327381934393962,502592611936844,756719475330798,1119130473102768,1628413638264057,2334283760986632,3299763591802134,4605368943885192,6351784643101520,8662995818654940,11694146092834142,15634608864694184,20711923444343124,27206534396294948,35453888988257376
mul $0,2
seq $0,13957 ; sigma_9(n), the sum of the 9th powers of the divisors of n.
|
SFX_Cry1C_3_Ch5:
duty_cycle_pattern 3, 3, 1, 1
square_note 7, 13, 6, 2017
square_note 6, 12, 6, 2018
square_note 9, 13, 6, 2017
square_note 7, 12, 6, 2016
square_note 5, 11, 6, 2018
square_note 7, 12, 6, 2017
square_note 6, 11, 6, 2016
square_note 8, 10, 1, 2015
sound_ret
SFX_Cry1C_3_Ch6:
duty_cycle_pattern 1, 0, 1, 0
square_note 6, 12, 3, 1993
square_note 6, 11, 3, 1991
square_note 10, 12, 4, 1987
square_note 8, 11, 4, 1991
square_note 6, 12, 3, 1993
square_note 15, 10, 2, 1989
sound_ret
SFX_Cry1C_3_Ch8:
noise_note 13, 1, -1, 124
noise_note 13, 15, 7, 140
noise_note 12, 13, 6, 124
noise_note 8, 12, 4, 108
noise_note 15, 11, 3, 92
sound_ret
|
db 0 ; species ID placeholder
db 80, 92, 65, 68, 65, 80
; hp atk def spd sat sdf
db WATER, WATER ; type
db 60 ; catch rate
db 170 ; base exp
db NO_ITEM, NO_ITEM ; items
db GENDER_F50 ; gender ratio
db 20 ; step cycles to hatch
INCBIN "gfx/pokemon/seaking/front.dimensions"
db GROWTH_MEDIUM_FAST ; growth rate
dn EGG_WATER_2, EGG_WATER_2 ; egg groups
db 70 ; happiness
; tm/hm learnset
tmhm WATER_PULSE, TOXIC, HAIL, HIDDEN_POWER, ICE_BEAM, BLIZZARD, HYPER_BEAM, PROTECT, RAIN_DANCE, FRUSTRATION, RETURN, DOUBLE_TEAM, FACADE, SECRET_POWER, REST, ATTRACT, ENDURE, GIGA_IMPACT, CAPTIVATE, SLEEP_TALK, NATURAL_GIFT, POISON_JAB, SWAGGER, SUBSTITUTE, SURF, WATERFALL, AQUA_TAIL, BOUNCE, DIVE, FURY_CUTTER, ICY_WIND, KNOCK_OFF, MUD_SLAP, SNORE, SWIFT
; end
|
// Copyright (c) 2011-2017 The Bitcoin Core developers
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#if defined(HAVE_CONFIG_H)
#include <config/bitcoin-config.h>
#endif
#include <qt/addressbookpage.h>
#include <qt/forms/ui_addressbookpage.h>
#include <qt/addresstablemodel.h>
#include <qt/bitcoingui.h>
#include <qt/csvmodelwriter.h>
#include <qt/editaddressdialog.h>
#include <qt/guiutil.h>
#include <qt/platformstyle.h>
#include <QIcon>
#include <QMenu>
#include <QMessageBox>
#include <QSortFilterProxyModel>
AddressBookPage::AddressBookPage(const PlatformStyle *platformStyle, Mode _mode, Tabs _tab, QWidget *parent) :
QDialog(parent),
ui(new Ui::AddressBookPage),
model(0),
mode(_mode),
tab(_tab)
{
ui->setupUi(this);
if (!platformStyle->getImagesOnButtons()) {
ui->newAddress->setIcon(QIcon());
ui->copyAddress->setIcon(QIcon());
ui->deleteAddress->setIcon(QIcon());
ui->exportButton->setIcon(QIcon());
} else {
ui->newAddress->setIcon(platformStyle->SingleColorIcon(":/icons/add"));
ui->copyAddress->setIcon(platformStyle->SingleColorIcon(":/icons/editcopy"));
ui->deleteAddress->setIcon(platformStyle->SingleColorIcon(":/icons/remove"));
ui->exportButton->setIcon(platformStyle->SingleColorIcon(":/icons/export"));
}
switch(mode)
{
case ForSelection:
switch(tab)
{
case SendingTab: setWindowTitle(tr("Choose the address to send coins to")); break;
case ReceivingTab: setWindowTitle(tr("Choose the address to receive coins with")); break;
}
connect(ui->tableView, SIGNAL(doubleClicked(QModelIndex)), this, SLOT(accept()));
ui->tableView->setEditTriggers(QAbstractItemView::NoEditTriggers);
ui->tableView->setFocus();
ui->closeButton->setText(tr("C&hoose"));
ui->exportButton->hide();
break;
case ForEditing:
switch(tab)
{
case SendingTab: setWindowTitle(tr("Sending addresses")); break;
case ReceivingTab: setWindowTitle(tr("Receiving addresses")); break;
}
break;
}
switch(tab)
{
case SendingTab:
ui->labelExplanation->setText(tr("These are your Sugarchain addresses for sending payments. Always check the amount and the receiving address before sending coins."));
ui->deleteAddress->setVisible(true);
break;
case ReceivingTab:
ui->labelExplanation->setText(tr("These are your Sugarchain addresses for receiving payments. It is recommended to use a new receiving address for each transaction."));
ui->deleteAddress->setVisible(false);
break;
}
// Context menu actions
QAction *copyAddressAction = new QAction(tr("&Copy Address"), this);
QAction *copyLabelAction = new QAction(tr("Copy &Label"), this);
QAction *editAction = new QAction(tr("&Edit"), this);
deleteAction = new QAction(ui->deleteAddress->text(), this);
// Build context menu
contextMenu = new QMenu(this);
contextMenu->addAction(copyAddressAction);
contextMenu->addAction(copyLabelAction);
contextMenu->addAction(editAction);
if(tab == SendingTab)
contextMenu->addAction(deleteAction);
contextMenu->addSeparator();
// Connect signals for context menu actions
connect(copyAddressAction, SIGNAL(triggered()), this, SLOT(on_copyAddress_clicked()));
connect(copyLabelAction, SIGNAL(triggered()), this, SLOT(onCopyLabelAction()));
connect(editAction, SIGNAL(triggered()), this, SLOT(onEditAction()));
connect(deleteAction, SIGNAL(triggered()), this, SLOT(on_deleteAddress_clicked()));
connect(ui->tableView, SIGNAL(customContextMenuRequested(QPoint)), this, SLOT(contextualMenu(QPoint)));
connect(ui->closeButton, SIGNAL(clicked()), this, SLOT(accept()));
}
AddressBookPage::~AddressBookPage()
{
delete ui;
}
void AddressBookPage::setModel(AddressTableModel *_model)
{
this->model = _model;
if(!_model)
return;
proxyModel = new QSortFilterProxyModel(this);
proxyModel->setSourceModel(_model);
proxyModel->setDynamicSortFilter(true);
proxyModel->setSortCaseSensitivity(Qt::CaseInsensitive);
proxyModel->setFilterCaseSensitivity(Qt::CaseInsensitive);
switch(tab)
{
case ReceivingTab:
// Receive filter
proxyModel->setFilterRole(AddressTableModel::TypeRole);
proxyModel->setFilterFixedString(AddressTableModel::Receive);
break;
case SendingTab:
// Send filter
proxyModel->setFilterRole(AddressTableModel::TypeRole);
proxyModel->setFilterFixedString(AddressTableModel::Send);
break;
}
ui->tableView->setModel(proxyModel);
ui->tableView->sortByColumn(0, Qt::AscendingOrder);
// Set column widths
#if QT_VERSION < 0x050000
ui->tableView->horizontalHeader()->setResizeMode(AddressTableModel::Label, QHeaderView::Stretch);
ui->tableView->horizontalHeader()->setResizeMode(AddressTableModel::Address, QHeaderView::ResizeToContents);
#else
ui->tableView->horizontalHeader()->setSectionResizeMode(AddressTableModel::Label, QHeaderView::Stretch);
ui->tableView->horizontalHeader()->setSectionResizeMode(AddressTableModel::Address, QHeaderView::ResizeToContents);
#endif
connect(ui->tableView->selectionModel(), SIGNAL(selectionChanged(QItemSelection,QItemSelection)),
this, SLOT(selectionChanged()));
// Select row for newly created address
connect(_model, SIGNAL(rowsInserted(QModelIndex,int,int)), this, SLOT(selectNewAddress(QModelIndex,int,int)));
selectionChanged();
}
void AddressBookPage::on_copyAddress_clicked()
{
GUIUtil::copyEntryData(ui->tableView, AddressTableModel::Address);
}
void AddressBookPage::onCopyLabelAction()
{
GUIUtil::copyEntryData(ui->tableView, AddressTableModel::Label);
}
void AddressBookPage::onEditAction()
{
if(!model)
return;
if(!ui->tableView->selectionModel())
return;
QModelIndexList indexes = ui->tableView->selectionModel()->selectedRows();
if(indexes.isEmpty())
return;
EditAddressDialog dlg(
tab == SendingTab ?
EditAddressDialog::EditSendingAddress :
EditAddressDialog::EditReceivingAddress, this);
dlg.setModel(model);
QModelIndex origIndex = proxyModel->mapToSource(indexes.at(0));
dlg.loadRow(origIndex.row());
dlg.exec();
}
void AddressBookPage::on_newAddress_clicked()
{
if(!model)
return;
EditAddressDialog dlg(
tab == SendingTab ?
EditAddressDialog::NewSendingAddress :
EditAddressDialog::NewReceivingAddress, this);
dlg.setModel(model);
if(dlg.exec())
{
newAddressToSelect = dlg.getAddress();
}
}
void AddressBookPage::on_deleteAddress_clicked()
{
QTableView *table = ui->tableView;
if(!table->selectionModel())
return;
QModelIndexList indexes = table->selectionModel()->selectedRows();
if(!indexes.isEmpty())
{
table->model()->removeRow(indexes.at(0).row());
}
}
void AddressBookPage::selectionChanged()
{
// Set button states based on selected tab and selection
QTableView *table = ui->tableView;
if(!table->selectionModel())
return;
if(table->selectionModel()->hasSelection())
{
switch(tab)
{
case SendingTab:
// In sending tab, allow deletion of selection
ui->deleteAddress->setEnabled(true);
ui->deleteAddress->setVisible(true);
deleteAction->setEnabled(true);
break;
case ReceivingTab:
// Deleting receiving addresses, however, is not allowed
ui->deleteAddress->setEnabled(false);
ui->deleteAddress->setVisible(false);
deleteAction->setEnabled(false);
break;
}
ui->copyAddress->setEnabled(true);
}
else
{
ui->deleteAddress->setEnabled(false);
ui->copyAddress->setEnabled(false);
}
}
void AddressBookPage::done(int retval)
{
QTableView *table = ui->tableView;
if(!table->selectionModel() || !table->model())
return;
// Figure out which address was selected, and return it
QModelIndexList indexes = table->selectionModel()->selectedRows(AddressTableModel::Address);
for (const QModelIndex& index : indexes) {
QVariant address = table->model()->data(index);
returnValue = address.toString();
}
if(returnValue.isEmpty())
{
// If no address entry selected, return rejected
retval = Rejected;
}
QDialog::done(retval);
}
void AddressBookPage::on_exportButton_clicked()
{
// CSV is currently the only supported format
QString filename = GUIUtil::getSaveFileName(this,
tr("Export Address List"), QString(),
tr("Comma separated file (*.csv)"), nullptr);
if (filename.isNull())
return;
CSVModelWriter writer(filename);
// name, column, role
writer.setModel(proxyModel);
writer.addColumn("Label", AddressTableModel::Label, Qt::EditRole);
writer.addColumn("Address", AddressTableModel::Address, Qt::EditRole);
if(!writer.write()) {
QMessageBox::critical(this, tr("Exporting Failed"),
tr("There was an error trying to save the address list to %1. Please try again.").arg(filename));
}
}
void AddressBookPage::contextualMenu(const QPoint &point)
{
QModelIndex index = ui->tableView->indexAt(point);
if(index.isValid())
{
contextMenu->exec(QCursor::pos());
}
}
void AddressBookPage::selectNewAddress(const QModelIndex &parent, int begin, int /*end*/)
{
QModelIndex idx = proxyModel->mapFromSource(model->index(begin, AddressTableModel::Address, parent));
if(idx.isValid() && (idx.data(Qt::EditRole).toString() == newAddressToSelect))
{
// Select row of newly created address, once
ui->tableView->setFocus();
ui->tableView->selectRow(idx.row());
newAddressToSelect.clear();
}
}
|
$CASE ON
;; Macro to add jump table elements
JP_FAR MACRO lbl
LD NB,#@DPAG(lbl)
JRL lbl
ENDM
;; Begin pokemon mini header
DEFSECT ".min_header", CODE AT 2100H
SECT ".min_header"
ASCII "MN"
JP_FAR __START
JP_FAR _prc_frame_copy_irq
JP_FAR _prc_render_irq
JP_FAR _timer_2h_underflow_irq
JP_FAR _timer_2l_underflow_irq
JP_FAR _timer_1h_underflow_irq
JP_FAR _timer_1l_underflow_irq
JP_FAR _timer_3h_underflow_irq
JP_FAR _timer_3_cmp_irq
JP_FAR _timer_32hz_irq
JP_FAR _timer_8hz_irq
JP_FAR _timer_2hz_irq
JP_FAR _timer_1hz_irq
JP_FAR _ir_rx_irq
JP_FAR _shake_irq
JP_FAR _key_power_irq
JP_FAR _key_right_irq
JP_FAR _key_left_irq
JP_FAR _key_down_irq
JP_FAR _key_up_irq
JP_FAR _key_c_irq
JP_FAR _key_b_irq
JP_FAR _key_a_irq
JP_FAR _unknown_irq
JP_FAR _unknown_irq
JP_FAR _unknown_irq
JP_FAR _cartridge_irq
ASCII "NINTENDO"
DEFSECT ".min_header_tail", CODE AT 21BCH
SECT ".min_header_tail"
ASCII "2P"
DB 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
;; Begin startup code
DEFSECT ".startup", CODE, SHORT
SECT ".startup"
__start_cpt:
__START:
;==========================================================================
;=================== system initialization ==============================
;==========================================================================
LD SP,#02000h ; stack pointer initialize
LD BR,#020h ; BR register initialize to I/O area
LD [BR:21h],#0Ch
LD [BR:25h],#080h
LD [BR:80h],#08h
LD [BR:81h],#08h
;LD [BR:81h],#09h
LD SC, #0h
LD [BR:27h],#0FFh
LD [BR:28h],#0FFh
LD [BR:29h],#0FFh
LD [BR:2Ah],#0FFh
CARL __copytable
CARL _main
CARL __exit
RETE
GLOBAL __start_cpt
GLOBAL __START
EXTERN (CODE) __copytable
EXTERN (CODE) _main
EXTERN (CODE) __exit
CALLS '_start_cpt', '_copytable'
CALLS '_start_cpt', 'main'
CALLS '_start_cpt', '_exit'
EXTERN _prc_frame_copy_irq
EXTERN _prc_render_irq
EXTERN _timer_2h_underflow_irq
EXTERN _timer_2l_underflow_irq
EXTERN _timer_1h_underflow_irq
EXTERN _timer_1l_underflow_irq
EXTERN _timer_3h_underflow_irq
EXTERN _timer_3_cmp_irq
EXTERN _timer_32hz_irq
EXTERN _timer_8hz_irq
EXTERN _timer_2hz_irq
EXTERN _timer_1hz_irq
EXTERN _ir_rx_irq
EXTERN _shake_irq
EXTERN _key_power_irq
EXTERN _key_right_irq
EXTERN _key_left_irq
EXTERN _key_down_irq
EXTERN _key_up_irq
EXTERN _key_c_irq
EXTERN _key_b_irq
EXTERN _key_a_irq
EXTERN _unknown_irq
EXTERN _cartridge_irq
END
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r8
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x16427, %rsi
lea addresses_A_ht+0x1a0ba, %rdi
nop
nop
nop
nop
add %rbp, %rbp
mov $99, %rcx
rep movsb
nop
nop
nop
nop
nop
add $50042, %r10
lea addresses_D_ht+0x5d9f, %r8
nop
nop
sub $15557, %r11
mov $0x6162636465666768, %rcx
movq %rcx, (%r8)
nop
nop
nop
nop
cmp %rsi, %rsi
lea addresses_D_ht+0x1de47, %rbp
and %rsi, %rsi
mov $0x6162636465666768, %r10
movq %r10, %xmm0
vmovups %ymm0, (%rbp)
nop
nop
nop
nop
cmp %rsi, %rsi
lea addresses_normal_ht+0x610f, %rsi
lea addresses_UC_ht+0x470f, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
and $40870, %r9
mov $36, %rcx
rep movsw
nop
nop
nop
xor %r8, %r8
lea addresses_UC_ht+0x11d0f, %rsi
lea addresses_A_ht+0xcaf, %rdi
add %r9, %r9
mov $81, %rcx
rep movsq
nop
nop
nop
cmp $22617, %r11
lea addresses_UC_ht+0x1c76d, %rsi
lea addresses_D_ht+0x1220f, %rdi
nop
cmp $45246, %rbp
mov $30, %rcx
rep movsb
nop
nop
add %rsi, %rsi
lea addresses_D_ht+0xd10f, %rsi
nop
cmp $28078, %r9
mov (%rsi), %bp
add $12322, %rsi
lea addresses_D_ht+0x686f, %rcx
nop
nop
nop
nop
add $42115, %rbp
mov (%rcx), %r11
sub %rsi, %rsi
lea addresses_UC_ht+0x157a3, %r11
nop
nop
nop
nop
and %r10, %r10
movb $0x61, (%r11)
nop
sub %rcx, %rcx
lea addresses_WT_ht+0xefbb, %r9
nop
nop
nop
sub %r8, %r8
movb $0x61, (%r9)
nop
xor %r9, %r9
lea addresses_A_ht+0x138d4, %rdi
nop
nop
nop
nop
nop
add $44031, %r11
movups (%rdi), %xmm4
vpextrq $1, %xmm4, %r8
nop
nop
nop
nop
nop
inc %rdi
lea addresses_D_ht+0x6d8f, %rcx
nop
nop
nop
nop
sub $35017, %rbp
vmovups (%rcx), %ymm5
vextracti128 $1, %ymm5, %xmm5
vpextrq $0, %xmm5, %r11
nop
nop
nop
and $63189, %rsi
lea addresses_D_ht+0xf10f, %rsi
clflush (%rsi)
nop
nop
nop
nop
nop
dec %r11
mov $0x6162636465666768, %r8
movq %r8, %xmm5
vmovups %ymm5, (%rsi)
xor %r10, %r10
lea addresses_normal_ht+0xd4fb, %rsi
lea addresses_UC_ht+0x18e4f, %rdi
nop
cmp %r8, %r8
mov $74, %rcx
rep movsq
nop
nop
nop
nop
cmp %rbp, %rbp
lea addresses_A_ht+0x510f, %rcx
nop
nop
nop
nop
nop
dec %r8
mov $0x6162636465666768, %rdi
movq %rdi, %xmm4
movups %xmm4, (%rcx)
nop
nop
nop
and $53290, %r9
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r8
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r13
push %r15
push %r8
push %rbx
push %rcx
// Store
lea addresses_WT+0x2ccf, %r10
nop
sub $20805, %r8
mov $0x5152535455565758, %r15
movq %r15, (%r10)
nop
nop
add $54024, %rcx
// Store
lea addresses_A+0x6faf, %rcx
nop
nop
nop
sub %r8, %r8
movb $0x51, (%rcx)
nop
nop
nop
and %r13, %r13
// Faulty Load
lea addresses_RW+0x610f, %r11
dec %rbx
mov (%r11), %ecx
lea oracles, %r8
and $0xff, %rcx
shlq $12, %rcx
mov (%r8,%rcx,1), %rcx
pop %rcx
pop %rbx
pop %r8
pop %r15
pop %r13
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'AVXalign': False, 'congruent': 0, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'AVXalign': False, 'congruent': 6, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A', 'AVXalign': False, 'congruent': 5, 'size': 1, 'same': False, 'NT': True}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_RW', 'AVXalign': False, 'congruent': 0, 'size': 4, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 0, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 3, 'size': 32, 'same': True, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 9, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 7, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 10, 'size': 2, 'same': True, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 1, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'AVXalign': False, 'congruent': 2, 'size': 1, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'AVXalign': False, 'congruent': 2, 'size': 1, 'same': True, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'AVXalign': False, 'congruent': 0, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 7, 'size': 32, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 11, 'size': 32, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 1, 'same': True}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 5, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A_ht', 'AVXalign': False, 'congruent': 11, 'size': 16, 'same': True, 'NT': False}}
{'32': 21829}
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
*/
|
SECTION code_fp_am9511
PUBLIC cam32_sdcc___sint2fs
EXTERN asm_am9511_float16
.cam32_sdcc___sint2fs
pop bc ;return
pop hl ;value
push hl
push bc
jp asm_am9511_float16
|
// Time: O(n)
// Space: O(k)
class Solution {
public:
vector<int> distinctNumbers(vector<int>& nums, int k) {
vector<int> result;
unordered_map<int, int> count;
for (int i = 0; i < size(nums); ++i) {
++count[nums[i]];
if (i >= k) {
if (--count[nums[i - k]] == 0) {
count.erase(nums[i - k]);
}
}
if (i + 1 >= k) {
result.emplace_back(size(count));
}
}
return result;
}
};
|
; A305397: Largest diameter of a lattice polygon.
; Submitted by Christian Krause
; 2,3,4,4,5,6,6,7,8,8,8,9,10,10,10,11,12
mov $2,$0
add $0,1
lpb $0
sub $0,1
mov $3,$2
sub $3,$0
sub $3,1
mov $4,0
mov $10,$3
sub $10,$0
mov $7,$10
mov $8,$10
mov $9,$0
lpb $7
mov $0,1
mov $5,$9
mod $5,2
mov $6,$8
mod $6,2
mul $5,$6
add $4,$5
div $8,2
mov $7,$8
add $7,$6
lpe
cmp $4,0
add $1,$4
lpe
mov $0,$1
add $0,1
|
.model small
public InitXMode320x240x256
public CloseXMode320x240x256
SC_INDEX equ 03c4h ; sequencer port
CRTC_INDEX equ 03d4h ; CRT controller port
MISC_OUTPUT equ 03c2h ; miscellaneous output register
MAP_MASK equ 02h ; index map mask registru
SCREEN_SEG equ 0a000h
; --- data for CRT controller which are diferent from mode 13 ---
.data
; !!! DANGER !!!
; data rewritten from IBM manual
; if changed monitor can be damaged
; !!! DANGER !!!
CRTParams label word ; label
dw 00d06h ; vertical total
dw 03e07h ; overflow - bit 8 of vertcal counts
dw 04109h ; cell height - 2 to double scan
dw 0ea10h ; vertical sync start
dw 0ac11h ; vertical sync and protect cr0-cr7
dw 0df12h ; vertical displayed
dw 00014h ; turn off dword mode
dw 0e715h ; vertical blank start
dw 00616h ; vertical blank end
dw 0e317h ; turn on byte mode
CRTPARAMS_LENGHT equ (($-CRTParams)/2) ; in bytes from here
.code
;------------------------------------------------------------------------------
;
; Mode - X 320 x 240 x 256
;
; Initialization routine: void InitXMode320x240x256( void );
;
;------------------------------------------------------------------------------
InitXMode320x240x256 proc near
push bp
push si
push di
mov ax, 13h
int 10h ; initializing mode 13 using BIOS
mov dx, SC_INDEX
mov ax, 0604h
out dx, ax ; chain4 mode forbidden
; I unchainded it => 4 pages
mov ax, 0100h
out dx, ax ; synchronnous reset when switching funct.
mov dx, MISC_OUTPUT
mov al, 0e3h
out dx, ax ; setting 28MHz pointly and 60hz rowly
mov dx, SC_INDEX
mov ax, 0300h
out dx, ax
mov dx, CRTC_INDEX ; reprogramming crtc controller
mov al, 11h ; vsync end reg obsahuje register zapisu
out dx, al ; ochranneho bitu
inc dx ; CRT controller data register
in al, dx ; ziskani aktualniho vsync end reg nastaveni
and al, 7fh ; zmena ochranneho bitu pro zapis
out dx, al ; crtc registers
dec dx ; crt controller index
cld
mov si, offset CRTParams ; label to crt parameter table
mov cx, CRTPARAMS_LENGHT ; lenght of table
CRT: lodsw ; loading from table and out to crt port
out dx, ax
loop CRT
; now clear video RAM ...
mov dx, SC_INDEX
mov ax, 0f02h
out dx, ax ; enable writing to all rows
mov ax, SCREEN_SEG
mov es, ax
sub di, di
sub ax, ax
mov cx, 8000h ; size of whole video RAM
rep stosw ; CLEAR whole video RAM
pop di
pop si
pop bp
ret
InitXMode320x240x256 endp
;------------------------------------------------------------------------------
;
; Mode - X 320 x 240 x 256
;
; void CloseXMode320x240x256( void ); == set text mode
;
;------------------------------------------------------------------------------
CloseXMode320x240x256 proc near
mov ax, 0003h
int 10h
CloseXMode320x240x256 endp
end
|
; A277636: Number of 3 X 3 matrices having all elements in {0,...,n} with determinant = permanent.
; 1,343,6859,50653,226981,753571,2048383,4826809,10218313,19902511,36264691,62570773,103161709,163667323,251239591,374805361,545338513,776151559,1083206683,1485446221,2005142581,2668267603,3504881359,4549540393,5841725401,7426288351
mov $1,1
mov $2,9
mov $5,$0
mov $6,$0
lpb $2
add $1,$5
sub $2,1
lpe
mov $3,$6
lpb $3
sub $3,1
add $4,$5
lpe
mov $2,36
mov $5,$4
lpb $2
add $1,$5
sub $2,1
lpe
mov $3,$6
mov $4,0
lpb $3
sub $3,1
add $4,$5
lpe
mov $2,81
mov $5,$4
lpb $2
add $1,$5
sub $2,1
lpe
mov $3,$6
mov $4,0
lpb $3
sub $3,1
add $4,$5
lpe
mov $2,108
mov $5,$4
lpb $2
add $1,$5
sub $2,1
lpe
mov $3,$6
mov $4,0
lpb $3
sub $3,1
add $4,$5
lpe
mov $2,81
mov $5,$4
lpb $2
add $1,$5
sub $2,1
lpe
mov $3,$6
mov $4,0
lpb $3
sub $3,1
add $4,$5
lpe
mov $2,27
mov $5,$4
lpb $2
add $1,$5
sub $2,1
lpe
|
/*******************************************************************************
* Filename : spi5fieldvalues.hpp
*
* Details : Enumerations related with SPI5 peripheral. This header file is
* auto-generated for STM32F411 device.
*
*
*******************************************************************************/
#if !defined(SPI5ENUMS_HPP)
#define SPI5ENUMS_HPP
#include "fieldvalue.hpp" //for FieldValues
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_BIDIMODE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_BIDIMODE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_BIDIMODE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_BIDIOE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_BIDIOE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_BIDIOE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_CRCEN_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_CRCEN_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_CRCEN_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_CRCNEXT_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_CRCNEXT_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_CRCNEXT_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_DFF_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_DFF_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_DFF_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_RXONLY_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_RXONLY_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_RXONLY_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_SSM_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_SSM_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_SSM_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_SSI_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_SSI_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_SSI_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_LSBFIRST_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_LSBFIRST_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_LSBFIRST_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_SPE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_SPE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_SPE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_BR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_BR_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_BR_Values, BaseType, 1U> ;
using Value2 = FieldValue<SPI5_CR1_BR_Values, BaseType, 2U> ;
using Value3 = FieldValue<SPI5_CR1_BR_Values, BaseType, 3U> ;
using Value4 = FieldValue<SPI5_CR1_BR_Values, BaseType, 4U> ;
using Value5 = FieldValue<SPI5_CR1_BR_Values, BaseType, 5U> ;
using Value6 = FieldValue<SPI5_CR1_BR_Values, BaseType, 6U> ;
using Value7 = FieldValue<SPI5_CR1_BR_Values, BaseType, 7U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_MSTR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_MSTR_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_MSTR_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_CPOL_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_CPOL_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_CPOL_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR1_CPHA_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR1_CPHA_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR1_CPHA_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_TXEIE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_TXEIE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_TXEIE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_RXNEIE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_RXNEIE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_RXNEIE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_ERRIE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_ERRIE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_ERRIE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_FRF_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_FRF_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_FRF_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_SSOE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_SSOE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_SSOE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_TXDMAEN_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_TXDMAEN_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_TXDMAEN_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CR2_RXDMAEN_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_CR2_RXDMAEN_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_CR2_RXDMAEN_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_TIFRFE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_TIFRFE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_TIFRFE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_BSY_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_BSY_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_BSY_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_OVR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_OVR_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_OVR_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_MODF_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_MODF_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_MODF_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_CRCERR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_CRCERR_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_CRCERR_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_UDR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_UDR_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_UDR_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_CHSIDE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_CHSIDE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_CHSIDE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_TXE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_TXE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_TXE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_SR_RXNE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_SR_RXNE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_SR_RXNE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_DR_DR_Values: public RegisterField<Reg, offset, size, AccessMode>
{
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_CRCPR_CRCPOLY_Values: public RegisterField<Reg, offset, size, AccessMode>
{
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_RXCRCR_RxCRC_Values: public RegisterField<Reg, offset, size, AccessMode>
{
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_TXCRCR_TxCRC_Values: public RegisterField<Reg, offset, size, AccessMode>
{
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_I2SMOD_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_I2SMOD_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_I2SMOD_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_I2SE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_I2SE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_I2SE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_I2SCFG_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_I2SCFG_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_I2SCFG_Values, BaseType, 1U> ;
using Value2 = FieldValue<SPI5_I2SCFGR_I2SCFG_Values, BaseType, 2U> ;
using Value3 = FieldValue<SPI5_I2SCFGR_I2SCFG_Values, BaseType, 3U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_PCMSYNC_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_PCMSYNC_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_PCMSYNC_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_I2SSTD_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_I2SSTD_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_I2SSTD_Values, BaseType, 1U> ;
using Value2 = FieldValue<SPI5_I2SCFGR_I2SSTD_Values, BaseType, 2U> ;
using Value3 = FieldValue<SPI5_I2SCFGR_I2SSTD_Values, BaseType, 3U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_CKPOL_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_CKPOL_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_CKPOL_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_DATLEN_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_DATLEN_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_DATLEN_Values, BaseType, 1U> ;
using Value2 = FieldValue<SPI5_I2SCFGR_DATLEN_Values, BaseType, 2U> ;
using Value3 = FieldValue<SPI5_I2SCFGR_DATLEN_Values, BaseType, 3U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SCFGR_CHLEN_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SCFGR_CHLEN_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SCFGR_CHLEN_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SPR_MCKOE_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SPR_MCKOE_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SPR_MCKOE_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SPR_ODD_Values: public RegisterField<Reg, offset, size, AccessMode>
{
using Value0 = FieldValue<SPI5_I2SPR_ODD_Values, BaseType, 0U> ;
using Value1 = FieldValue<SPI5_I2SPR_ODD_Values, BaseType, 1U> ;
} ;
template <typename Reg, size_t offset, size_t size, typename AccessMode, typename BaseType>
struct SPI5_I2SPR_I2SDIV_Values: public RegisterField<Reg, offset, size, AccessMode>
{
} ;
#endif //#if !defined(SPI5ENUMS_HPP)
|
; L1009.asm
; Generated 10.30.2000 by mlevel
; Modified 10.30.2000 by Abe Pralle
INCLUDE "Source/Defs.inc"
INCLUDE "Source/Levels.inc"
;---------------------------------------------------------------------
SECTION "Level1009Section",ROMX
;---------------------------------------------------------------------
L1009_Contents::
DW L1009_Load
DW L1009_Init
DW L1009_Check
DW L1009_Map
;---------------------------------------------------------------------
; Load
;---------------------------------------------------------------------
L1009_Load:
DW ((L1009_LoadFinished - L1009_Load2)) ;size
L1009_Load2:
call ParseMap
ret
L1009_LoadFinished:
;---------------------------------------------------------------------
; Map
;---------------------------------------------------------------------
L1009_Map:
INCBIN "Data/Levels/L1009_warzone.lvl"
;---------------------------------------------------------------------
; Init
;---------------------------------------------------------------------
L1009_Init:
DW ((L1009_InitFinished - L1009_Init2)) ;size
L1009_Init2:
ret
L1009_InitFinished:
;---------------------------------------------------------------------
; Check
;---------------------------------------------------------------------
L1009_Check:
DW ((L1009_CheckFinished - L1009_Check2)) ;size
L1009_Check2:
ret
L1009_CheckFinished:
PRINT "1009 Script Sizes (Load/Init/Check) (of $500): "
PRINT (L1009_LoadFinished - L1009_Load2)
PRINT " / "
PRINT (L1009_InitFinished - L1009_Init2)
PRINT " / "
PRINT (L1009_CheckFinished - L1009_Check2)
PRINT "\n"
|
; A010853: Constant sequence: a(n) = 14.
; 14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14
mov $1,14
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2018-2019, Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%define GCM256_MODE 1
;; single buffer implementation
%include "avx512/gcm_vaes_avx512.asm"
|
;
; ZX81 libraries
;
;--------------------------------------------------------------
; This code comes from the 'HRG_Tool'
; by Matthias Swatosch
; Original function name: "HRG_Tool_TXTcopy"
;--------------------------------------------------------------
;
; $Id: copytxt_arx.asm,v 1.5 2017/01/02 22:58:00 aralbrec Exp $
;
;----------------------------------------------------------------
;
; HRG_Tool_TXTcopy
; hl = pointer to display array
;
; copies the textscreen (DFILE) into HRG
;
;----------------------------------------------------------------
SECTION smc_clib
PUBLIC copytxt
PUBLIC copytxt
EXTERN base_graphics
copytxt:
_copytxt:
ld (ovmode),hl
ld hl,(base_graphics)
ld de,($400C) ; D_FILE
inc de
IF FORzx81hrg64
ld b,8
ELSE
ld b,24
ENDIF
ld c,0
HRG_TXTcopyLoop:
ld a,(de)
or a
jr z,HRG_TXTcopyNextChar
cp 118
jr z,HRG_TXTcopyNextLine
push hl ; HL points to byte in HRG
push de ; A is character
push bc
cp $40 ; inverse?
push af
ld de,$1e00 ; start of characters in ROM
ld b,0
and $3f
ld c,a
or a
rl c ; multiply BC by 8
rl b
rl c
rl b
rl c
rl b
ex de,hl
add hl,bc
ex de,hl ; now DE is pointer to pixel code
ld c,$00 ; C stores invers character information
pop af ; inverse?
jr c,HRG_TXTcopyNormal
dec c ; if inverse character then C is $ff
HRG_TXTcopyNormal:
ld b,8 ; counter
HRG_TXTcopyLoop2:
ld a,(de)
xor c
ovmode: nop
nop
;or (hl) ; plot the character to HRG
ld (hl),a
; push bc
; ld bc,32
; add hl,bc
; pop bc
inc hl
inc de
djnz HRG_TXTcopyLoop2
pop bc
pop de
pop hl
HRG_TXTcopyNextChar:
inc de
push bc
ld bc,8
add hl,bc
pop bc
;inc hl
jr HRG_TXTcopyLoop
HRG_TXTcopyNextLine:
inc c
inc de
ld hl,(base_graphics)
push bc
ld b,c
ld c,0
add hl,bc
pop bc
djnz HRG_TXTcopyLoop
ret
|
page ,132
;Thunk Compiler Version 1.8 Dec 14 1994 14:53:05
;File Compiled Fri Jun 20 10:27:33 1997
;Command Line: thunk -P2 -NC ddraw -t thk3216 ..\32to16.thk -o 32to16.asm
TITLE $32to16.asm
.386
OPTION READONLY
OPTION OLDSTRUCTS
IFNDEF IS_16
IFNDEF IS_32
%out command line error: specify one of -DIS_16, -DIS_32
.err
ENDIF ;IS_32
ENDIF ;IS_16
IFDEF IS_32
IFDEF IS_16
%out command line error: you can't specify both -DIS_16 and -DIS_32
.err
ENDIF ;IS_16
;************************* START OF 32-BIT CODE *************************
.model FLAT,STDCALL
;-- Import common flat thunk routines (in k32)
externDef MapHInstLS :near32
externDef MapHInstLS_PN :near32
externDef MapHInstSL :near32
externDef MapHInstSL_PN :near32
externDef FT_Prolog :near32
externDef FT_Thunk :near32
externDef QT_Thunk :near32
externDef FT_Exit0 :near32
externDef FT_Exit4 :near32
externDef FT_Exit8 :near32
externDef FT_Exit12 :near32
externDef FT_Exit16 :near32
externDef FT_Exit20 :near32
externDef FT_Exit24 :near32
externDef FT_Exit28 :near32
externDef FT_Exit32 :near32
externDef FT_Exit36 :near32
externDef FT_Exit40 :near32
externDef FT_Exit44 :near32
externDef FT_Exit48 :near32
externDef FT_Exit52 :near32
externDef FT_Exit56 :near32
externDef SMapLS :near32
externDef SUnMapLS :near32
externDef SMapLS_IP_EBP_8 :near32
externDef SUnMapLS_IP_EBP_8 :near32
externDef SMapLS_IP_EBP_12 :near32
externDef SUnMapLS_IP_EBP_12 :near32
externDef SMapLS_IP_EBP_16 :near32
externDef SUnMapLS_IP_EBP_16 :near32
externDef SMapLS_IP_EBP_20 :near32
externDef SUnMapLS_IP_EBP_20 :near32
externDef SMapLS_IP_EBP_24 :near32
externDef SUnMapLS_IP_EBP_24 :near32
externDef SMapLS_IP_EBP_28 :near32
externDef SUnMapLS_IP_EBP_28 :near32
externDef SMapLS_IP_EBP_32 :near32
externDef SUnMapLS_IP_EBP_32 :near32
externDef SMapLS_IP_EBP_36 :near32
externDef SUnMapLS_IP_EBP_36 :near32
externDef SMapLS_IP_EBP_40 :near32
externDef SUnMapLS_IP_EBP_40 :near32
MapSL PROTO NEAR STDCALL p32:DWORD
.code
;************************* COMMON PER-MODULE ROUTINES *************************
.data
public thk3216_ThunkData32 ;This symbol must be exported.
thk3216_ThunkData32 label dword
dd 3130534ch ;Protocol 'LS01'
dd 0210141h ;Checksum
dd 0 ;Jump table address.
dd 3130424ch ;'LB01'
dd 0 ;Flags
dd 0 ;Reserved (MUST BE 0)
dd 0 ;Reserved (MUST BE 0)
dd offset QT_Thunk_thk3216 - offset thk3216_ThunkData32
dd offset FT_Prolog_thk3216 - offset thk3216_ThunkData32
.code
externDef ThunkConnect32@24:near32
public thk3216_ThunkConnect32@16
thk3216_ThunkConnect32@16:
pop edx
push offset thk3216_ThkData16
push offset thk3216_ThunkData32
push edx
jmp ThunkConnect32@24
thk3216_ThkData16 label byte
db "thk3216_ThunkData16",0
pfnQT_Thunk_thk3216 dd offset QT_Thunk_thk3216
pfnFT_Prolog_thk3216 dd offset FT_Prolog_thk3216
.data
QT_Thunk_thk3216 label byte
db 32 dup(0cch) ;Patch space.
FT_Prolog_thk3216 label byte
db 32 dup(0cch) ;Patch space.
.code
;************************ START OF THUNK BODIES************************
;
public DD16_GetMonitorMaxSize@4
DD16_GetMonitorMaxSize@4:
mov cl,54
; DD16_GetMonitorMaxSize(16) = DD16_GetMonitorMaxSize(32) {}
;
; dword ptr [ebp+8]: dev
;
public IIDD16_GetMonitorMaxSize@4
IIDD16_GetMonitorMaxSize@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;dev: dword->dword
call dword ptr [pfnQT_Thunk_thk3216]
cwde
leave
retn 4
;
public DD16_GetMonitorRefreshRateRanges@20
DD16_GetMonitorRefreshRateRanges@20:
mov cx, (5 SHL 10) + (0 SHL 8) + 53
; DD16_GetMonitorRefreshRateRanges(16) = DD16_GetMonitorRefreshRateRanges(32) {}
;
; dword ptr [ebp+8]: dev
; dword ptr [ebp+12]: xres
; dword ptr [ebp+16]: yres
; dword ptr [ebp+20]: pmin
; dword ptr [ebp+24]: pmax
;
public IIDD16_GetMonitorRefreshRateRanges@20
IIDD16_GetMonitorRefreshRateRanges@20:
call dword ptr [pfnFT_Prolog_thk3216]
xor eax,eax
push eax
push eax
mov edx, dword ptr [ebp+20]
or edx,edx
jz @F
or dword ptr [edx], 0
@@:
mov edx, dword ptr [ebp+24]
or edx,edx
jz @F
or dword ptr [edx], 0
@@:
push dword ptr [ebp+8] ;dev: dword->dword
push word ptr [ebp+12] ;xres: dword->word
push word ptr [ebp+16] ;yres: dword->word
mov eax, dword ptr [ebp+20]
call SMapLS
mov [ebp-68],edx
push eax
mov eax, dword ptr [ebp+24]
call SMapLS
mov [ebp-72],edx
push eax
call FT_Thunk
movsx ebx,ax
mov edx, dword ptr [ebp+20]
or edx,edx
jz L0
movsx ecx, word ptr [edx]
mov dword ptr [edx], ecx
L0:
mov ecx, dword ptr [ebp-68]
call SUnMapLS
mov edx, dword ptr [ebp+24]
or edx,edx
jz L1
movsx ecx, word ptr [edx]
mov dword ptr [edx], ecx
L1:
mov ecx, dword ptr [ebp-72]
call SUnMapLS
jmp FT_Exit20
;
public DD16_IsWin95MiniDriver@0
DD16_IsWin95MiniDriver@0:
mov cl,51
; DD16_IsWin95MiniDriver(16) = DD16_IsWin95MiniDriver(32) {}
;
;
public IIDD16_IsWin95MiniDriver@0
IIDD16_IsWin95MiniDriver@0:
push ebp
mov ebp,esp
push ecx
sub esp,60
call dword ptr [pfnQT_Thunk_thk3216]
cwde
leave
retn
;
public ModeX_SetPaletteEntries@12
ModeX_SetPaletteEntries@12:
mov cl,50
; ModeX_SetPaletteEntries(16) = ModeX_SetPaletteEntries(32) {}
;
; dword ptr [ebp+8]: wBase
; dword ptr [ebp+12]: wNum
; dword ptr [ebp+16]: lpPaletteEntries
;
public IIModeX_SetPaletteEntries@12
IIModeX_SetPaletteEntries@12:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;wBase: dword->word
push word ptr [ebp+12] ;wNum: dword->word
call SMapLS_IP_EBP_16
push eax
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
call SUnMapLS_IP_EBP_16
leave
retn 12
;
public ModeX_SetMode@8
ModeX_SetMode@8:
mov cl,49
; ModeX_SetMode(16) = ModeX_SetMode(32) {}
;
; dword ptr [ebp+8]: wWidth
; dword ptr [ebp+12]: wHeight
;
public IIModeX_SetMode@8
IIModeX_SetMode@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;wWidth: dword->word
push word ptr [ebp+12] ;wHeight: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
leave
retn 8
;
public ModeX_RestoreMode@0
ModeX_RestoreMode@0:
mov cl,48
; ModeX_RestoreMode(16) = ModeX_RestoreMode(32) {}
;
;
public IIModeX_RestoreMode@0
IIModeX_RestoreMode@0:
push ebp
mov ebp,esp
push ecx
sub esp,60
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
leave
retn
;
public ModeX_Flip@4
ModeX_Flip@4:
mov cl,47
; ModeX_Flip(16) = ModeX_Flip(32) {}
;
; dword ptr [ebp+8]: lpBackBuffer
;
public IIModeX_Flip@4
IIModeX_Flip@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;lpBackBuffer: dword->dword
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
leave
retn 4
;
public DD16_SetEventHandle@8
DD16_SetEventHandle@8:
mov cl,46
; DD16_SetEventHandle(16) = DD16_SetEventHandle(32) {}
;
; dword ptr [ebp+8]: hInstance
; dword ptr [ebp+12]: dwEvent
;
public IIDD16_SetEventHandle@8
IIDD16_SetEventHandle@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;hInstance: dword->dword
push dword ptr [ebp+12] ;dwEvent: dword->dword
call dword ptr [pfnQT_Thunk_thk3216]
leave
retn 8
;
public DD16_ChangeDisplaySettings@8
DD16_ChangeDisplaySettings@8:
mov cl,42
; DD16_ChangeDisplaySettings(16) = DD16_ChangeDisplaySettings(32) {}
;
; dword ptr [ebp+8]: pdm
; dword ptr [ebp+12]: flags
;
public IIDD16_ChangeDisplaySettings@8
IIDD16_ChangeDisplaySettings@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
push dword ptr [ebp+12] ;flags: dword->dword
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
call SUnMapLS_IP_EBP_8
leave
retn 8
;
public DD16_SafeMode@8
DD16_SafeMode@8:
mov cl,41
; DD16_SafeMode(16) = DD16_SafeMode(32) {}
;
; dword ptr [ebp+8]: hdc
; dword ptr [ebp+12]: fSafeMode
;
public IIDD16_SafeMode@8
IIDD16_SafeMode@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hdc: dword->word
push word ptr [ebp+12] ;fSafeMode: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
cwde
leave
retn 8
;
public DD16_GetDC@4
DD16_GetDC@4:
mov cl,40
; DD16_GetDC(16) = DD16_GetDC(32) {}
;
; dword ptr [ebp+8]: pddsd
;
public IIDD16_GetDC@4
IIDD16_GetDC@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
call dword ptr [pfnQT_Thunk_thk3216]
movzx eax,ax
call SUnMapLS_IP_EBP_8
leave
retn 4
;
public DD16_Exclude@8
DD16_Exclude@8:
mov cl,38
; DD16_Exclude(16) = DD16_Exclude(32) {}
;
; dword ptr [ebp+8]: dwPDevice
; dword ptr [ebp+12]: prcl
;
public IIDD16_Exclude@8
IIDD16_Exclude@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;dwPDevice: dword->dword
call SMapLS_IP_EBP_12
push eax
call dword ptr [pfnQT_Thunk_thk3216]
call SUnMapLS_IP_EBP_12
leave
retn 8
;
public DD16_Unexclude@4
DD16_Unexclude@4:
mov cl,37
jmp IIDD16_Unexclude@4
public DD16_DoneDriver@4
DD16_DoneDriver@4:
mov cl,45
; DD16_Unexclude(16) = DD16_Unexclude(32) {}
;
; dword ptr [ebp+8]: dwPDevice
;
public IIDD16_Unexclude@4
IIDD16_Unexclude@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;dwPDevice: dword->dword
call dword ptr [pfnQT_Thunk_thk3216]
leave
retn 4
;
public DD16_Stretch@56
DD16_Stretch@56:
mov cl,36
; DD16_Stretch(16) = DD16_Stretch(32) {}
;
; dword ptr [ebp+8]: DstPtr
; dword ptr [ebp+12]: DstPitch
; dword ptr [ebp+16]: DstBPP
; dword ptr [ebp+20]: DstX
; dword ptr [ebp+24]: DstY
; dword ptr [ebp+28]: DstDX
; dword ptr [ebp+32]: DstDY
; dword ptr [ebp+36]: SrcPtr
; dword ptr [ebp+40]: SrcPitch
; dword ptr [ebp+44]: SrcBPP
; dword ptr [ebp+48]: SrcX
; dword ptr [ebp+52]: SrcY
; dword ptr [ebp+56]: SrcDX
; dword ptr [ebp+60]: SrcDY
;
public IIDD16_Stretch@56
IIDD16_Stretch@56:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;DstPtr: dword->dword
push word ptr [ebp+12] ;DstPitch: dword->word
push word ptr [ebp+16] ;DstBPP: dword->word
push word ptr [ebp+20] ;DstX: dword->word
push word ptr [ebp+24] ;DstY: dword->word
push word ptr [ebp+28] ;DstDX: dword->word
push word ptr [ebp+32] ;DstDY: dword->word
push dword ptr [ebp+36] ;SrcPtr: dword->dword
push word ptr [ebp+40] ;SrcPitch: dword->word
push word ptr [ebp+44] ;SrcBPP: dword->word
push word ptr [ebp+48] ;SrcX: dword->word
push word ptr [ebp+52] ;SrcY: dword->word
push word ptr [ebp+56] ;SrcDX: dword->word
push word ptr [ebp+60] ;SrcDY: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
cwde
leave
retn 56
;
public DD16_SelectPalette@12
DD16_SelectPalette@12:
mov cl,35
; DD16_SelectPalette(16) = DD16_SelectPalette(32) {}
;
; dword ptr [ebp+8]: hDC
; dword ptr [ebp+12]: hPalette
; dword ptr [ebp+16]: f
;
public IIDD16_SelectPalette@12
IIDD16_SelectPalette@12:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hDC: dword->word
push word ptr [ebp+12] ;hPalette: dword->word
push word ptr [ebp+16] ;f: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
leave
retn 12
;
public DD16_InquireVisRgn@4
DD16_InquireVisRgn@4:
mov cl,34
; DD16_InquireVisRgn(16) = DD16_InquireVisRgn(32) {}
;
; dword ptr [ebp+8]: hDC
;
public IIDD16_InquireVisRgn@4
IIDD16_InquireVisRgn@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hDC: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
movzx eax,ax
leave
retn 4
;
public DD16_GetPaletteEntries@12
DD16_GetPaletteEntries@12:
mov cl,31
jmp IIDD16_GetPaletteEntries@12
public DD16_SetPaletteEntries@12
DD16_SetPaletteEntries@12:
mov cl,32
; DD16_GetPaletteEntries(16) = DD16_GetPaletteEntries(32) {}
;
; dword ptr [ebp+8]: dwBase
; dword ptr [ebp+12]: dwNum
; dword ptr [ebp+16]: lpPaletteEntries
;
public IIDD16_GetPaletteEntries@12
IIDD16_GetPaletteEntries@12:
push ebp
mov ebp,esp
push ecx
sub esp,60
push dword ptr [ebp+8] ;dwBase: dword->dword
push dword ptr [ebp+12] ;dwNum: dword->dword
call SMapLS_IP_EBP_16
push eax
call dword ptr [pfnQT_Thunk_thk3216]
cwde
call SUnMapLS_IP_EBP_16
leave
retn 12
;
public DDThunk16_SetEntries@4
DDThunk16_SetEntries@4:
mov cx, (1 SHL 10) + (0 SHL 8) + 20
; DDThunk16_SetEntries(16) = DDThunk16_SetEntries(32) {}
;
; dword ptr [ebp+8]: lpSetEntriesData
;
public IIDDThunk16_SetEntries@4
IIDDThunk16_SetEntries@4:
call dword ptr [pfnFT_Prolog_thk3216]
xor eax,eax
push eax
sub esp,28
mov esi,[ebp+8]
or esi,esi
jz @F
or byte ptr [esi], 0
or byte ptr [esi + 27], 0
@@:
mov esi,[ebp+8]
or esi,esi
jnz L2
push esi
jmp L3
L2:
lea edi,[ebp-96]
push edi ;lpSetEntriesData: lpstruct32->lpstruct16
or dword ptr [ebp-20],01h ;Set flag to fixup ESP-rel argument.
mov ecx,4
rep movsd
lodsd ;lpEntries near32->far16
call SMapLS
mov [ebp-68],edx
stosd
movsd
movsd
L3:
call FT_Thunk
shrd ebx,edx,16
mov bx,ax
mov edi,[ebp+8]
or edi,edi
jz L4
lea esi,[ebp-96] ;lpSetEntriesData Struct16->Struct32
mov ecx,4
rep movsd
lodsd ;lpEntries far16->near32
push eax
call MapSL
stosd
movsd
movsd
L4:
mov ecx, [ebp-68] ;lpEntries
call SUnMapLS
jmp FT_Exit4
;
public DDThunk16_GetFlipStatus@4
DDThunk16_GetFlipStatus@4:
mov cl,7
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_CreatePalette@4
DDThunk16_CreatePalette@4:
mov cl,30
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_CreateSurface@4
DDThunk16_CreateSurface@4:
mov cl,29
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_CanCreateSurface@4
DDThunk16_CanCreateSurface@4:
mov cl,28
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_WaitForVerticalBlank@4
DDThunk16_WaitForVerticalBlank@4:
mov cl,27
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_DestroyDriver@4
DDThunk16_DestroyDriver@4:
mov cl,26
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetMode@4
DDThunk16_SetMode@4:
mov cl,25
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_GetScanLine@4
DDThunk16_GetScanLine@4:
mov cl,24
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetExclusiveMode@4
DDThunk16_SetExclusiveMode@4:
mov cl,23
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_FlipToGDISurface@4
DDThunk16_FlipToGDISurface@4:
mov cl,22
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_DestroyPalette@4
DDThunk16_DestroyPalette@4:
mov cl,21
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_DestroySurface@4
DDThunk16_DestroySurface@4:
mov cl,19
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_Flip@4
DDThunk16_Flip@4:
mov cl,18
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_Blt@4
DDThunk16_Blt@4:
mov cl,17
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_Lock@4
DDThunk16_Lock@4:
mov cl,16
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_Unlock@4
DDThunk16_Unlock@4:
mov cl,15
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_AddAttachedSurface@4
DDThunk16_AddAttachedSurface@4:
mov cl,14
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetColorKey@4
DDThunk16_SetColorKey@4:
mov cl,13
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetClipList@4
DDThunk16_SetClipList@4:
mov cl,12
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_UpdateOverlay@4
DDThunk16_UpdateOverlay@4:
mov cl,11
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetOverlayPosition@4
DDThunk16_SetOverlayPosition@4:
mov cl,10
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_SetPalette@4
DDThunk16_SetPalette@4:
mov cl,9
jmp IIDDThunk16_GetFlipStatus@4
public DDThunk16_GetBltStatus@4
DDThunk16_GetBltStatus@4:
mov cl,8
; DDThunk16_GetFlipStatus(16) = DDThunk16_GetFlipStatus(32) {}
;
; dword ptr [ebp+8]: lpGetFlipStatusData
;
public IIDDThunk16_GetFlipStatus@4
IIDDThunk16_GetFlipStatus@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
call dword ptr [pfnQT_Thunk_thk3216]
shl eax,16
shrd eax,edx,16
call SUnMapLS_IP_EBP_8
leave
retn 4
;
public DCIIsBanked@4
DCIIsBanked@4:
mov cl,6
; DCIIsBanked(16) = DCIIsBanked(32) {}
;
; dword ptr [ebp+8]: hdc
;
public IIDCIIsBanked@4
IIDCIIsBanked@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hdc: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
cwde
leave
retn 4
;
public DCIOpenProvider@0
DCIOpenProvider@0:
mov cl,5
; DCIOpenProvider(16) = DCIOpenProvider(32) {}
;
;
public IIDCIOpenProvider@0
IIDCIOpenProvider@0:
push ebp
mov ebp,esp
push ecx
sub esp,60
call dword ptr [pfnQT_Thunk_thk3216]
movzx eax,ax
leave
retn
;
public DCICloseProvider@4
DCICloseProvider@4:
mov cl,4
jmp IIDCICloseProvider@4
public DD16_SetCertified@4
DD16_SetCertified@4:
mov cl,52
jmp IIDCICloseProvider@4
public DD16_ReleaseDC@4
DD16_ReleaseDC@4:
mov cl,39
jmp IIDCICloseProvider@4
public DD16_EnableReboot@4
DD16_EnableReboot@4:
mov cl,33
; DCICloseProvider(16) = DCICloseProvider(32) {}
;
; dword ptr [ebp+8]: hdc
;
public IIDCICloseProvider@4
IIDCICloseProvider@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hdc: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
leave
retn 4
;
public DCICreatePrimary32@8
DCICreatePrimary32@8:
mov cl,3
; DCICreatePrimary32(16) = DCICreatePrimary32(32) {}
;
; dword ptr [ebp+8]: hdc
; dword ptr [ebp+12]: lpSurface
;
public IIDCICreatePrimary32@8
IIDCICreatePrimary32@8:
push ebp
mov ebp,esp
push ecx
sub esp,60
push word ptr [ebp+8] ;hdc: dword->word
call SMapLS_IP_EBP_12
push eax
call dword ptr [pfnQT_Thunk_thk3216]
cwde
call SUnMapLS_IP_EBP_12
leave
retn 8
;
public DCIEndAccess@4
DCIEndAccess@4:
mov cl,1
jmp IIDCIEndAccess@4
public DD16_GetDriverFns@4
DD16_GetDriverFns@4:
mov cl,44
jmp IIDCIEndAccess@4
public DD16_GetHALInfo@4
DD16_GetHALInfo@4:
mov cl,43
jmp IIDCIEndAccess@4
public DCIDestroy32@4
DCIDestroy32@4:
mov cl,2
; DCIEndAccess(16) = DCIEndAccess(32) {}
;
; dword ptr [ebp+8]: pdci
;
public IIDCIEndAccess@4
IIDCIEndAccess@4:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
call dword ptr [pfnQT_Thunk_thk3216]
call SUnMapLS_IP_EBP_8
leave
retn 4
;
public DCIBeginAccess@20
DCIBeginAccess@20:
mov cl,0
; DCIBeginAccess(16) = DCIBeginAccess(32) {}
;
; dword ptr [ebp+8]: pdci
; dword ptr [ebp+12]: x
; dword ptr [ebp+16]: y
; dword ptr [ebp+20]: dx
; dword ptr [ebp+24]: dy
;
public IIDCIBeginAccess@20
IIDCIBeginAccess@20:
push ebp
mov ebp,esp
push ecx
sub esp,60
call SMapLS_IP_EBP_8
push eax
push word ptr [ebp+12] ;x: dword->word
push word ptr [ebp+16] ;y: dword->word
push word ptr [ebp+20] ;dx: dword->word
push word ptr [ebp+24] ;dy: dword->word
call dword ptr [pfnQT_Thunk_thk3216]
cwde
call SUnMapLS_IP_EBP_8
leave
retn 20
ELSE
;************************* START OF 16-BIT CODE *************************
OPTION SEGMENT:USE16
.model LARGE,PASCAL
.code ddraw
externDef DCIBeginAccess:far16
externDef DCIEndAccess:far16
externDef DCIDestroy:far16
externDef DCICreatePrimary32:far16
externDef DCICloseProvider:far16
externDef DCIOpenProvider:far16
externDef DCIIsBanked:far16
externDef DDThunk16_GetFlipStatus:far16
externDef DDThunk16_GetBltStatus:far16
externDef DDThunk16_SetPalette:far16
externDef DDThunk16_SetOverlayPosition:far16
externDef DDThunk16_UpdateOverlay:far16
externDef DDThunk16_SetClipList:far16
externDef DDThunk16_SetColorKey:far16
externDef DDThunk16_AddAttachedSurface:far16
externDef DDThunk16_Unlock:far16
externDef DDThunk16_Lock:far16
externDef DDThunk16_Blt:far16
externDef DDThunk16_Flip:far16
externDef DDThunk16_DestroySurface:far16
externDef DDThunk16_SetEntries:far16
externDef DDThunk16_DestroyPalette:far16
externDef DDThunk16_FlipToGDISurface:far16
externDef DDThunk16_SetExclusiveMode:far16
externDef DDThunk16_GetScanLine:far16
externDef DDThunk16_SetMode:far16
externDef DDThunk16_DestroyDriver:far16
externDef DDThunk16_WaitForVerticalBlank:far16
externDef DDThunk16_CanCreateSurface:far16
externDef DDThunk16_CreateSurface:far16
externDef DDThunk16_CreatePalette:far16
externDef DD16_GetPaletteEntries:far16
externDef DD16_SetPaletteEntries:far16
externDef DD16_EnableReboot:far16
externDef DD16_InquireVisRgn:far16
externDef DD16_SelectPalette:far16
externDef DD16_Stretch:far16
externDef DD16_Unexclude:far16
externDef DD16_Exclude:far16
externDef DD16_ReleaseDC:far16
externDef DD16_GetDC:far16
externDef DD16_SafeMode:far16
externDef DD16_ChangeDisplaySettings:far16
externDef DD16_GetHALInfo:far16
externDef DD16_GetDriverFns:far16
externDef DD16_DoneDriver:far16
externDef DD16_SetEventHandle:far16
externDef ModeX_Flip:far16
externDef ModeX_RestoreMode:far16
externDef ModeX_SetMode:far16
externDef ModeX_SetPaletteEntries:far16
externDef DD16_IsWin95MiniDriver:far16
externDef DD16_SetCertified:far16
externDef DD16_GetMonitorRefreshRateRanges:far16
externDef DD16_GetMonitorMaxSize:far16
FT_thk3216TargetTable label word
dw offset DCIBeginAccess
dw seg DCIBeginAccess
dw offset DCIEndAccess
dw seg DCIEndAccess
dw offset DCIDestroy
dw seg DCIDestroy
dw offset DCICreatePrimary32
dw seg DCICreatePrimary32
dw offset DCICloseProvider
dw seg DCICloseProvider
dw offset DCIOpenProvider
dw seg DCIOpenProvider
dw offset DCIIsBanked
dw seg DCIIsBanked
dw offset DDThunk16_GetFlipStatus
dw seg DDThunk16_GetFlipStatus
dw offset DDThunk16_GetBltStatus
dw seg DDThunk16_GetBltStatus
dw offset DDThunk16_SetPalette
dw seg DDThunk16_SetPalette
dw offset DDThunk16_SetOverlayPosition
dw seg DDThunk16_SetOverlayPosition
dw offset DDThunk16_UpdateOverlay
dw seg DDThunk16_UpdateOverlay
dw offset DDThunk16_SetClipList
dw seg DDThunk16_SetClipList
dw offset DDThunk16_SetColorKey
dw seg DDThunk16_SetColorKey
dw offset DDThunk16_AddAttachedSurface
dw seg DDThunk16_AddAttachedSurface
dw offset DDThunk16_Unlock
dw seg DDThunk16_Unlock
dw offset DDThunk16_Lock
dw seg DDThunk16_Lock
dw offset DDThunk16_Blt
dw seg DDThunk16_Blt
dw offset DDThunk16_Flip
dw seg DDThunk16_Flip
dw offset DDThunk16_DestroySurface
dw seg DDThunk16_DestroySurface
dw offset DDThunk16_SetEntries
dw seg DDThunk16_SetEntries
dw offset DDThunk16_DestroyPalette
dw seg DDThunk16_DestroyPalette
dw offset DDThunk16_FlipToGDISurface
dw seg DDThunk16_FlipToGDISurface
dw offset DDThunk16_SetExclusiveMode
dw seg DDThunk16_SetExclusiveMode
dw offset DDThunk16_GetScanLine
dw seg DDThunk16_GetScanLine
dw offset DDThunk16_SetMode
dw seg DDThunk16_SetMode
dw offset DDThunk16_DestroyDriver
dw seg DDThunk16_DestroyDriver
dw offset DDThunk16_WaitForVerticalBlank
dw seg DDThunk16_WaitForVerticalBlank
dw offset DDThunk16_CanCreateSurface
dw seg DDThunk16_CanCreateSurface
dw offset DDThunk16_CreateSurface
dw seg DDThunk16_CreateSurface
dw offset DDThunk16_CreatePalette
dw seg DDThunk16_CreatePalette
dw offset DD16_GetPaletteEntries
dw seg DD16_GetPaletteEntries
dw offset DD16_SetPaletteEntries
dw seg DD16_SetPaletteEntries
dw offset DD16_EnableReboot
dw seg DD16_EnableReboot
dw offset DD16_InquireVisRgn
dw seg DD16_InquireVisRgn
dw offset DD16_SelectPalette
dw seg DD16_SelectPalette
dw offset DD16_Stretch
dw seg DD16_Stretch
dw offset DD16_Unexclude
dw seg DD16_Unexclude
dw offset DD16_Exclude
dw seg DD16_Exclude
dw offset DD16_ReleaseDC
dw seg DD16_ReleaseDC
dw offset DD16_GetDC
dw seg DD16_GetDC
dw offset DD16_SafeMode
dw seg DD16_SafeMode
dw offset DD16_ChangeDisplaySettings
dw seg DD16_ChangeDisplaySettings
dw offset DD16_GetHALInfo
dw seg DD16_GetHALInfo
dw offset DD16_GetDriverFns
dw seg DD16_GetDriverFns
dw offset DD16_DoneDriver
dw seg DD16_DoneDriver
dw offset DD16_SetEventHandle
dw seg DD16_SetEventHandle
dw offset ModeX_Flip
dw seg ModeX_Flip
dw offset ModeX_RestoreMode
dw seg ModeX_RestoreMode
dw offset ModeX_SetMode
dw seg ModeX_SetMode
dw offset ModeX_SetPaletteEntries
dw seg ModeX_SetPaletteEntries
dw offset DD16_IsWin95MiniDriver
dw seg DD16_IsWin95MiniDriver
dw offset DD16_SetCertified
dw seg DD16_SetCertified
dw offset DD16_GetMonitorRefreshRateRanges
dw seg DD16_GetMonitorRefreshRateRanges
dw offset DD16_GetMonitorMaxSize
dw seg DD16_GetMonitorMaxSize
.data
public thk3216_ThunkData16 ;This symbol must be exported.
thk3216_ThunkData16 dd 3130534ch ;Protocol 'LS01'
dd 0210141h ;Checksum
dw offset FT_thk3216TargetTable
dw seg FT_thk3216TargetTable
dd 0 ;First-time flag.
.code ddraw
externDef ThunkConnect16:far16
public thk3216_ThunkConnect16
thk3216_ThunkConnect16:
pop ax
pop dx
push seg thk3216_ThunkData16
push offset thk3216_ThunkData16
push seg thk3216_ThkData32
push offset thk3216_ThkData32
push cs
push dx
push ax
jmp ThunkConnect16
thk3216_ThkData32 label byte
db "thk3216_ThunkData32",0
ENDIF
END
|
; A195062: Period 7: repeat [1, 0, 1, 0, 1, 0, 1].
; 1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1
mod $0,7
mod $0,2
pow $1,$0
|
; Gravity Ring
; Negate pit damage if we have the gravity ring
; Guard/Diamond rings also reduces the damage dealt.
DoPitDamage:
LDA !GravityRingFlag : BEQ + ; check if we have the gravity ring
RTL ; if we have it, don't do anything
+
JSL.l OHKOTimer ; otherwise, call damage routines
LDA $7EF36D : SBC #8 ; and reduce health by one heart (8 health)
ADC !GuardRingFlag ; calculate guard ring reduction
ADC !GuardRingFlag ; (it's double the current ring)
STA $7EF36D
CMP.b #$A8 : BCC .notDead ; for overflowed numbers, set health to 0
LDA.b #$00 : STA $7EF36D
.notDead
RTL
; See newitems/jump for the jump functionality
|
;--------------------------------------------------------------
; ARX816 style Graphics
; for the ZX81
;--------------------------------------------------------------
;
; Invert screen output
;
; Stefano - Oct 2011
;
;
; $Id: invhrg_arx.asm,v 1.3 2016-06-27 20:26:33 dom Exp $
;
SECTION code_clib
PUBLIC invhrg
PUBLIC _invhrg
EXTERN HRG_LineStart
invhrg:
_invhrg:
ld hl,HRG_LineStart
ld c,2
invhrg2:
ld b,32
invloop:
ld a,(hl)
xor 128
ld (hl),a
inc hl
djnz invloop
inc hl
ld b,32
dec c
jr nz,invhrg2
ret
|
bootblockother.o： 檔案格式 elf32-i386
Disassembly of section .text:
00007000 <start>:
# This code combines elements of bootasm.S and entry.S.
.code16
.globl start
start:
cli
7000: fa cli
# Zero data segment registers DS, ES, and SS.
xorw %ax,%ax
7001: 31 c0 xor %eax,%eax
movw %ax,%ds
7003: 8e d8 mov %eax,%ds
movw %ax,%es
7005: 8e c0 mov %eax,%es
movw %ax,%ss
7007: 8e d0 mov %eax,%ss
# Switch from real to protected mode. Use a bootstrap GDT that makes
# virtual addresses map directly to physical addresses so that the
# effective memory map doesn't change during the transition.
lgdt gdtdesc
7009: 0f 01 16 lgdtl (%esi)
700c: 84 70 0f test %dh,0xf(%eax)
movl %cr0, %eax
700f: 20 c0 and %al,%al
orl $CR0_PE, %eax
7011: 66 83 c8 01 or $0x1,%ax
movl %eax, %cr0
7015: 0f 22 c0 mov %eax,%cr0
# Complete the transition to 32-bit protected mode by using a long jmp
# to reload %cs and %eip. The segment descriptors are set up with no
# translation, so that the mapping is still the identity mapping.
ljmpl $(SEG_KCODE<<3), $(start32)
7018: 66 ea 20 70 00 00 ljmpw $0x0,$0x7020
701e: 08 00 or %al,(%eax)
00007020 <start32>:
//PAGEBREAK!
.code32 # Tell assembler to generate 32-bit code now.
start32:
# Set up the protected-mode data segment registers
movw $(SEG_KDATA<<3), %ax # Our data segment selector
7020: 66 b8 10 00 mov $0x10,%ax
movw %ax, %ds # -> DS: Data Segment
7024: 8e d8 mov %eax,%ds
movw %ax, %es # -> ES: Extra Segment
7026: 8e c0 mov %eax,%es
movw %ax, %ss # -> SS: Stack Segment
7028: 8e d0 mov %eax,%ss
movw $0, %ax # Zero segments not ready for use
702a: 66 b8 00 00 mov $0x0,%ax
movw %ax, %fs # -> FS
702e: 8e e0 mov %eax,%fs
movw %ax, %gs # -> GS
7030: 8e e8 mov %eax,%gs
# Turn on page size extension for 4Mbyte pages
movl %cr4, %eax
7032: 0f 20 e0 mov %cr4,%eax
orl $(CR4_PSE), %eax
7035: 83 c8 10 or $0x10,%eax
movl %eax, %cr4
7038: 0f 22 e0 mov %eax,%cr4
# Use entrypgdir as our initial page table
movl (start-12), %eax
703b: a1 f4 6f 00 00 mov 0x6ff4,%eax
movl %eax, %cr3
7040: 0f 22 d8 mov %eax,%cr3
# Turn on paging.
movl %cr0, %eax
7043: 0f 20 c0 mov %cr0,%eax
orl $(CR0_PE|CR0_PG|CR0_WP), %eax
7046: 0d 01 00 01 80 or $0x80010001,%eax
movl %eax, %cr0
704b: 0f 22 c0 mov %eax,%cr0
# Switch to the stack allocated by startothers()
movl (start-4), %esp
704e: 8b 25 fc 6f 00 00 mov 0x6ffc,%esp
# Call mpenter()
call *(start-8)
7054: ff 15 f8 6f 00 00 call *0x6ff8
movw $0x8a00, %ax
705a: 66 b8 00 8a mov $0x8a00,%ax
movw %ax, %dx
705e: 66 89 c2 mov %ax,%dx
outw %ax, %dx
7061: 66 ef out %ax,(%dx)
movw $0x8ae0, %ax
7063: 66 b8 e0 8a mov $0x8ae0,%ax
outw %ax, %dx
7067: 66 ef out %ax,(%dx)
00007069 <spin>:
spin:
jmp spin
7069: eb fe jmp 7069 <spin>
706b: 90 nop
0000706c <gdt>:
...
7074: ff (bad)
7075: ff 00 incl (%eax)
7077: 00 00 add %al,(%eax)
7079: 9a cf 00 ff ff 00 00 lcall $0x0,$0xffff00cf
7080: 00 .byte 0x0
7081: 92 xchg %eax,%edx
7082: cf iret
...
00007084 <gdtdesc>:
7084: 17 pop %ss
7085: 00 6c 70 00 add %ch,0x0(%eax,%esi,2)
...
|
Name: zel_ending.asm
Type: file
Size: 102194
Last-Modified: '2016-05-13T04:20:48Z'
SHA-1: 1245B96E6CD53964BBC3274533C37CD51E0F16E4
Description: null
|
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x0000000000000000", "0x0000000000000000"],
"XMM1": ["0xffffffffffffffff", "0xffffffffffffffff"],
"XMM2": ["0x0b0d090e0b0d090e", "0x0b0d090e0b0d090e"],
"XMM3": ["0xffffffff00000000", "0x0b0d090effffffff"],
"XMM4": ["0x0202020202020202", "0x0303030303030303"]
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x0000000000000000
mov [rdx + 8 * 0], rax
mov [rdx + 8 * 1], rax
mov rax, 0xFFFFFFFFFFFFFFFF
mov [rdx + 8 * 2], rax
mov [rdx + 8 * 3], rax
mov rax, 0x0000000100000001
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov rax, 0xFFFFFFFF00000000
mov [rdx + 8 * 6], rax
mov rax, 0x00000001FFFFFFFF
mov [rdx + 8 * 7], rax
mov rax, 0x0202020202020202
mov [rdx + 8 * 8], rax
mov rax, 0x0303030303030303
mov [rdx + 8 * 9], rax
aesimc xmm0, [rdx + 8 * 0]
aesimc xmm1, [rdx + 8 * 2]
aesimc xmm2, [rdx + 8 * 4]
aesimc xmm3, [rdx + 8 * 6]
aesimc xmm4, [rdx + 8 * 8]
hlt
|
; ===============================================================
; 2017
; ===============================================================
;
; void tshc_cls_wc(struct r_Rect8 *r, uchar attr)
;
; Clear the rectangular area on screen.
;
; ===============================================================
SECTION code_clib
SECTION code_arch
PUBLIC asm_tshc_cls_wc
EXTERN asm_tshc_cls_wc_pix
EXTERN asm_tshc_cls_wc_attr
asm_tshc_cls_wc:
; enter : l = attr
; ix = rect *
;
; uses : af, bc, de, hl
push hl ; save attribute
ld l,0
call asm_tshc_cls_wc_pix
pop hl
jp asm_tshc_cls_wc_attr
|
; A062192: Row sums of unsigned triangle A062138 (generalized a=5 Laguerre).
; Submitted by Christian Krause
; 1,7,57,529,5509,63591,805597,11109337,165625929,2654025319,45481765921,829903882017,16062421776397,328634683136839,7086337847838789,160604998959958441,3816483607166825617,94879581028960162887,2462697953106973897609,66615865437610370161969,1874723678075686559978901,54804080150752083238023847,1661800799157527216914688557,52198217147487150619262951289,1696305794159371455127876987609,56966859544114373201026220221351,1974881648394990681112586811910257,70602728462748265385615488404296257
add $0,1
mov $1,3
lpb $0
sub $0,1
add $2,4
mul $3,$2
mov $2,$0
add $3,$1
mul $1,$0
add $1,$3
lpe
mov $0,$3
div $0,3
|
#ifndef Integral_Value_Operator_hh
#define Integral_Value_Operator_hh
#include "Integration_Mesh.hh"
#include "Vector_Operator.hh"
#include <memory>
#include <vector>
class Angular_Discretization;
class Energy_Discretization;
class Weak_Spatial_Discretization;
class Integral_Value_Operator : public Vector_Operator
{
public:
Integral_Value_Operator(std::shared_ptr<Integration_Mesh_Options> options,
std::shared_ptr<Weak_Spatial_Discretization> spatial,
std::shared_ptr<Angular_Discretization> angular,
std::shared_ptr<Energy_Discretization> energy);
virtual int row_size() const override
{
return row_size_;
}
virtual int column_size() const override
{
return column_size_;
}
virtual void check_class_invariants() const override;
virtual std::string description() const override
{
return "Integral_Value_Operator";
}
private:
virtual void apply(std::vector<double> &x) const override;
void get_flux(std::shared_ptr<Integration_Cell> const cell,
std::vector<double> const &b_val,
std::vector<double> const &coeff,
std::vector<double> &flux) const;
int row_size_;
int column_size_;
std::shared_ptr<Integration_Mesh_Options> integration_options_;
std::shared_ptr<Weak_Spatial_Discretization> spatial_;
std::shared_ptr<Angular_Discretization> angular_;
std::shared_ptr<Energy_Discretization> energy_;
mutable bool initialized_;
mutable std::shared_ptr<Integration_Mesh> mesh_;
};
#endif
|
; A055374: Invert transform applied three times to Pascal's triangle A007318.
; Submitted by Christian Krause
; 1,1,1,4,8,4,16,48,48,16,64,256,384,256,64,256,1280,2560,2560,1280,256,1024,6144,15360,20480,15360,6144,1024,4096,28672,86016,143360,143360,86016,28672,4096,16384,131072,458752,917504,1146880,917504
lpb $0
add $1,1
sub $0,$1
mov $2,$1
sub $2,1
lpe
bin $1,$0
mov $0,4
pow $0,$2
mul $1,$0
mov $0,$1
|
%include "../defaults_bin.asm"
mov cx,64
loopTop:
push cx
mov ah,0
sub ah,cl
mov al,0xc4
push ax
call trial
pop ax
mov al,0xc5
push ax
call trial
pop ax
pop cx
loop loopTop
; mov cx,8
;loopTop2:
; push cx
; mov ah,0x40
; sub ah,cl
; mov al,0xff
; push ax
; call trial
; pop ax
; pop cx
; loop loopTop2
mov ax,0x38ff
call trial
mov ax,0x39ff
call trial
mov ax,0x3aff
call trial
mov ax,0x3bff
call trial
mov ax,0x3cff
call trial
mov ax,0x3dff
call trial
mov ax,0x3eff
call trial
mov ax,0x3fff
call trial
mov ax,0x78ff
call trial
mov ax,0x79ff
call trial
mov ax,0x7aff
call trial
mov ax,0x7bff
call trial
mov ax,0x7cff
call trial
mov ax,0x7dff
call trial
mov ax,0x7eff
call trial
mov ax,0x7fff
call trial
mov ax,0xb8ff
call trial
mov ax,0xb9ff
call trial
mov ax,0xbaff
call trial
mov ax,0xbbff
call trial
mov ax,0xbcff
call trial
mov ax,0xbdff
call trial
mov ax,0xbeff
call trial
mov ax,0xbfff
call trial
mov ax,0xf8ff
call trial
mov ax,0xf9ff
call trial
mov ax,0xfaff
call trial
mov ax,0xfbff
call trial
mov ax,0xfcff
call trial
mov ax,0xfdff
call trial
mov ax,0xfeff
call trial
mov ax,0xffff
call trial
mov ax,0x9090
call trial
complete
trial:
cli
mov [cs:data],ax
mov [cs:data + 2],ax
mov [cs:savedStack],sp
mov [cs:savedStack+2],ss
mov ax,0x89ab
mov ds,ax
mov ax,0x9acd
mov es,ax
mov ax,0x1234
mov bx,0x2345
mov cx,0x3579
mov dx,0x4abc
mov si,0x5678
mov di,0x6996
mov bp,0x7adf
mov [bx+2],bx
mov [bx],dx
mov ax,word[bx+1] ; data = 0x454a address = 0x2346
; mov bp,[bx]
mov ax,0x1234
mov ax,0x1234
mov ax,0x1234
data:
db 0xc5, 0xf1 ; lds si,ax ; DS = [0x2348] = 0x0023 SI = 0x454a
db 0xc5, 0xf1 ; lds si,ax ; DS = [0x234A] = 0x0000 SI = 0x0023
mov [cs:outRegs],ax
mov [cs:outRegs + 2],cx
mov [cs:outRegs + 4],dx
mov [cs:outRegs + 6],bx
mov [cs:outRegs + 8],sp
mov [cs:outRegs + 10],bp
mov [cs:outRegs + 12],si
mov [cs:outRegs + 14],di
mov [cs:outRegs + 16],es
mov [cs:outRegs + 18],cs
mov [cs:outRegs + 20],ss
mov [cs:outRegs + 22],ds
mov sp,[cs:savedStack]
mov ss,[cs:savedStack+2]
pushf
pop ax
mov [cs:outRegs + 24],ax
sti
mov ax,[cs:outRegs]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 2]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 4]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 6]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 8]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 10]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 12]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 14]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 16]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 18]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 20]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 22]
outputHex
outputCharacter ' '
mov ax,[cs:outRegs + 24]
outputHex
outputCharacter 10
ret
savedStack: dw 0,0
outRegs: dw 0,0,0,0, 0,0,0,0, 0,0,0,0, 0
; Output: 1234 2345 3579 4ABC 5678 6996 FFFC 7ADF 00A8 89AB 9ACD 9000
; 1234 2345 3579 4ABC F046 6996 FFFC 7ADF 00A8 0000 9ACD 9000
; AX BX CX DX SI DI SP BP CS DS ES SS
|
setrepeat 2
frame 1, 04
frame 0, 04
frame 2, 04
frame 0, 04
dorepeat 1
endanim
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r14
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x884c, %rsi
lea addresses_D_ht+0x8cdc, %rdi
inc %r11
mov $81, %rcx
rep movsw
nop
cmp $11445, %rdx
lea addresses_A_ht+0x138dc, %r11
nop
nop
nop
nop
nop
cmp %rbx, %rbx
mov (%r11), %cx
nop
nop
nop
and %r11, %r11
lea addresses_normal_ht+0x31dc, %rsi
nop
nop
nop
nop
nop
sub %r14, %r14
mov (%rsi), %rdi
nop
nop
xor %rdi, %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %r14
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r14
push %r9
push %rax
push %rbx
push %rcx
push %rsi
// Store
mov $0x23bf39000000058a, %rsi
nop
nop
nop
cmp %r9, %r9
mov $0x5152535455565758, %rbx
movq %rbx, %xmm7
vmovups %ymm7, (%rsi)
nop
nop
nop
nop
xor %r9, %r9
// Faulty Load
lea addresses_normal+0x40dc, %r9
clflush (%r9)
nop
nop
nop
nop
nop
add $53974, %r10
mov (%r9), %r14
lea oracles, %rbx
and $0xff, %r14
shlq $12, %r14
mov (%rbx,%r14,1), %r14
pop %rsi
pop %rcx
pop %rbx
pop %rax
pop %r9
pop %r14
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_normal', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 1, 'NT': False, 'type': 'addresses_NC', 'size': 32, 'AVXalign': False}}
[Faulty Load]
{'src': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_normal', 'size': 8, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_D_ht', 'congruent': 4, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 10, 'same': False}}
{'src': {'same': False, 'congruent': 9, 'NT': False, 'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 8, 'NT': False, 'type': 'addresses_normal_ht', 'size': 8, 'AVXalign': False}, 'OP': 'LOAD'}
{'34': 241}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
|
/********************* */
/*! \file ce_guided_instantiation.cpp
** \verbatim
** Original author: Andrew Reynolds
** Major contributors: none
** Minor contributors (to current version): none
** This file is part of the CVC4 project.
** Copyright (c) 2009-2014 New York University and The University of Iowa
** See the file COPYING in the top-level source directory for licensing
** information.\endverbatim
**
** \brief counterexample guided instantiation class
**
**/
#include "theory/quantifiers/ce_guided_instantiation.h"
#include "theory/theory_engine.h"
#include "theory/quantifiers/options.h"
#include "theory/quantifiers/term_database.h"
#include "theory/quantifiers/first_order_model.h"
using namespace CVC4;
using namespace CVC4::kind;
using namespace CVC4::theory;
using namespace CVC4::theory::quantifiers;
using namespace std;
namespace CVC4 {
CegInstantiation::CegConjecture::CegConjecture( context::Context* c ) : d_active( c, false ), d_infeasible( c, false ), d_curr_lit( c, 0 ){
}
void CegInstantiation::CegConjecture::assign( Node q ) {
Assert( d_quant.isNull() );
Assert( q.getKind()==FORALL );
d_quant = q;
for( unsigned i=0; i<q[0].getNumChildren(); i++ ){
d_candidates.push_back( NodeManager::currentNM()->mkSkolem( "e", q[0][i].getType() ) );
}
}
void CegInstantiation::CegConjecture::initializeGuard( QuantifiersEngine * qe ){
if( d_guard.isNull() ){
d_guard = Rewriter::rewrite( NodeManager::currentNM()->mkSkolem( "G", NodeManager::currentNM()->booleanType() ) );
//specify guard behavior
d_guard = qe->getValuation().ensureLiteral( d_guard );
AlwaysAssert( !d_guard.isNull() );
qe->getOutputChannel().requirePhase( d_guard, true );
if( !d_syntax_guided ){
//add immediate lemma
Node lem = NodeManager::currentNM()->mkNode( OR, d_guard.negate(), d_base_inst.negate() );
Trace("cegqi") << "Add candidate lemma : " << lem << std::endl;
qe->getOutputChannel().lemma( lem );
}
}
}
Node CegInstantiation::CegConjecture::getLiteral( QuantifiersEngine * qe, int i ) {
if( d_measure_term.isNull() ){
return Node::null();
}else{
std::map< int, Node >::iterator it = d_lits.find( i );
if( it==d_lits.end() ){
Node lit = NodeManager::currentNM()->mkNode( LEQ, d_measure_term, NodeManager::currentNM()->mkConst( Rational( i ) ) );
lit = Rewriter::rewrite( lit );
d_lits[i] = lit;
Node lem = NodeManager::currentNM()->mkNode( kind::OR, lit, lit.negate() );
Trace("cegqi-lemma") << "Fairness split : " << lem << std::endl;
qe->getOutputChannel().lemma( lem );
qe->getOutputChannel().requirePhase( lit, true );
return lit;
}else{
return it->second;
}
}
}
CegInstantiation::CegInstantiation( QuantifiersEngine * qe, context::Context* c ) : QuantifiersModule( qe ){
d_conj = new CegConjecture( d_quantEngine->getSatContext() );
}
bool CegInstantiation::needsCheck( Theory::Effort e ) {
return e>=Theory::EFFORT_LAST_CALL;
}
bool CegInstantiation::needsModel( Theory::Effort e ) {
return true;
}
bool CegInstantiation::needsFullModel( Theory::Effort e ) {
return false;
}
void CegInstantiation::check( Theory::Effort e, unsigned quant_e ) {
if( quant_e==QuantifiersEngine::QEFFORT_MODEL ){
Trace("cegqi-engine") << "---Counterexample Guided Instantiation Engine---" << std::endl;
Trace("cegqi-engine-debug") << std::endl;
Trace("cegqi-engine-debug") << "Current conjecture status : active : " << d_conj->d_active << " feasible : " << !d_conj->d_infeasible << std::endl;
if( d_conj->d_active && !d_conj->d_infeasible ){
checkCegConjecture( d_conj );
}
Trace("cegqi-engine") << "Finished Counterexample Guided Instantiation engine." << std::endl;
}
}
void CegInstantiation::registerQuantifier( Node q ) {
if( d_quantEngine->getOwner( q )==this ){
if( !d_conj->isAssigned() ){
Trace("cegqi") << "Register conjecture : " << q << std::endl;
d_conj->assign( q );
//construct base instantiation
d_conj->d_base_inst = Rewriter::rewrite( d_quantEngine->getInstantiation( q, d_conj->d_candidates ) );
Trace("cegqi") << "Base instantiation is : " << d_conj->d_base_inst << std::endl;
if( getTermDatabase()->isQAttrSygus( q ) ){
Assert( d_conj->d_base_inst.getKind()==NOT );
Assert( d_conj->d_base_inst[0].getKind()==FORALL );
for( unsigned j=0; j<d_conj->d_base_inst[0][0].getNumChildren(); j++ ){
d_conj->d_inner_vars.push_back( d_conj->d_base_inst[0][0][j] );
}
d_conj->d_syntax_guided = true;
}else if( getTermDatabase()->isQAttrSynthesis( q ) ){
d_conj->d_syntax_guided = false;
}else{
Assert( false );
}
//fairness
if( options::ceGuidedInstFair()!=CEGQI_FAIR_NONE ){
std::vector< Node > mc;
for( unsigned j=0; j<d_conj->d_candidates.size(); j++ ){
TypeNode tn = d_conj->d_candidates[j].getType();
if( options::ceGuidedInstFair()==CEGQI_FAIR_DT_SIZE ){
if( tn.isDatatype() ){
mc.push_back( NodeManager::currentNM()->mkNode( DT_SIZE, d_conj->d_candidates[j] ) );
}
}else if( options::ceGuidedInstFair()==CEGQI_FAIR_UF_DT_SIZE ){
registerMeasuredType( tn );
std::map< TypeNode, Node >::iterator it = d_uf_measure.find( tn );
if( it!=d_uf_measure.end() ){
mc.push_back( NodeManager::currentNM()->mkNode( APPLY_UF, it->second, d_conj->d_candidates[j] ) );
}
}
}
if( !mc.empty() ){
d_conj->d_measure_term = mc.size()==1 ? mc[0] : NodeManager::currentNM()->mkNode( PLUS, mc );
Trace("cegqi") << "Measure term is : " << d_conj->d_measure_term << std::endl;
}
}
}else{
Assert( d_conj->d_quant==q );
}
}
}
void CegInstantiation::assertNode( Node n ) {
Trace("cegqi-debug") << "Cegqi : Assert : " << n << std::endl;
bool pol = n.getKind()!=NOT;
Node lit = n.getKind()==NOT ? n[0] : n;
if( lit==d_conj->d_guard ){
//d_guard_assertions[lit] = pol;
d_conj->d_infeasible = !pol;
}
if( lit==d_conj->d_quant ){
d_conj->d_active = true;
}
}
Node CegInstantiation::getNextDecisionRequest() {
d_conj->initializeGuard( d_quantEngine );
bool value;
if( !d_quantEngine->getValuation().hasSatValue( d_conj->d_guard, value ) ) {
if( d_conj->d_guard_split.isNull() ){
Node lem = NodeManager::currentNM()->mkNode( OR, d_conj->d_guard.negate(), d_conj->d_guard );
d_quantEngine->getOutputChannel().lemma( lem );
}
Trace("cegqi-debug") << "CEGQI : Decide next on : " << d_conj->d_guard << "..." << std::endl;
return d_conj->d_guard;
}
//enforce fairness
if( d_conj->isAssigned() && options::ceGuidedInstFair()!=CEGQI_FAIR_NONE ){
Node lit = d_conj->getLiteral( d_quantEngine, d_conj->d_curr_lit.get() );
if( d_quantEngine->getValuation().hasSatValue( lit, value ) ) {
if( !value ){
d_conj->d_curr_lit.set( d_conj->d_curr_lit.get() + 1 );
lit = d_conj->getLiteral( d_quantEngine, d_conj->d_curr_lit.get() );
Trace("cegqi-debug") << "CEGQI : Decide on next lit : " << lit << "..." << std::endl;
return lit;
}
}else{
Trace("cegqi-debug") << "CEGQI : Decide on current lit : " << lit << "..." << std::endl;
return lit;
}
}
return Node::null();
}
void CegInstantiation::checkCegConjecture( CegConjecture * conj ) {
Node q = conj->d_quant;
Trace("cegqi-engine") << "Synthesis conjecture : " << q << std::endl;
Trace("cegqi-engine") << " * Candidate program/output symbol : ";
for( unsigned i=0; i<conj->d_candidates.size(); i++ ){
Trace("cegqi-engine") << conj->d_candidates[i] << " ";
}
Trace("cegqi-engine") << std::endl;
if( options::ceGuidedInstFair()!=CEGQI_FAIR_NONE ){
Trace("cegqi-engine") << " * Current term size : " << conj->d_curr_lit.get() << std::endl;
}
if( conj->d_ce_sk.empty() ){
Trace("cegqi-engine") << " *** Check candidate phase..." << std::endl;
if( getTermDatabase()->isQAttrSygus( q ) ){
std::vector< Node > model_values;
if( getModelValues( conj->d_candidates, model_values ) ){
//check if we must apply fairness lemmas
std::vector< Node > lems;
if( options::ceGuidedInstFair()==CEGQI_FAIR_UF_DT_SIZE ){
for( unsigned j=0; j<conj->d_candidates.size(); j++ ){
getMeasureLemmas( conj->d_candidates[j], model_values[j], lems );
}
}
if( !lems.empty() ){
for( unsigned j=0; j<lems.size(); j++ ){
Trace("cegqi-lemma") << "Measure lemma : " << lems[j] << std::endl;
d_quantEngine->addLemma( lems[j] );
}
Trace("cegqi-engine") << " ...refine size." << std::endl;
}else{
//must get a counterexample to the value of the current candidate
Node inst = conj->d_base_inst.substitute( conj->d_candidates.begin(), conj->d_candidates.end(), model_values.begin(), model_values.end() );
inst = Rewriter::rewrite( inst );
//body should be an existential
Assert( inst.getKind()==NOT );
Assert( inst[0].getKind()==FORALL );
//immediately skolemize
Node inst_sk = getTermDatabase()->getSkolemizedBody( inst[0] );
Trace("cegqi-lemma") << "Counterexample lemma : " << inst_sk << std::endl;
d_quantEngine->addLemma( NodeManager::currentNM()->mkNode( OR, q.negate(), inst_sk.negate() ) );
conj->d_ce_sk.push_back( inst[0] );
Trace("cegqi-engine") << " ...find counterexample." << std::endl;
}
}
}else if( getTermDatabase()->isQAttrSynthesis( q ) ){
Trace("cegqi-engine") << " * Value is : ";
std::vector< Node > model_terms;
for( unsigned i=0; i<conj->d_candidates.size(); i++ ){
Node t = getModelTerm( conj->d_candidates[i] );
model_terms.push_back( t );
Trace("cegqi-engine") << t << " ";
}
Trace("cegqi-engine") << std::endl;
d_quantEngine->addInstantiation( q, model_terms, false );
}
}else{
Trace("cegqi-engine") << " *** Refine candidate phase..." << std::endl;
for( unsigned j=0; j<conj->d_ce_sk.size(); j++ ){
Node ce_q = conj->d_ce_sk[j];
Assert( conj->d_inner_vars.size()==getTermDatabase()->d_skolem_constants[ce_q].size() );
std::vector< Node > model_values;
if( getModelValues( getTermDatabase()->d_skolem_constants[ce_q], model_values ) ){
//candidate refinement : the next candidate must satisfy the counterexample found for the current model of the candidate
Node inst_ce_refine = conj->d_base_inst[0][1].substitute( conj->d_inner_vars.begin(), conj->d_inner_vars.end(),
model_values.begin(), model_values.end() );
Node lem = NodeManager::currentNM()->mkNode( OR, conj->d_guard.negate(), inst_ce_refine );
Trace("cegqi-lemma") << "Candidate refinement lemma : " << lem << std::endl;
Trace("cegqi-engine") << " ...refine candidate." << std::endl;
d_quantEngine->addLemma( lem );
}
}
conj->d_ce_sk.clear();
}
}
bool CegInstantiation::getModelValues( std::vector< Node >& n, std::vector< Node >& v ) {
bool success = true;
Trace("cegqi-engine") << " * Value is : ";
for( unsigned i=0; i<n.size(); i++ ){
Node nv = getModelValue( n[i] );
v.push_back( nv );
Trace("cegqi-engine") << nv << " ";
if( nv.isNull() ){
success = false;
}
}
Trace("cegqi-engine") << std::endl;
return success;
}
Node CegInstantiation::getModelValue( Node n ) {
Trace("cegqi-mv") << "getModelValue for : " << n << std::endl;
return d_quantEngine->getModel()->getValue( n );
}
Node CegInstantiation::getModelTerm( Node n ){
//TODO
return getModelValue( n );
}
void CegInstantiation::registerMeasuredType( TypeNode tn ) {
std::map< TypeNode, Node >::iterator it = d_uf_measure.find( tn );
if( it==d_uf_measure.end() ){
if( tn.isDatatype() ){
TypeNode op_tn = NodeManager::currentNM()->mkFunctionType( tn, NodeManager::currentNM()->integerType() );
Node op = NodeManager::currentNM()->mkSkolem( "tsize", op_tn, "was created by ceg instantiation to enforce fairness." );
d_uf_measure[tn] = op;
}
}
}
Node CegInstantiation::getSizeTerm( Node n, TypeNode tn, std::vector< Node >& lems ) {
std::map< Node, Node >::iterator itt = d_size_term.find( n );
if( itt==d_size_term.end() ){
registerMeasuredType( tn );
Node sn = NodeManager::currentNM()->mkNode( APPLY_UF, d_uf_measure[tn], n );
lems.push_back( NodeManager::currentNM()->mkNode( LEQ, NodeManager::currentNM()->mkConst( Rational(0) ), sn ) );
d_size_term[n] = sn;
return sn;
}else{
return itt->second;
}
}
void CegInstantiation::getMeasureLemmas( Node n, Node v, std::vector< Node >& lems ) {
Trace("cegqi-lemma-debug") << "Get measure lemma " << n << " " << v << std::endl;
Assert( n.getType()==v.getType() );
TypeNode tn = n.getType();
if( tn.isDatatype() ){
Assert( v.getKind()==APPLY_CONSTRUCTOR );
const Datatype& dt = ((DatatypeType)(tn).toType()).getDatatype();
int index = Datatype::indexOf( v.getOperator().toExpr() );
std::map< int, Node >::iterator it = d_size_term_lemma[n].find( index );
if( it==d_size_term_lemma[n].end() ){
Node lhs = getSizeTerm( n, tn, lems );
//add measure lemma
std::vector< Node > sumc;
for( unsigned j=0; j<dt[index].getNumArgs(); j++ ){
TypeNode tnc = v[j].getType();
if( tnc.isDatatype() ){
Node seln = NodeManager::currentNM()->mkNode( APPLY_SELECTOR_TOTAL, Node::fromExpr( dt[index][j].getSelector() ), n );
sumc.push_back( getSizeTerm( seln, tnc, lems ) );
}
}
Node rhs;
if( !sumc.empty() ){
sumc.push_back( NodeManager::currentNM()->mkConst( Rational(1) ) );
rhs = NodeManager::currentNM()->mkNode( PLUS, sumc );
}else{
rhs = NodeManager::currentNM()->mkConst( Rational(0) );
}
Node lem = lhs.eqNode( rhs );
Node cond = NodeManager::currentNM()->mkNode( APPLY_TESTER, Node::fromExpr( dt[index].getTester() ), n );
lem = NodeManager::currentNM()->mkNode( OR, cond.negate(), lem );
d_size_term_lemma[n][index] = lem;
Trace("cegqi-lemma-debug") << "...constructed lemma " << lem << std::endl;
lems.push_back( lem );
//return;
}
//get lemmas for children
for( unsigned i=0; i<v.getNumChildren(); i++ ){
Node nn = NodeManager::currentNM()->mkNode( APPLY_SELECTOR_TOTAL, Node::fromExpr( dt[index][i].getSelector() ), n );
getMeasureLemmas( nn, v[i], lems );
}
}
}
}
|
; A217527: a(n) = 2^(n-2)*(n-2)^2+2^(n-1).
; 2,6,24,88,288,864,2432,6528,16896,42496,104448,251904,598016,1400832,3244032,7438336,16908288,38141952,85458944,190316544,421527552,929038336,2038431744,4454350848,9697230848,21038628864,45499809792,98113159168,210990268416,452582178816,968515125248,2068026753024,4406636445696,9371618639872,19894288515072,42159398977536,89197880803328,188428805210112,397473453441024,837278104551424,1761417627697152,3700956139094016,7766950138609664
mov $1,$0
mul $1,$0
add $1,2
mov $2,$0
add $2,7
lpb $2,1
mul $1,2
sub $2,1
lpe
div $1,256
mul $1,2
|
; A109523: a(n) is the sum of the (1,2)- and (1,3)-entries of the matrix P^n + T^n, where the 3 X 3 matrices P and T are defined by P = [0,1,0; 0,0,1; 1,0,0] and T = [0,1,0; 0,0,1; 1,1,1].
; Submitted by Simon Strandgaard
; 0,2,2,2,5,8,13,25,45,81,150,275,504,928,1706,3136,5769,10610,19513,35891,66013,121415,223318,410745,755476,1389538,2555758,4700770,8646065,15902592,29249425,53798081,98950097,181997601,334745778
lpb $0
sub $0,1
add $1,$2
mul $4,2
add $4,1
mov $2,$4
add $2,$3
mov $4,$3
mov $3,$1
div $4,2
add $4,2
lpe
mov $0,$4
|
// =============================================================================
// PROJECT CHRONO - http://projectchrono.org
//
// Copyright (c) 2014 projectchrono.org
// All right reserved.
//
// Use of this source code is governed by a BSD-style license that can be found
// in the LICENSE file at the top level of the distribution and at
// http://projectchrono.org/license-chrono.txt.
//
// =============================================================================
// Authors: Radu Serban, Justin Madsen
// =============================================================================
//
// Base class for a vehicle powertrain.
//
// =============================================================================
#include "subsys/ChPowertrain.h"
namespace chrono {
ChPowertrain::ChPowertrain()
: m_drive_mode(FORWARD)
{
}
} // end namespace chrono
|
/*
** Copyright 2011-2013 Merethis
**
** This file is part of Centreon Engine.
**
** Centreon Engine is free software: you can redistribute it and/or
** modify it under the terms of the GNU General Public License version 2
** as published by the Free Software Foundation.
**
** Centreon Engine is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
** General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with Centreon Engine. If not, see
** <http://www.gnu.org/licenses/>.
*/
#include <exception>
#include "com/centreon/engine/exceptions/error.hh"
#include "com/centreon/engine/globals.hh"
#include "com/centreon/engine/modules/external_commands/commands.hh"
#include "com/centreon/logging/engine.hh"
#include "test/unittest.hh"
using namespace com::centreon::engine;
/**
* Run disable_servicegroup_svc_checks test.
*/
static int check_disable_servicegroup_svc_checks(int argc, char** argv) {
(void)argc;
(void)argv;
service* svc = add_service(
"name", "description", NULL, NULL, 0, 42, 0, 0, 0, 42.0, 0.0, 0.0, NULL,
0, 0, 0, 0, 0, 0, 0, 0, NULL, 0, "command", 0, 0, 0.0, 0.0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, 0, 0);
if (!svc)
throw(engine_error() << "create service failed.");
servicegroup* group = add_servicegroup("group", NULL, NULL, NULL, NULL);
if (!group)
throw(engine_error() << "create servicegroup failed.");
servicesmember* member =
add_service_to_servicegroup(group, "name", "description");
if (!member)
throw(engine_error() << "create servicemember failed.");
member->service_ptr = svc;
svc->checks_enabled = true;
char const* cmd("[1317196300] DISABLE_SERVICEGROUP_SVC_CHECKS;group");
process_external_command(cmd);
if (svc->checks_enabled)
throw(engine_error() << "disable_servicegroup_svc_checks failed.");
return (0);
}
/**
* Init unit test.
*/
int main(int argc, char** argv) {
unittest utest(argc, argv, &check_disable_servicegroup_svc_checks);
return (utest.run());
}
|
/*=========================================================================
Program: CMake - Cross-Platform Makefile Generator
Module: $RCSfile: CMakeSetupDialog.cxx,v $
Language: C++
Date: $Date: 2012/03/29 17:21:09 $
Version: $Revision: 1.1.1.1 $
Copyright (c) 2002 Kitware, Inc., Insight Consortium. All rights reserved.
See Copyright.txt or http://www.cmake.org/HTML/Copyright.html for details.
This software is distributed WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the above copyright notices for more information.
=========================================================================*/
#include "CMakeSetupDialog.h"
#include <QFileDialog>
#include <QProgressBar>
#include <QMessageBox>
#include <QStatusBar>
#include <QToolButton>
#include <QDialogButtonBox>
#include <QCloseEvent>
#include <QCoreApplication>
#include <QSettings>
#include <QMenu>
#include <QMenuBar>
#include <QDragEnterEvent>
#include <QMimeData>
#include <QUrl>
#include <QShortcut>
#include <QMacInstallDialog.h>
#include "QCMake.h"
#include "QCMakeCacheView.h"
#include "AddCacheEntry.h"
#include "CMakeFirstConfigure.h"
QCMakeThread::QCMakeThread(QObject* p)
: QThread(p), CMakeInstance(NULL)
{
}
QCMake* QCMakeThread::cmakeInstance() const
{
return this->CMakeInstance;
}
void QCMakeThread::run()
{
this->CMakeInstance = new QCMake;
// emit that this cmake thread is ready for use
emit this->cmakeInitialized();
this->exec();
delete this->CMakeInstance;
this->CMakeInstance = NULL;
}
CMakeSetupDialog::CMakeSetupDialog()
: ExitAfterGenerate(true), CacheModified(false), CurrentState(Interrupting)
{
// create the GUI
QSettings settings;
settings.beginGroup("Settings/StartPath");
int h = settings.value("Height", 500).toInt();
int w = settings.value("Width", 700).toInt();
this->resize(w, h);
QWidget* cont = new QWidget(this);
this->setupUi(cont);
this->Splitter->setStretchFactor(0, 3);
this->Splitter->setStretchFactor(1, 1);
this->setCentralWidget(cont);
this->ProgressBar->reset();
this->RemoveEntry->setEnabled(false);
this->AddEntry->setEnabled(false);
bool groupView = settings.value("GroupView", false).toBool();
if(groupView)
{
this->setViewType(2);
this->ViewType->setCurrentIndex(2);
}
QMenu* FileMenu = this->menuBar()->addMenu(tr("&File"));
this->ReloadCacheAction = FileMenu->addAction(tr("&Reload Cache"));
QObject::connect(this->ReloadCacheAction, SIGNAL(triggered(bool)),
this, SLOT(doReloadCache()));
this->DeleteCacheAction = FileMenu->addAction(tr("&Delete Cache"));
QObject::connect(this->DeleteCacheAction, SIGNAL(triggered(bool)),
this, SLOT(doDeleteCache()));
this->ExitAction = FileMenu->addAction(tr("E&xit"));
QObject::connect(this->ExitAction, SIGNAL(triggered(bool)),
this, SLOT(close()));
QMenu* ToolsMenu = this->menuBar()->addMenu(tr("&Tools"));
this->ConfigureAction = ToolsMenu->addAction(tr("&Configure"));
// prevent merging with Preferences menu item on Mac OS X
this->ConfigureAction->setMenuRole(QAction::NoRole);
QObject::connect(this->ConfigureAction, SIGNAL(triggered(bool)),
this, SLOT(doConfigure()));
this->GenerateAction = ToolsMenu->addAction(tr("&Generate"));
QObject::connect(this->GenerateAction, SIGNAL(triggered(bool)),
this, SLOT(doGenerate()));
#if defined(Q_WS_MAC)
this->InstallForCommandLineAction
= ToolsMenu->addAction(tr("&Install For Command Line Use"));
QObject::connect(this->InstallForCommandLineAction, SIGNAL(triggered(bool)),
this, SLOT(doInstallForCommandLine()));
#endif
QMenu* OptionsMenu = this->menuBar()->addMenu(tr("&Options"));
this->SuppressDevWarningsAction = OptionsMenu->addAction(tr("&Suppress dev Warnings (-Wno-dev)"));
this->SuppressDevWarningsAction->setCheckable(true);
QAction* debugAction = OptionsMenu->addAction(tr("&Debug Output"));
debugAction->setCheckable(true);
QObject::connect(debugAction, SIGNAL(toggled(bool)),
this, SLOT(setDebugOutput(bool)));
OptionsMenu->addSeparator();
QAction* expandAction = OptionsMenu->addAction(tr("&Expand Grouped Entries"));
QObject::connect(expandAction, SIGNAL(triggered(bool)),
this->CacheValues, SLOT(expandAll()));
QAction* collapseAction = OptionsMenu->addAction(tr("&Collapse Grouped Entries"));
QObject::connect(collapseAction, SIGNAL(triggered(bool)),
this->CacheValues, SLOT(collapseAll()));
QMenu* HelpMenu = this->menuBar()->addMenu(tr("&Help"));
QAction* a = HelpMenu->addAction(tr("About"));
QObject::connect(a, SIGNAL(triggered(bool)),
this, SLOT(doAbout()));
a = HelpMenu->addAction(tr("Help"));
QObject::connect(a, SIGNAL(triggered(bool)),
this, SLOT(doHelp()));
QShortcut* filterShortcut = new QShortcut(QKeySequence::Find, this);
QObject::connect(filterShortcut, SIGNAL(activated()),
this, SLOT(startSearch()));
this->setAcceptDrops(true);
// get the saved binary directories
QStringList buildPaths = this->loadBuildPaths();
this->BinaryDirectory->addItems(buildPaths);
this->BinaryDirectory->setCompleter(new QCMakeFileCompleter(this, true));
this->SourceDirectory->setCompleter(new QCMakeFileCompleter(this, true));
// fixed pitch font in output window
QFont outputFont("Courier");
this->Output->setFont(outputFont);
this->ErrorFormat.setForeground(QBrush(Qt::red));
// start the cmake worker thread
this->CMakeThread = new QCMakeThread(this);
QObject::connect(this->CMakeThread, SIGNAL(cmakeInitialized()),
this, SLOT(initialize()), Qt::QueuedConnection);
this->CMakeThread->start();
this->enterState(ReadyConfigure);
}
void CMakeSetupDialog::initialize()
{
// now the cmake worker thread is running, lets make our connections to it
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(propertiesChanged(const QCMakePropertyList&)),
this->CacheValues->cacheModel(),
SLOT(setProperties(const QCMakePropertyList&)));
QObject::connect(this->ConfigureButton, SIGNAL(clicked(bool)),
this, SLOT(doConfigure()));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(configureDone(int)),
this, SLOT(finishConfigure(int)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(generateDone(int)),
this, SLOT(finishGenerate(int)));
QObject::connect(this->GenerateButton, SIGNAL(clicked(bool)),
this, SLOT(doGenerate()));
QObject::connect(this->BrowseSourceDirectoryButton, SIGNAL(clicked(bool)),
this, SLOT(doSourceBrowse()));
QObject::connect(this->BrowseBinaryDirectoryButton, SIGNAL(clicked(bool)),
this, SLOT(doBinaryBrowse()));
QObject::connect(this->BinaryDirectory, SIGNAL(editTextChanged(QString)),
this, SLOT(onBinaryDirectoryChanged(QString)));
QObject::connect(this->SourceDirectory, SIGNAL(textChanged(QString)),
this, SLOT(onSourceDirectoryChanged(QString)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(sourceDirChanged(QString)),
this, SLOT(updateSourceDirectory(QString)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(binaryDirChanged(QString)),
this, SLOT(updateBinaryDirectory(QString)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(progressChanged(QString, float)),
this, SLOT(showProgress(QString,float)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(errorMessage(QString)),
this, SLOT(error(QString)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(outputMessage(QString)),
this, SLOT(message(QString)));
QObject::connect(this->ViewType, SIGNAL(currentIndexChanged(int)),
this, SLOT(setViewType(int)));
QObject::connect(this->Search, SIGNAL(textChanged(QString)),
this->CacheValues, SLOT(setSearchFilter(QString)));
QObject::connect(this->CMakeThread->cmakeInstance(),
SIGNAL(generatorChanged(QString)),
this, SLOT(updateGeneratorLabel(QString)));
this->updateGeneratorLabel(QString());
QObject::connect(this->CacheValues->cacheModel(),
SIGNAL(dataChanged(QModelIndex,QModelIndex)),
this, SLOT(setCacheModified()));
QObject::connect(this->CacheValues->selectionModel(),
SIGNAL(selectionChanged(QItemSelection,QItemSelection)),
this, SLOT(selectionChanged()));
QObject::connect(this->RemoveEntry, SIGNAL(clicked(bool)),
this, SLOT(removeSelectedCacheEntries()));
QObject::connect(this->AddEntry, SIGNAL(clicked(bool)),
this, SLOT(addCacheEntry()));
QObject::connect(this->SuppressDevWarningsAction, SIGNAL(triggered(bool)),
this->CMakeThread->cmakeInstance(), SLOT(setSuppressDevWarnings(bool)));
if(!this->SourceDirectory->text().isEmpty() ||
!this->BinaryDirectory->lineEdit()->text().isEmpty())
{
this->onSourceDirectoryChanged(this->SourceDirectory->text());
this->onBinaryDirectoryChanged(this->BinaryDirectory->lineEdit()->text());
}
else
{
this->onBinaryDirectoryChanged(this->BinaryDirectory->lineEdit()->text());
}
}
CMakeSetupDialog::~CMakeSetupDialog()
{
QSettings settings;
settings.beginGroup("Settings/StartPath");
settings.setValue("Height", this->height());
settings.setValue("Width", this->width());
// wait for thread to stop
this->CMakeThread->quit();
this->CMakeThread->wait(2000);
}
void CMakeSetupDialog::doConfigure()
{
if(this->CurrentState == Configuring)
{
// stop configure
doInterrupt();
return;
}
// make sure build directory exists
QString bindir = this->CMakeThread->cmakeInstance()->binaryDirectory();
QDir dir(bindir);
if(!dir.exists())
{
QString message = tr("Build directory does not exist, "
"should I create it?")
+ "\n\n"
+ tr("Directory: ");
message += bindir;
QString title = tr("Create Directory");
QMessageBox::StandardButton btn;
btn = QMessageBox::information(this, title, message,
QMessageBox::Yes | QMessageBox::No);
if(btn == QMessageBox::No)
{
return;
}
dir.mkpath(".");
}
// if no generator, prompt for it and other setup stuff
if(this->CMakeThread->cmakeInstance()->generator().isEmpty())
{
if(!this->setupFirstConfigure())
{
return;
}
}
// remember path
this->addBinaryPath(dir.absolutePath());
this->enterState(Configuring);
this->CacheValues->selectionModel()->clear();
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"setProperties", Qt::QueuedConnection,
Q_ARG(QCMakePropertyList,
this->CacheValues->cacheModel()->properties()));
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"configure", Qt::QueuedConnection);
}
void CMakeSetupDialog::finishConfigure(int err)
{
if(0 == err && !this->CacheValues->cacheModel()->newPropertyCount())
{
this->enterState(ReadyGenerate);
}
else
{
this->enterState(ReadyConfigure);
this->CacheValues->scrollToTop();
}
if(err != 0)
{
QMessageBox::critical(this, tr("Error"),
tr("Error in configuration process, project files may be invalid"),
QMessageBox::Ok);
}
}
void CMakeSetupDialog::finishGenerate(int err)
{
this->enterState(ReadyGenerate);
if(err != 0)
{
QMessageBox::critical(this, tr("Error"),
tr("Error in generation process, project files may be invalid"),
QMessageBox::Ok);
}
}
void CMakeSetupDialog::doInstallForCommandLine()
{
QMacInstallDialog setupdialog(0);
setupdialog.exec();
}
void CMakeSetupDialog::doGenerate()
{
if(this->CurrentState == Generating)
{
// stop generate
doInterrupt();
return;
}
this->enterState(Generating);
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"generate", Qt::QueuedConnection);
}
void CMakeSetupDialog::closeEvent(QCloseEvent* e)
{
// prompt for close if there are unsaved changes, and we're not busy
if(this->CacheModified)
{
QString message = tr("You have changed options but not rebuilt, "
"are you sure you want to exit?");
QString title = tr("Confirm Exit");
QMessageBox::StandardButton btn;
btn = QMessageBox::critical(this, title, message,
QMessageBox::Yes | QMessageBox::No);
if(btn == QMessageBox::No)
{
e->ignore();
}
}
// don't close if we're busy, unless the user really wants to
if(this->CurrentState == Configuring)
{
QString message = "You are in the middle of a Configure.\n"
"If you Exit now the configure information will be lost.\n"
"Are you sure you want to Exit?";
QString title = tr("Confirm Exit");
QMessageBox::StandardButton btn;
btn = QMessageBox::critical(this, title, message,
QMessageBox::Yes | QMessageBox::No);
if(btn == QMessageBox::No)
{
e->ignore();
}
else
{
this->doInterrupt();
}
}
// let the generate finish
if(this->CurrentState == Generating)
{
e->ignore();
}
}
void CMakeSetupDialog::doHelp()
{
QString msg = tr("CMake is used to configure and generate build files for "
"software projects. The basic steps for configuring a project are as "
"follows:\r\n\r\n1. Select the source directory for the project. This should "
"contain the CMakeLists.txt files for the project.\r\n\r\n2. Select the build "
"directory for the project. This is the directory where the project will be "
"built. It can be the same or a different directory than the source "
"directory. For easy clean up, a separate build directory is recommended. "
"CMake will create the directory if it does not exist.\r\n\r\n3. Once the "
"source and binary directories are selected, it is time to press the "
"Configure button. This will cause CMake to read all of the input files and "
"discover all the variables used by the project. The first time a variable "
"is displayed it will be in Red. Users should inspect red variables making "
"sure the values are correct. For some projects the Configure process can "
"be iterative, so continue to press the Configure button until there are no "
"longer red entries.\r\n\r\n4. Once there are no longer red entries, you "
"should click the Generate button. This will write the build files to the build "
"directory.");
QDialog dialog;
QFontMetrics met(this->font());
int msgWidth = met.width(msg);
dialog.setMinimumSize(msgWidth/15,20);
dialog.setWindowTitle(tr("Help"));
QVBoxLayout* l = new QVBoxLayout(&dialog);
QLabel* lab = new QLabel(&dialog);
lab->setText(msg);
lab->setWordWrap(true);
QDialogButtonBox* btns = new QDialogButtonBox(QDialogButtonBox::Ok,
Qt::Horizontal, &dialog);
QObject::connect(btns, SIGNAL(accepted()), &dialog, SLOT(accept()));
l->addWidget(lab);
l->addWidget(btns);
dialog.exec();
}
void CMakeSetupDialog::doInterrupt()
{
this->enterState(Interrupting);
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"interrupt", Qt::QueuedConnection);
}
void CMakeSetupDialog::doSourceBrowse()
{
QString dir = QFileDialog::getExistingDirectory(this,
tr("Enter Path to Source"), this->SourceDirectory->text());
if(!dir.isEmpty())
{
this->setSourceDirectory(dir);
}
}
void CMakeSetupDialog::updateSourceDirectory(const QString& dir)
{
if(this->SourceDirectory->text() != dir)
{
this->SourceDirectory->blockSignals(true);
this->SourceDirectory->setText(dir);
this->SourceDirectory->blockSignals(false);
}
}
void CMakeSetupDialog::updateBinaryDirectory(const QString& dir)
{
if(this->BinaryDirectory->currentText() != dir)
{
this->BinaryDirectory->blockSignals(true);
this->BinaryDirectory->setEditText(dir);
this->BinaryDirectory->blockSignals(false);
}
}
void CMakeSetupDialog::doBinaryBrowse()
{
QString dir = QFileDialog::getExistingDirectory(this,
tr("Enter Path to Build"), this->BinaryDirectory->currentText());
if(!dir.isEmpty() && dir != this->BinaryDirectory->currentText())
{
this->setBinaryDirectory(dir);
}
}
void CMakeSetupDialog::setBinaryDirectory(const QString& dir)
{
this->BinaryDirectory->setEditText(dir);
}
void CMakeSetupDialog::onSourceDirectoryChanged(const QString& dir)
{
this->Output->clear();
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"setSourceDirectory", Qt::QueuedConnection, Q_ARG(QString, dir));
}
void CMakeSetupDialog::onBinaryDirectoryChanged(const QString& dir)
{
this->CacheModified = false;
this->CacheValues->cacheModel()->clear();
this->Output->clear();
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"setBinaryDirectory", Qt::QueuedConnection, Q_ARG(QString, dir));
}
void CMakeSetupDialog::setSourceDirectory(const QString& dir)
{
this->SourceDirectory->setText(dir);
}
void CMakeSetupDialog::showProgress(const QString& /*msg*/, float percent)
{
this->ProgressBar->setValue(qRound(percent * 100));
}
void CMakeSetupDialog::error(const QString& message)
{
this->Output->setCurrentCharFormat(this->ErrorFormat);
this->Output->append(message);
}
void CMakeSetupDialog::message(const QString& message)
{
this->Output->setCurrentCharFormat(this->MessageFormat);
this->Output->append(message);
}
void CMakeSetupDialog::setEnabledState(bool enabled)
{
// disable parts of the GUI during configure/generate
this->CacheValues->cacheModel()->setEditEnabled(enabled);
this->SourceDirectory->setEnabled(enabled);
this->BrowseSourceDirectoryButton->setEnabled(enabled);
this->BinaryDirectory->setEnabled(enabled);
this->BrowseBinaryDirectoryButton->setEnabled(enabled);
this->ReloadCacheAction->setEnabled(enabled);
this->DeleteCacheAction->setEnabled(enabled);
this->ExitAction->setEnabled(enabled);
this->ConfigureAction->setEnabled(enabled);
this->AddEntry->setEnabled(enabled);
this->RemoveEntry->setEnabled(false); // let selection re-enable it
}
bool CMakeSetupDialog::setupFirstConfigure()
{
CMakeFirstConfigure dialog;
// initialize dialog and restore saved settings
// add generators
dialog.setGenerators(this->CMakeThread->cmakeInstance()->availableGenerators());
// restore from settings
dialog.loadFromSettings();
if(dialog.exec() == QDialog::Accepted)
{
dialog.saveToSettings();
this->CMakeThread->cmakeInstance()->setGenerator(dialog.getGenerator());
QCMakeCacheModel* m = this->CacheValues->cacheModel();
if(dialog.compilerSetup())
{
QString fortranCompiler = dialog.getFortranCompiler();
if(!fortranCompiler.isEmpty())
{
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_Fortran_COMPILER",
"Fortran compiler.", fortranCompiler, false);
}
QString cxxCompiler = dialog.getCXXCompiler();
if(!cxxCompiler.isEmpty())
{
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_CXX_COMPILER",
"CXX compiler.", cxxCompiler, false);
}
QString cCompiler = dialog.getCCompiler();
if(!cCompiler.isEmpty())
{
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_C_COMPILER",
"C compiler.", cCompiler, false);
}
}
else if(dialog.crossCompilerSetup())
{
QString toolchainFile = dialog.crossCompilerToolChainFile();
if(!toolchainFile.isEmpty())
{
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_TOOLCHAIN_FILE",
"Cross Compile ToolChain File", toolchainFile, false);
}
else
{
QString fortranCompiler = dialog.getFortranCompiler();
if(!fortranCompiler.isEmpty())
{
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_Fortran_COMPILER",
"Fortran compiler.", fortranCompiler, false);
}
QString mode = dialog.getCrossIncludeMode();
m->insertProperty(QCMakeProperty::STRING, "CMAKE_FIND_ROOT_PATH_MODE_INCLUDE",
"CMake Find Include Mode", mode, false);
mode = dialog.getCrossLibraryMode();
m->insertProperty(QCMakeProperty::STRING, "CMAKE_FIND_ROOT_PATH_MODE_LIBRARY",
"CMake Find Library Mode", mode, false);
mode = dialog.getCrossProgramMode();
m->insertProperty(QCMakeProperty::STRING, "CMAKE_FIND_ROOT_PATH_MODE_PROGRAM",
"CMake Find Program Mode", mode, false);
QString rootPath = dialog.getCrossRoot();
m->insertProperty(QCMakeProperty::PATH, "CMAKE_FIND_ROOT_PATH",
"CMake Find Root Path", rootPath, false);
QString systemName = dialog.getSystemName();
m->insertProperty(QCMakeProperty::STRING, "CMAKE_SYSTEM_NAME",
"CMake System Name", systemName, false);
QString cxxCompiler = dialog.getCXXCompiler();
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_CXX_COMPILER",
"CXX compiler.", cxxCompiler, false);
QString cCompiler = dialog.getCCompiler();
m->insertProperty(QCMakeProperty::FILEPATH, "CMAKE_C_COMPILER",
"C compiler.", cCompiler, false);
}
}
return true;
}
return false;
}
void CMakeSetupDialog::updateGeneratorLabel(const QString& gen)
{
QString str = tr("Current Generator: ");
if(gen.isEmpty())
{
str += tr("None");
}
else
{
str += gen;
}
this->Generator->setText(str);
}
void CMakeSetupDialog::doReloadCache()
{
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"reloadCache", Qt::QueuedConnection);
}
void CMakeSetupDialog::doDeleteCache()
{
QString title = tr("Delete Cache");
QString message = "Are you sure you want to delete the cache?";
QMessageBox::StandardButton btn;
btn = QMessageBox::information(this, title, message,
QMessageBox::Yes | QMessageBox::No);
if(btn == QMessageBox::No)
{
return;
}
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"deleteCache", Qt::QueuedConnection);
}
void CMakeSetupDialog::doAbout()
{
QString msg = "CMake\nwww.cmake.org";
QDialog dialog;
dialog.setWindowTitle(tr("About"));
QVBoxLayout* l = new QVBoxLayout(&dialog);
QLabel* lab = new QLabel(&dialog);
l->addWidget(lab);
lab->setText(msg);
lab->setWordWrap(true);
QDialogButtonBox* btns = new QDialogButtonBox(QDialogButtonBox::Ok,
Qt::Horizontal, &dialog);
QObject::connect(btns, SIGNAL(accepted()), &dialog, SLOT(accept()));
l->addWidget(btns);
dialog.exec();
}
void CMakeSetupDialog::setExitAfterGenerate(bool b)
{
this->ExitAfterGenerate = b;
}
void CMakeSetupDialog::addBinaryPath(const QString& path)
{
QString cleanpath = QDir::cleanPath(path);
// update UI
this->BinaryDirectory->blockSignals(true);
int idx = this->BinaryDirectory->findText(cleanpath);
if(idx != -1)
{
this->BinaryDirectory->removeItem(idx);
}
this->BinaryDirectory->insertItem(0, cleanpath);
this->BinaryDirectory->setCurrentIndex(0);
this->BinaryDirectory->blockSignals(false);
// save to registry
QStringList buildPaths = this->loadBuildPaths();
buildPaths.removeAll(cleanpath);
buildPaths.prepend(cleanpath);
this->saveBuildPaths(buildPaths);
}
void CMakeSetupDialog::dragEnterEvent(QDragEnterEvent* e)
{
if(!(this->CurrentState == ReadyConfigure ||
this->CurrentState == ReadyGenerate))
{
e->ignore();
return;
}
const QMimeData* dat = e->mimeData();
QList<QUrl> urls = dat->urls();
QString file = urls.count() ? urls[0].toLocalFile() : QString();
if(!file.isEmpty() &&
(file.endsWith("CMakeCache.txt", Qt::CaseInsensitive) ||
file.endsWith("CMakeLists.txt", Qt::CaseInsensitive) ) )
{
e->accept();
}
else
{
e->ignore();
}
}
void CMakeSetupDialog::dropEvent(QDropEvent* e)
{
if(!(this->CurrentState == ReadyConfigure ||
this->CurrentState == ReadyGenerate))
{
return;
}
const QMimeData* dat = e->mimeData();
QList<QUrl> urls = dat->urls();
QString file = urls.count() ? urls[0].toLocalFile() : QString();
if(file.endsWith("CMakeCache.txt", Qt::CaseInsensitive))
{
QFileInfo info(file);
if(this->CMakeThread->cmakeInstance()->binaryDirectory() != info.absolutePath())
{
this->setBinaryDirectory(info.absolutePath());
}
}
else if(file.endsWith("CMakeLists.txt", Qt::CaseInsensitive))
{
QFileInfo info(file);
if(this->CMakeThread->cmakeInstance()->binaryDirectory() != info.absolutePath())
{
this->setSourceDirectory(info.absolutePath());
this->setBinaryDirectory(info.absolutePath());
}
}
}
QStringList CMakeSetupDialog::loadBuildPaths()
{
QSettings settings;
settings.beginGroup("Settings/StartPath");
QStringList buildPaths;
for(int i=0; i<10; i++)
{
QString p = settings.value(QString("WhereBuild%1").arg(i)).toString();
if(!p.isEmpty())
{
buildPaths.append(p);
}
}
return buildPaths;
}
void CMakeSetupDialog::saveBuildPaths(const QStringList& paths)
{
QSettings settings;
settings.beginGroup("Settings/StartPath");
int num = paths.count();
if(num > 10)
{
num = 10;
}
for(int i=0; i<num; i++)
{
settings.setValue(QString("WhereBuild%1").arg(i), paths[i]);
}
}
void CMakeSetupDialog::setCacheModified()
{
this->CacheModified = true;
this->enterState(ReadyConfigure);
}
void CMakeSetupDialog::removeSelectedCacheEntries()
{
QModelIndexList idxs = this->CacheValues->selectionModel()->selectedRows();
QList<QPersistentModelIndex> pidxs;
foreach(QModelIndex i, idxs)
{
pidxs.append(i);
}
foreach(QPersistentModelIndex pi, pidxs)
{
this->CacheValues->model()->removeRow(pi.row(), pi.parent());
}
}
void CMakeSetupDialog::selectionChanged()
{
QModelIndexList idxs = this->CacheValues->selectionModel()->selectedRows();
if(idxs.count() &&
(this->CurrentState == ReadyConfigure ||
this->CurrentState == ReadyGenerate) )
{
this->RemoveEntry->setEnabled(true);
}
else
{
this->RemoveEntry->setEnabled(false);
}
}
void CMakeSetupDialog::enterState(CMakeSetupDialog::State s)
{
if(s == this->CurrentState)
{
return;
}
this->CurrentState = s;
if(s == Interrupting)
{
this->ConfigureButton->setEnabled(false);
this->GenerateButton->setEnabled(false);
}
else if(s == Configuring)
{
this->Output->clear();
this->setEnabledState(false);
this->GenerateButton->setEnabled(false);
this->GenerateAction->setEnabled(false);
this->ConfigureButton->setText(tr("&Stop"));
}
else if(s == Generating)
{
this->CacheModified = false;
this->setEnabledState(false);
this->ConfigureButton->setEnabled(false);
this->GenerateAction->setEnabled(false);
this->GenerateButton->setText(tr("&Stop"));
}
else if(s == ReadyConfigure)
{
this->ProgressBar->reset();
this->setEnabledState(true);
this->GenerateButton->setEnabled(false);
this->GenerateAction->setEnabled(false);
this->ConfigureButton->setEnabled(true);
this->ConfigureButton->setText(tr("&Configure"));
this->GenerateButton->setText(tr("&Generate"));
}
else if(s == ReadyGenerate)
{
this->ProgressBar->reset();
this->setEnabledState(true);
this->GenerateButton->setEnabled(true);
this->GenerateAction->setEnabled(true);
this->ConfigureButton->setEnabled(true);
this->ConfigureButton->setText(tr("&Configure"));
this->GenerateButton->setText(tr("&Generate"));
}
}
void CMakeSetupDialog::addCacheEntry()
{
QDialog dialog(this);
dialog.resize(400, 200);
dialog.setWindowTitle(tr("Add Cache Entry"));
QVBoxLayout* l = new QVBoxLayout(&dialog);
AddCacheEntry* w = new AddCacheEntry(&dialog);
QDialogButtonBox* btns = new QDialogButtonBox(
QDialogButtonBox::Ok | QDialogButtonBox::Cancel,
Qt::Horizontal, &dialog);
QObject::connect(btns, SIGNAL(accepted()), &dialog, SLOT(accept()));
QObject::connect(btns, SIGNAL(rejected()), &dialog, SLOT(reject()));
l->addWidget(w);
l->addStretch();
l->addWidget(btns);
if(QDialog::Accepted == dialog.exec())
{
QCMakeCacheModel* m = this->CacheValues->cacheModel();
m->insertProperty(w->type(), w->name(), w->description(), w->value(), false);
}
}
void CMakeSetupDialog::startSearch()
{
this->Search->setFocus(Qt::OtherFocusReason);
this->Search->selectAll();
}
void CMakeSetupDialog::setDebugOutput(bool flag)
{
QMetaObject::invokeMethod(this->CMakeThread->cmakeInstance(),
"setDebugOutput", Qt::QueuedConnection, Q_ARG(bool, flag));
}
void CMakeSetupDialog::setViewType(int v)
{
if(v == 0) // simple view
{
this->CacheValues->cacheModel()->setViewType(QCMakeCacheModel::FlatView);
this->CacheValues->setRootIsDecorated(false);
this->CacheValues->setShowAdvanced(false);
}
else if(v == 1) // advanced view
{
this->CacheValues->cacheModel()->setViewType(QCMakeCacheModel::FlatView);
this->CacheValues->setRootIsDecorated(false);
this->CacheValues->setShowAdvanced(true);
}
else if(v == 2) // grouped view
{
this->CacheValues->cacheModel()->setViewType(QCMakeCacheModel::GroupView);
this->CacheValues->setRootIsDecorated(true);
this->CacheValues->setShowAdvanced(true);
}
QSettings settings;
settings.beginGroup("Settings/StartPath");
settings.setValue("GroupView", v == 2);
}
|
; A014900: a(1)=1, a(n)=17*a(n-1)+n.
; 1,19,326,5546,94287,1602885,27249052,463233892,7874976173,133874594951,2275868114178,38689757941038,657725884997659,11181340044960217,190082780764323704,3231407272993502984,54933923640889550745,933876701895122362683,15875903932217080165630,269890366847690362815730,4588136236410736167867431,77998316018982514853746349,1325971372322702752513687956,22541513329485946792732695276,383205726601261095476455819717,6514497352221438623099748935215,110746454987764456592695731898682
add $0,1
lpb $0
sub $0,1
add $2,1
mul $2,17
add $1,$2
lpe
div $1,17
mov $0,$1
|
.inesprg 1 ; 1x 16KB PRG code
.ineschr 1 ; 1x 8KB CHR data
.inesmap 0 ; mapper 0 = NROM, no bank swapping
.inesmir 1 ; VERT mirroring for HORIZ scrolling
;;;;;;;;;;;;;;;
;; DECLARE SOME VARIABLES HERE
.rsset $0000 ;;start variables at ram location 0
scroll .rs 1 ; horizontal scroll count
nametable .rs 1 ; which nametable to use, 0 or 1
columnLow .rs 1 ; low byte of new column address
columnHigh .rs 1 ; high byte of new column address
;;;;;;;;;;;;
.bank 0
.org $C000
RESET:
SEI ; disable IRQs
CLD ; disable decimal mode
LDX #$40
STX $4017 ; disable APU frame IRQ
LDX #$FF
TXS ; Set up stack
INX ; now X = 0
STX $2000 ; disable NMI
STX $2001 ; disable rendering
STX $4010 ; disable DMC IRQs
vblankwait1: ; First wait for vblank to make sure PPU is ready
BIT $2002
BPL vblankwait1
clrmem:
LDA #$00
STA $0000, x
STA $0100, x
STA $0300, x
STA $0400, x
STA $0500, x
STA $0600, x
STA $0700, x
LDA #$FE
STA $0200, x
INX
BNE clrmem
vblankwait2: ; Second wait for vblank, PPU is ready after this
BIT $2002
BPL vblankwait2
LoadPalettes:
LDA $2002 ; read PPU status to reset the high/low latch
LDA #$3F
STA $2006 ; write the high byte of $3F00 address
LDA #$00
STA $2006 ; write the low byte of $3F00 address
LDX #$00 ; start out at 0
LoadPalettesLoop:
LDA palette, x ; load data from address (palette + the value in x)
; 1st time through loop it will load palette+0
; 2nd time through loop it will load palette+1
; 3rd time through loop it will load palette+2
; etc
STA $2007 ; write to PPU
INX ; X = X + 1
CPX #$20 ; Compare X to hex $10, decimal 16 - copying 16 bytes = 4 sprites
BNE LoadPalettesLoop ; Branch to LoadPalettesLoop if compare was Not Equal to zero
; if compare was equal to 32, keep going down
LoadSprites:
LDX #$00 ; start at 0
LoadSpritesLoop:
LDA sprites, x ; load data from address (sprites + x)
STA $0200, x ; store into RAM address ($0200 + x)
INX ; X = X + 1
CPX #$10 ; Compare X to hex $20, decimal 16
BNE LoadSpritesLoop ; Branch to LoadSpritesLoop if compare was Not Equal to zero
; if compare was equal to 16, keep going down
FillNametables:
LDA $2002 ; read PPU status to reset the high/low latch
LDA #$20
STA $2006 ; write the high byte of $2000 address (nametable 0)
LDA #$00
STA $2006 ; write the low byte of $2000 address
LDY #$08
LDX #$00 ; fill 256 x 8 bytes = 2KB, both nametables all full
LDA #$7F
FillNametablesLoop:
STA $2007
DEX
BNE FillNametablesLoop
DEY
BNE FillNametablesLoop
FillAttrib0:
LDA $2002 ; read PPU status to reset the high/low latch
LDA #$23
STA $2006 ; write the high byte of $23C0 address (nametable 0 attributes)
LDA #$C0
STA $2006 ; write the low byte of $23C0 address
LDX #$40 ; fill 64 bytes
LDA #$00
FillAttrib0Loop:
STA $2007
DEX
BNE FillAttrib0Loop
FillAttrib1:
LDA $2002 ; read PPU status to reset the high/low latch
LDA #$27
STA $2006 ; write the high byte of $27C0 address (nametable 1 attributes)
LDA #$C0
STA $2006 ; write the low byte of $27C0 address
LDX #$40 ; fill 64 bytes
LDA #$FF
FillAttrib1Loop:
STA $2007
DEX
BNE FillAttrib1Loop
LDA #%10010000 ; enable NMI, sprites from Pattern Table 0, background from Pattern Table 1
STA $2000
LDA #%00011110 ; enable sprites, enable background, no clipping on left side
STA $2001
Forever:
JMP Forever ;jump back to Forever, infinite loop
NMI:
INC scroll ; add one to our scroll variable each frame
NTSwapCheck:
LDA scroll ; check if the scroll just wrapped from 255 to 0
BNE NTSwapCheckDone
NTSwap:
LDA nametable ; load current nametable number (0 or 1)
EOR #$01 ; exclusive OR of bit 0 will flip that bit
STA nametable ; so if nametable was 0, now 1
; if nametable was 1, now 0
NTSwapCheckDone:
NewColumnCheck:
LDA scroll
AND #%00000111 ; throw away higher bits
BNE NewColumnCheckDone ; done if lower bits != 0
JSR DrawNewColumn
NewColumnCheckDone:
LDA #$00
STA $2003
LDA #$02
STA $4014 ; sprite DMA from $0200
; run other game graphics updating code here
LDA #$00
STA $2006 ; clean up PPU address registers
STA $2006
LDA scroll
STA $2005 ; write the horizontal scroll count register
LDA #$00 ; no vertical scrolling
STA $2005
;;This is the PPU clean up section, so rendering the next frame starts properly.
LDA #%10010000 ; enable NMI, sprites from Pattern Table 0, background from Pattern Table 1
ORA nametable ; select correct nametable for bit 0
STA $2000
LDA #%00011110 ; enable sprites, enable background, no clipping on left side
STA $2001
; run normal game engine code here
; reading from controllers, etc
RTI ; return from interrupt
DrawNewColumn:
LDA scroll ; calculate new column address using scroll register
LSR A
LSR A
LSR A ; shift right 3 times = divide by 8
STA columnLow ; $00 to $1F, screen is 32 tiles wide
LDA nametable ; calculate new column address using current nametable
EOR #$01 ; invert low bit, A = $00 or $01
ASL A ; shift up, A = $00 or $02
ASL A ; $00 or $04
CLC
ADC #$20 ; add high byte of nametable base address ($2000)
STA columnHigh ; now address = $20 or $24 for nametable 0 or 1
DrawColumn:
LDA #%10010000 ; enable NMI, sprites from Pattern Table 0, background from Pattern Table 1
ORA nametable ; select correct nametable for bit 0
ORA #%00000100 ; set to increment +32 mode
STA $2000
LDA $2002 ; read PPU status to reset the high/low latch
LDA columnHigh
STA $2006 ; write the high byte of column address
LDA columnLow
STA $2006 ; write the low byte of column address
LDX #$1E ; copy 30 bytes
LDY #$00
DrawColumnLoop:
LDA columnData, y
STA $2007
INY
DEX
BNE DrawColumnLoop
RTS
;;;;;;;;;;;;;;
.bank 1
.org $E000
palette:
.db $22,$29,$1A,$0F, $22,$36,$17,$0F, $22,$30,$21,$0F, $22,$27,$17,$0F ;;background palette
.db $22,$1C,$15,$14, $22,$02,$38,$3C, $22,$1C,$15,$14, $22,$02,$38,$3C ;;sprite palette
sprites:
;vert tile attr horiz
.db $80, $32, $00, $80 ;sprite 0
.db $80, $33, $00, $88 ;sprite 1
.db $88, $34, $00, $80 ;sprite 2
.db $88, $35, $00, $88 ;sprite 3
columnData:
.db $00, $01, $02, $03, $04, $05, $06, $07, $08, $09, $0A, $0B, $0C, $0D, $0E, $0F
.db $10, $11, $12, $13, $14, $15, $16, $17, $18, $19, $1A, $1B, $1C, $1D
.org $FFFA ;first of the three vectors starts here
.dw NMI ;when an NMI happens (once per frame if enabled) the
;processor will jump to the label NMI:
.dw RESET ;when the processor first turns on or is reset, it will jump
;to the label RESET:
.dw 0 ;external interrupt IRQ is not used in this tutorial
;;;;;;;;;;;;;;
.bank 2
.org $0000
.incbin "mario.chr" ;includes 8KB graphics file from SMB1 |
; Blob dropping code V2.00 1992 Tony Tebby
;
; d0 c s byte offset / composite colour
; d1 c s row offset
; d2 c s horizontal pattern repeat / horizontal offset
; d3 c s vertical pattern repeat / vertical offset
; d4 s blob mask
; d5 c s sprite word counter / horizontal mask (high word)
; d6 c s row counter
; d7 c p right shift (low word) / 16-shift (high word)
;
; a0 s
; a1 s running pointer to pattern
; a2 c s pointer to pattern definition / pointer to blob
; a3 c s new pointer to screen
; a4 s pointer to colour pattern
; a5 c s pointer to blob pointers / pointer to pattern mask
; a6 c p address increment of screen
section driver
xdef bl_drop
xref.s pt.spxlw
bl_drop
exg a2,a5 get blob and pattern in logical order
addq.l #4,a2 skip null pointer to colour pattern
add.l (a2),a2 set blob address
add.w d0,a2
move.l d5,-(sp) save pointers
addq.l #4,a5 skip pattern form
moveq #0,d4
move.w (a5)+,d4 horizontal repeat
moveq #pt.spxlw,d0
lsr.w d0,d4 in long words
ext.l d2
divu d4,d2 horizontal offset
move.l d2,d5 save offset in msw d5
move.w d4,d2
lsl.l #2,d4 length of line
move.w (a5)+,d0 vertical repeat
addq.l #4,a5 skip zeros
move.l a5,a4
add.l (a5)+,a4 set colour pattern pointer
tst.l (a5) is there a mask?
add.l (a5),a5 (set pattern mask pointer)
beq.l solid no, do solid colour code
ext.l d3 what is here?
add.l d3,d1
divu d0,d1 vertical offset
swap d1 ... is remainder
move.w d1,d5 save offset in lsw d5
mulu d4,d1 offset to first line in pattern
move.w d0,d3
swap d3
move.w d4,d3 d3 Ny (msw) Dy (lsw)
swap d2
moveq #4,d4 ; 4 bytes per long word
mulu d2,d4
move.w d4,d2 d2 Nx (msw) Dx (lsw)
movem.l d2/d3/a4/a5,-(sp) save counters and pattern pointer
add.w d1,a4 offset pointers
add.w d1,a5
move.l a4,a0
move.l a5,a1
swap d2
swap d3
sub.w d5,d3 adjust y counter by offset
swap d5
sub.w d5,d2 and x counter
move.w d2,-(sp)
stk_ox equ 0
stk_nx equ 2
stk_dx equ 4
stk_ny equ 6
stk_dy equ 8
stk_cp equ $a
stk_pm equ $e
stk_d5 equ $12
frame equ $16
bl_line
add.w stk_dx(sp),a0 set start of pattern
add.w stk_dx(sp),a1
move.l stk_d5(sp),d5 set counter
moveq #0,d4 preset mask
long_word
movep.w 0(a2),d4 set mask - blob
addq.l #4,a2 move pointer on
last_word
ror.l d7,d4
movep.w 0(a1),d0 and set the composite mask
and.w d0,d4
swap d5 check if this word to be dropped in
lsl.w #1,d5
bcs.s next_word
movep.w 1(a0),d1 red pattern
and.w d4,d1 mask pattern (red first)
movep.w 1(a3),d0 get current background from screen
not.w d4
and.w d4,d0
not.w d4
eor.w d1,d0
movep.w 0(a0),d1 now green
and.w d4,d1
not.w d4
movep.w d0,1(a3) replace red
movep.w 0(a3),d0 and get green
and.w d4,d0
eor.w d1,d0
movep.w d0,0(a3) replace green
not.w d4
addq.l #4,a3 move screen address on
next_word
addq.l #4,a0 and colour pattern
addq.l #4,a1 and pattern mask
swap d7
lsr.l d7,d4 restore mask for next go
swap d7
subq.w #1,d2 decrement pointer to pattern
bgt.s next_d5
move.w stk_nx(sp),d2 reset horizontal pattern count
move.l a4,a0 and pointers
move.l a5,a1
next_d5
swap d5
subq.w #1,d5 next long word
bgt.s long_word ... there is another one
blt.s next_line ... all gone
clr.w d4 no more blob definition
bra.s last_word
next_line
move.w stk_ox(sp),d2 reset x counter
add.w a6,a3 move address to next line
add.w stk_dy(sp),a4 and pattern pointer
add.w stk_dy(sp),a5
subq.w #1,d3
bgt.s next_a1
move.w stk_ny(sp),d3 reset vertical pattern count
move.l stk_cp(sp),a4 and pointers
move.l stk_pm(sp),a5
next_a1
move.l a4,a0
move.l a5,a1
dbra d6,bl_line next line
add.w #frame,sp remove counters
rts
; Come here if there's no mask: the pattern is solid
solid
ext.l d3 what is here?
add.l d3,d1
divu d0,d1 vertical offset
swap d1 ... is remainder
move.w d1,d5 save offset in lsw d5
mulu d4,d1 offset to first line in pattern
move.w d0,d3
swap d3
move.w d4,d3 d3 Ny (msw) Dy (lsw)
swap d2
moveq #4,d4
mulu d2,d4
move.w d4,d2 d2 Nx (msw) Dx (lsw)
movem.l d2/d3/a4/a5,-(sp) save counters and pattern pointer
add.w d1,a4 offset pointers
move.l a4,a0
swap d2
swap d3
sub.w d5,d3 adjust y counter by offset
swap d5
sub.w d5,d2 and x counter
move.w d2,-(sp)
sbl_line
add.w stk_dx(sp),a0 set start of pattern
move.l stk_d5(sp),d5 set counter
moveq #0,d4 preset mask
slong_word
movep.w 0(a2),d4 set mask - blob
addq.l #4,a2 move pointer on
slast_word
ror.l d7,d4
swap d5 check if this word to be dropped in
lsl.w #1,d5
bcs.s snext_word
movep.w 1(a0),d1 red pattern
and.w d4,d1 mask pattern (red first)
movep.w 1(a3),d0 get current background from screen
not.w d4
and.w d4,d0
not.w d4
eor.w d1,d0
movep.w 0(a0),d1 now green
and.w d4,d1
not.w d4
movep.w d0,1(a3) replace red
movep.w 0(a3),d0 and get green
and.w d4,d0
eor.w d1,d0
movep.w d0,0(a3) replace green
not.w d4
addq.l #4,a3 move screen address on
snext_word
addq.l #4,a0 and colour pattern
swap d7
lsr.l d7,d4 restore mask for next go
swap d7
subq.w #1,d2 decrement pointer to pattern
bgt.s snext_d5
move.w stk_nx(sp),d2 reset horizontal pattern count
move.l a4,a0 and pointers
snext_d5
swap d5
subq.w #1,d5 next long word
bgt.s slong_word ... there is another one
blt.s snext_line ... all gone
clr.w d4 no more blob definition
bra.s slast_word
snext_line
move.w stk_ox(sp),d2 reset x counter
add.w a6,a3 move address to next line
add.w stk_dy(sp),a4 and pattern pointer
subq.w #1,d3
bgt.s snext_a1
move.w stk_ny(sp),d3 reset vertical pattern count
move.l stk_cp(sp),a4 and pointers
snext_a1
move.l a4,a0
dbra d6,sbl_line next line
add.w #frame,sp remove counters
rts
end
|
SECTION code_driver
SECTION code_driver_terminal_output
PUBLIC console_01_output_stdio_msg_putc
EXTERN OTERM_MSG_PUTC, l_jpix
console_01_output_stdio_msg_putc:
; E' = char
; BC' = number > 0
; HL = number > 0
;
; return:
;
; HL = number of bytes successfully output
; carry set if error
exx
ld hl,0
putc_loop:
ld a,e
exx
ld c,a ; c = char
ld a,OTERM_MSG_PUTC
call l_jpix
exx
cpi ; hl++, bc--
jp pe, putc_loop
or a
ret
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r13
push %r9
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0xf57b, %rax
nop
nop
nop
nop
sub %r9, %r9
mov $0x6162636465666768, %r13
movq %r13, (%rax)
nop
nop
nop
nop
dec %r11
lea addresses_D_ht+0xbabb, %rsi
lea addresses_WC_ht+0x39fb, %rdi
nop
nop
nop
nop
nop
sub $28506, %r10
mov $5, %rcx
rep movsw
nop
nop
nop
nop
and $20865, %rdi
lea addresses_A_ht+0x1d45b, %rdi
clflush (%rdi)
nop
nop
add %rcx, %rcx
mov $0x6162636465666768, %r13
movq %r13, %xmm3
vmovups %ymm3, (%rdi)
nop
cmp %rdi, %rdi
lea addresses_normal_ht+0x16ebb, %rax
clflush (%rax)
add $27523, %r9
movups (%rax), %xmm4
vpextrq $1, %xmm4, %rdi
nop
nop
nop
nop
inc %rdi
lea addresses_WT_ht+0x92bb, %rsi
lea addresses_normal_ht+0x1b3bb, %rdi
clflush (%rsi)
nop
add %rax, %rax
mov $97, %rcx
rep movsl
nop
nop
xor $64632, %rax
lea addresses_UC_ht+0x1a3a5, %rsi
lea addresses_WC_ht+0x6dcb, %rdi
nop
nop
inc %rax
mov $55, %rcx
rep movsb
nop
nop
nop
nop
sub $16114, %r13
lea addresses_normal_ht+0x1b5e3, %rcx
clflush (%rcx)
nop
add %r13, %r13
movl $0x61626364, (%rcx)
nop
add $47979, %r13
lea addresses_WT_ht+0x70bb, %rsi
lea addresses_D_ht+0x1277b, %rdi
nop
dec %r9
mov $80, %rcx
rep movsw
nop
nop
nop
cmp %r11, %r11
lea addresses_WC_ht+0x1eebb, %rsi
lea addresses_WT_ht+0x44bb, %rdi
clflush (%rdi)
nop
nop
nop
nop
sub %r13, %r13
mov $1, %rcx
rep movsq
nop
add $26588, %rcx
lea addresses_D_ht+0xd724, %rsi
lea addresses_A_ht+0x15caf, %rdi
nop
inc %r13
mov $71, %rcx
rep movsq
nop
nop
nop
nop
nop
and $42179, %rax
lea addresses_A_ht+0xecbb, %rsi
nop
nop
nop
xor $35193, %r13
mov (%rsi), %rdi
nop
nop
nop
nop
nop
xor %rdi, %rdi
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r13
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r15
push %r9
push %rax
push %rbp
push %rdi
push %rdx
// Store
lea addresses_PSE+0x9dbb, %rdi
clflush (%rdi)
nop
nop
nop
nop
inc %rbp
mov $0x5152535455565758, %r11
movq %r11, (%rdi)
nop
nop
nop
cmp %rax, %rax
// Faulty Load
lea addresses_WC+0x78bb, %r9
nop
nop
nop
nop
nop
cmp $39610, %rdx
movb (%r9), %al
lea oracles, %r15
and $0xff, %rax
shlq $12, %rax
mov (%r15,%rax,1), %rax
pop %rdx
pop %rdi
pop %rbp
pop %rax
pop %r9
pop %r15
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_WC', 'same': False, 'AVXalign': True, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_PSE', 'same': False, 'AVXalign': False, 'congruent': 8}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_WC', 'same': True, 'AVXalign': False, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_D_ht', 'congruent': 8}, 'dst': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 3}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 9}, 'dst': {'same': False, 'type': 'addresses_normal_ht', 'congruent': 7}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_UC_ht', 'congruent': 1}, 'dst': {'same': True, 'type': 'addresses_WC_ht', 'congruent': 3}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 1}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 10}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 6}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_WC_ht', 'congruent': 9}, 'dst': {'same': False, 'type': 'addresses_WT_ht', 'congruent': 10}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_D_ht', 'congruent': 0}, 'dst': {'same': False, 'type': 'addresses_A_ht', 'congruent': 2}}
{'OP': 'LOAD', 'src': {'size': 8, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
; A157861: a(n) = 3600*n^2 + n.
; 3601,14402,32403,57604,90005,129606,176407,230408,291609,360010,435611,518412,608413,705614,810015,921616,1040417,1166418,1299619,1440020,1587621,1742422,1904423,2073624,2250025,2433626,2624427,2822428,3027629,3240030,3459631,3686432,3920433,4161634,4410035,4665636,4928437,5198438,5475639,5760040,6051641,6350442,6656443,6969644,7290045,7617646,7952447,8294448,8643649,9000050,9363651,9734452,10112453,10497654,10890055,11289656,11696457,12110458,12531659,12960060,13395661,13838462,14288463
seq $0,157862 ; a(n) = 1728000*n + 240.
pow $0,2
sub $0,2986813497600
div $0,829440000
add $0,3601
|
; A242602: Integers repeated thrice in a canonical order.
; 0,0,0,1,1,1,-1,-1,-1,2,2,2,-2,-2,-2,3,3,3,-3,-3,-3,4,4,4,-4,-4,-4,5,5,5,-5,-5,-5,6,6,6,-6,-6,-6,7,7,7,-7,-7,-7,8,8,8,-8,-8,-8,9,9,9,-9,-9,-9,10,10,10,-10,-10,-10,11,11,11,-11,-11,-11,12,12,12,-12,-12,-12,13,13,13,-13,-13,-13,14,14,14,-14,-14,-14
mul $0,2
div $0,6
mov $1,$0
add $1,2
mov $2,4
mov $4,2
lpb $1
lpb $4
sub $2,$1
add $2,$4
mov $3,$2
sub $4,$1
mod $4,2
lpe
sub $3,2
mov $1,$3
sub $1,1
lpe
mul $1,2
sub $1,2
div $1,4
|
/*
* Copyright (c) 2017, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
L0:
(W&~f0.1)jmpi L528
L16:
add (1|M0) a0.0<1>:ud r23.5<0;1,0>:ud 0x48EC100:ud
mov (1|M0) r16.2<1>:ud 0x0:ud
and (1|M0) r16.3<1>:ud r0.3<0;1,0>:ud 0xFFFFFFFE:ud
mov (8|M0) r17.0<1>:ud r25.0<8;8,1>:ud
cmp (1|M0) (eq)f1.0 null.0<1>:w r24.2<0;1,0>:ub 0x1:uw
(~f1.0) mov (1|M0) r17.2<1>:f r10.1<0;1,0>:f
(~f1.0) mov (1|M0) r17.3<1>:f r10.7<0;1,0>:f
(f1.0) mov (1|M0) r17.2<1>:f r10.6<0;1,0>:f
(f1.0) mov (1|M0) r17.3<1>:f r10.7<0;1,0>:f
send (1|M0) r80:uw r16:ub 0x2 a0.0
(~f1.0) mov (1|M0) r17.2<1>:f r10.1<0;1,0>:f
(~f1.0) mov (1|M0) r17.3<1>:f r10.4<0;1,0>:f
(f1.0) mov (1|M0) r17.2<1>:f r10.6<0;1,0>:f
(f1.0) mov (1|M0) r17.3<1>:f r10.4<0;1,0>:f
send (1|M0) r88:uw r16:ub 0x2 a0.0
mov (16|M0) r13.0<1>:uw r80.0<16;16,1>:uw
mov (16|M0) r12.0<1>:uw r81.0<16;16,1>:uw
mov (16|M0) r80.0<1>:uw r84.0<16;16,1>:uw
mov (16|M0) r81.0<1>:uw r85.0<16;16,1>:uw
mov (16|M0) r84.0<1>:uw r13.0<16;16,1>:uw
mov (16|M0) r85.0<1>:uw r12.0<16;16,1>:uw
mov (16|M0) r13.0<1>:uw r88.0<16;16,1>:uw
mov (16|M0) r12.0<1>:uw r89.0<16;16,1>:uw
mov (16|M0) r88.0<1>:uw r92.0<16;16,1>:uw
mov (16|M0) r89.0<1>:uw r93.0<16;16,1>:uw
mov (16|M0) r92.0<1>:uw r13.0<16;16,1>:uw
mov (16|M0) r93.0<1>:uw r12.0<16;16,1>:uw
mov (1|M0) a0.8<1>:uw 0xA00:uw
mov (1|M0) a0.9<1>:uw 0xA40:uw
mov (1|M0) a0.10<1>:uw 0xA80:uw
mov (1|M0) a0.11<1>:uw 0xAC0:uw
add (4|M0) a0.12<1>:uw a0.8<4;4,1>:uw 0x100:uw
L528:
nop
|
; A323741: a(n) = m-p where m = (2n+1)^2 and p is the largest prime < m.
; 2,2,2,2,8,2,2,6,2,2,6,6,2,2,8,2,2,2,10,12,2,8,2,2,8,6,2,20,12,2,2,6,6,2,2,6,2,2,12,8,6,6,8,2,8,2,12,6,10,8,2,22,2,14,20,6,6,2,2,2,8,6,2,8,2,6,2,12,2,14,6,2,8,8,14,10,2,18,20,2,8,14,6,2,10,2,32,2,12,12,2,8,6,44,2,6,14,6,20,14
seq $0,73577 ; a(n) = 4*n^2 + 4*n - 1.
seq $0,64722 ; a(1) = 0; for n >= 2, a(n) = n - (largest prime <= n).
add $0,1
|
#include "PID.h"
/**
* TODO: Complete the PID class. You may add any additional desired functions.
*/
PID::PID() {}
PID::~PID() {}
void PID::Init(double Kp_, double Ki_, double Kd_) {
/**
* Initialization PID coefficients (and errors)
*/
PID::Kp = Kp_;
PID::Ki = Ki_;
PID::Kd = Kd_;
error_p = 0.0;
error_i = 0.0;
error_d = 0.0;
// Previous cte
cte_prev = 0.0;
}
void PID::UpdateError(double cte) {
/**
* Update PID errors based on cte.
*/
error_p = cte;
error_d = cte - cte_prev;
error_i += cte;
}
double PID::TotalError() {
/**
* Calculate and return the total error
*/
return error_p * Kp + error_i * Ki + error_d * Kd;; // TODO: Add your total error calc here!
} |
#include <EditorFrameworkPCH.h>
#include <EditorFramework/Actions/AssetActions.h>
#include <EditorFramework/Assets/AssetCurator.h>
#include <EditorFramework/Assets/AssetDocument.h>
#include <GuiFoundation/Action/ActionManager.h>
#include <GuiFoundation/Action/ActionMapManager.h>
ezActionDescriptorHandle ezAssetActions::s_hAssetCategory;
ezActionDescriptorHandle ezAssetActions::s_hTransformAsset;
ezActionDescriptorHandle ezAssetActions::s_hTransformAllAssets;
ezActionDescriptorHandle ezAssetActions::s_hResaveAllAssets;
ezActionDescriptorHandle ezAssetActions::s_hCheckFileSystem;
ezActionDescriptorHandle ezAssetActions::s_hWriteLookupTable;
void ezAssetActions::RegisterActions()
{
s_hAssetCategory = EZ_REGISTER_CATEGORY("AssetCategory");
s_hTransformAsset =
EZ_REGISTER_ACTION_1("Asset.Transform", ezActionScope::Document, "Assets", "Ctrl+E", ezAssetAction, ezAssetAction::ButtonType::TransformAsset);
s_hTransformAllAssets = EZ_REGISTER_ACTION_1(
"Asset.TransformAll", ezActionScope::Global, "Assets", "Ctrl+Shift+E", ezAssetAction, ezAssetAction::ButtonType::TransformAllAssets);
s_hResaveAllAssets =
EZ_REGISTER_ACTION_1("Asset.ResaveAll", ezActionScope::Global, "Assets", "", ezAssetAction, ezAssetAction::ButtonType::ResaveAllAssets);
s_hCheckFileSystem =
EZ_REGISTER_ACTION_1("Asset.CheckFilesystem", ezActionScope::Global, "Assets", "", ezAssetAction, ezAssetAction::ButtonType::CheckFileSystem);
s_hWriteLookupTable =
EZ_REGISTER_ACTION_1("Asset.WriteLookupTable", ezActionScope::Global, "Assets", "", ezAssetAction, ezAssetAction::ButtonType::WriteLookupTable);
}
void ezAssetActions::UnregisterActions()
{
ezActionManager::UnregisterAction(s_hAssetCategory);
ezActionManager::UnregisterAction(s_hTransformAsset);
ezActionManager::UnregisterAction(s_hTransformAllAssets);
ezActionManager::UnregisterAction(s_hResaveAllAssets);
ezActionManager::UnregisterAction(s_hCheckFileSystem);
ezActionManager::UnregisterAction(s_hWriteLookupTable);
}
void ezAssetActions::MapActions(const char* szMapping, bool bDocument)
{
ezActionMap* pMap = ezActionMapManager::GetActionMap(szMapping);
EZ_ASSERT_DEV(pMap != nullptr, "The given mapping ('{0}') does not exist, mapping the actions failed!", szMapping);
pMap->MapAction(s_hAssetCategory, "", 10.0f);
if (bDocument)
{
pMap->MapAction(s_hTransformAsset, "AssetCategory", 1.0f);
}
else
{
pMap->MapAction(s_hCheckFileSystem, "AssetCategory", 0.0f);
pMap->MapAction(s_hTransformAllAssets, "AssetCategory", 3.0f);
pMap->MapAction(s_hResaveAllAssets, "AssetCategory", 4.0f);
// pMap->MapAction(s_hWriteLookupTable, "AssetCategory", 5.0f);
}
}
////////////////////////////////////////////////////////////////////////
// ezAssetAction
////////////////////////////////////////////////////////////////////////
EZ_BEGIN_DYNAMIC_REFLECTED_TYPE(ezAssetAction, 1, ezRTTINoAllocator)
EZ_END_DYNAMIC_REFLECTED_TYPE;
ezAssetAction::ezAssetAction(const ezActionContext& context, const char* szName, ButtonType button)
: ezButtonAction(context, szName, false, "")
{
m_ButtonType = button;
switch (m_ButtonType)
{
case ezAssetAction::ButtonType::TransformAsset:
SetIconPath(":/EditorFramework/Icons/TransformAssets16.png");
break;
case ezAssetAction::ButtonType::TransformAllAssets:
SetIconPath(":/EditorFramework/Icons/TransformAllAssets16.png");
break;
case ezAssetAction::ButtonType::ResaveAllAssets:
SetIconPath(":/EditorFramework/Icons/ResavAllAssets16.png");
break;
case ezAssetAction::ButtonType::CheckFileSystem:
SetIconPath(":/EditorFramework/Icons/CheckFileSystem16.png");
break;
case ezAssetAction::ButtonType::WriteLookupTable:
SetIconPath(":/EditorFramework/Icons/WriteLookupTable16.png");
break;
}
}
ezAssetAction::~ezAssetAction() {}
void ezAssetAction::Execute(const ezVariant& value)
{
switch (m_ButtonType)
{
case ezAssetAction::ButtonType::TransformAsset:
{
if (m_Context.m_pDocument->IsModified())
{
ezStatus res = const_cast<ezDocument*>(m_Context.m_pDocument)->SaveDocument();
if (res.m_Result.Failed())
{
ezLog::Error("Failed to save document '{0}': '{1}'", m_Context.m_pDocument->GetDocumentPath(), res.m_sMessage);
break;
}
}
auto ret = ezAssetCurator::GetSingleton()->TransformAsset(
m_Context.m_pDocument->GetGuid(), ezTransformFlags::ForceTransform | ezTransformFlags::TriggeredManually);
if (ret.m_Result.Failed())
{
ezLog::Error("Transform failed: '{0}' ({1})", ret.m_sMessage, m_Context.m_pDocument->GetDocumentPath());
}
else
{
ezAssetCurator::GetSingleton()->WriteAssetTables();
}
}
break;
case ezAssetAction::ButtonType::TransformAllAssets:
{
ezAssetCurator::GetSingleton()->CheckFileSystem();
ezAssetCurator::GetSingleton()->TransformAllAssets(ezTransformFlags::None);
}
break;
case ezAssetAction::ButtonType::ResaveAllAssets:
{
ezAssetCurator::GetSingleton()->ResaveAllAssets();
}
break;
case ezAssetAction::ButtonType::CheckFileSystem:
{
ezAssetCurator::GetSingleton()->CheckFileSystem();
ezAssetCurator::GetSingleton()->WriteAssetTables();
}
break;
case ezAssetAction::ButtonType::WriteLookupTable:
{
ezAssetCurator::GetSingleton()->WriteAssetTables();
}
break;
}
}
|
; A017392: a(n) = (11*n)^4.
; 0,14641,234256,1185921,3748096,9150625,18974736,35153041,59969536,96059601,146410000,214358881,303595776,418161601,562448656,741200625,959512576,1222830961,1536953616,1908029761,2342560000,2847396321,3429742096,4097152081,4857532416,5719140625,6690585616,7780827681,8999178496,10355301121,11859210000,13521270961,15352201216,17363069361,19565295376,21970650625,24591257856,27439591201,30528476176,33871089681,37480960000,41371966801,45558341136,50054665441,54875873536,60037250625,65554433296,71443409521,77720518656,84402451441,91506250000,99049307841,107049369856,115524532321,124493242896,133974300625,143986855936,154550410641,165684817936,177410282401,189747360000,202716958081,216340335376,230639102001,245635219456,261351000625,277809109776,295032562561,313044726016,331869318561,351530410000,372052421521,393460125696,415778646481,439033459216,463250390625,488455618816,514675673281,541937434896,570268135921,599695360000,630247042161,661951468816,694837277761,728933458176,764269350625,800874647056,838779390801,878013976576,918609150481,960596010000,1004006004001,1048870932736,1095222947841,1143094552336,1192518600625,1243528298496,1296157203121,1350439223056,1406408618241
mul $0,11
pow $0,4
|
;
; Amstrad CPC library
; ******************************************************
; ** Librería de rutinas para Amstrad CPC **
; ** Raúl Simarro, Artaburu 2009 **
; ******************************************************
;
; cpc_GetScrAddress(int x, int y) __smallc ;
;
; $Id: cpc_GetScrAddress.asm $
;
SECTION code_clib
PUBLIC cpc_GetScrAddress
EXTERN cpc_GetScrAddress0
.cpc_GetScrAddress
; coordinates are in (A,L)
pop af
pop hl ; y
pop bc ; x
push bc
push hl
push af
ld a,c
jp cpc_GetScrAddress0
|
#include "game.h"
extern int fog;
namespace ai
{
using namespace game;
avoidset obstacles;
int updatemillis = 0, iteration = 0, itermillis = 0, forcegun = -1;
vec aitarget(0, 0, 0);
VAR(aidebug, 0, 0, 6);
VAR(aiforcegun, -1, -1, NUMGUNS - 1);
ICOMMAND(addbot, "s", (char *s), addmsg(N_ADDBOT, "ri", *s ? clamp(parseint(s), 1, 101) : -1));
ICOMMAND(delbot, "", (), addmsg(N_DELBOT, "r"));
ICOMMAND(botlimit, "i", (int *n), addmsg(N_BOTLIMIT, "ri", *n));
ICOMMAND(botbalance, "i", (int *n), addmsg(N_BOTBALANCE, "ri", *n));
float viewdist(int x)
{
return x <= 100 ? clamp((SIGHTMIN + (SIGHTMAX - SIGHTMIN)) / 100.f * float(x), float(SIGHTMIN), float(fog))
: float(fog);
}
float viewfieldx(int x)
{
return x <= 100 ? clamp((VIEWMIN + (VIEWMAX - VIEWMIN)) / 100.f * float(x), float(VIEWMIN), float(VIEWMAX))
: float(VIEWMAX);
}
float viewfieldy(int x)
{
return viewfieldx(x) * 3.f / 4.f;
}
bool canmove(fpsent *d)
{
return d->state != CS_DEAD && !intermission;
}
float weapmindist(int weap)
{
return max(int(guns[weap].exprad), 2);
}
float weapmaxdist(int weap)
{
return guns[weap].range + 4;
}
bool weaprange(fpsent *d, int weap, float dist)
{
float mindist = weapmindist(weap), maxdist = weapmaxdist(weap);
return dist >= mindist * mindist && dist <= maxdist * maxdist;
}
bool targetable(fpsent *d, fpsent *e)
{
if (d == e || !canmove(d))
return false;
return e->state == CS_ALIVE && !isteam(d->team, e->team);
}
bool getsight(vec &o, float yaw, float pitch, vec &q, vec &v, float mdist, float fovx, float fovy)
{
float dist = o.dist(q);
if (dist <= mdist)
{
float x = fmod(fabs(asin((q.z - o.z) / dist) / RAD - pitch), 360);
float y = fmod(fabs(-atan2(q.x - o.x, q.y - o.y) / RAD - yaw), 360);
if (min(x, 360 - x) <= fovx && min(y, 360 - y) <= fovy)
return raycubelos(o, q, v);
}
return false;
}
bool cansee(fpsent *d, vec &x, vec &y, vec &targ)
{
aistate &b = d->ai->getstate();
if (canmove(d) && b.type != AI_S_WAIT)
return getsight(x, d->yaw, d->pitch, y, targ, d->ai->views[2], d->ai->views[0], d->ai->views[1]);
return false;
}
bool canshoot(fpsent *d, fpsent *e)
{
if (weaprange(d, d->gunselect, e->o.squaredist(d->o)) && targetable(d, e))
return d->ammo[d->gunselect] > 0 && lastmillis - d->lastaction >= d->gunwait;
return false;
}
bool canshoot(fpsent *d)
{
return !d->ai->becareful && d->ammo[d->gunselect] > 0 && lastmillis - d->lastaction >= d->gunwait;
}
bool hastarget(fpsent *d, aistate &b, fpsent *e, float yaw, float pitch, float dist)
{ // add margins of error
if (weaprange(d, d->gunselect, dist) || (d->skill <= 100 && !rnd(d->skill)))
{
if (d->gunselect == GUN_FIST)
return true;
float skew = clamp(float(lastmillis - d->ai->enemymillis) /
float((d->skill * guns[d->gunselect].attackdelay / 200.f)),
0.f, guns[d->gunselect].projspeed ? 0.25f : 1e16f),
offy = yaw - d->yaw, offp = pitch - d->pitch;
if (offy > 180)
offy -= 360;
else if (offy < -180)
offy += 360;
if (fabs(offy) <= d->ai->views[0] * skew && fabs(offp) <= d->ai->views[1] * skew)
return true;
}
return false;
}
vec getaimpos(fpsent *d, fpsent *e)
{
vec o = e->o;
if (d->gunselect == GUN_RL)
o.z += (e->aboveeye * 0.2f) - (0.8f * d->eyeheight);
else if (d->gunselect != GUN_GL)
o.z += (e->aboveeye - e->eyeheight) * 0.5f;
if (d->skill <= 100)
{
if (lastmillis >= d->ai->lastaimrnd)
{
const int aiskew[NUMGUNS] = {1, 10, 50, 5, 20, 1, 100, 10, 10, 10, 1, 1};
#define rndaioffset(r) \
((rnd(int(r * aiskew[d->gunselect] * 2) + 1) - (r * aiskew[d->gunselect])) * (1.f / float(max(d->skill, 1))))
loopk(3) d->ai->aimrnd[k] = rndaioffset(e->radius);
int dur = (d->skill + 10) * 10;
d->ai->lastaimrnd = lastmillis + dur + rnd(dur);
}
loopk(3) o[k] += d->ai->aimrnd[k];
}
return o;
}
void create(fpsent *d)
{
if (!d->ai)
d->ai = new aiinfo;
}
void destroy(fpsent *d)
{
if (d->ai)
DELETEP(d->ai);
}
void init(fpsent *d, int at, int ocn, int sk, int bn, int pm, const char *name, const char *team)
{
loadwaypoints();
fpsent *o = newclient(ocn);
d->aitype = at;
bool resetthisguy = false;
if (!d->name[0])
{
if (aidebug)
conoutf(CON_DEBUG, "%s assigned to %s at skill %d", colorname(d, name), o ? colorname(o) : "?", sk);
else
conoutf("\f0join:\f7 %s", colorname(d, name));
resetthisguy = true;
}
else
{
if (d->ownernum != ocn)
{
if (aidebug)
conoutf(CON_DEBUG, "%s reassigned to %s", colorname(d, name), o ? colorname(o) : "?");
resetthisguy = true;
}
if (d->skill != sk && aidebug)
conoutf(CON_DEBUG, "%s changed skill to %d", colorname(d, name), sk);
}
copystring(d->name, name, MAXNAMELEN + 1);
copystring(d->team, team, MAXTEAMLEN + 1);
d->ownernum = ocn;
d->plag = 0;
d->skill = sk;
d->playermodel = chooserandomplayermodel(pm);
if (resetthisguy)
removeweapons(d);
if (d->ownernum >= 0 && player1->clientnum == d->ownernum)
{
create(d);
if (d->ai)
{
d->ai->views[0] = viewfieldx(d->skill);
d->ai->views[1] = viewfieldy(d->skill);
d->ai->views[2] = viewdist(d->skill);
}
}
else if (d->ai)
destroy(d);
}
void update()
{
if (intermission)
{
loopv(players) if (players[i]->ai) players[i]->stopmoving();
}
else // fixed rate logic done out-of-sequence at 1 frame per second for each ai
{
if (totalmillis - updatemillis > 1000)
{
avoid();
forcegun = multiplayer(false) ? -1 : aiforcegun;
updatemillis = totalmillis;
}
if (!iteration && totalmillis - itermillis > 1000)
{
iteration = 1;
itermillis = totalmillis;
}
int count = 0;
loopv(players) if (players[i]->ai) think(players[i], ++count == iteration ? true : false);
if (++iteration > count)
iteration = 0;
}
}
bool checkothers(vector<int> &targets, fpsent *d, int state, int targtype, int target, bool teams, int *members)
{ // checks the states of other ai for a match
targets.setsize(0);
loopv(players)
{
fpsent *e = players[i];
if (targets.find(e->clientnum) >= 0)
continue;
if (teams && d && !isteam(d->team, e->team))
continue;
if (members)
(*members)++;
if (e == d || !e->ai || e->state != CS_ALIVE)
continue;
aistate &b = e->ai->getstate();
if (state >= 0 && b.type != state)
continue;
if (target >= 0 && b.target != target)
continue;
if (targtype >= 0 && b.targtype != targtype)
continue;
targets.add(e->clientnum);
}
return !targets.empty();
}
bool makeroute(fpsent *d, aistate &b, int node, bool changed, int retries)
{
if (!iswaypoint(d->lastnode))
return false;
if (changed && d->ai->route.length() > 1 && d->ai->route[0] == node)
return true;
if (route(d, d->lastnode, node, d->ai->route, obstacles, retries))
{
b.override = false;
return true;
}
// retry fails: 0 = first attempt, 1 = try ignoring obstacles, 2 = try ignoring prevnodes too
if (retries <= 1)
return makeroute(d, b, node, false, retries + 1);
return false;
}
bool makeroute(fpsent *d, aistate &b, const vec &pos, bool changed, int retries)
{
int node = closestwaypoint(pos, SIGHTMIN, true);
return makeroute(d, b, node, changed, retries);
}
bool randomnode(fpsent *d, aistate &b, const vec &pos, float guard, float wander)
{
static vector<int> candidates;
candidates.setsize(0);
findwaypointswithin(pos, guard, wander, candidates);
while (!candidates.empty())
{
int w = rnd(candidates.length()), n = candidates.removeunordered(w);
if (n != d->lastnode && !d->ai->hasprevnode(n) && !obstacles.find(n, d) && makeroute(d, b, n))
return true;
}
return false;
}
bool randomnode(fpsent *d, aistate &b, float guard, float wander)
{
return randomnode(d, b, d->feetpos(), guard, wander);
}
bool badhealth(fpsent *d)
{
if (d->skill <= 100)
return d->health <= (111 - d->skill) / 4;
return false;
}
bool enemy(fpsent *d, aistate &b, const vec &pos, float guard = SIGHTMIN, int pursue = 0)
{
fpsent *t = NULL;
vec dp = d->headpos();
float mindist = guard * guard, bestdist = 1e16f;
loopv(players)
{
fpsent *e = players[i];
if (e == d || !targetable(d, e))
continue;
vec ep = getaimpos(d, e);
float dist = ep.squaredist(dp);
if (dist < bestdist && (cansee(d, dp, ep) || dist <= mindist))
{
t = e;
bestdist = dist;
}
}
if (t && violence(d, b, t, pursue))
return true;
return false;
}
bool patrol(fpsent *d, aistate &b, const vec &pos, float guard, float wander, int walk, bool retry)
{
vec feet = d->feetpos();
if (walk == 2 || b.override || (walk && feet.squaredist(pos) <= guard * guard) || !makeroute(d, b, pos))
{ // run away and back to keep ourselves busy
if (!b.override && randomnode(d, b, pos, guard, wander))
{
b.override = true;
return true;
}
else if (d->ai->route.empty())
{
if (!retry)
{
b.override = false;
return patrol(d, b, pos, guard, wander, walk, true);
}
b.override = false;
return false;
}
}
b.override = false;
return true;
}
bool defend(fpsent *d, aistate &b, const vec &pos, float guard, float wander, int walk)
{
bool hasenemy = enemy(d, b, pos, wander, d->gunselect == GUN_FIST ? 1 : 0);
if (!walk)
{
if (d->feetpos().squaredist(pos) <= guard * guard)
{
b.idle = hasenemy ? 2 : 1;
return true;
}
walk++;
}
return patrol(d, b, pos, guard, wander, walk);
}
bool violence(fpsent *d, aistate &b, fpsent *e, int pursue)
{
if (e && targetable(d, e))
{
if (pursue)
{
if ((b.targtype != AI_T_AFFINITY || !(pursue % 2)) && makeroute(d, b, e->lastnode))
d->ai->switchstate(b, AI_S_PURSUE, AI_T_PLAYER, e->clientnum);
else if (pursue >= 3)
return false; // can't pursue
}
if (d->ai->enemy != e->clientnum)
{
d->ai->enemyseen = d->ai->enemymillis = lastmillis;
d->ai->enemy = e->clientnum;
}
return true;
}
return false;
}
bool target(fpsent *d, aistate &b, int pursue = 0, bool force = false, float mindist = 0.f)
{
static vector<fpsent *> hastried;
hastried.setsize(0);
vec dp = d->headpos();
while (true)
{
float dist = 1e16f;
fpsent *t = NULL;
loopv(players)
{
fpsent *e = players[i];
if (e == d || hastried.find(e) >= 0 || !targetable(d, e))
continue;
vec ep = getaimpos(d, e);
float v = ep.squaredist(dp);
if ((!t || v < dist) && (mindist <= 0 || v <= mindist) && (force || cansee(d, dp, ep)))
{
t = e;
dist = v;
}
}
if (t)
{
if (violence(d, b, t, pursue))
return true;
hastried.add(t);
}
else
break;
}
return false;
}
int isgoodammo(int gun)
{
return gun >= GUN_SG && gun <= GUN_GL;
}
bool hasgoodammo(fpsent *d)
{
static const int goodguns[] = {GUN_CG, GUN_RL, GUN_SG, GUN_RIFLE};
loopi(sizeof(goodguns) / sizeof(goodguns[0])) if (d->hasammo(goodguns[0])) return true;
if (d->ammo[GUN_GL] > 5)
return true;
return false;
}
void assist(fpsent *d, aistate &b, vector<interest> &interests, bool all, bool force)
{
loopv(players)
{
fpsent *e = players[i];
if (e == d || (!all && e->aitype != AI_NONE) || !isteam(d->team, e->team))
continue;
interest &n = interests.add();
n.state = AI_S_DEFEND;
n.node = e->lastnode;
n.target = e->clientnum;
n.targtype = AI_T_PLAYER;
n.score = e->o.squaredist(d->o) / (hasgoodammo(d) ? 1e8f : (force ? 1e4f : 1e2f));
}
}
static void tryitem(fpsent *d, extentity &e, int id, aistate &b, vector<interest> &interests, bool force = false)
{
float score = 0;
switch (e.type)
{
case I_HEALTH:
if (d->health < min(d->skill, 75))
score = 1e3f;
break;
case I_QUAD:
score = 1e3f;
break;
case I_BOOST:
score = 1e2f;
break;
case I_GREENARMOUR:
case I_YELLOWARMOUR: {
int atype = A_GREEN + e.type - I_GREENARMOUR;
if (atype > d->armourtype)
score = atype == A_YELLOW ? 1e2f : 1e1f;
else if (d->armour < 50)
score = 1e1f;
break;
}
default: {
if (e.type >= I_SHELLS && e.type <= I_CARTRIDGES && !d->hasmaxammo(e.type))
{
int gun = e.type - I_SHELLS + GUN_SG;
// go get a weapon upgrade
if (gun == d->ai->weappref)
score = 1e8f;
else if (isgoodammo(gun))
score = hasgoodammo(d) ? 1e2f : 1e4f;
}
break;
}
}
if (score != 0)
{
interest &n = interests.add();
n.state = AI_S_INTEREST;
n.node = closestwaypoint(e.o, SIGHTMIN, true);
n.target = id;
n.targtype = AI_T_ENTITY;
n.score = d->feetpos().squaredist(e.o) / (force ? -1 : score);
}
}
void items(fpsent *d, aistate &b, vector<interest> &interests, bool force = false)
{
loopv(entities::ents)
{
extentity &e = *(extentity *)entities::ents[i];
if (!e.spawned() || e.nopickup() || !d->canpickup(e.type))
continue;
tryitem(d, e, i, b, interests, force);
}
}
static vector<int> targets;
bool parseinterests(fpsent *d, aistate &b, vector<interest> &interests, bool override, bool ignore)
{
while (!interests.empty())
{
int q = interests.length() - 1;
loopi(interests.length() - 1) if (interests[i].score < interests[q].score) q = i;
interest n = interests.removeunordered(q);
bool proceed = true;
if (!ignore)
switch (n.state)
{
case AI_S_DEFEND: // don't get into herds
{
int members = 0;
proceed =
!checkothers(targets, d, n.state, n.targtype, n.target, true, &members) && members > 1;
break;
}
default:
break;
}
if (proceed && makeroute(d, b, n.node))
{
d->ai->switchstate(b, n.state, n.targtype, n.target);
return true;
}
}
return false;
}
bool find(fpsent *d, aistate &b, bool override = false)
{
static vector<interest> interests;
interests.setsize(0);
if (!m_noitems)
{
if ((!m_noammo && !hasgoodammo(d)) || d->health < min(d->skill - 15, 75))
items(d, b, interests);
else
{
static vector<int> nearby;
nearby.setsize(0);
findents(I_SHELLS, I_QUAD, false, d->feetpos(), vec(32, 32, 24), nearby);
loopv(nearby)
{
int id = nearby[i];
extentity &e = *(extentity *)entities::ents[id];
if (d->canpickup(e.type))
tryitem(d, e, id, b, interests);
}
}
}
if (cmode)
cmode->aifind(d, b, interests);
if (m_teammode)
assist(d, b, interests);
return parseinterests(d, b, interests, override);
}
bool findassist(fpsent *d, aistate &b, bool override = false)
{
static vector<interest> interests;
interests.setsize(0);
assist(d, b, interests);
while (!interests.empty())
{
int q = interests.length() - 1;
loopi(interests.length() - 1) if (interests[i].score < interests[q].score) q = i;
interest n = interests.removeunordered(q);
bool proceed = true;
switch (n.state)
{
case AI_S_DEFEND: // don't get into herds
{
int members = 0;
proceed = !checkothers(targets, d, n.state, n.targtype, n.target, true, &members) && members > 1;
break;
}
default:
break;
}
if (proceed && makeroute(d, b, n.node))
{
d->ai->switchstate(b, n.state, n.targtype, n.target);
return true;
}
}
return false;
}
void damaged(fpsent *d, fpsent *e)
{
if (d->ai && canmove(d) && targetable(d, e)) // see if this ai is interested in a grudge
{
aistate &b = d->ai->getstate();
if (violence(d, b, e, d->gunselect == GUN_FIST ? 1 : 0))
return;
}
if (checkothers(targets, d, AI_S_DEFEND, AI_T_PLAYER, d->clientnum, true))
{
loopv(targets)
{
fpsent *t = getclient(targets[i]);
if (!t->ai || !canmove(t) || !targetable(t, e))
continue;
aistate &c = t->ai->getstate();
if (violence(t, c, e, d->gunselect == GUN_FIST ? 1 : 0))
return;
}
}
}
void findorientation(vec &o, float yaw, float pitch, vec &pos)
{
vec dir;
vecfromyawpitch(yaw, pitch, 1, 0, dir);
if (raycubepos(o, dir, pos, 0, RAY_CLIPMAT | RAY_SKIPFIRST) == -1)
pos = dir.mul(2 * getworldsize()).add(o);
}
void setup(fpsent *d)
{
d->ai->clearsetup();
d->ai->reset(true);
d->ai->lastrun = lastmillis;
if (m_insta)
d->ai->weappref = GUN_RIFLE;
else
{
if (forcegun >= 0 && forcegun < NUMGUNS)
d->ai->weappref = forcegun;
else if (m_noammo)
d->ai->weappref = -1;
else
d->ai->weappref = rnd(GUN_GL - GUN_SG + 1) + GUN_SG;
}
vec dp = d->headpos();
findorientation(dp, d->yaw, d->pitch, d->ai->target);
}
void spawned(fpsent *d)
{
if (d->ai)
setup(d);
}
void killed(fpsent *d, fpsent *e)
{
if (d->ai)
d->ai->reset();
}
void itemspawned(int ent)
{
if (entities::ents.inrange(ent) && entities::ents[ent]->type >= I_SHELLS && entities::ents[ent]->type <= I_QUAD)
{
loopv(players) if (players[i] && players[i]->ai && players[i]->aitype == AI_BOT &&
players[i]->canpickup(entities::ents[ent]->type))
{
fpsent *d = players[i];
bool wantsitem = false;
switch (entities::ents[ent]->type)
{
case I_BOOST:
case I_HEALTH:
wantsitem = badhealth(d);
break;
case I_GREENARMOUR:
case I_YELLOWARMOUR:
case I_QUAD:
break;
default: {
itemstat &is = itemstats[entities::ents[ent]->type - I_SHELLS];
wantsitem = isgoodammo(is.info) &&
d->ammo[is.info] <= (d->ai->weappref == is.info ? is.add : is.add / 2);
break;
}
}
if (wantsitem)
{
aistate &b = d->ai->getstate();
if (b.targtype == AI_T_AFFINITY)
continue;
if (b.type == AI_S_INTEREST && b.targtype == AI_T_ENTITY)
{
if (entities::ents.inrange(b.target))
{
if (d->o.squaredist(entities::ents[ent]->o) < d->o.squaredist(entities::ents[b.target]->o))
d->ai->switchstate(b, AI_S_INTEREST, AI_T_ENTITY, ent);
}
continue;
}
d->ai->switchstate(b, AI_S_INTEREST, AI_T_ENTITY, ent);
}
}
}
}
bool check(fpsent *d, aistate &b)
{
if (cmode && cmode->aicheck(d, b))
return true;
return false;
}
int dowait(fpsent *d, aistate &b)
{
d->ai->clear(true); // ensure they're clean
if (check(d, b) || find(d, b))
return 1;
if (target(d, b, 4, false))
return 1;
if (target(d, b, 4, true))
return 1;
if (randomnode(d, b, SIGHTMIN, 1e16f))
{
d->ai->switchstate(b, AI_S_INTEREST, AI_T_NODE, d->ai->route[0]);
return 1;
}
return 0; // but don't pop the state
}
int dodefend(fpsent *d, aistate &b)
{
if (d->state == CS_ALIVE)
{
switch (b.targtype)
{
case AI_T_NODE:
if (check(d, b))
return 1;
if (iswaypoint(b.target))
return defend(d, b, waypoints[b.target].o) ? 1 : 0;
break;
case AI_T_ENTITY:
if (check(d, b))
return 1;
if (entities::ents.inrange(b.target))
return defend(d, b, entities::ents[b.target]->o) ? 1 : 0;
break;
case AI_T_AFFINITY:
if (cmode)
return cmode->aidefend(d, b) ? 1 : 0;
break;
case AI_T_PLAYER: {
if (check(d, b))
return 1;
fpsent *e = getclient(b.target);
if (e && e->state == CS_ALIVE)
return defend(d, b, e->feetpos()) ? 1 : 0;
break;
}
default:
break;
}
}
return 0;
}
int dointerest(fpsent *d, aistate &b)
{
if (d->state != CS_ALIVE)
return 0;
switch (b.targtype)
{
case AI_T_NODE: // this is like a wait state without sitting still..
if (check(d, b) || find(d, b))
return 1;
if (target(d, b, 4, true))
return 1;
if (iswaypoint(b.target) && vec(waypoints[b.target].o).sub(d->feetpos()).magnitude() > CLOSEDIST)
return makeroute(d, b, waypoints[b.target].o) ? 1 : 0;
break;
case AI_T_ENTITY:
if (entities::ents.inrange(b.target))
{
extentity &e = *(extentity *)entities::ents[b.target];
if (!e.spawned() || e.nopickup() || e.type < I_SHELLS || e.type > I_CARTRIDGES ||
d->hasmaxammo(e.type))
return 0;
// if(d->feetpos().squaredist(e.o) <= CLOSEDIST*CLOSEDIST)
//{
// b.idle = 1;
// return true;
//}
return makeroute(d, b, e.o) ? 1 : 0;
}
break;
}
return 0;
}
int dopursue(fpsent *d, aistate &b)
{
if (d->state == CS_ALIVE)
{
switch (b.targtype)
{
case AI_T_NODE: {
if (check(d, b))
return 1;
if (iswaypoint(b.target))
return defend(d, b, waypoints[b.target].o) ? 1 : 0;
break;
}
case AI_T_AFFINITY: {
if (cmode)
return cmode->aipursue(d, b) ? 1 : 0;
break;
}
case AI_T_PLAYER: {
// if(check(d, b)) return 1;
fpsent *e = getclient(b.target);
if (e && e->state == CS_ALIVE)
{
float guard = SIGHTMIN, wander = guns[d->gunselect].range;
if (d->gunselect == GUN_FIST)
guard = 0.f;
return patrol(d, b, e->feetpos(), guard, wander) ? 1 : 0;
}
break;
}
default:
break;
}
}
return 0;
}
int closenode(fpsent *d)
{
vec pos = d->feetpos();
int node1 = -1, node2 = -1;
float mindist1 = CLOSEDIST * CLOSEDIST, mindist2 = CLOSEDIST * CLOSEDIST;
loopv(d->ai->route) if (iswaypoint(d->ai->route[i]))
{
vec epos = waypoints[d->ai->route[i]].o;
float dist = epos.squaredist(pos);
if (dist > FARDIST * FARDIST)
continue;
int entid = obstacles.remap(d, d->ai->route[i], epos);
if (entid >= 0)
{
if (entid != i)
dist = epos.squaredist(pos);
if (dist < mindist1)
{
node1 = i;
mindist1 = dist;
}
}
else if (dist < mindist2)
{
node2 = i;
mindist2 = dist;
}
}
return node1 >= 0 ? node1 : node2;
}
int wpspot(fpsent *d, int n, bool check = false)
{
if (iswaypoint(n))
loopk(2)
{
vec epos = waypoints[n].o;
int entid = obstacles.remap(d, n, epos, k != 0);
if (iswaypoint(entid))
{
d->ai->spot = epos;
d->ai->targnode = entid;
return !check || d->feetpos().squaredist(epos) > MINWPDIST * MINWPDIST ? 1 : 2;
}
}
return 0;
}
int randomlink(fpsent *d, int n)
{
if (iswaypoint(n) && waypoints[n].haslinks())
{
waypoint &w = waypoints[n];
static vector<int> linkmap;
linkmap.setsize(0);
loopi(MAXWAYPOINTLINKS)
{
if (!w.links[i])
break;
if (iswaypoint(w.links[i]) && !d->ai->hasprevnode(w.links[i]) && d->ai->route.find(w.links[i]) < 0)
linkmap.add(w.links[i]);
}
if (!linkmap.empty())
return linkmap[rnd(linkmap.length())];
}
return -1;
}
bool anynode(fpsent *d, aistate &b, int len = NUMPREVNODES)
{
if (iswaypoint(d->lastnode))
loopk(2)
{
d->ai->clear(k ? true : false);
int n = randomlink(d, d->lastnode);
if (wpspot(d, n))
{
d->ai->route.add(n);
d->ai->route.add(d->lastnode);
loopi(len)
{
n = randomlink(d, n);
if (iswaypoint(n))
d->ai->route.insert(0, n);
else
break;
}
return true;
}
}
return false;
}
bool checkroute(fpsent *d, int n)
{
if (d->ai->route.empty() || !d->ai->route.inrange(n))
return false;
int last = d->ai->lastcheck ? lastmillis - d->ai->lastcheck : 0;
if (last < 500 || n < 3)
return false; // route length is too short
d->ai->lastcheck = lastmillis;
int w = iswaypoint(d->lastnode) ? d->lastnode : d->ai->route[n], c = min(n - 1, NUMPREVNODES);
loopj(c) // check ahead to see if we need to go around something
{
int p = n - j - 1, v = d->ai->route[p];
if (d->ai->hasprevnode(v) || obstacles.find(v, d)) // something is in the way, try to remap around it
{
int m = p - 1;
if (m < 3)
return false; // route length is too short from this point
loopirev(m)
{
int t = d->ai->route[i];
if (!d->ai->hasprevnode(t) && !obstacles.find(t, d))
{
static vector<int> remap;
remap.setsize(0);
if (route(d, w, t, remap, obstacles))
{ // kill what we don't want and put the remap in
while (d->ai->route.length() > i)
d->ai->route.pop();
loopvk(remap) d->ai->route.add(remap[k]);
return true;
}
return false; // we failed
}
}
return false;
}
}
return false;
}
bool hunt(fpsent *d, aistate &b)
{
if (!d->ai->route.empty())
{
int n = closenode(d);
if (d->ai->route.inrange(n) && checkroute(d, n))
n = closenode(d);
if (d->ai->route.inrange(n))
{
if (!n)
{
switch (wpspot(d, d->ai->route[n], true))
{
case 2:
d->ai->clear(false);
case 1:
return true; // not close enough to pop it yet
case 0:
default:
break;
}
}
else
{
while (d->ai->route.length() > n + 1)
d->ai->route.pop(); // waka-waka-waka-waka
int m = n - 1; // next, please!
if (d->ai->route.inrange(m) && wpspot(d, d->ai->route[m]))
return true;
}
}
}
b.override = false;
return anynode(d, b);
}
void jumpto(fpsent *d, aistate &b, const vec &pos)
{
vec off = vec(pos).sub(d->feetpos()), dir(off.x, off.y, 0);
bool sequenced = d->ai->blockseq || d->ai->targseq, offground = d->timeinair && !d->inwater,
jump = !offground && lastmillis >= d->ai->jumpseed &&
(sequenced || off.z >= JUMPMIN || lastmillis >= d->ai->jumprand);
if (jump)
{
vec old = d->o;
d->o = vec(pos).add(vec(0, 0, d->eyeheight));
if (collide(d, vec(0, 0, 1)))
jump = false;
d->o = old;
if (jump)
{
float radius = 18 * 18;
loopv(entities::ents) if (entities::ents[i]->type == JUMPPAD)
{
fpsentity &e = *(fpsentity *)entities::ents[i];
if (e.o.squaredist(pos) <= radius)
{
jump = false;
break;
}
}
}
}
if (jump)
{
d->jumping = true;
int seed = (111 - d->skill) * (d->inwater ? 3 : 5);
d->ai->jumpseed = lastmillis + seed + rnd(seed);
seed *= b.idle ? 50 : 25;
d->ai->jumprand = lastmillis + seed + rnd(seed);
}
}
void fixfullrange(float &yaw, float &pitch, float &roll, bool full)
{
if (full)
{
while (pitch < -180.0f)
pitch += 360.0f;
while (pitch >= 180.0f)
pitch -= 360.0f;
while (roll < -180.0f)
roll += 360.0f;
while (roll >= 180.0f)
roll -= 360.0f;
}
else
{
if (pitch > 89.9f)
pitch = 89.9f;
if (pitch < -89.9f)
pitch = -89.9f;
if (roll > 89.9f)
roll = 89.9f;
if (roll < -89.9f)
roll = -89.9f;
}
while (yaw < 0.0f)
yaw += 360.0f;
while (yaw >= 360.0f)
yaw -= 360.0f;
}
void fixrange(float &yaw, float &pitch)
{
float r = 0.f;
fixfullrange(yaw, pitch, r, false);
}
void getyawpitch(const vec &from, const vec &pos, float &yaw, float &pitch)
{
float dist = from.dist(pos);
yaw = -atan2(pos.x - from.x, pos.y - from.y) / RAD;
pitch = asin((pos.z - from.z) / dist) / RAD;
}
void scaleyawpitch(float &yaw, float &pitch, float targyaw, float targpitch, float frame, float scale)
{
if (yaw < targyaw - 180.0f)
yaw += 360.0f;
if (yaw > targyaw + 180.0f)
yaw -= 360.0f;
float offyaw = fabs(targyaw - yaw) * frame, offpitch = fabs(targpitch - pitch) * frame * scale;
if (targyaw > yaw)
{
yaw += offyaw;
if (targyaw < yaw)
yaw = targyaw;
}
else if (targyaw < yaw)
{
yaw -= offyaw;
if (targyaw > yaw)
yaw = targyaw;
}
if (targpitch > pitch)
{
pitch += offpitch;
if (targpitch < pitch)
pitch = targpitch;
}
else if (targpitch < pitch)
{
pitch -= offpitch;
if (targpitch > pitch)
pitch = targpitch;
}
fixrange(yaw, pitch);
}
bool lockon(fpsent *d, fpsent *e, float maxdist)
{
if (d->gunselect == GUN_FIST && !d->blocked && !d->timeinair)
{
vec dir = vec(e->o).sub(d->o);
float xydist = dir.x * dir.x + dir.y * dir.y, zdist = dir.z * dir.z, mdist = maxdist * maxdist,
ddist = d->radius * d->radius + e->radius * e->radius;
if (zdist <= ddist && xydist >= ddist + 4 && xydist <= mdist + ddist)
return true;
}
return false;
}
int process(fpsent *d, aistate &b)
{
int result = 0, stupify = d->skill <= 10 + rnd(15) ? rnd(d->skill * 1000) : 0, skmod = 101 - d->skill;
float frame = d->skill <= 100 ? float(lastmillis - d->ai->lastrun) / float(max(skmod, 1) * 10) : 1;
vec dp = d->headpos();
bool idle = b.idle == 1 || (stupify && stupify <= skmod);
d->ai->dontmove = false;
if (idle)
{
d->ai->lastaction = d->ai->lasthunt = lastmillis;
d->ai->dontmove = true;
d->ai->spot = vec(0, 0, 0);
}
else if (hunt(d, b))
{
getyawpitch(dp, vec(d->ai->spot).add(vec(0, 0, d->eyeheight)), d->ai->targyaw, d->ai->targpitch);
d->ai->lasthunt = lastmillis;
}
else
{
idle = d->ai->dontmove = true;
d->ai->spot = vec(0, 0, 0);
}
if (!d->ai->dontmove)
jumpto(d, b, d->ai->spot);
fpsent *e = getclient(d->ai->enemy);
bool enemyok = e && targetable(d, e);
if (!enemyok || d->skill >= 50)
{
fpsent *f = (fpsent *)intersectclosest(dp, d->ai->target, d);
if (f)
{
if (targetable(d, f))
{
if (!enemyok)
violence(d, b, f, d->gunselect == GUN_FIST ? 1 : 0);
enemyok = true;
e = f;
}
else
enemyok = false;
}
else if (!enemyok && target(d, b, d->gunselect == GUN_FIST ? 1 : 0, false, SIGHTMIN))
enemyok = (e = getclient(d->ai->enemy)) != NULL;
}
if (enemyok)
{
vec ep = getaimpos(d, e);
float yaw, pitch;
getyawpitch(dp, ep, yaw, pitch);
fixrange(yaw, pitch);
bool insight = cansee(d, dp, ep),
hasseen = d->ai->enemyseen && lastmillis - d->ai->enemyseen <= (d->skill * 10) + 3000,
quick =
d->ai->enemyseen && lastmillis - d->ai->enemyseen <= (d->gunselect == GUN_CG ? 300 : skmod) + 30;
if (insight)
d->ai->enemyseen = lastmillis;
if (idle || insight || hasseen || quick)
{
float sskew = insight || d->skill > 100 ? 1.5f : (hasseen ? 1.f : 0.5f);
if (insight && lockon(d, e, 16))
{
d->ai->targyaw = yaw;
d->ai->targpitch = pitch;
if (!idle)
frame *= 2;
d->ai->becareful = false;
}
scaleyawpitch(d->yaw, d->pitch, yaw, pitch, frame, sskew);
if (insight || quick)
{
if (canshoot(d, e) && hastarget(d, b, e, yaw, pitch, dp.squaredist(ep)))
{
d->attacking = true;
d->ai->lastaction = lastmillis;
result = 3;
}
else
result = 2;
}
else
result = 1;
}
else
{
if (!d->ai->enemyseen || lastmillis - d->ai->enemyseen > (d->skill * 50) + 3000)
{
d->ai->enemy = -1;
d->ai->enemyseen = d->ai->enemymillis = 0;
}
enemyok = false;
result = 0;
}
}
else
{
if (!enemyok)
{
d->ai->enemy = -1;
d->ai->enemyseen = d->ai->enemymillis = 0;
}
enemyok = false;
result = 0;
}
fixrange(d->ai->targyaw, d->ai->targpitch);
if (!result)
scaleyawpitch(d->yaw, d->pitch, d->ai->targyaw, d->ai->targpitch, frame * 0.25f, 1.f);
if (d->ai->becareful && d->physstate == PHYS_FALL)
{
float offyaw, offpitch;
vectoyawpitch(d->vel, offyaw, offpitch);
offyaw -= d->yaw;
offpitch -= d->pitch;
if (fabs(offyaw) + fabs(offpitch) >= 135)
d->ai->becareful = false;
else if (d->ai->becareful)
d->ai->dontmove = true;
}
else
d->ai->becareful = false;
if (d->ai->dontmove)
d->move = d->strafe = 0;
else
{ // our guys move one way.. but turn another?! :)
const struct aimdir
{
int move, strafe, offset;
} aimdirs[8] = {{1, 0, 0}, {1, -1, 45}, {0, -1, 90}, {-1, -1, 135},
{-1, 0, 180}, {-1, 1, 225}, {0, 1, 270}, {1, 1, 315}};
float yaw = d->ai->targyaw - d->yaw;
while (yaw < 0.0f)
yaw += 360.0f;
while (yaw >= 360.0f)
yaw -= 360.0f;
int r = clamp(((int)floor((yaw + 22.5f) / 45.0f)) & 7, 0, 7);
const aimdir &ad = aimdirs[r];
d->move = ad.move;
d->strafe = ad.strafe;
}
findorientation(dp, d->yaw, d->pitch, d->ai->target);
return result;
}
bool hasrange(fpsent *d, fpsent *e, int weap)
{
if (!e)
return true;
if (targetable(d, e))
{
vec ep = getaimpos(d, e);
float dist = ep.squaredist(d->headpos());
if (weaprange(d, weap, dist))
return true;
}
return false;
}
bool request(fpsent *d, aistate &b)
{
fpsent *e = getclient(d->ai->enemy);
if (!d->hasammo(d->gunselect) || !hasrange(d, e, d->gunselect) ||
(d->gunselect != d->ai->weappref && (!isgoodammo(d->gunselect) || d->hasammo(d->ai->weappref))))
{
static const int gunprefs[] = {GUN_CG, GUN_RL, GUN_SG, GUN_RIFLE, GUN_GL, GUN_PISTOL, GUN_FIST};
int gun = -1;
if (d->hasammo(d->ai->weappref) && hasrange(d, e, d->ai->weappref))
gun = d->ai->weappref;
else
{
loopi(sizeof(gunprefs) / sizeof(gunprefs[0])) if (d->hasammo(gunprefs[i]) &&
hasrange(d, e, gunprefs[i]))
{
gun = gunprefs[i];
break;
}
}
if (gun >= 0 && gun != d->gunselect)
gunselect(gun, d);
}
return process(d, b) >= 2;
}
void timeouts(fpsent *d, aistate &b)
{
if (d->blocked)
{
d->ai->blocktime += lastmillis - d->ai->lastrun;
if (d->ai->blocktime > (d->ai->blockseq + 1) * 1000)
{
d->ai->blockseq++;
switch (d->ai->blockseq)
{
case 1:
case 2:
case 3:
if (entities::ents.inrange(d->ai->targnode))
d->ai->addprevnode(d->ai->targnode);
d->ai->clear(false);
break;
case 4:
d->ai->reset(true);
break;
case 5:
d->ai->reset(false);
break;
case 6:
default:
suicide(d);
return;
break; // this is our last resort..
}
}
}
else
d->ai->blocktime = d->ai->blockseq = 0;
if (d->ai->targnode == d->ai->targlast)
{
d->ai->targtime += lastmillis - d->ai->lastrun;
if (d->ai->targtime > (d->ai->targseq + 1) * 1000)
{
d->ai->targseq++;
switch (d->ai->targseq)
{
case 1:
case 2:
case 3:
if (entities::ents.inrange(d->ai->targnode))
d->ai->addprevnode(d->ai->targnode);
d->ai->clear(false);
break;
case 4:
d->ai->reset(true);
break;
case 5:
d->ai->reset(false);
break;
case 6:
default:
suicide(d);
return;
break; // this is our last resort..
}
}
}
else
{
d->ai->targtime = d->ai->targseq = 0;
d->ai->targlast = d->ai->targnode;
}
if (d->ai->lasthunt)
{
int millis = lastmillis - d->ai->lasthunt;
if (millis <= 1000)
{
d->ai->tryreset = false;
d->ai->huntseq = 0;
}
else if (millis > (d->ai->huntseq + 1) * 1000)
{
d->ai->huntseq++;
switch (d->ai->huntseq)
{
case 1:
d->ai->reset(true);
break;
case 2:
d->ai->reset(false);
break;
case 3:
default:
suicide(d);
return;
break; // this is our last resort..
}
}
}
}
void logic(fpsent *d, aistate &b, bool run)
{
bool allowmove = canmove(d) && b.type != AI_S_WAIT;
if (d->state != CS_ALIVE || !allowmove)
d->stopmoving();
if (d->state == CS_ALIVE)
{
if (allowmove)
{
if (!request(d, b))
target(d, b, d->gunselect == GUN_FIST ? 1 : 0, b.idle ? true : false);
shoot(d, d->ai->target);
}
if (!intermission)
{
if (d->ragdoll)
cleanragdoll(d);
moveplayer(d, 10, true);
if (allowmove && !b.idle)
timeouts(d, b);
if (d->quadmillis)
entities::checkquad(curtime, d);
entities::checkitems(d);
if (cmode)
cmode->checkitems(d);
}
}
else if (d->state == CS_DEAD)
{
if (d->ragdoll)
moveragdoll(d);
else if (lastmillis - d->lastpain < 2000)
{
d->move = d->strafe = 0;
moveplayer(d, 10, false);
}
}
d->attacking = d->jumping = false;
}
void avoid()
{
// guess as to the radius of ai and other critters relying on the avoid set for now
float guessradius = player1->radius;
obstacles.clear();
loopv(players)
{
dynent *d = players[i];
if (d->state != CS_ALIVE)
continue;
obstacles.avoidnear(d, d->o.z + d->aboveeye + 1, d->feetpos(), guessradius + d->radius);
}
extern avoidset wpavoid;
obstacles.add(wpavoid);
avoidweapons(obstacles, guessradius);
}
void think(fpsent *d, bool run)
{
// the state stack works like a chain of commands, certain commands simply replace each other
// others spawn new commands to the stack the ai reads the top command from the stack and executes
// it or pops the stack and goes back along the history until it finds a suitable command to execute
bool cleannext = false;
if (d->ai->state.empty())
d->ai->addstate(AI_S_WAIT);
loopvrev(d->ai->state)
{
aistate &c = d->ai->state[i];
if (cleannext)
{
c.millis = lastmillis;
c.override = false;
cleannext = false;
}
if (d->state == CS_DEAD && d->respawned != d->lifesequence && (!cmode || cmode->respawnwait(d, 250) <= 0) &&
lastmillis - d->lastpain >= 500)
{
addmsg(N_TRYSPAWN, "rc", d);
d->respawned = d->lifesequence;
}
else if (d->state == CS_ALIVE && run)
{
int result = 0;
c.idle = 0;
switch (c.type)
{
case AI_S_WAIT:
result = dowait(d, c);
break;
case AI_S_DEFEND:
result = dodefend(d, c);
break;
case AI_S_PURSUE:
result = dopursue(d, c);
break;
case AI_S_INTEREST:
result = dointerest(d, c);
break;
default:
result = 0;
break;
}
if (result <= 0)
{
if (c.type != AI_S_WAIT)
{
switch (result)
{
case 0:
default:
d->ai->removestate(i);
cleannext = true;
break;
case -1:
i = d->ai->state.length() - 1;
break;
}
continue; // shouldn't interfere
}
}
}
logic(d, c, run);
break;
}
if (d->ai->trywipe)
d->ai->wipe();
d->ai->lastrun = lastmillis;
}
void drawroute(fpsent *d, float amt = 1.f)
{
int last = -1;
loopvrev(d->ai->route)
{
if (d->ai->route.inrange(last))
{
int index = d->ai->route[i], prev = d->ai->route[last];
if (iswaypoint(index) && iswaypoint(prev))
{
waypoint &e = waypoints[index], &f = waypoints[prev];
vec fr = f.o, dr = e.o;
fr.z += amt;
dr.z += amt;
particle_flare(fr, dr, 1, PART_STREAK, 0xFFFFFF);
}
}
last = i;
}
if (aidebug >= 5)
{
vec pos = d->feetpos();
if (d->ai->spot != vec(0, 0, 0))
particle_flare(pos, d->ai->spot, 1, PART_LIGHTNING, 0x00FFFF);
if (iswaypoint(d->ai->targnode))
particle_flare(pos, waypoints[d->ai->targnode].o, 1, PART_LIGHTNING, 0xFF00FF);
if (iswaypoint(d->lastnode))
particle_flare(pos, waypoints[d->lastnode].o, 1, PART_LIGHTNING, 0xFFFF00);
loopi(NUMPREVNODES) if (iswaypoint(d->ai->prevnodes[i]))
{
particle_flare(pos, waypoints[d->ai->prevnodes[i]].o, 1, PART_LIGHTNING, 0x884400);
pos = waypoints[d->ai->prevnodes[i]].o;
}
}
}
VAR(showwaypoints, 0, 0, 1);
VAR(showwaypointsradius, 0, 200, 10000);
const char *stnames[AI_S_MAX] = {"wait", "defend", "pursue", "interest"},
*sttypes[AI_T_MAX + 1] = {"none", "node", "player", "affinity", "entity"};
void render()
{
if (aidebug > 1)
{
int total = 0, alive = 0;
loopv(players) if (players[i]->ai) total++;
loopv(players) if (players[i]->state == CS_ALIVE && players[i]->ai)
{
fpsent *d = players[i];
vec pos = d->abovehead();
pos.z += 3;
alive++;
if (aidebug >= 4)
drawroute(d, 4.f * (float(alive) / float(total)));
if (aidebug >= 3)
{
defformatstring(q, "node: %d route: %d (%d)", d->lastnode,
!d->ai->route.empty() ? d->ai->route[0] : -1, d->ai->route.length());
particle_textcopy(pos, q, PART_TEXT, 1);
pos.z += 2;
}
bool top = true;
loopvrev(d->ai->state)
{
aistate &b = d->ai->state[i];
defformatstring(s, "%s%s (%d ms) %s:%d", top ? "\fg" : "\fy", stnames[b.type],
lastmillis - b.millis, sttypes[b.targtype + 1], b.target);
particle_textcopy(pos, s, PART_TEXT, 1);
pos.z += 2;
if (top)
{
if (aidebug >= 3)
top = false;
else
break;
}
}
if (aidebug >= 3)
{
if (d->ai->weappref >= 0 && d->ai->weappref < NUMGUNS)
{
particle_textcopy(pos, guns[d->ai->weappref].name, PART_TEXT, 1);
pos.z += 2;
}
fpsent *e = getclient(d->ai->enemy);
if (e)
{
particle_textcopy(pos, colorname(e), PART_TEXT, 1);
pos.z += 2;
}
}
}
if (aidebug >= 4)
{
int cur = 0;
loopv(obstacles.obstacles)
{
const avoidset::obstacle &ob = obstacles.obstacles[i];
int next = cur + ob.numwaypoints;
for (; cur < next; cur++)
{
int ent = obstacles.waypoints[cur];
if (iswaypoint(ent))
regular_particle_splash(PART_EDIT, 2, 40, waypoints[ent].o, 0xFF6600, 1.5f);
}
cur = next;
}
}
}
if (showwaypoints || aidebug >= 6)
{
vector<int> close;
int len = waypoints.length();
if (showwaypointsradius)
{
findwaypointswithin(camera1->o, 0, showwaypointsradius, close);
len = close.length();
}
loopi(len)
{
waypoint &w = waypoints[showwaypointsradius ? close[i] : i];
loopj(MAXWAYPOINTLINKS)
{
int link = w.links[j];
if (!link)
break;
particle_flare(w.o, waypoints[link].o, 1, PART_STREAK, 0x0000FF);
}
}
}
}
} // namespace ai
|
; int vfprintf_unlocked(FILE *stream, const char *format, void *arg)
SECTION code_clib
SECTION code_stdio
PUBLIC vfprintf_unlocked
EXTERN asm_vfprintf_unlocked
vfprintf_unlocked:
pop af
pop bc
pop de
pop ix
push hl
push de
push bc
push af
jp asm_vfprintf_unlocked
|
; A040481: Continued fraction for sqrt(504).
; 22,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2,44,2,4,2
mov $1,4
mov $2,$0
gcd $2,4
pow $1,$2
lpb $0
mov $0,1
mul $1,2
lpe
div $1,24
mul $1,2
add $1,2
mov $0,$1
|
MOD_A: BEGIN
SECTION TEXT
MOD_B: EXTERN
PUBLIC FAT
PUBLIC N
INPUT N
LOAD N
FAT: SUB ONE
JMPZ FIM
JMP MOD_B
FIM: OUTPUT N
STOP
SECTION BSS
N: SPACE
SECTION DATA
ONE: CONST 1
END
|
;++
;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
; Licensed under the MIT License.
;
; Module Name:
;
; SgemmKernelAvx512F.asm
;
; Abstract:
;
; This module implements the kernels for the single precision matrix/matrix
; multiply operation (SGEMM).
;
; This implementation uses AVX512F instructions.
;
;--
.xlist
INCLUDE mlasi.inc
INCLUDE SgemmKernelCommon.inc
.list
;
; ComputeBlockAvx512FBy32
;
; This macro multiplies and accumulates for a 32xN block of the output matrix.
;
; Arguments:
;
; Count - Supplies the number of rows to access from matrix A.
;
; VectorOffset - Supplies the byte offset from matrix B to fetch elements.
;
; BroadcastOffset - Supplies the byte offset from matrix A to fetch elements.
;
; PrefetchOffset - Optionally supplies the byte offset from matrix B to
; prefetch elements.
;
; Implicit Arguments:
;
; rbx - Supplies the address into the matrix A data plus 3 rows.
;
; rcx - Supplies the address into the matrix A data.
;
; rdx - Supplies the address into the matrix B data.
;
; r10 - Supplies the length in bytes of a row from matrix A.
;
; r13 - Supplies the address into the matrix A data plus 6 rows.
;
; r14 - Supplies the address into the matrix A data plus 9 rows.
;
; zmm4-zmm27 - Supplies the block accumulators.
;
ComputeBlockAvx512FBy32 MACRO Count, VectorOffset, BroadcastOffset, PrefetchOffset
IFNB <PrefetchOffset>
prefetcht0 [rdx+VectorOffset+PrefetchOffset]
prefetcht0 [rdx+r12+VectorOffset+PrefetchOffset]
ENDIF
IF Count EQ 1
vbroadcastss zmm3,DWORD PTR [rcx+BroadcastOffset]
vfmadd231ps zmm4,zmm3,ZMMWORD PTR [rdx+VectorOffset]
vfmadd231ps zmm5,zmm3,ZMMWORD PTR [rdx+r12+VectorOffset]
ELSE
vmovaps zmm0,ZMMWORD PTR [rdx+VectorOffset]
vmovaps zmm1,ZMMWORD PTR [rdx+r12+VectorOffset]
EmitIfCountGE Count, 1, <vbroadcastss zmm3,DWORD PTR [rcx+BroadcastOffset]>
EmitIfCountGE Count, 1, <vfmadd231ps zmm4,zmm3,zmm0>
EmitIfCountGE Count, 1, <vfmadd231ps zmm5,zmm3,zmm1>
EmitIfCountGE Count, 2, <vbroadcastss zmm3,DWORD PTR [rcx+r10+BroadcastOffset]>
EmitIfCountGE Count, 2, <vfmadd231ps zmm6,zmm3,zmm0>
EmitIfCountGE Count, 2, <vfmadd231ps zmm7,zmm3,zmm1>
EmitIfCountGE Count, 3, <vbroadcastss zmm3,DWORD PTR [rcx+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 3, <vfmadd231ps zmm8,zmm3,zmm0>
EmitIfCountGE Count, 3, <vfmadd231ps zmm9,zmm3,zmm1>
EmitIfCountGE Count, 4, <vbroadcastss zmm3,DWORD PTR [rbx+BroadcastOffset]>
EmitIfCountGE Count, 4, <vfmadd231ps zmm10,zmm3,zmm0>
EmitIfCountGE Count, 4, <vfmadd231ps zmm11,zmm3,zmm1>
EmitIfCountGE Count, 5, <vbroadcastss zmm3,DWORD PTR [rbx+r10+BroadcastOffset]>
EmitIfCountGE Count, 5, <vfmadd231ps zmm12,zmm3,zmm0>
EmitIfCountGE Count, 5, <vfmadd231ps zmm13,zmm3,zmm1>
EmitIfCountGE Count, 6, <vbroadcastss zmm3,DWORD PTR [rbx+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 6, <vfmadd231ps zmm14,zmm3,zmm0>
EmitIfCountGE Count, 6, <vfmadd231ps zmm15,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r13+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm16,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm17,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r13+r10+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm18,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm19,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r13+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm20,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm21,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r14+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm22,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm23,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r14+r10+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm24,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm25,zmm3,zmm1>
EmitIfCountGE Count, 12, <vbroadcastss zmm3,DWORD PTR [r14+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm26,zmm3,zmm0>
EmitIfCountGE Count, 12, <vfmadd231ps zmm27,zmm3,zmm1>
ENDIF
ENDM
;
; ComputeBlockAvx512FBy16
;
; This macro multiplies and accumulates for a 16xN block of the output matrix.
;
; Arguments:
;
; Count - Supplies the number of rows to access from matrix A.
;
; VectorOffset - Supplies the byte offset from matrix B to fetch elements.
;
; BroadcastOffset - Supplies the byte offset from matrix A to fetch elements.
;
; PrefetchOffset - Optionally supplies the byte offset from matrix B to
; prefetch elements.
;
; Implicit Arguments:
;
; rbx - Supplies the address into the matrix A data plus 3 rows.
;
; rcx - Supplies the address into the matrix A data.
;
; rdx - Supplies the address into the matrix B data.
;
; r10 - Supplies the length in bytes of a row from matrix A.
;
; r13 - Supplies the address into the matrix A data plus 6 rows.
;
; r14 - Supplies the address into the matrix A data plus 9 rows.
;
; zmm4-zmm27 - Supplies the block accumulators.
;
ComputeBlockAvx512FBy16 MACRO Count, VectorOffset, BroadcastOffset, PrefetchOffset
IFNB <PrefetchOffset>
prefetcht0 [rdx+VectorOffset+PrefetchOffset]
ENDIF
vmovaps zmm0,ZMMWORD PTR [rdx+VectorOffset]
EmitIfCountGE Count, 1, <vfmadd231ps zmm5,zmm0,DWORD BCST [rcx+BroadcastOffset]>
EmitIfCountGE Count, 2, <vfmadd231ps zmm7,zmm0,DWORD BCST [rcx+r10+BroadcastOffset]>
EmitIfCountGE Count, 3, <vfmadd231ps zmm9,zmm0,DWORD BCST [rcx+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 4, <vfmadd231ps zmm11,zmm0,DWORD BCST [rbx+BroadcastOffset]>
EmitIfCountGE Count, 5, <vfmadd231ps zmm13,zmm0,DWORD BCST [rbx+r10+BroadcastOffset]>
EmitIfCountGE Count, 6, <vfmadd231ps zmm15,zmm0,DWORD BCST [rbx+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm17,zmm0,DWORD BCST [r13+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm19,zmm0,DWORD BCST [r13+r10+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm21,zmm0,DWORD BCST [r13+r10*2+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm23,zmm0,DWORD BCST [r14+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm25,zmm0,DWORD BCST [r14+r10+BroadcastOffset]>
EmitIfCountGE Count, 12, <vfmadd231ps zmm27,zmm0,DWORD BCST [r14+r10*2+BroadcastOffset]>
ENDM
;
; ComputeBlockAvx512FLoop
;
; This macro generates code to execute the block compute macro multiple
; times and advancing the matrix A and matrix B data pointers.
;
; Arguments:
;
; ComputeBlock - Supplies the macro to compute a single block.
;
; Count - Supplies the number of rows to access from matrix A.
;
; Implicit Arguments:
;
; rbx - Supplies the address into the matrix A data plus N rows.
;
; rcx - Supplies the address into the matrix A data.
;
; rdx - Supplies the address into the matrix B data.
;
; r9 - Supplies the number of columns from matrix A and the number of rows
; from matrix B to iterate over.
;
; ymm4-ymm15 - Supplies the block accumulators.
;
ComputeBlockAvx512FLoop MACRO ComputeBlock, Count
IF Count GT 3
lea rbx,[r10*2+r10]
IF Count EQ 12
lea r13,[rcx+rbx*2] ; compute matrix A plus 6 rows
lea r14,[r13+rbx] ; compute matrix A plus 9 rows
ENDIF
add rbx,rcx ; compute matrix A plus 3 rows
ENDIF
ComputeBlockLoop ComputeBlock, Count, <Count GT 3>
IF Count GT 3
lea rbx,[rax*2+rax]
IF Count EQ 12
lea r13,[r8+rbx*2] ; compute matrix C plus 6 rows
lea r14,[r13+rbx] ; compute matrix C plus 9 rows
ENDIF
add rbx,r8 ; compute matrix C plus 3 rows
ENDIF
ENDM
;
; ProcessCountMAvx512F
;
; Macro Description:
;
; This macro generates code to compute matrix multiplication for a fixed set
; of rows.
;
; Arguments:
;
; Mode - Supplies the mode of operation for updating the contents of matrix C.
;
; Count - Supplies the number of rows to process.
;
; Implicit Arguments:
;
; rcx - Supplies the address of matrix A.
;
; rdx - Supplies the address of matrix B.
;
; rsi - Supplies the address of matrix A.
;
; rbp - Supplies the number of columns from matrix B and matrix C to iterate
; over.
;
; r8 - Supplies the address of matrix C.
;
; r9 - Supplies the number of columns from matrix A and the number of rows
; from matrix B to iterate over.
;
; r10 - Supplies the length in bytes of a row from matrix A.
;
ProcessCountMAvx512F MACRO Mode, Count
LOCAL ProcessNextColumnLoop32xN
LOCAL Output16xNBlock
LOCAL Output16xNBlockWithMask
LOCAL ProcessRemainingCountN
cmp rbp,16
jbe ProcessRemainingCountN
ProcessNextColumnLoop32xN:
EmitIfCountGE Count, 12, <vmovaps zmm16,zmm4>
; clear upper block accumulators
EmitIfCountGE Count, 12, <vmovaps zmm17,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm18,zmm4>
EmitIfCountGE Count, 12, <vmovaps zmm19,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm20,zmm4>
EmitIfCountGE Count, 12, <vmovaps zmm21,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm22,zmm4>
EmitIfCountGE Count, 12, <vmovaps zmm23,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm24,zmm4>
EmitIfCountGE Count, 12, <vmovaps zmm25,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm26,zmm4>
EmitIfCountGE Count, 12, <vmovaps zmm27,zmm5>
ComputeBlockAvx512FLoop ComputeBlockAvx512FBy32, Count
add rdx,r12 ; advance matrix B by 16*CountK floats
IFDIFI <Mode>, <Add>
EmitIfCountGE Count, 1, <vmulps zmm4,zmm4,zmm31>
EmitIfCountGE Count, 2, <vmulps zmm6,zmm6,zmm31>
EmitIfCountGE Count, 3, <vmulps zmm8,zmm8,zmm31>
EmitIfCountGE Count, 4, <vmulps zmm10,zmm10,zmm31>
EmitIfCountGE Count, 5, <vmulps zmm12,zmm12,zmm31>
EmitIfCountGE Count, 6, <vmulps zmm14,zmm14,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm16,zmm16,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm18,zmm18,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm20,zmm20,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm22,zmm22,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm24,zmm24,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm26,zmm26,zmm31>
ELSE
EmitIfCountGE Count, 1, <vfmadd213ps zmm4,zmm31,ZMMWORD PTR [r8]>
EmitIfCountGE Count, 2, <vfmadd213ps zmm6,zmm31,ZMMWORD PTR [r8+rax]>
EmitIfCountGE Count, 3, <vfmadd213ps zmm8,zmm31,ZMMWORD PTR [r8+rax*2]>
EmitIfCountGE Count, 4, <vfmadd213ps zmm10,zmm31,ZMMWORD PTR [rbx]>
EmitIfCountGE Count, 5, <vfmadd213ps zmm12,zmm31,ZMMWORD PTR [rbx+rax]>
EmitIfCountGE Count, 6, <vfmadd213ps zmm14,zmm31,ZMMWORD PTR [rbx+rax*2]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm16,zmm31,ZMMWORD PTR [r13]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm18,zmm31,ZMMWORD PTR [r13+rax]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm20,zmm31,ZMMWORD PTR [r13+rax*2]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm22,zmm31,ZMMWORD PTR [r14]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm24,zmm31,ZMMWORD PTR [r14+rax]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm26,zmm31,ZMMWORD PTR [r14+rax*2]>
ENDIF
EmitIfCountGE Count, 1, <vmovups ZMMWORD PTR [r8],zmm4>
EmitIfCountGE Count, 2, <vmovups ZMMWORD PTR [r8+rax],zmm6>
EmitIfCountGE Count, 3, <vmovups ZMMWORD PTR [r8+rax*2],zmm8>
EmitIfCountGE Count, 4, <vmovups ZMMWORD PTR [rbx],zmm10>
EmitIfCountGE Count, 5, <vmovups ZMMWORD PTR [rbx+rax],zmm12>
EmitIfCountGE Count, 6, <vmovups ZMMWORD PTR [rbx+rax*2],zmm14>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13],zmm16>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13+rax],zmm18>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13+rax*2],zmm20>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14],zmm22>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14+rax],zmm24>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14+rax*2],zmm26>
add r8,16*4 ; advance matrix C by 16 columns
IF Count GT 3
add rbx,16*4 ; advance matrix C plus 3 rows by 16 columns
add r13,16*4 ; advance matrix C plus 6 rows by 16 columns
add r14,16*4 ; advance matrix C plus 9 rows by 16 columns
ENDIF
sub rbp,16
Output16xNBlock:
sub rbp,16
jae Output16xNBlockWithMask
lea ecx,[ebp+16] ; correct for over-subtract above
mov edi,1
shl edi,cl
dec edi
kmovw k1,edi ; update mask for remaining columns
xor ebp,ebp ; no more columns remaining
Output16xNBlockWithMask:
IFDIFI <Mode>, <Add>
EmitIfCountGE Count, 1, <vmulps zmm5,zmm5,zmm31>
EmitIfCountGE Count, 2, <vmulps zmm7,zmm7,zmm31>
EmitIfCountGE Count, 3, <vmulps zmm9,zmm9,zmm31>
EmitIfCountGE Count, 4, <vmulps zmm11,zmm11,zmm31>
EmitIfCountGE Count, 5, <vmulps zmm13,zmm13,zmm31>
EmitIfCountGE Count, 6, <vmulps zmm15,zmm15,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm17,zmm17,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm19,zmm19,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm21,zmm21,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm23,zmm23,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm25,zmm25,zmm31>
EmitIfCountGE Count, 12, <vmulps zmm27,zmm27,zmm31>
ELSE
EmitIfCountGE Count, 1, <vfmadd213ps zmm5{k1},zmm31,ZMMWORD PTR [r8]>
EmitIfCountGE Count, 2, <vfmadd213ps zmm7{k1},zmm31,ZMMWORD PTR [r8+rax]>
EmitIfCountGE Count, 3, <vfmadd213ps zmm9{k1},zmm31,ZMMWORD PTR [r8+rax*2]>
EmitIfCountGE Count, 4, <vfmadd213ps zmm11{k1},zmm31,ZMMWORD PTR [rbx]>
EmitIfCountGE Count, 5, <vfmadd213ps zmm13{k1},zmm31,ZMMWORD PTR [rbx+rax]>
EmitIfCountGE Count, 6, <vfmadd213ps zmm15{k1},zmm31,ZMMWORD PTR [rbx+rax*2]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm17{k1},zmm31,ZMMWORD PTR [r13]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm19{k1},zmm31,ZMMWORD PTR [r13+rax]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm21{k1},zmm31,ZMMWORD PTR [r13+rax*2]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm23{k1},zmm31,ZMMWORD PTR [r14]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm25{k1},zmm31,ZMMWORD PTR [r14+rax]>
EmitIfCountGE Count, 12, <vfmadd213ps zmm27{k1},zmm31,ZMMWORD PTR [r14+rax*2]>
ENDIF
EmitIfCountGE Count, 1, <vmovups ZMMWORD PTR [r8]{k1},zmm5>
EmitIfCountGE Count, 2, <vmovups ZMMWORD PTR [r8+rax]{k1},zmm7>
EmitIfCountGE Count, 3, <vmovups ZMMWORD PTR [r8+rax*2]{k1},zmm9>
EmitIfCountGE Count, 4, <vmovups ZMMWORD PTR [rbx]{k1},zmm11>
EmitIfCountGE Count, 5, <vmovups ZMMWORD PTR [rbx+rax]{k1},zmm13>
EmitIfCountGE Count, 6, <vmovups ZMMWORD PTR [rbx+rax*2]{k1},zmm15>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13]{k1},zmm17>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13+rax]{k1},zmm19>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r13+rax*2]{k1},zmm21>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14]{k1},zmm23>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14+rax]{k1},zmm25>
EmitIfCountGE Count, 12, <vmovups ZMMWORD PTR [r14+rax*2]{k1},zmm27>
add r8,16*4 ; advance matrix C by 16 columns
mov rcx,rsi ; reload matrix A
vzeroall
cmp rbp,16
ja ProcessNextColumnLoop32xN
test rbp,rbp
jz ExitKernel
ProcessRemainingCountN:
EmitIfCountGE Count, 12, <vmovaps zmm17,zmm5>
; clear upper block accumulators
EmitIfCountGE Count, 12, <vmovaps zmm19,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm21,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm23,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm25,zmm5>
EmitIfCountGE Count, 12, <vmovaps zmm27,zmm5>
ComputeBlockAvx512FLoop ComputeBlockAvx512FBy16, Count
jmp Output16xNBlock
ENDM
;++
;
; Routine Description:
;
; This routine is an inner kernel to compute matrix multiplication for a
; set of rows.
;
; Arguments:
;
; A (rcx) - Supplies the address of matrix A.
;
; B (rdx) - Supplies the address of matrix B. The matrix data has been packed
; using MlasSgemmCopyPackB or MlasSgemmTransposePackB.
;
; C (r8) - Supplies the address of matrix C.
;
; CountK (r9) - Supplies the number of columns from matrix A and the number
; of rows from matrix B to iterate over.
;
; CountM - Supplies the maximum number of rows that can be processed for
; matrix A and matrix C. The actual number of rows handled for this
; invocation depends on the kernel implementation.
;
; CountN - Supplies the number of columns from matrix B and matrix C to iterate
; over.
;
; lda - Supplies the first dimension of matrix A.
;
; ldc - Supplies the first dimension of matrix C.
;
; Alpha - Supplies the scaler multiplier (see SGEMM definition).
;
; Return Value:
;
; Returns the number of rows handled.
;
;--
SgemmKernelAvx512FFunction MACRO Mode
NESTED_ENTRY MlasSgemmKernel&Mode&Avx512F, _TEXT
SgemmKernelAvxEntry SaveExtra
mov r12,r9
shl r12,6 ; compute 16*CountK*sizeof(float)
mov edi,-1
kmovw k1,edi ; update mask to write all columns
vbroadcastss zmm31,DWORD PTR SgemmKernelFrame.Alpha[rsp]
;
; Process N rows of the matrices.
;
cmp r11,12
jb ProcessCountMLessThan12
mov r11d,12 ; return 12 rows handled
ProcessCountMAvx512F Mode, 12
ProcessCountMLessThan12:
cmp r11,5
ja ProcessCountM6
je ProcessCountM5
cmp r11,3
ja ProcessCountM4
je ProcessCountM3
cmp r11,1
je ProcessCountM1
ProcessCountM2:
ProcessCountMAvx512F Mode, 2
ProcessCountM4:
ProcessCountMAvx512F Mode, 4
ProcessCountM6:
mov r11d,6 ; return 6 rows handled
ProcessCountMAvx512F Mode, 6
;
; Restore non-volatile registers and return.
;
ExitKernel:
SgemmKernelAvxExit RestoreExtra
ProcessCountM1:
ProcessCountMAvx512F Mode, 1
ProcessCountM3:
ProcessCountMAvx512F Mode, 3
ProcessCountM5:
ProcessCountMAvx512F Mode, 5
NESTED_END MlasSgemmKernel&Mode&Avx512F, _TEXT
ENDM
SgemmKernelAvx512FFunction Zero
SgemmKernelAvx512FFunction Add
END
|
MODULE __printf_number
SECTION code_clib
PUBLIC __printf_number
EXTERN __printf_print_to_buf
EXTERN __printf_print_the_buffer
EXTERN l_int2long_s
EXTERN l_long_neg
EXTERN l_long_div_u
EXTERN l_div_u
EXTERN l_neg
EXTERN get_16bit_ap_parameter
EXTERN __printf_add_offset
EXTERN __printf_issccz80
EXTERN __printf_get_base
EXTERN __printf_check_long_flag
EXTERN __printf_context
EXTERN __math_block2
defc handlelong = 1
; Print a number
; Entry: hl = fmt (character after format)
; de = ap
; c = 1 = signed, 0 = unsigned
__printf_number:
push hl ;save fmt
IF __CPU_INTEL__ | __CPU_GBZ80__
call __printf_check_long_flag
ELSE
bit 6,(ix-4)
ENDIF
jr z,printf_number16
IF __CPU_INTEL__ | __CPU_GBZ80__
call __printf_issccz80
ELSE
bit 0,(ix+6) ;sccz80 flag
ENDIF
jr nz,pickuplong_sccz80
; Picking up a long sdcc style
ex de,hl ;hl=where tp pick up from
ld e,(hl) ;LSW
inc hl
ld d,(hl)
inc hl
IF __CPU_GBZ80__
ld a,(hl+)
ELSE
ld a,(hl)
inc hl
ENDIF
ld b,(hl)
inc hl
push hl ; save ap
ld h,b
ld l,a
ex de,hl ;dehl=long, c: 1=signed, 0=unsigned
printlong:
ld a,c
jp miniprintn
pickuplong_sccz80:
ex de,hl
ld e,(hl) ;MSW
inc hl
ld d,(hl)
dec hl
dec hl
ld b,(hl) ;LSW
dec hl
IF __CPU_GBZ80__
ld a,(hl-)
ELSE
ld a,(hl)
dec hl
ENDIF
dec hl
push hl ;Save ap for next time
ld h,b
ld l,a
jr printlong
printf_number16:
call get_16bit_ap_parameter ;de = new ap, hl = number to print
push de ; save ap
ld de,0 ;make it a long
ld a,c ;signed?
and a
call nz,l_int2long_s ;extend it out
jr printlong
; Entry: a = flag (0=unsigned, 1 = signed)
; dehl = number
miniprintn:
ld b,a
IF handlelong
ld a,d
ELSE
ld a,h
ENDIF
rlca
and 1
and b
jr z,noneg
IF handlelong
call l_long_neg
ELSE
call l_neg
ENDIF
ld a,'-'
printsign:
call __printf_print_to_buf
jr miniprintn_start_process
noneg:
IF __CPU_INTEL__ || __CPU_GBZ80__
push hl
IF __CPU_GBZ80__
ld hl,__printf_context
ld a,(hl+)
ld h,(hl)
ld l,a
ELSE
ld hl,(__printf_context)
ENDIF
dec hl
dec hl
dec hl
dec hl
ld c,l
ld b,h
pop hl
ld a,(bc)
and 8
ld a,' '
jr nz,printsign
ld a,(bc)
and 2
ld a,'+'
jr nz,printsign
ld a,(bc)
and 16
jr z,miniprintn_start_process
ELSE
ld a,' '
bit 3,(ix-4)
jr nz,printsign
ld a,'+'
bit 1,(ix-4) ;do we force a +
jr nz,printsign
bit 4,(ix-4) ;# indicator
jr z,miniprintn_start_process
ENDIF
IF __CPU_INTEL__ | __CPU_GBZ80__
push hl
call __printf_get_base
ld a,l
pop hl
ELSE
ld a,(ix-9) ;get base
ENDIF
cp 10
jr z,miniprintn_start_process
push af
ld a,'0'
call __printf_print_to_buf
pop af
cp 16
jr nz,miniprintn_start_process
ld a,'x'
IF __CPU_INTEL__ | __CPU_GBZ80__
call __printf_add_offset
ELSE
add (ix-3)
ENDIF
call __printf_print_to_buf
miniprintn_start_process:
xor a
push af ; set terminator
.divloop
IF handlelong
IF __CPU_INTEL__ | __CPU_GBZ80__
push de ; number MSW
push hl ; number LSW
call __printf_get_base
ld d,h
ld e,h
call l_long_div_u
ld a,(__math_block2) ;We know that's where the modulus is kept
cp 255
push af
ELSE
push de ; number MSW
push hl ; number LSW
ld l,(ix-9) ;base
ld h,0
ld d,h
ld e,h
call l_long_div_u
exx
ld a,l
cp 255 ; force flag to non-zero
push af ; save reminder as a digit in stack
exx
ENDIF
ELSE
ex de,hl
IF __CPU_INTEL__ | __CPU_GBZ80__
call __printf_get_base
ELSE
ld l,(ix-9) ;base
ld h,0
ENDIF
call l_div_u ;hl=de/hl de=de%hl
ld a,e
cp 255 ; force flag to non-zero
push af ; save reminder as a digit in stack
ENDIF
ld a,h
IF handlelong
or d
or e
ENDIF
or l ; is integer part of last division zero ?
jr nz,divloop ; not still ?.. loop
; now recurse for the single digit
; pick all from stack until you get the terminator
;
.printloop
pop af
jp z,__printf_print_the_buffer
add '0'
; We only print hex at level 2
cp '9'+1
jr c,printloop1
add 'a' - '9' -1
IF __CPU_INTEL__ | __CPU_GBZ80__
call __printf_add_offset
ELSE
add (ix-3)
ENDIF
printloop1:
call __printf_print_to_buf
jr printloop
|
; Copyright 2021 Carl Georg Biermann
; This file contains a range of macros used by the synth engine.
; Some macros do VERA stuff, some macros do various types of
; multiplication. Some are for memory allocation.
; Synth engine definitions
.define N_VOICES 16
.define N_TIMBRES 32
.define N_OSCILLATORS 16 ; total number of PSG voices, which correspond to oscillators
.define N_FM_VOICES 8
.define MAX_OSCS_PER_VOICE 4
.define MAX_ENVS_PER_VOICE 3
.define MAX_LFOS_PER_VOICE 1
.define N_TOT_MODSOURCES MAX_ENVS_PER_VOICE+MAX_LFOS_PER_VOICE
.define MAX_VOLUME 63
.define MAX_VOLUME_INTERNAL 64
.define ENV_PEAK 127
.define N_OPERATORS 4
.define MAX_FILENAME_LENGTH 8
.define FILE_VERSION 0 ; 0-255 specifying which version of Concerto presets is used
.macro VOICE_BYTE_FIELD
.repeat N_VOICES, I
.byte 0
.endrep
.endmacro
.macro TIMBRE_BYTE_FIELD
.repeat N_TIMBRES, I
.byte 0
.endrep
.endmacro
.macro OSCILLATOR_BYTE_FIELD
.repeat N_OSCILLATORS, I
.byte 0
.endrep
.endmacro
; osc1: timbre1 timbre2 timbre3 ... osc2: timbre1 timbre2 timbre3 ...
; ---> this format saves multiplication when accessing with arbitrary timbre indes
.macro OSCILLATOR_TIMBRE_BYTE_FIELD
.repeat MAX_OSCS_PER_VOICE*N_TIMBRES
.byte 0
.endrep
.endmacro
; osc1: voice1 voice2 voice3 ... osc2: voice1 voice2 voice3 ...
.macro OSCILLATOR_VOICE_BYTE_FIELD
.repeat MAX_OSCS_PER_VOICE*N_VOICES
.byte 0
.endrep
.endmacro
; env1: timbre1 timbre2 timbre3 ... env2: timbre1 timbre2 tibre3 ...
; ---> this format saves multiplication when accessing with arbitrary timbre indices
.macro ENVELOPE_TIMBRE_BYTE_FIELD
.repeat MAX_ENVS_PER_VOICE*N_TIMBRES
.byte 0
.endrep
.endmacro
; env1: voice1 voice2 voice3 ... env2: voice1 voice2 voice3 ...
.macro ENVELOPE_VOICE_BYTE_FIELD
.repeat MAX_ENVS_PER_VOICE*N_VOICES
.byte 0
.endrep
.endmacro
; lfo1: timbre1 timbre2 timbre3 ... lfo2: timbre1 timbre2 tibre3 ...
; ---> this format saves multiplication when accessing with arbitrary timbre indices
.macro LFO_TIMBRE_BYTE_FIELD
.repeat MAX_LFOS_PER_VOICE*N_TIMBRES
.byte 0
.endrep
.endmacro
; lfo1: voice1 voice2 voice3 ... lfo2: voice1 voice2 voice3 ...
.macro LFO_VOICE_BYTE_FIELD
.repeat MAX_LFOS_PER_VOICE*N_VOICES
.byte 0
.endrep
.endmacro
.macro OPERATOR_TIMBRE_BYTE_FIELD
.repeat N_OPERATORS*N_TIMBRES
.byte 0
.endrep
.endmacro
.macro FM_VOICE_BYTE_FIELD
.repeat N_FM_VOICES
.byte 0
.endrep
.endmacro
.ifndef SYNTH_MACROS_INC
SYNTH_MACROS_INC = 1
.macro VERA_SET_VOICE_PARAMS n_voice, frequency, volume, waveform
VERA_SET_ADDR $1F9C0+4*n_voice, 1
stz VERA_ctrl
lda #<frequency
sta VERA_data0
lda #>frequency
sta VERA_data0
lda #volume
sta VERA_data0
lda #waveform
sta VERA_data0
.endmacro
; parameters in memory, but PSG voice number A
.macro VERA_SET_VOICE_PARAMS_MEM_A frequency, volume, waveform
pha
lda #$11
sta VERA_addr_high
lda #$F9
sta VERA_addr_mid
pla
asl
asl
clc
adc #$C0
sta VERA_addr_low
stz VERA_ctrl
lda frequency
sta VERA_data0
lda frequency+1
sta VERA_data0
lda volume
sta VERA_data0
lda waveform
sta VERA_data0
.endmacro
; mutes a voice
.macro VERA_MUTE_VOICE n_voice
VERA_SET_ADDR ($1F9C0+4*n_voice+2), 1
lda #0
sta VERA_ctrl
stz VERA_data0
.endmacro
; sets volume to value stored in register X
.macro VERA_SET_VOICE_VOLUME_X n_voice, channels
VERA_SET_ADDR ($1F9C0+4*n_voice+2), 1
lda #0
sta VERA_ctrl
txa
clc
adc #channels
sta VERA_data0
.endmacro
; mutes PSG voice with index stored in register X
.macro VERA_MUTE_VOICE_X
lda #$11
sta VERA_addr_high
lda #$F9
sta VERA_addr_mid
txa
asl
asl
clc
adc #$C2
sta VERA_addr_low
stz VERA_ctrl
stz VERA_data0
.endmacro
; mutes PSG voice with index stored in register A
.macro VERA_MUTE_VOICE_A
pha
lda #$11
sta VERA_addr_high
lda #$F9
sta VERA_addr_mid
pla
asl
asl
clc
adc #$C2
sta VERA_addr_low
stz VERA_ctrl
stz VERA_data0
.endmacro
; sets volume to value stored in register X
.macro VERA_SET_VOICE_FREQUENCY svf_n_voice, svf_frequency
VERA_SET_ADDR ($1F9C0+4*svf_n_voice), 1
lda #0
sta VERA_ctrl
lda svf_frequency
sta VERA_data0
lda svf_frequency+1
sta VERA_data0
.endmacro
; naive writing to a register in the YM2151
; Potentially burns a lot of cycles in the waiting loop
.macro SET_YM reg, data
: bit YM_data
bmi :-
lda #reg
sta YM_reg
lda #data
sta YM_data
.endmacro
; In this macro, the slide distance is multiplied by the portamento (base-)rate.
; The result is the effective portamento rate.
; It guarantees that the portamento time is constant regardless of how far
; two notes are apart.
; Expects voice index in X, timbre index in Y, slide distance in mzpbb
.macro MUL8x8_PORTA ; uses ZP variables in the process
mp_slide_distance = mzpbb ; must be the same as in "continue_note"!
mp_return_value = mzpwb
; the idea is that portamento is finished in a constant time
; that means, rate must be higher, the larger the porta distance is
; This is achieved by multiplying the "base rate" by the porta distance
; initialization
; mp_return_value stores the porta rate. It needs a 16 bit variable because it is left shifted
; throughout the multiplication
lda timbres::Timbre::porta_r, y
sta mp_return_value+1
stz mp_return_value
stz Voice::pitch_slide::rateL, x
stz Voice::pitch_slide::rateH, x
; multiplication
bbr0 mp_slide_distance, :+
lda mp_return_value+1
sta Voice::pitch_slide::rateL, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr1 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr2 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr3 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr4 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr5 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr6 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: clc
rol mp_return_value+1
rol mp_return_value
bbr7 mp_slide_distance, :+
clc
lda mp_return_value+1
adc Voice::pitch_slide::rateL, x
sta Voice::pitch_slide::rateL, x
lda mp_return_value
adc Voice::pitch_slide::rateH, x
sta Voice::pitch_slide::rateH, x
: ; check if porta going down. if yes, invert rate
lda Voice::pitch_slide::active, x
cmp #2
bne :+
lda Voice::pitch_slide::rateL, x
eor #%11111111
inc
sta Voice::pitch_slide::rateL, x
lda Voice::pitch_slide::rateH, x
eor #%11111111
sta Voice::pitch_slide::rateH, x
:
.endmacro
; computes the frequency of a given pitch+fine combo
; may have to redo it with indirect mode for more flexibility later
; Pitch Computation Variables
; TODO: replace some CLC-ROR by LSR
.macro COMPUTE_FREQUENCY cf_pitch, cf_fine, cf_output ; done in ISR
.local @skip_bit0
.local @skip_bit1
.local @skip_bit2
.local @skip_bit3
.local @skip_bit4
.local @skip_bit5
.local @skip_bit6
.local @skip_bit7
ldx cf_pitch
; copy lower frequency to output
lda pitch_dataL,x
sta cf_output
lda pitch_dataH,x
sta cf_output+1 ; 20 cycles
; compute difference between higher and lower frequency
ldy cf_pitch
iny
sec
lda pitch_dataL,y
sbc pitch_dataL,x
sta mzpwb ; here: contains frequency difference between the two adjacent half steps
lda pitch_dataH,y
sbc pitch_dataH,x
sta mzpwb+1 ; 32 cycles
; add 0.fine * mzpwb to output
lda cf_fine
sta mzpbf ; 7 cycles
clc
ror mzpwb+1
ror mzpwb
bbr7 mzpbf, @skip_bit7
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1 ; 38 cycles
@skip_bit7:
clc
ror mzpwb+1
ror mzpwb
bbr6 mzpbf, @skip_bit6
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit6:
clc
ror mzpwb+1
ror mzpwb
bbr5 mzpbf, @skip_bit5
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit5:
clc
ror mzpwb+1
ror mzpwb
bbr4 mzpbf, @skip_bit4
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit4:
clc
ror mzpwb+1
ror mzpwb
bbr3 mzpbf, @skip_bit3
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit3:
clc
ror mzpwb+1
ror mzpwb
bbr2 mzpbf, @skip_bit2
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit2:
clc
ror mzpwb+1
ror mzpwb
bbr1 mzpbf, @skip_bit1
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1
@skip_bit1:
clc
ror mzpwb+1
ror mzpwb
bbr0 mzpbf, @skip_bit0
clc
lda mzpwb
adc cf_output
sta cf_output
lda mzpwb+1
adc cf_output+1
sta cf_output+1 ; 38 * 8 cycles = 304 cycles
; total 373 cycles + page crossings ~= 47 us
@skip_bit0:
.endmacro
; This macro multiplies the value in the accumulator with a value in memory.
; Only the 7 lowest bits of the memory value are considered.
; The result will be right-shifted 6 times,
; meaning that multiplying with 64 is actually multiplying with 1.
; The result is returned in the accumulator.
; Index denotes, whether the memory held value is indexed by X (1), by Y (2), or not at all (0)
.macro SCALE_U7 su7_value, index
.local @skip_bit0
.local @skip_bit1
.local @skip_bit2
.local @skip_bit3
.local @skip_bit4
.local @skip_bit5
.local @skip_bit6
; ZP variables available for multiplication:
; mzpwb, mzpbf
sta mzpwb ; this will hold the right-shifted value
.if(index=0)
lda su7_value
.endif
.if(index=1)
lda su7_value, x
.endif
.if(index=2)
lda su7_value, y
.endif
sta mzpbf ; this is used for bit-testing
lda #0
bbr6 mzpbf, @skip_bit6
clc
adc mzpwb
@skip_bit6:
lsr mzpwb
bbr5 mzpbf, @skip_bit5
clc
adc mzpwb
@skip_bit5:
lsr mzpwb
bbr4 mzpbf, @skip_bit4
clc
adc mzpwb
@skip_bit4:
lsr mzpwb
bbr3 mzpbf, @skip_bit3
clc
adc mzpwb
@skip_bit3:
lsr mzpwb
bbr2 mzpbf, @skip_bit2
clc
adc mzpwb
@skip_bit2:
lsr mzpwb
bbr1 mzpbf, @skip_bit1
clc
adc mzpwb
@skip_bit1:
lsr mzpwb
bbr0 mzpbf, @skip_bit0
clc
adc mzpwb
@skip_bit0:
; worst case: 91 cycles. best case: 63 cycles. Average: 77 cycles.
.endmacro
; This is used for modulation of the parameters that are only 6 bits wide,
; namely volume and pulse width.
; The index parameter can be 0, 1 or 2. It influences how the modulation depth is indexed (no indexing, by X, by Y)
; modulation source is assumed to be in register A (and all flags from loading of A)
; result is returned in register A
.macro SCALE_S6 moddepth, index
; with this sequence, we do several tasks at once:
; We extract the sign from the modulation source and store it in mzpbf
; We truncate the sign from the modulation source
; and right shift it effectively once, because the amplitude of any modulation source is too high anyway
stz mzpwc+1
asl ; push sign out
rol mzpwc+1 ; push sign into variable
lsr
lsr
; initialize zero page 8 bit value
sta mzpwc ; only low byte is used
.local @skip_bit0
.local @skip_bit1
.local @skip_bit2
.local @skip_bit3
.local @skip_bit4
.local @skip_bit5
.local @skip_bit6
; ZP variables available for multiplication:
; mzpwb, mzpbf
sta mzpwb ; this will hold the right-shifted value
.if(index=0)
lda moddepth
.endif
.if(index=1)
lda moddepth, x
.endif
.if(index=2)
lda moddepth, y
.endif
sta mzpbf ; this is used for bit-testing
lda #0
bbr6 mzpbf, @skip_bit6
clc
adc mzpwb
@skip_bit6:
lsr mzpwb
bbr5 mzpbf, @skip_bit5
clc
adc mzpwb
@skip_bit5:
lsr mzpwb
bbr4 mzpbf, @skip_bit4
clc
adc mzpwb
@skip_bit4:
lsr mzpwb
bbr3 mzpbf, @skip_bit3
clc
adc mzpwb
@skip_bit3:
lsr mzpwb
bbr2 mzpbf, @skip_bit2
clc
adc mzpwb
@skip_bit2:
lsr mzpwb
bbr1 mzpbf, @skip_bit1
clc
adc mzpwb
@skip_bit1:
lsr mzpwb
bbr0 mzpbf, @skip_bit0
clc
adc mzpwb
@skip_bit0:
; result is in register A
sta mzpwb ; save it
; determine overall sign (mod source * mod depth)
.if(index=0)
lda moddepth
.endif
.if(index=1)
lda moddepth, x
.endif
.if(index=2)
lda moddepth, y
.endif
and #%10000000
beq :+
inc mzpwc+1
: ; now if lowest bit of mzpbf is even, sign is positive and if it's odd, sign is negative
; now add/subtract scaling result to modulation destiny, according to sign
.local @minusS
.local @endS
lda mzpwc+1
ror
bcs @minusS
; if we're here, sign is positive
lda mzpwb
bra @endS
@minusS:
; if we're here, sign is negative
lda mzpwb
eor #%11111111
inc
@endS:
.endmacro
; this is used for various modulation depth scalings of 16 bit modulation values (mainly pitch)
; modulation depth is assumed to be indexed by register Y
; modulation source is assumed to be indexed by register X (not preserved)
; result is added to the literal addesses
; moddepth is allowed to have a sign bit (bit 7)
; moddepth has the format %SLLLHHHH
; where %HHHH is the number of rightshifts to be applied to the 16 bit mod source
; and %LLL is the number of the sub-level
; skipping is NOT done in this macro if modsource select is "none"
; modsourceH is also allowed to have a sign bit (bit 7)
.macro SCALE5_16 modsourceL, modsourceH, moddepth, resultL, resultH
; mzpbf will hold the sign
stz mzpbf
; initialize zero page 16 bit value
lda modsourceL, x
sta mzpwb
lda modsourceH, x
and #%01111111
cmp modsourceH, x
sta mzpwb+1 ; 14 cycles
; from now on, the mod source isn't directly accessed anymore, so we can discard X
; store the modulation sign
beq :+
inc mzpbf
:
lda moddepth, y
sta scale5_moddepth
; jump to macro-parameter independent code, which can be reused (hence, it is outside the macro)
; you can read that subroutine as if it was part of this macro.
jsr scale5_16_internal
; now add/subtract scaling result to modulation destiny, according to sign
.local @minusS
.local @endS
lda mzpbf
ror
bcs @minusS
; if we're here, sign is positive --> add
clc
lda mzpwb
adc resultL
sta resultL
lda mzpwb+1
adc resultH
sta resultH
bra @endS
@minusS:
; if we're here, sign is negative --> sub
sec
lda resultL
sbc mzpwb
sta resultL
lda resultH
sbc mzpwb+1
sta resultH
@endS:
; 35 cycles
; worst case overall: 35 + 64 + 24 + 107 + 14 = 244 cycles ... much more than I hoped. (even more now with proper sign handling)
.endmacro
scale5_moddepth:
.byte 0
; does the heavy lifting of the above macro scale5_16. Reusable code here.
scale5_16_internal:
; do %HHHH rightshifts
; cycle counting needs to be redone, because initially, I forgot about LSR, so I CLCed before each ROR
; instead of the naive approach of looping over rightshifting a 16 bit variable
; we are taking a more efficient approach of testing each bit
; of the %HHHH value and perform suitable actions
; alternative rightshifts: binary branching
; check bit 3
lda scale5_moddepth
and #%00001000
beq @skipH3
; 8 rightshifts = copy high byte to low byte, set high byte to 0
; the subsequent rightshifting can be done entirely inside accumulator, no memory access needed
lda scale5_moddepth
and #%00000111
bne :+ ; if no other bit is set, we just move the bytes and are done
lda mzpwb+1
sta mzpwb
stz mzpwb+1
jmp @endH
: ; if we got here, we've got a nonzero number of rightshifts to be done in register A
tax
lda mzpwb+1
@loopH:
lsr
dex
bne @loopH
sta mzpwb
stz mzpwb+1
jmp @endH ; worst case if bit 3 is set: 15 rightshifts, makes 9*7 + 35 cycles = 98 cycles
@skipH3:
; check bit 2
lda scale5_moddepth
and #%00000100
beq @skipH2
lda mzpwb
lsr mzpwb+1
ror
lsr mzpwb+1
ror
lsr mzpwb+1
ror
lsr mzpwb+1
ror
sta mzpwb
@skipH2:
; check bit 1
lda scale5_moddepth
and #%00000010
beq @skipH1
lda mzpwb
lsr mzpwb+1
ror
lsr mzpwb+1
ror
sta mzpwb
@skipH1:
; check bit 1
lda scale5_moddepth
and #%00000001
beq @skipH0
lsr mzpwb+1
ror mzpwb
@skipH0: ; worst case if bit 3 is not set: 107 cycles.
@endH:
; maximum number of cycles for rightshifts is 107 cycles. Good compared to 230 from naive approach.
; still hurts tho.
; do sublevel scaling
; select subroutine
lda scale5_moddepth
and #%01110000
beq :+
clc
ror
ror
ror
tax
jmp (@tableL-2, x) ; if x=0, nothing has to be done. if x=2,4,6 or 8, jump to respective subroutine
: jmp @endL
; 24 cycles
@tableL:
.word @sublevel_1
.word @sublevel_2
.word @sublevel_3
.word @sublevel_4
@sublevel_1:
; 2^(1/5) ~= %1.001
; do first ROR while copying to mzpwc
lda mzpwb+1
lsr
sta mzpwc+1
lda mzpwb
ror
sta mzpwc
; then do remaining RORS with high byte in accumulator and low byte in memory
lda mzpwc+1
lsr
ror mzpwc
lsr
; but last low byte ROR already in accumulator, since we are going to do addition with it
sta mzpwc+1
lda mzpwc
ror
clc
adc mzpwb
sta mzpwb
lda mzpwc+1
adc mzpwb+1
sta mzpwb+1
jmp @endL ; 62 cycles ... ouch!
@sublevel_2:
; 2^(2/5) ~= %1.01
; do first ROR while copying to mzpwc
lda mzpwb+1
lsr
sta mzpwc+1
lda mzpwb
ror
sta mzpwc
; do second ROR and addition
lsr mzpwc+1
lda mzpwc
ror
clc
adc mzpwb
sta mzpwb
lda mzpwc+1
adc mzpwb+1
sta mzpwb+1
jmp @endL ; 49 cycles
@sublevel_3:
; 2^(3/5) ~= %1.1
lda mzpwb+1
lsr
sta mzpwc+1
lda mzpwb
ror
clc
adc mzpwb
sta mzpwb
lda mzpwc+1
adc mzpwb+1
sta mzpwb+1
jmp @endL ; 35 cycles
@sublevel_4:
; 2^(4/5) ~= %1.11
; do first ROR while copying to mzpwc
lda mzpwb+1
lsr
sta mzpwc+1
lda mzpwb
ror
sta mzpwc
; do second ROR while copying to mzpwf
lda mzpwc+1
lsr
sta mzpwf+1
lda mzpwc
ror
;sta mzpwf ;redundant, because we don't read from it anyway
; do all additions
; first addition
clc
adc mzpwc ; mzpwf still in A
sta mzpwc
lda mzpwf+1
adc mzpwc+1
sta mzpwc+1
; second addition
clc
lda mzpwc
adc mzpwb
sta mzpwb
lda mzpwc+1
adc mzpwb+1
sta mzpwb+1
; 66 cycles ... ouch!!
@endL:
; determine overall sign (mod source * mod depth)
lda scale5_moddepth
and #%10000000
beq :+
inc mzpbf
: ; now if lowest bit of mzpbf is even, sign is positive and if it's odd, sign is negative
; return to macro
rts
; This macro multiplies the value in the accumulator with a value in memory.
; The result will be right-shifted 7 times,
; meaning that multiplying with 128 is actually multiplying with 1.
; The result is returned in the accumulator.
; Index denotes, whether the memory held value is indexed by X (1), by Y (2), or not at all (0)
.macro SCALE_U8 su8_value, index
.local @skip_bit0
.local @skip_bit1
.local @skip_bit2
.local @skip_bit3
.local @skip_bit4
.local @skip_bit5
.local @skip_bit6
.local @skip_bit7
; ZP variables available for multiplication:
; mzpwb, mzpbf
sta mzpwb ; this will hold the right-shifted value
.if(index=0)
lda su8_value
.endif
.if(index=1)
lda su8_value, x
.endif
.if(index=2)
lda su8_value, y
.endif
sta mzpbf ; this is used for bit-testing
lda #0
bbr7 mzpbf, @skip_bit7
clc
adc mzpwb
@skip_bit7:
lsr mzpwb
bbr6 mzpbf, @skip_bit6
clc
adc mzpwb
@skip_bit6:
lsr mzpwb
bbr5 mzpbf, @skip_bit5
clc
adc mzpwb
@skip_bit5:
lsr mzpwb
bbr4 mzpbf, @skip_bit4
clc
adc mzpwb
@skip_bit4:
lsr mzpwb
bbr3 mzpbf, @skip_bit3
clc
adc mzpwb
@skip_bit3:
lsr mzpwb
bbr2 mzpbf, @skip_bit2
clc
adc mzpwb
@skip_bit2:
lsr mzpwb
bbr1 mzpbf, @skip_bit1
clc
adc mzpwb
@skip_bit1:
lsr mzpwb
bbr0 mzpbf, @skip_bit0
clc
adc mzpwb
@skip_bit0:
; worst case: 103 cycles. best case: 71 cycles. Average: 87 cycles.
.endmacro
.endif |
#include "blpch.h"
#include "Bolt/Core/Input.h"
#include "Bolt/Core/Application.h"
#include <GLFW/glfw3.h>
#ifdef BL_PLATFORM_WINDOWS
namespace Bolt {
bool Input::IsKeyPressed(KeyCode keycode) {
BL_PROFILE_FUNCTION();
auto window = static_cast<GLFWwindow*>(Application::Get().GetWindow().GetNativeWindow());
auto state = glfwGetKey(window, keycode);
return state == GLFW_PRESS || state == GLFW_REPEAT;
}
bool Input::IsMouseButtonPressed(MouseCode button) {
BL_PROFILE_FUNCTION();
auto window = static_cast<GLFWwindow*>(Application::Get().GetWindow().GetNativeWindow());
auto state = glfwGetMouseButton(window, button);
return state == GLFW_PRESS;
}
float Input::GetMouseX() {
BL_PROFILE_FUNCTION();
auto [x, y] = GetMousePosition();
return x;
}
float Input::GetMouseY() {
BL_PROFILE_FUNCTION();
auto [x, y] = GetMousePosition();
return y;
}
std::pair<float, float> Input::GetMousePosition() {
BL_PROFILE_FUNCTION();
auto window = static_cast<GLFWwindow*>(Application::Get().GetWindow().GetNativeWindow());
double xPos, yPos;
glfwGetCursorPos(window, &xPos, &yPos);
return { (float)xPos, (float)yPos };
}
}
#endif // BL_PLATFORM_WINDOWS |
public _blake3_hash_many_sse2
public blake3_hash_many_sse2
public blake3_compress_in_place_sse2
public _blake3_compress_in_place_sse2
public blake3_compress_xof_sse2
public _blake3_compress_xof_sse2
_TEXT SEGMENT ALIGN(16) 'CODE'
ALIGN 16
blake3_hash_many_sse2 PROC
_blake3_hash_many_sse2 PROC
push r15
push r14
push r13
push r12
push rsi
push rdi
push rbx
push rbp
mov rbp, rsp
sub rsp, 528
and rsp, 0FFFFFFFFFFFFFFC0H
movdqa xmmword ptr [rsp+170H], xmm6
movdqa xmmword ptr [rsp+180H], xmm7
movdqa xmmword ptr [rsp+190H], xmm8
movdqa xmmword ptr [rsp+1A0H], xmm9
movdqa xmmword ptr [rsp+1B0H], xmm10
movdqa xmmword ptr [rsp+1C0H], xmm11
movdqa xmmword ptr [rsp+1D0H], xmm12
movdqa xmmword ptr [rsp+1E0H], xmm13
movdqa xmmword ptr [rsp+1F0H], xmm14
movdqa xmmword ptr [rsp+200H], xmm15
mov rdi, rcx
mov rsi, rdx
mov rdx, r8
mov rcx, r9
mov r8, qword ptr [rbp+68H]
movzx r9, byte ptr [rbp+70H]
neg r9d
movd xmm0, r9d
pshufd xmm0, xmm0, 00H
movdqa xmmword ptr [rsp+130H], xmm0
movdqa xmm1, xmm0
pand xmm1, xmmword ptr [ADD0]
pand xmm0, xmmword ptr [ADD1]
movdqa xmmword ptr [rsp+150H], xmm0
movd xmm0, r8d
pshufd xmm0, xmm0, 00H
paddd xmm0, xmm1
movdqa xmmword ptr [rsp+110H], xmm0
pxor xmm0, xmmword ptr [CMP_MSB_MASK]
pxor xmm1, xmmword ptr [CMP_MSB_MASK]
pcmpgtd xmm1, xmm0
shr r8, 32
movd xmm2, r8d
pshufd xmm2, xmm2, 00H
psubd xmm2, xmm1
movdqa xmmword ptr [rsp+120H], xmm2
mov rbx, qword ptr [rbp+90H]
mov r15, rdx
shl r15, 6
movzx r13d, byte ptr [rbp+78H]
movzx r12d, byte ptr [rbp+88H]
cmp rsi, 4
jc final3blocks
outerloop4:
movdqu xmm3, xmmword ptr [rcx]
pshufd xmm0, xmm3, 00H
pshufd xmm1, xmm3, 55H
pshufd xmm2, xmm3, 0AAH
pshufd xmm3, xmm3, 0FFH
movdqu xmm7, xmmword ptr [rcx+10H]
pshufd xmm4, xmm7, 00H
pshufd xmm5, xmm7, 55H
pshufd xmm6, xmm7, 0AAH
pshufd xmm7, xmm7, 0FFH
mov r8, qword ptr [rdi]
mov r9, qword ptr [rdi+8H]
mov r10, qword ptr [rdi+10H]
mov r11, qword ptr [rdi+18H]
movzx eax, byte ptr [rbp+80H]
or eax, r13d
xor edx, edx
innerloop4:
mov r14d, eax
or eax, r12d
add rdx, 64
cmp rdx, r15
cmovne eax, r14d
movdqu xmm8, xmmword ptr [r8+rdx-40H]
movdqu xmm9, xmmword ptr [r9+rdx-40H]
movdqu xmm10, xmmword ptr [r10+rdx-40H]
movdqu xmm11, xmmword ptr [r11+rdx-40H]
movdqa xmm12, xmm8
punpckldq xmm8, xmm9
punpckhdq xmm12, xmm9
movdqa xmm14, xmm10
punpckldq xmm10, xmm11
punpckhdq xmm14, xmm11
movdqa xmm9, xmm8
punpcklqdq xmm8, xmm10
punpckhqdq xmm9, xmm10
movdqa xmm13, xmm12
punpcklqdq xmm12, xmm14
punpckhqdq xmm13, xmm14
movdqa xmmword ptr [rsp], xmm8
movdqa xmmword ptr [rsp+10H], xmm9
movdqa xmmword ptr [rsp+20H], xmm12
movdqa xmmword ptr [rsp+30H], xmm13
movdqu xmm8, xmmword ptr [r8+rdx-30H]
movdqu xmm9, xmmword ptr [r9+rdx-30H]
movdqu xmm10, xmmword ptr [r10+rdx-30H]
movdqu xmm11, xmmword ptr [r11+rdx-30H]
movdqa xmm12, xmm8
punpckldq xmm8, xmm9
punpckhdq xmm12, xmm9
movdqa xmm14, xmm10
punpckldq xmm10, xmm11
punpckhdq xmm14, xmm11
movdqa xmm9, xmm8
punpcklqdq xmm8, xmm10
punpckhqdq xmm9, xmm10
movdqa xmm13, xmm12
punpcklqdq xmm12, xmm14
punpckhqdq xmm13, xmm14
movdqa xmmword ptr [rsp+40H], xmm8
movdqa xmmword ptr [rsp+50H], xmm9
movdqa xmmword ptr [rsp+60H], xmm12
movdqa xmmword ptr [rsp+70H], xmm13
movdqu xmm8, xmmword ptr [r8+rdx-20H]
movdqu xmm9, xmmword ptr [r9+rdx-20H]
movdqu xmm10, xmmword ptr [r10+rdx-20H]
movdqu xmm11, xmmword ptr [r11+rdx-20H]
movdqa xmm12, xmm8
punpckldq xmm8, xmm9
punpckhdq xmm12, xmm9
movdqa xmm14, xmm10
punpckldq xmm10, xmm11
punpckhdq xmm14, xmm11
movdqa xmm9, xmm8
punpcklqdq xmm8, xmm10
punpckhqdq xmm9, xmm10
movdqa xmm13, xmm12
punpcklqdq xmm12, xmm14
punpckhqdq xmm13, xmm14
movdqa xmmword ptr [rsp+80H], xmm8
movdqa xmmword ptr [rsp+90H], xmm9
movdqa xmmword ptr [rsp+0A0H], xmm12
movdqa xmmword ptr [rsp+0B0H], xmm13
movdqu xmm8, xmmword ptr [r8+rdx-10H]
movdqu xmm9, xmmword ptr [r9+rdx-10H]
movdqu xmm10, xmmword ptr [r10+rdx-10H]
movdqu xmm11, xmmword ptr [r11+rdx-10H]
movdqa xmm12, xmm8
punpckldq xmm8, xmm9
punpckhdq xmm12, xmm9
movdqa xmm14, xmm10
punpckldq xmm10, xmm11
punpckhdq xmm14, xmm11
movdqa xmm9, xmm8
punpcklqdq xmm8, xmm10
punpckhqdq xmm9, xmm10
movdqa xmm13, xmm12
punpcklqdq xmm12, xmm14
punpckhqdq xmm13, xmm14
movdqa xmmword ptr [rsp+0C0H], xmm8
movdqa xmmword ptr [rsp+0D0H], xmm9
movdqa xmmword ptr [rsp+0E0H], xmm12
movdqa xmmword ptr [rsp+0F0H], xmm13
movdqa xmm9, xmmword ptr [BLAKE3_IV_1]
movdqa xmm10, xmmword ptr [BLAKE3_IV_2]
movdqa xmm11, xmmword ptr [BLAKE3_IV_3]
movdqa xmm12, xmmword ptr [rsp+110H]
movdqa xmm13, xmmword ptr [rsp+120H]
movdqa xmm14, xmmword ptr [BLAKE3_BLOCK_LEN]
movd xmm15, eax
pshufd xmm15, xmm15, 00H
prefetcht0 byte ptr [r8+rdx+80H]
prefetcht0 byte ptr [r9+rdx+80H]
prefetcht0 byte ptr [r10+rdx+80H]
prefetcht0 byte ptr [r11+rdx+80H]
paddd xmm0, xmmword ptr [rsp]
paddd xmm1, xmmword ptr [rsp+20H]
paddd xmm2, xmmword ptr [rsp+40H]
paddd xmm3, xmmword ptr [rsp+60H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [BLAKE3_IV_0]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+10H]
paddd xmm1, xmmword ptr [rsp+30H]
paddd xmm2, xmmword ptr [rsp+50H]
paddd xmm3, xmmword ptr [rsp+70H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+80H]
paddd xmm1, xmmword ptr [rsp+0A0H]
paddd xmm2, xmmword ptr [rsp+0C0H]
paddd xmm3, xmmword ptr [rsp+0E0H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+90H]
paddd xmm1, xmmword ptr [rsp+0B0H]
paddd xmm2, xmmword ptr [rsp+0D0H]
paddd xmm3, xmmword ptr [rsp+0F0H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+20H]
paddd xmm1, xmmword ptr [rsp+30H]
paddd xmm2, xmmword ptr [rsp+70H]
paddd xmm3, xmmword ptr [rsp+40H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+60H]
paddd xmm1, xmmword ptr [rsp+0A0H]
paddd xmm2, xmmword ptr [rsp]
paddd xmm3, xmmword ptr [rsp+0D0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+10H]
paddd xmm1, xmmword ptr [rsp+0C0H]
paddd xmm2, xmmword ptr [rsp+90H]
paddd xmm3, xmmword ptr [rsp+0F0H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+0B0H]
paddd xmm1, xmmword ptr [rsp+50H]
paddd xmm2, xmmword ptr [rsp+0E0H]
paddd xmm3, xmmword ptr [rsp+80H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+30H]
paddd xmm1, xmmword ptr [rsp+0A0H]
paddd xmm2, xmmword ptr [rsp+0D0H]
paddd xmm3, xmmword ptr [rsp+70H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+40H]
paddd xmm1, xmmword ptr [rsp+0C0H]
paddd xmm2, xmmword ptr [rsp+20H]
paddd xmm3, xmmword ptr [rsp+0E0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+60H]
paddd xmm1, xmmword ptr [rsp+90H]
paddd xmm2, xmmword ptr [rsp+0B0H]
paddd xmm3, xmmword ptr [rsp+80H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+50H]
paddd xmm1, xmmword ptr [rsp]
paddd xmm2, xmmword ptr [rsp+0F0H]
paddd xmm3, xmmword ptr [rsp+10H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+0A0H]
paddd xmm1, xmmword ptr [rsp+0C0H]
paddd xmm2, xmmword ptr [rsp+0E0H]
paddd xmm3, xmmword ptr [rsp+0D0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+70H]
paddd xmm1, xmmword ptr [rsp+90H]
paddd xmm2, xmmword ptr [rsp+30H]
paddd xmm3, xmmword ptr [rsp+0F0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+40H]
paddd xmm1, xmmword ptr [rsp+0B0H]
paddd xmm2, xmmword ptr [rsp+50H]
paddd xmm3, xmmword ptr [rsp+10H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp]
paddd xmm1, xmmword ptr [rsp+20H]
paddd xmm2, xmmword ptr [rsp+80H]
paddd xmm3, xmmword ptr [rsp+60H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+0C0H]
paddd xmm1, xmmword ptr [rsp+90H]
paddd xmm2, xmmword ptr [rsp+0F0H]
paddd xmm3, xmmword ptr [rsp+0E0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+0D0H]
paddd xmm1, xmmword ptr [rsp+0B0H]
paddd xmm2, xmmword ptr [rsp+0A0H]
paddd xmm3, xmmword ptr [rsp+80H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+70H]
paddd xmm1, xmmword ptr [rsp+50H]
paddd xmm2, xmmword ptr [rsp]
paddd xmm3, xmmword ptr [rsp+60H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+20H]
paddd xmm1, xmmword ptr [rsp+30H]
paddd xmm2, xmmword ptr [rsp+10H]
paddd xmm3, xmmword ptr [rsp+40H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+90H]
paddd xmm1, xmmword ptr [rsp+0B0H]
paddd xmm2, xmmword ptr [rsp+80H]
paddd xmm3, xmmword ptr [rsp+0F0H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+0E0H]
paddd xmm1, xmmword ptr [rsp+50H]
paddd xmm2, xmmword ptr [rsp+0C0H]
paddd xmm3, xmmword ptr [rsp+10H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+0D0H]
paddd xmm1, xmmword ptr [rsp]
paddd xmm2, xmmword ptr [rsp+20H]
paddd xmm3, xmmword ptr [rsp+40H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+30H]
paddd xmm1, xmmword ptr [rsp+0A0H]
paddd xmm2, xmmword ptr [rsp+60H]
paddd xmm3, xmmword ptr [rsp+70H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+0B0H]
paddd xmm1, xmmword ptr [rsp+50H]
paddd xmm2, xmmword ptr [rsp+10H]
paddd xmm3, xmmword ptr [rsp+80H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+0F0H]
paddd xmm1, xmmword ptr [rsp]
paddd xmm2, xmmword ptr [rsp+90H]
paddd xmm3, xmmword ptr [rsp+60H]
paddd xmm0, xmm4
paddd xmm1, xmm5
paddd xmm2, xmm6
paddd xmm3, xmm7
pxor xmm12, xmm0
pxor xmm13, xmm1
pxor xmm14, xmm2
pxor xmm15, xmm3
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm12
paddd xmm9, xmm13
paddd xmm10, xmm14
paddd xmm11, xmm15
pxor xmm4, xmm8
pxor xmm5, xmm9
pxor xmm6, xmm10
pxor xmm7, xmm11
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
paddd xmm0, xmmword ptr [rsp+0E0H]
paddd xmm1, xmmword ptr [rsp+20H]
paddd xmm2, xmmword ptr [rsp+30H]
paddd xmm3, xmmword ptr [rsp+70H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
pshuflw xmm15, xmm15, 0B1H
pshufhw xmm15, xmm15, 0B1H
pshuflw xmm12, xmm12, 0B1H
pshufhw xmm12, xmm12, 0B1H
pshuflw xmm13, xmm13, 0B1H
pshufhw xmm13, xmm13, 0B1H
pshuflw xmm14, xmm14, 0B1H
pshufhw xmm14, xmm14, 0B1H
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
movdqa xmmword ptr [rsp+100H], xmm8
movdqa xmm8, xmm5
psrld xmm8, 12
pslld xmm5, 20
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 12
pslld xmm6, 20
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 12
pslld xmm7, 20
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 12
pslld xmm4, 20
por xmm4, xmm8
paddd xmm0, xmmword ptr [rsp+0A0H]
paddd xmm1, xmmword ptr [rsp+0C0H]
paddd xmm2, xmmword ptr [rsp+40H]
paddd xmm3, xmmword ptr [rsp+0D0H]
paddd xmm0, xmm5
paddd xmm1, xmm6
paddd xmm2, xmm7
paddd xmm3, xmm4
pxor xmm15, xmm0
pxor xmm12, xmm1
pxor xmm13, xmm2
pxor xmm14, xmm3
movdqa xmm8, xmm15
psrld xmm15, 8
pslld xmm8, 24
pxor xmm15, xmm8
movdqa xmm8, xmm12
psrld xmm12, 8
pslld xmm8, 24
pxor xmm12, xmm8
movdqa xmm8, xmm13
psrld xmm13, 8
pslld xmm8, 24
pxor xmm13, xmm8
movdqa xmm8, xmm14
psrld xmm14, 8
pslld xmm8, 24
pxor xmm14, xmm8
paddd xmm10, xmm15
paddd xmm11, xmm12
movdqa xmm8, xmmword ptr [rsp+100H]
paddd xmm8, xmm13
paddd xmm9, xmm14
pxor xmm5, xmm10
pxor xmm6, xmm11
pxor xmm7, xmm8
pxor xmm4, xmm9
pxor xmm0, xmm8
pxor xmm1, xmm9
pxor xmm2, xmm10
pxor xmm3, xmm11
movdqa xmm8, xmm5
psrld xmm8, 7
pslld xmm5, 25
por xmm5, xmm8
movdqa xmm8, xmm6
psrld xmm8, 7
pslld xmm6, 25
por xmm6, xmm8
movdqa xmm8, xmm7
psrld xmm8, 7
pslld xmm7, 25
por xmm7, xmm8
movdqa xmm8, xmm4
psrld xmm8, 7
pslld xmm4, 25
por xmm4, xmm8
pxor xmm4, xmm12
pxor xmm5, xmm13
pxor xmm6, xmm14
pxor xmm7, xmm15
mov eax, r13d
jne innerloop4
movdqa xmm9, xmm0
punpckldq xmm0, xmm1
punpckhdq xmm9, xmm1
movdqa xmm11, xmm2
punpckldq xmm2, xmm3
punpckhdq xmm11, xmm3
movdqa xmm1, xmm0
punpcklqdq xmm0, xmm2
punpckhqdq xmm1, xmm2
movdqa xmm3, xmm9
punpcklqdq xmm9, xmm11
punpckhqdq xmm3, xmm11
movdqu xmmword ptr [rbx], xmm0
movdqu xmmword ptr [rbx+20H], xmm1
movdqu xmmword ptr [rbx+40H], xmm9
movdqu xmmword ptr [rbx+60H], xmm3
movdqa xmm9, xmm4
punpckldq xmm4, xmm5
punpckhdq xmm9, xmm5
movdqa xmm11, xmm6
punpckldq xmm6, xmm7
punpckhdq xmm11, xmm7
movdqa xmm5, xmm4
punpcklqdq xmm4, xmm6
punpckhqdq xmm5, xmm6
movdqa xmm7, xmm9
punpcklqdq xmm9, xmm11
punpckhqdq xmm7, xmm11
movdqu xmmword ptr [rbx+10H], xmm4
movdqu xmmword ptr [rbx+30H], xmm5
movdqu xmmword ptr [rbx+50H], xmm9
movdqu xmmword ptr [rbx+70H], xmm7
movdqa xmm1, xmmword ptr [rsp+110H]
movdqa xmm0, xmm1
paddd xmm1, xmmword ptr [rsp+150H]
movdqa xmmword ptr [rsp+110H], xmm1
pxor xmm0, xmmword ptr [CMP_MSB_MASK]
pxor xmm1, xmmword ptr [CMP_MSB_MASK]
pcmpgtd xmm0, xmm1
movdqa xmm1, xmmword ptr [rsp+120H]
psubd xmm1, xmm0
movdqa xmmword ptr [rsp+120H], xmm1
add rbx, 128
add rdi, 32
sub rsi, 4
cmp rsi, 4
jnc outerloop4
test rsi, rsi
jne final3blocks
unwind:
movdqa xmm6, xmmword ptr [rsp+170H]
movdqa xmm7, xmmword ptr [rsp+180H]
movdqa xmm8, xmmword ptr [rsp+190H]
movdqa xmm9, xmmword ptr [rsp+1A0H]
movdqa xmm10, xmmword ptr [rsp+1B0H]
movdqa xmm11, xmmword ptr [rsp+1C0H]
movdqa xmm12, xmmword ptr [rsp+1D0H]
movdqa xmm13, xmmword ptr [rsp+1E0H]
movdqa xmm14, xmmword ptr [rsp+1F0H]
movdqa xmm15, xmmword ptr [rsp+200H]
mov rsp, rbp
pop rbp
pop rbx
pop rdi
pop rsi
pop r12
pop r13
pop r14
pop r15
ret
ALIGN 16
final3blocks:
test esi, 2H
je final1block
movups xmm0, xmmword ptr [rcx]
movups xmm1, xmmword ptr [rcx+10H]
movaps xmm8, xmm0
movaps xmm9, xmm1
movd xmm13, dword ptr [rsp+110H]
movd xmm14, dword ptr [rsp+120H]
punpckldq xmm13, xmm14
movaps xmmword ptr [rsp], xmm13
movd xmm14, dword ptr [rsp+114H]
movd xmm13, dword ptr [rsp+124H]
punpckldq xmm14, xmm13
movaps xmmword ptr [rsp+10H], xmm14
mov r8, qword ptr [rdi]
mov r9, qword ptr [rdi+8H]
movzx eax, byte ptr [rbp+80H]
or eax, r13d
xor edx, edx
innerloop2:
mov r14d, eax
or eax, r12d
add rdx, 64
cmp rdx, r15
cmovne eax, r14d
movaps xmm2, xmmword ptr [BLAKE3_IV]
movaps xmm10, xmm2
movups xmm4, xmmword ptr [r8+rdx-40H]
movups xmm5, xmmword ptr [r8+rdx-30H]
movaps xmm3, xmm4
shufps xmm4, xmm5, 136
shufps xmm3, xmm5, 221
movaps xmm5, xmm3
movups xmm6, xmmword ptr [r8+rdx-20H]
movups xmm7, xmmword ptr [r8+rdx-10H]
movaps xmm3, xmm6
shufps xmm6, xmm7, 136
pshufd xmm6, xmm6, 93H
shufps xmm3, xmm7, 221
pshufd xmm7, xmm3, 93H
movups xmm12, xmmword ptr [r9+rdx-40H]
movups xmm13, xmmword ptr [r9+rdx-30H]
movaps xmm11, xmm12
shufps xmm12, xmm13, 136
shufps xmm11, xmm13, 221
movaps xmm13, xmm11
movups xmm14, xmmword ptr [r9+rdx-20H]
movups xmm15, xmmword ptr [r9+rdx-10H]
movaps xmm11, xmm14
shufps xmm14, xmm15, 136
pshufd xmm14, xmm14, 93H
shufps xmm11, xmm15, 221
pshufd xmm15, xmm11, 93H
shl rax, 20H
or rax, 40H
movd xmm3, rax
movdqa xmmword ptr [rsp+20H], xmm3
movaps xmm3, xmmword ptr [rsp]
movaps xmm11, xmmword ptr [rsp+10H]
punpcklqdq xmm3, xmmword ptr [rsp+20H]
punpcklqdq xmm11, xmmword ptr [rsp+20H]
mov al, 7
roundloop2:
paddd xmm0, xmm4
paddd xmm8, xmm12
movaps xmmword ptr [rsp+20H], xmm4
movaps xmmword ptr [rsp+30H], xmm12
paddd xmm0, xmm1
paddd xmm8, xmm9
pxor xmm3, xmm0
pxor xmm11, xmm8
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
pshuflw xmm11, xmm11, 0B1H
pshufhw xmm11, xmm11, 0B1H
paddd xmm2, xmm3
paddd xmm10, xmm11
pxor xmm1, xmm2
pxor xmm9, xmm10
movdqa xmm4, xmm1
pslld xmm1, 20
psrld xmm4, 12
por xmm1, xmm4
movdqa xmm4, xmm9
pslld xmm9, 20
psrld xmm4, 12
por xmm9, xmm4
paddd xmm0, xmm5
paddd xmm8, xmm13
movaps xmmword ptr [rsp+40H], xmm5
movaps xmmword ptr [rsp+50H], xmm13
paddd xmm0, xmm1
paddd xmm8, xmm9
pxor xmm3, xmm0
pxor xmm11, xmm8
movdqa xmm13, xmm3
psrld xmm3, 8
pslld xmm13, 24
pxor xmm3, xmm13
movdqa xmm13, xmm11
psrld xmm11, 8
pslld xmm13, 24
pxor xmm11, xmm13
paddd xmm2, xmm3
paddd xmm10, xmm11
pxor xmm1, xmm2
pxor xmm9, xmm10
movdqa xmm4, xmm1
pslld xmm1, 25
psrld xmm4, 7
por xmm1, xmm4
movdqa xmm4, xmm9
pslld xmm9, 25
psrld xmm4, 7
por xmm9, xmm4
pshufd xmm0, xmm0, 93H
pshufd xmm8, xmm8, 93H
pshufd xmm3, xmm3, 4EH
pshufd xmm11, xmm11, 4EH
pshufd xmm2, xmm2, 39H
pshufd xmm10, xmm10, 39H
paddd xmm0, xmm6
paddd xmm8, xmm14
paddd xmm0, xmm1
paddd xmm8, xmm9
pxor xmm3, xmm0
pxor xmm11, xmm8
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
pshuflw xmm11, xmm11, 0B1H
pshufhw xmm11, xmm11, 0B1H
paddd xmm2, xmm3
paddd xmm10, xmm11
pxor xmm1, xmm2
pxor xmm9, xmm10
movdqa xmm4, xmm1
pslld xmm1, 20
psrld xmm4, 12
por xmm1, xmm4
movdqa xmm4, xmm9
pslld xmm9, 20
psrld xmm4, 12
por xmm9, xmm4
paddd xmm0, xmm7
paddd xmm8, xmm15
paddd xmm0, xmm1
paddd xmm8, xmm9
pxor xmm3, xmm0
pxor xmm11, xmm8
movdqa xmm13, xmm3
psrld xmm3, 8
pslld xmm13, 24
pxor xmm3, xmm13
movdqa xmm13, xmm11
psrld xmm11, 8
pslld xmm13, 24
pxor xmm11, xmm13
paddd xmm2, xmm3
paddd xmm10, xmm11
pxor xmm1, xmm2
pxor xmm9, xmm10
movdqa xmm4, xmm1
pslld xmm1, 25
psrld xmm4, 7
por xmm1, xmm4
movdqa xmm4, xmm9
pslld xmm9, 25
psrld xmm4, 7
por xmm9, xmm4
pshufd xmm0, xmm0, 39H
pshufd xmm8, xmm8, 39H
pshufd xmm3, xmm3, 4EH
pshufd xmm11, xmm11, 4EH
pshufd xmm2, xmm2, 93H
pshufd xmm10, xmm10, 93H
dec al
je endroundloop2
movdqa xmm12, xmmword ptr [rsp+20H]
movdqa xmm5, xmmword ptr [rsp+40H]
pshufd xmm13, xmm12, 0FH
shufps xmm12, xmm5, 214
pshufd xmm4, xmm12, 39H
movdqa xmm12, xmm6
shufps xmm12, xmm7, 250
pand xmm13, xmmword ptr [PBLENDW_0x33_MASK]
pand xmm12, xmmword ptr [PBLENDW_0xCC_MASK]
por xmm13, xmm12
movdqa xmmword ptr [rsp+20H], xmm13
movdqa xmm12, xmm7
punpcklqdq xmm12, xmm5
movdqa xmm13, xmm6
pand xmm12, xmmword ptr [PBLENDW_0x3F_MASK]
pand xmm13, xmmword ptr [PBLENDW_0xC0_MASK]
por xmm12, xmm13
pshufd xmm12, xmm12, 78H
punpckhdq xmm5, xmm7
punpckldq xmm6, xmm5
pshufd xmm7, xmm6, 1EH
movdqa xmmword ptr [rsp+40H], xmm12
movdqa xmm5, xmmword ptr [rsp+30H]
movdqa xmm13, xmmword ptr [rsp+50H]
pshufd xmm6, xmm5, 0FH
shufps xmm5, xmm13, 214
pshufd xmm12, xmm5, 39H
movdqa xmm5, xmm14
shufps xmm5, xmm15, 250
pand xmm6, xmmword ptr [PBLENDW_0x33_MASK]
pand xmm5, xmmword ptr [PBLENDW_0xCC_MASK]
por xmm6, xmm5
movdqa xmm5, xmm15
punpcklqdq xmm5, xmm13
movdqa xmmword ptr [rsp+30H], xmm2
movdqa xmm2, xmm14
pand xmm5, xmmword ptr [PBLENDW_0x3F_MASK]
pand xmm2, xmmword ptr [PBLENDW_0xC0_MASK]
por xmm5, xmm2
movdqa xmm2, xmmword ptr [rsp+30H]
pshufd xmm5, xmm5, 78H
punpckhdq xmm13, xmm15
punpckldq xmm14, xmm13
pshufd xmm15, xmm14, 1EH
movdqa xmm13, xmm6
movdqa xmm14, xmm5
movdqa xmm5, xmmword ptr [rsp+20H]
movdqa xmm6, xmmword ptr [rsp+40H]
jmp roundloop2
endroundloop2:
pxor xmm0, xmm2
pxor xmm1, xmm3
pxor xmm8, xmm10
pxor xmm9, xmm11
mov eax, r13d
cmp rdx, r15
jne innerloop2
movups xmmword ptr [rbx], xmm0
movups xmmword ptr [rbx+10H], xmm1
movups xmmword ptr [rbx+20H], xmm8
movups xmmword ptr [rbx+30H], xmm9
mov eax, dword ptr [rsp+130H]
neg eax
mov r10d, dword ptr [rsp+110H+8*rax]
mov r11d, dword ptr [rsp+120H+8*rax]
mov dword ptr [rsp+110H], r10d
mov dword ptr [rsp+120H], r11d
add rdi, 16
add rbx, 64
sub rsi, 2
final1block:
test esi, 1H
je unwind
movups xmm0, xmmword ptr [rcx]
movups xmm1, xmmword ptr [rcx+10H]
movd xmm13, dword ptr [rsp+110H]
movd xmm14, dword ptr [rsp+120H]
punpckldq xmm13, xmm14
mov r8, qword ptr [rdi]
movzx eax, byte ptr [rbp+80H]
or eax, r13d
xor edx, edx
innerloop1:
mov r14d, eax
or eax, r12d
add rdx, 64
cmp rdx, r15
cmovne eax, r14d
movaps xmm2, xmmword ptr [BLAKE3_IV]
shl rax, 32
or rax, 64
movd xmm12, rax
movdqa xmm3, xmm13
punpcklqdq xmm3, xmm12
movups xmm4, xmmword ptr [r8+rdx-40H]
movups xmm5, xmmword ptr [r8+rdx-30H]
movaps xmm8, xmm4
shufps xmm4, xmm5, 136
shufps xmm8, xmm5, 221
movaps xmm5, xmm8
movups xmm6, xmmword ptr [r8+rdx-20H]
movups xmm7, xmmword ptr [r8+rdx-10H]
movaps xmm8, xmm6
shufps xmm6, xmm7, 136
pshufd xmm6, xmm6, 93H
shufps xmm8, xmm7, 221
pshufd xmm7, xmm8, 93H
mov al, 7
roundloop1:
paddd xmm0, xmm4
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm5
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 93H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 39H
paddd xmm0, xmm6
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm7
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 39H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 93H
dec al
jz endroundloop1
movdqa xmm8, xmm4
shufps xmm8, xmm5, 214
pshufd xmm9, xmm4, 0FH
pshufd xmm4, xmm8, 39H
movdqa xmm8, xmm6
shufps xmm8, xmm7, 250
pand xmm9, xmmword ptr [PBLENDW_0x33_MASK]
pand xmm8, xmmword ptr [PBLENDW_0xCC_MASK]
por xmm9, xmm8
movdqa xmm8, xmm7
punpcklqdq xmm8, xmm5
movdqa xmm10, xmm6
pand xmm8, xmmword ptr [PBLENDW_0x3F_MASK]
pand xmm10, xmmword ptr [PBLENDW_0xC0_MASK]
por xmm8, xmm10
pshufd xmm8, xmm8, 78H
punpckhdq xmm5, xmm7
punpckldq xmm6, xmm5
pshufd xmm7, xmm6, 1EH
movdqa xmm5, xmm9
movdqa xmm6, xmm8
jmp roundloop1
endroundloop1:
pxor xmm0, xmm2
pxor xmm1, xmm3
mov eax, r13d
cmp rdx, r15
jne innerloop1
movups xmmword ptr [rbx], xmm0
movups xmmword ptr [rbx+10H], xmm1
jmp unwind
_blake3_hash_many_sse2 ENDP
blake3_hash_many_sse2 ENDP
blake3_compress_in_place_sse2 PROC
_blake3_compress_in_place_sse2 PROC
sub rsp, 120
movdqa xmmword ptr [rsp], xmm6
movdqa xmmword ptr [rsp+10H], xmm7
movdqa xmmword ptr [rsp+20H], xmm8
movdqa xmmword ptr [rsp+30H], xmm9
movdqa xmmword ptr [rsp+40H], xmm11
movdqa xmmword ptr [rsp+50H], xmm14
movdqa xmmword ptr [rsp+60H], xmm15
movups xmm0, xmmword ptr [rcx]
movups xmm1, xmmword ptr [rcx+10H]
movaps xmm2, xmmword ptr [BLAKE3_IV]
movzx eax, byte ptr [rsp+0A0H]
movzx r8d, r8b
shl rax, 32
add r8, rax
movd xmm3, r9
movd xmm4, r8
punpcklqdq xmm3, xmm4
movups xmm4, xmmword ptr [rdx]
movups xmm5, xmmword ptr [rdx+10H]
movaps xmm8, xmm4
shufps xmm4, xmm5, 136
shufps xmm8, xmm5, 221
movaps xmm5, xmm8
movups xmm6, xmmword ptr [rdx+20H]
movups xmm7, xmmword ptr [rdx+30H]
movaps xmm8, xmm6
shufps xmm6, xmm7, 136
pshufd xmm6, xmm6, 93H
shufps xmm8, xmm7, 221
pshufd xmm7, xmm8, 93H
mov al, 7
@@:
paddd xmm0, xmm4
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm5
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 93H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 39H
paddd xmm0, xmm6
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm7
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 39H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 93H
dec al
jz @F
movdqa xmm8, xmm4
shufps xmm8, xmm5, 214
pshufd xmm9, xmm4, 0FH
pshufd xmm4, xmm8, 39H
movdqa xmm8, xmm6
shufps xmm8, xmm7, 250
pand xmm9, xmmword ptr [PBLENDW_0x33_MASK]
pand xmm8, xmmword ptr [PBLENDW_0xCC_MASK]
por xmm9, xmm8
movdqa xmm8, xmm7
punpcklqdq xmm8, xmm5
movdqa xmm10, xmm6
pand xmm8, xmmword ptr [PBLENDW_0x3F_MASK]
pand xmm10, xmmword ptr [PBLENDW_0xC0_MASK]
por xmm8, xmm10
pshufd xmm8, xmm8, 78H
punpckhdq xmm5, xmm7
punpckldq xmm6, xmm5
pshufd xmm7, xmm6, 1EH
movdqa xmm5, xmm9
movdqa xmm6, xmm8
jmp @B
@@:
pxor xmm0, xmm2
pxor xmm1, xmm3
movups xmmword ptr [rcx], xmm0
movups xmmword ptr [rcx+10H], xmm1
movdqa xmm6, xmmword ptr [rsp]
movdqa xmm7, xmmword ptr [rsp+10H]
movdqa xmm8, xmmword ptr [rsp+20H]
movdqa xmm9, xmmword ptr [rsp+30H]
movdqa xmm11, xmmword ptr [rsp+40H]
movdqa xmm14, xmmword ptr [rsp+50H]
movdqa xmm15, xmmword ptr [rsp+60H]
add rsp, 120
ret
_blake3_compress_in_place_sse2 ENDP
blake3_compress_in_place_sse2 ENDP
ALIGN 16
blake3_compress_xof_sse2 PROC
_blake3_compress_xof_sse2 PROC
sub rsp, 120
movdqa xmmword ptr [rsp], xmm6
movdqa xmmword ptr [rsp+10H], xmm7
movdqa xmmword ptr [rsp+20H], xmm8
movdqa xmmword ptr [rsp+30H], xmm9
movdqa xmmword ptr [rsp+40H], xmm11
movdqa xmmword ptr [rsp+50H], xmm14
movdqa xmmword ptr [rsp+60H], xmm15
movups xmm0, xmmword ptr [rcx]
movups xmm1, xmmword ptr [rcx+10H]
movaps xmm2, xmmword ptr [BLAKE3_IV]
movzx eax, byte ptr [rsp+0A0H]
movzx r8d, r8b
mov r10, qword ptr [rsp+0A8H]
shl rax, 32
add r8, rax
movd xmm3, r9
movd xmm4, r8
punpcklqdq xmm3, xmm4
movups xmm4, xmmword ptr [rdx]
movups xmm5, xmmword ptr [rdx+10H]
movaps xmm8, xmm4
shufps xmm4, xmm5, 136
shufps xmm8, xmm5, 221
movaps xmm5, xmm8
movups xmm6, xmmword ptr [rdx+20H]
movups xmm7, xmmword ptr [rdx+30H]
movaps xmm8, xmm6
shufps xmm6, xmm7, 136
pshufd xmm6, xmm6, 93H
shufps xmm8, xmm7, 221
pshufd xmm7, xmm8, 93H
mov al, 7
@@:
paddd xmm0, xmm4
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm5
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 93H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 39H
paddd xmm0, xmm6
paddd xmm0, xmm1
pxor xmm3, xmm0
pshuflw xmm3, xmm3, 0B1H
pshufhw xmm3, xmm3, 0B1H
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 20
psrld xmm11, 12
por xmm1, xmm11
paddd xmm0, xmm7
paddd xmm0, xmm1
pxor xmm3, xmm0
movdqa xmm14, xmm3
psrld xmm3, 8
pslld xmm14, 24
pxor xmm3, xmm14
paddd xmm2, xmm3
pxor xmm1, xmm2
movdqa xmm11, xmm1
pslld xmm1, 25
psrld xmm11, 7
por xmm1, xmm11
pshufd xmm0, xmm0, 39H
pshufd xmm3, xmm3, 4EH
pshufd xmm2, xmm2, 93H
dec al
jz @F
movdqa xmm8, xmm4
shufps xmm8, xmm5, 214
pshufd xmm9, xmm4, 0FH
pshufd xmm4, xmm8, 39H
movdqa xmm8, xmm6
shufps xmm8, xmm7, 250
pand xmm9, xmmword ptr [PBLENDW_0x33_MASK]
pand xmm8, xmmword ptr [PBLENDW_0xCC_MASK]
por xmm9, xmm8
movdqa xmm8, xmm7
punpcklqdq xmm8, xmm5
movdqa xmm10, xmm6
pand xmm8, xmmword ptr [PBLENDW_0x3F_MASK]
pand xmm10, xmmword ptr [PBLENDW_0xC0_MASK]
por xmm8, xmm10
pshufd xmm8, xmm8, 78H
punpckhdq xmm5, xmm7
punpckldq xmm6, xmm5
pshufd xmm7, xmm6, 1EH
movdqa xmm5, xmm9
movdqa xmm6, xmm8
jmp @B
@@:
movdqu xmm4, xmmword ptr [rcx]
movdqu xmm5, xmmword ptr [rcx+10H]
pxor xmm0, xmm2
pxor xmm1, xmm3
pxor xmm2, xmm4
pxor xmm3, xmm5
movups xmmword ptr [r10], xmm0
movups xmmword ptr [r10+10H], xmm1
movups xmmword ptr [r10+20H], xmm2
movups xmmword ptr [r10+30H], xmm3
movdqa xmm6, xmmword ptr [rsp]
movdqa xmm7, xmmword ptr [rsp+10H]
movdqa xmm8, xmmword ptr [rsp+20H]
movdqa xmm9, xmmword ptr [rsp+30H]
movdqa xmm11, xmmword ptr [rsp+40H]
movdqa xmm14, xmmword ptr [rsp+50H]
movdqa xmm15, xmmword ptr [rsp+60H]
add rsp, 120
ret
_blake3_compress_xof_sse2 ENDP
blake3_compress_xof_sse2 ENDP
_TEXT ENDS
_RDATA SEGMENT READONLY PAGE ALIAS(".rdata") 'CONST'
ALIGN 64
BLAKE3_IV:
dd 6A09E667H, 0BB67AE85H, 3C6EF372H, 0A54FF53AH
ADD0:
dd 0, 1, 2, 3
ADD1:
dd 4 dup (4)
BLAKE3_IV_0:
dd 4 dup (6A09E667H)
BLAKE3_IV_1:
dd 4 dup (0BB67AE85H)
BLAKE3_IV_2:
dd 4 dup (3C6EF372H)
BLAKE3_IV_3:
dd 4 dup (0A54FF53AH)
BLAKE3_BLOCK_LEN:
dd 4 dup (64)
CMP_MSB_MASK:
dd 8 dup(80000000H)
PBLENDW_0x33_MASK:
dd 0FFFFFFFFH, 000000000H, 0FFFFFFFFH, 000000000H
PBLENDW_0xCC_MASK:
dd 000000000H, 0FFFFFFFFH, 000000000H, 0FFFFFFFFH
PBLENDW_0x3F_MASK:
dd 0FFFFFFFFH, 0FFFFFFFFH, 0FFFFFFFFH, 000000000H
PBLENDW_0xC0_MASK:
dd 000000000H, 000000000H, 000000000H, 0FFFFFFFFH
_RDATA ENDS
END
|
; stdio_numprec
; 05.2008 aralbrec
PUBLIC stdio_numprec
EXTERN stdio_utoa_any
INCLUDE "../stdio.def"
; outputs unsigned integer to string buffer taking precision into account
;
; enter : a = precision
; b = num chars in buffer
; c = radix
; de = number
; hl = & next free position in destination buffer
; exit : b = num chars in buffer
; hl = & next free position in destination buffer
; uses : af, b, de, hl
.stdio_numprec
cp STDIO_MAXPRECISION + 1 ; limit precision to protect buffer
jr c, precok
ld a,STDIO_MAXPRECISION
.precok
add a,b
push af ; save precision
cp b ; zero precision?
jr nz, notzeroprec
ld a,d ; special case: zero precison and integer == 0 means don't print number
or e
jr z, skipoutput
.notzeroprec
; b = num chars in buffer
; c = radix
; de = number
; hl = & destination buffer
call stdio_utoa_any ; write unsigned integer into buffer
.skipoutput
pop af ; a = precision
.handleprec
sub b ; is precision requirement satisfied?
ret c ; precision satisfied, all done
.precloop ; if not add leading zeroes before the sign
or a
ret z
ld (hl),'0'
dec hl
inc b
dec a
jp precloop
|
;[]------------------------------------------------------------[]
;| _FTOUL.ASM -- Float to 64-bit unsigned long conversion |
;[]------------------------------------------------------------[]
;
; C/C++ Run Time Library - Version 10.0
;
; Copyright (c) 1996, 2000 by Inprise Corporation
; All Rights Reserved.
;
; $Revision: 9.0 $
include RULES.ASI
Header@
Data_Seg@
Data_EndS@
Code_Seg@
;
; _ftoul - Takes a float and returns an unsigned __int64
;
; Prototype: unsigned __int64 _ftoul (float value);
;
Func@ _ftoul, _EXPFUNC, cdecl
add esp,-12
fstcw [esp]
fwait
mov al,[esp+1]
or byte ptr [esp+1],0Ch ; Rounding control -> Chop
fldcw [esp]
fistp qword ptr [esp+4]
mov byte ptr [esp+1], al
fldcw [esp]
mov eax,[esp+4]
mov edx,[esp+8]
add esp,12
Return@
EndFunc@ _ftoul
Code_EndS@
end
|
; A142981: a(1) = 1, a(2) = 7, a(n+2) = 7*a(n+1) + (n+1)^2*a(n).
; Submitted by Jon Maiga
; 1,7,53,434,3886,38052,406260,4708368,58959216,794092320,11454567840,176267145600,2883327788160,49972442123520,914939341344000,17648374867200000,357763095454464000,7604722004802048000,169148296960860672000,3929342722459564032000,95164717841561217024000,2398993165495596257280000,62852675593784802840576000,1709036113703664039985152000,48166393937945694716067840000,1405312328630409888003194880000,42397668602464158844084224000000,1321256367788817920262918635520000,42488566758853625975602462064640000
mov $3,1
lpb $0
mov $2,$3
mul $3,7
add $3,$1
mov $1,$0
mul $2,$0
sub $0,1
mul $1,$2
lpe
mov $0,$3
|
; ----------------------------------------------------------------------------
; Copyright 1987-1988,2019 by T.Zoerner (tomzo at users.sf.net)
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; ----------------------------------------------------------------------------
module BUTTON_2
;section fuenf
;pagelen 32767
;pagewid 133
;noexpand
include "f_sys.s"
include "f_def.s"
;
XREF frradier,frpinsel,frmuster,new_1koo,new_2koo,vdicall
XREF hide_m,show_m,noch_qu,return,set_wrmo,win_xy,logbase
XREF bildbuff,frsprayd,frlinie,frpunkt,noch_qu,clip_on
XREF set_attr,set_att2,ret_attr,ret_att2,chooset,sinus
;
XDEF punkt,pinsel,spdose,radier,gummi,kurve
*-----------------------------------------------------------------------------
* This module (together with "fg.asm") contains handlers for drawing
* operations, which all start with a mouse click into an image window.
* See "fg.asm for details.
*-----------------------------------------------------------------------------
* Global register mapping:
*
* [a4 Address of address of current window record] - unused
* a6 Base address of data section
*-----------------------------------------------------------------------------
;
punkt clr.w d1 *** Shape: Pencil ***
move.b frpunkt+33,d1
bne punkt2
; ------- Pencil ------
vdi 15 0 1 1 ;polyline type: solid
vdi 16 1 0 !frpunkt+6 0 ;line width
vdi 17 0 1 !frpunkt+20 ;polyline color index
vdi 108 0 2 0 0 ;polyline end style: squared
bsr set_wrmo ;writing mode
bsr hide_m
move.l d3,d4
move.w frpunkt+6,d0
cmp #1,d0 line width larger than 1?
beq punkt1
subq.w #1,d0 yes: draw initial dot: square with line width
swap d0 ;(needed as VDI does not draw anything when X1/Y1==X2/Y2)
ext.w d0
add.l d3,d0
move.l d0,PTSIN+0(a6)
move.l d3,PTSIN+4(a6)
vdi 6 2 0 ;polyline
bra.s punkt4
punkt1 move.l d3,PTSIN+0(a6) -- Loop while mouse button pressed --
move.l d4,PTSIN+4(a6)
vdi 6 2 0 ;polyline: draw from prev. to current mouse coord.
punkt4 bsr show_m
bsr new_1koo Pos. merken
move.l d3,d4
bsr noch_qu
bsr hide_m
move.l last_koo+4,d0
tst.b MOUSE_LBUT+1(a6)
bne punkt1 -> another dot to draw
bra ret_attr
;
punkt2 addq.b #1,d1 ------ Polymarker ------
vdi 18 0 1 !d1 ;set_polymarker_type
move.w frpunkt+6,d0
mulu.w #11,d0
sub.w #5,d0
vdi 19 1 0 0 !d0 ;...height
vdi 20 0 1 !frpunkt+20 ;...color_index
bsr set_wrmo ;...writing_mode
bsr clip_on
punkt3 bsr hide_m -- Loop while mouse button pressed --
bsr new_1koo
move.l d3,PTSIN+0(a6)
vdi 7 1 0 ;polymarker
bsr show_m
bsr noch_qu
tst.b MOUSE_LBUT+1(a6)
bne punkt3 loop to next marker
bsr hide_m
bra return
;
*-----------------------------------------------------------------------------
pinsel move.b frpinsel+33,d0 *** Shape: Brush ***
cmp.b #4,d0
beq pinsel7
pinsel6 bsr set_wrmo -- initialization --
bsr clip_on
vdi 23 0 1 !frmuster+6 ; fill style
vdi 24 0 1 !frmuster+20 ; fill index
vdi 25 0 1 !frpinsel+20 ; fill color
vdi 104 0 1 0 ; border off
clr.w d0 calc. the offset table
move.b frpinsel+33,d0 get shape of the brush from config
lsl.w #2,d0
lea pin_data,a0
add.w d0,a0
move.w frpinsel+6,d6 get size of the brush from config
move.w d6,d7
muls.w (a0)+,d6 D6: X-offset
bne.s pinsel11
add.w #1,d6
pinsel11 muls.w (a0),d7 D7: Y-offset
bne.s pinsel1
add.w #1,d7
pinsel1 move.l d3,d4 -- Loop while mouse button pressed --
bsr noch_qu
bsr hide_m
tst.b MOUSE_LBUT+1(a6)
beq ret_att2 -> done
move.l d3,PTSIN+0(a6)
move.l d4,PTSIN+4(a6)
move.l d4,PTSIN+8(a6)
move.l d3,PTSIN+12(a6)
sub.w d6,PTSIN+0(a6)
sub.w d6,PTSIN+4(a6)
add.w d6,PTSIN+8(a6)
add.w d6,PTSIN+12(a6)
sub.w d7,PTSIN+2(a6)
sub.w d7,PTSIN+6(a6)
add.w d7,PTSIN+10(a6)
add.w d7,PTSIN+14(a6)
vdi 9 4 0 ;filled area (4 corners)
bsr show_m
bra pinsel1
;
pinsel7 move.w frpinsel+6,d0 --- Shape "O" brush ---
beq pinsel6
lsl.w #1,d0
addq.w #1,d0
vdi 16 1 0 !d0 0 ; polyline line width: brush width
vdi 17 0 1 !frpinsel+20 ; polyline color
vdi 108 0 2 0 2 ; polyline end style: round end
bsr set_wrmo
bsr clip_on
pinsel8 move.l d3,d4 -- Loop while mouse button pressed --
bsr noch_qu
tst.b MOUSE_LBUT+1(a6)
beq.s pinsel9
bsr hide_m
move.l d3,PTSIN+0(a6) ; X1/Y1 = X2/Y2
move.l d4,PTSIN+4(a6)
vdi 6 2 0 ; polyline
bsr show_m
bra pinsel8
pinsel9 move.l PTSIN+0(a6),d0
move.l PTSIN+4(a6),d1
bsr new_2koo
vdi 16 1 0 1 0
vdi 17 0 1 1
vdi 108 0 2 0 0
bsr hide_m
bra return
;
*-----------------------------------------------------------------------------
spdose bsr hide_m *** Shape: Spraycan ***
moveq.l #1,d6
moveq.l #1,d7
clr.w d0
move.b frsprayd+19,d0 get spray mode from config
move.w d0,d1
lsl.w #1,d1
lea spdosex,a0
move.w (a0,d1.w),spdose7-spdosex(a0)
cmp.b #3,d0 INV-Modus ?
blo.s spdose9
move.l bildbuff,a0
move.w #3999,d0
spdose10 clr.l (a0)+
clr.l (a0)+
dbra d0,spdose10
spdose9 move.l bildbuff,a0 initialize density table
lea spr_dich,a1
moveq.l #15,d0
spdose2 move.w frsprayd+6,d1 get spray radius from config
addq.w #1,d1
mulu.w (a1)+,d1
lsr.w #7,d1
move.w d1,(a0)+
dbra d0,spdose2
move.l bildbuff,a3 A3: Address of density table
lea sinus,a4
spdose1 move.w #17,-(sp) get RAND number
trap #14
addq.l #2,sp
move.l d0,d5
add.w d0,d7 D7: angle * 2
eor.w d6,d7
and.w #$fe,d7
cmp.w #180,d7
blo.s spdose3
sub.w #180,d7
spdose3 lsr.l #8,d0
add.w d0,d6 D6: radius
eor.w d7,d6
lsr.w #8,d0
and.w #$1e,d0
divu (a3,d0.w),d6
clr.w d6
swap d6
move.w d6,d2
mulu.w (a4,d7.w),d2 D2: Y-offset
swap d2
rol.l #1,d2
move.w d6,d1
neg.w d7
add.w #180,d7
mulu.w (a4,d7.w),d1 D1: X-offset
swap d1
rol.l #1,d1
btst #23,d5
beq.s spdose4
neg.w d2
spdose4 btst #22,d5
beq.s spdose5
neg.w d1
spdose5 sub.l a0,a0 calc pixel-addresse
move.w d3,d4
add.w d2,d4
cmp.w win_xy+2,d4 still within the window?
blo.s spdose6
cmp.w win_xy+6,d4
bhi.s spdose6
mulu.w #80,d4
add.l d4,a0 Y-byte
swap d3
add.w d1,d3
cmp.w win_xy,d3 still within the window?
blo.s spdose6
cmp.w win_xy+4,d3
bhi.s spdose6
move.w d3,d4
lsr.w #3,d3
add.w d3,a0 X-byte
and.w #7,d4
neg.w d4
add.w #7,d4
move.b frsprayd+19,d0 INV mode?
cmp.b #3,d0
blo.s spdose8
move.l bildbuff,a1
add.l a0,a1
bset.b d4,(a1)
bne.s spdose6
spdose8 add.l logbase,a0
spdose7 bset.b d4,(a0)
spdose6 move.l MOUSE_CUR_XY(a6),d3
tst.b MOUSE_LBUT+1(a6)
bne spdose1
rts
spdosex bclr.b d4,(a0) op-code table for different spray modes
bset.b d4,(a0)
bchg.b d4,(a0)
bchg.b d4,(a0)
;
*-----------------------------------------------------------------------------
gummi bsr set_att2 *** Shape: Rubberband ***
move.l d3,d7
clr.w d0
clr.w d1
move.b frlinie+47,d0
move.b frlinie+49,d1
vdi 108 0 2 !d0 !d1 ;set_line_end
gummi1 bsr show_m
bsr noch_qu
bsr hide_m
tst.b MOUSE_LBUT+1(a6)
beq ret_attr
move.l d7,PTSIN+0(a6)
move.l d3,PTSIN+4(a6)
vdi 6 2 0 ;polyline
bra gummi1
;
*-----------------------------------------------------------------------------
radier move.b frradier+33,d0 *** Shape: Eraser ***
bne.s radier3
bsr clip_on -- normal mode --
vdi 32 0 1 1 ;set writing mode: replace
vdi 23 0 1 1 ;fill pattern type: opaque
vdi 25 0 1 0 ;fill color: 0
bra.s radier4
radier3 lea chooset,a3 -- pattern mode --
move.w (a3),d6 D6/D7: backup shape fill configuration
move.w 4(a3),d7
move.w #-1,(a3) temporarily enable fill & rounded corner (actually unused)
clr.w 4(a3) temporarily disable border
bsr set_attr
move.w d6,(a3) restore config.
move.w d7,4(a3)
radier4 move.w frradier+6,d5 X-offset
move.w d5,d7
lsr.w #1,d5
lsr.w #1,d7
bcs.s radier2
subq.w #1,d7
radier2 swap d7
move.w frradier+20,d6 Y-offset
move.w d6,d7
lsr.w #1,d6
lsr.w #1,d7
bcs.s radier1
subq.w #1,d7
radier1 bsr hide_m ++ loop ++
move.l d3,PTSIN+0(a6)
move.l d3,PTSIN+4(a6)
sub.w d5,PTSIN+0(a6)
sub.w d6,PTSIN+2(a6)
add.l d7,PTSIN+4(a6)
move.w #1,CONTRL+10(a6)
vdi 11 2 0 ;bar
bsr show_m
bsr noch_qu
tst.b MOUSE_LBUT+1(a6)
bne radier1 -> continue loop
bsr hide_m
bra ret_att2
;
kurve bra hide_m *** Curve ***
;
*-----------------------------------------------------------------DATA--------
pin_data dc.w 0,1 ; shape "|"
dc.w 1,0 ; shape "-"
dc.w 1,-1 ; shape "/"
dc.w 1,1 ; shape "\" (note shape "O" handled separately)
spr_dich dc.w 60,76,85,90,95,96,97,98,99,103,108,111,115,120,124,128
*-----------------------------------------------------------------------------
END
|
; A239031: Number of 4 X n 0..2 arrays with no element equal to the sum of elements to its left or one plus the sum of the elements above it, modulo 3.
; 4,11,28,59,110,189,306,473,704,1015,1424,1951,2618,3449,4470,5709,7196,8963,11044,13475,16294,19541,23258,27489,32280,37679,43736,50503,58034,66385,75614,85781,96948,109179,122540,137099,152926,170093,188674,208745,230384,253671,278688,305519,334250,364969,397766,432733,469964,509555,551604,596211,643478,693509,746410,802289,861256,923423,988904,1057815,1130274,1206401,1286318,1370149,1458020,1550059,1646396,1747163,1852494,1962525,2077394,2197241,2322208,2452439,2588080,2729279,2876186,3028953,3187734,3352685,3523964,3701731,3886148,4077379,4275590,4480949,4693626,4913793,5141624,5377295,5620984,5872871,6133138,6401969,6679550,6966069,7261716,7566683,7881164,8205355,8539454,8883661,9238178,9603209,9978960,10365639,10763456,11172623,11593354,12025865,12470374,12927101,13396268,13878099,14372820,14880659,15401846,15936613,16485194,17047825,17624744,18216191,18822408,19443639,20080130,20732129,21399886,22083653,22783684,23500235,24233564,24983931,25751598,26536829,27339890,28161049,29000576,29858743,30735824,31632095,32547834,33483321,34438838,35414669,36411100,37428419,38466916,39526883,40608614,41712405,42838554,43987361,45159128,46354159,47572760,48815239,50081906,51373073,52689054,54030165,55396724,56789051,58207468,59652299,61123870,62622509,64148546,65702313,67284144,68894375,70533344,72201391,73898858,75626089,77383430,79171229,80989836,82839603,84720884,86634035,88579414,90557381,92568298,94612529,96690440,98802399,100948776,103129943,105346274,107598145,109885934,112210021,114570788,116968619,119403900,121877019,124388366,126938333,129527314,132155705,134823904,137532311,140281328,143071359,145902810,148776089,151691606,154649773,157651004,160695715
mov $4,$0
mov $5,$0
lpb $0,1
sub $0,1
add $2,1
add $3,$2
add $4,$3
add $4,2
sub $4,$2
add $1,$4
lpe
add $1,1
mul $1,2
sub $1,1
lpb $5,1
add $1,1
sub $5,1
lpe
add $1,3
|
; A137893: Fixed point of the morphism 0->100, 1->101, starting from a(1) = 1.
; 1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,0,1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,0,1,0,1,1,0,0,1,0,0,1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,0,1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,1,1,0,1,1,0,0,1,0,0,1,0,1,1,0,0
add $0,1
mul $0,2
mov $1,$0
lpb $0,2
div $1,3
gcd $1,$0
lpe
sub $1,1
|
; void closeall(void)
; 07.2009 aralbrec
XLIB closeall
LIB close
XREF LIBDISP2_CLOSE
INCLUDE "../stdio.def"
; close all open fds
; does not close any open FILEs -- for that see fcloseall
; fcloseall should always be called before closeall
; running closeall without first running fcloseall can
; orphan open FILEs with bad consequences.
.closeall
ld hl,_stdio_fdtbl
ld b,STDIO_NUMFD
.loop
ld e,(hl)
ld ixl,e
inc hl
ld a,(hl)
ld ixh,a ; ix = fdstruct*
push hl
push bc
or e
call nz, close + LIBDISP2_CLOSE
pop bc
pop hl
inc hl
djnz loop
ret
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r12
push %r15
push %r9
push %rbp
push %rcx
lea addresses_A_ht+0xaa3a, %r10
clflush (%r10)
nop
xor %r11, %r11
mov (%r10), %cx
nop
nop
nop
nop
sub %r12, %r12
lea addresses_UC_ht+0x174aa, %r11
nop
xor %rbp, %rbp
mov (%r11), %r15w
nop
nop
nop
and %r11, %r11
lea addresses_WC_ht+0xeeea, %r11
add $19514, %r9
mov $0x6162636465666768, %rcx
movq %rcx, %xmm5
vmovups %ymm5, (%r11)
nop
nop
inc %rcx
pop %rcx
pop %rbp
pop %r9
pop %r15
pop %r12
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r15
push %r8
push %r9
push %rbp
push %rbx
push %rdx
// Store
lea addresses_D+0x83ca, %r15
sub $16463, %rbx
mov $0x5152535455565758, %r8
movq %r8, (%r15)
nop
nop
nop
nop
xor $8974, %rbp
// Faulty Load
lea addresses_PSE+0x1beea, %r9
nop
nop
nop
nop
add %r8, %r8
mov (%r9), %dx
lea oracles, %r8
and $0xff, %rdx
shlq $12, %rdx
mov (%r8,%rdx,1), %rdx
pop %rdx
pop %rbx
pop %rbp
pop %r9
pop %r8
pop %r15
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'size': 4, 'AVXalign': True, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 11, 'same': False}}
{'33': 195}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
|
; A155626: 5^n-4^n+1.
; 1,2,10,62,370,2102,11530,61742,325090,1690982,8717050,44633822,227363410,1153594262,5835080170,29443836302,148292923330,745759583942,3745977788890,18798608421182,94267920012850,472439111692022
mov $2,13
lpb $0,1
sub $0,1
add $1,$2
mul $1,5
mul $2,4
lpe
div $1,65
add $1,1
|
;
; ^C status routines for MSDOS
;
INCLUDE DOSSEG.ASM
CODE SEGMENT BYTE PUBLIC 'CODE'
ASSUME SS:DOSGROUP,CS:DOSGROUP
.xlist
.xcref
INCLUDE DOSSYM.ASM
INCLUDE DEVSYM.ASM
.cref
.list
i_need DevIOBuf,BYTE
i_need DidCTRLC,BYTE
i_need INDOS,BYTE
i_need DSKSTCOM,BYTE
i_need DSKSTCALL,BYTE
i_need DSKSTST,WORD
i_need BCON,DWORD
i_need DSKCHRET,BYTE
i_need DSKSTCNT,WORD
i_need IDLEINT,BYTE
i_need CONSWAP,BYTE
i_need user_SS,WORD
i_need user_SP,WORD
i_need ERRORMODE,BYTE
i_need ConC_spSave,WORD
i_need Exit_type,BYTE
i_need PFLAG,BYTE
i_need ExitHold,DWORD
i_need WPErr,BYTE
i_need ReadOp,BYTE
i_need CONTSTK,WORD
i_need Exit_Code,WORD
i_need CurrentPDB,WORD
i_need DIVMES,BYTE
i_need DivMesLen,BYTE
SUBTTL Checks for ^C in CON I/O
PAGE
ASSUME DS:NOTHING,ES:NOTHING
procedure DSKSTATCHK,NEAR ; Check for ^C if only one level in
CMP BYTE PTR [INDOS],1
retnz ; Do NOTHING
PUSH CX
PUSH ES
PUSH BX
PUSH DS
PUSH SI
PUSH CS
POP ES
PUSH CS
POP DS
ASSUME DS:DOSGROUP
XOR CX,CX
MOV BYTE PTR [DSKSTCOM],DEVRDND
MOV BYTE PTR [DSKSTCALL],DRDNDHL
MOV [DSKSTST],CX
MOV BX,OFFSET DOSGROUP:DSKSTCALL
LDS SI,[BCON]
ASSUME DS:NOTHING
invoke DEVIOCALL2
TEST [DSKSTST],STBUI
JNZ ZRET ; No characters available
MOV AL,BYTE PTR [DSKCHRET]
DSK1:
CMP AL,"C"-"@"
JNZ RET36
MOV BYTE PTR [DSKSTCOM],DEVRD
MOV BYTE PTR [DSKSTCALL],DRDWRHL
MOV BYTE PTR [DSKCHRET],CL
MOV [DSKSTST],CX
INC CX
MOV [DSKSTCNT],CX
invoke DEVIOCALL2 ; Eat the ^C
POP SI
POP DS
POP BX ; Clean stack
POP ES
POP CX
JMP SHORT CNTCHAND
ZRET:
XOR AL,AL ; Set zero
RET36:
POP SI
POP DS
POP BX
POP ES
POP CX
return
NOSTOP:
CMP AL,"P"-"@"
JZ INCHK
IF NOT TOGLPRN
CMP AL,"N"-"@"
JZ INCHK
ENDIF
CMP AL,"C"-"@"
JZ INCHK
return
DSKSTATCHK ENDP
procedure SPOOLINT,NEAR
PUSHF
CMP BYTE PTR [IDLEINT],0
JZ POPFRET
CMP BYTE PTR [ERRORMODE],0
JNZ POPFRET ;No spool ints in error mode
INT int_spooler
POPFRET:
POPF
RET18: return
SPOOLINT ENDP
procedure STATCHK,NEAR
invoke DSKSTATCHK ; Allows ^C to be detected under
; input redirection
PUSH BX
XOR BX,BX
invoke GET_IO_FCB
POP BX
JC RET18
MOV AH,1
invoke IOFUNC
JZ SPOOLINT
CMP AL,'S'-'@'
JNZ NOSTOP
XOR AH,AH
invoke IOFUNC ; Eat Cntrl-S
JMP SHORT PAUSOSTRT
PRINTOFF:
PRINTON:
NOT BYTE PTR [PFLAG]
return
PAUSOLP:
CALL SPOOLINT
PAUSOSTRT:
MOV AH,1
invoke IOFUNC
JZ PAUSOLP
INCHK:
PUSH BX
XOR BX,BX
invoke GET_IO_FCB
POP BX
JC RET18
XOR AH,AH
invoke IOFUNC
CMP AL,'P'-'@'
JZ PRINTON
IF NOT TOGLPRN
CMP AL,'N'-'@'
JZ PRINTOFF
ENDIF
CMP AL,'C'-'@'
retnz
STATCHK ENDP
procedure CNTCHAND,NEAR
; Ctrl-C handler.
; "^C" and CR/LF is printed. Then the user registers are restored and
; the user CTRL-C handler is executed. At this point the top of the stack
; has 1) the interrupt return address should the user CTRL-C handler wish
; to allow processing to continue; 2) the original interrupt return address
; to the code that performed the function call in the first place. If
; the user CTRL-C handler wishes to continue, it must leave all registers
; unchanged and RET (not IRET) with carry CLEAR. If carry is SET then
; an terminate system call is simulated.
MOV AL,3 ; Display "^C"
invoke BUFOUT
invoke CRLF
PUSH SS
POP DS
ASSUME DS:DOSGROUP
CMP BYTE PTR [CONSWAP],0
JZ NOSWAP
invoke SWAPBACK
NOSWAP:
CLI ; Prepare to play with stack
MOV SP,[user_SP]
MOV SS,[user_SS] ; User stack now restored
ASSUME SS:NOTHING
invoke restore_world ; User registers now restored
ASSUME DS:NOTHING
MOV BYTE PTR [INDOS],0 ; Go to known state
MOV BYTE PTR [ERRORMODE],0
MOV [ConC_spsave],SP ; save his SP
INT int_ctrl_c ; Execute user Ctrl-C handler
MOV [user_SS],AX ; save the AX
PUSHF ; and the flags (maybe new call)
POP AX
CMP SP,[ConC_spsave]
JNZ ctrlc_try_new ; new syscall maybe?
ctrlc_repeat:
MOV AX,[user_SS] ; no...
transfer COMMAND ; Repeat command otherwise
ctrlc_try_new:
SUB [ConC_spsave],2 ; Are there flags on the stack?
CMP SP,[ConC_spsave]
JZ ctrlc_new ; yes, new system call
ctrlc_abort:
MOV AX,(EXIT SHL 8) + 0
MOV BYTE PTR [DidCTRLC],0FFh
transfer COMMAND ; give up by faking $EXIT
ctrlc_new:
PUSH AX
POPF
POP [user_SS]
JNC ctrlc_repeat ; repeat operation
JMP ctrlc_abort ; indicate ^ced
CNTCHAND ENDP
SUBTTL DIVISION OVERFLOW INTERRUPT
PAGE
; Default handler for division overflow trap
procedure DIVOV,NEAR
ASSUME DS:NOTHING,ES:NOTHING,SS:NOTHING
MOV SI,OFFSET DOSGROUP:DIVMES
CALL RealDivOv
JMP ctrlc_abort ; Use Ctrl-C abort on divide overflow
DIVOV ENDP
;
; RealDivOv: perform actual divide overflow stuff.
; Inputs: none
; Outputs: message to BCON
;
procedure RealDivOv,NEAR ; Do divide overflow and clock process
PUSH CS ; get ES addressability
POP ES
PUSH CS ; get DS addressability
POP DS
ASSUME DS:DOSGROUP
MOV BYTE PTR [DskStCom],DevWrt
MOV BYTE PTR [DskStCall],DRdWrHL
MOV [DskSTST],0
MOV BL,[DivMesLen]
XOR BH,BH
MOV [DskStCnt],BX
MOV BX,OFFSET DOSGROUP:DskStCall
MOV WORD PTR [DskChRet+1],SI ; transfer address (need an EQU)
LDS SI,[BCON]
ASSUME DS:NOTHING
invoke DEVIOCALL2
MOV WORD PTR [DskChRet+1],OFFSET DOSGROUP:DevIOBuf
MOV [DskStCnt],1
return
RealDivOv ENDP
SUBTTL CHARHRD,HARDERR,ERROR -- HANDLE DISK ERRORS AND RETURN TO USER
PAGE
procedure CHARHARD,NEAR
ASSUME DS:NOTHING,ES:NOTHING,SS:DOSGROUP
; Character device error handler
; Same function as HARDERR
MOV WORD PTR [EXITHOLD+2],ES
MOV WORD PTR [EXITHOLD],BP
PUSH SI
AND DI,STECODE
MOV BP,DS ;Device pointer is BP:SI
CALL FATALC
POP SI
return
CHARHARD ENDP
procedure HardErr,NEAR
ASSUME DS:NOTHING,ES:NOTHING
; Hard disk error handler. Entry conditions:
; DS:BX = Original disk transfer address
; DX = Original logical sector number
; CX = Number of sectors to go (first one gave the error)
; AX = Hardware error code
; DI = Original sector transfer count
; ES:BP = Base of drive parameters
; [READOP] = 0 for read, 1 for write
;
XCHG AX,DI ; Error code in DI, count in AX
AND DI,STECODE ; And off status bits
CMP DI,WRECODE ; Write Protect Error?
JNZ NOSETWRPERR
PUSH AX
MOV AL,ES:[BP.dpb_drive]
MOV BYTE PTR [WPERR],AL ; Flag drive with WP error
POP AX
NOSETWRPERR:
SUB AX,CX ; Number of sectors successfully transferred
ADD DX,AX ; First sector number to retry
PUSH DX
MUL ES:[BP.dpb_sector_size] ; Number of bytes transferred
POP DX
ADD BX,AX ; First address for retry
XOR AH,AH ; Flag disk section in error
CMP DX,ES:[BP.dpb_first_FAT] ; In reserved area?
JB ERRINT
INC AH ; Flag for FAT
CMP DX,ES:[BP.dpb_dir_sector] ; In FAT?
JB ERRINT
INC AH
CMP DX,ES:[BP.dpb_first_sector] ; In directory?
JB ERRINT
INC AH ; Must be in data area
ERRINT:
SHL AH,1 ; Make room for read/write bit
OR AH,BYTE PTR [READOP]
entry FATAL
MOV AL,ES:[BP.dpb_drive] ; Get drive number
entry FATAL1
MOV WORD PTR [EXITHOLD+2],ES
MOV WORD PTR [EXITHOLD],BP ; The only things we preserve
LES SI,ES:[BP.dpb_driver_addr]
MOV BP,ES ; BP:SI points to the device involved
FATALC:
CMP BYTE PTR [ERRORMODE],0
JNZ SETIGN ; No INT 24s if already INT 24
MOV [CONTSTK],SP
PUSH SS
POP ES
ASSUME ES:DOSGROUP
CLI ; Prepare to play with stack
INC BYTE PTR [ERRORMODE] ; Flag INT 24 in progress
DEC BYTE PTR [INDOS] ; INT 24 handler might not return
MOV SS,[user_SS]
ASSUME SS:NOTHING
MOV SP,ES:[user_SP] ; User stack pointer restored
INT int_fatal_abort ; Fatal error interrupt vector, must preserve ES
MOV ES:[user_SP],SP ; restore our stack
MOV ES:[user_SS],SS
MOV SP,ES
MOV SS,SP
ASSUME SS:DOSGROUP
MOV SP,[CONTSTK]
INC BYTE PTR [INDOS] ; Back in the DOS
MOV BYTE PTR [ERRORMODE],0 ; Back from INT 24
STI
IGNRET:
LES BP,[EXITHOLD]
ASSUME ES:NOTHING
CMP AL,2
JZ error_abort
MOV BYTE PTR [WPERR],-1 ;Forget about WP error
return
SETIGN:
XOR AL,AL ;Flag ignore
JMP SHORT IGNRET
error_abort:
PUSH SS
POP DS
ASSUME DS:DOSGROUP
CMP BYTE PTR [CONSWAP],0
JZ NOSWAP2
invoke SWAPBACK
NOSWAP2:
MOV BYTE PTR [exit_Type],Exit_hard_error
MOV DS,[CurrentPDB]
ASSUME DS:NOTHING
;
; reset_environment checks the DS value against the CurrentPDB. If they
; are different, then an old-style return is performed. If they are
; the same, then we release jfns and restore to parent. We still use
; the PDB at DS:0 as the source of the terminate addresses.
;
; output: none.
;
entry reset_environment
ASSUME DS:NOTHING,ES:NOTHING
PUSH DS ; save PDB of process
MOV AL,int_Terminate
invoke $Get_interrupt_vector ; and who to go to
MOV WORD PTR [EXITHOLD+2],ES ; save return address
MOV WORD PTR [EXITHOLD],BX
MOV BX,[CurrentPDB] ; get current process
MOV DS,BX ;
MOV AX,DS:[PDB_Parent_PID] ; get parent to return to
POP CX
;
; AX = parentPDB, BX = CurrentPDB, CX = ThisPDB
; Only free handles if AX <> BX and BX = CX and [exit_code].upper is not
; Exit_keep_process
;
CMP AX,BX
JZ reset_return ; parentPDB = CurrentPDB
CMP BX,CX
JNZ reset_return ; CurrentPDB <> ThisPDB
PUSH AX ; save parent
CMP BYTE PTR [exit_type],Exit_keep_process
JZ reset_to_parent ; keeping this process
invoke arena_free_process
; reset environment at [CurrentPDB]; close those handles
MOV CX,FilPerProc
reset_free_jfn:
MOV BX,CX
PUSH CX
DEC BX ; get jfn
invoke $CLOSE ; close it, ignore return
POP CX
LOOP reset_free_jfn ; and do 'em all
reset_to_parent:
POP [CurrentPDB] ; set up process as parent
reset_return: ; come here for normal return
PUSH CS
POP DS
ASSUME DS:DOSGROUP
MOV AL,-1
invoke FLUSHBUF ; make sure that everything is clean
CLI
MOV BYTE PTR [INDOS],0 ;Go to known state
MOV BYTE PTR [WPERR],-1 ;Forget about WP error
;
; Snake into multitasking... Get stack from CurrentPDB person
;
MOV DS,[CurrentPDB]
ASSUME DS:NOTHING
MOV SS,WORD PTR DS:[PDB_user_stack+2]
MOV SP,WORD PTR DS:[PDB_user_stack]
ASSUME SS:NOTHING
invoke restore_world
ASSUME ES:NOTHING
POP AX ; suck off CS:IP of interrupt...
POP AX
POP AX
MOV AX,0F202h ; STI
PUSH AX
PUSH WORD PTR [EXITHOLD+2]
PUSH WORD PTR [EXITHOLD]
STI
IRET ; Long return back to user terminate address
HardErr ENDP
ASSUME SS:DOSGROUP
do_ext
CODE ENDS
END
|
/**
* Copyright (c) 2017-present, Facebook, Inc.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <gtest/gtest.h>
#include "logdevice/common/settings/SettingsUpdater.h"
#include "logdevice/common/test/NodeSetTestUtil.h"
#include "logdevice/server/locallogstore/test/TemporaryLogStore.h"
#include "logdevice/server/rebuilding/RebuildingReadStorageTaskV2.h"
using namespace facebook::logdevice;
static const std::chrono::milliseconds MINUTE = std::chrono::minutes(1);
static const std::chrono::milliseconds PARTITION_DURATION = MINUTE * 15;
static const RecordTimestamp BASE_TIME{
TemporaryPartitionedStore::baseTime().toMilliseconds()};
static const std::string BIG_PAYLOAD(10000, '.');
static const ShardID N0{0, 0};
static const ShardID N1{1, 0};
static const ShardID N2{2, 0};
static const ShardID N3{3, 0};
static const ShardID N4{4, 0};
static const ShardID N5{5, 0};
static const ShardID N6{6, 0};
static const ShardID N7{7, 0};
static const ShardID N8{8, 0};
static const ShardID N9{9, 0};
// Ain't nobody got time to spell "compose_lsn(epoch_t(1), esn_t(1))".
lsn_t mklsn(epoch_t::raw_type epoch, esn_t::raw_type esn) {
return compose_lsn(epoch_t(epoch), esn_t(esn));
}
class RebuildingReadStorageTaskTest : public ::testing::Test {
public:
class MockRebuildingReadStorageTaskV2 : public RebuildingReadStorageTaskV2 {
public:
MockRebuildingReadStorageTaskV2(RebuildingReadStorageTaskTest* test,
std::weak_ptr<Context> context)
: RebuildingReadStorageTaskV2(context), test(test) {}
RebuildingReadStorageTaskTest* test;
protected:
UpdateableSettings<Settings> getSettings() override {
return test->settings;
}
std::shared_ptr<UpdateableConfig> getConfig() override {
return test->config;
}
folly::Optional<NodeID> getMyNodeID() override {
return folly::none;
}
std::unique_ptr<LocalLogStore::AllLogsIterator> createIterator(
const LocalLogStore::ReadOptions& opts,
const std::unordered_map<logid_t, std::pair<lsn_t, lsn_t>>& logs)
override {
return test->store->readAllLogs(opts, logs);
}
bool fetchTrimPoints(Context* context) override {
return true;
}
void updateTrimPoint(logid_t log,
Context* context,
Context::LogState* log_state) override {}
StatsHolder* getStats() override {
return &test->stats;
}
};
RebuildingReadStorageTaskTest() {
// Create nodes and logs config. This part is super boilerplaty, just skip
// the code and read comments.
configuration::Nodes nodes;
// Nodes 0..9.
NodeSetTestUtil::addNodes(&nodes, /* nodes */ 10, /* shards */ 2, "....");
auto logs_config = std::make_shared<configuration::LocalLogsConfig>();
logsconfig::LogAttributes log_attrs;
// Logs 1..10, replication factor 3.
log_attrs.set_backlogDuration(std::chrono::seconds(3600 * 24 * 1));
log_attrs.set_replicationFactor(3);
logs_config->insert(
boost::icl::right_open_interval<logid_t::raw_type>(1, 10),
"lg1",
log_attrs);
// Event log, replication factor 3.
log_attrs.set_backlogDuration(folly::none);
log_attrs.set_replicationFactor(3);
configuration::InternalLogs internal_logs;
ld_check(internal_logs.insert("event_log_deltas", log_attrs));
logs_config->setInternalLogsConfig(internal_logs);
logs_config->markAsFullyLoaded();
// Metadata logs, nodeset 5..9, replication factor 3.
configuration::MetaDataLogsConfig meta_logs_config;
meta_logs_config.metadata_nodes = {5, 6, 7, 8, 9};
meta_logs_config.setMetadataLogGroup(
logsconfig::LogGroupNode("metadata logs",
log_attrs,
logid_range_t(LOGID_INVALID, LOGID_INVALID)));
auto server_config = std::shared_ptr<ServerConfig>(
ServerConfig::fromDataTest("RebuildingReadStorageTaskTest",
configuration::NodesConfig(nodes),
meta_logs_config));
auto cfg = std::make_shared<Configuration>(server_config, logs_config);
config = std::make_shared<UpdateableConfig>(cfg);
config->updateableNodesConfiguration()->update(
config->getNodesConfigurationFromServerConfigSource());
// Create local log store (logsdb) and 6 partitions, 15 minutes apart.
store = std::make_unique<TemporaryPartitionedStore>();
for (size_t i = 0; i < 6; ++i) {
RecordTimestamp t = BASE_TIME + PARTITION_DURATION * i;
store->setTime(SystemTimestamp(t.toMilliseconds()));
store->createPartition();
partition_start.push_back(t);
}
}
void
setRebuildingSettings(std::unordered_map<std::string, std::string> settings) {
SettingsUpdater u;
u.registerSettings(rebuildingSettings);
u.setFromConfig(settings);
}
// The caller needs to assign `onDone` and `logs` afterwards.
std::shared_ptr<RebuildingReadStorageTaskV2::Context>
createContext(std::shared_ptr<const RebuildingSet> rebuilding_set,
ShardID my_shard_id = ShardID(1, 0)) {
auto c = std::make_shared<RebuildingReadStorageTaskV2::Context>();
c->rebuildingSet = rebuilding_set;
c->rebuildingSettings = rebuildingSettings;
c->myShardID = my_shard_id;
c->onDone = [&](std::vector<std::unique_ptr<ChunkData>> c) {
chunks = std::move(c);
};
return c;
}
UpdateableSettings<Settings> settings;
UpdateableSettings<RebuildingSettings> rebuildingSettings;
std::shared_ptr<UpdateableConfig> config;
StatsHolder stats{StatsParams().setIsServer(true)};
std::unique_ptr<TemporaryPartitionedStore> store;
std::vector<RecordTimestamp> partition_start;
std::vector<std::unique_ptr<ChunkData>> chunks;
};
struct ChunkDescription {
logid_t log;
lsn_t min_lsn;
size_t num_records = 1;
bool big_payload = false;
bool operator==(const ChunkDescription& rhs) const {
return std::tie(log, min_lsn, num_records, big_payload) ==
std::tie(rhs.log, rhs.min_lsn, rhs.num_records, rhs.big_payload);
}
};
static std::vector<ChunkDescription>
convertChunks(const std::vector<std::unique_ptr<ChunkData>>& chunks) {
std::vector<ChunkDescription> res;
for (auto& c : chunks) {
EXPECT_EQ(c->numRecords(), c->address.max_lsn - c->address.min_lsn + 1);
// Expect payload to be either BIG_PAYLOAD or log_id concatenated with lsn.
bool big = c->totalBytes() > BIG_PAYLOAD.size();
if (big) {
EXPECT_EQ(1, c->numRecords());
}
// Verify payloads.
for (size_t i = 0; i < c->numRecords(); ++i) {
EXPECT_EQ(c->address.min_lsn + i, c->getLSN(i));
Payload payload;
int rv = LocalLogStoreRecordFormat::parse(c->getRecordBlob(i),
nullptr,
nullptr,
nullptr,
nullptr,
nullptr,
nullptr,
0,
nullptr,
nullptr,
&payload,
shard_index_t(0));
EXPECT_EQ(0, rv);
std::string expected_payload;
if (big) {
expected_payload = BIG_PAYLOAD;
} else {
expected_payload =
toString(c->address.log.val()) + lsn_to_string(c->getLSN(i));
}
EXPECT_EQ(expected_payload, payload.toString());
}
res.push_back(ChunkDescription{c->address.log,
c->address.min_lsn,
c->address.max_lsn - c->address.min_lsn + 1,
big});
}
return res;
}
std::ostream& operator<<(std::ostream& out, const ChunkDescription& c) {
out << c.log.val() << lsn_to_string(c.min_lsn);
if (c.num_records != 1) {
out << ":" << c.num_records;
}
if (c.big_payload) {
out << ":big";
}
return out;
}
TEST_F(RebuildingReadStorageTaskTest, Basic) {
logid_t L1(1), L2(2), L3(3), L4(4);
logid_t M1 = MetaDataLog::metaDataLogID(L1);
logid_t I1 = configuration::InternalLogs::EVENT_LOG_DELTAS;
auto& P = partition_start;
ReplicationProperty R({{NodeLocationScope::NODE, 3}});
StorageSet all_nodes{N0, N1, N2, N3, N4, N5, N6, N7, N8, N9};
Slice big_payload = Slice::fromString(BIG_PAYLOAD);
// Read 10 KB per storage task.
setRebuildingSettings({{"rebuilding-max-batch-bytes", "10000"}});
// Rebuilding set is {N2}.
auto rebuilding_set = std::make_shared<RebuildingSet>();
rebuilding_set->shards.emplace(
ShardID(2, 0), RebuildingNodeInfo(RebuildingMode::RESTORE));
auto c = createContext(rebuilding_set);
// Fill out rebuilding plan.
// For internal and metadata log read all epochs.
c->logs[I1].plan.untilLSN = LSN_MAX;
c->logs[I1].plan.addEpochRange(
EPOCH_INVALID, EPOCH_MAX, std::make_shared<EpochMetaData>(all_nodes, R));
c->logs[M1].plan.untilLSN = LSN_MAX;
c->logs[M1].plan.addEpochRange(
EPOCH_INVALID, EPOCH_MAX, std::make_shared<EpochMetaData>(all_nodes, R));
// For log 1 read epochs 3-4 and 7-8, and stop at e8n50.
c->logs[L1].plan.untilLSN = mklsn(8, 50);
c->logs[L1].plan.addEpochRange(
epoch_t(3), epoch_t(4), std::make_shared<EpochMetaData>(all_nodes, R));
c->logs[L1].plan.addEpochRange(
epoch_t(7), epoch_t(8), std::make_shared<EpochMetaData>(all_nodes, R));
// For log 2 read all epochs and stop at e10n50.
c->logs[L2].plan.untilLSN = mklsn(10, 50);
c->logs[L2].plan.addEpochRange(
EPOCH_INVALID, EPOCH_MAX, std::make_shared<EpochMetaData>(all_nodes, R));
// Don't read log 3.
// For log 4 read only epoch 1.
c->logs[L4].plan.untilLSN = LSN_MAX;
c->logs[L4].plan.addEpochRange(
epoch_t(1), epoch_t(1), std::make_shared<EpochMetaData>(all_nodes, R));
// Write some records. Commment '-' means the record will be filtered out.
// Remember that we're N1, and rebuilding set is {N2}.
// Internal log.
store->putRecord(I1, mklsn(1, 10), BASE_TIME, {N1, N0, N2}); // +
// Metadata log.
store->putRecord(M1, mklsn(2, 1), BASE_TIME - MINUTE, {N2, N1, N0}); // +
store->putRecord(M1, mklsn(2, 2), BASE_TIME - MINUTE, {N2, N1, N0}); // +
store->putRecord(M1, mklsn(3, 1), BASE_TIME - MINUTE, {N1, N3, N4}); // -
store->putRecord(M1, mklsn(3, 2), BASE_TIME - MINUTE, {N1, N2, N3}); // +
// Data logs in partition 0.
store->putRecord(L1, mklsn(1, 10), P[0] + MINUTE, {N2, N1, N3}); // -
store->putRecord(L1, mklsn(2, 10), P[0] + MINUTE, {N2, N1, N3}); // -
store->putRecord(L1, mklsn(3, 10), P[0] + MINUTE, {N3, N1, N2}); // -
store->putRecord(L1, mklsn(3, 11), P[0] + MINUTE, {N1, N3, N2}); // +
store->putRecord(L1, mklsn(3, 12), P[0] + MINUTE * 2, {N1, N3, N2}); // +
store->putRecord(
L1, mklsn(4, 1), P[0] + MINUTE * 2, {N1, N3, N2}, 0, big_payload); // +
store->putRecord(L2, mklsn(1, 1), P[0] + MINUTE, {N3, N1, N2}); // -
store->putRecord(L3, mklsn(1, 1), P[0] + MINUTE, {N2, N1, N3}); // -
store->putRecord(
L4, mklsn(1, 1), P[0] + MINUTE, {N2, N1, N5}, 0, big_payload); // +
// Data logs in partition 1.
store->putRecord(L4,
mklsn(1, 2),
P[1] + MINUTE,
{N2, N1, N5},
LocalLogStoreRecordFormat::FLAG_DRAINED); // -
// Keep partition 2 empty.
// Data logs in partition 3.
store->putRecord(L1, mklsn(4, 2), P[3] + MINUTE, {N1, N3, N2}); // +
store->putRecord(L1, mklsn(5, 1), P[3] + MINUTE, {N1, N3, N2}); // -
store->putRecord(L1, mklsn(8, 50), P[3] + MINUTE, {N1, N3, N2}); // +
store->putRecord(L1, mklsn(8, 51), P[3] + MINUTE, {N1, N3, N2}); // -
store->putRecord(L2, mklsn(10, 40), P[3] + MINUTE * 2, {N1, N3, N2}); // +
store->putRecord(L2, mklsn(10, 60), P[3] + MINUTE * 2, {N1, N3, N2}); // -
store->putRecord(L3, mklsn(10, 10), P[3] + MINUTE, {N2, N1, N3}); // -
store->putRecord(L4, mklsn(1, 3), P[3] + MINUTE * 2, {N1, N3, N2}); // +
// Write lots of CSI entries that'll be filtered out. This should get iterator
// into LIMIT_REACHED state.
for (size_t i = 0; i < 2000; ++i) {
store->putRecord(L4, mklsn(1, i + 4), P[3] + MINUTE * 2, {N1, N3, N4}); // -
}
store->putRecord(L4, mklsn(1, 100000), P[3] + MINUTE * 2, {N1, N3, N2}); // +
store->putRecord(L4, mklsn(2, 1), P[3] + MINUTE * 2, {N1, N3, N2}); // -
// Sanity check that the records didn't end up in totally wrong partitions.
EXPECT_EQ(std::vector<size_t>({4, 1, 0, 4}), store->getNumLogsPerPartition());
{
// Read up to the big record that exceeds the byte limit.
MockRebuildingReadStorageTaskV2 task(this, c);
task.execute();
task.onDone();
EXPECT_FALSE(c->reachedEnd);
EXPECT_FALSE(c->persistentError);
EXPECT_EQ(std::vector<ChunkDescription>({{I1, mklsn(1, 10)},
{M1, mklsn(2, 1), 2},
{M1, mklsn(3, 2)},
{L1, mklsn(3, 11), 2}}),
convertChunks(chunks));
}
size_t block_id;
{
// Read up to the next big record. Note that the first big record doesn't
// count towards the limit for this batch because it was counted by the
// previous batch.
MockRebuildingReadStorageTaskV2 task(this, c);
task.execute();
task.onDone();
EXPECT_FALSE(c->reachedEnd);
EXPECT_FALSE(c->persistentError);
EXPECT_EQ(
std::vector<ChunkDescription>({{L1, mklsn(4, 1), 1, /* big */ true}}),
convertChunks(chunks));
block_id = chunks.at(0)->blockID;
}
{
MockRebuildingReadStorageTaskV2 task(this, c);
task.execute();
task.onDone();
EXPECT_FALSE(c->reachedEnd);
EXPECT_FALSE(c->persistentError);
EXPECT_EQ(
std::vector<ChunkDescription>({{L4, mklsn(1, 1), 1, /* big */ true},
{L1, mklsn(4, 2)},
{L1, mklsn(8, 50)},
{L2, mklsn(10, 40)},
{L4, mklsn(1, 3)}}),
convertChunks(chunks));
// Check that chunk e4n2 from this batch has the same block ID as chunk
// e4n1 from previous batch.
EXPECT_EQ(block_id, chunks.at(1)->blockID);
// Check that next chunk for same log has next block ID.
EXPECT_EQ(block_id + 1, chunks.at(2)->blockID);
}
// Read through a long sequence of CSI that doesn't pass filter.
int empty_batches = 0;
while (true) {
MockRebuildingReadStorageTaskV2 task(this, c);
task.execute();
task.onDone();
EXPECT_FALSE(c->persistentError);
if (c->reachedEnd) {
break;
}
EXPECT_EQ(0, chunks.size());
++empty_batches;
// Invalidate iterator after first batch.
if (empty_batches == 1) {
c->iterator->invalidate();
}
}
EXPECT_GE(empty_batches, 2);
EXPECT_EQ(std::vector<ChunkDescription>({{L4, mklsn(1, 100000)}}),
convertChunks(chunks));
// Run a task after Context is destroyed. Check that callback is not called.
{
chunks.clear();
chunks.push_back(std::make_unique<ChunkData>());
chunks.back()->address.min_lsn = 42;
MockRebuildingReadStorageTaskV2 task(this, c);
c.reset();
task.execute();
task.onDone();
ASSERT_EQ(1, chunks.size());
EXPECT_EQ(42, chunks.at(0)->address.min_lsn);
}
}
TEST_F(RebuildingReadStorageTaskTest, TimeRanges) {
// N1 is us.
// N2 needs to be rebuilt for partitions 0-2.
// N3 needs to be rebuilt for partitions 1 and 4.
// N4 needs to be rebuilt for partition 5.
// Log 1 epoch 3 has nodeset {N1, N2, N3, N5, N6}.
// Log 1 epoch 4 has nodeset {N1, N3, N5, N6}.
// Log 2 epoch 2 has nodeset {N1, N4, N5, N6}.
logid_t L1(1), L2(2);
auto& P = partition_start;
ReplicationProperty R({{NodeLocationScope::NODE, 3}});
// Fill out rebuilding set according to comment above.
auto rebuilding_set = std::make_shared<RebuildingSet>();
RecordTimeIntervals n2_dirty_ranges;
n2_dirty_ranges.insert(
RecordTimeInterval(P[0] + MINUTE * 2, P[3] - MINUTE * 2));
rebuilding_set->shards.emplace(
N2,
RebuildingNodeInfo(
{{DataClass::APPEND, n2_dirty_ranges}}, RebuildingMode::RESTORE));
RecordTimeIntervals n3_dirty_ranges;
n3_dirty_ranges.insert(
RecordTimeInterval(P[1] + MINUTE * 2, P[2] - MINUTE * 2));
n3_dirty_ranges.insert(
RecordTimeInterval(P[4] + MINUTE * 2, P[5] - MINUTE * 2));
rebuilding_set->shards.emplace(
N3,
RebuildingNodeInfo(
{{DataClass::APPEND, n3_dirty_ranges}}, RebuildingMode::RESTORE));
RecordTimeIntervals n4_dirty_ranges;
n4_dirty_ranges.insert(RecordTimeInterval(
P[5] + MINUTE * 2, P[5] + PARTITION_DURATION - MINUTE * 2));
rebuilding_set->shards.emplace(
N4,
RebuildingNodeInfo(
{{DataClass::APPEND, n4_dirty_ranges}}, RebuildingMode::RESTORE));
auto c = createContext(rebuilding_set);
// Fill out rebuilding plan according to comment above.
c->logs[L1].plan.untilLSN = LSN_MAX;
c->logs[L1].plan.addEpochRange(
epoch_t(3),
epoch_t(3),
std::make_shared<EpochMetaData>(StorageSet{N1, N2, N3, N5, N6}, R));
c->logs[L1].plan.addEpochRange(
epoch_t(4),
epoch_t(4),
std::make_shared<EpochMetaData>(StorageSet{N1, N3, N5, N6}, R));
c->logs[L2].plan.untilLSN = LSN_MAX;
c->logs[L2].plan.addEpochRange(
epoch_t(2),
epoch_t(2),
std::make_shared<EpochMetaData>(StorageSet{N1, N4, N5, N6}, R));
// Write some records, trying to hit as many different cases as possible.
// Partition 0.
store->putRecord(L1, mklsn(2, 1), P[0] + MINUTE * 3, {N1, N2, N3}); // -
store->putRecord(L1, mklsn(3, 1), P[0] + MINUTE * 1, {N1, N2, N3}); // -
store->putRecord(L1, mklsn(3, 2), P[0] + MINUTE * 3, {N1, N2, N3}); // +
store->putRecord(L1, mklsn(3, 3), P[0] + MINUTE * 3, {N1, N3, N5}); // -
store->putRecord(L1, mklsn(3, 4), P[0] + MINUTE * 3, {N1, N5, N6}); // -
store->putRecord(L1, mklsn(3, 5), P[0] + MINUTE * 3, {N1, N2, N6}); // +
store->putRecord(L1, mklsn(3, 6), P[1] - MINUTE * 1, {N1, N2, N6}); // +
store->putRecord(L2, mklsn(1, 1), P[0] + MINUTE * 3, {N1, N7, N8}); // -
store->putRecord(L2, mklsn(2, 1), P[0] + MINUTE * 3, {N1, N4, N5}); // -
// Partition 1.
store->putRecord(L1, mklsn(3, 7), P[1] + MINUTE * 1, {N1, N2, N5}); // +
store->putRecord(L1, mklsn(3, 8), P[1] + MINUTE * 1, {N1, N3, N5}); // -
store->putRecord(L1, mklsn(3, 9), P[1] + MINUTE * 3, {N1, N3, N5}); // +
store->putRecord(L1, mklsn(3, 10), P[1] + MINUTE * 3, {N1, N2, N3}); // +
store->putRecord(L1, mklsn(4, 1), P[1] + MINUTE * 4, {N1, N3, N5}); // +
// Partition 2.
store->putRecord(L1, mklsn(4, 2), P[2] + MINUTE * 4, {N1, N3, N5}); // -
store->putRecord(L1, mklsn(4, 3), P[2] + MINUTE * 4, {N1, N5, N6}); // -
// Partition 3.
store->putRecord(L1, mklsn(4, 4), P[3] + MINUTE * 4, {N1, N3, N4}); // -
store->putRecord(L2, mklsn(2, 2), P[3] + MINUTE * 4, {N1, N4, N5}); // -
// Partition 4.
store->putRecord(L1, mklsn(4, 5), P[4] + MINUTE * 4, {N1, N3, N5}); // +
store->putRecord(L1, mklsn(4, 6), P[4] + MINUTE * 4, {N1, N5, N6}); // -
store->putRecord(L1, mklsn(5, 1), P[4] + MINUTE * 4, {N1, N5, N6}); // -
store->putRecord(
L1, mklsn(2000000000, 1), P[4] + MINUTE * 4, {N1, N5, N6}); // -
// Partition 5.
store->putRecord(
L1, mklsn(2000000000, 2), P[5] + MINUTE * 4, {N1, N5, N6}); // -
store->putRecord(L2, mklsn(2, 3), P[5] + MINUTE * 4, {N1, N4, N5}); // +
EXPECT_EQ(
std::vector<size_t>({2, 1, 1, 2, 1, 2}), store->getNumLogsPerPartition());
{
MockRebuildingReadStorageTaskV2 task(this, c);
task.execute();
task.onDone();
EXPECT_TRUE(c->reachedEnd);
EXPECT_FALSE(c->persistentError);
EXPECT_EQ(std::vector<ChunkDescription>({{L1, mklsn(3, 2)},
{L1, mklsn(3, 5), 2},
{L1, mklsn(3, 7)},
{L1, mklsn(3, 9)},
{L1, mklsn(3, 10)},
{L1, mklsn(4, 1)},
{L1, mklsn(4, 5)},
{L2, mklsn(2, 3)}}),
convertChunks(chunks));
}
}
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r13
push %r9
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x11dca, %r13
nop
nop
nop
nop
nop
and %r11, %r11
mov $0x6162636465666768, %r9
movq %r9, (%r13)
dec %r10
lea addresses_A_ht+0x1cf53, %rsi
lea addresses_WT_ht+0x1c67e, %rdi
nop
nop
nop
nop
nop
dec %rax
mov $86, %rcx
rep movsb
nop
nop
nop
nop
nop
and %rdi, %rdi
lea addresses_WC_ht+0xd912, %rsi
lea addresses_WC_ht+0x9c52, %rdi
clflush (%rdi)
nop
nop
nop
dec %r10
mov $89, %rcx
rep movsl
nop
nop
xor $33461, %r9
lea addresses_normal_ht+0x15352, %rsi
lea addresses_WT_ht+0x3cd2, %rdi
nop
nop
sub %r9, %r9
mov $83, %rcx
rep movsb
nop
nop
nop
nop
add %rsi, %rsi
lea addresses_D_ht+0x111ca, %rdi
clflush (%rdi)
nop
nop
and $6988, %rcx
movl $0x61626364, (%rdi)
nop
add %r10, %r10
lea addresses_A_ht+0x764a, %r10
clflush (%r10)
nop
nop
nop
nop
nop
sub %r13, %r13
mov (%r10), %r11w
nop
nop
nop
inc %rdi
lea addresses_D_ht+0x15452, %rsi
lea addresses_WT_ht+0xd85a, %rdi
nop
nop
nop
dec %rax
mov $44, %rcx
rep movsl
nop
nop
nop
nop
and %rsi, %rsi
lea addresses_WT_ht+0x10552, %r9
nop
nop
nop
nop
sub %r11, %r11
movups (%r9), %xmm3
vpextrq $0, %xmm3, %r10
nop
nop
nop
nop
xor %rax, %rax
lea addresses_WT_ht+0x1ac16, %rsi
lea addresses_UC_ht+0xd9c6, %rdi
clflush (%rdi)
nop
sub %rax, %rax
mov $122, %rcx
rep movsw
cmp %r9, %r9
lea addresses_UC_ht+0x17e52, %r9
nop
nop
nop
nop
mfence
mov $0x6162636465666768, %rsi
movq %rsi, %xmm4
vmovups %ymm4, (%r9)
nop
nop
nop
nop
inc %r10
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r13
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r13
push %r14
push %rbp
push %rdi
push %rdx
// Store
mov $0x19cbe70000000352, %r11
nop
nop
sub %rdi, %rdi
mov $0x5152535455565758, %r13
movq %r13, %xmm3
movups %xmm3, (%r11)
nop
nop
nop
nop
cmp %r12, %r12
// Store
lea addresses_normal+0x15df2, %r14
add $41956, %r13
movl $0x51525354, (%r14)
and $28377, %rdx
// Store
lea addresses_WC+0x1af52, %r13
nop
sub $24644, %rbp
movb $0x51, (%r13)
nop
and %r11, %r11
// Faulty Load
lea addresses_WC+0x1af52, %r12
clflush (%r12)
nop
nop
nop
nop
and %r13, %r13
movups (%r12), %xmm3
vpextrq $1, %xmm3, %r11
lea oracles, %r14
and $0xff, %r11
shlq $12, %r11
mov (%r14,%r11,1), %r11
pop %rdx
pop %rdi
pop %rbp
pop %r14
pop %r13
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_NC', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 5, 'type': 'addresses_normal', 'AVXalign': False, 'size': 4}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': True, 'size': 1}}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 8}}
{'src': {'same': False, 'congruent': 0, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 2, 'type': 'addresses_WT_ht'}}
{'src': {'same': False, 'congruent': 6, 'type': 'addresses_WC_ht'}, 'OP': 'REPM', 'dst': {'same': True, 'congruent': 7, 'type': 'addresses_WC_ht'}}
{'src': {'same': False, 'congruent': 9, 'type': 'addresses_normal_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 7, 'type': 'addresses_WT_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4}}
{'src': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 2}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 6, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 3, 'type': 'addresses_WT_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 7, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 1, 'type': 'addresses_WT_ht'}, 'OP': 'REPM', 'dst': {'same': True, 'congruent': 2, 'type': 'addresses_UC_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 8, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 32}}
{'54': 1, '46': 136, '44': 1, '00': 21609, '35': 1, '48': 4, '42': 2, '45': 73, '49': 2}
00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 45 45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 45 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
;;
;; Copyright (c) 2012-2021, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the distribution.
;; * Neither the name of Intel Corporation nor the names of its contributors
;; may be used to endorse or promote products derived from this software
;; without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;
%include "include/os.asm"
%include "include/imb_job.asm"
%include "include/mb_mgr_datastruct.asm"
%include "include/cet.inc"
%include "include/reg_sizes.asm"
%include "include/memcpy.asm"
%include "include/const.inc"
%ifndef AES_XCBC_X8
%define AES_XCBC_X8 aes_xcbc_mac_128_x8
%define SUBMIT_JOB_AES_XCBC submit_job_aes_xcbc_avx
%endif
; void AES_XCBC_X8(AES_XCBC_ARGS_x16 *args, UINT64 len_in_bytes);
extern AES_XCBC_X8
section .data
default rel
align 16
dupw: ;ddq 0x01000100010001000100010001000100
dq 0x0100010001000100, 0x0100010001000100
x80: ;ddq 0x00000000000000000000000000000080
dq 0x0000000000000080, 0x0000000000000000
section .text
%ifdef LINUX
%define arg1 rdi
%define arg2 rsi
%else
%define arg1 rcx
%define arg2 rdx
%endif
%define state arg1
%define job arg2
%define len2 arg2
%define job_rax rax
%if 1
; idx needs to be in rbp
%define len r11
%define idx rbp
%define tmp2 rbp
%define tmp r14
%define lane r8
%define icv r9
%define p2 r9
%define last_len r10
%define lane_data r12
%define p r13
%define unused_lanes rbx
%endif
; STACK_SPACE needs to be an odd multiple of 8
; This routine and its callee clobbers all GPRs
struc STACK
_gpr_save: resq 8
_rsp_save: resq 1
endstruc
; JOB* SUBMIT_JOB_AES_XCBC(MB_MGR_AES_XCBC_OOO *state, IMB_JOB *job)
; arg 1 : state
; arg 2 : job
MKGLOBAL(SUBMIT_JOB_AES_XCBC,function,internal)
SUBMIT_JOB_AES_XCBC:
mov rax, rsp
sub rsp, STACK_size
and rsp, -16
mov [rsp + _gpr_save + 8*0], rbx
mov [rsp + _gpr_save + 8*1], rbp
mov [rsp + _gpr_save + 8*2], r12
mov [rsp + _gpr_save + 8*3], r13
mov [rsp + _gpr_save + 8*4], r14
mov [rsp + _gpr_save + 8*5], r15
%ifndef LINUX
mov [rsp + _gpr_save + 8*6], rsi
mov [rsp + _gpr_save + 8*7], rdi
%endif
mov [rsp + _rsp_save], rax ; original SP
mov unused_lanes, [state + _aes_xcbc_unused_lanes]
mov lane, unused_lanes
and lane, 0xF
shr unused_lanes, 4
imul lane_data, lane, _XCBC_LANE_DATA_size
lea lane_data, [state + _aes_xcbc_ldata + lane_data]
mov len, [job + _msg_len_to_hash_in_bytes]
mov [state + _aes_xcbc_unused_lanes], unused_lanes
mov [lane_data + _xcbc_job_in_lane], job
mov dword [lane_data + _xcbc_final_done], 0
mov tmp, [job + _k1_expanded]
mov [state + _aes_xcbc_args_keys + lane*8], tmp
mov p, [job + _src]
add p, [job + _hash_start_src_offset_in_bytes]
mov last_len, len
cmp len, 16
jle small_buffer
mov [state + _aes_xcbc_args_in + lane*8], p
add p, len ; set point to end of data
and last_len, 15 ; Check lsbs of msg len
jnz slow_copy ; if not 16B mult, do slow copy
fast_copy:
vmovdqu xmm0, [p - 16] ; load last block M[n]
mov tmp, [job + _k2] ; load K2 address
vmovdqu xmm1, [tmp] ; load K2
vpxor xmm0, xmm0, xmm1 ; M[n] XOR K2
vmovdqa [lane_data + _xcbc_final_block], xmm0
sub len, 16 ; take last block off length
end_fast_copy:
vpxor xmm0, xmm0, xmm0
shl lane, 4 ; multiply by 16
vmovdqa [state + _aes_xcbc_args_ICV + lane], xmm0
vmovdqa xmm0, [state + _aes_xcbc_lens]
XVPINSRW xmm0, xmm1, tmp, lane, len, no_scale
vmovdqa [state + _aes_xcbc_lens], xmm0
cmp unused_lanes, 0xf
jne return_null
start_loop:
; Find min length
vphminposuw xmm1, xmm0
vpextrw DWORD(len2), xmm1, 0 ; min value
vpextrw DWORD(idx), xmm1, 1 ; min index (0...7)
cmp len2, 0
je len_is_0
vpshufb xmm1, xmm1, [rel dupw] ; duplicate words across all lanes
vpsubw xmm0, xmm0, xmm1
vmovdqa [state + _aes_xcbc_lens], xmm0
; "state" and "args" are the same address, arg1
; len is arg2
call AES_XCBC_X8
; state and idx are intact
len_is_0:
; process completed job "idx"
imul lane_data, idx, _XCBC_LANE_DATA_size
lea lane_data, [state + _aes_xcbc_ldata + lane_data]
cmp dword [lane_data + _xcbc_final_done], 0
jne end_loop
mov dword [lane_data + _xcbc_final_done], 1
vmovdqa xmm0, [state + _aes_xcbc_lens]
XVPINSRW xmm0, xmm1, tmp, idx, 16, scale_x16
vmovdqa [state + _aes_xcbc_lens], xmm0
lea tmp, [lane_data + _xcbc_final_block]
mov [state + _aes_xcbc_args_in + 8*idx], tmp
jmp start_loop
end_loop:
; process completed job "idx"
mov job_rax, [lane_data + _xcbc_job_in_lane]
mov icv, [job_rax + _auth_tag_output]
mov unused_lanes, [state + _aes_xcbc_unused_lanes]
mov qword [lane_data + _xcbc_job_in_lane], 0
or dword [job_rax + _status], IMB_STATUS_COMPLETED_AUTH
shl unused_lanes, 4
or unused_lanes, idx
shl idx, 4 ; multiply by 16
mov [state + _aes_xcbc_unused_lanes], unused_lanes
; copy 12 bytes
vmovdqa xmm0, [state + _aes_xcbc_args_ICV + idx]
vmovq [icv], xmm0
vpextrd [icv + 8], xmm0, 2
%ifdef SAFE_DATA
;; Clear ICV
vpxor xmm0, xmm0
vmovdqa [state + _aes_xcbc_args_ICV + idx], xmm0
;; Clear final block (32 bytes)
vmovdqa [lane_data + _xcbc_final_block], xmm0
vmovdqa [lane_data + _xcbc_final_block + 16], xmm0
%endif
return:
mov rbx, [rsp + _gpr_save + 8*0]
mov rbp, [rsp + _gpr_save + 8*1]
mov r12, [rsp + _gpr_save + 8*2]
mov r13, [rsp + _gpr_save + 8*3]
mov r14, [rsp + _gpr_save + 8*4]
mov r15, [rsp + _gpr_save + 8*5]
%ifndef LINUX
mov rsi, [rsp + _gpr_save + 8*6]
mov rdi, [rsp + _gpr_save + 8*7]
%endif
mov rsp, [rsp + _rsp_save] ; original SP
ret
small_buffer:
; For buffers <= 16 Bytes
; The input data is set to final block
lea tmp, [lane_data + _xcbc_final_block] ; final block
mov [state + _aes_xcbc_args_in + lane*8], tmp
add p, len ; set point to end of data
cmp len, 16
je fast_copy
slow_copy:
and len, ~15 ; take final block off len
sub p, last_len ; adjust data pointer
lea p2, [lane_data + _xcbc_final_block + 16] ; upper part of final
sub p2, last_len ; adjust data pointer backwards
memcpy_avx_16_1 p2, p, last_len, tmp, tmp2
vmovdqa xmm0, [rel x80] ; fill reg with padding
vmovdqu [lane_data + _xcbc_final_block + 16], xmm0 ; add padding
vmovdqu xmm0, [p2] ; load final block to process
mov tmp, [job + _k3] ; load K3 address
vmovdqu xmm1, [tmp] ; load K3
vpxor xmm0, xmm0, xmm1 ; M[n] XOR K3
vmovdqu [lane_data + _xcbc_final_block], xmm0 ; write final block
jmp end_fast_copy
return_null:
xor job_rax, job_rax
jmp return
%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
|
// This file is licensed under the Elastic License 2.0. Copyright 2021 StarRocks Limited.
#include "aggregate_streaming_sink_operator.h"
#include "simd/simd.h"
namespace starrocks::pipeline {
Status AggregateStreamingSinkOperator::prepare(RuntimeState* state) {
RETURN_IF_ERROR(Operator::prepare(state));
RETURN_IF_ERROR(_aggregator->prepare(state, state->obj_pool(), get_runtime_profile(), _mem_tracker.get()));
return _aggregator->open(state);
}
Status AggregateStreamingSinkOperator::close(RuntimeState* state) {
RETURN_IF_ERROR(_aggregator->unref(state));
return Operator::close(state);
}
void AggregateStreamingSinkOperator::set_finishing(RuntimeState* state) {
_is_finished = true;
if (_aggregator->hash_map_variant().size() == 0) {
_aggregator->set_ht_eos();
}
_aggregator->sink_complete();
}
StatusOr<vectorized::ChunkPtr> AggregateStreamingSinkOperator::pull_chunk(RuntimeState* state) {
return Status::InternalError("Not support");
}
Status AggregateStreamingSinkOperator::push_chunk(RuntimeState* state, const vectorized::ChunkPtr& chunk) {
size_t chunk_size = chunk->num_rows();
_aggregator->update_num_input_rows(chunk_size);
COUNTER_SET(_aggregator->input_row_count(), _aggregator->num_input_rows());
_aggregator->evaluate_exprs(chunk.get());
if (_aggregator->streaming_preaggregation_mode() == TStreamingPreaggregationMode::FORCE_STREAMING) {
return _push_chunk_by_force_streaming();
} else if (_aggregator->streaming_preaggregation_mode() == TStreamingPreaggregationMode::FORCE_PREAGGREGATION) {
return _push_chunk_by_force_preaggregation(chunk->num_rows());
} else {
return _push_chunk_by_auto(chunk->num_rows());
}
}
Status AggregateStreamingSinkOperator::_push_chunk_by_force_streaming() {
SCOPED_TIMER(_aggregator->streaming_timer());
vectorized::ChunkPtr chunk = std::make_shared<vectorized::Chunk>();
_aggregator->output_chunk_by_streaming(&chunk);
_aggregator->offer_chunk_to_buffer(chunk);
return Status::OK();
}
Status AggregateStreamingSinkOperator::_push_chunk_by_force_preaggregation(const size_t chunk_size) {
SCOPED_TIMER(_aggregator->agg_compute_timer());
if (false) {
}
#define HASH_MAP_METHOD(NAME) \
else if (_aggregator->hash_map_variant().type == vectorized::HashMapVariant::Type::NAME) \
_aggregator->build_hash_map<decltype(_aggregator->hash_map_variant().NAME)::element_type>( \
*_aggregator->hash_map_variant().NAME, chunk_size);
APPLY_FOR_VARIANT_ALL(HASH_MAP_METHOD)
#undef HASH_MAP_METHOD
else {
DCHECK(false);
}
if (_aggregator->is_none_group_by_exprs()) {
_aggregator->compute_single_agg_state(chunk_size);
} else {
_aggregator->compute_batch_agg_states(chunk_size);
}
_mem_tracker->set(_aggregator->hash_map_variant().memory_usage() + _aggregator->mem_pool()->total_reserved_bytes());
_aggregator->try_convert_to_two_level_map();
COUNTER_SET(_aggregator->hash_table_size(), (int64_t)_aggregator->hash_map_variant().size());
return Status::OK();
}
Status AggregateStreamingSinkOperator::_push_chunk_by_auto(const size_t chunk_size) {
// TODO: calc the real capacity of hashtable, will add one interface in the class of habletable
size_t real_capacity = _aggregator->hash_map_variant().capacity() - _aggregator->hash_map_variant().capacity() / 8;
size_t remain_size = real_capacity - _aggregator->hash_map_variant().size();
bool ht_needs_expansion = remain_size < chunk_size;
if (!ht_needs_expansion ||
_aggregator->should_expand_preagg_hash_tables(_aggregator->num_input_rows(), chunk_size,
_aggregator->mem_pool()->total_allocated_bytes(),
_aggregator->hash_map_variant().size())) {
// hash table is not full or allow expand the hash table according reduction rate
SCOPED_TIMER(_aggregator->agg_compute_timer());
if (false) {
}
#define HASH_MAP_METHOD(NAME) \
else if (_aggregator->hash_map_variant().type == vectorized::HashMapVariant::Type::NAME) \
_aggregator->build_hash_map<decltype(_aggregator->hash_map_variant().NAME)::element_type>( \
*_aggregator->hash_map_variant().NAME, chunk_size);
APPLY_FOR_VARIANT_ALL(HASH_MAP_METHOD)
#undef HASH_MAP_METHOD
else {
DCHECK(false);
}
if (_aggregator->is_none_group_by_exprs()) {
_aggregator->compute_single_agg_state(chunk_size);
} else {
_aggregator->compute_batch_agg_states(chunk_size);
}
_mem_tracker->set(_aggregator->hash_map_variant().memory_usage() +
_aggregator->mem_pool()->total_reserved_bytes());
_aggregator->try_convert_to_two_level_map();
COUNTER_SET(_aggregator->hash_table_size(), (int64_t)_aggregator->hash_map_variant().size());
} else {
{
SCOPED_TIMER(_aggregator->agg_compute_timer());
if (false) {
}
#define HASH_MAP_METHOD(NAME) \
else if (_aggregator->hash_map_variant().type == vectorized::HashMapVariant::Type::NAME) _aggregator \
->build_hash_map_with_selection<typename decltype(_aggregator->hash_map_variant().NAME)::element_type>( \
*_aggregator->hash_map_variant().NAME, chunk_size);
APPLY_FOR_VARIANT_ALL(HASH_MAP_METHOD)
#undef HASH_MAP_METHOD
else {
DCHECK(false);
}
}
size_t zero_count = SIMD::count_zero(_aggregator->streaming_selection());
// very poor aggregation
if (zero_count == 0) {
SCOPED_TIMER(_aggregator->streaming_timer());
vectorized::ChunkPtr chunk = std::make_shared<vectorized::Chunk>();
_aggregator->output_chunk_by_streaming(&chunk);
_aggregator->offer_chunk_to_buffer(chunk);
}
// very high aggregation
else if (zero_count == _aggregator->streaming_selection().size()) {
SCOPED_TIMER(_aggregator->agg_compute_timer());
_aggregator->compute_batch_agg_states(chunk_size);
} else {
// middle cases, first aggregate locally and output by stream
{
SCOPED_TIMER(_aggregator->agg_compute_timer());
_aggregator->compute_batch_agg_states_with_selection(chunk_size);
}
{
SCOPED_TIMER(_aggregator->streaming_timer());
vectorized::ChunkPtr chunk = std::make_shared<vectorized::Chunk>();
_aggregator->output_chunk_by_streaming_with_selection(&chunk);
_aggregator->offer_chunk_to_buffer(chunk);
}
}
COUNTER_SET(_aggregator->hash_table_size(), (int64_t)_aggregator->hash_map_variant().size());
}
return Status::OK();
}
} // namespace starrocks::pipeline
|
.nolist ; We don't want to actually include defs in our listing file.
.include "m168def.inc" ; m168def.inc defines all the pins on the Mega168 so we can
; use them by their names rather than addresses (not fun).
.list ; We DO want to include the following code in our listing ;D
rjmp main ; You usually place these two lines after all your
main: ; directives. They make sure that resets work correctly.
ldi r16,0xFF ; LoaD Immediate. This sets r16 = 0xFF (255)
out DDRB,r16 ; Out writes to SRAM, which is one way of accessing
; pins. DDRB controls PORTB's in/out state.
ldi r16,0x00 ; r16 is where we'll store current LED state
; 0x00 means all off. This is preserved over loops.
loop: ; This is a label (like main above) where we can come back to
com r16 ; Flip all the bits in r16 (one's complement)
; So, originally, we go from 0x00 (off) to 0xFF (on)
out PORTB,r16 ; set all B pins to current state. PORTB is where our favorite flashing pin is (pin 13)!
; Waiting for a specified time:
; Ok, so we want to wait one second between each LED flip.
; Our Arduino should be clocked at 16Mhz, so that means we have to wait
; 16 million cycles between flips. Different instructions take different
; amounts of clock cycles to complete, so we have to count the cycles
; to get an accurate wait time. We're going to use a combination of a
; word and a byte to get the number of cycles right, since just a single
; byte or word can't hold near enough to wait for our needed time.
; Counting cycles:
; Below you'll see a couple instructions with numbers in their comments.
; The numbers represent how many clock cycles the instruction takes.
; You can find all of these cycle amounts in the atmega168 datasheet.
; 1/2 means it can take either one or two cycles depending on the flag
; state. For these branch instructions (BRNE), they take one cycle if
; the condition is false, and two cycles if it's true. We'll only care
; about the two cycle case, since that will be happening 99% of the time.
; Also, just for extra laziness we wont care about the outside loop's cycles.
; The inner is the really time critical one anyway ;D
; The math:
; The Arduino is clocked at 16Mhz, or 16000000 cycles per second.
; Our main loop takes 4 cycles to complete one loop, since SBIW
; takes 2 cycles and BRNE will (usually) take 2 cycles. This means
; that we need to find an X < 256 and Y < 65536 so that X*Y*4 = 16000000.
; X=100 and Y=40000 fit that bill quite nicely, so we'll go with those.
; The outer loop runs 100 times, and the inner runs 40000 times per outer
; loop. This gives us about 1 second per flip!
ldi r17,100 ; r17 is our outer loop counter
outer:
; ZH and ZL are a word pseudo-register. It's actually a combination
; of r31 and r30, giving us 16 bits to use for SBIW. Handy!
; The HIGH and LOW macros just give us the high and low bits of a
; number.
ldi ZH,HIGH(40000) ; 1
ldi ZL,LOW(40000) ; 1
inner:
; These next two instructions SuBtract Immediate from Word and
; BRanch if Not Equal. Basically, we subtract one from the Z psuedo
; register (which begins with ZL, the low bits), and then, if we haven't
; reached 0, go back to the inner label. Otherwise we keep on going with
; the check for the outer loop!
sbiw ZL,1 ;2 \_ Main Loop (4 cycles)
brne inner ;1/2 /
; The following instructions DECrement and BRanch if Not Equal. BRNE
; works exactly the same as above. DEC is shorthand for subtract one
; from this register. Only takes one clock cycle, too!
dec r17 ;1
brne outer ;1/2
; Finally we've reached the end of the loop. Relative JuMP just brings
; us back to the label listed. Back to loop we go!
rjmp loop
|
; A059144: A hierarchical sequence (W3{2,2}*cc - see A059126).
; 15,24,15,33,15,24,15,42,15,24,15,33,15,24,15,51,15,24,15,33,15,24,15,42,15,24,15,33,15,24,15,60,15,24,15,33,15,24,15,42,15,24,15,33,15,24,15,51,15,24,15,33,15,24,15,42,15,24,15,33,15,24,15,69,15,24,15,33,15
add $0,1
lpb $0
dif $0,2
add $1,1
lpe
mul $1,9
add $1,15
mov $0,$1
|
; fasm example of using the C library in Linux
; compile the source with commands like:
; fasm libcdemo.asm libcdemo.o
; gcc libcdemo.o -o libcdemo
; strip libcdemo
format ELF
include 'cdecl.inc'
section '.text' executable
public main
extrn printf
extrn getpid
main:
call getpid
ccall printf, msg,eax
ret
section '.data' writeable
msg db "Current process ID is %d.",0xA,0
|
db HITMONCHAN ; 107
db 50, 105, 79, 76, 35, 110
; hp atk def spd sat sdf
db FIGHTING, FIGHTING ; type
db 45 ; catch rate
db 140 ; base exp
db NO_ITEM, NO_ITEM ; items
db GENDER_F0 ; gender ratio
db 100 ; unknown 1
db 25 ; step cycles to hatch
db 5 ; unknown 2
INCBIN "gfx/pokemon/hitmonchan/front.dimensions"
db 0, 0, 0, 0 ; padding
db GROWTH_MEDIUM_FAST ; growth rate
dn EGG_HUMANSHAPE, EGG_HUMANSHAPE ; egg groups
; tm/hm learnset
tmhm DYNAMICPUNCH, HEADBUTT, CURSE, TOXIC, ROCK_SMASH, HIDDEN_POWER, SUNNY_DAY, SNORE, PROTECT, ENDURE, FRUSTRATION, RETURN, MUD_SLAP, DOUBLE_TEAM, ICE_PUNCH, SWAGGER, SLEEP_TALK, SWIFT, THUNDERPUNCH, DETECT, REST, ATTRACT, THIEF, FIRE_PUNCH, STRENGTH
; end
|
; Listing generated by Microsoft (R) Optimizing Compiler Version 19.00.23506.0
TITLE D:\Projects\TaintAnalysis\AntiTaint\Epilog\src\func-rets.c
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB MSVCRT
INCLUDELIB OLDNAMES
PUBLIC ___local_stdio_printf_options
PUBLIC __vfprintf_l
PUBLIC _printf
PUBLIC _func
PUBLIC _main
EXTRN __imp____acrt_iob_func:PROC
EXTRN __imp____stdio_common_vfprintf:PROC
EXTRN _gets:PROC
_DATA SEGMENT
COMM ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9:QWORD ; `__local_stdio_printf_options'::`2'::_OptionsStorage
_DATA ENDS
; Function compile flags: /Ogtp
; File d:\projects\taintanalysis\antitaint\epilog\src\func-rets.c
; COMDAT _main
_TEXT SEGMENT
$T1 = -80 ; size = 20
$T2 = -80 ; size = 20
_b$ = -80 ; size = 20
_a$2$ = -48 ; size = 16
_b$2$ = -32 ; size = 16
$T3 = -32 ; size = 20
_main PROC ; COMDAT
; 25 : {
push ebx
mov ebx, esp
sub esp, 8
and esp, -16 ; fffffff0H
add esp, 4
push ebp
mov ebp, DWORD PTR [ebx+4]
mov DWORD PTR [esp+4], ebp
mov ebp, esp
sub esp, 80 ; 00000050H
; 26 : struct S a,b,c;
; 27 : int z = 0;
; 28 : a = func();
lea eax, DWORD PTR $T3[ebp]
push eax
call _func
movups xmm0, XMMWORD PTR [eax]
; 29 : z += a.a;
; 30 : b = func();
lea eax, DWORD PTR $T2[ebp]
push eax
movaps XMMWORD PTR _a$2$[ebp], xmm0
call _func
movups xmm0, XMMWORD PTR [eax]
mov eax, DWORD PTR [eax+16]
mov DWORD PTR _b$[ebp+16], eax
; 31 : c = func();
lea eax, DWORD PTR $T1[ebp]
push eax
movaps XMMWORD PTR _b$2$[ebp], xmm0
call _func
; 32 : z += c.c + b.b;
movaps xmm1, XMMWORD PTR _b$2$[ebp]
add esp, 12 ; 0000000cH
psrldq xmm1, 4
movd ecx, xmm1
movups xmm0, XMMWORD PTR [eax]
psrldq xmm0, 8
movd eax, xmm0
movaps xmm0, XMMWORD PTR _a$2$[ebp]
add eax, ecx
movd ecx, xmm0
add eax, ecx
; 33 : return z;
; 34 : }
mov esp, ebp
pop ebp
mov esp, ebx
pop ebx
ret 0
_main ENDP
_TEXT ENDS
; Function compile flags: /Ogtp
; File d:\projects\taintanalysis\antitaint\epilog\src\func-rets.c
; COMDAT _func
_TEXT SEGMENT
_buf$ = -8 ; size = 8
$T1 = 8 ; size = 4
_func PROC ; COMDAT
; 15 : {
push ebp
mov ebp, esp
sub esp, 8
; 16 : char buf[8];
; 17 : struct S s;
; 18 : s.a = (int)gets(buf) - (int)buf;
lea eax, DWORD PTR _buf$[ebp]
push esi
push eax
call _gets
mov esi, DWORD PTR $T1[ebp]
lea ecx, DWORD PTR _buf$[ebp]
sub eax, ecx
mov DWORD PTR [esi], eax
; 19 : s.b = printf(buf);
mov eax, ecx
push eax
call _printf
; 20 : s.c = s.a + s.b;
mov ecx, DWORD PTR [esi]
add esp, 8
add ecx, eax
mov DWORD PTR [esi+4], eax
mov DWORD PTR [esi+8], ecx
; 21 : return s;
mov eax, esi
pop esi
; 22 : }
mov esp, ebp
pop ebp
ret 0
_func ENDP
_TEXT ENDS
; Function compile flags: /Ogtp
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT _printf
_TEXT SEGMENT
__Format$ = 8 ; size = 4
_printf PROC ; COMDAT
; 950 : {
push ebp
mov ebp, esp
; 951 : int _Result;
; 952 : va_list _ArgList;
; 953 : __crt_va_start(_ArgList, _Format);
; 954 : _Result = _vfprintf_l(stdout, _Format, NULL, _ArgList);
lea eax, DWORD PTR __Format$[ebp+4]
push eax
push 0
push DWORD PTR __Format$[ebp]
push 1
call DWORD PTR __imp____acrt_iob_func
add esp, 4
push eax
call __vfprintf_l
add esp, 16 ; 00000010H
; 955 : __crt_va_end(_ArgList);
; 956 : return _Result;
; 957 : }
pop ebp
ret 0
_printf ENDP
_TEXT ENDS
; Function compile flags: /Ogtp
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT __vfprintf_l
_TEXT SEGMENT
__Stream$ = 8 ; size = 4
__Format$ = 12 ; size = 4
__Locale$ = 16 ; size = 4
__ArgList$ = 20 ; size = 4
__vfprintf_l PROC ; COMDAT
; 638 : {
push ebp
mov ebp, esp
; 639 : return __stdio_common_vfprintf(_CRT_INTERNAL_LOCAL_PRINTF_OPTIONS, _Stream, _Format, _Locale, _ArgList);
push DWORD PTR __ArgList$[ebp]
push DWORD PTR __Locale$[ebp]
push DWORD PTR __Format$[ebp]
push DWORD PTR __Stream$[ebp]
call ___local_stdio_printf_options
push DWORD PTR [eax+4]
push DWORD PTR [eax]
call DWORD PTR __imp____stdio_common_vfprintf
add esp, 24 ; 00000018H
; 640 : }
pop ebp
ret 0
__vfprintf_l ENDP
_TEXT ENDS
; Function compile flags: /Ogtp
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\corecrt_stdio_config.h
; COMDAT ___local_stdio_printf_options
_TEXT SEGMENT
___local_stdio_printf_options PROC ; COMDAT
; 74 : static unsigned __int64 _OptionsStorage;
; 75 : return &_OptionsStorage;
mov eax, OFFSET ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9 ; `__local_stdio_printf_options'::`2'::_OptionsStorage
; 76 : }
ret 0
___local_stdio_printf_options ENDP
_TEXT ENDS
END
|
//*********************************************************************
//17/04/2019 1.0.0 Rémi Saint-Amant Creation
//*********************************************************************
#include "BudBurst.h"
#include "Basic/WeatherDefine.h"
#include "ModelBase/EntryPoint.h"
using namespace std;
using namespace WBSF::HOURLY_DATA;
namespace WBSF
{
//this line link this model with the EntryPoint of the DLL
static const bool bRegistred =
CModelFactory::RegisterModel(CBudBurst::CreateObject);
CBudBurst::CBudBurst()
{
// initialize your variable here (optional)
NB_INPUT_PARAMETER = 1;
VERSION = "1.0.0 (2019)";
}
CBudBurst::~CBudBurst()
{
}
//This method is call to compute solution
ERMsg CBudBurst::OnExecuteAnnual()
{
ERMsg msg;
CTPeriod pp(m_weather.GetEntireTPeriod(CTM::ANNUAL));
pp.Begin().m_year++;
m_output.Init(pp, 3);
static const double Sw150 = 16.891;
static const double α2 = -0.0675;
for (size_t y = 0; y < m_weather.GetNbYears()-1; y++)
{
CTRef budBurst;
double sum = 0;
int dc = 0;
int year = m_weather[y].GetTRef().GetYear();
CTPeriod p(CTRef(year, DECEMBER, DAY_01), CTRef(year+1, DECEMBER, DAY_01));
for (CTRef TRef = p.Begin(); TRef < p.End()&& !budBurst.IsInit(); TRef++)
{
const CWeatherDay& wDay = m_weather.GetDay(TRef);
if (wDay[H_TAIR][MEAN] < 10)
dc++;
else
sum+= wDay[H_TAIR][MEAN] - 10;
double Sw = Sw150 * exp(α2*(dc - 150.0));
if(sum >= Sw)
{
budBurst = TRef;
}
}
if (budBurst.IsInit())
{
m_output[y][0] = dc;
m_output[y][1] = Sw150 * exp(α2*(dc - 150.0));
m_output[y][2] = budBurst.GetRef();
}
}
return msg;
}
//this method is call to load your parameter in your variable
ERMsg CBudBurst::ProcessParameters(const CParameterVector& parameters)
{
ERMsg msg;
//transfer your parameter here
short c=0;
m_species = parameters[c++].GetInt();
return msg;
}
} |
lc r4, 0x7fffffff
lc r5, 0x00000000
gts r6, r4, r5
halt
#@expected values
#r4 = 0x7fffffff
#r5 = 0x00000000
#r6 = 0x00000001
#pc = -2147483628
#e0 = 0
#e1 = 0
#e2 = 0
#e3 = 0
|
; A310373: Coordination sequence Gal.6.150.5 where G.u.t.v denotes the coordination sequence for a vertex of type v in tiling number t in the Galebach list of u-uniform tilings.
; Submitted by Christian Krause
; 1,4,10,14,18,23,27,31,36,40,44,50,54,58,64,68,72,77,81,85,90,94,98,104,108,112,118,122,126,131,135,139,144,148,152,158,162,166,172,176,180,185,189,193,198,202,206,212,216,220
mov $1,$0
seq $0,312890 ; Coordination sequence Gal.6.115.5 where G.u.t.v denotes the coordination sequence for a vertex of type v in tiling number t in the Galebach list of u-uniform tilings.
add $1,1
div $1,3
add $0,$1
|
; A024072: a(n) = 6^n - n^10.
; 1,5,-988,-58833,-1047280,-9757849,-60419520,-282195313,-1072062208,-3476706705,-9939533824,-25574627545,-59740581888,-124797797833,-210890490880,-106465406049,1721598279680,14910665544287,97989489441792,603228673752695,3645918440062976,21920270759399655,131595143919475712,789688796542389167,4738317934940651520,28430192662498060751,170581587012482554880,1023490163186337154887,6140941918268048801792,36845652866081659683095,221073919130243357899776,1326443517504771860417855,7958661108820500977549312,47751966658146826321087167,286511799956006054084049920,1719070799745664043675142551,10314424798486879387731886080,61886548790938404692659276487,371319292745653001450342177792,2227915756473947537567055804495,13367494538843723582078845976576,80204967233062390984373765707055,481229803398374409362000333478912,2887378820390246537041708417656167,17324272922341479324721783447224320,103945637534048876077464237397839351,623673825204293256626668450400353280
mov $1,6
pow $1,$0
pow $0,10
sub $1,$0
mov $0,$1
|
; A094806: Number of (s(0), s(1), ..., s(2n)) such that 0 < s(i) < 8 and |s(i) - s(i-1)| = 1 for i = 1,2,...,2n, s(0) = 1, s(2n) = 5.
; 1,5,20,74,264,924,3200,11016,37792,129392,442496,1512224,5165952,17643456,60250112,205729920,702452224,2398414592,8188884992,27958972928,95458646016,325917686784,1112755552256,3799191029760,12971261403136,44286680330240,151204232069120,516243634724864,1762566208978944,6017777834901504,20545979458519040,70148363238014976,239501496182505472,817709262548959232,2791834066420760576,9531917757764993024,32544002932578189312,111112176283502247936,379360699406291566592,1295218445333039677440,4422152383069331390464,15098172642710757834752,51548385806903391813632,175997197946590098096128,600892020181349701779456,2051573684849810796969984,7004510699071728156409856,23914895426657659775877120,81650560308627920279044096,278772450381477836541132800,951788680909218455559864320,3249609822875044049064034304,11094861929683991084950093824,37880228072990379841299677184,129331188432602544394553262080,441564297584447432294123175936,1507594813472620669184405143552,5147250658721659869743412150272,17573813007941542255792914169856,60000750714323137514060984090624,204855376841410042005410411446272,699420005936995045915024284450816,2387969270065162405492285528604672,8153037068386664141825111972904960,27836209733416340979687913689186304,95038764796892054081845504520486912,324482639720735571261494338122678272
lpb $0
mov $2,$0
sub $0,1
seq $2,94821 ; Number of (s(0), s(1), ..., s(2n)) such that 0 < s(i) < 8 and |s(i) - s(i-1)| = 1 for i = 1,2,....,2n, s(0) = 3, s(2n) = 5.
add $1,$2
lpe
add $1,1
mov $0,$1
|
; A067897: a(n) = A000085(n) - (1 + Sum_{j=1..n-1} A000085(j)).
; Submitted by Jamie Morken(s1)
; 0,0,0,0,2,8,32,112,412,1504,5760,22464,91224,379424,1632896,7201472,32709136,152094976,725810176,3540883968,17680145184,90115509888,469094763008,2489169367808,13465672180160,74161734785536
mov $3,1
lpb $0
sub $0,1
sub $1,1
mov $2,$3
mul $2,$0
add $3,$1
mov $1,$2
sub $2,1
lpe
sub $3,$2
mov $0,$3
sub $0,1
|
;este es un comentario
list p=18f4550 ;modelo de procesador
#include<p18f4550.inc> ;libreria de nombre de registros
;Bits de configuracion del microcontrolador
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT oscillator (XT))
CONFIG PWRT = ON ; Power-up Timer Enable bit (PWRT enabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
org 0x0000
goto init_conf
org 0x0020
init_conf: clrf TRISD ;RD como salida
clrf TRISB ;RB como salida
inicio: movlw 0x5A ;cargamos a W 0x5A
movwf LATD ;movemos contenido de Wreg a RD
movlw 0xA5 ;cargamos a W 0xA5
movwf LATB ;movemos contenido de Wreg a RB
end ;fin del programa |
//////////////////////////////////////////////////////////////////////////////
//
// (C) Copyright Ion Gaztanaga 2004-2012. Distributed under the Boost
// Software License, Version 1.0. (See accompanying file
// LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
//
// See http://www.boost.org/libs/interprocess for documentation.
//
//////////////////////////////////////////////////////////////////////////////
#include <boost/config.hpp>
#ifdef BOOST_WINDOWS
//Force user-defined get_shared_dir
#define BOOST_INTERPROCESS_SHARED_DIR_FUNC
#include <boost/interprocess/detail/shared_dir_helpers.hpp>
#include <string>
#include "get_process_id_name.hpp"
namespace boost {
namespace interprocess {
namespace ipcdetail {
static bool dir_created = false;
inline void get_shared_dir(std::string &shared_dir)
{
shared_dir = boost::interprocess::ipcdetail::get_temporary_path();
shared_dir += "/boostipctest_";
shared_dir += boost::interprocess::test::get_process_id_name();
if(!dir_created)
ipcdetail::create_directory(shared_dir.c_str());
dir_created = true;
}
}}} //namespace boost::interprocess::ipcdetail
#include <boost/interprocess/shared_memory_object.hpp>
#include <iostream>
int main ()
{
using namespace boost::interprocess;
const char *const shm_name = "test_shm";
std::string shared_dir;
ipcdetail::get_shared_dir(shared_dir);
std::string shm_path(shared_dir);
shm_path += "/";
shm_path += shm_name;
int ret = 0;
shared_memory_object::remove(shm_name);
{
{
shared_memory_object shm(create_only, shm_name, read_write);
}
ret = ipcdetail::invalid_file() == ipcdetail::open_existing_file(shm_path.c_str(), read_only) ?
1 : 0;
if(ret)
{
std::cerr << "Error opening user get_shared_dir()/shm file" << std::endl;
}
}
shared_memory_object::remove(shm_name);
ipcdetail::remove_directory(shared_dir.c_str());
return ret;
}
#else
int main()
{
return 0;
}
#endif //#ifdef BOOST_WINDOWS
|
.global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r14
push %r8
push %r9
push %rbp
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0x44b9, %r9
nop
nop
nop
add %rdx, %rdx
movb $0x61, (%r9)
nop
nop
nop
nop
nop
cmp $37542, %rbx
lea addresses_D_ht+0x14d71, %r14
inc %r8
movb $0x61, (%r14)
nop
nop
nop
nop
nop
cmp $65386, %r14
lea addresses_UC_ht+0x1d389, %rsi
lea addresses_D_ht+0x1789, %rdi
clflush (%rdi)
and %rbp, %rbp
mov $74, %rcx
rep movsq
nop
nop
xor %rdx, %rdx
lea addresses_normal_ht+0x14389, %r9
add %rcx, %rcx
mov $0x6162636465666768, %rbp
movq %rbp, (%r9)
nop
nop
nop
nop
nop
and $1137, %r8
lea addresses_normal_ht+0xbb89, %rsi
nop
nop
add %rbp, %rbp
movups (%rsi), %xmm7
vpextrq $0, %xmm7, %rdx
nop
nop
nop
nop
nop
add %r14, %r14
lea addresses_normal_ht+0x9c89, %rdi
nop
nop
cmp %rdx, %rdx
vmovups (%rdi), %ymm0
vextracti128 $1, %ymm0, %xmm0
vpextrq $1, %xmm0, %rsi
and $37178, %rdx
lea addresses_D_ht+0x1c389, %rdi
nop
nop
mfence
movb (%rdi), %cl
cmp $41570, %rbp
lea addresses_UC_ht+0x1589, %rbx
nop
add %rdi, %rdi
mov $0x6162636465666768, %r8
movq %r8, %xmm6
and $0xffffffffffffffc0, %rbx
movaps %xmm6, (%rbx)
and $41812, %r14
lea addresses_A_ht+0x11c57, %rdi
xor %rsi, %rsi
mov (%rdi), %r14d
nop
nop
nop
dec %r12
lea addresses_D_ht+0x1dc81, %r14
nop
nop
nop
nop
nop
dec %rdi
mov $0x6162636465666768, %r8
movq %r8, (%r14)
nop
nop
nop
nop
sub %rbx, %rbx
lea addresses_A_ht+0x7fc9, %rsi
lea addresses_WC_ht+0x4429, %rdi
nop
nop
xor %rbx, %rbx
mov $63, %rcx
rep movsb
nop
nop
nop
nop
nop
inc %r14
lea addresses_normal_ht+0x5569, %rsi
lea addresses_WC_ht+0xaa7b, %rdi
nop
nop
sub %rbx, %rbx
mov $59, %rcx
rep movsw
nop
nop
nop
nop
nop
and $11768, %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r9
pop %r8
pop %r14
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r14
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
// REPMOV
lea addresses_D+0x94f5, %rsi
lea addresses_WC+0x14389, %rdi
nop
and %rdx, %rdx
mov $95, %rcx
rep movsl
sub %rdx, %rdx
// Store
lea addresses_RW+0xe089, %rcx
nop
nop
cmp $8829, %rsi
mov $0x5152535455565758, %rdi
movq %rdi, %xmm7
movups %xmm7, (%rcx)
nop
nop
dec %rsi
// Store
lea addresses_RW+0x51a5, %rdi
nop
nop
nop
cmp %r12, %r12
movl $0x51525354, (%rdi)
nop
nop
sub $47448, %rsi
// Faulty Load
lea addresses_A+0xfb89, %rdx
nop
nop
nop
nop
and %r12, %r12
movups (%rdx), %xmm7
vpextrq $1, %xmm7, %r14
lea oracles, %rdx
and $0xff, %r14
shlq $12, %r14
mov (%rdx,%r14,1), %r14
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %r14
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_A', 'same': False, 'size': 2, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_WC', 'congruent': 11, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 16, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 4, 'congruent': 2, 'NT': True, 'AVXalign': False}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_A', 'same': True, 'size': 16, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'type': 'addresses_WC_ht', 'same': False, 'size': 1, 'congruent': 4, 'NT': False, 'AVXalign': True}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 1, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_normal_ht', 'same': False, 'size': 8, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_normal_ht', 'same': False, 'size': 16, 'congruent': 11, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal_ht', 'same': False, 'size': 32, 'congruent': 7, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'same': False, 'size': 1, 'congruent': 9, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_UC_ht', 'same': False, 'size': 16, 'congruent': 6, 'NT': True, 'AVXalign': True}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 4, 'congruent': 1, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 8, 'congruent': 2, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 4, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 1, 'same': True}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 1, 'same': False}, 'OP': 'REPM'}
{'00': 7976}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
; A006416: Number of rooted planar maps. Also a(n)=T(4,n-3), array T as in A049600.
; 1,8,20,38,63,96,138,190,253,328,416,518,635,768,918,1086,1273,1480,1708,1958,2231,2528,2850,3198,3573,3976,4408,4870,5363,5888,6446,7038,7665,8328,9028,9766,10543,11360,12218,13118,14061,15048,16080,17158,18283,19456,20678,21950,23273,24648,26076,27558,29095,30688,32338,34046,35813,37640,39528,41478,43491,45568,47710,49918,52193,54536,56948,59430,61983,64608,67306,70078,72925,75848,78848,81926,85083,88320,91638,95038,98521,102088,105740,109478,113303,117216,121218,125310,129493,133768,138136,142598,147155,151808,156558,161406,166353,171400,176548,181798,187151,192608,198170,203838,209613,215496,221488,227590,233803,240128,246566,253118,259785,266568,273468,280486,287623,294880,302258,309758,317381,325128,333000,340998,349123,357376,365758,374270,382913,391688,400596,409638,418815,428128,437578,447166,456893,466760,476768,486918,497211,507648,518230,528958,539833,550856,562028,573350,584823,596448,608226,620158,632245,644488,656888,669446,682163,695040,708078,721278,734641,748168,761860,775718,789743,803936,818298,832830,847533,862408,877456,892678,908075,923648,939398,955326,971433,987720,1004188,1020838,1037671,1054688,1071890,1089278,1106853,1124616,1142568,1160710,1179043,1197568,1216286,1235198,1254305,1273608,1293108,1312806,1332703,1352800,1373098,1393598,1414301,1435208,1456320,1477638,1499163,1520896,1542838,1564990,1587353,1609928,1632716,1655718,1678935,1702368,1726018,1749886,1773973,1798280,1822808,1847558,1872531,1897728,1923150,1948798,1974673,2000776,2027108,2053670,2080463,2107488,2134746,2162238,2189965,2217928,2246128,2274566,2303243,2332160,2361318,2390718,2420361,2450248,2480380,2510758,2541383,2572256,2603378,2634750,2666373,2698248
mov $2,$0
add $0,5
bin $0,3
mul $2,3
sub $0,$2
mov $1,$0
sub $1,9
|
;
;
; Z88 Maths Routines
;
; C Interface for Small C+ Compiler
;
; 7/12/98 djm
;double asin(double)
;Number in FA..
SECTION code_fp
INCLUDE "fpp.def"
PUBLIC asin
EXTERN fsetup
EXTERN stkequ2
.asin
call fsetup
fpp(FP_ASN)
jp stkequ2
|
; A158275: Denominators of antiharmonic means of divisors of n.
; Submitted by Christian Krause
; 1,3,2,1,3,6,4,3,1,9,6,2,7,12,6,1,9,3,10,1,8,18,12,6,1,21,2,4,15,18,16,3,12,27,12,1,19,6,14,9,21,24,22,2,3,36,24,2,1,1,18,7,27,6,18,12,4,9,30,2,31,48,4,1,21,36,34,3,24,36,36,3,37,57,2,10,24,42,40,3,1,63,42,8,27,66,6,18,45,9,28,4,32,72,30,6,49,3,6,1
add $0,1
mov $2,$0
lpb $0
add $1,$4
mov $3,$2
dif $3,$0
cmp $3,$2
cmp $3,0
mul $3,$0
sub $0,1
add $4,$3
lpe
add $4,1
gcd $1,$4
div $4,$1
mov $0,$4
|
rainbow_bridge:
lw t2, RAINBOW_BRIDGE_CONDITION
beq t2, r0, @@open
li at, 1
beq t2, at, @@medallions
li at, 2
beq t2, at, @@dungeons
li at, 3
beq t2, at, @@stones
li at, 4
beq t2, at, @@vanilla
li at, 5
beq t2, at, @@tokens
@@open:
li at, 0
jr ra
li t2, 0
@@medallions:
li at, 0x3F ; medallions
and t2, v0, at
li t7, 0
andi t8, t2, 0x01
beqz t8, @@medallions_1
nop
addiu t7, 1
@@medallions_1:
andi t8, t2, 0x02
beqz t8, @@medallions_2
nop
addiu t7, 1
@@medallions_2:
andi t8, t2, 0x04
beqz t8, @@medallions_3
nop
addiu t7, 1
@@medallions_3:
andi t8, t2, 0x08
beqz t8, @@medallions_4
nop
addiu t7, 1
@@medallions_4:
andi t8, t2, 0x10
beqz t8, @@medallions_5
nop
addiu t7, 1
@@medallions_5:
andi t8, t2, 0x20
beqz t8, @@medallions_6
nop
addiu t7, 1
@@medallions_6:
b @@count
nop
@@dungeons:
li at, 0x1C003F ; stones and medallions
and t2, v0, at
li t7, 0
andi t8, t2, 0x01
beqz t8, @@dungeons_1
nop
addiu t7, 1
@@dungeons_1:
andi t8, t2, 0x02
beqz t8, @@dungeons_2
nop
addiu t7, 1
@@dungeons_2:
andi t8, t2, 0x04
beqz t8, @@dungeons_3
nop
addiu t7, 1
@@dungeons_3:
andi t8, t2, 0x08
beqz t8, @@dungeons_4
nop
addiu t7, 1
@@dungeons_4:
andi t8, t2, 0x10
beqz t8, @@dungeons_5
nop
addiu t7, 1
@@dungeons_5:
andi t8, t2, 0x20
beqz t8, @@dungeons_6
nop
addiu t7, 1
@@dungeons_6:
lui t8, 0x04
and t8, t2, t8
beqz t8, @@dungeons_7
nop
addiu t7, 1
@@dungeons_7:
lui t8, 0x08
and t8, t2, t8
beqz t8, @@dungeons_8
nop
addiu t7, 1
@@dungeons_8:
lui t8, 0x10
and t8, t2, t8
beqz t8, @@dungeons_9
nop
addiu t7, 1
@@dungeons_9:
b @@count
nop
@@stones:
li at, 0x1C0000 ; stones
and t2, v0, at
li t7, 0
lui t8, 0x04
and t8, t2, t8
beqz t8, @@stones_1
nop
addiu t7, 1
@@stones_1:
lui t8, 0x08
and t8, t2, t8
beqz t8, @@stones_2
nop
addiu t7, 1
@@stones_2:
lui t8, 0x10
and t8, t2, t8
beqz t8, @@stones_3
nop
addiu t7, 1
@@stones_3:
b @@count
nop
@@tokens:
lh t7, 0xD0(a3) ; Gold Skulltulas
@@count:
li at, 0
lh t8, RAINBOW_BRIDGE_COUNT
jr ra
slt t2, t7, t8
@@vanilla:
li at, 0x18 ; shadow and spirit medallions
and t2, v0, at
bne t2, at, @@return
nop
lbu t7, 0x84(a3) ; Light arrow slot
li t2, 0x12 ; light arrow item id
beq t2, t7, @@return
nop
li at, 0xFFFF
@@return:
jr ra
and t2, v0, at
|
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