text stringlengths 1 1.05M |
|---|
; A285077: Positions of 0 in A285076; complement of A285078.
; 2,3,5,7,8,10,12,13,15,17,19,20,22,24,25,27,29,31,32,34,36,37,39,41,42,44,46,48,49,51,53,54,56,58,60,61,63,65,66,68,70,71,73,75,77,78,80,82,83,85,87,89,90,92,94,95,97,99,101,102,104,106,107,109,111,112,114,116,118,119,121,123,124,126,128,130,131,133,135,136,138,140,141,143,145,147,148,150,152,153,155,157,159,160,162,164,165,167,169,171,172,174,176,177,179,181,182,184,186,188,189,191,193,194,196,198,200,201,203,205,206,208,210,211,213,215,217,218,220,222,223,225,227,229,230,232,234,235,237,239,240,242,244,246,247,249,251,252,254,256,258,259,261,263,264,266,268,270,271,273,275,276,278,280,281,283,285,287,288,290,292,293,295,297,299,300,302,304,305,307,309,310,312,314,316,317,319,321,322,324,326,328,329,331,333,334,336,338,340,341,343,345,346,348,350,351,353,355,357,358,360,362,363,365,367,369,370,372,374,375,377,379,380,382,384,386,387,389,391,392,394,396,398,399,401,403,404,406,408,409,411,413,415,416,418,420,421,423,425,427
mov $2,$0
pow $0,2
div $0,2
lpb $0
add $1,1
sub $0,$1
sub $0,$1
trn $0,1
lpe
add $1,2
add $1,$2
|
; A060790: Inscribe two circles of curvature 2 inside a circle of curvature -1. Sequence gives curvatures of the smallest circles that can be sequentially inscribed in such a diagram.
; Submitted by Jon Maiga
; -1,2,2,3,15,38,110,323,927,2682,7754,22403,64751,187134,540822,1563011,4517183,13054898,37729362,109039875,315131087,910745750,2632104062,7606921923,21984412383,63536130986,183622826522,530679817859,1533693138351,4432455434478,12810033954854,37021685237507,106994656115327,309220295180898,893663239112610,2582734695580163,7464241803632015,21572059181468678,62344408122249102,180178683519119427,520726059842042399,1504926243785353178,4349317566170780906,12569761056077233539,36327283672224692847
mov $1,1
mov $4,-2
lpb $0
sub $0,1
add $2,$1
sub $3,1
add $4,$3
add $3,$4
add $1,$3
add $4,$2
add $3,$4
sub $4,$3
sub $3,3
add $3,$4
add $3,2
add $3,$2
add $2,1
sub $3,1
lpe
mov $0,$4
div $0,2
|
.global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r9
push %rax
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0x2778, %rbx
nop
nop
nop
nop
sub $22417, %rcx
mov (%rbx), %r12
nop
nop
nop
sub %r9, %r9
lea addresses_WC_ht+0x145f0, %rax
nop
and %rdi, %rdi
movb (%rax), %bl
nop
sub %r12, %r12
lea addresses_WT_ht+0x1508, %rax
nop
nop
sub $48352, %rbp
movw $0x6162, (%rax)
nop
nop
nop
inc %rbp
lea addresses_normal_ht+0xf734, %rbx
nop
nop
nop
nop
cmp $3693, %r9
vmovups (%rbx), %ymm2
vextracti128 $0, %ymm2, %xmm2
vpextrq $1, %xmm2, %rcx
nop
inc %rdi
lea addresses_A_ht+0x1d378, %rcx
nop
nop
and $53039, %r9
movups (%rcx), %xmm4
vpextrq $1, %xmm4, %r12
nop
nop
nop
nop
add %rcx, %rcx
lea addresses_normal_ht+0x7678, %rcx
nop
cmp $12079, %rbx
movl $0x61626364, (%rcx)
add %rcx, %rcx
lea addresses_A_ht+0xa500, %rsi
lea addresses_UC_ht+0x8b78, %rdi
nop
nop
cmp %rbx, %rbx
mov $100, %rcx
rep movsl
nop
sub %rdi, %rdi
lea addresses_normal_ht+0x2638, %rsi
lea addresses_UC_ht+0xc378, %rdi
nop
nop
nop
nop
sub %rax, %rax
mov $58, %rcx
rep movsl
nop
nop
dec %rsi
lea addresses_A_ht+0xad38, %rdi
nop
nop
nop
nop
add $16106, %rbx
mov (%rdi), %rsi
nop
nop
add $34149, %rax
lea addresses_UC_ht+0xd578, %rsi
clflush (%rsi)
nop
nop
nop
nop
nop
xor %rcx, %rcx
mov (%rsi), %ax
nop
nop
nop
xor %rax, %rax
lea addresses_WC_ht+0xcb78, %rsi
lea addresses_A_ht+0x7c78, %rdi
nop
nop
nop
xor $12362, %rbx
mov $69, %rcx
rep movsl
nop
xor %r9, %r9
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %rax
pop %r9
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r14
push %rax
push %rbx
push %rcx
// Faulty Load
lea addresses_WC+0x3378, %r14
nop
nop
nop
nop
nop
xor $64091, %rbx
mov (%r14), %r11d
lea oracles, %rcx
and $0xff, %r11
shlq $12, %r11
mov (%rcx,%r11,1), %r11
pop %rcx
pop %rbx
pop %rax
pop %r14
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_WC', 'same': False, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'type': 'addresses_WC', 'same': True, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_A_ht', 'same': True, 'size': 8, 'congruent': 10, 'NT': False, 'AVXalign': True}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WC_ht', 'same': False, 'size': 1, 'congruent': 3, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_WT_ht', 'same': False, 'size': 2, 'congruent': 1, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_normal_ht', 'same': False, 'size': 32, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 16, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_normal_ht', 'same': False, 'size': 4, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'congruent': 1, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 8, 'congruent': 5, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'same': False, 'size': 2, 'congruent': 8, 'NT': True, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WC_ht', 'congruent': 8, 'same': True}, 'dst': {'type': 'addresses_A_ht', 'congruent': 8, 'same': False}, 'OP': 'REPM'}
{'38': 21829}
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
*/
|
/*
*-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
*
* Copyright 2018 Intel Corporation All Rights Reserved.
*
*-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
*/
#include <iostream>
#include "HumiResource.h"
#include "OCPlatform.h"
#define INTERFACE_KEY "if"
using namespace OC;
namespace PH = std::placeholders;
HumiResource::HumiResource(std::string resourceUri):
m_interestedObservers{},
m_var_value_humi{0},
m_var_value_ds_humi{0},
m_var_value_n{},
m_var_value_if{},
m_var_value_rt{}
{
std::cout << "Running: HumiResource constructor" << std::endl;
// VS2013 will fail list initialization so use array initialization
m_resourceUri = resourceUri;
m_RESOURCE_TYPE[0] = "oic.r.humidity";
m_RESOURCE_INTERFACE[0] = "oic.if.baseline";
m_RESOURCE_INTERFACE[1] = "oic.if.a";
m_IF_UPDATE[0] = "oic.if.baseline";
m_IF_UPDATE[1] = "oic.if.a";
m_var_name_ds_humi ="desiredHumidity";
m_var_name_humi = "humidity";
m_var_name_n = "n";
m_var_name_if = "if";
m_var_name_rt = "rt";
// initialize member variables /dimming
m_var_value_humi = 0;
m_var_value_ds_humi =0;
m_var_value_n = ""; // current value of property "n"
// initialize vector if
m_var_value_if.push_back("oic.if.baseline");
m_var_value_if.push_back("oic.if.a");
// initialize vector rt
m_var_value_rt.push_back("oic.r.humidity");
}
HumiResource::~HumiResource(void) { }
OCStackResult HumiResource::registerResource(uint8_t resourceProperty)
{
EntityHandler cb = std::bind(&HumiResource::entityHandler, this, PH::_1);
OCStackResult result = OC_STACK_ERROR;
result = OCPlatform::registerResource(m_resourceHandle,
m_resourceUri,
m_RESOURCE_TYPE[0],
m_RESOURCE_INTERFACE[0],
cb,
resourceProperty);
if (OC_STACK_OK != result)
{
std::cerr << "Failed to register BinarySwitchResoruce." << std::endl;
return result;
}
/// add the additional resource types
for( size_t a = 1; a < (sizeof(m_RESOURCE_TYPE)/sizeof(m_RESOURCE_TYPE[0])); a++ )
{
result = OCPlatform::bindTypeToResource(m_resourceHandle, m_RESOURCE_TYPE[a].c_str());
if (OC_STACK_OK != result)
{
std::cerr << "Could not bind resource type:" << m_RESOURCE_INTERFACE[a] << std::endl;
return result;
}
}
// add the additional interfaces
for( size_t a = 1; a < (sizeof(m_RESOURCE_INTERFACE)/sizeof(m_RESOURCE_INTERFACE[0])); a++)
{
result = OCPlatform::bindInterfaceToResource(m_resourceHandle, m_RESOURCE_INTERFACE[a].c_str());
if (OC_STACK_OK != result)
{
std::cerr << "Could not bind interface:" << m_RESOURCE_INTERFACE[a] << std::endl;
return result;
}
}
std::cout << "HumiResource:" << std::endl;
std::cout << "\t" << "# resource interfaces: "
<< (sizeof(m_RESOURCE_INTERFACE)/sizeof(m_RESOURCE_INTERFACE[0])) << std::endl;
std::cout << "\t" << "# resource types : "
<< (sizeof(m_RESOURCE_TYPE)/sizeof(m_RESOURCE_TYPE[0])) << std::endl;
return result;
}
int HumiResource::getHumi(void)
{
return m_var_value_humi;
}
void HumiResource::setHumi(int humi)
{
m_var_value_humi = humi;
std::cout << "\t\t" << "property 'humidity': " << m_var_value_humi << std::endl;
}
OCStackResult HumiResource::sendNotification(void)
{
OCStackResult sResult = OC_STACK_OK;
if ( m_interestedObservers.size() > 0) {
std::cout << "Notifying list" << m_interestedObservers.size() << " of observers\n";
auto pResponse = std::make_shared<OC::OCResourceResponse>();
sResult = OCPlatform::notifyListOfObservers(m_resourceHandle,
m_interestedObservers,
pResponse);
}
return sResult;
}
OC::OCRepresentation HumiResource::get(const OC::OCRepresentation& rep , OC::QueryParamsMap queries)
{
OC_UNUSED(queries);
OC::OCRepresentation result_rep;
//if (rep.hasAttribute(m_var_name_humi)){
// result_rep.setValue(m_var_name_humi, m_var_value_humi );
//}
result_rep.setValue(m_var_name_ds_humi, m_var_value_ds_humi );
return result_rep;
}
OC::OCRepresentation HumiResource::get(OC::QueryParamsMap queries)
{
OC_UNUSED(queries);
m_rep.setValue(m_var_name_humi, m_var_value_humi );
m_rep.setValue(m_var_name_ds_humi,m_var_value_ds_humi);
// m_rep.setValue(m_var_name_n, m_var_value_n );
m_rep.setValue(m_var_name_if, m_var_value_if );
m_rep.setValue(m_var_name_rt, m_var_value_rt );
return m_rep;
}
OCEntityHandlerResult HumiResource::post(OC::QueryParamsMap queries, const OC::OCRepresentation& rep)
{
OCEntityHandlerResult ehResult = OC_EH_OK;
OC_UNUSED(queries);
if (ehResult == OC_EH_OK)
{
// no error: assign the variables
/*
try {
// value exist in payload
if (rep.getValue(m_var_name_humi, m_var_value_humi ))
{
std::cout << "\t\t" << "property 'humidity': " << m_var_value_humi << std::endl;
}
else
{
std::cout << "\t\t" << "property 'humidity' not found in the representation" << std::endl;
}
}
catch (std::exception& e)
{
std::cout << e.what() << std::endl;
}
*/
try {
// value exist in payload
if (rep.hasAttribute(m_var_name_ds_humi) && rep.getValue(m_var_name_ds_humi, m_var_value_ds_humi ))
{
std::cout << "\t\t" << "property 'ds_humidity': " << m_var_value_ds_humi << std::endl;
}
else
{
std::cout << "\t\t" << "property 'ds_humidity' not found in the representation" << std::endl;
}
}
catch (std::exception& e)
{
std::cout << e.what() << std::endl;
}
try {
if (rep.hasAttribute(m_var_name_if))
{
rep.getValue(m_var_name_if, m_var_value_if);
int first = 1;
std::cout << "\t\t" << "property 'if' : " ;
for(auto myvar: m_var_value_if)
{
if (first)
{
std::cout << myvar;
first = 0;
}
else
{
std::cout << "," << myvar;
}
}
std::cout << std::endl;
}
else
{
std::cout << "\t\t" << "property 'if' not found in the representation" << std::endl;
}
}
catch (std::exception& e)
{
std::cout << e.what() << std::endl;
}
try {
if (rep.hasAttribute(m_var_name_rt))
{
rep.getValue(m_var_name_rt, m_var_value_rt);
int first = 1;
std::cout << "\t\t" << "property 'rt' : " ;
for(auto myvar: m_var_value_rt)
{
if (first)
{
std::cout << myvar;
first = 0;
}
else
{
std::cout << "," << myvar;
}
}
std::cout << std::endl;
}
else
{
std::cout << "\t\t" << "property 'rt' not found in the representation" << std::endl;
}
}
catch (std::exception& e)
{
std::cout << e.what() << std::endl;
}
}
return ehResult;
}
OCEntityHandlerResult HumiResource::entityHandler(std::shared_ptr<OC::OCResourceRequest> request)
{
OCEntityHandlerResult ehResult = OC_EH_ERROR;
if (request)
{
std::cout << "In entity handler for HumiResource, URI is : "
<< request->getResourceUri() << std::endl;
// Check for query params (if any)
QueryParamsMap queries = request->getQueryParameters();
if (!queries.empty())
{
std::cout << "\nQuery processing up to entityHandler" << std::endl;
}
for (auto it : queries)
{
std::cout << "Query key: " << it.first << " value : " << it.second
<< std::endl;
}
// get the value, so that we can AND it to check which flags are set
int requestFlag = request->getRequestHandlerFlag();
if (requestFlag & RequestHandlerFlag::RequestFlag)
{
// request flag is set
auto pResponse = std::make_shared<OC::OCResourceResponse>();
pResponse->setRequestHandle(request->getRequestHandle());
pResponse->setResourceHandle(request->getResourceHandle());
if (request->getRequestType() == "GET")
{
std::cout<<"HumiResource Get Request"<< std::endl;
pResponse->setResourceRepresentation(get(queries), "");
if (OC_STACK_OK == OCPlatform::sendResponse(pResponse))
{
ehResult = OC_EH_OK;
}
}
else if (request->getRequestType() == "POST")
{
std::cout <<"HumiResource Post Request"<<std::endl;
try {
ehResult = post(queries, request->getResourceRepresentation());
if (request->getResourceRepresentation().hasAttribute(m_var_name_humi))
{
pResponse->setResponseResult(OCEntityHandlerResult::OC_EH_FORBIDDEN);
}
//pResponse->setResourceRepresentation(get(request->getResourceRepresentation(),queries), "");
pResponse->setResourceRepresentation(get(queries), "");
}
catch (std::exception& e)
{
std::cout << e.what() << std::endl;
}
if (OC_STACK_OK == OCPlatform::sendResponse(pResponse))
{
if (OC_STACK_OK != sendNotification() )
{
std::cerr << "NOTIFY failed." << std::endl;
}
}
}
else
{
std::cout << "HumiResource unsupported request type (delete,put,..)"
<< request->getRequestType() << std::endl;
pResponse->setResponseResult(OC_EH_ERROR);
pResponse->setResourceRepresentation(get(request->getResourceRepresentation(),queries), "");
OCPlatform::sendResponse(pResponse);
ehResult = OC_EH_ERROR;
}
}
if (requestFlag & RequestHandlerFlag::ObserverFlag)
{
// observe flag is set
std::cout << "\t\trequestFlag : Observer ";
ObservationInfo observationInfo = request->getObservationInfo();
((ObserveAction::ObserveRegister == observationInfo.action) ? std::cout << "Register\n" : std::cout << "Unregister\n");
if (ObserveAction::ObserveRegister == observationInfo.action)
{
// add observer
m_interestedObservers.push_back(observationInfo.obsId);
}
else if (ObserveAction::ObserveUnregister == observationInfo.action)
{
// delete observer
m_interestedObservers.erase(std::remove(
m_interestedObservers.begin(),
m_interestedObservers.end(),
observationInfo.obsId),
m_interestedObservers.end());
}
ehResult = OC_EH_OK;
}
}
return ehResult;
}
|
; A052980: Expansion of (1 - x)/(1 - 2*x - x^3).
; 1,1,2,5,11,24,53,117,258,569,1255,2768,6105,13465,29698,65501,144467,318632,702765,1549997,3418626,7540017,16630031,36678688,80897393,178424817,393528322,867954037,1914332891,4222194104,9312342245,20539017381,45300228866,99912799977,220364617335,486029463536,1071971727049,2364308071433,5214645606402,11501262939853,25366833951139,55948313508680,123397889957213,272162613865565,600273541239810,1323944972436833,2920052558739231,6440378658718272
add $0,1
mov $4,1
lpb $0,1
sub $0,1
mov $3,$2
mov $5,$2
add $5,$1
mov $1,$5
trn $1,2
add $1,$4
mov $2,$4
add $4,$5
sub $4,$3
lpe
|
; A032766: Numbers that are congruent to 0 or 1 (mod 3).
; 0,1,3,4,6,7,9,10,12,13,15,16,18,19,21,22,24,25,27,28,30,31,33,34,36,37,39,40,42,43,45,46,48,49,51,52,54,55,57,58,60,61,63,64,66,67,69,70,72,73,75,76,78,79,81,82,84,85,87,88,90,91,93,94,96,97,99,100,102,103,105,106,108,109,111,112,114,115,117,118,120,121,123,124,126,127,129,130,132,133,135,136,138,139,141,142,144,145,147,148,150,151,153,154,156,157,159,160,162,163,165,166,168,169,171,172,174,175,177,178,180,181,183,184,186,187,189,190,192,193,195,196,198,199,201,202,204,205,207,208,210,211,213,214,216,217,219,220,222,223,225,226,228,229,231,232,234,235,237,238,240,241,243,244,246,247,249,250,252,253,255,256,258,259,261,262,264,265,267,268,270,271,273,274,276,277,279,280,282,283,285,286,288,289,291,292,294,295,297,298,300,301,303,304,306,307,309,310,312,313,315,316,318,319,321,322,324,325,327,328,330,331,333,334,336,337,339,340,342,343,345,346,348,349,351,352,354,355,357,358,360,361,363,364,366,367,369,370,372,373
mul $0,6
div $0,4
mov $1,$0
|
_ls: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
close(fd);
}
int
main(int argc, char *argv[])
{
0: f3 0f 1e fb endbr32
4: 8d 4c 24 04 lea 0x4(%esp),%ecx
8: 83 e4 f0 and $0xfffffff0,%esp
b: ff 71 fc pushl -0x4(%ecx)
e: 55 push %ebp
f: 89 e5 mov %esp,%ebp
11: 56 push %esi
12: 53 push %ebx
13: 51 push %ecx
14: 83 ec 0c sub $0xc,%esp
17: 8b 01 mov (%ecx),%eax
19: 8b 51 04 mov 0x4(%ecx),%edx
int i;
if(argc < 2){
1c: 83 f8 01 cmp $0x1,%eax
1f: 7e 28 jle 49 <main+0x49>
21: 8d 5a 04 lea 0x4(%edx),%ebx
24: 8d 34 82 lea (%edx,%eax,4),%esi
27: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2e: 66 90 xchg %ax,%ax
ls(".");
exit();
}
for(i=1; i<argc; i++)
ls(argv[i]);
30: 83 ec 0c sub $0xc,%esp
33: ff 33 pushl (%ebx)
35: 83 c3 04 add $0x4,%ebx
38: e8 c3 00 00 00 call 100 <ls>
for(i=1; i<argc; i++)
3d: 83 c4 10 add $0x10,%esp
40: 39 f3 cmp %esi,%ebx
42: 75 ec jne 30 <main+0x30>
exit();
44: e8 5a 05 00 00 call 5a3 <exit>
ls(".");
49: 83 ec 0c sub $0xc,%esp
4c: 68 c0 0a 00 00 push $0xac0
51: e8 aa 00 00 00 call 100 <ls>
exit();
56: e8 48 05 00 00 call 5a3 <exit>
5b: 66 90 xchg %ax,%ax
5d: 66 90 xchg %ax,%ax
5f: 90 nop
00000060 <fmtname>:
{
60: f3 0f 1e fb endbr32
64: 55 push %ebp
65: 89 e5 mov %esp,%ebp
67: 56 push %esi
68: 53 push %ebx
69: 8b 75 08 mov 0x8(%ebp),%esi
for(p=path+strlen(path); p >= path && *p != '/'; p--)
6c: 83 ec 0c sub $0xc,%esp
6f: 56 push %esi
70: e8 4b 03 00 00 call 3c0 <strlen>
75: 83 c4 10 add $0x10,%esp
78: 01 f0 add %esi,%eax
7a: 89 c3 mov %eax,%ebx
7c: 73 0b jae 89 <fmtname+0x29>
7e: eb 0e jmp 8e <fmtname+0x2e>
80: 8d 43 ff lea -0x1(%ebx),%eax
83: 39 c6 cmp %eax,%esi
85: 77 0a ja 91 <fmtname+0x31>
87: 89 c3 mov %eax,%ebx
89: 80 3b 2f cmpb $0x2f,(%ebx)
8c: 75 f2 jne 80 <fmtname+0x20>
8e: 83 c3 01 add $0x1,%ebx
if(strlen(p) >= DIRSIZ)
91: 83 ec 0c sub $0xc,%esp
94: 53 push %ebx
95: e8 26 03 00 00 call 3c0 <strlen>
9a: 83 c4 10 add $0x10,%esp
9d: 83 f8 0d cmp $0xd,%eax
a0: 77 4a ja ec <fmtname+0x8c>
memmove(buf, p, strlen(p));
a2: 83 ec 0c sub $0xc,%esp
a5: 53 push %ebx
a6: e8 15 03 00 00 call 3c0 <strlen>
ab: 83 c4 0c add $0xc,%esp
ae: 50 push %eax
af: 53 push %ebx
b0: 68 f4 0d 00 00 push $0xdf4
b5: e8 b6 04 00 00 call 570 <memmove>
memset(buf+strlen(p), ' ', DIRSIZ-strlen(p));
ba: 89 1c 24 mov %ebx,(%esp)
bd: e8 fe 02 00 00 call 3c0 <strlen>
c2: 89 1c 24 mov %ebx,(%esp)
return buf;
c5: bb f4 0d 00 00 mov $0xdf4,%ebx
memset(buf+strlen(p), ' ', DIRSIZ-strlen(p));
ca: 89 c6 mov %eax,%esi
cc: e8 ef 02 00 00 call 3c0 <strlen>
d1: ba 0e 00 00 00 mov $0xe,%edx
d6: 83 c4 0c add $0xc,%esp
d9: 29 f2 sub %esi,%edx
db: 05 f4 0d 00 00 add $0xdf4,%eax
e0: 52 push %edx
e1: 6a 20 push $0x20
e3: 50 push %eax
e4: e8 17 03 00 00 call 400 <memset>
return buf;
e9: 83 c4 10 add $0x10,%esp
}
ec: 8d 65 f8 lea -0x8(%ebp),%esp
ef: 89 d8 mov %ebx,%eax
f1: 5b pop %ebx
f2: 5e pop %esi
f3: 5d pop %ebp
f4: c3 ret
f5: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
fc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000100 <ls>:
{
100: f3 0f 1e fb endbr32
104: 55 push %ebp
105: 89 e5 mov %esp,%ebp
107: 57 push %edi
108: 56 push %esi
109: 53 push %ebx
10a: 81 ec 64 02 00 00 sub $0x264,%esp
110: 8b 7d 08 mov 0x8(%ebp),%edi
if((fd = open(path, 0)) < 0){
113: 6a 00 push $0x0
115: 57 push %edi
116: e8 c8 04 00 00 call 5e3 <open>
11b: 83 c4 10 add $0x10,%esp
11e: 85 c0 test %eax,%eax
120: 0f 88 9a 01 00 00 js 2c0 <ls+0x1c0>
if(fstat(fd, &st) < 0){
126: 83 ec 08 sub $0x8,%esp
129: 8d b5 d4 fd ff ff lea -0x22c(%ebp),%esi
12f: 89 c3 mov %eax,%ebx
131: 56 push %esi
132: 50 push %eax
133: e8 c3 04 00 00 call 5fb <fstat>
138: 83 c4 10 add $0x10,%esp
13b: 85 c0 test %eax,%eax
13d: 0f 88 bd 01 00 00 js 300 <ls+0x200>
switch(st.type){
143: 0f b7 85 d4 fd ff ff movzwl -0x22c(%ebp),%eax
14a: 66 83 f8 01 cmp $0x1,%ax
14e: 74 60 je 1b0 <ls+0xb0>
150: 66 83 f8 02 cmp $0x2,%ax
154: 74 1a je 170 <ls+0x70>
close(fd);
156: 83 ec 0c sub $0xc,%esp
159: 53 push %ebx
15a: e8 6c 04 00 00 call 5cb <close>
15f: 83 c4 10 add $0x10,%esp
}
162: 8d 65 f4 lea -0xc(%ebp),%esp
165: 5b pop %ebx
166: 5e pop %esi
167: 5f pop %edi
168: 5d pop %ebp
169: c3 ret
16a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
printf(1, "%s %d %d %d\n", fmtname(path), st.type, st.ino, st.size);
170: 83 ec 0c sub $0xc,%esp
173: 8b 95 e4 fd ff ff mov -0x21c(%ebp),%edx
179: 8b b5 dc fd ff ff mov -0x224(%ebp),%esi
17f: 57 push %edi
180: 89 95 b4 fd ff ff mov %edx,-0x24c(%ebp)
186: e8 d5 fe ff ff call 60 <fmtname>
18b: 8b 95 b4 fd ff ff mov -0x24c(%ebp),%edx
191: 59 pop %ecx
192: 5f pop %edi
193: 52 push %edx
194: 56 push %esi
195: 6a 02 push $0x2
197: 50 push %eax
198: 68 a0 0a 00 00 push $0xaa0
19d: 6a 01 push $0x1
19f: e8 6c 05 00 00 call 710 <printf>
break;
1a4: 83 c4 20 add $0x20,%esp
1a7: eb ad jmp 156 <ls+0x56>
1a9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(strlen(path) + 1 + DIRSIZ + 1 > sizeof buf){
1b0: 83 ec 0c sub $0xc,%esp
1b3: 57 push %edi
1b4: e8 07 02 00 00 call 3c0 <strlen>
1b9: 83 c4 10 add $0x10,%esp
1bc: 83 c0 10 add $0x10,%eax
1bf: 3d 00 02 00 00 cmp $0x200,%eax
1c4: 0f 87 16 01 00 00 ja 2e0 <ls+0x1e0>
strcpy(buf, path);
1ca: 83 ec 08 sub $0x8,%esp
1cd: 57 push %edi
1ce: 8d bd e8 fd ff ff lea -0x218(%ebp),%edi
1d4: 57 push %edi
1d5: e8 66 01 00 00 call 340 <strcpy>
p = buf+strlen(buf);
1da: 89 3c 24 mov %edi,(%esp)
1dd: e8 de 01 00 00 call 3c0 <strlen>
while(read(fd, &de, sizeof(de)) == sizeof(de)){
1e2: 83 c4 10 add $0x10,%esp
p = buf+strlen(buf);
1e5: 01 f8 add %edi,%eax
*p++ = '/';
1e7: 8d 48 01 lea 0x1(%eax),%ecx
p = buf+strlen(buf);
1ea: 89 85 a8 fd ff ff mov %eax,-0x258(%ebp)
*p++ = '/';
1f0: 89 8d a4 fd ff ff mov %ecx,-0x25c(%ebp)
1f6: c6 00 2f movb $0x2f,(%eax)
while(read(fd, &de, sizeof(de)) == sizeof(de)){
1f9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
200: 83 ec 04 sub $0x4,%esp
203: 8d 85 c4 fd ff ff lea -0x23c(%ebp),%eax
209: 6a 10 push $0x10
20b: 50 push %eax
20c: 53 push %ebx
20d: e8 a9 03 00 00 call 5bb <read>
212: 83 c4 10 add $0x10,%esp
215: 83 f8 10 cmp $0x10,%eax
218: 0f 85 38 ff ff ff jne 156 <ls+0x56>
if(de.inum == 0)
21e: 66 83 bd c4 fd ff ff cmpw $0x0,-0x23c(%ebp)
225: 00
226: 74 d8 je 200 <ls+0x100>
memmove(p, de.name, DIRSIZ);
228: 83 ec 04 sub $0x4,%esp
22b: 8d 85 c6 fd ff ff lea -0x23a(%ebp),%eax
231: 6a 0e push $0xe
233: 50 push %eax
234: ff b5 a4 fd ff ff pushl -0x25c(%ebp)
23a: e8 31 03 00 00 call 570 <memmove>
p[DIRSIZ] = 0;
23f: 8b 85 a8 fd ff ff mov -0x258(%ebp),%eax
245: c6 40 0f 00 movb $0x0,0xf(%eax)
if(stat(buf, &st) < 0){
249: 58 pop %eax
24a: 5a pop %edx
24b: 56 push %esi
24c: 57 push %edi
24d: e8 8e 02 00 00 call 4e0 <stat>
252: 83 c4 10 add $0x10,%esp
255: 85 c0 test %eax,%eax
257: 0f 88 cb 00 00 00 js 328 <ls+0x228>
printf(1, "%s %d %d %d\n", fmtname(buf), st.type, st.ino, st.size);
25d: 83 ec 0c sub $0xc,%esp
260: 8b 8d e4 fd ff ff mov -0x21c(%ebp),%ecx
266: 8b 95 dc fd ff ff mov -0x224(%ebp),%edx
26c: 57 push %edi
26d: 0f bf 85 d4 fd ff ff movswl -0x22c(%ebp),%eax
274: 89 8d ac fd ff ff mov %ecx,-0x254(%ebp)
27a: 89 95 b0 fd ff ff mov %edx,-0x250(%ebp)
280: 89 85 b4 fd ff ff mov %eax,-0x24c(%ebp)
286: e8 d5 fd ff ff call 60 <fmtname>
28b: 5a pop %edx
28c: 8b 95 b0 fd ff ff mov -0x250(%ebp),%edx
292: 59 pop %ecx
293: 8b 8d ac fd ff ff mov -0x254(%ebp),%ecx
299: 51 push %ecx
29a: 52 push %edx
29b: ff b5 b4 fd ff ff pushl -0x24c(%ebp)
2a1: 50 push %eax
2a2: 68 a0 0a 00 00 push $0xaa0
2a7: 6a 01 push $0x1
2a9: e8 62 04 00 00 call 710 <printf>
2ae: 83 c4 20 add $0x20,%esp
2b1: e9 4a ff ff ff jmp 200 <ls+0x100>
2b6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2bd: 8d 76 00 lea 0x0(%esi),%esi
printf(2, "ls: cannot open %s\n", path);
2c0: 83 ec 04 sub $0x4,%esp
2c3: 57 push %edi
2c4: 68 78 0a 00 00 push $0xa78
2c9: 6a 02 push $0x2
2cb: e8 40 04 00 00 call 710 <printf>
return;
2d0: 83 c4 10 add $0x10,%esp
}
2d3: 8d 65 f4 lea -0xc(%ebp),%esp
2d6: 5b pop %ebx
2d7: 5e pop %esi
2d8: 5f pop %edi
2d9: 5d pop %ebp
2da: c3 ret
2db: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
2df: 90 nop
printf(1, "ls: path too long\n");
2e0: 83 ec 08 sub $0x8,%esp
2e3: 68 ad 0a 00 00 push $0xaad
2e8: 6a 01 push $0x1
2ea: e8 21 04 00 00 call 710 <printf>
break;
2ef: 83 c4 10 add $0x10,%esp
2f2: e9 5f fe ff ff jmp 156 <ls+0x56>
2f7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
2fe: 66 90 xchg %ax,%ax
printf(2, "ls: cannot stat %s\n", path);
300: 83 ec 04 sub $0x4,%esp
303: 57 push %edi
304: 68 8c 0a 00 00 push $0xa8c
309: 6a 02 push $0x2
30b: e8 00 04 00 00 call 710 <printf>
close(fd);
310: 89 1c 24 mov %ebx,(%esp)
313: e8 b3 02 00 00 call 5cb <close>
return;
318: 83 c4 10 add $0x10,%esp
}
31b: 8d 65 f4 lea -0xc(%ebp),%esp
31e: 5b pop %ebx
31f: 5e pop %esi
320: 5f pop %edi
321: 5d pop %ebp
322: c3 ret
323: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
327: 90 nop
printf(1, "ls: cannot stat %s\n", buf);
328: 83 ec 04 sub $0x4,%esp
32b: 57 push %edi
32c: 68 8c 0a 00 00 push $0xa8c
331: 6a 01 push $0x1
333: e8 d8 03 00 00 call 710 <printf>
continue;
338: 83 c4 10 add $0x10,%esp
33b: e9 c0 fe ff ff jmp 200 <ls+0x100>
00000340 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, const char *t)
{
340: f3 0f 1e fb endbr32
344: 55 push %ebp
char *os;
os = s;
while((*s++ = *t++) != 0)
345: 31 c0 xor %eax,%eax
{
347: 89 e5 mov %esp,%ebp
349: 53 push %ebx
34a: 8b 4d 08 mov 0x8(%ebp),%ecx
34d: 8b 5d 0c mov 0xc(%ebp),%ebx
while((*s++ = *t++) != 0)
350: 0f b6 14 03 movzbl (%ebx,%eax,1),%edx
354: 88 14 01 mov %dl,(%ecx,%eax,1)
357: 83 c0 01 add $0x1,%eax
35a: 84 d2 test %dl,%dl
35c: 75 f2 jne 350 <strcpy+0x10>
;
return os;
}
35e: 89 c8 mov %ecx,%eax
360: 5b pop %ebx
361: 5d pop %ebp
362: c3 ret
363: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
36a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
00000370 <strcmp>:
int
strcmp(const char *p, const char *q)
{
370: f3 0f 1e fb endbr32
374: 55 push %ebp
375: 89 e5 mov %esp,%ebp
377: 53 push %ebx
378: 8b 4d 08 mov 0x8(%ebp),%ecx
37b: 8b 55 0c mov 0xc(%ebp),%edx
while(*p && *p == *q)
37e: 0f b6 01 movzbl (%ecx),%eax
381: 0f b6 1a movzbl (%edx),%ebx
384: 84 c0 test %al,%al
386: 75 19 jne 3a1 <strcmp+0x31>
388: eb 26 jmp 3b0 <strcmp+0x40>
38a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
390: 0f b6 41 01 movzbl 0x1(%ecx),%eax
p++, q++;
394: 83 c1 01 add $0x1,%ecx
397: 83 c2 01 add $0x1,%edx
while(*p && *p == *q)
39a: 0f b6 1a movzbl (%edx),%ebx
39d: 84 c0 test %al,%al
39f: 74 0f je 3b0 <strcmp+0x40>
3a1: 38 d8 cmp %bl,%al
3a3: 74 eb je 390 <strcmp+0x20>
return (uchar)*p - (uchar)*q;
3a5: 29 d8 sub %ebx,%eax
}
3a7: 5b pop %ebx
3a8: 5d pop %ebp
3a9: c3 ret
3aa: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
3b0: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
3b2: 29 d8 sub %ebx,%eax
}
3b4: 5b pop %ebx
3b5: 5d pop %ebp
3b6: c3 ret
3b7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
3be: 66 90 xchg %ax,%ax
000003c0 <strlen>:
uint
strlen(const char *s)
{
3c0: f3 0f 1e fb endbr32
3c4: 55 push %ebp
3c5: 89 e5 mov %esp,%ebp
3c7: 8b 55 08 mov 0x8(%ebp),%edx
int n;
for(n = 0; s[n]; n++)
3ca: 80 3a 00 cmpb $0x0,(%edx)
3cd: 74 21 je 3f0 <strlen+0x30>
3cf: 31 c0 xor %eax,%eax
3d1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
3d8: 83 c0 01 add $0x1,%eax
3db: 80 3c 02 00 cmpb $0x0,(%edx,%eax,1)
3df: 89 c1 mov %eax,%ecx
3e1: 75 f5 jne 3d8 <strlen+0x18>
;
return n;
}
3e3: 89 c8 mov %ecx,%eax
3e5: 5d pop %ebp
3e6: c3 ret
3e7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
3ee: 66 90 xchg %ax,%ax
for(n = 0; s[n]; n++)
3f0: 31 c9 xor %ecx,%ecx
}
3f2: 5d pop %ebp
3f3: 89 c8 mov %ecx,%eax
3f5: c3 ret
3f6: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
3fd: 8d 76 00 lea 0x0(%esi),%esi
00000400 <memset>:
void*
memset(void *dst, int c, uint n)
{
400: f3 0f 1e fb endbr32
404: 55 push %ebp
405: 89 e5 mov %esp,%ebp
407: 57 push %edi
408: 8b 55 08 mov 0x8(%ebp),%edx
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
40b: 8b 4d 10 mov 0x10(%ebp),%ecx
40e: 8b 45 0c mov 0xc(%ebp),%eax
411: 89 d7 mov %edx,%edi
413: fc cld
414: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
416: 89 d0 mov %edx,%eax
418: 5f pop %edi
419: 5d pop %ebp
41a: c3 ret
41b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
41f: 90 nop
00000420 <strchr>:
char*
strchr(const char *s, char c)
{
420: f3 0f 1e fb endbr32
424: 55 push %ebp
425: 89 e5 mov %esp,%ebp
427: 8b 45 08 mov 0x8(%ebp),%eax
42a: 0f b6 4d 0c movzbl 0xc(%ebp),%ecx
for(; *s; s++)
42e: 0f b6 10 movzbl (%eax),%edx
431: 84 d2 test %dl,%dl
433: 75 16 jne 44b <strchr+0x2b>
435: eb 21 jmp 458 <strchr+0x38>
437: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
43e: 66 90 xchg %ax,%ax
440: 0f b6 50 01 movzbl 0x1(%eax),%edx
444: 83 c0 01 add $0x1,%eax
447: 84 d2 test %dl,%dl
449: 74 0d je 458 <strchr+0x38>
if(*s == c)
44b: 38 d1 cmp %dl,%cl
44d: 75 f1 jne 440 <strchr+0x20>
return (char*)s;
return 0;
}
44f: 5d pop %ebp
450: c3 ret
451: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
return 0;
458: 31 c0 xor %eax,%eax
}
45a: 5d pop %ebp
45b: c3 ret
45c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000460 <gets>:
char*
gets(char *buf, int max)
{
460: f3 0f 1e fb endbr32
464: 55 push %ebp
465: 89 e5 mov %esp,%ebp
467: 57 push %edi
468: 56 push %esi
int i, cc;
char c;
for(i=0; i+1 < max; ){
469: 31 f6 xor %esi,%esi
{
46b: 53 push %ebx
46c: 89 f3 mov %esi,%ebx
46e: 83 ec 1c sub $0x1c,%esp
471: 8b 7d 08 mov 0x8(%ebp),%edi
for(i=0; i+1 < max; ){
474: eb 33 jmp 4a9 <gets+0x49>
476: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
47d: 8d 76 00 lea 0x0(%esi),%esi
cc = read(0, &c, 1);
480: 83 ec 04 sub $0x4,%esp
483: 8d 45 e7 lea -0x19(%ebp),%eax
486: 6a 01 push $0x1
488: 50 push %eax
489: 6a 00 push $0x0
48b: e8 2b 01 00 00 call 5bb <read>
if(cc < 1)
490: 83 c4 10 add $0x10,%esp
493: 85 c0 test %eax,%eax
495: 7e 1c jle 4b3 <gets+0x53>
break;
buf[i++] = c;
497: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
49b: 83 c7 01 add $0x1,%edi
49e: 88 47 ff mov %al,-0x1(%edi)
if(c == '\n' || c == '\r')
4a1: 3c 0a cmp $0xa,%al
4a3: 74 23 je 4c8 <gets+0x68>
4a5: 3c 0d cmp $0xd,%al
4a7: 74 1f je 4c8 <gets+0x68>
for(i=0; i+1 < max; ){
4a9: 83 c3 01 add $0x1,%ebx
4ac: 89 fe mov %edi,%esi
4ae: 3b 5d 0c cmp 0xc(%ebp),%ebx
4b1: 7c cd jl 480 <gets+0x20>
4b3: 89 f3 mov %esi,%ebx
break;
}
buf[i] = '\0';
return buf;
}
4b5: 8b 45 08 mov 0x8(%ebp),%eax
buf[i] = '\0';
4b8: c6 03 00 movb $0x0,(%ebx)
}
4bb: 8d 65 f4 lea -0xc(%ebp),%esp
4be: 5b pop %ebx
4bf: 5e pop %esi
4c0: 5f pop %edi
4c1: 5d pop %ebp
4c2: c3 ret
4c3: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
4c7: 90 nop
4c8: 8b 75 08 mov 0x8(%ebp),%esi
4cb: 8b 45 08 mov 0x8(%ebp),%eax
4ce: 01 de add %ebx,%esi
4d0: 89 f3 mov %esi,%ebx
buf[i] = '\0';
4d2: c6 03 00 movb $0x0,(%ebx)
}
4d5: 8d 65 f4 lea -0xc(%ebp),%esp
4d8: 5b pop %ebx
4d9: 5e pop %esi
4da: 5f pop %edi
4db: 5d pop %ebp
4dc: c3 ret
4dd: 8d 76 00 lea 0x0(%esi),%esi
000004e0 <stat>:
int
stat(const char *n, struct stat *st)
{
4e0: f3 0f 1e fb endbr32
4e4: 55 push %ebp
4e5: 89 e5 mov %esp,%ebp
4e7: 56 push %esi
4e8: 53 push %ebx
int fd;
int r;
fd = open(n, O_RDONLY);
4e9: 83 ec 08 sub $0x8,%esp
4ec: 6a 00 push $0x0
4ee: ff 75 08 pushl 0x8(%ebp)
4f1: e8 ed 00 00 00 call 5e3 <open>
if(fd < 0)
4f6: 83 c4 10 add $0x10,%esp
4f9: 85 c0 test %eax,%eax
4fb: 78 2b js 528 <stat+0x48>
return -1;
r = fstat(fd, st);
4fd: 83 ec 08 sub $0x8,%esp
500: ff 75 0c pushl 0xc(%ebp)
503: 89 c3 mov %eax,%ebx
505: 50 push %eax
506: e8 f0 00 00 00 call 5fb <fstat>
close(fd);
50b: 89 1c 24 mov %ebx,(%esp)
r = fstat(fd, st);
50e: 89 c6 mov %eax,%esi
close(fd);
510: e8 b6 00 00 00 call 5cb <close>
return r;
515: 83 c4 10 add $0x10,%esp
}
518: 8d 65 f8 lea -0x8(%ebp),%esp
51b: 89 f0 mov %esi,%eax
51d: 5b pop %ebx
51e: 5e pop %esi
51f: 5d pop %ebp
520: c3 ret
521: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
return -1;
528: be ff ff ff ff mov $0xffffffff,%esi
52d: eb e9 jmp 518 <stat+0x38>
52f: 90 nop
00000530 <atoi>:
int
atoi(const char *s)
{
530: f3 0f 1e fb endbr32
534: 55 push %ebp
535: 89 e5 mov %esp,%ebp
537: 53 push %ebx
538: 8b 55 08 mov 0x8(%ebp),%edx
int n;
n = 0;
while('0' <= *s && *s <= '9')
53b: 0f be 02 movsbl (%edx),%eax
53e: 8d 48 d0 lea -0x30(%eax),%ecx
541: 80 f9 09 cmp $0x9,%cl
n = 0;
544: b9 00 00 00 00 mov $0x0,%ecx
while('0' <= *s && *s <= '9')
549: 77 1a ja 565 <atoi+0x35>
54b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
54f: 90 nop
n = n*10 + *s++ - '0';
550: 83 c2 01 add $0x1,%edx
553: 8d 0c 89 lea (%ecx,%ecx,4),%ecx
556: 8d 4c 48 d0 lea -0x30(%eax,%ecx,2),%ecx
while('0' <= *s && *s <= '9')
55a: 0f be 02 movsbl (%edx),%eax
55d: 8d 58 d0 lea -0x30(%eax),%ebx
560: 80 fb 09 cmp $0x9,%bl
563: 76 eb jbe 550 <atoi+0x20>
return n;
}
565: 89 c8 mov %ecx,%eax
567: 5b pop %ebx
568: 5d pop %ebp
569: c3 ret
56a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
00000570 <memmove>:
void*
memmove(void *vdst, const void *vsrc, int n)
{
570: f3 0f 1e fb endbr32
574: 55 push %ebp
575: 89 e5 mov %esp,%ebp
577: 57 push %edi
578: 8b 45 10 mov 0x10(%ebp),%eax
57b: 8b 55 08 mov 0x8(%ebp),%edx
57e: 56 push %esi
57f: 8b 75 0c mov 0xc(%ebp),%esi
char *dst;
const char *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
582: 85 c0 test %eax,%eax
584: 7e 0f jle 595 <memmove+0x25>
586: 01 d0 add %edx,%eax
dst = vdst;
588: 89 d7 mov %edx,%edi
58a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
*dst++ = *src++;
590: a4 movsb %ds:(%esi),%es:(%edi)
while(n-- > 0)
591: 39 f8 cmp %edi,%eax
593: 75 fb jne 590 <memmove+0x20>
return vdst;
}
595: 5e pop %esi
596: 89 d0 mov %edx,%eax
598: 5f pop %edi
599: 5d pop %ebp
59a: c3 ret
0000059b <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
59b: b8 01 00 00 00 mov $0x1,%eax
5a0: cd 40 int $0x40
5a2: c3 ret
000005a3 <exit>:
SYSCALL(exit)
5a3: b8 02 00 00 00 mov $0x2,%eax
5a8: cd 40 int $0x40
5aa: c3 ret
000005ab <wait>:
SYSCALL(wait)
5ab: b8 03 00 00 00 mov $0x3,%eax
5b0: cd 40 int $0x40
5b2: c3 ret
000005b3 <pipe>:
SYSCALL(pipe)
5b3: b8 04 00 00 00 mov $0x4,%eax
5b8: cd 40 int $0x40
5ba: c3 ret
000005bb <read>:
SYSCALL(read)
5bb: b8 05 00 00 00 mov $0x5,%eax
5c0: cd 40 int $0x40
5c2: c3 ret
000005c3 <write>:
SYSCALL(write)
5c3: b8 10 00 00 00 mov $0x10,%eax
5c8: cd 40 int $0x40
5ca: c3 ret
000005cb <close>:
SYSCALL(close)
5cb: b8 15 00 00 00 mov $0x15,%eax
5d0: cd 40 int $0x40
5d2: c3 ret
000005d3 <kill>:
SYSCALL(kill)
5d3: b8 06 00 00 00 mov $0x6,%eax
5d8: cd 40 int $0x40
5da: c3 ret
000005db <exec>:
SYSCALL(exec)
5db: b8 07 00 00 00 mov $0x7,%eax
5e0: cd 40 int $0x40
5e2: c3 ret
000005e3 <open>:
SYSCALL(open)
5e3: b8 0f 00 00 00 mov $0xf,%eax
5e8: cd 40 int $0x40
5ea: c3 ret
000005eb <mknod>:
SYSCALL(mknod)
5eb: b8 11 00 00 00 mov $0x11,%eax
5f0: cd 40 int $0x40
5f2: c3 ret
000005f3 <unlink>:
SYSCALL(unlink)
5f3: b8 12 00 00 00 mov $0x12,%eax
5f8: cd 40 int $0x40
5fa: c3 ret
000005fb <fstat>:
SYSCALL(fstat)
5fb: b8 08 00 00 00 mov $0x8,%eax
600: cd 40 int $0x40
602: c3 ret
00000603 <link>:
SYSCALL(link)
603: b8 13 00 00 00 mov $0x13,%eax
608: cd 40 int $0x40
60a: c3 ret
0000060b <mkdir>:
SYSCALL(mkdir)
60b: b8 14 00 00 00 mov $0x14,%eax
610: cd 40 int $0x40
612: c3 ret
00000613 <chdir>:
SYSCALL(chdir)
613: b8 09 00 00 00 mov $0x9,%eax
618: cd 40 int $0x40
61a: c3 ret
0000061b <dup>:
SYSCALL(dup)
61b: b8 0a 00 00 00 mov $0xa,%eax
620: cd 40 int $0x40
622: c3 ret
00000623 <getpid>:
SYSCALL(getpid)
623: b8 0b 00 00 00 mov $0xb,%eax
628: cd 40 int $0x40
62a: c3 ret
0000062b <sbrk>:
SYSCALL(sbrk)
62b: b8 0c 00 00 00 mov $0xc,%eax
630: cd 40 int $0x40
632: c3 ret
00000633 <sleep>:
SYSCALL(sleep)
633: b8 0d 00 00 00 mov $0xd,%eax
638: cd 40 int $0x40
63a: c3 ret
0000063b <uptime>:
SYSCALL(uptime)
63b: b8 0e 00 00 00 mov $0xe,%eax
640: cd 40 int $0x40
642: c3 ret
00000643 <waitx>:
SYSCALL(waitx)
643: b8 16 00 00 00 mov $0x16,%eax
648: cd 40 int $0x40
64a: c3 ret
0000064b <ps>:
SYSCALL(ps)
64b: b8 17 00 00 00 mov $0x17,%eax
650: cd 40 int $0x40
652: c3 ret
00000653 <set_priority>:
653: b8 18 00 00 00 mov $0x18,%eax
658: cd 40 int $0x40
65a: c3 ret
65b: 66 90 xchg %ax,%ax
65d: 66 90 xchg %ax,%ax
65f: 90 nop
00000660 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
660: 55 push %ebp
661: 89 e5 mov %esp,%ebp
663: 57 push %edi
664: 56 push %esi
665: 53 push %ebx
666: 83 ec 3c sub $0x3c,%esp
669: 89 4d c4 mov %ecx,-0x3c(%ebp)
uint x;
neg = 0;
if(sgn && xx < 0){
neg = 1;
x = -xx;
66c: 89 d1 mov %edx,%ecx
{
66e: 89 45 b8 mov %eax,-0x48(%ebp)
if(sgn && xx < 0){
671: 85 d2 test %edx,%edx
673: 0f 89 7f 00 00 00 jns 6f8 <printint+0x98>
679: f6 45 08 01 testb $0x1,0x8(%ebp)
67d: 74 79 je 6f8 <printint+0x98>
neg = 1;
67f: c7 45 bc 01 00 00 00 movl $0x1,-0x44(%ebp)
x = -xx;
686: f7 d9 neg %ecx
} else {
x = xx;
}
i = 0;
688: 31 db xor %ebx,%ebx
68a: 8d 75 d7 lea -0x29(%ebp),%esi
68d: 8d 76 00 lea 0x0(%esi),%esi
do{
buf[i++] = digits[x % base];
690: 89 c8 mov %ecx,%eax
692: 31 d2 xor %edx,%edx
694: 89 cf mov %ecx,%edi
696: f7 75 c4 divl -0x3c(%ebp)
699: 0f b6 92 cc 0a 00 00 movzbl 0xacc(%edx),%edx
6a0: 89 45 c0 mov %eax,-0x40(%ebp)
6a3: 89 d8 mov %ebx,%eax
6a5: 8d 5b 01 lea 0x1(%ebx),%ebx
}while((x /= base) != 0);
6a8: 8b 4d c0 mov -0x40(%ebp),%ecx
buf[i++] = digits[x % base];
6ab: 88 14 1e mov %dl,(%esi,%ebx,1)
}while((x /= base) != 0);
6ae: 39 7d c4 cmp %edi,-0x3c(%ebp)
6b1: 76 dd jbe 690 <printint+0x30>
if(neg)
6b3: 8b 4d bc mov -0x44(%ebp),%ecx
6b6: 85 c9 test %ecx,%ecx
6b8: 74 0c je 6c6 <printint+0x66>
buf[i++] = '-';
6ba: c6 44 1d d8 2d movb $0x2d,-0x28(%ebp,%ebx,1)
buf[i++] = digits[x % base];
6bf: 89 d8 mov %ebx,%eax
buf[i++] = '-';
6c1: ba 2d 00 00 00 mov $0x2d,%edx
while(--i >= 0)
6c6: 8b 7d b8 mov -0x48(%ebp),%edi
6c9: 8d 5c 05 d7 lea -0x29(%ebp,%eax,1),%ebx
6cd: eb 07 jmp 6d6 <printint+0x76>
6cf: 90 nop
6d0: 0f b6 13 movzbl (%ebx),%edx
6d3: 83 eb 01 sub $0x1,%ebx
write(fd, &c, 1);
6d6: 83 ec 04 sub $0x4,%esp
6d9: 88 55 d7 mov %dl,-0x29(%ebp)
6dc: 6a 01 push $0x1
6de: 56 push %esi
6df: 57 push %edi
6e0: e8 de fe ff ff call 5c3 <write>
while(--i >= 0)
6e5: 83 c4 10 add $0x10,%esp
6e8: 39 de cmp %ebx,%esi
6ea: 75 e4 jne 6d0 <printint+0x70>
putc(fd, buf[i]);
}
6ec: 8d 65 f4 lea -0xc(%ebp),%esp
6ef: 5b pop %ebx
6f0: 5e pop %esi
6f1: 5f pop %edi
6f2: 5d pop %ebp
6f3: c3 ret
6f4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
neg = 0;
6f8: c7 45 bc 00 00 00 00 movl $0x0,-0x44(%ebp)
6ff: eb 87 jmp 688 <printint+0x28>
701: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
708: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
70f: 90 nop
00000710 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, const char *fmt, ...)
{
710: f3 0f 1e fb endbr32
714: 55 push %ebp
715: 89 e5 mov %esp,%ebp
717: 57 push %edi
718: 56 push %esi
719: 53 push %ebx
71a: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
71d: 8b 75 0c mov 0xc(%ebp),%esi
720: 0f b6 1e movzbl (%esi),%ebx
723: 84 db test %bl,%bl
725: 0f 84 b4 00 00 00 je 7df <printf+0xcf>
ap = (uint*)(void*)&fmt + 1;
72b: 8d 45 10 lea 0x10(%ebp),%eax
72e: 83 c6 01 add $0x1,%esi
write(fd, &c, 1);
731: 8d 7d e7 lea -0x19(%ebp),%edi
state = 0;
734: 31 d2 xor %edx,%edx
ap = (uint*)(void*)&fmt + 1;
736: 89 45 d0 mov %eax,-0x30(%ebp)
739: eb 33 jmp 76e <printf+0x5e>
73b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
73f: 90 nop
740: 89 55 d4 mov %edx,-0x2c(%ebp)
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
state = '%';
743: ba 25 00 00 00 mov $0x25,%edx
if(c == '%'){
748: 83 f8 25 cmp $0x25,%eax
74b: 74 17 je 764 <printf+0x54>
write(fd, &c, 1);
74d: 83 ec 04 sub $0x4,%esp
750: 88 5d e7 mov %bl,-0x19(%ebp)
753: 6a 01 push $0x1
755: 57 push %edi
756: ff 75 08 pushl 0x8(%ebp)
759: e8 65 fe ff ff call 5c3 <write>
75e: 8b 55 d4 mov -0x2c(%ebp),%edx
} else {
putc(fd, c);
761: 83 c4 10 add $0x10,%esp
for(i = 0; fmt[i]; i++){
764: 0f b6 1e movzbl (%esi),%ebx
767: 83 c6 01 add $0x1,%esi
76a: 84 db test %bl,%bl
76c: 74 71 je 7df <printf+0xcf>
c = fmt[i] & 0xff;
76e: 0f be cb movsbl %bl,%ecx
771: 0f b6 c3 movzbl %bl,%eax
if(state == 0){
774: 85 d2 test %edx,%edx
776: 74 c8 je 740 <printf+0x30>
}
} else if(state == '%'){
778: 83 fa 25 cmp $0x25,%edx
77b: 75 e7 jne 764 <printf+0x54>
if(c == 'd'){
77d: 83 f8 64 cmp $0x64,%eax
780: 0f 84 9a 00 00 00 je 820 <printf+0x110>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
786: 81 e1 f7 00 00 00 and $0xf7,%ecx
78c: 83 f9 70 cmp $0x70,%ecx
78f: 74 5f je 7f0 <printf+0xe0>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
791: 83 f8 73 cmp $0x73,%eax
794: 0f 84 d6 00 00 00 je 870 <printf+0x160>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
79a: 83 f8 63 cmp $0x63,%eax
79d: 0f 84 8d 00 00 00 je 830 <printf+0x120>
putc(fd, *ap);
ap++;
} else if(c == '%'){
7a3: 83 f8 25 cmp $0x25,%eax
7a6: 0f 84 b4 00 00 00 je 860 <printf+0x150>
write(fd, &c, 1);
7ac: 83 ec 04 sub $0x4,%esp
7af: c6 45 e7 25 movb $0x25,-0x19(%ebp)
7b3: 6a 01 push $0x1
7b5: 57 push %edi
7b6: ff 75 08 pushl 0x8(%ebp)
7b9: e8 05 fe ff ff call 5c3 <write>
putc(fd, c);
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
7be: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
7c1: 83 c4 0c add $0xc,%esp
7c4: 6a 01 push $0x1
7c6: 83 c6 01 add $0x1,%esi
7c9: 57 push %edi
7ca: ff 75 08 pushl 0x8(%ebp)
7cd: e8 f1 fd ff ff call 5c3 <write>
for(i = 0; fmt[i]; i++){
7d2: 0f b6 5e ff movzbl -0x1(%esi),%ebx
putc(fd, c);
7d6: 83 c4 10 add $0x10,%esp
}
state = 0;
7d9: 31 d2 xor %edx,%edx
for(i = 0; fmt[i]; i++){
7db: 84 db test %bl,%bl
7dd: 75 8f jne 76e <printf+0x5e>
}
}
}
7df: 8d 65 f4 lea -0xc(%ebp),%esp
7e2: 5b pop %ebx
7e3: 5e pop %esi
7e4: 5f pop %edi
7e5: 5d pop %ebp
7e6: c3 ret
7e7: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
7ee: 66 90 xchg %ax,%ax
printint(fd, *ap, 16, 0);
7f0: 83 ec 0c sub $0xc,%esp
7f3: b9 10 00 00 00 mov $0x10,%ecx
7f8: 6a 00 push $0x0
7fa: 8b 5d d0 mov -0x30(%ebp),%ebx
7fd: 8b 45 08 mov 0x8(%ebp),%eax
800: 8b 13 mov (%ebx),%edx
802: e8 59 fe ff ff call 660 <printint>
ap++;
807: 89 d8 mov %ebx,%eax
809: 83 c4 10 add $0x10,%esp
state = 0;
80c: 31 d2 xor %edx,%edx
ap++;
80e: 83 c0 04 add $0x4,%eax
811: 89 45 d0 mov %eax,-0x30(%ebp)
814: e9 4b ff ff ff jmp 764 <printf+0x54>
819: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
printint(fd, *ap, 10, 1);
820: 83 ec 0c sub $0xc,%esp
823: b9 0a 00 00 00 mov $0xa,%ecx
828: 6a 01 push $0x1
82a: eb ce jmp 7fa <printf+0xea>
82c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
putc(fd, *ap);
830: 8b 5d d0 mov -0x30(%ebp),%ebx
write(fd, &c, 1);
833: 83 ec 04 sub $0x4,%esp
putc(fd, *ap);
836: 8b 03 mov (%ebx),%eax
write(fd, &c, 1);
838: 6a 01 push $0x1
ap++;
83a: 83 c3 04 add $0x4,%ebx
write(fd, &c, 1);
83d: 57 push %edi
83e: ff 75 08 pushl 0x8(%ebp)
putc(fd, *ap);
841: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
844: e8 7a fd ff ff call 5c3 <write>
ap++;
849: 89 5d d0 mov %ebx,-0x30(%ebp)
84c: 83 c4 10 add $0x10,%esp
state = 0;
84f: 31 d2 xor %edx,%edx
851: e9 0e ff ff ff jmp 764 <printf+0x54>
856: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
85d: 8d 76 00 lea 0x0(%esi),%esi
putc(fd, c);
860: 88 5d e7 mov %bl,-0x19(%ebp)
write(fd, &c, 1);
863: 83 ec 04 sub $0x4,%esp
866: e9 59 ff ff ff jmp 7c4 <printf+0xb4>
86b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
86f: 90 nop
s = (char*)*ap;
870: 8b 45 d0 mov -0x30(%ebp),%eax
873: 8b 18 mov (%eax),%ebx
ap++;
875: 83 c0 04 add $0x4,%eax
878: 89 45 d0 mov %eax,-0x30(%ebp)
if(s == 0)
87b: 85 db test %ebx,%ebx
87d: 74 17 je 896 <printf+0x186>
while(*s != 0){
87f: 0f b6 03 movzbl (%ebx),%eax
state = 0;
882: 31 d2 xor %edx,%edx
while(*s != 0){
884: 84 c0 test %al,%al
886: 0f 84 d8 fe ff ff je 764 <printf+0x54>
88c: 89 75 d4 mov %esi,-0x2c(%ebp)
88f: 89 de mov %ebx,%esi
891: 8b 5d 08 mov 0x8(%ebp),%ebx
894: eb 1a jmp 8b0 <printf+0x1a0>
s = "(null)";
896: bb c2 0a 00 00 mov $0xac2,%ebx
while(*s != 0){
89b: 89 75 d4 mov %esi,-0x2c(%ebp)
89e: b8 28 00 00 00 mov $0x28,%eax
8a3: 89 de mov %ebx,%esi
8a5: 8b 5d 08 mov 0x8(%ebp),%ebx
8a8: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
8af: 90 nop
write(fd, &c, 1);
8b0: 83 ec 04 sub $0x4,%esp
s++;
8b3: 83 c6 01 add $0x1,%esi
8b6: 88 45 e7 mov %al,-0x19(%ebp)
write(fd, &c, 1);
8b9: 6a 01 push $0x1
8bb: 57 push %edi
8bc: 53 push %ebx
8bd: e8 01 fd ff ff call 5c3 <write>
while(*s != 0){
8c2: 0f b6 06 movzbl (%esi),%eax
8c5: 83 c4 10 add $0x10,%esp
8c8: 84 c0 test %al,%al
8ca: 75 e4 jne 8b0 <printf+0x1a0>
8cc: 8b 75 d4 mov -0x2c(%ebp),%esi
state = 0;
8cf: 31 d2 xor %edx,%edx
8d1: e9 8e fe ff ff jmp 764 <printf+0x54>
8d6: 66 90 xchg %ax,%ax
8d8: 66 90 xchg %ax,%ax
8da: 66 90 xchg %ax,%ax
8dc: 66 90 xchg %ax,%ax
8de: 66 90 xchg %ax,%ax
000008e0 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
8e0: f3 0f 1e fb endbr32
8e4: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
8e5: a1 04 0e 00 00 mov 0xe04,%eax
{
8ea: 89 e5 mov %esp,%ebp
8ec: 57 push %edi
8ed: 56 push %esi
8ee: 53 push %ebx
8ef: 8b 5d 08 mov 0x8(%ebp),%ebx
8f2: 8b 10 mov (%eax),%edx
bp = (Header*)ap - 1;
8f4: 8d 4b f8 lea -0x8(%ebx),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
8f7: 39 c8 cmp %ecx,%eax
8f9: 73 15 jae 910 <free+0x30>
8fb: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
8ff: 90 nop
900: 39 d1 cmp %edx,%ecx
902: 72 14 jb 918 <free+0x38>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
904: 39 d0 cmp %edx,%eax
906: 73 10 jae 918 <free+0x38>
{
908: 89 d0 mov %edx,%eax
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
90a: 8b 10 mov (%eax),%edx
90c: 39 c8 cmp %ecx,%eax
90e: 72 f0 jb 900 <free+0x20>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
910: 39 d0 cmp %edx,%eax
912: 72 f4 jb 908 <free+0x28>
914: 39 d1 cmp %edx,%ecx
916: 73 f0 jae 908 <free+0x28>
break;
if(bp + bp->s.size == p->s.ptr){
918: 8b 73 fc mov -0x4(%ebx),%esi
91b: 8d 3c f1 lea (%ecx,%esi,8),%edi
91e: 39 fa cmp %edi,%edx
920: 74 1e je 940 <free+0x60>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
922: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
925: 8b 50 04 mov 0x4(%eax),%edx
928: 8d 34 d0 lea (%eax,%edx,8),%esi
92b: 39 f1 cmp %esi,%ecx
92d: 74 28 je 957 <free+0x77>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
92f: 89 08 mov %ecx,(%eax)
freep = p;
}
931: 5b pop %ebx
freep = p;
932: a3 04 0e 00 00 mov %eax,0xe04
}
937: 5e pop %esi
938: 5f pop %edi
939: 5d pop %ebp
93a: c3 ret
93b: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
93f: 90 nop
bp->s.size += p->s.ptr->s.size;
940: 03 72 04 add 0x4(%edx),%esi
943: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
946: 8b 10 mov (%eax),%edx
948: 8b 12 mov (%edx),%edx
94a: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
94d: 8b 50 04 mov 0x4(%eax),%edx
950: 8d 34 d0 lea (%eax,%edx,8),%esi
953: 39 f1 cmp %esi,%ecx
955: 75 d8 jne 92f <free+0x4f>
p->s.size += bp->s.size;
957: 03 53 fc add -0x4(%ebx),%edx
freep = p;
95a: a3 04 0e 00 00 mov %eax,0xe04
p->s.size += bp->s.size;
95f: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
962: 8b 53 f8 mov -0x8(%ebx),%edx
965: 89 10 mov %edx,(%eax)
}
967: 5b pop %ebx
968: 5e pop %esi
969: 5f pop %edi
96a: 5d pop %ebp
96b: c3 ret
96c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000970 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
970: f3 0f 1e fb endbr32
974: 55 push %ebp
975: 89 e5 mov %esp,%ebp
977: 57 push %edi
978: 56 push %esi
979: 53 push %ebx
97a: 83 ec 1c sub $0x1c,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
97d: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
980: 8b 3d 04 0e 00 00 mov 0xe04,%edi
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
986: 8d 70 07 lea 0x7(%eax),%esi
989: c1 ee 03 shr $0x3,%esi
98c: 83 c6 01 add $0x1,%esi
if((prevp = freep) == 0){
98f: 85 ff test %edi,%edi
991: 0f 84 a9 00 00 00 je a40 <malloc+0xd0>
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
997: 8b 07 mov (%edi),%eax
if(p->s.size >= nunits){
999: 8b 48 04 mov 0x4(%eax),%ecx
99c: 39 f1 cmp %esi,%ecx
99e: 73 6d jae a0d <malloc+0x9d>
9a0: 81 fe 00 10 00 00 cmp $0x1000,%esi
9a6: bb 00 10 00 00 mov $0x1000,%ebx
9ab: 0f 43 de cmovae %esi,%ebx
p = sbrk(nu * sizeof(Header));
9ae: 8d 0c dd 00 00 00 00 lea 0x0(,%ebx,8),%ecx
9b5: 89 4d e4 mov %ecx,-0x1c(%ebp)
9b8: eb 17 jmp 9d1 <malloc+0x61>
9ba: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
9c0: 8b 10 mov (%eax),%edx
if(p->s.size >= nunits){
9c2: 8b 4a 04 mov 0x4(%edx),%ecx
9c5: 39 f1 cmp %esi,%ecx
9c7: 73 4f jae a18 <malloc+0xa8>
9c9: 8b 3d 04 0e 00 00 mov 0xe04,%edi
9cf: 89 d0 mov %edx,%eax
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
9d1: 39 c7 cmp %eax,%edi
9d3: 75 eb jne 9c0 <malloc+0x50>
p = sbrk(nu * sizeof(Header));
9d5: 83 ec 0c sub $0xc,%esp
9d8: ff 75 e4 pushl -0x1c(%ebp)
9db: e8 4b fc ff ff call 62b <sbrk>
if(p == (char*)-1)
9e0: 83 c4 10 add $0x10,%esp
9e3: 83 f8 ff cmp $0xffffffff,%eax
9e6: 74 1b je a03 <malloc+0x93>
hp->s.size = nu;
9e8: 89 58 04 mov %ebx,0x4(%eax)
free((void*)(hp + 1));
9eb: 83 ec 0c sub $0xc,%esp
9ee: 83 c0 08 add $0x8,%eax
9f1: 50 push %eax
9f2: e8 e9 fe ff ff call 8e0 <free>
return freep;
9f7: a1 04 0e 00 00 mov 0xe04,%eax
if((p = morecore(nunits)) == 0)
9fc: 83 c4 10 add $0x10,%esp
9ff: 85 c0 test %eax,%eax
a01: 75 bd jne 9c0 <malloc+0x50>
return 0;
}
}
a03: 8d 65 f4 lea -0xc(%ebp),%esp
return 0;
a06: 31 c0 xor %eax,%eax
}
a08: 5b pop %ebx
a09: 5e pop %esi
a0a: 5f pop %edi
a0b: 5d pop %ebp
a0c: c3 ret
if(p->s.size >= nunits){
a0d: 89 c2 mov %eax,%edx
a0f: 89 f8 mov %edi,%eax
a11: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(p->s.size == nunits)
a18: 39 ce cmp %ecx,%esi
a1a: 74 54 je a70 <malloc+0x100>
p->s.size -= nunits;
a1c: 29 f1 sub %esi,%ecx
a1e: 89 4a 04 mov %ecx,0x4(%edx)
p += p->s.size;
a21: 8d 14 ca lea (%edx,%ecx,8),%edx
p->s.size = nunits;
a24: 89 72 04 mov %esi,0x4(%edx)
freep = prevp;
a27: a3 04 0e 00 00 mov %eax,0xe04
}
a2c: 8d 65 f4 lea -0xc(%ebp),%esp
return (void*)(p + 1);
a2f: 8d 42 08 lea 0x8(%edx),%eax
}
a32: 5b pop %ebx
a33: 5e pop %esi
a34: 5f pop %edi
a35: 5d pop %ebp
a36: c3 ret
a37: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
a3e: 66 90 xchg %ax,%ax
base.s.ptr = freep = prevp = &base;
a40: c7 05 04 0e 00 00 08 movl $0xe08,0xe04
a47: 0e 00 00
base.s.size = 0;
a4a: bf 08 0e 00 00 mov $0xe08,%edi
base.s.ptr = freep = prevp = &base;
a4f: c7 05 08 0e 00 00 08 movl $0xe08,0xe08
a56: 0e 00 00
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
a59: 89 f8 mov %edi,%eax
base.s.size = 0;
a5b: c7 05 0c 0e 00 00 00 movl $0x0,0xe0c
a62: 00 00 00
if(p->s.size >= nunits){
a65: e9 36 ff ff ff jmp 9a0 <malloc+0x30>
a6a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
prevp->s.ptr = p->s.ptr;
a70: 8b 0a mov (%edx),%ecx
a72: 89 08 mov %ecx,(%eax)
a74: eb b1 jmp a27 <malloc+0xb7>
|
;
; ZXPac v3 (c) 2014/21 Jouni 'Mr.Spiv' Korhonen
; Done for fun.. ;-) And definitely not the greatest.
;
; ZXPac v3 bit tag encoding is as follows:
;
; [n] means an arbitrary bit vector of length n
; [B] means a complete byte in byte boundary
; 11100 means a bit vector, MSB 1 and LSB 0
; 1xx11 means a bit vector with two varying bits 'xx'
; + means a concatenation
;
; 0 + [B] -> RAW literal
; 1 + OM + Offset + MatchLen
;
; The OM bits are precalculated and "optimally selected" offset and
; matchlen bit vector lengths. OM bits are encoded as 4 bits pairs
; at the end of file. There are 16 OM pairs thus 8 octets are used
; for them in each file. One OM octet is:
; oommoomm where
;
; oo 00 -> offset of 5 bits Base 1 + [5]
; 01 -> offset 0f 8 bits Base 33 + [8]
; 10 -> offset of 11 bits Base 289 + [11]
; 11 -> offset of 14 bits Base 2337 + [14]
;
; mm 00 -> matchlen of 1 bit Base 2 + [1]
; 01 -> matchlen of 3 bits Base 4 + [3]
; 10 -> matchlen of 5 bits Base 12 + [5]
; 11 -> matchlen of 7 bits Base 44 + [7]
;
; In the compressed bit stream OMs are indexed as:
;
; 100 -> OM index 0
; 101 -> OM index 1
; 1100 -> ..
; 1101
; 11100
; 11101
; 111100
; 111101
; 1111100
; 1111101
; 11111100
; 11111101
; 111111100
; 111111101
; 111111110
; 111111111 -> OM index 15
;
; The actul lengths OM index points at are precalculated before
; decompression into a table.
;
; Encoding of bit tags in the file:
; - bit buffer (hold in A register) is stored in octet boundary
; - literal run length is stored in an octet boundary
;
; Offsets are encoded as:
;
; length 5 -> [5]
; length 8 -> [B]
; length 11 -> [B] + [3]
; length 14 -> [B] + [6]
;
; The compressed file layout is roughly the following:
;
; [data] + [optional 2 octets inplace length] + [2 octets original length] + [8 OM octets]
;
INPLACE equ 1 ; MUST be 1 if the file was crunched with --inplace
org $8000
main:
;ld de,$4000
ld de,data
ld hl,dataend
ld b,$7f
di
exx
push hl
exx
call decompress
exx
pop hl
exx
ei
ret
;
; DE = destination
; HL = end of compressed data
; B = ptr to 256 octets aligned memory area for 32 octets
;
; Uses:
; A,BC,DE,HL,IX
; A',BC',DE',HL,
;
; On return AF or AF' is selected.
;
;
decompress:
push de
ld c,32
createomloop:
dec hl
createomloop_nodec:
ld a,(hl)
;
; 0 1
; A = mmoo|mmoo
;
and 00000011b
ld e,a
add a,a
add a,e
add a,5
dec c
ld (bc),a ; A = oo*3 + 5 -> offset bits
;
ld a,00001100b
and (hl)
rrca
inc a
dec c
ld (bc),a ; A = mm*2 + 1
;
IF 0
ld a,00110000b
and (hl)
rrca
rrca
rrca
ld e,a
rrca
add a,e
add a,5
dec c
ld (bc),a ; A = oo*3 +5
ld a,11000000b
and (hl)
rlca
rlca
rlca ; Clears C-flag
inc a
dec c
ld (bc),a
ELSE
rrd
ld a,00000011b
and c
jr nz, createomloop_nodec
xor c
ENDIF
jr nz,createomloop
;
;dec c
push bc
pop ix
dec hl
ld b,(hl)
dec hl
ld c,(hl)
;
ex (sp),hl ; HL = destination
; (sp) = end of compressed data
add hl,bc ; HL = end of destination
ex (sp),hl ; HL = end of compressed data
; (sp) = end of destination
; inplace length
IF INPLACE
dec hl
ld b,(hl)
dec hl
ld c,(hl) ; inplace "original size"
ENDIF
pop de ; DE = end of destination
;
; HL = end of compressed data
; DE = end of destination
; BC = original size
; IX = pointer to OM table (32 octets)
;
dec hl
ld a,(hl)
dec hl
dec de
jr decompressmain
decompressliteral:
;
; tag 0 + [8]
;
ldd
decompressexit:
ret po
decompressmain:
add a,a
jr nz,mainNZ
ld a,(hl)
adc a,a
dec hl
mainNZ:
jr nc,decompressliteral
;
decompresstag:
exx
push ix
pop hl
;
ld b,7 ;;
getomtag:
;inc l
add a,a
jr nz,omNZ
exx ; 4
ld a,(hl) ; 7
dec hl ; 6
exx ; 4 -> 21 (4 octets)
adc a,a
omNZ:
jr nc,omtagend
inc l
djnz getomtag
;inc l
omtagend:
add a,a
jr nz,omNZ2
exx
ld a,(hl)
dec hl
exx
adc a,a
omNZ2:
rl l
sla l ; Clears C-flag
ld c,(hl) ; C = 0000mmmm
inc l
ld b,(hl) ; B = 0000oooo
sbc hl,hl ; HL = 0, clears C-flag
ex af,af'
ld a,b
;
ld de,0+1
sub 8
jr c,ooStart1
; and delete 8 from the bits to input..
; make sure nothing changes flags now..
ld e,32+1
ld b,a
; need to fetch a full octet into L
exx
ld a,(hl)
dec hl
exx
ld l,a
jr z,ooDone
bit 0,b
jr nz,ooStart
ld d,00001000b
ooStart:
inc d
ooStart1:
ex af,af'
;
ooLoop:
add a,a
jr nz,ooNZ3
exx
ld a,(hl)
dec hl
exx
adc a,a
ooNZ3:
adc hl,hl
djnz ooLoop
db $fe ; CP n
ooDone:
ex af,af'
add hl,de
push hl
;
; HL = inputbits + base
; Now extract macthlen
;
ld e,b ; E = 0
ld b,c ; B = num of bits
;
; 1 -> 2 + [1] 00000010 + 0000000x
; 3 -> 4 + [3] 00000100 + 00000xxx
; 5 -> 12 + [5] 00001100 + 000xxxxx
; 7 -> 44 + [7] 00101100 + 0xxxxxxx
;
ld l,01010101b
getmatchlen:
sla l ; add hl,hl would be shorter but slower
;add hl,hl
mmX:
add a,a
jr nz,mmNZ
exx
ld a,(hl)
dec hl
exx
adc a,a
mmNZ:
rl e
djnz getmatchlen
ex af,af'
ld a,10101011b ; Adds base-1
xor l
add a,e
;
exx
ex (sp),hl
add hl,de
mmCopy:
ldd
dec a
jr nz,mmCopy
ldd
pop hl
ret po
ex af,af'
jr decompressmain
data:
incbin "tst.pac"
;
;
dataend:
END main
/* vim: set tabstop=4:softtabstop=4:shiftwidth=4:noexpandtab */
|
/*
* Copyright (c) Contributors to the Open 3D Engine Project. For complete copyright and license terms please see the LICENSE at the root of this distribution.
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*
*/
#include <AzCore/UnitTest/TestTypes.h>
#include <AzCore/Component/ComponentApplication.h>
#include <Atom/Feature/Utils/IndexableList.h>
#include <AzCore/Memory/SystemAllocator.h>
#include <gtest/gtest.h>
#include <AzCore/Math/Random.h>
#include <AzCore/UnitTest/TestTypes.h>
namespace UnitTest
{
using namespace AZ;
using namespace AZ::Render;
class IndexableListTests
: public UnitTest::AllocatorsTestFixture
{
public:
void SetUp() override
{
UnitTest::AllocatorsTestFixture::SetUp();
}
void TearDown() override
{
UnitTest::AllocatorsTestFixture::TearDown();
}
};
TEST_F(IndexableListTests, TestBasics)
{
IndexableList<float> container;
EXPECT_EQ(0, container.size());
EXPECT_EQ(0, container.capacity());
EXPECT_EQ(-1, container.begin());
}
TEST_F(IndexableListTests, TestReserveFromZero)
{
IndexableList<float> container;
container.reserve(1);
EXPECT_LE(1, container.capacity());
EXPECT_EQ(0, container.size());
EXPECT_EQ(-1, container.begin());
}
TEST_F(IndexableListTests, TestPushFront)
{
const float valueToInsert = 123.25f;
IndexableList<float> container;
int position = container.push_front(valueToInsert);
EXPECT_EQ(1, container.size());
EXPECT_EQ(valueToInsert, container[position]);
}
TEST_F(IndexableListTests, TestErase)
{
const float valueToInsert = 123.25f;
IndexableList<float> container;
int position = container.push_front(valueToInsert);
container.erase(position);
EXPECT_EQ(0, container.size());
}
TEST_F(IndexableListTests, TestBegin)
{
const int testValue = 123;
IndexableList<int> container;
container.push_front(testValue);
int listHead = container.begin();
EXPECT_EQ(testValue, container[listHead]);
}
TEST_F(IndexableListTests, TestNextOnce)
{
const int testValue0 = 123;
const int testValue1 = 456;
IndexableList<int> container;
container.push_front(testValue0);
container.push_front(testValue1);
int iterator = container.begin();
iterator = container.next(iterator);
EXPECT_EQ(testValue0, container[iterator]);
}
TEST_F(IndexableListTests, TestNextMultiple)
{
IndexableList<int> container;
container.push_front(0);
container.push_front(1);
int element2 = container.push_front(2);
container.push_front(3);
container.erase(element2);
int numItemsIteratedThrough = 0;
int iterator = container.begin();
while (iterator != -1)
{
iterator = container.next(iterator);
numItemsIteratedThrough++;
}
EXPECT_EQ(numItemsIteratedThrough, container.size());
}
TEST_F(IndexableListTests, TestMultipleReserve)
{
const int testValue0 = -9;
const int testValue1 = 65;
const int testValue2 = 32;
IndexableList<int> container;
container.reserve(2);
int element0 = container.push_front(testValue0);
container.reserve(4);
int element1 = container.push_front(testValue1);
container.reserve(6);
int element2 = container.push_front(testValue2);
EXPECT_LE(6, container.capacity());
EXPECT_EQ(3, container.size());
EXPECT_EQ(testValue0, container[element0]);
EXPECT_EQ(testValue1, container[element1]);
EXPECT_EQ(testValue2, container[element2]);
}
TEST_F(IndexableListTests, TestInsertToMaxThenReserve)
{
const int testValue0 = -9;
const int testValue1 = 65;
const int testValue2 = 32;
const int testValue3 = 0;
const int testValue4 = -1;
const int testValue5 = 2;
IndexableList<int> container;
container.reserve(3);
int element0 = container.push_front(testValue0);
int element1 = container.push_front(testValue1);
int element2 = container.push_front(testValue2);
container.reserve(6);
int element3 = container.push_front(testValue3);
int element4 = container.push_front(testValue4);
int element5 = container.push_front(testValue5);
EXPECT_EQ(testValue0, container[element0]);
EXPECT_EQ(testValue1, container[element1]);
EXPECT_EQ(testValue2, container[element2]);
EXPECT_EQ(testValue3, container[element3]);
EXPECT_EQ(testValue4, container[element4]);
EXPECT_EQ(testValue5, container[element5]);
}
TEST_F(IndexableListTests, TestHolesInList)
{
const int testValue0 = -9;
const int testValue1 = 65;
const int testValue2 = 32;
const int testValue3 = 0;
const int testValue4 = -1;
const int testValue5 = 2;
IndexableList<int> container;
int element0 = container.push_front(testValue0);
int element1 = container.push_front(testValue1);
int element2 = container.push_front(testValue2);
container.erase(element1);
int element3 = container.push_front(testValue3);
int element4 = container.push_front(testValue4);
int element5 = container.push_front(testValue5);
container.erase(element4);
EXPECT_EQ(4, container.size());
EXPECT_EQ(testValue0, container[element0]);
EXPECT_EQ(testValue2, container[element2]);
EXPECT_EQ(testValue3, container[element3]);
EXPECT_EQ(testValue5, container[element5]);
}
TEST_F(IndexableListTests, TestArraySize)
{
const int testValue0 = 5;
IndexableList<int> container;
int element0 = container.push_front(testValue0);
container.erase(element0);
EXPECT_LE(container.size(), container.array_size());
EXPECT_LE(1, container.array_size());
}
TEST_F(IndexableListTests, ClearTest)
{
const int testValue = 5;
IndexableList<int> container;
container.push_front(testValue);
EXPECT_EQ(1, container.size());
container.clear();
EXPECT_EQ(0, container.size());
EXPECT_EQ(-1, container.begin());
}
}
|
; A092037: A092255 mod 3.
; Submitted by Christian Krause
; 1,1,0,1,2,0,0,0,0,1,2,0,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,1,2,0,2,2,0,0,0,0,2,2,0,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,2,0,2,2,0,0,0,0,2,2,0,2,2,0,0,0,0,0
seq $0,151668 ; G.f.: Product_{k>=0} (1 + 2*x^(3^k)).
sub $0,2
mod $0,4
div $0,2
add $0,1
|
SECTION FRAGMENT "Frag", ROM0/*[1]*/
db $40
SECTION "Word", ROM0/*[6]*/
dw $78d5
SECTION FRAGMENT "Frag", ROM0/*[2]*/,ALIGN[1]
db $2e
SECTION FRAGMENT "Frag", ROM0/*[3]*/
db $1f
SECTION "Byte", ROM0/*[0]*/
db $44
SECTION FRAGMENT "Frag", ROM0/*[4]*/
db $7b
align 2 ; Uh oh
|
// vim: ts=4:sw=4
/**********************************************************************************
* Project: HistFitter - A ROOT-based package for statistical data analysis *
* Package: HistFitter *
* Namespace: Util *
* *
* Description: *
* Implementation (see header for description) *
* *
* Authors: *
* HistFitter group, CERN, Geneva, Switzerland *
* Lorenzo Moneta, CERN, Geneva <Lorenzo.Moneta@cern.h> *
* See: FitPdf() *
* Wouter Verkerke, Nikhef, Amsterdam <verkerke@nikhef.nl> *
* See: GetPropagatedError() *
* *
* See corresponding .h file for author and license information *
**********************************************************************************/
#include <memory>
#include "Utils.h"
#include "ConfigMgr.h"
#include "TMsgLogger.h"
#include "ChannelStyle.h"
#include "HistogramPlotter.h"
#include "TMap.h"
#include "TString.h"
#include "TObjString.h"
#include "TObjArray.h"
#include "RooArgSet.h"
#include "TIterator.h"
#include "RooAbsReal.h"
#include "RooAbsPdf.h"
#include "RooAbsArg.h"
#include "RooFitResult.h"
#include "RooRealVar.h"
#include "RooWorkspace.h"
#include "RooSimultaneous.h"
#include "RooProdPdf.h"
#include "RooAddPdf.h"
#include "RooDataSet.h"
#include "RooPlot.h"
#include "RooProduct.h"
#include "RooMCStudy.h"
#include "Roo1DTable.h"
#include "RooCategory.h"
#include "RooRealSumPdf.h"
#include "RooGaussian.h"
#include "RooCurve.h"
#include "RooHist.h"
#include "RooMinimizer.h"
#include "RooConstVar.h"
#include "RooNumIntConfig.h"
#include "RooMinuit.h"
#include "RooFormulaVar.h"
#include "RooStats/ModelConfig.h"
#include "RooStats/ProfileLikelihoodTestStat.h"
#include "RooStats/ProfileLikelihoodCalculator.h"
#include "RooStats/LikelihoodInterval.h"
#include "RooStats/ToyMCSampler.h"
#include "RooStats/SamplingDistPlot.h"
#include "RooStats/HypoTestInverterResult.h"
#include "RooStats/HypoTestResult.h"
#include "RooStats/RooStatsUtils.h"
#include "RooStats/HistFactory/PiecewiseInterpolation.h"
#include "TAxis.h"
#include "TArrow.h"
#include "TF1.h"
#include "TH1F.h"
#include "TH2D.h"
#include "TTree.h"
#include "TBranch.h"
#include "TGraph2D.h"
#include "TGraphAsymmErrors.h"
#include "TPad.h"
#include "TGaxis.h"
#include "TStyle.h"
#include "TVectorD.h"
#include "TFile.h"
#include "TLine.h"
#include "TLatex.h"
#include "TCanvas.h"
#include "TLegend.h"
#include "TLegendEntry.h"
#include "TROOT.h"
#include <iostream>
#include <fstream>
#include <vector>
using namespace std;
using namespace RooFit;
using namespace RooStats;
namespace Util {
static TMsgLogger Logger("Util");
bool deactivateBinnedLikelihood = false;
}
//_____________________________________________________________________________
double Util::looseToTightVal(const TString& reg, TMap* map){
double nLMT=((TObjString*)map->GetValue("DATA_DATA_"+reg+"lmt"))->GetString().Atof();
double nTopTight=((TObjString*)map->GetValue("MC_tt_"+reg))->GetString().Atof();
double nWTight=((TObjString*)map->GetValue("MC_WZ_"+reg))->GetString().Atof();
double LtoTeffFake=((TObjString*)map->GetValue("LtoTeffFake_QCD"+reg+"_"+reg+"lmt"))->GetString().Atof();
double LtoTeffReal_tt=((TObjString*)map->GetValue("LtoTeffReal_tt_"+reg+"lmt"))->GetString().Atof();
double LtoTeffReal_W=((TObjString*)map->GetValue("LtoTeffReal_WZ_"+reg+"lmt"))->GetString().Atof();
double fBTagTop=((TObjString*)map->GetValue("btag_sep_tt"))->GetString().Atof();
double fBTagWZ=((TObjString*)map->GetValue("btag_sep_WZ"))->GetString().Atof();
double nTop=nTopTight * (LtoTeffReal_tt-1.0);
double nWZ=nWTight * (LtoTeffReal_W-1.0);
if(reg=="TR"){
nTop=nTop*fBTagTop;
nWZ=nWZ*fBTagWZ;
}
else if(reg=="WR"){
nTop=nTop*(1.0-fBTagTop);
nWZ=nWZ*(1.0-fBTagWZ);
}
double val=(nLMT-nTop-nWZ)/LtoTeffFake;
return val;
}
//_____________________________________________________________________________
double Util::looseToTightErr(const TString& reg, TMap* map){
double nLMT=((TObjString*)map->GetValue("DATA_DATA_"+reg+"lmt"))->GetString().Atof();
double LtoTeffFake=((TObjString*)map->GetValue("LtoTeffFake_QCD"+reg+"_"+reg+"lmt"))->GetString().Atof();
double err=sqrt(nLMT)/LtoTeffFake; //incomplete and temporary
return err;
}
//_____________________________________________________________________________
double Util::getNonQcdVal(const TString& proc, const TString& reg, TMap* map,const TString& opt){
TString prefix="MC_";
if(proc=="DATA"){ prefix="DATA_"; }
double val=((TObjString*)map->GetValue(prefix+proc+opt+"_"+reg))->GetString().Atof();
//exception #1: WTR, overwrite val
if((reg=="WR" || reg=="TR") && proc!="DATA"){
double mcVal=val;
double fBTag=((TObjString*)map->GetValue("btag_sep_"+proc))->GetString().Atof();
if(reg=="TR"){ val=mcVal*fBTag; }
else if(reg=="WR"){ val=mcVal*(1.0-fBTag); }
}
return val;
}
//_____________________________________________________________________________
void Util::GenerateFitAndPlot(TString fcName, TString anaName, Bool_t drawBeforeFit, Bool_t drawAfterFit, Bool_t plotCorrelationMatrix,
Bool_t plotSeparateComponents, Bool_t plotNLL, Bool_t minos, TString minosPars,
Bool_t doFixParameters, TString fixedPars, bool ReduceCorrMatrix, bool noFit, bool plotInterpolation ){
ConfigMgr* mgr = ConfigMgr::getInstance();
FitConfig* fc = mgr->getFitConfig(fcName);
Logger << kINFO << " GenerateFitAndPlot for FitConfig = " << fc->m_name << GEndl;
Logger << kINFO << " analysisName = " << anaName << GEndl;
Logger << kINFO << " drawBeforeFit = " << drawBeforeFit << GEndl;
Logger << kINFO << " drawAfterFit = " << drawAfterFit << GEndl;
Logger << kINFO << " plotCorrelationMatrix = " << plotCorrelationMatrix << GEndl;
Logger << kINFO << " plotSeparateComponents = " << plotSeparateComponents << GEndl;
Logger << kINFO << " plotNLL = " << plotNLL << GEndl;
Logger << kINFO << " minos = " << minos << GEndl;
Logger << kINFO << " minosPars = " << minosPars << GEndl;
Logger << kINFO << " doFixParameters = " << doFixParameters << GEndl;
Logger << kINFO << " fixedPars = " << fixedPars << GEndl;
Logger << kINFO << " ReduceCorrMatrix = " << ReduceCorrMatrix << GEndl;
Logger << kINFO << " noFit = " << noFit << GEndl;
Logger << kINFO << " plotInterpolation = " << plotInterpolation << GEndl;
auto inputFilename = fc->m_inputWorkspaceFileName;
Logger << kINFO << " Will read workspace from filename " << inputFilename << GEndl;
if(noFit) {
// TOOD: might not work when using ToyMC
inputFilename.ReplaceAll(".root","_afterFit.root");
Logger << kINFO << " Updated input filename to " << inputFilename << GEndl;
//if (suffix != "") { //comes from ToyMC::GetName()
//TString suff = "_" + suffix + ".root";
//outFileName.ReplaceAll(".root",suff);
//}
}
RooWorkspace* w = GetWorkspaceFromFile(inputFilename, "combined");
if(w==NULL){
Logger << kWARNING << " RooWorkspace('combined') does not exist, trying workspace('w')" << GEndl;
w = GetWorkspaceFromFile(inputFilename, "w");
if(w) {
Logger << kWARNING << "Managed to find workspace 'w'!" << GEndl;
}
}
if(w==NULL){
Logger << kERROR << " Cannot find RooWorkspace, quitting " << GEndl;
return;
}
Util::SetInterpolationCode(w,4);
if (not noFit ) {
// only modify the workspace when actually fitting
SaveInitialSnapshot(w);
}
TString plotChannels = "ALL";
// fit only in CRs and SRs, not in VR
TString fitChannels = "";
for(unsigned int i=0; i <fc->m_bkgConstrainChannels.size(); i++){
if (fitChannels.Length() > 0) fitChannels += ",";
fitChannels += fc->m_bkgConstrainChannels[i];
}
for(unsigned int i=0; i <fc->m_signalChannels.size(); i++){
if (fitChannels.Length() > 0) fitChannels += ",";
fitChannels += fc->m_signalChannels[i];
}
//hack to be fixed at HistFactory level (check again with ROOT 5.34)
// Bool_t lumiConst = kTRUE;
//if (fc->m_signalChannels.size() > 0)
Bool_t lumiConst = kFALSE;
// fit toy MC if specified. When left None, data is fit by default
RooAbsData* toyMC = NULL;
if(not noFit) {
if( mgr->m_seed != 0 && !mgr->m_useAsimovSet){
// generate a toy dataset
Logger << kINFO << " Util::GenerateFitAndPlot() : generating toy MC set for fitting and plotting. Seed =" << mgr->m_seed << GEndl;
toyMC = GetToyMC(); // this generates one toy dataset
} else if (mgr->m_useAsimovSet && mgr->m_seed == 0 ){
Logger << kINFO << " Util::GenerateFitAndPlot() : using Asimov set for fitting and plotting." << GEndl;
toyMC = GetAsimovSet(w); // this returns the asimov set
} else {
Logger << kINFO << " Util::GenerateFitAndPlot() : using data for fitting and plotting." << GEndl;
}
}
// set Errors of all parameters to 'natural' values before plotting/fitting
resetAllErrors(w);
// get a list of all floating parameters for all regions
RooAbsPdf* simPdf = w->pdf("simPdf");
ModelConfig* mc = GetModelConfig(w);
const RooArgSet* obsSet = mc->GetObservables();
RooArgList floatPars = getFloatParList(*simPdf, *obsSet);
// create an RooExpandedFitResult encompassing all the
// regions/parameters & save it to workspace
RooExpandedFitResult* expResultBefore;
if(not noFit) {
expResultBefore = new RooExpandedFitResult(floatPars);
ImportInWorkspace(w, expResultBefore, "RooExpandedFitResult_beforeFit");
} else {
// retrieve from the workspace
expResultBefore = static_cast<RooExpandedFitResult*>( w->genobj("RooExpandedFitResult_beforeFit") );
LoadSnapshotInWorkspace(w, "snapshot_paramsVals_RooExpandedFitResult_beforeFit");
}
// fire up a plotter
// plot before fit
if (drawBeforeFit) {
HistogramPlotter h(w, fc->m_name);
h.setAnalysisName(anaName);
h.setPlotRegions(plotChannels);
h.setPlotComponents(true);
h.setPlotSeparateComponents(false);
h.setOutputPrefix("beforeFit");
h.setFitResult(expResultBefore);
h.setInputData(toyMC);
h.Initialize();
h.PlotRegions();
//h.saveHistograms();
}
// perform fit
RooFitResult* result = nullptr;
RooExpandedFitResult* expResultAfter = nullptr;
if(not noFit) {
//fit of all regions
result = FitPdf(w, fitChannels, lumiConst, toyMC, "", minos, minosPars, doFixParameters, fixedPars);
if (result == NULL) {
Logger << kERROR << "PlotNLL(): running FitPdf() failed!" << GEndl;
return;
}
// create an RooExpandedFitResult encompassing all the regions/parameters
// with the result & save it to workspace
expResultAfter = new RooExpandedFitResult(result, floatPars);
ImportInWorkspace(w, expResultAfter, "RooExpandedFitResult_afterFit");
} else {
// load back the fit result
expResultAfter = static_cast<RooExpandedFitResult*>( w->genobj("RooExpandedFitResult_afterFit") );
LoadSnapshotInWorkspace(w, "snapshot_paramsVals_RooExpandedFitResult_afterFit");
}
// plot after fit
if (drawAfterFit) {
HistogramPlotter h(w, fc->m_name);
h.setAnalysisName(anaName);
h.setPlotRegions(plotChannels);
h.setPlotComponents(true);
h.setPlotSeparateComponents(false);
h.setOutputPrefix("afterFit");
h.setFitResult(expResultAfter);
h.setInputData(toyMC);
// plot each component of each region separately with propagated
// error after fit (interesting for debugging)
if(plotSeparateComponents) {
h.setPlotSeparateComponents(true);
}
h.Initialize();
h.PlotRegions();
}
//plot correlation matrix for result
if(plotCorrelationMatrix) {
//PlotCorrelationMatrix(result, anaName, ReduceCorrMatrix);
PlotCorrelationMatrix(expResultAfter, anaName, ReduceCorrMatrix);
}
// plot likelihood
Bool_t plotPLL = minos;
if(plotNLL) {
PlotNLL(w, expResultAfter, plotPLL, anaName, "", toyMC, minosPars, fitChannels, lumiConst);
}
if(not noFit) {
// only write out output workspace if we've run a fit
if (toyMC) {
WriteWorkspace(w, inputFilename, toyMC->GetName());
} else {
WriteWorkspace(w, inputFilename);
}
}
if (result){
result->Print("v");
PlotFitParameters(result,anaName);
}
// plot the interpolation of nuisance parameters
if (plotInterpolation) {
plotInterpolationScheme(w);
}
}
///////////////
//_____________________________________________________________________________
void Util::GeneratePlots(TString filename, TString anaName, Bool_t drawBeforeFit, Bool_t drawAfterFit, Bool_t plotCorrelationMatrix,
Bool_t plotSeparateComponents, Bool_t plotNLL, Bool_t minos, TString minosPars,
Bool_t doFixParameters, TString fixedPars, bool ReduceCorrMatrix){
const bool noFit = true; // we never re-fit an existing afterFit workspace
Logger << kINFO << " GeneratePlots for filename = " << filename << GEndl;
Logger << kINFO << " analysisName = " << anaName << GEndl;
Logger << kINFO << " drawBeforeFit = " << drawBeforeFit << GEndl;
Logger << kINFO << " drawAfterFit = " << drawAfterFit << GEndl;
Logger << kINFO << " plotCorrelationMatrix = " << plotCorrelationMatrix << GEndl;
Logger << kINFO << " plotSeparateComponents = " << plotSeparateComponents << GEndl;
Logger << kINFO << " plotNLL = " << plotNLL << GEndl;
Logger << kINFO << " minos = " << minos << GEndl;
Logger << kINFO << " minosPars = " << minosPars << GEndl;
Logger << kINFO << " doFixParameters = " << doFixParameters << GEndl;
Logger << kINFO << " fixedPars = " << fixedPars << GEndl;
Logger << kINFO << " ReduceCorrMatrix = " << ReduceCorrMatrix << GEndl;
auto inputFilename = filename;
Logger << kINFO << " Will read workspace from filename " << inputFilename << GEndl;
if(noFit) {
// TOOD: might not work when using ToyMC
inputFilename.ReplaceAll(".root","_afterFit.root");
Logger << kINFO << " Updated input filename to " << inputFilename << GEndl;
//if (suffix != "") { //comes from ToyMC::GetName()
//TString suff = "_" + suffix + ".root";
//outFileName.ReplaceAll(".root",suff);
//}
}
RooWorkspace* w = GetWorkspaceFromFile(inputFilename, "combined");
if(w==NULL){
Logger << kWARNING << " RooWorkspace('combined') does not exist, trying workspace('w')" << GEndl;
w = GetWorkspaceFromFile(inputFilename, "w");
if(w) {
Logger << kWARNING << "Managed to find workspace 'w'!" << GEndl;
}
}
if(w==NULL){
Logger << kERROR << " Cannot find RooWorkspace, quitting " << GEndl;
return;
}
Util::SetInterpolationCode(w,4);
if (not noFit ) {
// only modify the workspace when actually fitting
SaveInitialSnapshot(w);
}
TString plotChannels = "ALL";
//// fit only in CRs and SRs, not in VR
//TString fitChannels = "";
//for(unsigned int i=0; i <fc->m_bkgConstrainChannels.size(); i++){
//if (fitChannels.Length() > 0) fitChannels += ",";
//fitChannels += fc->m_bkgConstrainChannels[i];
//}
//for(unsigned int i=0; i <fc->m_signalChannels.size(); i++){
//if (fitChannels.Length() > 0) fitChannels += ",";
//fitChannels += fc->m_signalChannels[i];
//}
//hack to be fixed at HistFactory level (check again with ROOT 5.34)
// Bool_t lumiConst = kTRUE;
//if (fc->m_signalChannels.size() > 0)
Bool_t lumiConst = kFALSE;
// fit toy MC if specified. When left None, data is fit by default
RooAbsData* toyMC = NULL;
/* if(not noFit) {*/
//if( mgr->m_seed != 0 && !mgr->m_useAsimovSet){
//// generate a toy dataset
//Logger << kINFO << " Util::GenerateFitAndPlot() : generating toy MC set for fitting and plotting. Seed =" << mgr->m_seed << GEndl;
//toyMC = GetToyMC(); // this generates one toy dataset
//} else if (mgr->m_useAsimovSet && mgr->m_seed == 0 ){
//Logger << kINFO << " Util::GenerateFitAndPlot() : using Asimov set for fitting and plotting." << GEndl;
//toyMC = GetAsimovSet(w); // this returns the asimov set
//} else {
//Logger << kINFO << " Util::GenerateFitAndPlot() : using data for fitting and plotting." << GEndl;
//}
/*}*/
// set Errors of all parameters to 'natural' values before plotting/fitting
resetAllErrors(w);
// get a list of all floating parameters for all regions
RooAbsPdf* simPdf = w->pdf("simPdf");
ModelConfig* mc = GetModelConfig(w);
const RooArgSet* obsSet = mc->GetObservables();
RooArgList floatPars = getFloatParList(*simPdf, *obsSet);
// create an RooExpandedFitResult encompassing all the
// regions/parameters & save it to workspace
RooExpandedFitResult* expResultBefore;
if(not noFit) {
expResultBefore = new RooExpandedFitResult(floatPars);
ImportInWorkspace(w, expResultBefore, "RooExpandedFitResult_beforeFit");
} else {
// retrieve from the workspace
expResultBefore = static_cast<RooExpandedFitResult*>( w->genobj("RooExpandedFitResult_beforeFit") );
LoadSnapshotInWorkspace(w, "snapshot_paramsVals_RooExpandedFitResult_beforeFit");
}
// plot before fit
if (drawBeforeFit)
PlotPdfWithComponents(w, "beforeFit", anaName, plotChannels, "beforeFit", expResultBefore, toyMC);
RooFitResult* result = nullptr;
RooExpandedFitResult* expResultAfter = nullptr;
//if(not noFit) {
////fit of all regions
//result = FitPdf(w, fitChannels, lumiConst, toyMC, "", minos, minosPars, doFixParameters, fixedPars);
//if (result == NULL) {
//Logger << kERROR << "PlotNLL(): running FitPdf() failed!" << GEndl;
//return;
//}
//// create an RooExpandedFitResult encompassing all the regions/parameters
//// with the result & save it to workspace
//expResultAfter = new RooExpandedFitResult(result, floatPars);
//ImportInWorkspace(w, expResultAfter, "RooExpandedFitResult_afterFit");
//} else {
// load back the fit result
expResultAfter = static_cast<RooExpandedFitResult*>( w->genobj("RooExpandedFitResult_afterFit") );
LoadSnapshotInWorkspace(w, "snapshot_paramsVals_RooExpandedFitResult_afterFit");
//}
// plot after fit
if (drawAfterFit) {
PlotPdfWithComponents(w, "afterFit", anaName, plotChannels, "afterFit", expResultAfter, toyMC);
}
// plot each component of each region separately with propagated
// error after fit (interesting for debugging)
if(plotSeparateComponents) {
//PlotSeparateComponents(w, fc->m_name, anaName, plotChannels, "afterFit", result, toyMC);
PlotSeparateComponents(w, "afterFit_separateComponents", anaName, plotChannels, "afterFit", expResultAfter, toyMC);
}
//plot correlation matrix for result
if(plotCorrelationMatrix) {
//PlotCorrelationMatrix(result, anaName, ReduceCorrMatrix);
PlotCorrelationMatrix(expResultAfter, anaName, ReduceCorrMatrix);
}
// plot likelihood
Bool_t plotPLL = minos;
if(plotNLL) {
//PlotNLL(w, expResultAfter, plotPLL, anaName, "", toyMC, minosPars, fitChannels, lumiConst);
PlotNLL(w, expResultAfter, plotPLL, anaName, "", toyMC, minosPars, "ALL", lumiConst);
}
if(not noFit) {
// only write out output workspace if we've run a fit
if (toyMC) {
WriteWorkspace(w, inputFilename, toyMC->GetName());
} else {
WriteWorkspace(w, inputFilename);
}
}
if (result)
result->Print("v");
}
//_____________________________________________________________________________
void Util::SaveInitialSnapshot(RooWorkspace* w){
if(w==NULL){
Logger << kINFO << "Util::SaveInitialSnapshot(): workspace does not exist" << GEndl;
return;
}
w->SetName("w");
w->SetTitle("w");
// save snapshot before any fit has been done
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
if(pdf==NULL){
pdf = (RooSimultaneous*) w->pdf("combPdf");
}
if(pdf==NULL){
Logger << kWARNING << "Util::SaveInitialSnapshot(): not saving the initial snapshot as cannot find pdf (simPdf or combPdf) in workspace" << GEndl;
return;
}
RooAbsData* data = (RooAbsData*) w->data("obsData");
RooArgSet* params = (RooArgSet*) pdf->getParameters(*data) ;
if(!w->loadSnapshot("snapshot_paramsVals_initial")) {
w->saveSnapshot("snapshot_paramsVals_initial",*params);
} else {
Logger << kWARNING << "Snapshot 'snapshot_paramsVals_initial' already exists in workspace, will not overwrite it" << GEndl;
}
// Put workspace in the global directory
gDirectory->Add(w);
}
//_____________________________________________________________________________
void Util::LoadSnapshotInWorkspace(RooWorkspace* w,TString snapshot){
Bool_t loaded = w->loadSnapshot(snapshot);
if (loaded){
Logger << kINFO << "workspace loaded" << GEndl;
return;
} else {
Logger << kWARNING << "Util.LoadSnapshotInWorkspace() did not find snapshot named " << snapshot << ", check your workspace file" << GEndl;
}
return;
}
//_____________________________________________________________________________
void Util::WriteWorkspace(RooWorkspace* w, TString outFileName, TString suffix){
if(w==NULL){
Logger << kERROR << "Workspace not found, not writing workspace to file" << GEndl;
return;
}
outFileName.ReplaceAll(".root","_afterFit.root");
if (suffix != "") {
TString suff = "_" + suffix + ".root";
outFileName.ReplaceAll(".root",suff);
}
w->SetName("w");
w->SetTitle("w");
w->writeToFile(outFileName.Data());
Logger << kINFO << " Util::WriteWorkspace(): have written workspace to file " << outFileName << GEndl;
return;
}
/*
* The FitPdf() function is (partially) taken from the function
* RooStats::ProfileLikelihoodTestStat::GetMinNLL()
* See: http://root.cern.ch/root/html534/src/RooStats__ProfileLikelihoodTestStat.cxx.html
* ((http://root.cern.ch/drupal/content/license))
*/
//_____________________________________________________________________________
RooFitResult* Util::FitPdf( RooWorkspace* w, TString fitRegions, Bool_t lumiConst, RooAbsData* inputData, TString suffix, Bool_t minos, TString minosPars, Bool_t doFixParameters, TString fixedPars)
{
Logger << kINFO << " ------ Starting FitPdf with parameters: fitRegions = " << fitRegions << GEndl;
Logger << kINFO << " inputData = " << inputData << " suffix = " << suffix << " minos = " << minos << " minosPars = " << minosPars << " doFixParameters = " << doFixParameters << " fixedPars = " << fixedPars << GEndl;
// enable internal likelihood offsetting for enhanced numeric precision
RooStats::UseNLLOffset(true);
RooMsgService::instance().getStream(1).removeTopic(NumIntegration);
if(!w){
Logger << kERROR << "Workspace not found, no fitting performed" << GEndl;
return NULL;
}
if(!deactivateBinnedLikelihood) {
RooFIter iter = w->components().fwdIterator();
RooAbsArg* arg;
while ((arg = iter.next())) {
if (arg->IsA() == RooRealSumPdf::Class()) {
arg->setAttribute("BinnedLikelihood");
cout << "Activating binned likelihood attribute for " << arg->GetName() << endl;
}
}
}
RooSimultaneous* pdf = static_cast<RooSimultaneous*>(w->pdf("simPdf"));
RooAbsData* data = ( inputData!=0 ? inputData : static_cast<RooAbsData*>(w->data("obsData")) );
if(!data) {
Logger << kFATAL << "Can't find RooAbsData 'data' in workspace. Are you attempting to run a blinded fit but did you not add a (dummy) data sample?" << GEndl;
return NULL;
}
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
if(!regionCat) {
Logger << kERROR << "Can't find RooCategory 'channelCat' in workspace" << GEndl;
return NULL;
}
RooAbsCategory* absRegionCat = static_cast<RooAbsCategory*>(regionCat);
if(!absRegionCat) {
Logger << kERROR << "Can't cast RooAbsCategory 'channelCat' from workspace" << GEndl;
return NULL;
}
Logger << kINFO << "Will dump channelCat as RooAbsCategory now:" << GEndl;
absRegionCat->Print("v");
//auto table = data->table(*((RooAbsCategory*)regionCat));
auto table = data->table(*absRegionCat);
if(!table) {
Logger << kERROR << "data->table(channelCat) returned NULL" << GEndl;
return NULL;
}
Logger << kINFO << "Will dump table for channelCat now:" << GEndl;
table->Print("v");
if (lumiConst) {
RooRealVar* lumi = (RooRealVar*) w->var("Lumi");
if (lumi!=NULL) lumi->setConstant(lumiConst);
}
//fixing parameters to certain values
if (doFixParameters && fixedPars != "") {
std::vector<TString> fixedParsVector = Tokens(fixedPars,",");
for (unsigned int j=0; j<fixedParsVector.size(); j++) {
std::vector<TString> fixedParsPair = Tokens(fixedParsVector[j],":");
if (fixedParsPair.size() != 2) {
Logger << kERROR << " Util::FitPdf() fixing parameters to constant: wrong arguments given: " << fixedParsVector[j] << GEndl;
Logger << kERROR << " Util::FitPdf() Ignore this and continue." << GEndl;
continue;
}
RooRealVar* var = (RooRealVar*) w->var(fixedParsPair[0]);
if(var==NULL) Logger << kWARNING << " Util::FitPdf() could not find parameter(" << fixedParsPair[0] << ") in workspace while trying to fix this parameter" << GEndl;
else {
Logger << kINFO << " Util::FitPdf() Setting parameter " << fixedParsPair[0] << " to constant value " << fixedParsPair[1].Atof() << GEndl;
var->setVal(fixedParsPair[1].Atof());
var->setConstant(kTRUE);
}
}
}
// Construct an empty simultaneous pdf using category regionCat as index
RooSimultaneous* simPdfFitRegions = pdf;
RooDataSet* dataFitRegions = (RooDataSet*) data;
std::vector<TString> fitRegionsVec = GetRegionsVec(fitRegions, regionCat);
unsigned int numFitRegions = fitRegionsVec.size();
std::vector<RooDataSet*> dataVec;
std::vector<RooAbsPdf*> pdfVec;
for(unsigned int iVec=0; iVec<numFitRegions; iVec++){
TString regionCatLabel = fitRegionsVec[iVec];
if( regionCat->setLabel(regionCatLabel,kTRUE)){
Logger << kWARNING << " Label '" << regionCatLabel << "' is not a state of channelCat (see Table) " << GEndl;
} else{
// dataset for each channel/region/category
TString dataCatLabel = Form("channelCat==channelCat::%s",regionCatLabel.Data());
RooDataSet* regionData = (RooDataSet*) data->reduce(dataCatLabel.Data());
dataVec.push_back(regionData);
// pdf for each channel/region/category
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionCatLabel.Data());
pdfVec.push_back(regionPdf);
}
}
if(dataVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN DATASET, NO FIT WILL BE PERFORMED" << GEndl;
return 0;
}
else if(pdfVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN SIMULTANEOUS PDF, NO FIT WILL BE PERFORMED" << GEndl;
return 0;
}
else{
// Construct a simultaneous dataset for all fit regions
dataFitRegions = (RooDataSet*) dataVec[0]->Clone("dataFitRegions");
for(unsigned int jVec=1; jVec<dataVec.size(); jVec++){
dataFitRegions->append(*dataVec[jVec]);
}
// Construct a simultaneous pdf using category regionCat as index
simPdfFitRegions = new RooSimultaneous("simPdfFitRegions","simultaneous pdf only for fit regions",*regionCat) ;
for(unsigned int kVec=0; kVec<pdfVec.size(); kVec++){
simPdfFitRegions->addPdf(*pdfVec[kVec],fitRegionsVec[kVec].Data());
}
}
w->import(*simPdfFitRegions,kTRUE);
gDirectory->Add(simPdfFitRegions);
// find parameters requested for Minos
RooArgSet* minosParams = new RooArgSet();
if(minosPars != "" && minos && minosPars != "all" && minosPars != "ALL"){
std::vector<TString> parsVec = Tokens(minosPars,",");
for(unsigned int i=0; i<parsVec.size();i++){
RooRealVar* var = (RooRealVar*) w->var(parsVec[i]);
if(var==NULL) Logger << kWARNING << " Util::FitPdf() could not find parameter(" << parsVec[i] << ") in workspace while setting up minos" << GEndl;
else{
minosParams->add(*var);
}
}
}
// fit pdf to data
RooFitResult* r = 0;
TString datasetname = data->GetName();
Logger << kINFO << " Utils::FitPdf() using datasetname = " << datasetname << GEndl;
RooAbsPdf* pdf_FR = simPdfFitRegions;
RooDataSet* data_FR = dataFitRegions;
RooArgSet* allParams = pdf_FR->getParameters(data_FR);
RooStats::RemoveConstantParameters(allParams);
RooStats::ModelConfig* mc = Util::GetModelConfig( w );
const RooArgSet* globObs = mc->GetGlobalObservables();
RooAbsReal* nll = (RooNLLVar*) pdf_FR->createNLL(*data_FR, RooFit::GlobalObservables(*globObs), RooFit::Offset(true) );
int minimPrintLevel = 1; //verbose;
RooMinimizer minim(*nll);
int strategy = ROOT::Math::MinimizerOptions::DefaultStrategy();
minim.setStrategy( strategy);
// enable internal likelihood offsetting for enhanced numeric precision
minim.setOffsetting(true);
// use tolerance - but never smaller than 1 (default in RooMinimizer)
double tol = ROOT::Math::MinimizerOptions::DefaultTolerance();
tol = std::max(tol, 1.0); // 1.0 is the minimum value used in RooMinimizer
minim.setEps( tol );
//LM: RooMinimizer.setPrintLevel has +1 offset - so subtruct here -1
minim.setPrintLevel(minimPrintLevel-1);
int status = -1;
minim.optimizeConst(2);
TString minimizer = "Minuit2"; //ROOT::Math::MinimizerOptions::DefaultMinimizerType();
TString algorithm = ROOT::Math::MinimizerOptions::DefaultMinimizerAlgo();
Logger << kINFO << "Util::FitPdf() ........ using " << minimizer << " / " << algorithm << GEndl;
Logger << kINFO << " with strategy " << strategy << " and tolerance " << tol << GEndl;
for (int tries = 1, maxtries = 4; tries <= maxtries; ++tries) {
status = minim.minimize(minimizer, algorithm);
if (status%1000 == 0) { // ignore erros from Improve
break;
} else {
if (tries == 1) {
Logger << kINFO << " ----> Doing a re-scan first" << GEndl;
minim.minimize(minimizer,"Scan");
}
if (tries == 2) {
if (ROOT::Math::MinimizerOptions::DefaultStrategy() == 0 ) {
Logger << kINFO << " ----> trying with strategy = 1" << GEndl;
minim.setStrategy(1);
}
else
tries++; // skip this trial if stratehy is already 1
}
if (tries == 3) {
Logger << kINFO << " ----> trying with improve" << GEndl;
minimizer = "Minuit";
algorithm = "migradimproved";
}
}
}
if (status%100 == 0) { // ignore errors in Hesse or in Improve
// only calculate minos errors if fit with Migrad converged
if(minos && (minosPars == "all" || minosPars == "ALL")){
minim.hesse();
minim.minos();
}
else if(minos && minosPars!="" && minosParams->getSize()>0){
minim.hesse();
minim.minos(*minosParams);
}
else {
minim.hesse();
}
// save fit result
r = minim.save();
}
else {
Logger << kERROR << "FIT FAILED !- return a NaN NLL " << GEndl;
}
if (r!=0) r->Print("v");
TString fitName = data_FR->GetName();
for(unsigned int iVec=0; iVec<fitRegionsVec.size(); iVec++){
if(iVec ==0) fitName += "_fitRegions";
fitName += "_" + fitRegionsVec[iVec];
}
TString resultname = Form("RooFitResult_%s",fitName.Data());
if(suffix!= "") resultname += "_" + suffix;
if (r!=0) {
r->SetName(resultname.Data());
w->import(*r,kTRUE) ;
gDirectory->Add(r);
}
// save snapshot after fit has been done
RooArgSet* params = (RooArgSet*) pdf_FR->getParameters(*data_FR) ;
w->saveSnapshot(Form("snapshot_paramsVals_%s",resultname.Data()),*params);
return r;
}
//_____________________________________________________________________________
void
Util::SetInterpolationCode(RooWorkspace* w, Int_t code)
{
if(w==NULL){
Logger << kERROR << "Workspace is NULL. Return." << GEndl;
return;
}
RooArgSet funcs = w->allFunctions();
TIterator* iter = funcs.createIterator() ;
RooAbsArg* parg(0);
while((parg=(RooAbsArg*)iter->Next())) {
if ( parg->ClassName()!=TString("PiecewiseInterpolation") ) { continue; }
PiecewiseInterpolation* p = (PiecewiseInterpolation*)w->function( parg->GetName() ); // something I can modifiy :)
p->setAllInterpCodes(code);
}
delete iter;
}
//_____________________________________________________________________________
RooAbsData*
Util::GetAsimovSet( RooWorkspace* inputws )
{
RooWorkspace* w(0);
if (inputws!=NULL) { w = inputws; }
else { w = (RooWorkspace*) gDirectory->Get("w"); }
if(w==NULL){
Logger << kERROR << "Workspace not found, no Asimov set found. Return." << GEndl;
return 0;
}
RooAbsData* data = w->data("asimovData");
if (data==NULL) {
Logger << kERROR << "No Asimov set found. Return." << GEndl;
return 0;
}
return data;
}
//_____________________________________________________________________________
RooAbsData*
Util::GetToyMC( RooWorkspace* inputws )
{
RooWorkspace* w(0);
if (inputws!=NULL) { w = inputws; }
else { w = (RooWorkspace*) gDirectory->Get("w"); }
if(w==NULL){
Logger << kERROR << "Workspace not found, no toy dataset generated." << GEndl;
return 0;
}
RooStats::ModelConfig* mc = Util::GetModelConfig( w );
if (mc==NULL) {
Logger << kERROR << "No model config found. Return." << GEndl;
return 0;
}
RooAbsPdf* pdf = mc->GetPdf();
if (pdf==NULL) {
Logger << kERROR << "No pdf found. Return." << GEndl;
return 0;
}
RooAbsData* data = w->data("obsData");
if (data==NULL) {
Logger << kERROR << "No dataset found. Return." << GEndl;
return 0;
}
const RooArgSet* obsSet = mc->GetObservables();
if (obsSet==NULL) {
Logger << kERROR << "No observables found. Return." << GEndl;
return 0;
}
Logger << kINFO << "Util::GetToyMC() : now generating toy MC set with # events : " << data->sumEntries() << GEndl;
RooAbsData* toymc = pdf->generate( *obsSet, RooFit::NumEvents(int(data->sumEntries())), RooFit::AutoBinned(false) );
return toymc;
}
//_____________________________________________________________________________________________________________________________________
vector<TString> Util::GetRegionsVec(TString regions, RooCategory* regionCat){
std::vector<TString> regionsVec;
std::vector<TString> regionsAllVec = TokensALL(regionCat);
std::vector<TString> regionsRequestedVec = Tokens(regions,",");
if(regions=="ALL"){ regionsVec = regionsAllVec;
} else {
for(unsigned int iReg=0; iReg<regionsAllVec.size(); iReg++){
for(unsigned int jReg=0; jReg<regionsRequestedVec.size(); jReg++){
if( regionsAllVec[iReg].EqualTo(regionsRequestedVec[jReg]) ) {
regionsVec.push_back(regionsAllVec[iReg]);
}
}
}
}
return regionsVec;
}
//_____________________________________________________________________________________________________________________________________
void Util::DecomposeWS(const char* infile, const char* wsname, const char* outfile)
{
Logger << kINFO << " ------ Util::DecomposeWS with parameters: infile " << infile << " wsname = " << wsname << " outfile = " << outfile << GEndl;
TString fileName(infile);
if (fileName.IsNull()) {
Logger << kERROR << "Input filename is empty. Exit." << GEndl;
return;
}
// open file and check if input file exists
TFile * file = TFile::Open(fileName);
// if input file was specified but not found, quit
if(!file && !TString(infile).IsNull()){
Logger << kERROR << "file " << fileName << " not found" << GEndl;
return;
}
if(!file){
// if it is still not there, then we can't continue
Logger << kERROR << "Not able to open input file" <<GEndl;
return;
}
RooWorkspace* w = (RooWorkspace *)file->Get(wsname);
if (!w) {
// if it is still not there, then we can't continue
Logger << kERROR << "Not able to retrieve workspace" <<GEndl;
return;
}
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsData* data = ( (RooAbsData*)w->data("obsData") );
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
data->table(*((RooAbsCategory*)regionCat))->Print("v");
TString plotRegions = "ALL";
std::vector<TString> regionsVec = GetRegionsVec(plotRegions, regionCat);
unsigned int numPlots = regionsVec.size();
RooWorkspace* wcomb = new RooWorkspace(wsname);
TString allObs;
// iterate over all the regions
for(unsigned int iVec=0; iVec<numPlots; iVec++){
TString regionCatLabel = regionsVec[iVec];
if( regionCat->setLabel(regionCatLabel,kTRUE)){
Logger << kINFO << " Label '" << regionCatLabel << "' is not a state of channelCat (see Table) " << GEndl;
}else{
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionCatLabel.Data());
TString dataCatLabel = Form("channelCat==channelCat::%s",regionCatLabel.Data());
RooDataSet* regionData = (RooDataSet*) data->reduce(dataCatLabel.Data());
if(regionPdf==NULL || regionData==NULL){
Logger << kWARNING << " Either the Pdf or the Dataset do not have an appropriate state for the region = " << regionCatLabel << ", check the Workspace file" << GEndl;
Logger << kWARNING << " regionPdf = " << regionPdf << " regionData = " << regionData << GEndl;
continue;
}
RooRealVar* regionVar =(RooRealVar*) ((RooArgSet*) regionPdf->getObservables(*regionData))->find(Form("obs_x_%s",regionCatLabel.Data()));
RooDataSet* rdata = (RooDataSet*)regionData->reduce(RooArgSet(*regionVar,*w->var("weightVar")));
wcomb->import( *rdata, Rename( TString("obsData_")+TString(regionVar->GetName()) ), RenameVariable(regionVar->GetName(),"obs"), RecycleConflictNodes(true) );
wcomb->import( *regionPdf, RenameVariable(regionVar->GetName(),"obs"), RecycleConflictNodes(true) );
}
}
wcomb->writeToFile(outfile);
file->Close();
}
//__________________________________________________________________________________________________________________________________________________________
void Util::PlotPdfWithComponents(RooWorkspace* w, TString fcName, TString anaName, TString plotRegions, TString outputPrefix, RooFitResult* rFit, RooAbsData* inputData)
{
HistogramPlotter h(w, fcName);
h.setAnalysisName(anaName);
h.setPlotRegions(plotRegions);
h.setPlotComponents(true);
h.setOutputPrefix(outputPrefix);
h.setFitResult(rFit);
h.setInputData(inputData);
h.setPlotSeparateComponents(true); //TODO: hack
h.Initialize();
h.PlotRegions();
}
//_____________________________________________________________________________________________________________________________________
void Util::PlotSeparateComponents(RooWorkspace* w,TString fcName, TString anaName, TString plotRegions,TString outputPrefix, RooFitResult* rFit, RooAbsData* inputData)
{
if(rFit==NULL){
Logger << kWARNING << " Running PlotSeparateComponents() without a RooFitResult is pointless, I'm done" << GEndl ;
return;
}
Bool_t plotComponents=true;
ConfigMgr* mgr = ConfigMgr::getInstance();
FitConfig* fc = mgr->getFitConfig(fcName);
Logger << kINFO << " ------ Starting PlotSeparateComponents with parameters: analysisName = " << fcName << GEndl;
Logger << kINFO << " fitRegions = " << plotRegions << " plotComponents = " << plotComponents << " outputPrefix = " << outputPrefix << GEndl;
if(w==NULL){
Logger << kWARNING << " Workspace not found, no plotting performed" << GEndl;
return;
}
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsData* data = ( inputData!=0 ? inputData : (RooAbsData*)w->data("obsData") );
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
data->table(*((RooAbsCategory*)regionCat))->Print("v");
if(plotRegions =="") plotRegions = "ALL";
std::vector<TString> regionsVec = GetRegionsVec(plotRegions, regionCat);
unsigned int numRegions = regionsVec.size();
TCanvas* canVec[numRegions];
for(unsigned int iVec=0; iVec<numRegions; iVec++){
TString regionCatLabel = regionsVec[iVec];
if( regionCat->setLabel(regionCatLabel,kTRUE)){
Logger << kWARNING << " Label '" << regionCatLabel << "' is not a state of channelCat (see Table) " << GEndl;
} else{
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionCatLabel.Data());
TString dataCatLabel = Form("channelCat==channelCat::%s",regionCatLabel.Data());
RooAbsData* regionData = (RooAbsData*) data->reduce(dataCatLabel.Data());
ChannelStyle style = fc->getChannelStyle(regionCatLabel);
if(regionPdf==NULL || regionData==NULL){
Logger << kERROR << " Either the Pdf or the Dataset do not have an appropriate state for the region = " << regionCatLabel << ", check the Workspace file" << GEndl;
Logger << kERROR << " regionPdf = " << regionPdf << " regionData = " << regionData << GEndl;
continue;
}
RooRealVar* regionVar =(RooRealVar*) ((RooArgSet*) regionPdf->getObservables(*regionData))->find(Form("obs_x_%s",regionCatLabel.Data()));
// get all components/samples in this region
TString RRSPdfName = Form("%s_model",regionCatLabel.Data());
RooRealSumPdf* RRSPdf = (RooRealSumPdf*) regionPdf->getComponents()->find(RRSPdfName);
TString binWidthName = Form("binWidth_obs_x_%s_0",regionCatLabel.Data());
RooRealVar* regionBinWidth = ((RooRealVar*) RRSPdf->getVariables()->find(Form("binWidth_obs_x_%s_0",regionCatLabel.Data()))) ;
if(regionBinWidth==NULL){
Logger << kWARNING << " bindWidth variable not found for region(" << regionCatLabel << "), PLOTTING COMPONENTS WILL BE WRONG " << GEndl ;
}
vector<double> regionCompFracVec = GetAllComponentFracInRegion(w, regionCatLabel, regionPdf, regionVar,regionBinWidth);
vector<TString> regionCompNameVec = GetAllComponentNamesInRegion(regionCatLabel, regionPdf);
Int_t numComps = regionCompNameVec.size();
// divide the canvas
Int_t canVecDivX = 1;
Int_t canVecDivY = 1;
if(numComps>0){
canVecDivX = ((Int_t) (sqrt(numComps)));
canVecDivY = ((Int_t) (sqrt(numComps)+0.5));
if(canVecDivX<1)
canVecDivX = 1;
if(canVecDivY<1)
canVecDivY = 1;
}
TString canName=Form("can_%s_%s_separateComponents",regionCatLabel.Data(),outputPrefix.Data());
canVec[iVec] = new TCanvas(canName,canName,600,600); // .c_str())
canVec[iVec]->Divide(canVecDivX , canVecDivY);
//iterate over all samples and plot
for( unsigned int iComp=0; iComp<regionCompFracVec.size(); iComp++){
TString component = regionCompNameVec[iComp];
RooPlot* frame = regionVar->frame();
frame->SetName(Form("frame_%s_%s_%s",regionCatLabel.Data(),regionCompNameVec[iComp].Data(),outputPrefix.Data()));
Int_t compPlotColor = ( (fc!=0) ? style.getSampleColor(regionCompNameVec[iComp]) : static_cast<int>(iComp) );
TString compShortName = ( (fc!=0) ? style.getSampleName(regionCompNameVec[iComp]) : "" );
// normalize pdf to number of expected events, not to number of events in dataset
double normCount = regionPdf->expectedEvents(*regionVar);
if (rFit != NULL)
regionPdf->plotOn(frame,Components(regionCompNameVec[iComp].Data()),VisualizeError(*rFit),FillColor(kCyan),Precision(1e-5),Normalization(1,RooAbsReal::RelativeExpected));
regionPdf->plotOn(frame,Components(regionCompNameVec[iComp].Data()),LineColor(compPlotColor),Normalization(regionCompFracVec[iComp]*normCount,RooAbsReal::NumEvent),Precision(1e-5));
canVec[iVec]->cd(iComp+1);
frame->SetMinimum(0.);
frame->Draw();
TLegend* leg = new TLegend(0.55,0.65,0.85,0.9,"");
leg->SetFillStyle(0);
leg->SetFillColor(0);
leg->SetBorderSize(0);
TLegendEntry* entry=leg->AddEntry("","Prop. Fit Error","f") ;
entry->SetMarkerColor(kCyan);
entry->SetMarkerStyle();
entry->SetFillColor(kCyan);
entry->SetFillStyle(1001);
entry=leg->AddEntry("",compShortName.Data(),"l") ;
entry->SetLineColor(compPlotColor);
leg->Draw();
}
canVec[iVec]->SaveAs("results/"+anaName+"/"+canName+".pdf");
canVec[iVec]->SaveAs("results/"+anaName+"/"+canName+".eps");
}
}
}
//_____________________________________________________________________________________________________________________________________
void Util::PlotNLL(RooWorkspace* w, RooFitResult* rFit, Bool_t plotPLL, TString anaName, TString outputPrefix, RooAbsData* inputData, TString plotPars, TString fitRegions, Bool_t lumiConst)
{
if(rFit==NULL){
Logger << kWARNING << " Running PlotNLL() without a RooFitResult is pointless, I'm done" << GEndl ;
return;
}
Logger << kINFO << " ------ Starting PlotNLL with parameters: " << GEndl;
Logger << kINFO << " outputPrefix = " << outputPrefix << GEndl;
if(!w){
Logger << kINFO << " Workspace not found, no plotting performed" << GEndl;
return;
}
if(!deactivateBinnedLikelihood) {
RooFIter iter = w->components().fwdIterator();
RooAbsArg* arg;
while ((arg = iter.next())) {
if (arg->IsA() == RooRealSumPdf::Class()) {
arg->setAttribute("BinnedLikelihood");
cout << "Activating binned likelihood attribute for " << arg->GetName() << endl;
}
}
}
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsData* data = ( inputData!=0 ? inputData : (RooAbsData*)w->data("obsData") );
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
data->table(*((RooAbsCategory*)regionCat))->Print("v");
if (lumiConst) {
RooRealVar* lumi = (RooRealVar*) w->var("Lumi");
if (lumi!=NULL) lumi->setConstant(lumiConst);
}
// Construct an empty simultaneous pdf using category regionCat as index
RooSimultaneous* simPdfFitRegions = pdf;
RooDataSet* dataFitRegions = (RooDataSet*) data;
std::vector<TString> fitRegionsVec = GetRegionsVec(fitRegions, regionCat);
unsigned int numFitRegions = fitRegionsVec.size();
std::vector<RooDataSet*> dataVec;
std::vector<RooAbsPdf*> pdfVec;
for(unsigned int iVec=0; iVec<numFitRegions; iVec++){
TString regionCatLabel = fitRegionsVec[iVec];
if( regionCat->setLabel(regionCatLabel,kTRUE)){
Logger << kWARNING << " Label '" << regionCatLabel << "' is not a state of channelCat (see Table) " << GEndl;
} else{
// dataset for each channel/region/category
TString dataCatLabel = Form("channelCat==channelCat::%s",regionCatLabel.Data());
RooDataSet* regionData = (RooDataSet*) data->reduce(dataCatLabel.Data());
dataVec.push_back(regionData);
// pdf for each channel/region/category
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionCatLabel.Data());
pdfVec.push_back(regionPdf);
}
}
if(dataVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN DATASET, NO FIT WILL BE PERFORMED" << GEndl;
return;
}
else if(pdfVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN SIMULTANEOUS PDF, NO FIT WILL BE PERFORMED" << GEndl;
return;
}
else{
// Construct a simultaneous dataset for all fit regions
dataFitRegions = (RooDataSet*) dataVec[0]->Clone("dataFitRegions");
for(unsigned int jVec=1; jVec<dataVec.size(); jVec++){
dataFitRegions->append(*dataVec[jVec]);
}
// Construct a simultaneous pdf using category regionCat as index
simPdfFitRegions = new RooSimultaneous("simPdfFitRegions","simultaneous pdf only for fit regions",*regionCat) ;
for(unsigned int kVec=0; kVec<pdfVec.size(); kVec++){
simPdfFitRegions->addPdf(*pdfVec[kVec],fitRegionsVec[kVec].Data());
}
}
// find parameters requested for plotting
RooArgSet* plotParams = new RooArgSet();
if(plotPars != "") {
std::vector<TString> parsVec = Tokens(plotPars,",");
for(unsigned int i=0; i<parsVec.size();i++){
RooRealVar* var = (RooRealVar*) w->var(parsVec[i]);
if(var==NULL) Logger << kWARNING << " Util::PlotNLL() could not find parameter(" << parsVec[i] << ") in workspace while setting up minos" << GEndl;
else{
plotParams->add(*var);
}
}
}
// Get all parameters of result
RooArgList fpf = rFit->floatParsFinal();
RooStats::ModelConfig* mc = Util::GetModelConfig( w );
const RooArgSet* globObs = mc->GetGlobalObservables();
// Create Log Likelihood
RooAbsReal* nll = simPdfFitRegions->createNLL(*dataFitRegions,NumCPU(2), RooFit::GlobalObservables(*globObs), RooFit::Offset(true)) ;
unsigned int numParsP = plotParams->getSize();
if (numParsP==0) { numParsP = fpf.getSize(); }
unsigned int numPars = fpf.getSize();
if(numPars<1){
Logger << kWARNING << "Util::PlotNLL rFit contains no floating parameters" << GEndl;
return;
}
Logger << kINFO << "Util::PlotNLL rFit contains no floating parameters: " << numParsP << GEndl;
TCanvas* canVec[numPars];
// loop over all floating pars
for(unsigned int iPar=0, jPar=0; iPar<numPars ; iPar++){
RooAbsArg* arg = fpf.at(iPar);
if ( (plotParams->getSize()>0) && plotParams->find(arg->GetName())==0 ) { continue; }
if ( !arg->InheritsFrom("RooRealVar") ) { continue; }
jPar++; // special counter when selecting parameters
RooRealVar* par = (RooRealVar*) arg;
TString parName = par->GetName();
// if ( parName.Contains("gamma_stat_TR5JMu_cuts_bin_0") ){
Logger << kINFO << "Plotting NLL for par = " << parName << GEndl;
// set parameter range to readable range
double minRange = par->getMin();
double maxRange = par->getMax();
if(minRange < 0.){
par->setMin(-3.);
par->setMax(3.);
} else {
par->setMin(minRange);
par->setMax(2.);
}
RooPlot* frame = par->frame();
nll->plotOn(frame, ShiftToZero() );
frame->SetMinimum(0.);
// To be able to see the 1/2 sigma
frame->SetMaximum(2.5);
//const char* curvename = 0;
RooCurve* curve = (RooCurve*) frame->findObject(nullptr, RooCurve::Class()) ;
TGraph* nllCurve = static_cast<TGraph*>(curve->Clone());
nllCurve->SetName(TString("nll_")+parName);
Double_t curveMax = curve->getYAxisMax();
// safety for weird RooPlots where curve goes to infinity in first/last bin(s)
if (curveMax > 0. && !std::isinf(curveMax) && !std::isnan(curveMax) ) { ; } // frame->SetMaximum(curveMax * 2.);
else if(curveMax > 0. && (std::isinf(curveMax) || std::isnan(curveMax))){
for(Int_t iBin=1; iBin < curve->GetN()-1; iBin++){
Double_t xBin = 0.;
Double_t yBin = -1.;
curve->GetPoint(iBin,xBin,yBin) ;
if(std::isinf(yBin) || std::isnan(yBin)){
curve->RemovePoint(iBin);
Logger << kWARNING << " Removing bin = " << iBin << " as it was either inf or nan from NLL plot for parameter = " << parName<< GEndl;
iBin--;
}
}
Int_t iBin = 1;
Double_t xFirstBin = 0.;
Double_t yFirstBin = -1.;
while ( (yFirstBin<0 || std::isinf(yFirstBin) || std::isnan(yFirstBin) )&& iBin < curve->GetN()-1){
iBin++;
curve->GetPoint(iBin,xFirstBin,yFirstBin) ;
if(std::isinf(yFirstBin) || std::isnan(yFirstBin)){
curve->RemovePoint(iBin);
Logger << kWARNING << " Removing bin = " << iBin << " as it was either inf or nan from NLL plot for parameter = " << parName<< GEndl;
}
}
iBin = curve->GetN()-1;
Double_t xLastBin = 0.;
Double_t yLastBin = -1.;
while ( (yLastBin < 0 || std::isinf(yLastBin) || std::isnan(yLastBin) ) && iBin >0){
iBin--;
curve->GetPoint(iBin,xLastBin,yLastBin) ;
if(std::isinf(yLastBin) || std::isnan(yLastBin)){
curve->RemovePoint(iBin);
Logger << kWARNING << " Removing bin = " << iBin << " as it was either inf or nan from NLL plot for parameter = " << parName<< GEndl;
}
}
curveMax = yLastBin>yFirstBin ? yLastBin : yFirstBin;
}
// plot cosmetics
int firstbin = frame->GetXaxis()->GetFirst();
int lastbin = frame->GetXaxis()->GetLast();
double xmax = frame->GetXaxis()->GetBinUpEdge(lastbin) ;
double xmin = frame->GetXaxis()->GetBinLowEdge(firstbin) ;
TLine* l1 = new TLine(xmin, 2., xmax, 2.);
TLine* l2 = new TLine(xmin, 0.5, xmax, 0.5);
l1->SetLineStyle(3);
l2->SetLineStyle(3);
frame->addObject(l1);
frame->addObject(l2);
RooAbsReal* pll(0);
TGraph *pllCurve = 0;
if(plotPLL) {
pll = nll->createProfile(*par) ;
pll->plotOn(frame, LineColor(kRed), LineStyle(kDashed), NumCPU(4));
//const char* curvename = 0;
RooCurve* curve = (RooCurve*) frame->findObject(nullptr, RooCurve::Class()) ;
pllCurve = static_cast<TGraph*>(curve->Clone());
pllCurve->SetName(TString("nll_")+parName);
}
TString canName=Form("can_NLL_%s_%s_%s", outputPrefix.Data(), rFit->GetName(), parName.Data());
canVec[iPar] = new TCanvas(canName, canName, 600, 600);
canVec[iPar]->cd();
frame->Draw();
TLegend* leg = new TLegend(0.55, 0.65, 0.85, 0.9, "");
leg->SetFillStyle(0);
leg->SetFillColor(0);
leg->SetBorderSize(0);
TLegendEntry* entry=leg->AddEntry("", "NLL", "l") ;
entry->SetLineColor(kBlue);
if(plotPLL) {
entry=leg->AddEntry("", "PLL", "l") ;
entry->SetLineColor(kRed);
entry->SetLineStyle(kDashed);
}
leg->Draw();
// update plot
canVec[iPar]->Draw();
// reset parameter range to previous values
par->setMin(minRange);
par->setMax(maxRange);
if (plotPLL) {
delete pll; pll=0;
}
canVec[iPar]->SaveAs("results/"+anaName+"/"+canName+".pdf");
canVec[iPar]->SaveAs("results/"+anaName+"/"+canName+".C");
canVec[iPar]->SaveAs("results/"+anaName+"/"+canName+".eps");
TString fname("results/"+anaName+"/"+canName+".root");
TFile *f = TFile::Open(fname, "RECREATE");
nllCurve->Write();
if(pllCurve) { pllCurve->Write(); }
f->Close();
// }
}
delete nll ;
}
//_____________________________________________________________________________
TH2D* Util::PlotCorrelationMatrix(RooFitResult* rFit, TString anaName, bool ReduceMatrix){
if(rFit==NULL){
Logger << kWARNING << "Running PlotCorrelationMatrix() without a RooFitResult is pointless, I'm done" << GEndl ;
throw 1 ;
}
Logger << kINFO << " ------ Starting PlotCorrelationMatrix() " << GEndl;
Int_t numPars = rFit->floatParsFinal().getSize();
TString canName = Form("c_corrMatrix_%s",rFit->GetName());
TCanvas* c_corr = new TCanvas(canName.Data(),canName.Data(),600,400); // .c_str())
Double_t orig_MarkerSize = gStyle->GetMarkerSize();
Int_t orig_MarkerColor = gStyle->GetMarkerColor();
const char* orig_PaintTextFormat = gStyle->GetPaintTextFormat() ;
Double_t orig_LabelSize = gStyle->GetLabelSize();
gStyle->SetPalette(105) ;
gStyle->SetMarkerSize(1.45);
gStyle->SetMarkerColor(kWhite);
gStyle->SetPaintTextFormat("4.2f") ;
if(numPars<5) gStyle->SetMarkerSize(1.4);
else if(numPars<10) gStyle->SetMarkerSize(1.1);
else if(numPars<20) gStyle->SetMarkerSize(0.85);
else if(numPars<40) gStyle->SetMarkerSize(0.5);
else gStyle->SetMarkerSize(0.25);
TH2D* h_corr = (TH2D*) rFit->correlationHist(Form("h_corr_%s",rFit->GetName()));
if (ReduceMatrix) {
// Cleanup corrMattrix from rows and columns with content less then corrThres
vector <int> rm_idx; rm_idx.clear();
double corrThresh[3] = {0.01,0.1,0.2};
int nbins = h_corr->GetNbinsX();
int index_x=0, index_y=0, Thresh1Counter;//, Thresh0Counter, Thresh2Counter;
bool fillHistY, fillHistX;
// Look for rows and columns indices to remove
for (int ix=1; ix<nbins+1; ix++) {
//Thresh0Counter = 0;
Thresh1Counter = 0;
//Thresh2Counter = 0;
for (int iy=1; iy<nbins+1; iy++) {
if (ix==((nbins+1)-iy)) continue;
//if (fabs(h_corr->GetBinContent(ix,iy))>=corrThresh[0]) Thresh0Counter++;
if (fabs(h_corr->GetBinContent(ix,iy))>=corrThresh[1]) Thresh1Counter++;
//if (fabs(h_corr->GetBinContent(ix,iy))>=corrThresh[2]) Thresh2Counter++;
}
//if ( Thresh0Counter<(nbins+1)/5. && Thresh1Counter<(nbins+1)/10. && Thresh2Counter==0 ) rm_idx.push_back(ix);
if ( Thresh1Counter==0 ) rm_idx.push_back(ix);
}
int nrm_idx = rm_idx.size();
int newSize = numPars-nrm_idx;
TH2D* h_corr_reduced = new TH2D("h_corr_reduced","h_corr_reduced",newSize,0,newSize,newSize,0,newSize);
// Copy original matrix to the new without empty rows and columns
for (int ix=1; ix<nbins+1; ix++) {
index_y=0;
fillHistX=false;
for (int iy=1; iy<nbins+1; iy++) {
fillHistY=true;
for (int irm=0; irm<nrm_idx; irm++) {
if ( ix==rm_idx.at(irm) || iy==((nbins+1)-rm_idx.at(irm)) ) fillHistY=false;
}
if (fillHistY) {
h_corr_reduced->Fill(index_x,index_y,h_corr->GetBinContent(ix,iy));
index_y++;
if (index_x==0) h_corr_reduced->GetYaxis()->SetBinLabel(index_y,h_corr->GetYaxis()->GetBinLabel(iy));
fillHistX=true;
}
}
if (fillHistX) {
index_x++;
h_corr_reduced->GetXaxis()->SetBinLabel(index_x,h_corr->GetXaxis()->GetBinLabel(ix));
}
}
h_corr = h_corr_reduced;
numPars = newSize;
}
Double_t labelSize = orig_LabelSize;
if(numPars<5) labelSize = 0.05;
else if(numPars<10) labelSize = 0.04;
else if(numPars<20) labelSize = 0.025;
else if(numPars<40) labelSize = 0.02;
else labelSize = 0.015;
h_corr->GetXaxis()->SetLabelSize(labelSize);
h_corr->GetYaxis()->SetLabelSize(labelSize);
h_corr->GetXaxis()->LabelsOption("v");
gPad->SetLeftMargin(0.18);
gPad->SetRightMargin(0.13);
gStyle->SetMarkerSize(orig_MarkerSize);
gStyle->SetMarkerColor(orig_MarkerColor);
gStyle->SetPaintTextFormat(orig_PaintTextFormat) ;
gStyle->SetLabelSize(orig_LabelSize);
gStyle->SetOptStat(00000000);
h_corr->Draw("colz");
h_corr->Draw("textsame");
c_corr->SaveAs("results/"+anaName+"/"+canName+".pdf");
c_corr->SaveAs("results/"+anaName+"/"+canName+".eps");
gStyle->SetMarkerSize(orig_MarkerSize);
gStyle->SetMarkerColor(orig_MarkerColor);
gStyle->SetPaintTextFormat(orig_PaintTextFormat) ;
gStyle->SetLabelSize(orig_LabelSize);
gStyle->SetOptStat(00000000);
return h_corr;
}
//_____________________________________________________________________________
TH2D* Util::GetCorrelations(RooFitResult* rFit, double threshold, TString anaName) {
TH2D* h_corr = Util::PlotCorrelationMatrix(rFit, anaName);
unsigned int nBinsX = h_corr->GetNbinsX();
unsigned int nBinsY = h_corr->GetNbinsY();
for(unsigned int iBinY = 1; iBinY <= nBinsY; iBinY++){
for(unsigned int iBinX = 1; iBinX <= nBinsX && iBinX <= (nBinsX-iBinY); iBinX++){
if(fabs(h_corr->GetBinContent(iBinX,iBinY)) > threshold){
Logger << kWARNING << " High correlation coefficient between: par1 = " << h_corr->GetXaxis()->GetBinLabel(iBinX) << " and par2 = "
<< h_corr->GetYaxis()->GetBinLabel(iBinY) << " "
<< " val = " << h_corr->GetBinContent(iBinX,iBinY) << GEndl;
}
}
}
return h_corr;
}
//_____________________________________________________________________________
vector<TString> Util::Tokens(TString aline,TString aDelim)
{
Int_t i;
TObjArray* InObjArray;
TObjString* os;
TString s;
vector<TString> OutStringVec;
OutStringVec.clear();
InObjArray=aline.Tokenize(aDelim);
for ( i=0; i<InObjArray->GetEntriesFast(); i++ )
{
os=(TObjString*)InObjArray->At(i);
s=os->GetString();
OutStringVec.push_back(s);
}
return OutStringVec;
}
//_____________________________________________________________________________
vector<TString> Util::TokensALL(RooCategory* cat)
{
vector<TString> OutStringVec;
OutStringVec.clear();
TIterator* iter = cat->typeIterator() ;
RooCatType* catType ;
while( (catType = (RooCatType*) iter->Next())) {
TString regionCatLabel = catType->GetName();
OutStringVec.push_back(regionCatLabel);
}
return OutStringVec;
}
//__________________________________________________________________________________________________________________________________________________________
Double_t Util::GetComponentFrac(RooWorkspace* w, const char* Component, const char* RRSPdfName, RooRealVar* observable, RooRealVar* binWidth){
RooAbsReal* i_RRSPdf = ((RooAbsPdf*)w->pdf(RRSPdfName))->createIntegral(RooArgSet(*observable));
RooAbsReal* i_component = ((RooProduct*)w->obj(Component))->createIntegral(RooArgSet(*observable));
Double_t Int_RRSPdf = i_RRSPdf->getVal();
Double_t Int_component = i_component->getVal();
Double_t componentFrac = 0.;
if(Int_RRSPdf != 0.) componentFrac = Int_component * binWidth->getVal() / Int_RRSPdf;
delete i_RRSPdf;
delete i_component;
return componentFrac;
}
//________________________________________________________________________________________________
RooWorkspace* Util::GetWorkspaceFromFile( const TString& infile, const TString& wsname ) {
TFile* file = TFile::Open(infile.Data(), "READ");
if (!file || file->IsZombie()) {
Logger << kERROR << "Cannot open file: " << infile << GEndl;
return NULL;
}
file->cd();
TObject* obj = file->Get( wsname.Data() ) ;
if (obj==0) {
Logger << kERROR << "Cannot open workspace <" << wsname << "> in file <" << infile << ">" << GEndl;
file->Close();
return NULL;
}
if (obj->ClassName()!=TString("RooWorkspace")) { // much faster than dynamic cast
Logger << kERROR << "Cannot open workspace <" << wsname << "> in file <" << infile << ">" << GEndl;
file->Close();
return NULL;
}
RooWorkspace* w = (RooWorkspace*)( obj );
if ( w==0 ) {
Logger << kERROR << "Cannot open workspace <" << wsname << "> in file <" << infile << ">" << GEndl;
file->Close();
return NULL;
}
return w;
}
//________________________________________________________________________________________________
RooStats::ModelConfig* Util::GetModelConfig( const RooWorkspace* w, const TString& mcName ) {
if (w==0) {
Logger << kERROR << "Workspace is a null pointer." << GEndl;
return NULL;
}
TObject* obj = w->obj( mcName.Data() ) ;
if (obj==0) {
Logger << kERROR << "Cannot open ModelConfig <" << mcName << "> from workspace." << GEndl;
return NULL;
}
RooStats::ModelConfig* mc = (RooStats::ModelConfig *)(obj);
if ( mc==0 ) {
Logger << kERROR << "Cannot open ModelConfig <" << mcName << "> from workspace" << GEndl;
return NULL;
}
return mc;
}
//________________________________________________________________________________________________
RooRealVar*
Util::GetPOI( const RooWorkspace* w )
{
if(w==0){
Logger << kERROR << "Input workspace is null!" << GEndl;
return NULL;
}
RooStats::ModelConfig* mc = Util::GetModelConfig(w);
if(mc==0){
Logger << kERROR << "ModelConfig is null!" << GEndl;
return NULL;
}
const RooArgSet* poiSet = mc->GetParametersOfInterest();
RooRealVar* firstPOI = ( poiSet!=0 ? (RooRealVar*) poiSet->first() : 0 );
return firstPOI;
}
//________________________________________________________________________________________________
RooFitResult*
Util::doFreeFit( RooWorkspace* w, RooDataSet* inputdata, const bool& verbose, const bool& resetAfterFit, bool hesse, Bool_t minos, TString minosPars )
{
// fit to reset the workspace
if(w==0){
Logger << kERROR << "Input workspace is null!" << GEndl;
return NULL;
}
if(!deactivateBinnedLikelihood) {
RooFIter iter = w->components().fwdIterator();
RooAbsArg* arg;
while ((arg = iter.next())) {
if (arg->IsA() == RooRealSumPdf::Class()) {
arg->setAttribute("BinnedLikelihood");
cout << "Activating binned likelihood attribute for " << arg->GetName() << endl;
}
}
}
RooStats::ModelConfig* mc = Util::GetModelConfig(w);
if(mc==0){
Logger << kERROR << "ModelConfig is null!" << GEndl;
return NULL;
}
/// get pdf and dataset
RooDataSet* data(0);
if (inputdata!=0) {
data = inputdata;
}
else
data = dynamic_cast<RooDataSet*>(w->data("obsData")); // default: fit to data
if (verbose) data->Print();
RooAbsPdf* pdf = mc->GetPdf();
if((data==0)||(pdf==0)){
Logger << kERROR << "data set or pdf not found" <<GEndl;
return NULL;
}
if (resetAfterFit) {
// save snapshot before any fit has been done
RooArgSet* params = (RooArgSet*) pdf->getParameters(*data) ;
if(!w->loadSnapshot("snapshot_paramsVals_initial")) {
w->saveSnapshot("snapshot_paramsVals_initial",*params);
} else {
Logger << kWARNING << "Snapshot 'snapshot_paramsVals_initial' already exists in workspace, will not overwrite it" << GEndl;
}
}
/////////////////////////////////////////////////////////////
RooArgSet* allParams = pdf->getParameters(data);
RooStats::RemoveConstantParameters(allParams);
const RooArgSet* globObs = mc->GetGlobalObservables();
RooAbsReal* nll = (RooNLLVar*) pdf->createNLL(*data, RooFit::GlobalObservables(*globObs), RooFit::Offset(true));
// find parameters requested for Minos
RooArgSet* minosParams = new RooArgSet();
if(minosPars != "" && minos && minosPars != "all" && minosPars != "ALL"){
std::vector<TString> parsVec = Tokens(minosPars,",");
for(unsigned int i=0; i<parsVec.size();i++){
RooRealVar* var = (RooRealVar*) w->var(parsVec[i]);
if(var==NULL) Logger << kWARNING << " Util::doFreeFit() could not find parameter(" << parsVec[i] << ") in workspace while setting up minos" << GEndl;
else{
minosParams->add(*var);
}
}
}
int minimPrintLevel = verbose;
RooMinimizer minim(*nll);
int strategy = ROOT::Math::MinimizerOptions::DefaultStrategy();
minim.setStrategy( strategy);
// use tolerance - but never smaller than 1 (default in RooMinimizer)
double tol = ROOT::Math::MinimizerOptions::DefaultTolerance();
tol = std::max(tol,1.0); // 1.0 is the minimum value used in RooMinimizer
minim.setEps( tol );
//LM: RooMinimizer.setPrintLevel has +1 offset - so subtruct here -1
minim.setPrintLevel(minimPrintLevel-1);
minim.optimizeConst(2);
TString minimizer = "Minuit2"; //ROOT::Math::MinimizerOptions::DefaultMinimizerType();
TString algorithm = ROOT::Math::MinimizerOptions::DefaultMinimizerAlgo();
int status = -1;
// require covQual = 3 from any fit while retrying?
bool requireGoodCovQual = true;
Logger << kINFO << "Util::doFreeFit() ........ using " << minimizer << " / " << algorithm
<< " with strategy " << strategy << " and tolerance " << tol << GEndl;
for (int tries = 1, maxtries = 5; tries <= maxtries; ++tries) {
// status = minim.minimize(fMinimizer, ROOT::Math::MinimizerOptions::DefaultMinimizerAlgo().c_str());
status = minim.minimize(minimizer, algorithm);
if (status%1000 == 0) { // ignore erros from Improve
// if desired, is the covariance matrix OK?
std::unique_ptr<RooFitResult> res(minim.save());
if(!requireGoodCovQual || res->covQual() == 3){
break;
} else {
Logger << kINFO << " status OK but covariance matrix not at full accuracy, retrying" << GEndl;
}
}
if (tries == 1) {
Logger << kINFO << " ----> Doing a re-scan first" << GEndl;
minim.minimize(minimizer,"Scan");
} else if (tries == 2) {
if (strategy == 0) {
Logger << kINFO << " ----> trying with strategy = 1" << GEndl;
strategy = 1;
minim.setStrategy(strategy);
} else {
tries++; // skip this trial if stratehy is already 1
}
} else if (tries == 3) {
if (strategy == 1) {
Logger << kINFO << " ----> trying with strategy = 2" << GEndl;
strategy = 2;
minim.setStrategy(strategy);
} else {
tries++; // skip this trial if stratehy is already 2
}
} else if (tries == 4) {
Logger << kINFO << " ----> trying with improve" << GEndl;
minimizer = "Minuit";
algorithm = "migradimproved";
}
}
std::unique_ptr<RooFitResult> res(minim.save());
if( requireGoodCovQual && res->covQual() != 3 && !hesse ) {
Logger << kINFO << "status OK but covariance matrix not at full accuracy, will retry with HESSE to improve" << GEndl;
hesse = true;
}
RooFitResult * result = 0;
if (status%100 == 0 ) { // ignore errors in Hesse or in Improve
// only calculate minos errors if fit with Migrad converged
Logger << kINFO << "status: " << status << ", hesse = " << hesse <<" minos = " << minos << " minosPars = " << minosPars << GEndl;
if(hesse || minos ) {
minim.hesse();
}
if(minos && (minosPars == "all" || minosPars == "ALL")) {
minim.minos();
} else if(minos && minosPars != "" && minosParams->getSize() > 0) {
minim.minos(*minosParams);
}
// save fit result
// ignore errors in Hesse or in Improve if minos option not activated
result = minim.save();
}
else {
Logger << kERROR << "FIT FAILED !- return a NaN NLL " << GEndl;
}
//////////////////////////////////////////////////////////////
if (resetAfterFit) {
w->loadSnapshot("snapshot_paramsVals_initial");
}
return result;
}
//________________________________________________________________________________________________
RooMCStudy*
Util::GetMCStudy( const RooWorkspace* w )
{
if (w==0) {
Logger << kERROR << "Input workspace is null. Return." << GEndl;
return NULL;
}
RooStats::ModelConfig* mc = Util::GetModelConfig(w);
if(mc==0){
Logger << kERROR << "ModelConfig is null!" << GEndl;
return NULL;
}
RooAbsPdf* pdf = mc->GetPdf();
const RooArgSet* obsset = mc->GetObservables();
if((pdf==0)||(obsset==0)){
Logger << kERROR << "pdf or observables not found" <<GEndl;
return NULL;
}
// caller owns mcstudy
return ( new RooMCStudy( *pdf, *obsset, RooFit::FitOptions("r") ) ) ;
}
//________________________________________________________________________________________________
// ATLAS specific - FIXME ; remove for public release
void Util::ATLASLabel(Double_t x,Double_t y,const char* text,Color_t color)
{
TLatex l;
l.SetNDC();
l.SetTextFont(72);
l.SetTextColor(color);
double delx = 0.115*696*gPad->GetWh()/(472*gPad->GetWw());
l.DrawLatex(x,y,"ATLAS");
if (text) {
TLatex p;
p.SetNDC();
p.SetTextFont(42);
p.SetTextColor(color);
p.DrawLatex(x+delx,y,text);
// p.DrawLatex(x,y,"#sqrt{s}=900GeV");
}
}
//________________________________________________________________________________________________
void Util::AddText(Double_t x,Double_t y,char* text,Color_t color)
{
TLatex l;
l.SetNDC();
l.SetTextFont(72);
l.SetTextColor(color);
double delx = 0.115*696*gPad->GetWh()/(472*gPad->GetWw());
if (text) {
TLatex p;
p.SetNDC();
p.SetTextFont(42);
p.SetTextColor(color);
p.DrawLatex(x+delx,y,text);
}
}
void Util::AddTextLabel(Double_t x, Double_t y, const char* text, Color_t color)
{
TLatex l;
l.SetNDC();
l.SetTextFont(72);
l.SetTextColor(color);
double delx = 0.115 * 696 * gPad->GetWh() / (472 * gPad->GetWw());
if (text) {
TLatex p;
p.SetNDC();
p.SetTextFont(42);
p.SetTextColor(color);
p.DrawLatex(x + delx, y, text);
}
}
//_____________________________________________________________________________
RooAbsReal* Util::GetComponent(RooWorkspace* w, TString component, TString region, bool exactRegionName, TString rangeName){
std::vector<TString> componentVec = Tokens(component,",");
if(componentVec.size() <1) { Logger << kWARNING << " componentVec.size() < 1, for components = " << component << GEndl; }
if(w==NULL){
Logger << kERROR << " Workspace not found, no GetComponent performed" << GEndl;
return NULL;
}
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
TString regionFullName;
if(exactRegionName){
Logger << kINFO << "GetComponent(): using exact region name: " << region << GEndl;
regionFullName = region;
} else {
regionFullName = GetFullRegionName(regionCat, region);
}
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionFullName.Data());
RooAbsData* data = (RooAbsData*)w->data("obsData");
TString dataCatLabel = Form("channelCat==channelCat::%s",regionFullName.Data());
RooAbsData* regionData = (RooAbsData*) data->reduce(dataCatLabel.Data());
if(regionPdf==NULL || regionData==NULL){
Logger << kERROR << " Either the Pdf or the Dataset do not have an appropriate state for the region = " << region << ", check the Workspace file" << GEndl;
Logger << kERROR << " regionPdf = " << regionPdf << " regionData = " << regionData << GEndl;
return NULL;
}
RooRealVar* regionVar =(RooRealVar*) ((RooArgSet*) regionPdf->getObservables(*regionData))->find(Form("obs_x_%s",regionFullName.Data()));
// get the binWidth variable, to be multiplied with component RooProduct, for a complete component RooFormulaVar, as used in RooRealSumPdf
TString binWidthName = Form("binWidth_obs_x_%s_0",regionFullName.Data());
RooRealVar* regionBinWidth = ((RooRealVar*) regionPdf->getVariables()->find(Form("binWidth_obs_x_%s_0",regionFullName.Data()))) ;
if(regionBinWidth==NULL){
Logger << kWARNING << " bindWidth variable not found for region(" << regionFullName << "), RETURNING COMPONENTS WILL BE WRONG " << GEndl ;
return NULL;
}
// find the correct RooProduct
vector<TString> regionCompNameVec = GetAllComponentNamesInRegion(regionFullName, regionPdf);
RooArgList compFuncList;
RooArgList compCoefList;
for(unsigned int iReg=0; iReg<regionCompNameVec.size(); iReg++){
for(unsigned int iComp=0; iComp< componentVec.size(); iComp++){
Logger << kDEBUG << " GetComponent: regionCompNameVec[" << iReg << "] = " << regionCompNameVec[iReg] << " componentVec[" << iComp << "] = " << componentVec[iComp] << GEndl;
TString target = "_"+componentVec[iComp]+"_";
if( regionCompNameVec[iReg].Contains(target.Data())) {
compFuncList.add(*(RooProduct*)w->obj(regionCompNameVec[iReg]));
compCoefList.add(*regionBinWidth);
}
}
}
if (compFuncList.getSize()==0 || compCoefList.getSize()==0 || compCoefList.getSize()!=compFuncList.getSize()){
Logger << kERROR << " Something wrong with compFuncList or compCoefList in Util::GetComponent(w," << component << "," << region
<< ") " << GEndl << " compFuncList.getSize() = " << compFuncList.getSize() << " compCoefList.getSize() = " << compCoefList.getSize() << GEndl;
return NULL;
}
TString compName = "comps";
for(unsigned int iVec=0; iVec<componentVec.size(); iVec++){
compName += "_" + componentVec[iVec];
}
RooRealSumPdf* compRRS = new RooRealSumPdf(Form("RRS_region_%s_%s",region.Data(),compName.Data()),Form("RRS_region_%s_%s",region.Data(),compName.Data()),compFuncList,compCoefList);
if(!compRRS){
Logger << kERROR << " Cannot create a RooRealSumPdf in Util::GetComponent() "<< GEndl;
return NULL;
}
RooAbsReal* compFunc;
if(rangeName==""){
compFunc = compRRS->createIntegral(RooArgSet(*regionVar));
}
else{
compFunc = compRRS->createIntegral(RooArgSet(*regionVar),rangeName);
}
if(compFunc == NULL){
Logger << kERROR << " compRooProduct not found for region(" << regionFullName << "), component(" << component << ") RETURNING COMPONENTS WILL BE WRONG " << GEndl ;
return NULL;
}
RooFormulaVar* form_frac = new RooFormulaVar("form_fracError","@0",RooArgList(*compFunc));
if(rangeName==""){
form_frac->SetName(Form("form_frac_region_%s_%s",region.Data(),compName.Data()));
form_frac->SetTitle(Form("form_frac_region_%s_%s",region.Data(),compName.Data()));
}
else{
form_frac->SetName(Form("form_frac_region_%s_%s_%s",region.Data(),compName.Data(),rangeName.Data()));
form_frac->SetTitle(Form("form_frac_region_%s_%s_%s",region.Data(),compName.Data(),rangeName.Data()));
}
Logger << kINFO << " Adding " << form_frac->GetName() << " to workspace" << GEndl;
w->import( *form_frac,kTRUE);
gDirectory->Add(form_frac);
return form_frac;
}
//_____________________________________________________________________________
Double_t Util::GetComponentFracInRegion(RooWorkspace* w, TString component, TString region){
std::vector<TString> componentVec = Tokens(component,",");
if(componentVec.size() <1) {
Logger << kWARNING << " componentVec.size() < 1, for components = " << component << GEndl;
}
if(w==NULL){
Logger << kERROR << " Workspace not found, no GetComponent performed" << GEndl;
return 0;
}
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
TString regionFullName = GetFullRegionName(regionCat, region);
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionFullName.Data());
RooAbsData* data = (RooAbsData*)w->data("obsData");
TString dataCatLabel = Form("channelCat==channelCat::%s",regionFullName.Data());
RooAbsData* regionData = (RooAbsData*) data->reduce(dataCatLabel.Data());
if(regionPdf==NULL || regionData==NULL){
Logger << kERROR << " Either the Pdf or the Dataset do not have an appropriate state for the region = " << region << ", check the Workspace file" << GEndl;
Logger << kERROR << " regionPdf = " << regionPdf << " regionData = " << regionData << GEndl;
return 0;
}
RooRealVar* regionVar =(RooRealVar*) ((RooArgSet*) regionPdf->getObservables(*regionData))->find(Form("obs_x_%s",regionFullName.Data()));
// get the binWidth variable, to be multiplied with component RooProduct, for a complete component RooFormulaVar, as used in RooRealSumPdf
TString binWidthName = Form("binWidth_obs_x_%s_0",regionFullName.Data());
RooRealVar* regionBinWidth = ((RooRealVar*) regionPdf->getVariables()->find(Form("binWidth_obs_x_%s_0",regionFullName.Data()))) ;
if(regionBinWidth==NULL){
Logger << kWARNING << " bindWidth variable not found for region(" << regionFullName << "), RETURNING COMPONENTS WILL BE WRONG " << GEndl ;
return 0;
}
// find the correct RooProduct
vector<TString> regionCompNameVec = GetAllComponentNamesInRegion(regionFullName, regionPdf);
RooArgList compFuncList;
RooArgList compCoefList;
for(unsigned int iReg=0; iReg<regionCompNameVec.size(); iReg++){
for(unsigned int iComp=0; iComp< componentVec.size(); iComp++){
TString target = "_"+componentVec[iComp]+"_";
if( regionCompNameVec[iReg].Contains(target.Data())) {
compFuncList.add(*(RooProduct*)w->obj(regionCompNameVec[iReg]));
compCoefList.add(*regionBinWidth);
}
}
}
if (compFuncList.getSize()==0 || compCoefList.getSize()==0 || compCoefList.getSize()!=compFuncList.getSize()){
Logger << kERROR << " Something wrong with compFuncList or compCoefList in Util::GetComponent() "<< GEndl;
return 0.;
}
TString compName = "comps";
for(unsigned int iVec=0; iVec<componentVec.size(); iVec++){
compName += "_" + componentVec[iVec];
}
// get the full RRSPdf of this region
TString RRSPdfName = Form("%s_model",regionFullName.Data());
double componentFrac = 0.;
for(unsigned int iReg=0; iReg<regionCompNameVec.size(); iReg++){
for(unsigned int iComp=0; iComp< componentVec.size(); iComp++){
TString target = "_"+componentVec[iComp]+"_";
if( regionCompNameVec[iReg].Contains(target.Data())) {
componentFrac += GetComponentFrac(w,regionCompNameVec[iReg],RRSPdfName,regionVar,regionBinWidth) ;
}
}
}
return componentFrac;
}
//_____________________________________________________________________________
RooAbsPdf* Util::GetRegionPdf(RooWorkspace* w, TString region){ //, unsigned int bin){
if(w==NULL){
Logger << kERROR << " Workspace not found, no GetRegionPdf performed" << GEndl;
return NULL;
}
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
TString regionFullName = GetFullRegionName(regionCat, region);
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionFullName.Data());
if(regionPdf==NULL){
Logger << kERROR << " The Simultaneous Pdf does not have an appropriate state for the region = " << region << ", check the Workspace file" << GEndl;
Logger << kERROR << " regionPdf = " << regionPdf << GEndl;
return NULL;
}
return regionPdf;
}
//_____________________________________________________________________________
RooRealVar* Util::GetRegionVar(RooWorkspace* w, TString region){
if(w==NULL){
Logger << kERROR << " Workspace not found, no GetComponent performed" << GEndl;
return NULL;
}
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
TString regionFullName = GetFullRegionName(regionCat, region);
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionFullName.Data());
RooAbsData* data = (RooAbsData*)w->data("obsData");
TString dataCatLabel = Form("channelCat==channelCat::%s",regionFullName.Data());
RooAbsData* regionData = (RooAbsData*) data->reduce(dataCatLabel.Data());
if(regionPdf==NULL || regionData==NULL){
Logger << kERROR << " Either the Pdf or the Dataset do not have an appropriate state for the region = " << region << ", check the Workspace file" << GEndl;
Logger << kERROR << " regionPdf = " << regionPdf << " regionData = " << regionData << GEndl;
return NULL;
}
RooRealVar* regionVar =(RooRealVar*) ((RooArgSet*) regionPdf->getObservables(*regionData))->find(Form("obs_x_%s",regionFullName.Data()));
return regionVar;
}
//__________________________________________________________________________________________
TString Util::GetFullRegionName(RooCategory* regionCat, TString regionShortName){
std::vector<TString> regionsAllVec = TokensALL(regionCat);
TString regionFullName;
Int_t foundReg = 0;
for(unsigned int iReg=0; iReg<regionsAllVec.size(); iReg++){
if( regionsAllVec[iReg].Contains(regionShortName) && foundReg==0) {
regionFullName = regionsAllVec[iReg];
foundReg++;
}
else if( regionsAllVec[iReg].Contains(regionShortName) && foundReg>0){
foundReg++;
}
}
if(foundReg>1)
Logger << kWARNING << "Util.GetFullRegionName() found more then one region in workspace with shortname = " << regionShortName
<< " \n Please use full region names (like WREl_meffInc) insted of shortnames (like WR) " << GEndl;
return regionFullName;
}
//__________________________________________________________________________________________
vector<TString> Util::GetAllComponentNamesInRegion(TString region, RooAbsPdf* regionPdf){
TString RRSPdfName = Form("%s_model",region.Data());
RooRealSumPdf* RRSPdf = (RooRealSumPdf*) regionPdf->getComponents()->find(RRSPdfName);
if(RRSPdf==NULL){
Logger << kERROR << " Util::GetAllComponentNamesInRegion() cannot find a RooRealSumPdf named " << RRSPdfName << GEndl ;
vector<TString> vec;
return vec;
}
RooArgList RRSComponentsList = RRSPdf->funcList();
RooLinkedListIter iter = RRSComponentsList.iterator() ;
RooProduct* component;
vector<TString> compNameVec;
compNameVec.clear();
while( (component = (RooProduct*) iter.Next())) {
TString componentName = component->GetName();
compNameVec.push_back(componentName);
}
return compNameVec;
}
//__________________________________________________________________________________________
vector<double> Util::GetAllComponentFracInRegion(RooWorkspace* w, TString region, RooAbsPdf* regionPdf, RooRealVar* obsRegion,RooRealVar* regionBinWidth){
TString RRSPdfName = Form("%s_model",region.Data());
RooRealSumPdf* RRSPdf = (RooRealSumPdf*) regionPdf->getComponents()->find(RRSPdfName);
RooArgList RRSComponentsList = RRSPdf->funcList();
RooLinkedListIter iter = RRSComponentsList.iterator() ;
RooProduct* component;
vector<double> compFracVec;
compFracVec.clear();
while( (component = (RooProduct*) iter.Next())) {
TString componentName = component->GetName();
double componentFrac = GetComponentFrac(w,componentName,RRSPdfName,obsRegion,regionBinWidth) ;
compFracVec.push_back(componentFrac);
}
return compFracVec;
}
/*
* Adopted from: RooAbsReal::GetPropagatedError()
* by Wouter Verkerke
* See: http://root.cern.ch/root/html534/src/RooAbsReal.h.html
* (http://roofit.sourceforge.net/license.txt)
*/
//_____________________________________________________________________________
double Util::GetPropagatedError(RooAbsReal* var, const RooFitResult& fr, const bool& doAsym)
{
Logger << kDEBUG << " GPP for variable = " << var->GetName() << GEndl;
// Clone self for internal use
RooAbsReal* cloneFunc = var; //(RooAbsReal*) var->cloneTree();
RooArgSet* errorParams = cloneFunc->getObservables(fr.floatParsFinal()) ;
RooArgSet* nset = cloneFunc->getParameters(*errorParams) ;
// Make list of parameter instances of cloneFunc in order of error matrix
RooArgList paramList ;
const RooArgList& fpf = fr.floatParsFinal() ;
vector<int> fpf_idx ;
for (Int_t i=0 ; i<fpf.getSize() ; i++) {
RooAbsArg* par = errorParams->find(fpf[i].GetName()) ;
if (par ) {
if (! par->isConstant() ) {
paramList.add(*par) ;
fpf_idx.push_back(i) ;
}
}
}
vector<Double_t> plusVar, minusVar ;
TMatrixDSym V( fr.covarianceMatrix() ) ;
for (Int_t ivar=0 ; ivar<paramList.getSize() ; ivar++) {
RooRealVar& rrv = (RooRealVar&)fpf[fpf_idx[ivar]] ;
int newI = fpf_idx[ivar];
Double_t cenVal = rrv.getVal() ;
Double_t errHes = sqrt(V(newI,newI)) ;
Double_t errHi = rrv.getErrorHi();
Double_t errLo = rrv.getErrorLo();
Double_t errAvg = (TMath::Abs(errLo) + TMath::Abs(errHi))/2.0;
Double_t errVal = errHes;
if (doAsym) { errVal = errAvg; }
Logger << kDEBUG << " GPP: par = " << rrv.GetName() << " cenVal = " << cenVal << " errSym = " << errHes << " errAvgAsym = " << errAvg << GEndl;
// Make Plus variation
((RooRealVar*)paramList.at(ivar))->setVal(cenVal+errVal) ;
plusVar.push_back(cloneFunc->getVal(nset)) ;
// Make Minus variation
((RooRealVar*)paramList.at(ivar))->setVal(cenVal-errVal) ;
minusVar.push_back(cloneFunc->getVal(nset)) ;
((RooRealVar*)paramList.at(ivar))->setVal(cenVal) ;
}
TMatrixDSym C(paramList.getSize()) ;
vector<double> errVec(paramList.getSize()) ;
for (int i=0 ; i<paramList.getSize() ; i++) {
int newII = fpf_idx[i];
errVec[i] = sqrt(V(newII,newII)) ;
for (int j=i ; j<paramList.getSize() ; j++) {
int newJ = fpf_idx[j];
C(i,j) = V(newII,newJ)/sqrt(V(newII,newII)*V(newJ,newJ)) ;
C(j,i) = C(i,j) ;
}
}
// Make vector of variations
TVectorD F(plusVar.size()) ;
for (unsigned int j=0 ; j<plusVar.size() ; j++) {
F[j] = (plusVar[j]-minusVar[j])/2 ;
}
if(Logger.GetMinLevel() < kDEBUG) {
F.Print();
C.Print();
}
// Calculate error in linear approximation from variations and correlation coefficient
Double_t sum = F*(C*F) ;
Logger << kDEBUG << " GPP : sum = " << sqrt(sum) << GEndl;
return sqrt(sum) ;
}
//_____________________________________________________________________________
void
Util::resetAllErrors( RooWorkspace* wspace )
{
RooStats::ModelConfig* mc = Util::GetModelConfig(wspace);
if (mc==0) return;
const RooArgSet* obsSet = mc->GetObservables();
if (obsSet==0) return;
RooAbsPdf* pdf = mc->GetPdf();
if (pdf==0) return;
RooArgList floatParList = Util::getFloatParList( *pdf, *obsSet );
Util::resetError(wspace,floatParList);
}
//_____________________________________________________________________________
void
Util::resetAllValues( RooWorkspace* wspace )
{
RooStats::ModelConfig* mc = Util::GetModelConfig(wspace);
if (mc==0) return;
const RooArgSet* obsSet = mc->GetObservables();
if (obsSet==0) return;
RooAbsPdf* pdf = mc->GetPdf();
if (pdf==0) return;
RooArgList floatParList = Util::getFloatParList( *pdf, *obsSet );
Util::resetValue(wspace,floatParList);
}
//_____________________________________________________________________________
void
Util::resetAllNominalValues( RooWorkspace* wspace )
{
RooStats::ModelConfig* mc = Util::GetModelConfig(wspace);
if (mc==0) return;
const RooArgSet* gobsSet = mc->GetGlobalObservables();
if (gobsSet==0) return;
gobsSet->Print("v");
Util::resetNominalValue( wspace,*gobsSet );
}
//_____________________________________________________________________________
RooArgList
Util::getFloatParList( const RooAbsPdf& pdf, const RooArgSet& obsSet )
{
RooArgList floatParList;
const RooArgSet* pars = pdf.getParameters( obsSet );
if (pars==0) { return floatParList; }
TIterator* iter = pars->createIterator() ;
RooAbsArg* arg ;
while( (arg=(RooAbsArg*)iter->Next()) ) {
if(arg->InheritsFrom("RooRealVar") && !arg->isConstant()){
floatParList.add( *arg );
}
}
delete iter;
return floatParList;
}
//_____________________________________________________________________________
void
Util::resetError( RooWorkspace* wspace, const RooArgList& parList, const RooArgList& vetoList )
{
/// For the given workspace,
/// find the input systematic with
/// the given name and shift that
/// systematic by 1-sigma
Logger << kINFO << " starting with workspace: " << wspace->GetName() << " parList.getSize(): " << parList.getSize() << " vetoList.size() = " << vetoList.getSize() << GEndl;
TIterator* iter = parList.createIterator() ;
RooAbsArg* arg ;
while( (arg=(RooAbsArg*)iter->Next()) ) {
std::string UncertaintyName;
if(arg->InheritsFrom("RooRealVar") && !arg->isConstant()){
UncertaintyName = arg->GetName();
} else { continue; }
if ( vetoList.FindObject( UncertaintyName.c_str() )!=0 ) { continue; }
RooRealVar* var = wspace->var( UncertaintyName.c_str() );
if( ! var ) {
Logger << kERROR << "Could not find variable: " << UncertaintyName
<< " in workspace: " << wspace->GetName() << ": " << wspace
<< GEndl;
}
// Initialize
double val_hi = FLT_MAX;
double val_low = FLT_MIN;
double sigma = 0.;
bool resetRange(false);
if( UncertaintyName == "" ) {
Logger << kERROR << "No Uncertainty Name provided" << GEndl;
throw -1;
}
// If it is a standard (gaussian) uncertainty
else if( string(UncertaintyName).find("alpha")!=string::npos ){
// Assume the values are +1, -1
val_hi = 1.0;
val_low = -1.0;
sigma = 1.0;
resetRange = true;
}
// If it is Lumi:
else if( UncertaintyName == "Lumi" ) {
// Get the Lumi's constraint term:
RooGaussian* lumiConstr = (RooGaussian*) wspace->pdf("lumiConstraint");
if(!lumiConstr){
Logger << kERROR << "Could not find wspace->pdf('lumiConstraint') "
<< " in workspace: " << wspace->GetName() << ": " << wspace
<< " when trying to reset error for parameter: Lumi"
<< GEndl;
continue;
}
// Get the uncertainty on the Lumi:
RooRealVar* lumiSigma = (RooRealVar*) lumiConstr->findServer(0);
sigma = lumiSigma->getVal();
RooRealVar* nominalLumi = wspace->var("nominalLumi");
double val_nom = nominalLumi->getVal();
val_hi = val_nom + sigma;
val_low = val_nom - sigma;
resetRange = true;
}
// If it is a stat uncertainty (gamma)
else if( string(UncertaintyName).find("gamma")!=string::npos ){
// Get the constraint and check its type:
RooAbsReal* constraint = (RooAbsReal*) wspace->obj( (UncertaintyName+"_constraint").c_str() );
std::string ConstraintType ="";
if(constraint != 0){ ConstraintType=constraint->IsA()->GetName(); }
if( ConstraintType == "" ) {
Logger << kINFO << "Assuming parameter :" << UncertaintyName << ": is a ShapeFactor and so unconstrained" << GEndl;
continue;
}
else if( ConstraintType == "RooGaussian" ){
RooAbsReal* sigmaVar = (RooAbsReal*) wspace->obj( (UncertaintyName+"_sigma").c_str() );
sigma = sigmaVar->getVal();
// Symmetrize shifts
val_hi = 1 + sigma;
val_low = 1 - sigma;
resetRange = true;
}
else if( ConstraintType == "RooPoisson" ){
RooAbsReal* nom_gamma = (RooAbsReal*) wspace->obj( ("nom_" + UncertaintyName).c_str() );
double nom_gamma_val = nom_gamma->getVal();
sigma = 1/TMath::Sqrt( nom_gamma_val );
val_hi = 1 + sigma;
val_low = 1 - sigma;
resetRange = true;
}
else {
Logger << kERROR << "Strange constraint type for Stat Uncertainties: " << ConstraintType << GEndl;
throw -1;
}
} // End Stat Error
else {
// Some unknown uncertainty
Logger << kINFO << "Couldn't identify type of uncertainty for parameter: " << UncertaintyName << ". Assuming a normalization factor." << GEndl;
Logger << kINFO << "Setting uncertainty to 0.0001 before the fit for parameter: " << UncertaintyName << GEndl;
sigma = 0.0001;
val_low = var->getVal() - sigma;
val_hi = var->getVal() + sigma;
resetRange = false;
}
var->setError(abs(sigma));
if (resetRange) {
double minrange = var->getMin();
double maxrange = var->getMax();
double newmin = var->getVal() - 6.*sigma;
double newmax = var->getVal() + 6.*sigma;
if (minrange<newmin) var->setMin(newmin);
if (newmax<maxrange) var->setMax(newmax);
}
Logger << kINFO << "Uncertainties on parameter: " << UncertaintyName
<< " low: " << val_low
<< " high: " << val_hi
<< " sigma: " << sigma
<< " min range: " << var->getMin()
<< " max range: " << var->getMax()
<< GEndl;
// Done
} // end loop
delete iter ;
}
//_____________________________________________________________________________
void
Util::resetValue( RooWorkspace* wspace, const RooArgList& parList, const RooArgList& vetoList )
{
/// For the given workspace,
/// find the input systematic with
/// the given name and shift that
/// systematic by 1-sigma
TIterator* iter = parList.createIterator() ;
RooAbsArg* arg ;
while( (arg=(RooAbsArg*)iter->Next()) ) {
std::string UncertaintyName;
if(arg->InheritsFrom("RooRealVar") && !arg->isConstant()){
UncertaintyName = arg->GetName();
} else { continue; }
if ( vetoList.FindObject( UncertaintyName.c_str() )!=0 ) { continue; }
RooRealVar* var = wspace->var( UncertaintyName.c_str() );
if( ! var ) {
Logger << kERROR << "Could not find variable: " << UncertaintyName
<< " in workspace: " << wspace->GetName() << ": " << wspace
<< GEndl;
}
// Initialize
double valnom = 0.;
if( UncertaintyName == "" ) {
Logger << kERROR << "No Uncertainty Name provided" << GEndl;
throw -1;
}
// If it is a standard (gaussian) uncertainty
else if( string(UncertaintyName).find("alpha")!=string::npos ) {
valnom = 0.0;
}
// If it is Lumi:
else if( UncertaintyName == "Lumi" ) {
valnom = 1.0;
}
// If it is a stat uncertainty (gamma)
else if( string(UncertaintyName).find("gamma")!=string::npos ){
valnom = 1.0;
} // End Stat Error
else {
// Some unknown uncertainty
valnom = 1.0;
}
var->setVal(valnom);
// Done
} // end loop
delete iter ;
}
//_____________________________________________________________________________
void
Util::resetNominalValue( RooWorkspace* wspace, const RooArgSet& globSet )
{
/// For the given workspace,
/// find the input systematic with
/// the given name and shift that
/// systematic by 1-sigma
TIterator* iter = globSet.createIterator() ;
RooAbsArg* arg ;
while( (arg=(RooAbsArg*)iter->Next()) ) {
TString UncertaintyName;
if(arg->InheritsFrom("RooRealVar") && arg->isConstant()){
UncertaintyName = arg->GetName();
} else { continue; }
RooRealVar* var = wspace->var( UncertaintyName.Data() );
if( ! var ) {
Logger << kERROR << "Could not find variable: " << UncertaintyName
<< " in workspace: " << wspace->GetName() << ": " << wspace
<< GEndl;
}
// Initialize
double valnom = 0.;
if( UncertaintyName == "" ) {
Logger << kERROR << "No Uncertainty Name provided" << GEndl;
throw -1;
}
// If it is Lumi:
else if( UncertaintyName == TString("nominalLumi") ) {
valnom = 1.0;
}
// If it is a standard (gaussian) uncertainty
else if( string(UncertaintyName).find("gamma")!=string::npos ){
valnom = 1.0;
}
// If it is a standard (gaussian) uncertainty
else if ( UncertaintyName.BeginsWith("nom") ) {
valnom = 0.0;
}
var->setVal(valnom);
Logger << kDEBUG << "Now resetting: " << UncertaintyName << " to " << valnom << GEndl;
// Done
} // end loop
delete iter ;
}
//______________________________________________________________________________________________
void Util::ImportInWorkspace( RooWorkspace* wspace, TObject* obj, TString name) {
if(obj){
if(name && obj->InheritsFrom("TNamed") ) {
((TNamed*) obj)->SetName(name.Data());
((TNamed*) obj)->SetTitle(name.Data());
}
wspace->import(*obj,kTRUE) ;
}
else{
Logger << kWARNING << "Util::Import called with a NULL pointer, nothing will be imported" << GEndl;
}
// save snapshot
RooSimultaneous* pdf = (RooSimultaneous*) wspace->pdf("simPdf");
RooAbsData* data = (RooAbsData*)wspace->data("obsData");
RooArgSet* params = (RooArgSet*) pdf->getParameters(*data) ;
wspace->saveSnapshot(Form("snapshot_paramsVals_%s",name.Data()),*params);
}
//________________________________________________________________________________________________________________________________________
void Util::RemoveEmptyDataBins( RooPlot* frame){
// histname=0 means that the last RooHist is taken from the RooPlot
const char* histname = 0;
// Find histogram object
RooHist* hist = (RooHist*) frame->findObject(histname,RooHist::Class()) ;
if (!hist) {
Logger << kERROR << " Util::RemoveEmptyDataBins(" << frame->GetName() << ") cannot find histogram" << GEndl ;
return ;
}
for(Int_t i=0; i<hist->GetN(); i++){
Double_t x,y;
hist->GetPoint(i,x,y) ;
if( fabs(y)< 0.0000001 && hist->GetErrorYhigh(i) > 0.){
hist->RemovePoint(i);
if(i != hist->GetN()) --i;
}
}
return;
}
RooHist* Util::MakeRatioOrPullHist(RooAbsData *regionData, RooAbsPdf *regionPdf, RooRealVar *regionVar, bool makePull /*false*/) {
// data/pdf ratio histograms are plotted by RooPlot.ratioHist() through a dummy frame
RooPlot* frame_dummy = regionVar->frame();
regionData->plotOn(frame_dummy, RooFit::DataError(RooAbsData::Poisson));
// normalize pdf to number of expected events, not to number of events in dataset
regionPdf->plotOn(frame_dummy, RooFit::Normalization(1, RooAbsReal::RelativeExpected),
RooFit::Precision(1e-5));
if(makePull) {
//return static_cast<RooHist*>(frame_dummy->pullHist());
return static_cast<RooHist*>(frame_dummy->pullHist());
}
return static_cast<RooHist*>(frame_dummy->ratioHist());
}
//________________________________________________________________________________________________________________________________________
RooCurve* Util::MakePdfErrorRatioHist(RooAbsData* regionData, RooAbsPdf* regionPdf, RooRealVar* regionVar, RooFitResult* rFit, Double_t Nsigma){
RooPlot* frame = regionVar->frame();
regionData->plotOn(frame, RooFit::DataError(RooAbsData::Poisson));
// normalize pdf to number of expected events, not to number of events in dataset
regionPdf->plotOn(frame, Normalization(1, RooAbsReal::RelativeExpected), Precision(1e-5));
RooCurve* curveNom = (RooCurve*) frame->findObject(nullptr, RooCurve::Class()) ;
if (!curveNom) {
Logger << kERROR << "Util::MakePdfErrorRatioHist(" << frame->GetName() << ") cannot find curveNom" << curveNom->GetName() << GEndl ;
return 0 ;
}
if(rFit != NULL) {
regionPdf->plotOn(frame, Normalization(1, RooAbsReal::RelativeExpected),
Precision(1e-5),
FillColor(kBlue-5),
FillStyle(3004),
VisualizeError(*rFit, Nsigma));
}
// Find curve object
RooCurve* curveError = (RooCurve*) frame->findObject(nullptr, RooCurve::Class()) ;
if (!curveError) {
Logger << kERROR << "Util::makePdfErrorRatioHist(" << frame->GetName() << ") cannot find curveError" << GEndl ;
return 0 ;
}
RooCurve* ratioBand = new RooCurve ;
ratioBand->SetName(Form("%s_ratio_errorband", curveNom->GetName())) ;
ratioBand->SetLineWidth(1) ;
ratioBand->SetLineColor(kBlue-5);
ratioBand->SetFillColor(kBlue-5);
ratioBand->SetFillStyle(3004);
Int_t j = 0;
Bool_t bottomCurve = kFALSE;
for(Int_t i=1; i < curveError->GetN()-1; ++i){
Double_t x = 0.;
Double_t y = 0.;
curveError->GetPoint(i, x, y) ;
// errorBand curve has twice as many points as does a normal/nominal (pdf) curve
// first it walks through all +1 sigma points (topCurve), then the -1 sigma points (bottomCurve)
// to divide the errorCurve by the pdfCurve, we need to count back for the pdfCurve once we're in the middle of errorCurve
if( i >= (curveNom->GetN()-1) ) bottomCurve = kTRUE;
Double_t xNom = x;
Double_t yNom = y;
// each errorCurve has two more points just outside the plot, so we need to treat them separately
if( i == (curveNom->GetN() - 1) || i == curveNom->GetN() ){
ratioBand->addPoint(x, 0.);
continue;
}
if( bottomCurve){
curveNom->GetPoint(j,xNom,yNom);
j--;
} else {
j++;
curveNom->GetPoint(j,xNom,yNom);
}
// only divide by yNom if it is non-zero
if( fabs(yNom) > 0.00001 ){
ratioBand->addPoint(x, (y / yNom));
} else {
ratioBand->addPoint(x, 0.);
}
}
return ratioBand;
}
//_____________________________________________________________________________
void Util::SetPdfParError(RooWorkspace* w, double Nsigma){
RooStats::ModelConfig* mc = Util::GetModelConfig(w);
if (mc==0) return;
const RooArgSet* obsSet = mc->GetObservables();
if (obsSet==0) return;
RooAbsPdf* pdf = mc->GetPdf();
if (pdf==0) return;
RooArgList floatParList = Util::getFloatParList( *pdf, *obsSet );
TIterator* iter = floatParList.createIterator() ;
RooAbsArg* arg ;
while( (arg=(RooAbsArg*)iter->Next()) ) {
TString parName;
if(arg->InheritsFrom("RooRealVar") && !arg->isConstant()){
parName = arg->GetName();
} else { continue; }
RooRealVar* par = (RooRealVar*) w->var(parName.Data());
Double_t cenVal = par->getVal();
Double_t errVal = par->getError();
par->setVal(cenVal + Nsigma * errVal);
}
}
//_____________________________________________________________________________
RooAbsReal* Util::CreateNLL( RooWorkspace* w, TString fitRegions, Bool_t lumiConst)
{
if(w==NULL){
Logger << kERROR << "Workspace not found, no fitting performed" << GEndl;
return NULL;
}
RooSimultaneous* pdf = (RooSimultaneous*) w->pdf("simPdf");
RooAbsData* data = (RooAbsData*)w->data("obsData") ;
RooCategory* regionCat = (RooCategory*) w->cat("channelCat");
data->table(*((RooAbsCategory*)regionCat))->Print("v");
if (lumiConst) {
RooRealVar* lumi = (RooRealVar*) w->var("Lumi");
if (lumi!=NULL) lumi->setConstant(lumiConst);
}
// Construct an empty simultaneous pdf using category regionCat as index
RooSimultaneous* simPdfFitRegions = pdf;
RooDataSet* dataFitRegions = (RooDataSet*) data;
std::vector<TString> fitRegionsVec = GetRegionsVec(fitRegions, regionCat);
unsigned int numFitRegions = fitRegionsVec.size();
std::vector<RooDataSet*> dataVec;
std::vector<RooAbsPdf*> pdfVec;
for(unsigned int iVec=0; iVec<numFitRegions; iVec++){
TString regionCatLabel = fitRegionsVec[iVec];
if( regionCat->setLabel(regionCatLabel,kTRUE)){
Logger << kWARNING << " Label '" << regionCatLabel << "' is not a state of channelCat (see Table) " << GEndl;
} else{
// dataset for each channel/region/category
TString dataCatLabel = Form("channelCat==channelCat::%s",regionCatLabel.Data());
RooDataSet* regionData = (RooDataSet*) data->reduce(dataCatLabel.Data());
dataVec.push_back(regionData);
// pdf for each channel/region/category
RooAbsPdf* regionPdf = (RooAbsPdf*) pdf->getPdf(regionCatLabel.Data());
pdfVec.push_back(regionPdf);
}
}
if(dataVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN DATASET, NO FIT WILL BE PERFORMED" << GEndl;
return 0;
}
else if(pdfVec.empty()){
Logger << kERROR << " NONE OF THE REGIONS ARE SPECIFIED IN SIMULTANEOUS PDF, NO FIT WILL BE PERFORMED" << GEndl;
return 0;
}
else{
// Construct a simultaneous dataset for all fit regions
dataFitRegions = (RooDataSet*) dataVec[0]->Clone("dataFitRegions");
for(unsigned int jVec=1; jVec<dataVec.size(); jVec++){
dataFitRegions->append(*dataVec[jVec]);
}
// Construct a simultaneous pdf using category regionCat as index
simPdfFitRegions = new RooSimultaneous("simPdfFitRegions","simultaneous pdf only for fit regions",*regionCat) ;
for(unsigned int kVec=0; kVec<pdfVec.size(); kVec++){
simPdfFitRegions->addPdf(*pdfVec[kVec],fitRegionsVec[kVec].Data());
}
}
RooAbsPdf* pdf_FR = simPdfFitRegions;
RooDataSet* data_FR = dataFitRegions;
RooStats::ModelConfig* mc = Util::GetModelConfig( w );
const RooArgSet* globObs = mc->GetGlobalObservables();
RooAbsReal* nll = (RooNLLVar*) pdf_FR->createNLL(*data_FR, RooFit::GlobalObservables(*globObs) );
return nll;
}
TString
Util::scanStrForFloats(const TString& toscan, const TString& format)
{
int narg1 = format.CountChar('%');
TString wsid;
std::vector<float> wsarg(10);
int narg2 = sscanf( toscan.Data(), format.Data(), &wsarg[0],&wsarg[1],&wsarg[2],&wsarg[3],&wsarg[4],&wsarg[5],&wsarg[6],&wsarg[7],&wsarg[8],&wsarg[9] );
if ( !(narg1==narg2 && narg2>0) ) {
Logger << kERROR << "Util::scanStringForFloats incorrect lengths" << GEndl;
return wsid;
}
wsarg.resize(narg2);
wsid.Clear(); // form unique ws id
for (int i=0; i<narg2; ++i) {
if (i!=0) wsid += "_" ;
wsid += Form("%.0f", wsarg[i] );
}
return wsid;
}
//---------------------------------------------------------------------------------------
TGraph* Util::getErrorBand(TH1F* hNom, TH1F* hHigh, TH1F* hLow){
vector<double> nom(0), high(0), low(0);
vector<double> X(0), ErrXl(0), ErrXh(0);
for(int i=1;i<=hNom->GetNbinsX();i++){
X.push_back(hNom->GetBinCenter(i));
ErrXl.push_back(hNom->GetBinWidth(i)/2);
ErrXh.push_back(hNom->GetBinWidth(i)/2);
nom.push_back(hNom->GetBinContent(i));
//case in which high > nominal and nominal > low
if(hHigh->GetBinContent(i)>hNom->GetBinContent(i) && hNom->GetBinContent(i)>hLow->GetBinContent(i)){
high.push_back(hHigh->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(hNom->GetBinContent(i)-hLow->GetBinContent(i));
}
//case in which low > nominal and nominal > high
else if(hLow->GetBinContent(i)>hNom->GetBinContent(i) && hNom->GetBinContent(i)>hHigh->GetBinContent(i)){
high.push_back(hLow->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(hNom->GetBinContent(i)-hHigh->GetBinContent(i));
}
//case in which low and high > nominal
else if(hLow->GetBinContent(i)>hNom->GetBinContent(i) && hHigh->GetBinContent(i)>hNom->GetBinContent(i)){
if(hHigh->GetBinContent(i)>=hLow->GetBinContent(i)){
high.push_back(hHigh->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(0.);
}
else{
high.push_back(hLow->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(0.);
}
}
//case in which low and high < nominal
else if(hLow->GetBinContent(i)<hNom->GetBinContent(i) && hHigh->GetBinContent(i)<hNom->GetBinContent(i)){
if(hHigh->GetBinContent(i)>=hLow->GetBinContent(i)){
high.push_back(0.);
low.push_back(hNom->GetBinContent(i)-hLow->GetBinContent(i));
}
else{
high.push_back(0.);
low.push_back(hNom->GetBinContent(i)-hHigh->GetBinContent(i));
}
}
//all other cases
else{
if(hNom->GetBinContent(i) == hHigh->GetBinContent(i)){
if(hNom->GetBinContent(i)>hLow->GetBinContent(i)){
high.push_back(0.);
low.push_back(hNom->GetBinContent(i)-hLow->GetBinContent(i));
}
else{
high.push_back(hLow->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(0.);
}
}
else{
if(hNom->GetBinContent(i)>hHigh->GetBinContent(i)){
high.push_back(0.);
low.push_back(hNom->GetBinContent(i)-hHigh->GetBinContent(i));
}
else{
high.push_back(hHigh->GetBinContent(i)-hNom->GetBinContent(i));
low.push_back(0);
}
}
}
}
TGraph* g = new TGraph();
for(unsigned int i=0;i<X.size();i++){
g->SetPoint(2*i,X[i]-ErrXl[i],nom[i]+high[i]);
g->SetPoint(2*i+1,X[i]+ErrXh[i],nom[i]+high[i]);
}
int Ntmp = g->GetN();
for(unsigned int i=0;i<X.size();i++){
g->SetPoint(Ntmp+2*i,X[X.size()-1-i]+ErrXh[X.size()-1-i],nom[X.size()-1-i]-low[X.size()-1-i]);
g->SetPoint(Ntmp+2*i+1,X[X.size()-1-i]-ErrXl[X.size()-1-i],nom[X.size()-1-i]-low[X.size()-1-i]);
}
g->SetFillColor(kYellow);
return g;
}
void Util::plotDistribution(TFile* f, TString hNomName, TString Syst, TString NameSample, TString Region, TString Var){
TH1F* hNom = (TH1F*)f->Get(hNomName);
TString syst_name = Syst;
TString norm = "";
if (syst_name.EndsWith("Norm")) {
syst_name.ReplaceAll("Norm","");
norm = "Norm";
}
TString hHighName = hNomName;
hHighName.ReplaceAll("Nom",syst_name+"High");
TH1F* hHigh = (TH1F*)f->Get(hHighName+norm);
TString hLowName = hNomName;
hLowName.ReplaceAll("Nom",syst_name+"Low");
TH1F* hLow = (TH1F*)f->Get(hLowName+norm);
if(!hHigh || !hLow){
Logger << kWARNING << syst_name << " systematic (with or without normalization) has not been found " << GEndl;
return;
}
TH1F* hNomClone = (TH1F*)hNom->Clone();
for(int i=1;i<=hNomClone->GetNbinsX();i++){
if(hNom->GetBinContent(i)>0) hNomClone->SetBinError(i,hNom->GetBinError(i)/hNom->GetBinContent(i));
hNomClone->SetBinContent(i,1);
}
TH1F* hHighClone = (TH1F*)hHigh->Clone();
hHighClone->Divide(hNom);
for(int i=1;i<=hHighClone->GetNbinsX();i++){
hHighClone->SetBinError(i,0.);
}
TH1F* hLowClone = (TH1F*)hLow->Clone();
hLowClone->Divide(hNom);
for(int i=1;i<=hLowClone->GetNbinsX();i++){
hLowClone->SetBinError(i,0.);
}
for(int i=1;i<=hNom->GetNbinsX();i++){
if(hNom->GetBinContent(i)<=0){
if(hLow->GetBinContent(i)<=0 && hHigh->GetBinContent(i)<=0){
hLowClone->SetBinContent(i,1.);
hHighClone->SetBinContent(i,1);
}
else if(hLow->GetBinContent(i)<=0 && hHigh->GetBinContent(i)>0) hHighClone->SetBinContent(i,10);
else if(hLow->GetBinContent(i)>0 && hHigh->GetBinContent(i)<=0) hLowClone->SetBinContent(i,10);
else{
if(hHigh->GetBinContent(i)>hLow->GetBinContent(i)){
hHighClone->SetBinContent(i,10);
hLowClone->SetBinContent(i,1.);
}
else{
hLowClone->SetBinContent(i,10);
hHighClone->SetBinContent(i,1.);
}
}
}
}
TCanvas* c = new TCanvas(NameSample+"_"+Syst+"Syst_"+Region+"_Dist",NameSample+" "+Syst+" Syst ("+Region+") Dist",600,400);
TPad* pad1 = new TPad("pad1","pad1",0.0,0.3,1.0,1.0,0);
pad1->Draw();
pad1->cd();
TLegend* leg = new TLegend(0.65,0.7,0.85,0.85,"");
leg->SetFillStyle(0);
leg->SetFillColor(0);
leg->SetBorderSize(0);
TGraph* g = getErrorBand(hNom,hHigh,hLow);
g->SetName(Syst+" Syst");
g->SetTitle(Syst+" Syst");
g->GetXaxis()->SetTitle(Var);
g->GetYaxis()->SetTitle("Entries");
g->GetYaxis()->SetTitleSize(0.045);
leg->AddEntry(g,"","f");
g->Draw("APF2");
hNom->SetMarkerStyle(20);
leg->AddEntry(hNom,"Nom [MCStatError]","l");
hNom->Draw("samep");
hHigh->SetLineColor(kCyan-3);
hHigh->SetLineStyle(kDashed);
hHigh->SetLineWidth(2.);
leg->AddEntry(hHigh,Syst+" High","l");
hHigh->Draw("same");
hLow->SetLineColor(kMagenta-3);
hLow->SetLineStyle(kDotted);
hLow->SetLineWidth(2.);
leg->AddEntry(hLow,Syst+" Low","l");
hLow->Draw("same");
leg->Draw();
c->cd();
TPad* pad2 = new TPad("pad2","pad2",0.0,0.0,1.0,0.365,0);
pad2->SetTopMargin(0.1);
pad2->SetBottomMargin(0.2);
pad2->Draw();
pad2->cd();
TGraph* gClone = getErrorBand(hNomClone,hHighClone,hLowClone);
gClone->GetXaxis()->SetLabelSize(0.08);
gClone->GetXaxis()->SetTitleSize(0.08);
gClone->GetXaxis()->SetTitle(Var);
gClone->GetYaxis()->SetTitle("#Delta X/X[%]");
gClone->GetYaxis()->SetTitleOffset(0.5);
gClone->GetYaxis()->SetTitleSize(0.08);
gClone->GetYaxis()->SetRangeUser(0,2.);
gClone->GetYaxis()->SetLabelSize(0.06);
double minY=11., maxY=0;
for(int i=0;i<gClone->GetN();i++){
double x,y;
gClone->GetPoint(i,x,y);
if(y<minY) minY=y;
if(y>maxY) maxY=y;
}
if(maxY>2.) maxY=2.;
gClone->GetYaxis()->SetRangeUser(minY-0.01,maxY+0.01);
gClone->Draw("APF2");
hNomClone->SetMarkerStyle(20);
hNomClone->Draw("samep");
hHighClone->SetLineColor(kCyan-3);
hHighClone->SetLineStyle(kDashed);
hHighClone->SetLineWidth(2.);
hHighClone->Draw("same");
hLowClone->SetLineColor(kMagenta-3);
hLowClone->SetLineStyle(kDotted);
hLowClone->SetLineWidth(2.);
hLowClone->Draw("same");
c->SaveAs(Form("plots/%s.eps",c->GetName()));
c->SaveAs(Form("plots/%s.root",c->GetName()));
}
void Util::plotSystematics(TFile* f,TString hNomName, vector<TString> Syst, TString NameSample, TString Region, TString Var){
TH1F* h = (TH1F*)f->Get(hNomName);
if(!h) return;
float Nom = h->Integral();
const int NBins = Syst.size();
TH1F* hSystNom = new TH1F("hSystNom","hSystNom",NBins,0,NBins);
TH1F* hSystHigh = new TH1F("hSystHigh","hSystHigh",NBins,0,NBins);
TH1F* hSystLow = new TH1F("hSystLow","hSystLow",NBins,0,NBins);
for(int i=1;i<=NBins;i++){
TString syst_name = Syst[i-1];
TString norm = "";
if (syst_name.EndsWith("Norm")) {
syst_name.ReplaceAll("Norm","");
norm = "Norm";
}
hSystNom->SetBinContent(i,Nom);
TString hHighName = hNomName;
hHighName.ReplaceAll("Nom",syst_name+"High");
TH1F* hH = (TH1F*)f->Get(hHighName+norm);
TString hLowName = hNomName;
hLowName.ReplaceAll("Nom",syst_name+"Low");
TH1F* hL = (TH1F*)f->Get(hLowName+norm);
if(!hH || !hL){
Logger << kWARNING << syst_name <<" systematic (with or without normalization) has not been found" << GEndl;
hSystHigh->SetBinContent(i,Nom);
hSystLow->SetBinContent(i,Nom);
}
else{
hSystHigh->SetBinContent(i,hH->Integral());
hSystLow->SetBinContent(i,hL->Integral());
}
}
TCanvas* c = new TCanvas(NameSample+"_AllSyst_"+Region,NameSample+" All Syst ("+Region+")",600,400);
TLegend* leg = new TLegend(0.65,0.7,0.85,0.85,"");
leg->SetFillStyle(0);
leg->SetFillColor(0);
leg->SetBorderSize(0);
TGraph* g = getErrorBand(hSystNom,hSystHigh,hSystLow);
g->SetName("Syst");
g->SetTitle("Syst");
g->GetHistogram()->GetXaxis()->Set(NBins,0,NBins);
for(int i=1;i<=NBins;i++) g->GetHistogram()->GetXaxis()->SetBinLabel(i,Syst[i-1]);
g->GetXaxis()->SetTitle(Var);
g->GetYaxis()->SetTitle("Entries");
g->GetYaxis()->SetTitleOffset(1.25);
leg->AddEntry(g,"","f");
g->Draw("APF2");
hSystNom->SetLineWidth(2.);
leg->AddEntry(hSystNom,"Nom","l");
hSystNom->Draw("same");
hSystHigh->SetLineColor(kCyan-3);
hSystHigh->SetLineStyle(kDashed);
hSystHigh->SetLineWidth(2.);
leg->AddEntry(hSystHigh,"High Syst","l");
hSystHigh->Draw("same");
hSystLow->SetLineColor(kMagenta-3);
hSystLow->SetLineStyle(kDotted);
hSystLow->SetLineWidth(2.);
leg->AddEntry(hSystLow,"Low Syst","l");
hSystLow->Draw("same");
leg->Draw();
c->SaveAs(Form("plots/%s.eps",c->GetName()));
c->SaveAs(Form("plots/%s.root",c->GetName()));
}
void Util::plotUpDown(TString FileName, TString NameSample, TString SystName, TString Region, TString Var){
TFile* f = TFile::Open(FileName.Data(), "READ");
if (f->IsZombie()) {
Logger << kERROR << "Cannot open file: " << FileName << GEndl;
return;
}
f->cd();
//Loading the nominal histo
TString hNomName = "h"+NameSample+"Nom_"+Region+"_obs_"+Var;
int NBins = -1;
TH1F* h = (TH1F*)f->Get(hNomName);
if(h!=0) NBins = h->GetNbinsX();
delete h;
//Taking systematic labels
if(NBins>0){
vector<TString> Syst(0);
TObjArray* Obj = SystName.Tokenize(",");
if(Obj->LastIndex()>-1){
for(int i=0;i<=Obj->GetLast();i++) Syst.push_back(((TObjString*)Obj->At(i))->String());
}
else{
Syst.push_back(SystName);
}
if(NBins>0){
for(unsigned int i=0;i<Syst.size();i++) plotDistribution(f,hNomName,Syst[i],NameSample,Region,Var);
}
plotSystematics(f,hNomName,Syst,NameSample,Region,Var);
}
else Logger << kWARNING << " No nominal histogram for " << NameSample << GEndl;
//f->Close();
//delete f;
}
//-------------------------------------------------------------------------------------------------------
void Util::PlotFitParameters(RooFitResult* r, TString anaName){
RooArgList ListParams = r->floatParsFinal();
vector<TString> alpha_parNames, mcstat_parNames, mu_parNames;
vector<double> N, errN;
vector<double> alpha_parVals,alpha_parHighErrors,alpha_parLowErrors;
vector<double> mcstat_parVals,mcstat_parHighErrors,mcstat_parLowErrors;
vector<double> mu_parVals,mu_parHighErrors,mu_parLowErrors;
int count=0;
for(int i=0;i<ListParams.getSize();i++){
RooRealVar* x = (RooRealVar*) ListParams.at(ListParams.getSize()-i-1);
//cout<<x->GetName()<<" "<<x->getVal()<<" +- "<<x->getAsymErrorHi()<<" "<<x->getAsymErrorLo()<<endl;
TString tmpName = x->GetName();
if(tmpName.Contains("alpha")){
tmpName.ReplaceAll("alpha","#alpha");
count+=2;
alpha_parNames.push_back(tmpName);
alpha_parVals.push_back(x->getVal());
alpha_parHighErrors.push_back(x->getAsymErrorHi());
if(x->getAsymErrorLo()!=0) alpha_parLowErrors.push_back(fabs(x->getAsymErrorLo()));
else alpha_parLowErrors.push_back(x->getAsymErrorHi());
N.push_back(count);
errN.push_back(0);
}else if(tmpName.Contains("Lumi") || tmpName.Contains("mcstat") || tmpName.Contains("gamma_stat")){
tmpName.ReplaceAll("gamma_shape_mcstat","#gamma");
tmpName.ReplaceAll("gamma_stat","#gamma");
count+=2;
mcstat_parNames.push_back(tmpName);
mcstat_parVals.push_back(x->getVal()-1);
mcstat_parHighErrors.push_back(x->getAsymErrorHi());
if(x->getAsymErrorLo()!=0) mcstat_parLowErrors.push_back(fabs(x->getAsymErrorLo()));
else mcstat_parLowErrors.push_back(x->getAsymErrorHi());
N.push_back(count);
errN.push_back(0);
}else{
tmpName.ReplaceAll("mu","#mu");
count+=2;
mu_parNames.push_back(tmpName);
mu_parVals.push_back(x->getVal()-1);
mu_parHighErrors.push_back(x->getAsymErrorHi());
if(x->getAsymErrorLo()!=0) mu_parLowErrors.push_back(fabs(x->getAsymErrorLo()));
else mu_parLowErrors.push_back(x->getAsymErrorHi());
N.push_back(count);
errN.push_back(0);
}
}
vector<TString> parNames;
parNames.insert(parNames.end(), alpha_parNames.begin(), alpha_parNames.end());
parNames.insert(parNames.end(), mcstat_parNames.begin(), mcstat_parNames.end());
parNames.insert(parNames.end(), mu_parNames.begin(), mu_parNames.end());
vector<double> parVals, parHighErrors, parLowErrors;
parVals.insert(parVals.end(), alpha_parVals.begin(), alpha_parVals.end());
parVals.insert(parVals.end(), mcstat_parVals.begin(), mcstat_parVals.end());
parVals.insert(parVals.end(), mu_parVals.begin(), mu_parVals.end());
parHighErrors.insert(parHighErrors.end(), alpha_parHighErrors.begin(), alpha_parHighErrors.end());
parHighErrors.insert(parHighErrors.end(), mcstat_parHighErrors.begin(), mcstat_parHighErrors.end());
parHighErrors.insert(parHighErrors.end(), mu_parHighErrors.begin(), mu_parHighErrors.end());
parLowErrors.insert(parLowErrors.end(), alpha_parLowErrors.begin(), alpha_parLowErrors.end());
parLowErrors.insert(parLowErrors.end(), mcstat_parLowErrors.begin(), mcstat_parLowErrors.end());
parLowErrors.insert(parLowErrors.end(), mu_parLowErrors.begin(), mu_parLowErrors.end());
TCanvas* c_np = new TCanvas("fit_parameters","fit_parameters",1200,800);
c_np->cd();
TPad* p_np = new TPad("p_np","p_np",0,1,1,0.,0);
p_np->SetLeftMargin(0.3);
p_np->Draw();
p_np->cd();
TGraphAsymmErrors* g = new TGraphAsymmErrors(N.size(),&(parVals[0]),&(N[0]),&(parLowErrors[0]),&(parHighErrors[0]),&(errN[0]),&(errN[0]));
g->GetHistogram()->GetYaxis()->Set(count/2,1,count+1);
for(unsigned int i=1;i<=N.size();i++) g->GetHistogram()->GetYaxis()->SetBinLabel(i,parNames[i-1]);
g->GetHistogram()->GetYaxis()->SetRangeUser(1,count+1);
g->GetHistogram()->GetYaxis()->SetTickLength(0.);
g->GetHistogram()->GetYaxis()->SetLabelSize(0.035);
g->GetHistogram()->GetXaxis()->SetRangeUser(-1.5,1.5);
g->GetHistogram()->GetXaxis()->SetTitle("#alpha");
g->SetName("fit_results");
g->SetTitle("");
g->SetMarkerStyle(8);
g->SetMarkerSize(2);
g->SetLineWidth(1);
g->Draw("AP");
vector<double> _N, _errN;
vector<double> _parVals, _parHighErrors, _parLowErrors;
for(unsigned int i=1;i<=mcstat_parVals.size()+mu_parVals.size();i++){
_N.push_back(alpha_parVals.size()*2+2*i);
_errN.push_back(0);
}
_parVals.insert(_parVals.end(), mcstat_parVals.begin(), mcstat_parVals.end());
_parVals.insert(_parVals.end(), mu_parVals.begin(), mu_parVals.end());
_parHighErrors.insert(_parHighErrors.end(), mcstat_parHighErrors.begin(), mcstat_parHighErrors.end());
_parHighErrors.insert(_parHighErrors.end(), mu_parHighErrors.begin(), mu_parHighErrors.end());
_parLowErrors.insert(_parLowErrors.end(), mcstat_parLowErrors.begin(), mcstat_parLowErrors.end());
_parLowErrors.insert(_parLowErrors.end(), mu_parLowErrors.begin(), mu_parLowErrors.end());
TGraph* _g = new TGraph(_N.size(),&(_parVals[0]),&(_N[0]));
_g->SetName("_fit_results");
_g->SetTitle("");
_g->SetMarkerStyle(8);
_g->SetMarkerColor(kBlue);
_g->SetMarkerSize(2);
_g->Draw("Psame");
TGraph* yMCstatBand = new TGraph();
yMCstatBand->SetPoint(0,-1,0);
yMCstatBand->SetPoint(1,-1,count+2);
yMCstatBand->SetPoint(2,1,count+2);
yMCstatBand->SetPoint(3,1,0);
yMCstatBand->SetFillColor(kYellow);
yMCstatBand->SetFillStyle(3352);
TLine* lMCstat = new TLine(0,1,0,count+1);
lMCstat->SetLineStyle(8);
c_np->Update();
TGaxis *axis1 = new TGaxis(p_np->GetUxmin(),p_np->GetUymax(),p_np->GetUxmax(),p_np->GetUymax(),p_np->GetUxmin()+1,p_np->GetUxmax()+1,510,"-L");
axis1->SetLineColor(kBlue);
axis1->SetLabelColor(kBlue);
axis1->SetTitle("#gamma / #mu");
axis1->SetTitleColor(kBlue);
axis1->Draw("same");
yMCstatBand->Draw("Fsame");
lMCstat->Draw("same");
g->Draw("Psame");
_g->Draw("Psame");
c_np->SaveAs("results/"+anaName+"/"+c_np->GetName()+".root");
}
//-------------------------------------------------------------------------------------------------------
TH1* Util::ComponentToHistogram(RooRealSumPdf* component, RooRealVar* variable, RooFitResult *fitResult) {
// Build a TH1-based histogram from a pdf, an observable and a fit result
// Get the stepsize and build a histogram according to the binning of the variable
auto stepsize = variable->getBinning().averageBinWidth();
auto hist = component->createHistogram(Form("hist_%s", component->GetName()), *variable);
// Now loop over the bins and fill them
for(int i=0; i < hist->GetNbinsX()+2; ++i) {
auto low = hist->GetBinLowEdge(i);
auto width = hist->GetBinWidth(i);
// Constraint the observable to this bin
variable->setRange(Form("bin%d", i), low, low+width);
// Start by integrating in this bin
auto integral = component->createIntegral(RooArgSet(*variable), RooFit::Range(Form("bin%d", i)) );
// Now get the value and the error
auto sum = integral->getVal() / stepsize;
auto err = integral->getPropagatedError(*fitResult) / stepsize;
// and put them in the histogram
hist->SetBinContent(i, sum);
hist->SetBinError(i, err);
}
auto sum = component->createIntegral(RooArgSet(*variable))->getVal();
double scale = 0.0;
if(sum != 0 && hist->Integral() != 0) {
scale = sum / hist->Integral();
}
hist->Scale(scale);
return hist;
}
void Util::ScaleGraph(TGraphAsymmErrors *g, TH1* h) {
if (g->GetN() != h->GetNbinsX() ) {
Logger << kERROR << "Cannot multiply graph with " << g->GetN() << " points with histogram with " << h->GetNbinsX() << " points" << GEndl ;
throw 1 ;
}
for(int i=0; i < g->GetN(); ++i) {
// TGraphs are 0-indexed, TH1s are 1-indexed.
int j = i+1;
double x, y;
g->GetPoint(i, x, y);
g->SetPoint(i, x, y * h->GetBinContent(j));
g->SetPointEYhigh(i, g->GetErrorYhigh(i) * h->GetBinContent(j));
g->SetPointEYlow(i, g->GetErrorYlow(i) * h->GetBinContent(j));
}
return;
}
void Util::plotInterpolationScheme(RooWorkspace *w) {
RooAbsData* data = w->data("obsData");
RooArgSet funcs = w->allFunctions();
TIterator* iter = funcs.createIterator() ;
gDirectory->pwd();
TDirectory* currentDir = gDirectory->CurrentDirectory();
TFile* interpFile = new TFile("interpolation/interpFile.root","RECREATE");
interpFile->cd();
gStyle->SetOptStat(0);
gStyle->SetOptTitle(0);
RooAbsArg* parg(0);
while((parg=(RooAbsArg*)iter->Next())) {
if ( parg->ClassName()!=TString("PiecewiseInterpolation") ) { continue; }
PiecewiseInterpolation* p = (PiecewiseInterpolation*)w->function( parg->GetName() );
p->printAllInterpCodes();
const RooArgList paramList = p->paramList();
const RooArgSet* observables = p->getObservables(data);
TString obsName = TString( observables->contentsString() );
TString sampleName= TString( parg->GetName() );
for (int iParam = 0; iParam < paramList.getSize(); iParam++){
TString parNameTemp = TString( paramList.at(iParam)->GetName() );
TCanvas tempc(obsName+sampleName+parNameTemp,obsName+sampleName+parNameTemp,600,600);
tempc.cd();
TH2D* tempHisto = (TH2D*) p->createHistogram(obsName+","+parNameTemp);
int nominalBin = tempHisto->GetYaxis()->FindBin(0.);
TH1D* nominalHisto = tempHisto->ProjectionX(obsName+sampleName+parNameTemp+"nominal",nominalBin,nominalBin);
nominalHisto->Write();
tempHisto->Draw("SURF");
tempc.Print("interpolation/"+sampleName+"_"+obsName+"_"+parNameTemp+".pdf");
tempHisto->Write();
for (int iBin = 1; iBin <= tempHisto->GetNbinsX(); iBin++){
TString projectionName = obsName+sampleName+parNameTemp + std::to_string(iBin).c_str();
TH1D* projectionY = tempHisto->ProjectionY(projectionName,iBin,iBin);
TCanvas tempcProj(obsName+sampleName+projectionName,obsName+sampleName+projectionName,600,600);
tempcProj.SetBottomMargin(0.15);
tempcProj.SetLeftMargin(0.2);
tempcProj.cd();
projectionY->Draw("line");
projectionY->GetXaxis()->SetTitle(parNameTemp);
projectionY->GetXaxis()->SetTitleOffset(1.5);
projectionY->GetXaxis()->SetRangeUser(-2,2);
projectionY->GetYaxis()->SetTitle(obsName+" bin "+std::to_string(iBin).c_str());
projectionY->GetYaxis()->SetTitleOffset(2.5);
// Draw lines
tempcProj.Update();
double ymax = gPad->GetUymax();
double ymin = gPad->GetUymin();
double xmax = gPad->GetUxmax();
double xmin = gPad->GetUxmin();
double nominalVal = (projectionY->GetBinContent(projectionY->FindBin(0))+projectionY->GetBinContent(projectionY->FindBin(0)-1))/2.;
TLine* line1 = new TLine(-1,ymin,-1,ymax);
TLine* line2 = new TLine(1,ymin,1,ymax);
TLine* line3 = new TLine(0,ymin,0,ymax);
TLine* line4 = new TLine(xmin,nominalVal,xmax,nominalVal);
line1->Draw();
line2->Draw();
line3->Draw();
line4->Draw();
projectionY->Draw("line same");
projectionY->SetLineWidth(2);
// Save canvas
if (tempHisto->GetNbinsX()==1)
tempcProj.Print("interpolation/"+sampleName+"_"+obsName+"_"+parNameTemp+"_perBin.pdf");
else if (iBin==1)
tempcProj.Print("interpolation/"+sampleName+"_"+obsName+"_"+parNameTemp+"_perBin.pdf(");
else if (iBin>1 && iBin <tempHisto->GetNbinsX())
tempcProj.Print("interpolation/"+sampleName+"_"+obsName+"_"+parNameTemp+"_perBin.pdf");
else
tempcProj.Print("interpolation/"+sampleName+"_"+obsName+"_"+parNameTemp+"_perBin.pdf)");
projectionY->Write();
}
}
}
interpFile->Close();
currentDir->cd();
}
|
;
; Copyright (C) 2019 Assured Information Security, Inc.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in all
; copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
bits 64
default rel
%define IA32_XSS_MSR 0xDA0
%define VMCS_GUEST_RSP 0x0000681C
%define VMCS_GUEST_RIP 0x0000681E
global vmcs_launch:function
section .text
; Launch VMCS
;
; Launch the execution of a VMCS. Note that this function should not return.
; If it does, an error has occurred.
;
vmcs_launch:
push rbx
push r12
push r13
push r14
push r15
push rbp
mov rsi, [rdi + 0x108]
mov dr6, rsi
mov rsi, [rdi + 0x100]
mov dr3, rsi
mov rsi, [rdi + 0x0F8]
mov dr2, rsi
mov rsi, [rdi + 0x0F0]
mov dr1, rsi
mov rsi, [rdi + 0x0E8]
mov dr0, rsi
mov rsi, [rdi + 0x0E0]
mov cr8, rsi
mov rsi, [rdi + 0x0D8]
mov cr2, rsi
; See the exit handler and resume logic for comments. Note that we do
; add one thing here which is we have to tell xrstors that the save
; area is compressed. When the launch occurs, it is likely that a guest
; is being started for the first time (but not always, as is the case
; with VMCS migration and sleep/resume). When this happens, xsaves has
; not been run on the save area, which means it has not been properly
; configured to be used with xrstors (not sure why Intel didn't include
; an init instruction for xsave, but this basically emulates it).
mov rsi, [rdi + 0x0C8]
mov al, 0x80
mov [rsi + 0x20f], al
xor edx, edx
mov eax, 0xFFFFFFFF
xrstors64 [rsi]
mov eax, [rdi + 0x0B8]
xor edx, edx
mov ecx, IA32_XSS_MSR
wrmsr
mov eax, [rdi + 0x0A8]
xor edx, edx
xor ecx, ecx
xsetbv
mov rsi, VMCS_GUEST_RSP
vmwrite rsi, [rdi + 0x080]
mov rsi, VMCS_GUEST_RIP
vmwrite rsi, [rdi + 0x078]
mov r15, [rdi + 0x070]
mov r14, [rdi + 0x068]
mov r13, [rdi + 0x060]
mov r12, [rdi + 0x058]
mov r11, [rdi + 0x050]
mov r10, [rdi + 0x048]
mov r9, [rdi + 0x040]
mov r8, [rdi + 0x038]
mov rsi, [rdi + 0x028]
mov rbp, [rdi + 0x020]
mov rdx, [rdi + 0x018]
mov rcx, [rdi + 0x010]
mov rbx, [rdi + 0x008]
mov rax, [rdi + 0x000]
mov rdi, [rdi + 0x030]
vmlaunch
pop rbp
pop r15
pop r14
pop r13
pop r12
pop rbx
; We should never get this far. If we do, it's because the launch failed. If
; happens, we return so that we can throw an exception and tell the user that
; something really bad happened.
ret
|
; A288381: Fixed point of the mapping 00->0001, 1->11, starting with 00.
; 0,0,0,1,0,1,1,0,1,1,1,1,0,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
add $0,2
mov $2,5
lpb $0
add $3,$2
trn $3,$0
add $0,4
trn $0,$3
mov $1,5
sub $2,2
mul $2,2
mov $4,$0
add $4,1
mov $0,$4
trn $0,6
sub $1,$4
trn $1,3
lpe
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r15
push %r8
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0xc39e, %rbp
cmp %rdi, %rdi
movups (%rbp), %xmm4
vpextrq $1, %xmm4, %rsi
nop
sub %rsi, %rsi
lea addresses_UC_ht+0x1993a, %rsi
lea addresses_WC_ht+0x559e, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
dec %r8
mov $69, %rcx
rep movsb
nop
nop
nop
sub $32829, %rbp
lea addresses_D_ht+0x1719e, %r15
nop
nop
nop
inc %r8
mov $0x6162636465666768, %rsi
movq %rsi, (%r15)
nop
cmp $21847, %rsi
lea addresses_WC_ht+0xd12c, %rcx
nop
nop
nop
nop
cmp %rsi, %rsi
movl $0x61626364, (%rcx)
nop
nop
nop
nop
nop
add $4065, %r15
lea addresses_WT_ht+0x57a5, %rsi
lea addresses_WC_ht+0x18c9e, %rdi
nop
nop
nop
nop
nop
xor %r10, %r10
mov $78, %rcx
rep movsq
nop
nop
nop
nop
dec %rdi
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r8
pop %r15
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r8
push %rax
push %rbp
push %rdi
// Faulty Load
lea addresses_PSE+0x1059e, %rax
nop
nop
nop
nop
sub %r8, %r8
movaps (%rax), %xmm0
vpextrq $0, %xmm0, %r13
lea oracles, %rbp
and $0xff, %r13
shlq $12, %r13
mov (%rbp,%r13,1), %r13
pop %rdi
pop %rbp
pop %rax
pop %r8
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'AVXalign': False, 'congruent': 0, 'size': 32, 'same': False, 'NT': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'AVXalign': True, 'congruent': 0, 'size': 16, 'same': True, 'NT': False}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'AVXalign': False, 'congruent': 9, 'size': 16, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 11, 'same': True}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'congruent': 10, 'size': 8, 'same': False, 'NT': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'congruent': 0, 'size': 4, 'same': False, 'NT': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 7, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
section .text
global rotate
rotate:
mov r10, rdx
xor rcx, rcx
mov r11, 26
mov r12, 'a'
mov r13, 'A'
loop:
xor rax, rax
xor rbx, rbx
xor rdx, rdx
mov al, byte [rdi+rcx]
test al, al
jz end
mov r14, rax
call is_lower
cmovbe rbx, r12
mov r14, rax
call is_upper
cmovbe rbx, r13
test rbx, rbx
jz continue
sub al, bl
add rax, rsi
div r11
mov rax, rdx
add al, bl
continue:
mov byte [r10+rcx], al
inc rcx
jmp loop
end:
mov byte [r10+rcx], 0
ret
is_lower:
sub r14, 'a'
cmp r14, 25
ret
is_upper:
sub r14, 'A'
cmp r14, 25
ret
|
;PUC-ECEC-CMP1057-ARQ1-
;12/02/19
;Wellington Junio De Melo Fernandes
;
;Segundo Programa print.asm
segment .data
;dados inicializados
mens db "Adeus mundo cruel",10,10,"é mentira hahaha",10,10
tamm equ $-mens ; tamm=constante ao ponto que estou no caso 18 - a quantidade de palavras do vetor anterior
segment .text
global _start
_start:
print:
mov edx,tamm ;quantidade de caracteres, no caso ele imprime o tamanho armazenado em tamm
mov ecx,mens ;ponteiro da string
mov ebx,0 ;FD monitor
mov eax,4 ;Serviço PRINT
int 0x80 ;Kernel para executar serviço
sai:
mov eax,1 ; serviço EXIT
int 80h ;encerra (mesmo kernel para executar.. esse é o padrão)
|
.region ILI9341 COMMANDS
LCD_TFTWIDTH = 240 // ILI9341 max TFT width
LCD_TFTHEIGHT = 320 // ILI9341 max TFT height
LCD_NOP = 0x00 // No-op register
LCD_SWRESET = 0x01 // Software reset register
LCD_RDDID = 0x04 // Read display identification information
LCD_RDDST = 0x09 // Read Display Status
LCD_SLPIN = 0x10 // Enter Sleep Mode
LCD_SLPOUT = 0x11 // Sleep Out
LCD_PTLON = 0x12 // Partial Mode ON
LCD_NORON = 0x13 // Normal Display Mode ON
LCD_RDMODE = 0x0a // Read Display Power Mode
LCD_RDMADCTL = 0x0b // Read Display MADCTL
LCD_RDPIXFMT = 0x0c // Read Display Pixel Format
LCD_RDIMGFMT = 0x0d // Read Display Image Format
LCD_RDSELFDIAG = 0x0f // Read Display Self-Diagnostic Result
LCD_INVOFF = 0x20 // Display Inversion OFF
LCD_INVON = 0x21 // Display Inversion ON
LCD_GAMMASET = 0x26 // Gamma Set
LCD_DISPOFF = 0x28 // Display OFF
LCD_DISPON = 0x29 // Display ON
LCD_CASET = 0x2a // Column Address Set
LCD_PASET = 0x2b // Page Address Set
LCD_RAMWR = 0x2c // Memory Write
LCD_RAMRD = 0x2e // Memory Read
LCD_PTLAR = 0x30 // Partial Area
LCD_VSCRDEF = 0x33 // Vertical Scrolling Definition
LCD_MADCTL = 0x36 // Memory Access Control
LCD_VSCRSADD = 0x37 // Vertical Scrolling Start Address
LCD_PIXFMT = 0x3a // COLMOD: Pixel Format Set
LCD_FRMCTR1 = 0xb1 // Frame Rate Control (In Normal Mode/Full Colors)
LCD_FRMCTR2 = 0xb2 // Frame Rate Control (In Idle Mode/8 colors)
LCD_FRMCTR3 = 0xb3 // Frame Rate control (In Partial Mode/Full Colors)
LCD_INVCTR = 0xb4 // Display Inversion Control
LCD_DFUNCTR = 0xb6 // Display Function Control
LCD_PWCTR1 = 0xc0 // Power Control 1
LCD_PWCTR2 = 0xc1 // Power Control 2
LCD_VMCTR1 = 0xc5 // VCOM Control 1
LCD_VMCTR2 = 0xc7 // VCOM Control 2
LCD_RDID1 = 0xda // Read ID 1
LCD_RDID2 = 0xdb // Read ID 2
LCD_RDID3 = 0xdc // Read ID 3
LCD_RDID4 = 0xdd // Read ID 4
LCD_GMCTRP1 = 0xe0 // Positive Gamma Correction
LCD_GMCTRN1 = 0xe1 // Negative Gamma Correction
LCD_EN3G = 0xf2 // Enable 3G
.endregion
.region ILI9341 PINS
PORTB_PINS = 0b00111100
PORTA_PINS = 0b11100000
SCK = 0b10000000 //
SDO = 0b01000000 //
CS = 0b00100000 //
RST = 0b00010000 //
DC = 0b00001000 //
//TCS = 0b00000100 //
//TIRQ = 0b00000010 //
.endregion
LCD_startup:
.byte LCD_PWCTR1 , 1, 0x23, // set GVDD to 4.6V
.byte LCD_PWCTR2 , 1, 0x10, // UNKNOWN
.byte LCD_VMCTR1 , 2, 0x3e, 0x28, // set VCOMH to 4.275V, VCOML to -1.5V
.byte LCD_VMCTR2 , 1, 0x86, // set nVM to 1 and VMF to VMH –58 VML –58
.byte LCD_MADCTL , 1, 0x48, // set MX and BGR
.byte LCD_VSCRSADD, 1, 0x00, // set scrolling start address to 0 (should be 2 parameters?)
.byte LCD_PIXFMT , 1, 0x55, // set RGB and MCU to 16 bits / pixel
.byte LCD_FRMCTR1 , 2, 0x00, 0x18, // sets DIVA to 0 and frame rate to 79Hz and 24 clocks/line
.byte LCD_DFUNCTR , 3, 0x08, 0x82, 0x27, // sets interval scan, REV to normally white, ISC to 5 frames, NL to 320, doesn't set PCDIV???
.byte LCD_EN3G , 1, 0x02, // disables 3G
.byte LCD_GAMMASET, 1, 0x01, // select gamma curve 1
.byte LCD_GMCTRP1 , 15, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00,
.byte LCD_GMCTRN1 , 15, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F,
.byte LCD_NOP // finish startup
lcd_begin:
// set rst high (initially held low)
// for each of LCD_startup
// if command is 0x0 then stop
// send commend to LCD over 6522 SR
// get number of params
// loop until number
// send each param
// end param loop
// end startup loop
// sleep out
// display on
shift_cmd:
//set d/c low
jmp shift_out
shift_data:
//set d/c high
shift_out:
//set cs low
//start 6522 sr using 110 phi2 clock control
//wait for irqb
//stop 6522 sr
//set cs high |
; A267596: Decimal representation of the n-th iteration of the "Rule 173" elementary cellular automaton starting with a single ON (black) cell.
; 1,2,15,63,255,1023,4095,16383,65535,262143,1048575,4194303,16777215,67108863,268435455,1073741823,4294967295,17179869183,68719476735,274877906943,1099511627775,4398046511103,17592186044415,70368744177663,281474976710655,1125899906842623,4503599627370495,18014398509481983,72057594037927935,288230376151711743,1152921504606846975,4611686018427387903,18446744073709551615,73786976294838206463,295147905179352825855,1180591620717411303423,4722366482869645213695,18889465931478580854783,75557863725914323419135,302231454903657293676543,1208925819614629174706175,4835703278458516698824703,19342813113834066795298815,77371252455336267181195263,309485009821345068724781055,1237940039285380274899124223,4951760157141521099596496895,19807040628566084398385987583,79228162514264337593543950335,316912650057057350374175801343,1267650600228229401496703205375,5070602400912917605986812821503,20282409603651670423947251286015,81129638414606681695789005144063,324518553658426726783156020576255,1298074214633706907132624082305023,5192296858534827628530496329220095,20769187434139310514121985316880383,83076749736557242056487941267521535,332306998946228968225951765070086143
mov $2,$0
lpb $2
add $0,4
sub $0,$2
pow $0,$2
sub $0,2
mov $2,1
lpe
add $0,1
|
NULL equ 0
STD_OUTPUT_HANDLE equ -11
extern GetStdhandle
extern WriteFile
extern ExitProcess
section .data
cell db 0
section .bss
StdHandle resd 1
Written resd 1
section .text
global Start
mod:
cmp ebx, 0
jl lower
ret
lower:
add ebx, 128
mov [cell], ebx
ret
Start
push STD_OUTPUT_HANDLE
call GetStdHandle
mov dword [StdHandle], eax
push NULL
call ExitProcess
|
;; @file
; IPRT - ASMGetDS().
;
;
; Copyright (C) 2006-2015 Oracle Corporation
;
; This file is part of VirtualBox Open Source Edition (OSE), as
; available from http://www.virtualbox.org. This file is free software;
; you can redistribute it and/or modify it under the terms of the GNU
; General Public License (GPL) as published by the Free Software
; Foundation, in version 2 as it comes in the "COPYING" file of the
; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
;
; The contents of this file may alternatively be used under the terms
; of the Common Development and Distribution License Version 1.0
; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
; VirtualBox OSE distribution, in which case the provisions of the
; CDDL are applicable instead of those of the GPL.
;
; You may elect to license modified versions of this file under the
; terms and conditions of either the GPL or the CDDL or both.
;
;*******************************************************************************
;* Header Files *
;*******************************************************************************
%include "iprt/asmdefs.mac"
BEGINCODE
;;
; Get the ds register.
; @returns ds.
;
BEGINPROC_EXPORTED ASMGetDS
mov eax, DS
ret
ENDPROC ASMGetDS
|
/****************************************************************************
**
** Copyright (C) 2015 The Qt Company Ltd.
** Contact: http://www.qt.io/licensing/
**
** This file is part of the test suite of the Qt Toolkit.
**
** $QT_BEGIN_LICENSE:LGPL21$
** Commercial License Usage
** Licensees holding valid commercial Qt licenses may use this file in
** accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and The Qt Company. For licensing terms
** and conditions see http://www.qt.io/terms-conditions. For further
** information use the contact form at http://www.qt.io/contact-us.
**
** GNU Lesser General Public License Usage
** Alternatively, this file may be used under the terms of the GNU Lesser
** General Public License version 2.1 or version 3 as published by the Free
** Software Foundation and appearing in the file LICENSE.LGPLv21 and
** LICENSE.LGPLv3 included in the packaging of this file. Please review the
** following information to ensure the GNU Lesser General Public License
** requirements will be met: https://www.gnu.org/licenses/lgpl.html and
** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** As a special exception, The Qt Company gives you certain additional
** rights. These rights are described in The Qt Company LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
** $QT_END_LICENSE$
**
****************************************************************************/
#include <QtTest/QtTest>
#include <QtCore/QString>
#include <QSound>
#include <QSoundEffect>
class tst_QSound : public QObject
{
Q_OBJECT
public:
tst_QSound( QObject* parent=0) : QObject(parent) {}
private slots:
void initTestCase();
void cleanupTestCase();
void testLooping();
void testPlay();
void testStop();
void testStaticPlay();
private:
QSound* sound;
};
void tst_QSound::initTestCase()
{
sound = 0;
// Only perform tests if audio device exists
QStringList mimeTypes = QSoundEffect::supportedMimeTypes();
if (mimeTypes.empty())
QSKIP("No audio devices available");
const QString testFileName = QStringLiteral("test.wav");
const QString fullPath = QFINDTESTDATA(testFileName);
QVERIFY2(!fullPath.isEmpty(), qPrintable(QStringLiteral("Unable to locate ") + testFileName));
sound = new QSound(fullPath, this);
QVERIFY(!sound->fileName().isEmpty());
QCOMPARE(sound->loops(),1);
}
void tst_QSound::cleanupTestCase()
{
if (sound)
{
delete sound;
sound = NULL;
}
}
void tst_QSound::testLooping()
{
sound->setLoops(5);
QCOMPARE(sound->loops(),5);
sound->play();
QVERIFY(!sound->isFinished());
// test.wav is about 200ms, wait until it has finished playing 5 times
QTest::qWait(3000);
QVERIFY(sound->isFinished());
QCOMPARE(sound->loopsRemaining(),0);
}
void tst_QSound::testPlay()
{
sound->setLoops(1);
sound->play();
QVERIFY(!sound->isFinished());
QTest::qWait(1000);
QVERIFY(sound->isFinished());
}
void tst_QSound::testStop()
{
sound->setLoops(10);
sound->play();
QVERIFY(!sound->isFinished());
QTest::qWait(1000);
sound->stop();
QTest::qWait(1000);
QVERIFY(sound->isFinished());
}
void tst_QSound::testStaticPlay()
{
// Check that you hear sound with static play also.
const QString testFileName = QStringLiteral("test.wav");
const QString fullPath = QFINDTESTDATA(testFileName);
QVERIFY2(!fullPath.isEmpty(), qPrintable(QStringLiteral("Unable to locate ") + testFileName));
QSound::play(fullPath);
QTest::qWait(1000);
}
QTEST_MAIN(tst_QSound);
#include "tst_qsound.moc"
|
; This update does not print a confirmation code; print one yourself.
bits 16 ; Tells NASM to assume 16-bit registers
; no org because it doesn't matter
; mul R/M (implicitly with AX): DX=high, AX=low
; div R/M (implicitly DX:AX/(R/M)): DX=remainder, AX=quotient
; Why can I never remember where the results go?
cli
cld
push word 0
pop ss
push cs
pop ds
mov ax, 7C00h ; stack area goes below bootsector
mov sp, ax
mov bp, ax
xor ax, ax
push word 0B800h ; for PrintNum
pop fs
push word 07E0h ; to search for the filename and cluster number later
pop es
mov dh, dl ; duplicating disk number for debugging
;DAP-Search= LEA of [bp-16] (segment 07BFh)
push ax ; high word of DAP - never changed
push ax ; high LBA - never changed
push ax ; mid LBA - never changed
push ax ; low LBA (-8)
push es ; segment of the mem buffer (07E0) - never changed
push ax ; offset of the mem buffer - never changed
push word 1 ; number of sectors to load - never changed
push word 16 ; size of DAP in bytes - never changed
;DAP-Loader= LEA of [bp-32] (segment 07BEh)
push ax ; high word of DAP - never changed
push ax ; high LBA - never changed
push ax ; mid LBA (-22)
push ax ; low LBA (-24)
push word 1000h ; segment of the mem buffer - never changed
push ax ; offset of the mem buffer (-28)
push ax ; number of sectors to load
push word 16 ; size of the DAP in bytes
push ax ; segment alignment for debugging
push dx ; DiskNumber=[bp-36]
mov bx, [bp+14] ; BPB_RsvdSecCnt
movzx dx, byte[bp+16] ; BPB_NumFATs
mov ax, [bp+22] ; BPB_FATSz16
mul dx
add bx, ax
push bx ; StartRoot=[bp-38]
mov ax, [bp+17] ; BPB_RootEntCnt
shl ax, 5
xor dx, dx
mov cx, [bp+11] ; BPB_BytsPerSec
div cx
push ax ; NumRootSectors=[bp-40]
add bx, ax
push bx ; StartData=[bp-42]
movzx ax, byte[bp+13] ; BPB_SecPerClus
mov [bp-30], ax ; Load into number of sectors in DAP-Loader
mul cx
push ax ; BytesPerCluster=[bp-44]
shr cx, 5
push cx ; EntriesPerSector=[bp-46]
call Filename ; Filename=[bp-48]
db 'BOOTI386BIN' ; to search for the exact filename "BOOTI386.BIN"
Filename:
;RootSearch
xor cx, cx
LoadRootSector:
push cx ; Save RootSectorsChecked
add cx, [bp-38] ; add StartRoot value
mov [bp-8], cx ; load low LBA of DAP-Search
push word 07BFh
call ReadDisk
xor cx, cx
CheckEntries:
push cx ; save EntriesChecked
shl cx, 5
mov bx, cx ; save offset for later if file found
CheckEntryForFilename:
mov si, [bp-48] ; Filename address
mov di, cx
mov cx, 11
repz cmpsb ; Compare strings in [ds:si] and [es:di]. Repeat while equal.
jcxz FileFound ; If CX is zero, the end of the strings were reached.
pop cx ; load EntriesChecked
inc cx
cmp cx, [bp-46] ; check EntriesPerSector
jne short CheckEntries
pop cx ; load RootSectorsChecked
inc cx
cmp cx, [bp-40] ; check NumRootSectors
je short FileMissing
jmp short LoadRootSector
FileMissing:
push word 0EC0Fh ; Error Code - No File
call PrintNum
FileFound:
pop ax
pop ax
; bx= Entry Offset into sector
mov al, [es:bx+11]
test al, 18h ; 10h=Directory, 08h=VolumeID
jz short FileValid
push word 0ECFDh ; Error Code - File is a Directory
call PrintNum
FileValid:
push word [es:bx+26] ; Starting Cluster Number = [bp-50]
push word [es:bx+28] ; low word of file size
mov ax, [es:bx+30] ; high word of file size
test ax, ax
jz short ProcessSize
mov word[bp-52], 0FFFFh ; if high word nonzero, set size to 64KB
ProcessSize:
pop ax
test ax, ax
jnz short SizeNonzero
push word 0ECF0h ; Error Code - Filesize is Zero
call PrintNum
SizeNonzero:
xor dx, dx
div word [bp-44] ; BytesPerCluster
inc ax ; Unlikely that dx will be zero here, so round up
mov cx, ax ; cx = NumClusters
pop bx ; bx = Cluster Number
LoadFileClusters:
mov dx, bx
dec dx
dec dx
movzx ax, byte[bp+13] ; SecPerClus
mul dx
add ax, [bp-42] ; StartData
adc dx, 0
mov [bp-24], ax ; low LBA of DAP-Loader
mov [bp-22], dx ; mid LBA of DAP-Loader
push word 07BEh
call ReadDisk
mov ax, [bp-44] ; load BytesPerCluster
add [bp-28], ax ; update DAP-Loader offset
xor dx, dx
mov ax, bx
shl ax, 1
div word[bp+11] ; BytsPerSec
add ax, [bp+14] ; RsvdSecCnt
mov bx, dx
mov [bp-8], ax ; low LBA of DAP-Search
push word 07BFh
call ReadDisk
mov bx, [es:bx] ; cluster number updated
dec cx
jnz short LoadFileClusters
sti ; enable interrupts for the loaded program
jmp 1000h:0 ; location of loaded file
;PrintWords: ; needed this for debugging
; LArrow -1 sector, RArrow +1 sector, UArrow +1 offset, DArrow -1 offset
; pop gs
; pop di
; push gs
; push ds
; pusha
; mov dx, di
; mov dx, di
; xor bx, bx
;.Print:
; mov word[bp], 0
; mov ds, dx
; mov si, bx
; push ds
; call PrintNum
; push si
; call PrintNum
; lodsw
; push ax
; call PrintNum
;.GetKey:
; xor ax, ax
; int 16h
; cmp ah, 01h
; je short .Escape
; inc bx
; cmp ah, 48h
; je short .Print
; dec bx
; dec bx
; cmp ah, 50h
; je short .Print
; inc bx
; inc dx
; cmp ah, 4Dh
; je short .Print
; dec dx
; dec dx
; cmp ah, 4Bh
; je short .Print
; inc dx
; jmp short .GetKey
;.Escape:
; pop ds
; popa
; ret
ReadDisk: ; (v2)
pop gs ; save IP
pop di ; get argument
push gs ; restore IP
push ds
pusha
mov ds, di
sti
xor si, si
mov ah, 42h ; Extended Read Disk function index
mov dx, [bp-36] ; load BIOS Disk Number
int 13h
jnc short .NoProblems
;push word 0ECDEh ; Error Code - Disk Error
mov al, ah ; move Disk Error Code to low byte
mov ah, 0DEh ; high byte is DE to indicate a Disk Error
push ax
call PrintNum
.NoProblems:
cli
popa
pop ds
ret
PrintNum:
; Assume video mem segment is in FS, CursorPos is in [bp]
pop di ; get IP out of the way
pop ax ; get the argument
push fs
pop es
mov bx, 16
mov cx, 4
.ConvertNext:
xor dx, dx
div bx
add dx, 48
cmp dx, 58
jb short .lt10
add dx, 7
.lt10:
mov dh, 0Fh
push dx
dec cx
jnz short .ConvertNext
mov cx, 4
mov di, 0
.PrintNext:
pop ax
stosw
dec cx
jnz short .PrintNext
sti ; enable interrupts for rebooting
dw 0FEEBh ; halt
|
# Si implementi la procedura subseteq così definita:
# Input: due array di interi A1 e A2
# Output: 1 se ogni elemento di A1 è presente in A2, 0 altrimenti
.text
.globl subseteq
subseteq:
subu $sp, $sp, 16
sw $s0, 12($sp)
sw $s1, 8($sp)
sw $fp, 4($sp)
sw $ra, ($sp)
addiu $fp, $sp, 12
move $s0, $a0
move $s1, $a1
move $t0, $a2
move $t1, $a3
li $v0, 1
li $t2, 0
for_subseteq: beq $t2, $t0, return
mul $t3, $t2, 4
add $t3, $t3, $s0
lw $t3, ($t3)
move $a0, $s1
move $a1, $t3
jal belongs
beqz $v0, not_found
addi $t2, $t2, 1
j for_subseteq
not_found: li $v0, 0
return: lw $ra, ($sp)
lw $fp, 4($sp)
lw $s1, 8($sp)
lw $s0, 12($sp)
addi $sp, $sp, 16
jr $ra |
;################################################################################
;# Título: Interrupt Service Routines #
;# #
;# Versión: 1.0 Fecha: 13/09/2015 #
;# Autor: Javier Balloffet Tab: 4 #
;# Compilación: #
;# Usar Makefile #
;# Uso: - #
;# ------------------------------------------------------------------------#
;# Descripción: #
;# * Rutinas de atencion de excepciones e interrupciones #
;# ------------------------------------------------------------------------#
;# Revisiones: #
;# 1.0 | 13/09/2015 | J.BALLOFFET | Inicial #
;# ------------------------------------------------------------------------#
;# TODO: #
;# - #
;################################################################################
%include "general.inc"
USE32
;********************************************************************************
; Macros
;********************************************************************************
%define MAX_SERV 4
%define MAX_TABLES 0x00113000
%define TASKIDLE 0
%define TASK1 1
%define TASK2 2
%define TASK3 3
%define CONTEXT_ESP0 0x00
%define CONTEXT_SS0 0x04
%define CONTEXT_CR3 0x08
%define CONTEXT_EIP 0x0C
%define CONTEXT_ESP3 0x10
%define CONTEXT_ES 0x14
%define CONTEXT_CS 0x18
%define CONTEXT_SS3 0x1C
%define CONTEXT_DS 0x20
%define CONTEXT_FS 0x24
%define CONTEXT_GS 0x28
%define CONTEXT_ACCESS 0x2C
%define CONTEXT_STACK0 0x30
;********************************************************************************
; Simbolos externos y globales
;********************************************************************************
GLOBAL div_error_excep0_handler
GLOBAL debug_excep1_handler
GLOBAL breakpoint_excep3_handler
GLOBAL overflow_excep4_handler
GLOBAL bound_range_excep5_handler
GLOBAL undef_opcode_excep6_handler
GLOBAL dev_not_avail_excep7_handler
GLOBAL double_fault_excep8_handler
GLOBAL invalid_tss_excep10_handler
GLOBAL segm_not_pres_excep11_handler
GLOBAL stack_segment_excep12_handler
GLOBAL gen_prot_excep13_handler
GLOBAL page_fault_excep14_handler
GLOBAL float_error_excep16_handler
GLOBAL align_check_excep17_handler
GLOBAL machine_check_excep18_handler
GLOBAL simd_float_excep19_handler
GLOBAL virtual_excep20_handler
GLOBAL tmr_int32_handler
GLOBAL key_int33_handler
GLOBAL scankeyfifo
GLOBAL counter
GLOBAL shiftflag
GLOBAL Services
GLOBAL Task1SleepTime
GLOBAL Task2SleepTime
GLOBAL Task3SleepTime
EXTERN krn_print_screen ; definidos en lib32.asm
EXTERN krn_clear_screen
EXTERN PDPTE ; definidos en sys_tables.asm
EXTERN DS_SEL_KER
EXTERN TSS_INIT_SEL
EXTERN Task1State
EXTERN Task2State
EXTERN Task3State
EXTERN Task1Priority
EXTERN Task2Priority
EXTERN Task3Priority
EXTERN selector_nueva_tarea
EXTERN nueva_tarea
EXTERN service_print_screen ; definidos en services.asm
EXTERN service_scan_key
EXTERN service_sleep
EXTERN service_time
EXTERN CurrentTask
EXTERN ContextsList
EXTERN TSS_INIT
;********************************************************************************
; Datos
;********************************************************************************
SECTION .data
msgHandler0 db "Excepcion 0: Division por cero", NULL
msgHandler1 db "Excepcion 1: Debug", NULL
msgHandler3 db "Excepcion 3: Breakpoint", NULL
msgHandler4 db "Excepcion 4: Overflow", NULL
msgHandler5 db "Excepcion 5: Bound range excedido", NULL
msgHandler6 db "Excepcion 6: Opcode indefinido", NULL
msgHandler7 db "Excepcion 7: Dispositivo no disponible", NULL
msgHandler8 db "Excepcion 8: Doble falta", NULL
msgHandler10 db "Excepcion 10: TSS Invalida", NULL
msgHandler11 db "Excepcion 11: Segmento no presente", NULL
msgHandler12 db "Excepcion 12: Falla de segmento de pila", NULL
msgHandler13 db "Excepcion 13: Proteccion general", NULL
msgHandler14 db "Excepcion 14: Falla de pagina -> Repaginando...", NULL
msgHandler16 db "Excepcion 16: Error de punto flotante de FPU", NULL
msgHandler17 db "Excepcion 17: Chequeo de alineacion", NULL
msgHandler18 db "Excepcion 18: Chequeo de maquina", NULL
msgHandler19 db "Excepcion 19: Error de punto flotante de SIMD", NULL
msgHandler20 db "Excepcion 20: Virtualizacion", NULL
tablepointer dd 0x00106000
pagepointer dd 0x00160000
pdptedesc dd 0
dpdesc dd 0
tpdesc dd 0
counter dd 0
shiftflag db 0
Task1SleepTime dd 0
Task2SleepTime dd 0
Task3SleepTime dd 0
T1Runnable db 0
T2Runnable db 0
T3Runnable db 0
MaxPriorReach db 0
Handlers: ; Handlers: Puntero a funcion
dd 0 ; Null pointer
dd service_sleep
dd service_scan_key
dd service_print_screen
dd service_time
;********************************************************************************
; Datos no inicializados
;********************************************************************************
SECTION .bss
scankeyfifo resb 10
;********************************************************************************
; Interrupt Service Routines
;********************************************************************************
SECTION .lib progbits
;***************** Handler de Timer - Scheduler ***********************
tmr_int32_handler:
push ds ; Salvo registros
push es
pushad
mov ebx,0
mov bl, [CurrentTask]
mov eax, dword[ContextsList+ebx*4] ; Coloco EAX apuntando al contexto de la tarea actual (en ejecucion)
mov [eax +CONTEXT_ESP0], esp ; Guardo en el contexto de la tarea actual el ESP0
mov ax,DS_SEL_KER ; Direcciono datos de kernel
mov ds,ax
mov es,ax
mov al,0x20 ; PIC EOI (End of Interrupt)
out 0x20,al
;---------- Descuento de los contadores de Sleep ---------------
cmp byte [Task1State], 2 ; Me fijo si Tarea1 esta durmiendo (Sleep)
jne checktmr2 ; Si no duerme me voy
dec dword[Task1SleepTime] ; Decremento el contador de sleep
cmp dword[Task1SleepTime], 0 ; Me fijo si es cero
jne checktmr2 ; Si no es cero todavia debe dormir
mov byte [Task1State], 1 ; Arriba tarea1! Pasa a ready, fin del tiempo de sleep
checktmr2:
cmp byte [Task2State], 2 ; Me fijo si Tarea2 esta durmiendo (Sleep)
jne checktmr3 ; Si no duerme me voy
dec dword[Task2SleepTime] ; Decremento el contador de sleep
cmp dword[Task2SleepTime], 0 ; Me fijo si es cero
jne checktmr3 ; Si no es cero todavia debe dormir
mov byte [Task2State], 1 ; Arriba tarea2! Pasa a ready, fin del tiempo de sleep
checktmr3:
cmp byte [Task3State], 2 ; Me fijo si Tarea3 esta durmiendo (Sleep)
jne scheduler ; Si no duerme me voy
dec dword[Task3SleepTime] ; Decremento el contador de sleep
cmp dword[Task3SleepTime], 0 ; Me fijo si es cero
jne scheduler ; Si no es cero todavia debe dormir
mov byte [Task3State], 1 ; Arriba tarea3! Pasa a ready, fin del tiempo de sleep
;----------------------- Scheduler ------------------------------
scheduler:
mov byte [T1Runnable], 0 ; Evaluar prioridades
mov byte [T2Runnable], 0
mov byte [T3Runnable], 0
mov byte [MaxPriorReach], 0
mov ecx,0
mov cl,9 ; Cargo en cl el maximo nivel de prioridad (9)
priorityloop: ; Loop que recorre las prioridades desde 9 (max prioridad) hasta 1 (idle task)
cmp cl,[Task1Priority]
je CheckTask1
prior2:
cmp cl,[Task2Priority]
je CheckTask2
prior3:
cmp cl,[Task3Priority]
je CheckTask3
prior4:
cmp byte [MaxPriorReach], 1 ; Encontre alguna/s tarea/s en estado ready de mayor prioridad?
je dispatcher ; Si, me voy al dispatcher
dec cl ; No, entonces bajo la vara de prioridad
cmp cl,0 ; Llegue a cero?
jne priorityloop ; No, entonces recorro el bucle nuevamente en busca de alguna tarea ready
jmp dispatcher ; Si, me voy al dispatcher (ejecutara idle task)
CheckTask1:
cmp byte [Task1State], 1 ; Ready?
jne prior2 ; Not ready
mov byte [MaxPriorReach], 1 ; Es de mayor prioridad
mov byte [T1Runnable], 1 ; Factible de correr
jmp prior2
CheckTask2:
cmp byte [Task2State], 1 ; Ready?
jne prior3 ; Not ready
mov byte [MaxPriorReach], 1 ; Es de mayor prioridad
mov byte [T2Runnable], 1 ; Factible de correr
jmp prior3
CheckTask3:
cmp byte [Task3State], 1 ; Ready?
jne prior4 ; Not ready
mov byte [MaxPriorReach], 1 ; Es de mayor prioridad
mov byte [T3Runnable], 1 ; Factible de correr
jmp prior4
;----------------------- Dispatcher ------------------------------
dispatcher:
mov eax,0
mov ax,[CurrentTask] ; Obtener tarea que se estaba ejecutando
cmp ax, TASK1 ; Es tarea 1?
je EjecutaT1 ; Si es igual salto a EjecutaT1
cmp ax, TASK2 ; Es tarea 2?
je EjecutaT2 ; Si es igual salto a EjecutaT2
cmp ax, TASK3 ; Es tarea 3?
je EjecutaT3 ; Si es igual salto a EjecutaT3
cmp byte [T2Runnable], 1 ; Ejecuta Idle Task - Me fijo si Tarea2 esta despierta (Ready)
mov ax, TASK2
je CambiarTarea ; Si esta despierta cambio de tarea
cmp byte [T1Runnable], 1 ; Me fijo si Tarea1 esta despierta (Ready)
mov ax, TASK1
je CambiarTarea ; Si esta despierta cambio de tarea
cmp byte [T3Runnable], 1 ; Me fijo si Tarea3 esta despierta (Ready)
mov ax, TASK3
je CambiarTarea ; Si esta despierta cambio de tarea
jmp fin_tmr_hdlr ; TODAS LAS TAREAS DUERMEN (SLEEP) - NO CAMBIO DE TAREA, MANTIENE IDLE LA EJECUCION
EjecutaT1:
cmp byte [T2Runnable], 1 ; T1 es solidaria y si T2 quiere correr (Ready) le pasa la bocha
mov ax, TASK2
je CambiarTarea
cmp byte [T3Runnable], 1 ; T1 es solidaria y si T3 quiere correr (Ready) le pasa la bocha
mov ax, TASK3
je CambiarTarea
cmp byte [T1Runnable], 1 ; T1 esta ready?
mov ax, TASKIDLE
jne CambiarTarea ; Si no esta en ready, me voy a idle
jmp fin_tmr_hdlr
EjecutaT2:
cmp byte [T3Runnable], 1 ; T2 es solidaria y si T3 quiere correr (Ready) le pasa la bocha
mov ax, TASK3
je CambiarTarea
cmp byte [T1Runnable], 1 ; T2 es solidaria y si T1 quiere correr (Ready) le pasa la bocha
mov ax, TASK1
je CambiarTarea
cmp byte [T2Runnable], 1 ; T2 esta ready?
mov ax, TASKIDLE
jne CambiarTarea ; Si no esta en ready, me voy a idle
jmp fin_tmr_hdlr
EjecutaT3:
cmp byte [T1Runnable], 1 ; T3 es solidaria y si T1 quiere correr (Ready) le pasa la bocha
mov ax, TASK1
je CambiarTarea
cmp byte [T2Runnable], 1 ; T3 es solidaria y si T2 quiere correr (Ready) le pasa la bocha
mov ax, TASK2
je CambiarTarea
cmp byte [T3Runnable], 1 ; T3 esta ready?
mov ax, TASKIDLE
jne CambiarTarea ; Si no esta en ready, me voy a idle
jmp fin_tmr_hdlr
CambiarTarea:
mov [CurrentTask],ax ; Cambio la tarea actual por la nueva
mov ebx,0
mov bl, [CurrentTask]
mov eax, dword[ContextsList+ebx*4] ; Coloco EAX apuntando al contexto de la tarea nueva
mov ebx,[eax+CONTEXT_CR3]
mov cr3,ebx ; Cargo CR3 de la tarea nueva
mov bx,[eax+CONTEXT_GS]
mov gs,bx ; Cargo GS de la tarea nueva
mov bx,[eax+CONTEXT_FS]
mov fs,bx ; Cargo FS de la tarea nueva
mov bx,[eax+CONTEXT_ES]
mov es,bx ; Cargo ES de la tarea nueva
mov bx,[eax+CONTEXT_DS]
mov ds,bx ; Cargo DS de la tarea nueva
mov esp, [eax +CONTEXT_ESP0] ; Cargo ESP0 de la tarea nueva
mov ebx, [eax+CONTEXT_STACK0]
mov dword [TSS_INIT+4], ebx ; Cargo STACK0 de la tarea nueva en la TSS
mov ebx,[eax+CONTEXT_ACCESS] ; Es la primera vez que va a correr la tarea?
cmp ebx,0
je first_time ; Si, salto. No, sigo
popad ; Restaurar los registros de uso general.
pop es ; Restaurar el registro ES.
pop ds ; Restaurar el registro DS.
iret ; Volver al codigo principal de la tarea.
first_time:
mov dword[eax+CONTEXT_ACCESS], 1 ; Coloco a la tarea como ya ejecutada al menos una vez
mov ebx,[eax+CONTEXT_ESP3] ; Cargo ESP3 de la tarea nueva
mov ecx,[eax+CONTEXT_CS] ; Cargo CS de la tarea nueva
mov edx,[eax+CONTEXT_EIP] ; Cargo direccion de inicio de la tarea nueva
push ds ; Cargo DS de la tarea nueva en la pila
push ebx ; Cargo ESP3 de la tarea nueva en la pila
push 200h ; Cargo EFLAGS de la tarea nueva en la pila
push ecx ; Cargo CS de la tarea nueva en la pila
push edx ; Cargo direccion de inicio de la tarea nueva en la pila
mov ebp, 0 ; Cargo ebp de la tarea nueva
mov edi, 0 ; Cargo edi de la tarea nueva
mov esi, 0 ; Cargo esi de la tarea nueva
mov edx, 0 ; Cargo edx de la tarea nueva
mov ecx, 0 ; Cargo ecx de la tarea nueva
mov ebx, 0 ; Cargo ebx de la tarea nueva
mov eax, 0 ; Cargo eax de la tarea nueva
iret
fin_tmr_hdlr:
popad ;Restaurar los registros de uso general.
pop es ;Restaurar el registro ES.
pop ds ;Restaurar el registro DS.
iret ;Volver al codigo principal de la tarea.
;*********************** Handler de Teclado ****************************
key_int33_handler: ; Rutina de atencion de interrupcion de teclado
push ds
pushad
mov ax, DS_SEL_KER
mov ds, ax
in al,0x60 ; Leo el puerto (Requerimiento de Bochs, sino vuelve a entrar)
cmp al, 0x3B ; tecla "F1" downcode
je F1_on
cmp al, 0x3C ; tecla "F2" downcode
je F2_on
cmp al, 0x3D ; tecla "F3" downcode
je F3_on
cmp al, 0x3E ; tecla "F4" downcode
je F4_on
cmp al, 0x3F ; tecla "F5" downcode
je F5_on
cmp byte [Task3State], 0 ; T3 esta blocked?
je key_fin ; Si esta blocked, me voy
cmp byte [Task3State], 2 ; T3 esta sleeped?
je continue ; Si duerme leo teclado para cuando despierte
cmp byte [T3Runnable], 0 ; T3 esta para correr?
je key_fin ; Si no esta lista me voy
continue:
cmp al,0x2A ; tecla "shift izquierdo" downcode
je shift_on ; Si toque shift salto
cmp al,0xAA ; tecla "shift izquierdo" breakcode
je shift_off ; Si solte shift salto
cmp al,0x39 ; maximo scancode valido
ja key_fin ; si es mayor me voy
mov ebx,scankeyfifo
add ebx,[counter]
mov [ebx],al ; Cargo en scankeyfifo el scancode de la tecla presionada
add [counter],byte 1 ; incremento indice
mov al,[counter]
cmp al,10 ; chequeo si llego al maximo
jb key_fin
mov [counter],byte 0 ; vuelvo el indice a 0
jmp key_fin
shift_on:
mov [shiftflag],byte 1 ; Pongo flag de tecla shift pulsada en 1
jmp key_fin
shift_off:
mov [shiftflag],byte 0 ; Pongo flag de tecla shift pulsada en 0
jmp key_fin
F1_on:
cmp byte [Task1State], 0 ; Paso la tarea 1 de ready a blocked y viceversa
je readytask1
mov byte [Task1State], 0
jmp key_fin
readytask1:
mov byte [Task1State], 1
jmp key_fin
F2_on:
cmp byte [Task2State], 0 ; Paso la tarea 2 de ready a blocked y viceversa
je readytask2
mov byte [Task2State], 0
jmp key_fin
readytask2:
mov byte [Task2State], 1
jmp key_fin
F3_on:
cmp byte [Task3State], 0 ; Paso la tarea 3 de ready a blocked y viceversa
je readytask3
mov byte [Task3State], 0
jmp key_fin
readytask3:
mov byte [Task3State], 1
jmp key_fin
F4_on:
mov byte [Task1Priority], 2 ; Coloco todas las prioridades de las tareas en 2
mov byte [Task2Priority], 2
mov byte [Task3Priority], 2
jmp key_fin
F5_on:
mov byte [Task1Priority], 4 ; Vuelvo a las prioridades originales de las tareas
mov byte [Task2Priority], 2
mov byte [Task3Priority], 3
jmp key_fin
key_fin:
mov al,0x20 ; PIC (END OF INTERRUPT) EOI
out 0x20,al
popad
pop ds
iret ; Vuelvo al programa principal
;************************ DIVIDE ERROR EXCEPTION 0 HANDLER ************************
div_error_excep0_handler:
;xchg bx,bx ; Para saber que excepcion ocurrio
mov ebx,eax
;call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 4 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler0 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
mov eax,ebx
mov ecx,10 ; Salvo division por cero
iret
;exc0_fin:
; hlt
; jmp exc0_fin
;************************ DEBUG EXCEPTION 1 HANDLER ************************
debug_excep1_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler1 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc1_fin:
hlt
jmp exc1_fin
;************************ BREAKPOINT EXCEPTION 3 HANDLER ************************
breakpoint_excep3_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler3 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc3_fin:
hlt
jmp exc3_fin
;************************ OVERFLOW EXCEPTION 4 HANDLER ************************
overflow_excep4_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler4 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc4_fin:
hlt
jmp exc4_fin
;************************ BOUND RANGE EXCEPTION 5 HANDLER ************************
bound_range_excep5_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler5 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc5_fin:
hlt
jmp exc5_fin
;******************** UNDEFINED OPCODE EXCEPTION 6 HANDLER ************************
undef_opcode_excep6_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler6 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc6_fin:
hlt
jmp exc6_fin
;**************** DEVICE NOT AVAILABLE EXCEPTION 7 HANDLER ************************
dev_not_avail_excep7_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler7 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc7_fin:
hlt
jmp exc7_fin
;********************* DOUBLE FAULT EXCEPTION 8 HANDLER ***************************
double_fault_excep8_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler8 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc8_fin:
hlt
jmp exc8_fin
;********************* INVALID TSS EXCEPTION 10 HANDLER ***************************
invalid_tss_excep10_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler10 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc10_fin:
hlt
jmp exc10_fin
;***************** SEGMENT NOT PRESENT EXCEPTION 11 HANDLER ***********************
segm_not_pres_excep11_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler11 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc11_fin:
hlt
jmp exc11_fin
;***************** STACK-SEGMENT FAULT EXCEPTION 12 HANDLER ***********************
stack_segment_excep12_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler12 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc12_fin:
hlt
jmp exc12_fin
;***************** GENERAL PROTECTION EXCEPTION 13 HANDLER ***********************
gen_prot_excep13_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler13 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc13_fin:
hlt
jmp exc13_fin
;********************** PAGE FAULT EXCEPTION 14 HANDLER **************************
page_fault_excep14_handler:
;xchg bx,bx
cli
pop ebx ; Cargo error code
and ebx,0x00000001 ; Enmascaro bit de error presencia (Pagina no presente)
cmp ebx,0 ; Chequeo bit de error de presencia (P flag == 0 -> error)
jne finhdlr ; Si esta no es la fuente de error, salgo del Handler
pushad ; Resguardo registros
;call krn_clear_screen ; Borro pantalla
push WHITE_F | BLACK_B ; Atributos: Color
push 6 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler14 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
;------------------------ PAGINACION DE PAGINA FALTANTE --------------------------
mov ebx,cr2 ; Leo CR2 y chequeo en que dirección ocurrio #PF. La cargo en ebx. Direccion a paginar
mov ecx,ebx ; Cargo ecx con direccion lineal de error
mov edx,ecx ; Cargo ecx con direccion lineal de error
shr edx,30
and edx,0x00000003 ; Tengo en edx numero de descriptor de la pdpte (offset dentro de la PDPTE)
shr ebx,21
and ebx,0x000001FF ; Tengo en ebx numero de descriptor del directorio de paginas (offset dentro de DP)
shr ecx,12
and ecx,0x000001FF ; Tengo en ecx numero de descriptor de la tabla de paginas (offset dentro de TP)
shl edx,3 ; Multiplico por 8 (8 bytes - 64 bits)
mov [pdptedesc],edx ; Salvo Numero de Descriptor (en bytes) de PDPTE
shl ebx,3 ; Multiplico por 8 (8 bytes - 64 bits)
mov [dpdesc],ebx ; Salvo Numero de Descriptor (en bytes) de DP
shl ecx,3 ; Multiplico por 8 (8 bytes - 64 bits)
mov [tpdesc],ecx ; Salvo Numero de Descriptor (en bytes) de TP
mov eax,cr3 ; Cargo PDPTE - Estoy parado en el inicio de la PDPTE
add eax,[pdptedesc] ; Estoy parado en el descriptor correspondiente de la PDPTE
mov ebx,[eax] ; Cargo el contenido del descriptor de la PDPTE
and ebx,0x00000001
cmp ebx,1 ; Chequeo a ver si dicho DP esta creado
jne dpnotcreated ; Salto si esta NO PRESENTE
sigue1:
mov eax,[eax] ; Cargo direccion de DP - Estoy parado al inicio de la DP
and eax,0xFFFFF000
add eax,[dpdesc] ; Estoy parado en el descriptor correspondiente de la DP
mov ebx,[eax] ; Cargo el contenido del descriptor de la DP
and ebx,0x00000001
cmp ebx,1 ; Chequeo a ver si la tabla de paginas esta creada
jne ptnotcreated ; Salto si esta NO PRESENTE
sigue2:
mov eax,[eax] ; Cargo direccion de TP - Estoy parado al inicio de la TP
and eax,0xFFFFF000
add eax,[tpdesc] ; Estoy parado en el descriptor correspondiente de la TP
mov ebx,[pagepointer] ; Cargo puntero de pagina nueva
add ebx,7 ; + Atributos de pagina
mov [eax],ebx ; Completo el descriptor de Page Table con la nueva pagina
mov eax,[pagepointer] ; Incremento pagepointer
add eax,0x1000
mov [pagepointer],eax
finhdlr:
mov eax,cr3 ; Recargo cr3 (para forzar actualizacion de la TLB)
mov cr3,eax
popad
sti
iret
exc14_fin:
hlt
jmp exc14_fin
ptnotcreated:
mov ebx,[tablepointer] ; Cargo puntero de tabla nueva
add ebx,7 ; + Atributos de tabla de paginas
mov [eax],ebx ; Completo descriptor de la DP (Nueva tabla de pagina)
mov ebx,[tablepointer] ; Incremento tablepointer
add ebx,0x1000
cmp ebx,MAX_TABLES ; Veo si llegue al limite de espacio de tablas
jae exc14_fin
mov [tablepointer],ebx
jmp sigue2
dpnotcreated:
mov ebx,[tablepointer] ; Cargo puntero de tabla nueva
add ebx,1 ; + Atributos de DP
mov [eax],ebx ; Completo descriptor de la PDPTE (Nuevo DP)
mov ebx,[tablepointer] ; Incremento tablepointer
add ebx,0x1000
cmp ebx,MAX_TABLES ; Veo si llegue al limite de espacio de tablas
jae exc14_fin
mov [tablepointer],ebx
jmp sigue1
;************ FPU FLOATING POINT ERROR EXCEPTION 16 HANDLER **********************
float_error_excep16_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler16 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc16_fin:
hlt
jmp exc16_fin
;******************** ALIGNMENT CHECK EXCEPTION 17 HANDLER ************************
align_check_excep17_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler17 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc17_fin:
hlt
jmp exc17_fin
;********************* MACHINE CHECK EXCEPTION 18 HANDLER **************************
machine_check_excep18_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler18 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc18_fin:
hlt
jmp exc18_fin
;***************** SIMD FLOATING POINT EXCEPTION 19 HANDLER ***********************
simd_float_excep19_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler19 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc19_fin:
hlt
jmp exc19_fin
;******************** VIRTUALIZATION EXCEPTION 20 HANDLER ************************
virtual_excep20_handler:
xchg bx,bx ; Para saber que excepcion ocurrio
call krn_clear_screen
push WHITE_F | BLACK_B ; Atributos: Color
push 0 ; Y=0 (FILA)
push 0 ; X=0 (COLUMNA)
push msgHandler20 ; Mensaje
call krn_print_screen ; Imprime en pantalla. ABI32.
add esp, 16 ; Limpio stack de parametros
exc20_fin:
hlt
jmp exc20_fin
;************************** CALL GATE 0: SERVICES ********************************
Services:
mov eax,[esp+12] ; Cargo numero de servicio requerido
cmp eax,MAX_SERV
ja cg_end
mov ecx,[esp+8] ; Cargo puntero a estructura de parametros
call dword[Handlers+eax*4] ; Llamo a la subrutina correspondiente al servicio solicitado
cg_end:
retf 8 ; Fin de nuestros servicios. 4*cantidad de parametros, esto balancea la pila, si no esta bien, GP y Buenas Noches
;********************************************************************************
; - -- --- Fin de archivo --- -- -
; J. Balloffet c2015
;******************************************************************************** |
; A001903: Final digit of 7^n.
; 1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7,9,3,1,7
mul $0,2
mod $0,8
pow $0,3
mod $0,5
mov $1,$0
mul $1,2
add $1,1
|
;******************************************************************************
;* Vorbis x86 optimizations
;* Copyright (C) 2006 Loren Merritt <lorenm@u.washington.edu>
;*
;* This file is part of Libav.
;*
;* Libav is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* Libav is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with Libav; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "libavutil/x86/x86util.asm"
SECTION_RODATA
pdw_80000000: times 4 dd 0x80000000
SECTION .text
%if ARCH_X86_32
INIT_MMX 3dnow
cglobal vorbis_inverse_coupling, 3, 3, 6, mag, ang, block_size
pxor m7, m7
lea magq, [magq+block_sizeq*4]
lea angq, [angq+block_sizeq*4]
neg block_sizeq
.loop:
mova m0, [magq+block_sizeq*4]
mova m1, [angq+block_sizeq*4]
mova m2, m0
mova m3, m1
pfcmpge m2, m7 ; m <= 0.0
pfcmpge m3, m7 ; a <= 0.0
pslld m2, 31 ; keep only the sign bit
pxor m1, m2
mova m4, m3
pand m3, m1
pandn m4, m1
pfadd m3, m0 ; a = m + ((a < 0) & (a ^ sign(m)))
pfsub m0, m4 ; m = m + ((a > 0) & (a ^ sign(m)))
mova [angq+block_sizeq*4], m3
mova [magq+block_sizeq*4], m0
add block_sizeq, 2
jl .loop
femms
RET
%endif
INIT_XMM sse
cglobal vorbis_inverse_coupling, 3, 4, 6, mag, ang, block_size, cntr
mova m5, [pdw_80000000]
xor cntrq, cntrq
align 16
.loop:
mova m0, [magq+cntrq*4]
mova m1, [angq+cntrq*4]
xorps m2, m2
xorps m3, m3
cmpleps m2, m0 ; m <= 0.0
cmpleps m3, m1 ; a <= 0.0
andps m2, m5 ; keep only the sign bit
xorps m1, m2
mova m4, m3
andps m3, m1
andnps m4, m1
addps m3, m0 ; a = m + ((a < 0) & (a ^ sign(m)))
subps m0, m4 ; m = m + ((a > 0) & (a ^ sign(m)))
mova [angq+cntrq*4], m3
mova [magq+cntrq*4], m0
add cntrq, 4
cmp cntrq, block_sizeq
jl .loop
RET
|
%include "include/u7bg-all-includes.asm"
defineAddress 330, 0x005A, usecodeCallSite
defineAddress 330, 0x0087, usecodeCallSite_end
%include "../u7-common/patch-call-eop-barkOverItemInWorld.asm"
|
; Hook reading of animations in zCModelPrototype::ReadAniEnum (g1), zCModelPrototype::ReadAniEnumMSB (g2)
%include "inc/macros.inc"
%if GOTHIC_BASE_VERSION == 1
%include "inc/symbols_g1.inc"
%elif GOTHIC_BASE_VERSION == 2
%include "inc/symbols_g2.inc"
%endif
%ifidn __OUTPUT_FORMAT__, bin
org g1g2(0x57DC40,0x5961CD)
%endif
bits 32
section .text align=1 ; Prevent auto-alignment
jmp deploy_ani_ninja
times 2 nop
; Overwrites
; %if GOTHIC_BASE_VERSION == 1
; resetStackoffset 0xF54
; cmp [esp+stackoffset-0xE88], ebp
; %elif GOTHIC_BASE_VERSION == 2
; resetStackoffset 0x49C
; mov eax, [esp+stackoffset-0x3E0]
; %endif
|
; A007204: Crystal ball sequence for D_4 lattice.
; 1,25,169,625,1681,3721,7225,12769,21025,32761,48841,70225,97969,133225,177241,231361,297025,375769,469225,579121,707281,855625,1026169,1221025,1442401,1692601,1974025,2289169,2640625,3031081,3463321,3940225,4464769,5040025,5669161,6355441,7102225,7912969,8791225,9740641,10764961,11868025,13053769,14326225,15689521,17147881,18705625,20367169,22137025,24019801,26020201,28143025,30393169,32775625,35295481,37957921,40768225,43731769,46854025,50140561,53597041,57229225,61042969,65044225,69239041,73633561,78234025,83046769,88078225,93334921,98823481,104550625,110523169,116748025,123232201,129982801,137007025,144312169,151905625,159794881,167987521,176491225,185313769,194463025,203946961,213773641,223951225,234487969,245392225,256672441,268337161,280395025,292854769,305725225,319015321,332734081,346890625,361494169,376554025,392079601
mov $1,1
add $1,$0
pow $1,2
sub $1,$0
bin $1,2
div $1,3
mul $1,24
add $1,1
mov $0,$1
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r14
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0x1599, %r14
nop
nop
nop
nop
and $15944, %r10
movw $0x6162, (%r14)
nop
nop
nop
nop
dec %r14
lea addresses_D_ht+0x151e9, %rsi
lea addresses_D_ht+0x1e349, %rdi
nop
nop
nop
xor %rbp, %rbp
mov $0, %rcx
rep movsq
nop
nop
nop
and %rsi, %rsi
lea addresses_UC_ht+0x17839, %r11
nop
nop
xor $23258, %rcx
mov (%r11), %ebp
nop
dec %rdi
lea addresses_UC_ht+0x13705, %r11
nop
nop
nop
add $16090, %rbp
mov (%r11), %r10d
nop
nop
cmp %r14, %r14
lea addresses_WT_ht+0x1e739, %r10
nop
nop
nop
nop
and %r14, %r14
mov (%r10), %esi
and $22832, %rdi
lea addresses_WC_ht+0x1339, %rdi
dec %rbp
movw $0x6162, (%rdi)
nop
nop
nop
nop
nop
dec %r11
lea addresses_WT_ht+0x941b, %rsi
lea addresses_UC_ht+0x1cdd9, %rdi
nop
nop
nop
nop
nop
sub $42115, %rbp
mov $4, %rcx
rep movsl
nop
dec %r11
lea addresses_A_ht+0xc229, %rsi
lea addresses_normal_ht+0x15039, %rdi
nop
nop
nop
dec %r10
mov $32, %rcx
rep movsb
nop
nop
nop
nop
cmp $2821, %r14
lea addresses_normal_ht+0x16439, %r10
nop
nop
dec %rcx
mov $0x6162636465666768, %rbp
movq %rbp, (%r10)
nop
nop
nop
nop
and $59078, %r14
lea addresses_D_ht+0x1f39, %r14
nop
nop
nop
add $20117, %r11
and $0xffffffffffffffc0, %r14
vmovntdqa (%r14), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $0, %xmm7, %rcx
add $10605, %rdi
lea addresses_A_ht+0x14e39, %rsi
lea addresses_WT_ht+0x1db8b, %rdi
clflush (%rdi)
nop
nop
add $25600, %rax
mov $3, %rcx
rep movsq
nop
nop
nop
nop
and %rdi, %rdi
lea addresses_A_ht+0xdc39, %rsi
lea addresses_UC_ht+0x17a39, %rdi
nop
cmp $7259, %r10
mov $78, %rcx
rep movsq
nop
nop
cmp %r10, %r10
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r14
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r14
push %r15
push %rax
push %rcx
push %rdi
push %rsi
// Store
lea addresses_US+0x1e839, %r11
nop
nop
nop
nop
sub %r14, %r14
movw $0x5152, (%r11)
cmp $11205, %rcx
// Store
lea addresses_D+0xe539, %rsi
nop
nop
nop
nop
nop
cmp $51786, %rax
movb $0x51, (%rsi)
inc %rsi
// Store
lea addresses_PSE+0xd3c1, %r15
xor $43109, %r14
movw $0x5152, (%r15)
nop
nop
nop
nop
cmp %rdi, %rdi
// Store
lea addresses_RW+0x1efb9, %r14
nop
nop
nop
nop
xor %rax, %rax
movw $0x5152, (%r14)
nop
nop
nop
nop
xor %r14, %r14
// Load
lea addresses_WT+0x1d06a, %r14
nop
nop
nop
nop
nop
cmp %rdi, %rdi
vmovups (%r14), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $0, %xmm7, %rsi
nop
nop
add $44448, %rsi
// Store
lea addresses_A+0x11839, %r14
nop
nop
nop
nop
nop
and $60287, %rsi
movw $0x5152, (%r14)
nop
nop
nop
nop
xor %rax, %rax
// Load
lea addresses_RW+0xbb9, %rdi
nop
nop
cmp %rcx, %rcx
movb (%rdi), %r15b
nop
nop
nop
nop
and %rax, %rax
// Faulty Load
mov $0x58e3e80000000439, %rax
nop
cmp $6924, %r14
mov (%rax), %r11
lea oracles, %r15
and $0xff, %r11
shlq $12, %r11
mov (%r15,%r11,1), %r11
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r15
pop %r14
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_NC', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_US', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 7, 'type': 'addresses_D', 'AVXalign': False, 'size': 1}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_PSE', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 5, 'type': 'addresses_RW', 'AVXalign': True, 'size': 2}}
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WT', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_A', 'AVXalign': False, 'size': 2}}
{'src': {'NT': False, 'same': False, 'congruent': 6, 'type': 'addresses_RW', 'AVXalign': False, 'size': 1}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_NC', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 5, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 2}}
{'src': {'same': False, 'congruent': 1, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 3, 'type': 'addresses_D_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 8, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 8, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 2}}
{'src': {'same': False, 'congruent': 0, 'type': 'addresses_WT_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 1, 'type': 'addresses_UC_ht'}}
{'src': {'same': False, 'congruent': 3, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 10, 'type': 'addresses_normal_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_normal_ht', 'AVXalign': True, 'size': 8}}
{'src': {'NT': True, 'same': False, 'congruent': 8, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 9, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 1, 'type': 'addresses_WT_ht'}}
{'src': {'same': False, 'congruent': 10, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 9, 'type': 'addresses_UC_ht'}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
#pragma once
#include <hive/chain/hive_fwd.hpp>
#include <hive/protocol/asset.hpp>
namespace hive { namespace plugins { namespace condenser_api {
using hive::protocol::asset;
using hive::protocol::asset_symbol_type;
using hive::protocol::share_type;
struct legacy_asset
{
public:
legacy_asset() {}
asset to_asset()const
{
return asset( amount, symbol );
}
operator asset()const { return to_asset(); }
static legacy_asset from_asset( const asset& a )
{
legacy_asset leg;
leg.amount = a.amount;
leg.symbol = a.symbol;
return leg;
}
string to_string()const;
static legacy_asset from_string( const string& from );
share_type amount;
asset_symbol_type symbol = HIVE_SYMBOL;
};
} } } // hive::plugins::condenser_api
namespace fc {
inline void to_variant( const hive::plugins::condenser_api::legacy_asset& a, fc::variant& var )
{
var = a.to_string();
}
inline void from_variant( const fc::variant& var, hive::plugins::condenser_api::legacy_asset& a )
{
a = hive::plugins::condenser_api::legacy_asset::from_string( var.as_string() );
}
} // fc
FC_REFLECT( hive::plugins::condenser_api::legacy_asset,
(amount)
(symbol)
)
|
/*
* Copyright (c) 2017, Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
L0:
mov (8|M0) r16.0<1>:ud r0.0<8;8,1>:ud
(W&~f0.1)jmpi L400
L32:
mov (8|M0) r17.0<1>:ud r25.0<8;8,1>:ud
add (1|M0) a0.0<1>:ud r23.5<0;1,0>:ud 0x42EC100:ud
mov (1|M0) acc0.3<1>:f r25.3<0;1,0>:f
mac (1|M0) r17.3<1>:f r23.1<0;1,0>:f 2.0:f {AccWrEn}
mov (1|M0) r25.3<1>:f acc0.3<0;1,0>:f
mov (1|M0) r16.2<1>:ud 0xE000:ud
send (1|M0) r96:uw r16:ub 0x2 a0.0
mov (1|M0) r17.2<1>:f r10.1<0;1,0>:f
send (1|M0) r104:uw r16:ub 0x2 a0.0
add (1|M0) a0.0<1>:ud r23.5<0;1,0>:ud 0x44EC201:ud
mov (1|M0) r17.2<1>:f r25.2<0;1,0>:f
mov (1|M0) r16.2<1>:ud 0xC000:ud
send (1|M0) r100:uw r16:ub 0x2 a0.0
mov (1|M0) r17.2<1>:f r10.1<0;1,0>:f
send (1|M0) r108:uw r16:ub 0x2 a0.0
mov (16|M0) r98.0<1>:uw 0xFFFF:uw
mov (16|M0) r99.0<1>:uw 0xFFFF:uw
mov (16|M0) r106.0<1>:uw 0xFFFF:uw
mov (16|M0) r107.0<1>:uw 0xFFFF:uw
mov (1|M0) a0.8<1>:uw 0xC00:uw
mov (1|M0) a0.9<1>:uw 0xC80:uw
mov (1|M0) a0.10<1>:uw 0xCC0:uw
add (4|M0) a0.12<1>:uw a0.8<4;4,1>:uw 0x100:uw
L400:
nop
|
//
// Copyright (c) 2015 The ANGLE Project Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
//
// X11Window.cpp: Implementation of OSWindow for X11
#include "util/x11/X11Window.h"
#include "common/debug.h"
#include "util/Timer.h"
#include "util/system_utils.h"
namespace
{
Bool WaitForMapNotify(Display *dpy, XEvent *event, XPointer window)
{
return event->type == MapNotify && event->xmap.window == reinterpret_cast<Window>(window);
}
static Key X11CodeToKey(Display *display, unsigned int scancode)
{
int temp;
KeySym *keySymbols;
keySymbols = XGetKeyboardMapping(display, scancode, 1, &temp);
unsigned int keySymbol = keySymbols[0];
XFree(keySymbols);
switch (keySymbol)
{
case XK_Shift_L:
return KEY_LSHIFT;
case XK_Shift_R:
return KEY_RSHIFT;
case XK_Alt_L:
return KEY_LALT;
case XK_Alt_R:
return KEY_RALT;
case XK_Control_L:
return KEY_LCONTROL;
case XK_Control_R:
return KEY_RCONTROL;
case XK_Super_L:
return KEY_LSYSTEM;
case XK_Super_R:
return KEY_RSYSTEM;
case XK_Menu:
return KEY_MENU;
case XK_semicolon:
return KEY_SEMICOLON;
case XK_slash:
return KEY_SLASH;
case XK_equal:
return KEY_EQUAL;
case XK_minus:
return KEY_DASH;
case XK_bracketleft:
return KEY_LBRACKET;
case XK_bracketright:
return KEY_RBRACKET;
case XK_comma:
return KEY_COMMA;
case XK_period:
return KEY_PERIOD;
case XK_backslash:
return KEY_BACKSLASH;
case XK_asciitilde:
return KEY_TILDE;
case XK_Escape:
return KEY_ESCAPE;
case XK_space:
return KEY_SPACE;
case XK_Return:
return KEY_RETURN;
case XK_BackSpace:
return KEY_BACK;
case XK_Tab:
return KEY_TAB;
case XK_Page_Up:
return KEY_PAGEUP;
case XK_Page_Down:
return KEY_PAGEDOWN;
case XK_End:
return KEY_END;
case XK_Home:
return KEY_HOME;
case XK_Insert:
return KEY_INSERT;
case XK_Delete:
return KEY_DELETE;
case XK_KP_Add:
return KEY_ADD;
case XK_KP_Subtract:
return KEY_SUBTRACT;
case XK_KP_Multiply:
return KEY_MULTIPLY;
case XK_KP_Divide:
return KEY_DIVIDE;
case XK_Pause:
return KEY_PAUSE;
case XK_F1:
return KEY_F1;
case XK_F2:
return KEY_F2;
case XK_F3:
return KEY_F3;
case XK_F4:
return KEY_F4;
case XK_F5:
return KEY_F5;
case XK_F6:
return KEY_F6;
case XK_F7:
return KEY_F7;
case XK_F8:
return KEY_F8;
case XK_F9:
return KEY_F9;
case XK_F10:
return KEY_F10;
case XK_F11:
return KEY_F11;
case XK_F12:
return KEY_F12;
case XK_F13:
return KEY_F13;
case XK_F14:
return KEY_F14;
case XK_F15:
return KEY_F15;
case XK_Left:
return KEY_LEFT;
case XK_Right:
return KEY_RIGHT;
case XK_Down:
return KEY_DOWN;
case XK_Up:
return KEY_UP;
case XK_KP_Insert:
return KEY_NUMPAD0;
case XK_KP_End:
return KEY_NUMPAD1;
case XK_KP_Down:
return KEY_NUMPAD2;
case XK_KP_Page_Down:
return KEY_NUMPAD3;
case XK_KP_Left:
return KEY_NUMPAD4;
case XK_KP_5:
return KEY_NUMPAD5;
case XK_KP_Right:
return KEY_NUMPAD6;
case XK_KP_Home:
return KEY_NUMPAD7;
case XK_KP_Up:
return KEY_NUMPAD8;
case XK_KP_Page_Up:
return KEY_NUMPAD9;
case XK_a:
return KEY_A;
case XK_b:
return KEY_B;
case XK_c:
return KEY_C;
case XK_d:
return KEY_D;
case XK_e:
return KEY_E;
case XK_f:
return KEY_F;
case XK_g:
return KEY_G;
case XK_h:
return KEY_H;
case XK_i:
return KEY_I;
case XK_j:
return KEY_J;
case XK_k:
return KEY_K;
case XK_l:
return KEY_L;
case XK_m:
return KEY_M;
case XK_n:
return KEY_N;
case XK_o:
return KEY_O;
case XK_p:
return KEY_P;
case XK_q:
return KEY_Q;
case XK_r:
return KEY_R;
case XK_s:
return KEY_S;
case XK_t:
return KEY_T;
case XK_u:
return KEY_U;
case XK_v:
return KEY_V;
case XK_w:
return KEY_W;
case XK_x:
return KEY_X;
case XK_y:
return KEY_Y;
case XK_z:
return KEY_Z;
case XK_1:
return KEY_NUM1;
case XK_2:
return KEY_NUM2;
case XK_3:
return KEY_NUM3;
case XK_4:
return KEY_NUM4;
case XK_5:
return KEY_NUM5;
case XK_6:
return KEY_NUM6;
case XK_7:
return KEY_NUM7;
case XK_8:
return KEY_NUM8;
case XK_9:
return KEY_NUM9;
case XK_0:
return KEY_NUM0;
}
return Key(0);
}
static void AddX11KeyStateToEvent(Event *event, unsigned int state)
{
event->Key.Shift = state & ShiftMask;
event->Key.Control = state & ControlMask;
event->Key.Alt = state & Mod1Mask;
event->Key.System = state & Mod4Mask;
}
} // namespace
X11Window::X11Window()
: WM_DELETE_WINDOW(None),
WM_PROTOCOLS(None),
TEST_EVENT(None),
mDisplay(nullptr),
mWindow(0),
mRequestedVisualId(-1),
mVisible(false)
{}
X11Window::X11Window(int visualId)
: WM_DELETE_WINDOW(None),
WM_PROTOCOLS(None),
TEST_EVENT(None),
mDisplay(nullptr),
mWindow(0),
mRequestedVisualId(visualId),
mVisible(false)
{}
X11Window::~X11Window()
{
destroy();
}
bool X11Window::initialize(const std::string &name, size_t width, size_t height)
{
destroy();
mDisplay = XOpenDisplay(nullptr);
if (!mDisplay)
{
return false;
}
{
int screen = DefaultScreen(mDisplay);
Window root = RootWindow(mDisplay, screen);
Visual *visual;
if (mRequestedVisualId == -1)
{
visual = DefaultVisual(mDisplay, screen);
}
else
{
XVisualInfo visualTemplate;
visualTemplate.visualid = mRequestedVisualId;
int numVisuals = 0;
XVisualInfo *visuals =
XGetVisualInfo(mDisplay, VisualIDMask, &visualTemplate, &numVisuals);
if (numVisuals <= 0)
{
return false;
}
ASSERT(numVisuals == 1);
visual = visuals[0].visual;
XFree(visuals);
}
int depth = DefaultDepth(mDisplay, screen);
Colormap colormap = XCreateColormap(mDisplay, root, visual, AllocNone);
XSetWindowAttributes attributes;
unsigned long attributeMask = CWBorderPixel | CWColormap | CWEventMask;
attributes.event_mask = StructureNotifyMask | PointerMotionMask | ButtonPressMask |
ButtonReleaseMask | FocusChangeMask | EnterWindowMask |
LeaveWindowMask | KeyPressMask | KeyReleaseMask;
attributes.border_pixel = 0;
attributes.colormap = colormap;
mWindow = XCreateWindow(mDisplay, root, 0, 0, width, height, 0, depth, InputOutput, visual,
attributeMask, &attributes);
XFreeColormap(mDisplay, colormap);
}
if (!mWindow)
{
destroy();
return false;
}
// Tell the window manager to notify us when the user wants to close the
// window so we can do it ourselves.
WM_DELETE_WINDOW = XInternAtom(mDisplay, "WM_DELETE_WINDOW", False);
WM_PROTOCOLS = XInternAtom(mDisplay, "WM_PROTOCOLS", False);
if (WM_DELETE_WINDOW == None || WM_PROTOCOLS == None)
{
destroy();
return false;
}
if (XSetWMProtocols(mDisplay, mWindow, &WM_DELETE_WINDOW, 1) == 0)
{
destroy();
return false;
}
// Create an atom to identify our test event
TEST_EVENT = XInternAtom(mDisplay, "ANGLE_TEST_EVENT", False);
if (TEST_EVENT == None)
{
destroy();
return false;
}
XFlush(mDisplay);
mX = 0;
mY = 0;
mWidth = width;
mHeight = height;
return true;
}
void X11Window::destroy()
{
if (mWindow)
{
XDestroyWindow(mDisplay, mWindow);
mWindow = 0;
}
if (mDisplay)
{
XCloseDisplay(mDisplay);
mDisplay = nullptr;
}
WM_DELETE_WINDOW = None;
WM_PROTOCOLS = None;
}
void X11Window::resetNativeWindow() {}
EGLNativeWindowType X11Window::getNativeWindow() const
{
return mWindow;
}
EGLNativeDisplayType X11Window::getNativeDisplay() const
{
return mDisplay;
}
void X11Window::messageLoop()
{
int eventCount = XPending(mDisplay);
while (eventCount--)
{
XEvent event;
XNextEvent(mDisplay, &event);
processEvent(event);
}
}
void X11Window::setMousePosition(int x, int y)
{
XWarpPointer(mDisplay, None, mWindow, 0, 0, 0, 0, x, y);
}
bool X11Window::setPosition(int x, int y)
{
XMoveWindow(mDisplay, mWindow, x, y);
XFlush(mDisplay);
return true;
}
bool X11Window::resize(int width, int height)
{
XResizeWindow(mDisplay, mWindow, width, height);
XFlush(mDisplay);
Timer *timer = CreateTimer();
timer->start();
// Wait until the window as actually been resized so that the code calling resize
// can assume the window has been resized.
const double kResizeWaitDelay = 0.2;
while ((mHeight != height || mWidth != width) && timer->getElapsedTime() < kResizeWaitDelay)
{
messageLoop();
angle::Sleep(10);
}
delete timer;
return true;
}
void X11Window::setVisible(bool isVisible)
{
if (mVisible == isVisible)
{
return;
}
if (isVisible)
{
XMapWindow(mDisplay, mWindow);
// Wait until we get an event saying this window is mapped so that the
// code calling setVisible can assume the window is visible.
// This is important when creating a framebuffer as the framebuffer content
// is undefined when the window is not visible.
XEvent dummyEvent;
XIfEvent(mDisplay, &dummyEvent, WaitForMapNotify, reinterpret_cast<XPointer>(mWindow));
}
else
{
XUnmapWindow(mDisplay, mWindow);
XFlush(mDisplay);
}
mVisible = isVisible;
}
void X11Window::signalTestEvent()
{
XEvent event;
event.type = ClientMessage;
event.xclient.message_type = TEST_EVENT;
// Format needs to be valid or a BadValue is generated
event.xclient.format = 32;
// Hijack StructureNotifyMask as we know we will be listening for it.
XSendEvent(mDisplay, mWindow, False, StructureNotifyMask, &event);
// For test events, the tests want to check that it really did arrive, and they don't wait
// long. XSync here makes sure the event is sent by the time the messageLoop() is called.
XSync(mDisplay, false);
}
void X11Window::processEvent(const XEvent &xEvent)
{
// TODO(cwallez) text events
switch (xEvent.type)
{
case ButtonPress:
{
Event event;
MouseButton button = MOUSEBUTTON_UNKNOWN;
int wheelY = 0;
// The mouse wheel updates are sent via button events.
switch (xEvent.xbutton.button)
{
case Button4:
wheelY = 1;
break;
case Button5:
wheelY = -1;
break;
case 6:
break;
case 7:
break;
case Button1:
button = MOUSEBUTTON_LEFT;
break;
case Button2:
button = MOUSEBUTTON_MIDDLE;
break;
case Button3:
button = MOUSEBUTTON_RIGHT;
break;
case 8:
button = MOUSEBUTTON_BUTTON4;
break;
case 9:
button = MOUSEBUTTON_BUTTON5;
break;
default:
break;
}
if (wheelY != 0)
{
event.Type = Event::EVENT_MOUSE_WHEEL_MOVED;
event.MouseWheel.Delta = wheelY;
pushEvent(event);
}
if (button != MOUSEBUTTON_UNKNOWN)
{
event.Type = Event::EVENT_MOUSE_BUTTON_RELEASED;
event.MouseButton.Button = button;
event.MouseButton.X = xEvent.xbutton.x;
event.MouseButton.Y = xEvent.xbutton.y;
pushEvent(event);
}
}
break;
case ButtonRelease:
{
Event event;
MouseButton button = MOUSEBUTTON_UNKNOWN;
switch (xEvent.xbutton.button)
{
case Button1:
button = MOUSEBUTTON_LEFT;
break;
case Button2:
button = MOUSEBUTTON_MIDDLE;
break;
case Button3:
button = MOUSEBUTTON_RIGHT;
break;
case 8:
button = MOUSEBUTTON_BUTTON4;
break;
case 9:
button = MOUSEBUTTON_BUTTON5;
break;
default:
break;
}
if (button != MOUSEBUTTON_UNKNOWN)
{
event.Type = Event::EVENT_MOUSE_BUTTON_RELEASED;
event.MouseButton.Button = button;
event.MouseButton.X = xEvent.xbutton.x;
event.MouseButton.Y = xEvent.xbutton.y;
pushEvent(event);
}
}
break;
case KeyPress:
{
Event event;
event.Type = Event::EVENT_KEY_PRESSED;
event.Key.Code = X11CodeToKey(mDisplay, xEvent.xkey.keycode);
AddX11KeyStateToEvent(&event, xEvent.xkey.state);
pushEvent(event);
}
break;
case KeyRelease:
{
Event event;
event.Type = Event::EVENT_KEY_RELEASED;
event.Key.Code = X11CodeToKey(mDisplay, xEvent.xkey.keycode);
AddX11KeyStateToEvent(&event, xEvent.xkey.state);
pushEvent(event);
}
break;
case EnterNotify:
{
Event event;
event.Type = Event::EVENT_MOUSE_ENTERED;
pushEvent(event);
}
break;
case LeaveNotify:
{
Event event;
event.Type = Event::EVENT_MOUSE_LEFT;
pushEvent(event);
}
break;
case MotionNotify:
{
Event event;
event.Type = Event::EVENT_MOUSE_MOVED;
event.MouseMove.X = xEvent.xmotion.x;
event.MouseMove.Y = xEvent.xmotion.y;
pushEvent(event);
}
break;
case ConfigureNotify:
{
if (xEvent.xconfigure.width != mWidth || xEvent.xconfigure.height != mHeight)
{
Event event;
event.Type = Event::EVENT_RESIZED;
event.Size.Width = xEvent.xconfigure.width;
event.Size.Height = xEvent.xconfigure.height;
pushEvent(event);
}
if (xEvent.xconfigure.x != mX || xEvent.xconfigure.y != mY)
{
// Sometimes, the window manager reparents our window (for example
// when resizing) then the X and Y coordinates will be with respect to
// the new parent and not what the user wants to know. Use
// XTranslateCoordinates to get the coordinates on the screen.
int screen = DefaultScreen(mDisplay);
Window root = RootWindow(mDisplay, screen);
int x, y;
Window child;
XTranslateCoordinates(mDisplay, mWindow, root, 0, 0, &x, &y, &child);
if (x != mX || y != mY)
{
Event event;
event.Type = Event::EVENT_MOVED;
event.Move.X = x;
event.Move.Y = y;
pushEvent(event);
}
}
}
break;
case FocusIn:
if (xEvent.xfocus.mode == NotifyNormal || xEvent.xfocus.mode == NotifyWhileGrabbed)
{
Event event;
event.Type = Event::EVENT_GAINED_FOCUS;
pushEvent(event);
}
break;
case FocusOut:
if (xEvent.xfocus.mode == NotifyNormal || xEvent.xfocus.mode == NotifyWhileGrabbed)
{
Event event;
event.Type = Event::EVENT_LOST_FOCUS;
pushEvent(event);
}
break;
case DestroyNotify:
// We already received WM_DELETE_WINDOW
break;
case ClientMessage:
if (xEvent.xclient.message_type == WM_PROTOCOLS &&
static_cast<Atom>(xEvent.xclient.data.l[0]) == WM_DELETE_WINDOW)
{
Event event;
event.Type = Event::EVENT_CLOSED;
pushEvent(event);
}
else if (xEvent.xclient.message_type == TEST_EVENT)
{
Event event;
event.Type = Event::EVENT_TEST;
pushEvent(event);
}
break;
}
}
// static
OSWindow *OSWindow::New()
{
return new X11Window();
}
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r15
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x19cdf, %r15
nop
nop
nop
add $59715, %r9
movups (%r15), %xmm7
vpextrq $0, %xmm7, %rbp
nop
xor $54017, %rbp
lea addresses_A_ht+0x1ad9f, %rsi
lea addresses_WT_ht+0x10fad, %rdi
nop
nop
nop
xor %r11, %r11
mov $9, %rcx
rep movsb
nop
nop
nop
nop
and $37723, %r9
lea addresses_D_ht+0x1dfe2, %rcx
nop
nop
nop
nop
xor %r9, %r9
mov (%rcx), %bp
nop
cmp $59903, %r11
lea addresses_normal_ht+0xc4df, %rcx
nop
nop
inc %rbp
movb $0x61, (%rcx)
dec %r11
lea addresses_UC_ht+0x16ff9, %r9
clflush (%r9)
xor $18388, %r11
mov (%r9), %ebp
nop
nop
nop
nop
nop
add %r9, %r9
lea addresses_A_ht+0x11c27, %rsi
xor $19653, %r9
mov (%rsi), %cx
nop
nop
nop
xor %r15, %r15
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r15
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r13
push %rbx
push %rcx
push %rdx
push %rsi
// Store
mov $0x7ff, %r10
clflush (%r10)
nop
nop
nop
nop
and $48360, %rcx
movb $0x51, (%r10)
nop
sub %rbx, %rbx
// Load
lea addresses_normal+0x1f89f, %rbx
clflush (%rbx)
nop
nop
nop
nop
inc %rsi
vmovaps (%rbx), %ymm0
vextracti128 $1, %ymm0, %xmm0
vpextrq $1, %xmm0, %r13
nop
nop
nop
and $41372, %rsi
// Store
lea addresses_PSE+0xfcdf, %rbx
nop
nop
nop
cmp $27955, %rcx
movw $0x5152, (%rbx)
nop
nop
nop
nop
cmp $25857, %rdx
// Store
lea addresses_US+0x1f5af, %rsi
nop
xor $31830, %r13
mov $0x5152535455565758, %rbx
movq %rbx, %xmm1
vmovups %ymm1, (%rsi)
nop
nop
nop
nop
nop
xor $55181, %r13
// Store
lea addresses_PSE+0xfcdf, %rbx
and $45366, %rsi
movl $0x51525354, (%rbx)
nop
cmp $10951, %rcx
// Faulty Load
lea addresses_PSE+0xfcdf, %rcx
clflush (%rcx)
nop
dec %rsi
mov (%rcx), %r11d
lea oracles, %rcx
and $0xff, %r11
shlq $12, %r11
mov (%rcx,%r11,1), %r11
pop %rsi
pop %rdx
pop %rcx
pop %rbx
pop %r13
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_PSE', 'size': 8, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 5, 'NT': False, 'type': 'addresses_P', 'size': 1, 'AVXalign': False}}
{'src': {'same': False, 'congruent': 5, 'NT': False, 'type': 'addresses_normal', 'size': 32, 'AVXalign': True}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_PSE', 'size': 2, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 4, 'NT': False, 'type': 'addresses_US', 'size': 32, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_PSE', 'size': 4, 'AVXalign': False}}
[Faulty Load]
{'src': {'same': True, 'congruent': 0, 'NT': False, 'type': 'addresses_PSE', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'same': True, 'congruent': 11, 'NT': False, 'type': 'addresses_D_ht', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}}
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_D_ht', 'size': 2, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 9, 'NT': False, 'type': 'addresses_normal_ht', 'size': 1, 'AVXalign': False}}
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_UC_ht', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 2, 'NT': False, 'type': 'addresses_A_ht', 'size': 2, 'AVXalign': False}, 'OP': 'LOAD'}
{'54': 597}
54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54
*/
|
; AVX-512CD testcases from gas
;------------------------
;
; This file is taken from there
; https://gnu.googlesource.com/binutils/+/master/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d
; So the original author is "H.J. Lu" <hongjiu dot lu at intel dot com>
;
; Jin Kyu Song converted it for the nasm testing suite using gas2nasm.py
%macro testcase 2
%ifdef BIN
db %1
%endif
%ifdef SRC
%2
%endif
%endmacro
bits 64
testcase { 0x62, 0x02, 0x7d, 0x48, 0xc4, 0xf5 }, { vpconflictd zmm30,zmm29 }
testcase { 0x62, 0x02, 0x7d, 0x4f, 0xc4, 0xf5 }, { vpconflictd zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0x7d, 0xcf, 0xc4, 0xf5 }, { vpconflictd zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x31 }, { vpconflictd zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0x7d, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x31 }, { vpconflictd zmm30,DWORD [rcx]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictd zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vpconflictd zmm30,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vpconflictd zmm30,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x02, 0xfd, 0x48, 0xc4, 0xf5 }, { vpconflictq zmm30,zmm29 }
testcase { 0x62, 0x02, 0xfd, 0x4f, 0xc4, 0xf5 }, { vpconflictq zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0xfd, 0xcf, 0xc4, 0xf5 }, { vpconflictq zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x31 }, { vpconflictq zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0xfd, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x31 }, { vpconflictq zmm30,QWORD [rcx]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictq zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vpconflictq zmm30,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vpconflictq zmm30,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x02, 0x7d, 0x48, 0x44, 0xf5 }, { vplzcntd zmm30,zmm29 }
testcase { 0x62, 0x02, 0x7d, 0x4f, 0x44, 0xf5 }, { vplzcntd zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0x7d, 0xcf, 0x44, 0xf5 }, { vplzcntd zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x31 }, { vplzcntd zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0x7d, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x31 }, { vplzcntd zmm30,DWORD [rcx]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntd zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vplzcntd zmm30,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vplzcntd zmm30,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x02, 0xfd, 0x48, 0x44, 0xf5 }, { vplzcntq zmm30,zmm29 }
testcase { 0x62, 0x02, 0xfd, 0x4f, 0x44, 0xf5 }, { vplzcntq zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0xfd, 0xcf, 0x44, 0xf5 }, { vplzcntq zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x31 }, { vplzcntq zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0xfd, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x31 }, { vplzcntq zmm30,QWORD [rcx]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntq zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vplzcntq zmm30,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vplzcntq zmm30,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x92, 0x16, 0x40, 0x27, 0xec }, { vptestnmd k5,zmm29,zmm28 }
testcase { 0x62, 0x92, 0x16, 0x47, 0x27, 0xec }, { vptestnmd k5{k7},zmm29,zmm28 }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x29 }, { vptestnmd k5,zmm29,ZWORD [rcx] }
testcase { 0x62, 0xb2, 0x16, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x29 }, { vptestnmd k5,zmm29,DWORD [rcx]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rdx+0x2000] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2000] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2040] }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0x00, 0x02, 0x00, 0x00 }, { vptestnmd k5,zmm29,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0xfc, 0xfd, 0xff, 0xff }, { vptestnmd k5,zmm29,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x92, 0x96, 0x40, 0x27, 0xec }, { vptestnmq k5,zmm29,zmm28 }
testcase { 0x62, 0x92, 0x96, 0x47, 0x27, 0xec }, { vptestnmq k5{k7},zmm29,zmm28 }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x29 }, { vptestnmq k5,zmm29,ZWORD [rcx] }
testcase { 0x62, 0xb2, 0x96, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x29 }, { vptestnmq k5,zmm29,QWORD [rcx]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rdx+0x2000] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2000] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2040] }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0x00, 0x04, 0x00, 0x00 }, { vptestnmq k5,zmm29,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0xf8, 0xfb, 0xff, 0xff }, { vptestnmq k5,zmm29,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x62, 0x7e, 0x48, 0x3a, 0xf6 }, { vpbroadcastmw2d zmm30,k6 }
testcase { 0x62, 0x62, 0xfe, 0x48, 0x2a, 0xf6 }, { vpbroadcastmb2q zmm30,k6 }
|
; A081072: Fibonacci(4n) + 3, or Fibonacci(2n+2)*Lucas(2n-2).
; 3,6,24,147,990,6768,46371,317814,2178312,14930355,102334158,701408736,4807526979,32951280102,225851433720,1548008755923,10610209857726,72723460248144,498454011879267,3416454622906710,23416728348467688
mul $0,2
mov $2,1
lpb $0
sub $0,1
add $1,$2
add $2,$1
lpe
add $1,3
|
; BeepFX sound effect by shiru
; http://shiru.untergrund.net
SECTION rodata_sound_bit
PUBLIC _bfx_52
_bfx_52:
; Roboblip
defb 1 ;tone
defw 1,2000,200,0,128
defb 1 ;pause
defw 1,2000,0,0,0
defb 1 ;tone
defw 1,2000,200,0,32
defb 1 ;pause
defw 1,2000,0,0,0
defb 1 ;tone
defw 1,2000,200,0,16
defb 1 ;pause
defw 1,2000,0,0,0
defb 1 ;tone
defw 1,2000,200,0,8
defb 0
|
; Rectangle, Intervals and Points
; 05.2006 aralbrec
SECTION code_clib
PUBLIC RIsPtInIval8
; Determine if 8-bit point lies in an 8-bit interval.
; Interval bounds wrap across 0-255 boundaries.
;
; enter : a = coordinate of point
; d = interval start coordinate
; e = width of interval
; exit : carry flag set = in interval
; used : af
.RIsPtInIval8
sub d
cp e
ret
|
src_t *sp;
dest_t *dp;
*dp = (dest_t) *sp;
sp is stored in %rdi
dp is stored in %rsi
src_t dest_t instruction
long long movq (%rdi), %rax
movq %rax, (%rsi)
char int movb (%rdi), %al
movsbl %al, (%rsi)
char unsigned movzbl (%rdi), %eax
movl %eax, (%rsi)
uChar long movzbq (%rdi), %rax
movq %rax, (%rsi)
int char movb (%rdi), %al
movb %al, (%rsi)
u uChar movl (%rdi), %eax
movb %al, (%rsi)
char short movsbw (%rdi), %ax
movw %ax, (%rsi)
Solutions
long long movq (%rdi), %rax Read 8 bytes
movq %rax, (%rsi) Store 8 bytes
char int movsbl (%rdi), %eax Convert char to int
movl %eax, (%rsi) Store 4 bytes
char unsigned movsbl (%rdi), %eax Convert char to int
movl %eax, (%rsi) Store 4 bytes
unsigned char long movzbl (%rdi), %eax Read byte and zero-extend
movq %rax, (%rsi) Store 8 bytes
int char movl (%rdi), %eax Read 4 bytes
movb %al, (%rsi) Store low-order byte
unsigned uchar movl (%rdi), %eax Read 4 bytes
movb %al, (%rsi) Store low-order byte
char short movsbw (%rdi), %ax Read byte and sign-extend
movw %ax, (%rsi) Store 2 bytes
|
;/*
; * FreeRTOS Kernel V10.4.3
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; * 1 tab == 4 spaces!
; */
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern ulMaxSyscallInterruptPriorityConst
.global _vector_14
.global _lc_ref__vector_pp_14
.global SVC_Handler
.global vPortStartFirstTask
.global vPortEnableVFP
.global ulPortSetInterruptMask
.global vPortClearInterruptMask
;-----------------------------------------------------------
.section .text
.thumb
.align 4
_vector_14: .type func
mrs r0, psp
isb
;Get the location of the current TCB.
ldr.w r3, =pxCurrentTCB
ldr r2, [r3]
;Is the task using the FPU context? If so, push high vfp registers.
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
;Save the core registers.
stmdb r0!, {r4-r11, r14}
;Save the new top of stack into the first member of the TCB.
str r0, [r2]
stmdb sp!, {r0, r3}
ldr.w r0, =ulMaxSyscallInterruptPriorityConst
ldr r0, [r0]
msr basepri, r0
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r0, r3}
;The first item in pxCurrentTCB is the task top of stack.
ldr r1, [r3]
ldr r0, [r1]
;Pop the core registers.
ldmia r0!, {r4-r11, r14}
;Is the task using the FPU context? If so, pop the high vfp registers too.
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
bx r14
.size _vector_14, $-_vector_14
.endsec
;-----------------------------------------------------------
; This function is an XMC4000 silicon errata workaround. It will get used when
; the SILICON_BUG_PMC_CM_001 linker macro is defined.
.section .text
.thumb
.align 4
_lc_ref__vector_pp_14: .type func
mrs r0, psp
isb
;Get the location of the current TCB.
ldr.w r3, =pxCurrentTCB
ldr r2, [r3]
;Is the task using the FPU context? If so, push high vfp registers.
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
;Save the core registers.
stmdb r0!, {r4-r11, r14}
;Save the new top of stack into the first member of the TCB.
str r0, [r2]
stmdb sp!, {r3}
ldr.w r0, =ulMaxSyscallInterruptPriorityConst
ldr r0, [r0]
msr basepri, r0
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r3}
;The first item in pxCurrentTCB is the task top of stack.
ldr r1, [r3]
ldr r0, [r1]
;Pop the core registers.
ldmia r0!, {r4-r11, r14}
;Is the task using the FPU context? If so, pop the high vfp registers too.
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
push { lr }
pop { pc } ; XMC4000 specific errata workaround. Do not used "bx lr" here.
.size _lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14
.endsec
;-----------------------------------------------------------
.section .text
.thumb
.align 4
SVC_Handler: .type func
;Get the location of the current TCB.
ldr.w r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
;Pop the core registers.
ldmia r0!, {r4-r11, r14}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
bx r14
.size SVC_Handler, $-SVC_Handler
.endsec
;-----------------------------------------------------------
.section .text
.thumb
.align 4
vPortStartFirstTask .type func
;Use the NVIC offset register to locate the stack.
ldr.w r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
;Set the msp back to the start of the stack.
msr msp, r0
;Call SVC to start the first task.
cpsie i
cpsie f
dsb
isb
svc 0
.size vPortStartFirstTask, $-vPortStartFirstTask
.endsec
;-----------------------------------------------------------
.section .text
.thumb
.align 4
vPortEnableVFP .type func
;The FPU enable bits are in the CPACR.
ldr.w r0, =0xE000ED88
ldr r1, [r0]
;Enable CP10 and CP11 coprocessors, then save back.
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
.size vPortEnableVFP, $-vPortEnableVFP
.endsec
;-----------------------------------------------------------
.section .text
.thumb
.align 4
ulPortSetInterruptMask:
mrs r0, basepri
ldr.w r1, =ulMaxSyscallInterruptPriorityConst
ldr r1, [r1]
msr basepri, r1
bx r14
.size ulPortSetInterruptMask, $-ulPortSetInterruptMask
.endsec
;-----------------------------------------------------------
.section .text
.thumb
.align 4
vPortClearInterruptMask:
msr basepri, r0
bx r14
.size vPortClearInterruptMask, $-vPortClearInterruptMask
.endsec
;-----------------------------------------------------------
.end
|
SECTION code_fp_mbf64
INCLUDE "mbf64.def"
EXTERN ___mbf64_FA
; Put the two arguments into the required places
;
; This is for arithmetic routines, where we need to use
; double precision values (so pad them out)
;
; Entry: dehl = right hand operand
; Stack: defw return address
; defw callee return address
; defb 8,left hand ; -> FPARG
; FA = right hand ; -> FPREG
___mbf64_setup_arith:
ld hl,___mbf64_FA
ld de,___mbf64_FPARG
ld bc,8
ldir
ld hl,4
add hl,sp
ld de,___mbf64_FPREG
ld bc,8
ld a,5
ld (___mbf64_VALTYP),a
ldir
pop bc ;ret
pop de ;callee
ld hl,8 ;remove left hand from the stack
add hl,sp
ld sp,hl
push de
push ix ;Save callers
push bc
ret
|
; A197903: Ceiling((n+1/n)^4).
; 16,40,124,327,732,1447,2604,4359,6892,10407,15132,21319,29244,39207,51532,66567,84684,106279,131772,161607,196252,236199,281964,334087,393132,459687,534364,617799,710652,813607,927372,1052679,1190284,1340967,1505532,1684807,1879644,2090919,2319532,2566407,2832492,3118759,3426204,3755847,4108732,4485927,4888524,5317639,5774412,6260007,6775612,7322439,7901724,8514727,9162732,9847047,10569004,11329959,12131292,12974407,13860732,14791719,15768844,16793607,17867532,18992167,20169084,21399879,22686172,24029607,25431852,26894599,28419564,30008487,31663132,33385287,35176764,37039399,38975052,40985607,43072972,45239079,47485884,49815367,52229532,54730407,57320044,60000519,62773932,65642407,68608092,71673159,74839804,78110247,81486732,84971527,88566924,92275239,96098812,100040007,104101212,108284839,112593324,117029127,121594732,126292647,131125404,136095559,141205692,146458407,151856332,157402119,163098444,168948007,174953532,181117767,187443484,193933479,200590572,207417607,214417452,221592999,228947164,236482887,244203132,252110887,260209164,268500999,276989452,285677607,294568572,303665479,312971484,322489767,332223532,342176007,352350444,362750119,373378332,384238407,395333692,406667559,418243404,430064647,442134732,454457127,467035324,479872839,492973212,506340007,519976812,533887239,548074924,562543527,577296732,592338247,607671804,623301159,639230092,655462407,672001932,688852519,706018044,723502407,741309532,759443367,777907884,796707079,815844972,835325607,855153052,875331399,895864764,916757287,938013132,959636487,981631564,1004002599,1026753852,1049889607,1073414172,1097331879,1121647084,1146364167,1171487532,1197021607,1222970844,1249339719,1276132732,1303354407,1331009292,1359101959,1387637004,1416619047,1446052732,1475942727,1506293724,1537110439,1568397612,1600160007,1632402412,1665129639,1698346524,1732057927,1766268732,1800983847,1836208204,1871946759,1908204492,1944986407,1982297532,2020142919,2058527644,2097456807,2136935532,2176968967,2217562284,2258720679,2300449372,2342753607,2385638652,2429109799,2473172364,2517831687,2563093132,2608962087,2655443964,2702544199,2750268252,2798621607,2847609772,2897238279,2947512684,2998438567,3050021532,3102267207,3155181244,3208769319,3263037132,3317990407,3373634892,3429976359,3487020604,3544773447,3603240732,3662428327,3722342124,3782988039,3844372012,3906500007
mov $1,2
sub $1,$0
mul $1,2
mov $3,$0
trn $0,$1
add $1,$0
add $1,12
mov $2,11
mov $4,$3
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,10
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,4
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,1
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
|
; A063139: Composite numbers which in base 3 contain their largest proper factor as a substring.
; 9,15,21,27,33,39,45,49,51,57,63,69,75,81,87,93,99,105,111,117,123,129,135,141,147,153,159,165,171,177,183,189,195,201,207,213,219,225,231,237,243,249,255,261,267,273,279,285,291,297
mov $2,$0
trn $0,6
pow $0,2
mov $1,3
trn $1,$0
mul $1,2
add $1,3
mov $3,$2
mul $3,6
add $1,$3
mov $0,$1
|
ori $t0, $0, 0xcaca
sb $t0, 0($0)
sb $t0, 1($0)
lhu $t1, 0($0)
#slt $t3, $t0, $t1
bne $t3, $0, ACA
ori $t2, $0, 0xfafa
sw $t2, 4($0)
ACA:
hlt
|
; A173468: Sum n^k, k=0..n+1.
; 3,15,121,1365,19531,335923,6725601,153391689,3922632451,111111111111,3452271214393,116719860413533,4265491084507563,167534872139182395,7037580381120954241,314824432191309680913,14942027230321957802947,749896248023298716143375,39678305316298511426319801,2207528421052631578947368421,128829043755410914596453793483,7869099649727726941903667343555,502080344178161157553355109531361,33401382933294071986203083841652825,2312964634635742792549232641855875651,166461473448801533683942072758341510103
add $0,1
mov $1,$0
mov $2,$0
lpb $1
add $0,1
mul $0,$2
sub $1,1
lpe
add $0,1
|
; A075151: a(n)=L(n)^2*C(n), L(n)=Lucas numbers (A000032), C(n)=reflected Lucas numbers (comment to A061084).
; Submitted by Christian Krause
; 8,-1,27,-64,343,-1331,5832,-24389,103823,-438976,1860867,-7880599,33386248,-141420761,599077107,-2537716544,10749963743,-45537538411,192900170952,-817138135549,3461452853383,-14662949322176,62113250509227,-263115950765039,1114577054530568,-4721424167332081,20000273726375307,-84722519068761664,358890350008010023,-1520283919090142051,6440026026385825992,-27280388024605538549,115561578124853135423,-489526700523945017536,2073668380220751423507,-8784200221406759430919,37210469265848098645768
mov $1,1
mov $3,2
lpb $0
sub $0,1
sub $1,$3
mov $2,$3
mov $3,$1
mov $1,$2
lpe
pow $3,3
mov $0,$3
|
.global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r15
push %r8
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x1c8b, %r12
nop
nop
nop
inc %rsi
movw $0x6162, (%r12)
nop
nop
nop
nop
cmp %rbx, %rbx
lea addresses_D_ht+0x1d478, %r15
nop
nop
nop
nop
dec %rdi
vmovups (%r15), %ymm6
vextracti128 $1, %ymm6, %xmm6
vpextrq $0, %xmm6, %rcx
nop
nop
sub %r15, %r15
lea addresses_WC_ht+0xf578, %rsi
lea addresses_WT_ht+0x5978, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
sub $36283, %rbp
mov $31, %rcx
rep movsw
cmp %r8, %r8
lea addresses_UC_ht+0x15e45, %rsi
lea addresses_UC_ht+0xdd78, %rdi
nop
xor $30071, %rbp
mov $114, %rcx
rep movsw
nop
nop
nop
nop
add $22596, %rbp
lea addresses_D_ht+0x7178, %rsi
nop
nop
sub %rbp, %rbp
mov $0x6162636465666768, %r12
movq %r12, (%rsi)
cmp %r8, %r8
lea addresses_A_ht+0x1c918, %rbx
nop
nop
xor %rsi, %rsi
mov (%rbx), %r8
nop
nop
nop
nop
sub $15001, %rsi
lea addresses_normal_ht+0x13578, %rsi
lea addresses_normal_ht+0x7038, %rdi
nop
nop
nop
sub %r15, %r15
mov $52, %rcx
rep movsq
nop
nop
nop
nop
nop
add %r15, %r15
lea addresses_D_ht+0x6d79, %rsi
lea addresses_WT_ht+0x5ce0, %rdi
nop
nop
nop
and %rbx, %rbx
mov $81, %rcx
rep movsq
nop
nop
nop
nop
nop
inc %r15
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r8
pop %r15
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %r13
push %r8
push %rcx
push %rdi
push %rsi
// REPMOV
lea addresses_WT+0xd78, %rsi
lea addresses_normal+0xc9a8, %rdi
nop
nop
add $21131, %r13
mov $51, %rcx
rep movsl
nop
nop
nop
nop
cmp $65278, %rsi
// Load
lea addresses_RW+0xf378, %rsi
nop
nop
nop
dec %r8
movups (%rsi), %xmm5
vpextrq $0, %xmm5, %r13
nop
nop
nop
dec %r13
// Faulty Load
lea addresses_WT+0xd78, %rdi
nop
nop
nop
nop
and %r13, %r13
mov (%rdi), %r8d
lea oracles, %r10
and $0xff, %r8
shlq $12, %r8
mov (%r10,%r8,1), %r8
pop %rsi
pop %rdi
pop %rcx
pop %r8
pop %r13
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_WT', 'same': False, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WT', 'congruent': 0, 'same': True}, 'dst': {'type': 'addresses_normal', 'congruent': 3, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_RW', 'same': False, 'size': 16, 'congruent': 8, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'type': 'addresses_WT', 'same': True, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 2, 'congruent': 0, 'NT': True, 'AVXalign': True}, 'OP': 'STOR'}
{'src': {'type': 'addresses_D_ht', 'same': False, 'size': 32, 'congruent': 5, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WC_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'OP': 'REPM'}
{'dst': {'type': 'addresses_D_ht', 'same': False, 'size': 8, 'congruent': 10, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'src': {'type': 'addresses_A_ht', 'same': False, 'size': 8, 'congruent': 2, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 6, 'same': False}, 'OP': 'REPM'}
{'src': {'type': 'addresses_D_ht', 'congruent': 0, 'same': True}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}, 'OP': 'REPM'}
{'39': 21829}
39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39
*/
|
; A244728: a(n) = 9*n^3.
; 0,9,72,243,576,1125,1944,3087,4608,6561,9000,11979,15552,19773,24696,30375,36864,44217,52488,61731,72000,83349,95832,109503,124416,140625,158184,177147,197568,219501,243000,268119,294912,323433,353736,385875,419904,455877,493848,533871,576000,620289,666792,715563,766656,820125,876024,934407,995328,1058841,1125000,1193859,1265472,1339893,1417176,1497375,1580544,1666737,1756008,1848411,1944000,2042829,2144952,2250423,2359296,2471625,2587464,2706867,2829888,2956581,3087000,3221199,3359232,3501153,3647016,3796875,3950784,4108797,4270968,4437351,4608000,4782969,4962312,5146083,5334336,5527125,5724504,5926527,6133248,6344721,6561000,6782139,7008192,7239213,7475256,7716375,7962624,8214057,8470728,8732691
pow $0,3
mul $0,9
|
[BITS 64]
[GLOBAL MoveKPCRToRegister]
[GLOBAL GetKPCR]
MoveKPCRToRegister:
mov r14, rdi
ret
GetKPCR
mov rax, r14
ret |
/* crypto/des/cfb64ede.c */
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are aheared to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the rouines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publically available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.]
*/
#include "e_os.h"
#include "des_locl.h"
/* The input and output encrypted as though 64bit cfb mode is being
* used. The extra state information to record how much of the
* 64bit block we have used is contained in *num;
*/
void DES_ede3_cfb64_encrypt(const unsigned char *in, unsigned char *out,
long length, DES_key_schedule *ks1,
DES_key_schedule *ks2, DES_key_schedule *ks3,
DES_cblock *ivec, int *num, int enc)
{
register DES_LONG v0,v1;
register long l=length;
register int n= *num;
DES_LONG ti[2];
unsigned char *iv,c,cc;
iv=&(*ivec)[0];
if (enc)
{
while (l--)
{
if (n == 0)
{
c2l(iv,v0);
c2l(iv,v1);
ti[0]=v0;
ti[1]=v1;
DES_encrypt3(ti,ks1,ks2,ks3);
v0=ti[0];
v1=ti[1];
iv = &(*ivec)[0];
l2c(v0,iv);
l2c(v1,iv);
iv = &(*ivec)[0];
}
c= *(in++)^iv[n];
*(out++)=c;
iv[n]=c;
n=(n+1)&0x07;
}
}
else
{
while (l--)
{
if (n == 0)
{
c2l(iv,v0);
c2l(iv,v1);
ti[0]=v0;
ti[1]=v1;
DES_encrypt3(ti,ks1,ks2,ks3);
v0=ti[0];
v1=ti[1];
iv = &(*ivec)[0];
l2c(v0,iv);
l2c(v1,iv);
iv = &(*ivec)[0];
}
cc= *(in++);
c=iv[n];
iv[n]=cc;
*(out++)=c^cc;
n=(n+1)&0x07;
}
}
v0=v1=ti[0]=ti[1]=c=cc=0;
*num=n;
}
#ifdef undef /* MACRO */
void DES_ede2_cfb64_encrypt(unsigned char *in, unsigned char *out, long length,
DES_key_schedule ks1, DES_key_schedule ks2, DES_cblock (*ivec),
int *num, int enc)
{
DES_ede3_cfb64_encrypt(in,out,length,ks1,ks2,ks1,ivec,num,enc);
}
#endif
/* This is compatible with the single key CFB-r for DES, even thought that's
* not what EVP needs.
*/
void DES_ede3_cfb_encrypt(const unsigned char *in,unsigned char *out,
int numbits,long length,DES_key_schedule *ks1,
DES_key_schedule *ks2,DES_key_schedule *ks3,
DES_cblock *ivec,int enc)
{
register DES_LONG d0,d1,v0,v1;
register unsigned long l=length,n=((unsigned int)numbits+7)/8;
register int num=numbits,i;
DES_LONG ti[2];
unsigned char *iv;
unsigned char ovec[16];
if (num > 64) return;
iv = &(*ivec)[0];
c2l(iv,v0);
c2l(iv,v1);
if (enc)
{
while (l >= n)
{
l-=n;
ti[0]=v0;
ti[1]=v1;
DES_encrypt3(ti,ks1,ks2,ks3);
c2ln(in,d0,d1,n);
in+=n;
d0^=ti[0];
d1^=ti[1];
l2cn(d0,d1,out,n);
out+=n;
/* 30-08-94 - eay - changed because l>>32 and
* l<<32 are bad under gcc :-( */
if (num == 32)
{ v0=v1; v1=d0; }
else if (num == 64)
{ v0=d0; v1=d1; }
else
{
iv=&ovec[0];
l2c(v0,iv);
l2c(v1,iv);
l2c(d0,iv);
l2c(d1,iv);
/* shift ovec left most of the bits... */
TINYCLR_SSL_MEMMOVE(ovec,ovec+num/8,8+(num%8 ? 1 : 0));
/* now the remaining bits */
if(num%8 != 0)
for(i=0 ; i < 8 ; ++i)
{
ovec[i]<<=num%8;
ovec[i]|=ovec[i+1]>>(8-num%8);
}
iv=&ovec[0];
c2l(iv,v0);
c2l(iv,v1);
}
}
}
else
{
while (l >= n)
{
l-=n;
ti[0]=v0;
ti[1]=v1;
DES_encrypt3(ti,ks1,ks2,ks3);
c2ln(in,d0,d1,n);
in+=n;
/* 30-08-94 - eay - changed because l>>32 and
* l<<32 are bad under gcc :-( */
if (num == 32)
{ v0=v1; v1=d0; }
else if (num == 64)
{ v0=d0; v1=d1; }
else
{
iv=&ovec[0];
l2c(v0,iv);
l2c(v1,iv);
l2c(d0,iv);
l2c(d1,iv);
/* shift ovec left most of the bits... */
TINYCLR_SSL_MEMMOVE(ovec,ovec+num/8,8+(num%8 ? 1 : 0));
/* now the remaining bits */
if(num%8 != 0)
for(i=0 ; i < 8 ; ++i)
{
ovec[i]<<=num%8;
ovec[i]|=ovec[i+1]>>(8-num%8);
}
iv=&ovec[0];
c2l(iv,v0);
c2l(iv,v1);
}
d0^=ti[0];
d1^=ti[1];
l2cn(d0,d1,out,n);
out+=n;
}
}
iv = &(*ivec)[0];
l2c(v0,iv);
l2c(v1,iv);
v0=v1=d0=d1=ti[0]=ti[1]=0;
}
|
_ln： 文件格式 elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char *argv[])
{
0: 55 push %ebp
1: 89 e5 mov %esp,%ebp
3: 53 push %ebx
4: 83 e4 f0 and $0xfffffff0,%esp
7: 83 ec 10 sub $0x10,%esp
a: 8b 5d 0c mov 0xc(%ebp),%ebx
if(argc != 3){
d: 83 7d 08 03 cmpl $0x3,0x8(%ebp)
11: 74 19 je 2c <main+0x2c>
printf(2, "Usage: ln old new\n");
13: c7 44 24 04 0d 08 00 movl $0x80d,0x4(%esp)
1a: 00
1b: c7 04 24 02 00 00 00 movl $0x2,(%esp)
22: e8 d9 03 00 00 call 400 <printf>
exit();
27: e8 66 02 00 00 call 292 <exit>
}
if(link(argv[1], argv[2]) < 0)
2c: 8b 43 08 mov 0x8(%ebx),%eax
2f: 89 44 24 04 mov %eax,0x4(%esp)
33: 8b 43 04 mov 0x4(%ebx),%eax
36: 89 04 24 mov %eax,(%esp)
39: e8 b4 02 00 00 call 2f2 <link>
3e: 85 c0 test %eax,%eax
40: 78 05 js 47 <main+0x47>
printf(2, "link %s %s: failed\n", argv[1], argv[2]);
exit();
42: e8 4b 02 00 00 call 292 <exit>
printf(2, "link %s %s: failed\n", argv[1], argv[2]);
47: 8b 43 08 mov 0x8(%ebx),%eax
4a: 89 44 24 0c mov %eax,0xc(%esp)
4e: 8b 43 04 mov 0x4(%ebx),%eax
51: c7 44 24 04 20 08 00 movl $0x820,0x4(%esp)
58: 00
59: c7 04 24 02 00 00 00 movl $0x2,(%esp)
60: 89 44 24 08 mov %eax,0x8(%esp)
64: e8 97 03 00 00 call 400 <printf>
69: eb d7 jmp 42 <main+0x42>
6b: 66 90 xchg %ax,%ax
6d: 66 90 xchg %ax,%ax
6f: 90 nop
00000070 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, const char *t)
{
70: 55 push %ebp
71: 89 e5 mov %esp,%ebp
73: 8b 45 08 mov 0x8(%ebp),%eax
76: 8b 4d 0c mov 0xc(%ebp),%ecx
79: 53 push %ebx
char *os;
os = s;
while((*s++ = *t++) != 0)
7a: 89 c2 mov %eax,%edx
7c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
80: 83 c1 01 add $0x1,%ecx
83: 0f b6 59 ff movzbl -0x1(%ecx),%ebx
87: 83 c2 01 add $0x1,%edx
8a: 84 db test %bl,%bl
8c: 88 5a ff mov %bl,-0x1(%edx)
8f: 75 ef jne 80 <strcpy+0x10>
;
return os;
}
91: 5b pop %ebx
92: 5d pop %ebp
93: c3 ret
94: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
9a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
000000a0 <strcmp>:
int
strcmp(const char *p, const char *q)
{
a0: 55 push %ebp
a1: 89 e5 mov %esp,%ebp
a3: 8b 55 08 mov 0x8(%ebp),%edx
a6: 53 push %ebx
a7: 8b 4d 0c mov 0xc(%ebp),%ecx
while(*p && *p == *q)
aa: 0f b6 02 movzbl (%edx),%eax
ad: 84 c0 test %al,%al
af: 74 2d je de <strcmp+0x3e>
b1: 0f b6 19 movzbl (%ecx),%ebx
b4: 38 d8 cmp %bl,%al
b6: 74 0e je c6 <strcmp+0x26>
b8: eb 2b jmp e5 <strcmp+0x45>
ba: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
c0: 38 c8 cmp %cl,%al
c2: 75 15 jne d9 <strcmp+0x39>
p++, q++;
c4: 89 d9 mov %ebx,%ecx
c6: 83 c2 01 add $0x1,%edx
while(*p && *p == *q)
c9: 0f b6 02 movzbl (%edx),%eax
p++, q++;
cc: 8d 59 01 lea 0x1(%ecx),%ebx
while(*p && *p == *q)
cf: 0f b6 49 01 movzbl 0x1(%ecx),%ecx
d3: 84 c0 test %al,%al
d5: 75 e9 jne c0 <strcmp+0x20>
d7: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
d9: 29 c8 sub %ecx,%eax
}
db: 5b pop %ebx
dc: 5d pop %ebp
dd: c3 ret
de: 0f b6 09 movzbl (%ecx),%ecx
while(*p && *p == *q)
e1: 31 c0 xor %eax,%eax
e3: eb f4 jmp d9 <strcmp+0x39>
e5: 0f b6 cb movzbl %bl,%ecx
e8: eb ef jmp d9 <strcmp+0x39>
ea: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
000000f0 <strlen>:
uint
strlen(const char *s)
{
f0: 55 push %ebp
f1: 89 e5 mov %esp,%ebp
f3: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
for(n = 0; s[n]; n++)
f6: 80 39 00 cmpb $0x0,(%ecx)
f9: 74 12 je 10d <strlen+0x1d>
fb: 31 d2 xor %edx,%edx
fd: 8d 76 00 lea 0x0(%esi),%esi
100: 83 c2 01 add $0x1,%edx
103: 80 3c 11 00 cmpb $0x0,(%ecx,%edx,1)
107: 89 d0 mov %edx,%eax
109: 75 f5 jne 100 <strlen+0x10>
;
return n;
}
10b: 5d pop %ebp
10c: c3 ret
for(n = 0; s[n]; n++)
10d: 31 c0 xor %eax,%eax
}
10f: 5d pop %ebp
110: c3 ret
111: eb 0d jmp 120 <memset>
113: 90 nop
114: 90 nop
115: 90 nop
116: 90 nop
117: 90 nop
118: 90 nop
119: 90 nop
11a: 90 nop
11b: 90 nop
11c: 90 nop
11d: 90 nop
11e: 90 nop
11f: 90 nop
00000120 <memset>:
void*
memset(void *dst, int c, uint n)
{
120: 55 push %ebp
121: 89 e5 mov %esp,%ebp
123: 8b 55 08 mov 0x8(%ebp),%edx
126: 57 push %edi
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
127: 8b 4d 10 mov 0x10(%ebp),%ecx
12a: 8b 45 0c mov 0xc(%ebp),%eax
12d: 89 d7 mov %edx,%edi
12f: fc cld
130: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
132: 89 d0 mov %edx,%eax
134: 5f pop %edi
135: 5d pop %ebp
136: c3 ret
137: 89 f6 mov %esi,%esi
139: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000140 <strchr>:
char*
strchr(const char *s, char c)
{
140: 55 push %ebp
141: 89 e5 mov %esp,%ebp
143: 8b 45 08 mov 0x8(%ebp),%eax
146: 53 push %ebx
147: 8b 55 0c mov 0xc(%ebp),%edx
for(; *s; s++)
14a: 0f b6 18 movzbl (%eax),%ebx
14d: 84 db test %bl,%bl
14f: 74 1d je 16e <strchr+0x2e>
if(*s == c)
151: 38 d3 cmp %dl,%bl
153: 89 d1 mov %edx,%ecx
155: 75 0d jne 164 <strchr+0x24>
157: eb 17 jmp 170 <strchr+0x30>
159: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
160: 38 ca cmp %cl,%dl
162: 74 0c je 170 <strchr+0x30>
for(; *s; s++)
164: 83 c0 01 add $0x1,%eax
167: 0f b6 10 movzbl (%eax),%edx
16a: 84 d2 test %dl,%dl
16c: 75 f2 jne 160 <strchr+0x20>
return (char*)s;
return 0;
16e: 31 c0 xor %eax,%eax
}
170: 5b pop %ebx
171: 5d pop %ebp
172: c3 ret
173: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
179: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000180 <gets>:
char*
gets(char *buf, int max)
{
180: 55 push %ebp
181: 89 e5 mov %esp,%ebp
183: 57 push %edi
184: 56 push %esi
int i, cc;
char c;
for(i=0; i+1 < max; ){
185: 31 f6 xor %esi,%esi
{
187: 53 push %ebx
188: 83 ec 2c sub $0x2c,%esp
cc = read(0, &c, 1);
18b: 8d 7d e7 lea -0x19(%ebp),%edi
for(i=0; i+1 < max; ){
18e: eb 31 jmp 1c1 <gets+0x41>
cc = read(0, &c, 1);
190: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
197: 00
198: 89 7c 24 04 mov %edi,0x4(%esp)
19c: c7 04 24 00 00 00 00 movl $0x0,(%esp)
1a3: e8 02 01 00 00 call 2aa <read>
if(cc < 1)
1a8: 85 c0 test %eax,%eax
1aa: 7e 1d jle 1c9 <gets+0x49>
break;
buf[i++] = c;
1ac: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
for(i=0; i+1 < max; ){
1b0: 89 de mov %ebx,%esi
buf[i++] = c;
1b2: 8b 55 08 mov 0x8(%ebp),%edx
if(c == '\n' || c == '\r')
1b5: 3c 0d cmp $0xd,%al
buf[i++] = c;
1b7: 88 44 1a ff mov %al,-0x1(%edx,%ebx,1)
if(c == '\n' || c == '\r')
1bb: 74 0c je 1c9 <gets+0x49>
1bd: 3c 0a cmp $0xa,%al
1bf: 74 08 je 1c9 <gets+0x49>
for(i=0; i+1 < max; ){
1c1: 8d 5e 01 lea 0x1(%esi),%ebx
1c4: 3b 5d 0c cmp 0xc(%ebp),%ebx
1c7: 7c c7 jl 190 <gets+0x10>
break;
}
buf[i] = '\0';
1c9: 8b 45 08 mov 0x8(%ebp),%eax
1cc: c6 04 30 00 movb $0x0,(%eax,%esi,1)
return buf;
}
1d0: 83 c4 2c add $0x2c,%esp
1d3: 5b pop %ebx
1d4: 5e pop %esi
1d5: 5f pop %edi
1d6: 5d pop %ebp
1d7: c3 ret
1d8: 90 nop
1d9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
000001e0 <stat>:
int
stat(const char *n, struct stat *st)
{
1e0: 55 push %ebp
1e1: 89 e5 mov %esp,%ebp
1e3: 56 push %esi
1e4: 53 push %ebx
1e5: 83 ec 10 sub $0x10,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
1e8: 8b 45 08 mov 0x8(%ebp),%eax
1eb: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1f2: 00
1f3: 89 04 24 mov %eax,(%esp)
1f6: e8 d7 00 00 00 call 2d2 <open>
if(fd < 0)
1fb: 85 c0 test %eax,%eax
fd = open(n, O_RDONLY);
1fd: 89 c3 mov %eax,%ebx
if(fd < 0)
1ff: 78 27 js 228 <stat+0x48>
return -1;
r = fstat(fd, st);
201: 8b 45 0c mov 0xc(%ebp),%eax
204: 89 1c 24 mov %ebx,(%esp)
207: 89 44 24 04 mov %eax,0x4(%esp)
20b: e8 da 00 00 00 call 2ea <fstat>
close(fd);
210: 89 1c 24 mov %ebx,(%esp)
r = fstat(fd, st);
213: 89 c6 mov %eax,%esi
close(fd);
215: e8 a0 00 00 00 call 2ba <close>
return r;
21a: 89 f0 mov %esi,%eax
}
21c: 83 c4 10 add $0x10,%esp
21f: 5b pop %ebx
220: 5e pop %esi
221: 5d pop %ebp
222: c3 ret
223: 90 nop
224: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
return -1;
228: b8 ff ff ff ff mov $0xffffffff,%eax
22d: eb ed jmp 21c <stat+0x3c>
22f: 90 nop
00000230 <atoi>:
int
atoi(const char *s)
{
230: 55 push %ebp
231: 89 e5 mov %esp,%ebp
233: 8b 4d 08 mov 0x8(%ebp),%ecx
236: 53 push %ebx
int n;
n = 0;
while('0' <= *s && *s <= '9')
237: 0f be 11 movsbl (%ecx),%edx
23a: 8d 42 d0 lea -0x30(%edx),%eax
23d: 3c 09 cmp $0x9,%al
n = 0;
23f: b8 00 00 00 00 mov $0x0,%eax
while('0' <= *s && *s <= '9')
244: 77 17 ja 25d <atoi+0x2d>
246: 66 90 xchg %ax,%ax
n = n*10 + *s++ - '0';
248: 83 c1 01 add $0x1,%ecx
24b: 8d 04 80 lea (%eax,%eax,4),%eax
24e: 8d 44 42 d0 lea -0x30(%edx,%eax,2),%eax
while('0' <= *s && *s <= '9')
252: 0f be 11 movsbl (%ecx),%edx
255: 8d 5a d0 lea -0x30(%edx),%ebx
258: 80 fb 09 cmp $0x9,%bl
25b: 76 eb jbe 248 <atoi+0x18>
return n;
}
25d: 5b pop %ebx
25e: 5d pop %ebp
25f: c3 ret
00000260 <memmove>:
void*
memmove(void *vdst, const void *vsrc, int n)
{
260: 55 push %ebp
char *dst;
const char *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
261: 31 d2 xor %edx,%edx
{
263: 89 e5 mov %esp,%ebp
265: 56 push %esi
266: 8b 45 08 mov 0x8(%ebp),%eax
269: 53 push %ebx
26a: 8b 5d 10 mov 0x10(%ebp),%ebx
26d: 8b 75 0c mov 0xc(%ebp),%esi
while(n-- > 0)
270: 85 db test %ebx,%ebx
272: 7e 12 jle 286 <memmove+0x26>
274: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
*dst++ = *src++;
278: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
27c: 88 0c 10 mov %cl,(%eax,%edx,1)
27f: 83 c2 01 add $0x1,%edx
while(n-- > 0)
282: 39 da cmp %ebx,%edx
284: 75 f2 jne 278 <memmove+0x18>
return vdst;
}
286: 5b pop %ebx
287: 5e pop %esi
288: 5d pop %ebp
289: c3 ret
0000028a <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
28a: b8 01 00 00 00 mov $0x1,%eax
28f: cd 40 int $0x40
291: c3 ret
00000292 <exit>:
SYSCALL(exit)
292: b8 02 00 00 00 mov $0x2,%eax
297: cd 40 int $0x40
299: c3 ret
0000029a <wait>:
SYSCALL(wait)
29a: b8 03 00 00 00 mov $0x3,%eax
29f: cd 40 int $0x40
2a1: c3 ret
000002a2 <pipe>:
SYSCALL(pipe)
2a2: b8 04 00 00 00 mov $0x4,%eax
2a7: cd 40 int $0x40
2a9: c3 ret
000002aa <read>:
SYSCALL(read)
2aa: b8 05 00 00 00 mov $0x5,%eax
2af: cd 40 int $0x40
2b1: c3 ret
000002b2 <write>:
SYSCALL(write)
2b2: b8 10 00 00 00 mov $0x10,%eax
2b7: cd 40 int $0x40
2b9: c3 ret
000002ba <close>:
SYSCALL(close)
2ba: b8 15 00 00 00 mov $0x15,%eax
2bf: cd 40 int $0x40
2c1: c3 ret
000002c2 <kill>:
SYSCALL(kill)
2c2: b8 06 00 00 00 mov $0x6,%eax
2c7: cd 40 int $0x40
2c9: c3 ret
000002ca <exec>:
SYSCALL(exec)
2ca: b8 07 00 00 00 mov $0x7,%eax
2cf: cd 40 int $0x40
2d1: c3 ret
000002d2 <open>:
SYSCALL(open)
2d2: b8 0f 00 00 00 mov $0xf,%eax
2d7: cd 40 int $0x40
2d9: c3 ret
000002da <mknod>:
SYSCALL(mknod)
2da: b8 11 00 00 00 mov $0x11,%eax
2df: cd 40 int $0x40
2e1: c3 ret
000002e2 <unlink>:
SYSCALL(unlink)
2e2: b8 12 00 00 00 mov $0x12,%eax
2e7: cd 40 int $0x40
2e9: c3 ret
000002ea <fstat>:
SYSCALL(fstat)
2ea: b8 08 00 00 00 mov $0x8,%eax
2ef: cd 40 int $0x40
2f1: c3 ret
000002f2 <link>:
SYSCALL(link)
2f2: b8 13 00 00 00 mov $0x13,%eax
2f7: cd 40 int $0x40
2f9: c3 ret
000002fa <mkdir>:
SYSCALL(mkdir)
2fa: b8 14 00 00 00 mov $0x14,%eax
2ff: cd 40 int $0x40
301: c3 ret
00000302 <chdir>:
SYSCALL(chdir)
302: b8 09 00 00 00 mov $0x9,%eax
307: cd 40 int $0x40
309: c3 ret
0000030a <dup>:
SYSCALL(dup)
30a: b8 0a 00 00 00 mov $0xa,%eax
30f: cd 40 int $0x40
311: c3 ret
00000312 <getpid>:
SYSCALL(getpid)
312: b8 0b 00 00 00 mov $0xb,%eax
317: cd 40 int $0x40
319: c3 ret
0000031a <sbrk>:
SYSCALL(sbrk)
31a: b8 0c 00 00 00 mov $0xc,%eax
31f: cd 40 int $0x40
321: c3 ret
00000322 <sleep>:
SYSCALL(sleep)
322: b8 0d 00 00 00 mov $0xd,%eax
327: cd 40 int $0x40
329: c3 ret
0000032a <uptime>:
SYSCALL(uptime)
32a: b8 0e 00 00 00 mov $0xe,%eax
32f: cd 40 int $0x40
331: c3 ret
00000332 <info>:
SYSCALL(info)
332: b8 16 00 00 00 mov $0x16,%eax
337: cd 40 int $0x40
339: c3 ret
0000033a <settick>:
SYSCALL(settick)
33a: b8 17 00 00 00 mov $0x17,%eax
33f: cd 40 int $0x40
341: c3 ret
00000342 <tickprintf>:
SYSCALL(tickprintf)
342: b8 18 00 00 00 mov $0x18,%eax
347: cd 40 int $0x40
349: c3 ret
0000034a <clone>:
SYSCALL(clone)
34a: b8 19 00 00 00 mov $0x19,%eax
34f: cd 40 int $0x40
351: c3 ret
352: 66 90 xchg %ax,%ax
354: 66 90 xchg %ax,%ax
356: 66 90 xchg %ax,%ax
358: 66 90 xchg %ax,%ax
35a: 66 90 xchg %ax,%ax
35c: 66 90 xchg %ax,%ax
35e: 66 90 xchg %ax,%ax
00000360 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
360: 55 push %ebp
361: 89 e5 mov %esp,%ebp
363: 57 push %edi
364: 56 push %esi
365: 89 c6 mov %eax,%esi
367: 53 push %ebx
368: 83 ec 4c sub $0x4c,%esp
char buf[16];
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
36b: 8b 5d 08 mov 0x8(%ebp),%ebx
36e: 85 db test %ebx,%ebx
370: 74 09 je 37b <printint+0x1b>
372: 89 d0 mov %edx,%eax
374: c1 e8 1f shr $0x1f,%eax
377: 84 c0 test %al,%al
379: 75 75 jne 3f0 <printint+0x90>
neg = 1;
x = -xx;
} else {
x = xx;
37b: 89 d0 mov %edx,%eax
neg = 0;
37d: c7 45 c4 00 00 00 00 movl $0x0,-0x3c(%ebp)
384: 89 75 c0 mov %esi,-0x40(%ebp)
}
i = 0;
387: 31 ff xor %edi,%edi
389: 89 ce mov %ecx,%esi
38b: 8d 5d d7 lea -0x29(%ebp),%ebx
38e: eb 02 jmp 392 <printint+0x32>
do{
buf[i++] = digits[x % base];
390: 89 cf mov %ecx,%edi
392: 31 d2 xor %edx,%edx
394: f7 f6 div %esi
396: 8d 4f 01 lea 0x1(%edi),%ecx
399: 0f b6 92 3b 08 00 00 movzbl 0x83b(%edx),%edx
}while((x /= base) != 0);
3a0: 85 c0 test %eax,%eax
buf[i++] = digits[x % base];
3a2: 88 14 0b mov %dl,(%ebx,%ecx,1)
}while((x /= base) != 0);
3a5: 75 e9 jne 390 <printint+0x30>
if(neg)
3a7: 8b 55 c4 mov -0x3c(%ebp),%edx
buf[i++] = digits[x % base];
3aa: 89 c8 mov %ecx,%eax
3ac: 8b 75 c0 mov -0x40(%ebp),%esi
if(neg)
3af: 85 d2 test %edx,%edx
3b1: 74 08 je 3bb <printint+0x5b>
buf[i++] = '-';
3b3: 8d 4f 02 lea 0x2(%edi),%ecx
3b6: c6 44 05 d8 2d movb $0x2d,-0x28(%ebp,%eax,1)
while(--i >= 0)
3bb: 8d 79 ff lea -0x1(%ecx),%edi
3be: 66 90 xchg %ax,%ax
3c0: 0f b6 44 3d d8 movzbl -0x28(%ebp,%edi,1),%eax
3c5: 83 ef 01 sub $0x1,%edi
write(fd, &c, 1);
3c8: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3cf: 00
3d0: 89 5c 24 04 mov %ebx,0x4(%esp)
3d4: 89 34 24 mov %esi,(%esp)
3d7: 88 45 d7 mov %al,-0x29(%ebp)
3da: e8 d3 fe ff ff call 2b2 <write>
while(--i >= 0)
3df: 83 ff ff cmp $0xffffffff,%edi
3e2: 75 dc jne 3c0 <printint+0x60>
putc(fd, buf[i]);
}
3e4: 83 c4 4c add $0x4c,%esp
3e7: 5b pop %ebx
3e8: 5e pop %esi
3e9: 5f pop %edi
3ea: 5d pop %ebp
3eb: c3 ret
3ec: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
x = -xx;
3f0: 89 d0 mov %edx,%eax
3f2: f7 d8 neg %eax
neg = 1;
3f4: c7 45 c4 01 00 00 00 movl $0x1,-0x3c(%ebp)
3fb: eb 87 jmp 384 <printint+0x24>
3fd: 8d 76 00 lea 0x0(%esi),%esi
00000400 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, const char *fmt, ...)
{
400: 55 push %ebp
401: 89 e5 mov %esp,%ebp
403: 57 push %edi
char *s;
int c, i, state;
uint *ap;
state = 0;
404: 31 ff xor %edi,%edi
{
406: 56 push %esi
407: 53 push %ebx
408: 83 ec 3c sub $0x3c,%esp
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
40b: 8b 5d 0c mov 0xc(%ebp),%ebx
ap = (uint*)(void*)&fmt + 1;
40e: 8d 45 10 lea 0x10(%ebp),%eax
{
411: 8b 75 08 mov 0x8(%ebp),%esi
ap = (uint*)(void*)&fmt + 1;
414: 89 45 d4 mov %eax,-0x2c(%ebp)
for(i = 0; fmt[i]; i++){
417: 0f b6 13 movzbl (%ebx),%edx
41a: 83 c3 01 add $0x1,%ebx
41d: 84 d2 test %dl,%dl
41f: 75 39 jne 45a <printf+0x5a>
421: e9 c2 00 00 00 jmp 4e8 <printf+0xe8>
426: 66 90 xchg %ax,%ax
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
428: 83 fa 25 cmp $0x25,%edx
42b: 0f 84 bf 00 00 00 je 4f0 <printf+0xf0>
write(fd, &c, 1);
431: 8d 45 e2 lea -0x1e(%ebp),%eax
434: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
43b: 00
43c: 89 44 24 04 mov %eax,0x4(%esp)
440: 89 34 24 mov %esi,(%esp)
state = '%';
} else {
putc(fd, c);
443: 88 55 e2 mov %dl,-0x1e(%ebp)
write(fd, &c, 1);
446: e8 67 fe ff ff call 2b2 <write>
44b: 83 c3 01 add $0x1,%ebx
for(i = 0; fmt[i]; i++){
44e: 0f b6 53 ff movzbl -0x1(%ebx),%edx
452: 84 d2 test %dl,%dl
454: 0f 84 8e 00 00 00 je 4e8 <printf+0xe8>
if(state == 0){
45a: 85 ff test %edi,%edi
c = fmt[i] & 0xff;
45c: 0f be c2 movsbl %dl,%eax
if(state == 0){
45f: 74 c7 je 428 <printf+0x28>
}
} else if(state == '%'){
461: 83 ff 25 cmp $0x25,%edi
464: 75 e5 jne 44b <printf+0x4b>
if(c == 'd'){
466: 83 fa 64 cmp $0x64,%edx
469: 0f 84 31 01 00 00 je 5a0 <printf+0x1a0>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
46f: 25 f7 00 00 00 and $0xf7,%eax
474: 83 f8 70 cmp $0x70,%eax
477: 0f 84 83 00 00 00 je 500 <printf+0x100>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
47d: 83 fa 73 cmp $0x73,%edx
480: 0f 84 a2 00 00 00 je 528 <printf+0x128>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
486: 83 fa 63 cmp $0x63,%edx
489: 0f 84 35 01 00 00 je 5c4 <printf+0x1c4>
putc(fd, *ap);
ap++;
} else if(c == '%'){
48f: 83 fa 25 cmp $0x25,%edx
492: 0f 84 e0 00 00 00 je 578 <printf+0x178>
write(fd, &c, 1);
498: 8d 45 e6 lea -0x1a(%ebp),%eax
49b: 83 c3 01 add $0x1,%ebx
49e: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
4a5: 00
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
}
state = 0;
4a6: 31 ff xor %edi,%edi
write(fd, &c, 1);
4a8: 89 44 24 04 mov %eax,0x4(%esp)
4ac: 89 34 24 mov %esi,(%esp)
4af: 89 55 d0 mov %edx,-0x30(%ebp)
4b2: c6 45 e6 25 movb $0x25,-0x1a(%ebp)
4b6: e8 f7 fd ff ff call 2b2 <write>
putc(fd, c);
4bb: 8b 55 d0 mov -0x30(%ebp),%edx
write(fd, &c, 1);
4be: 8d 45 e7 lea -0x19(%ebp),%eax
4c1: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
4c8: 00
4c9: 89 44 24 04 mov %eax,0x4(%esp)
4cd: 89 34 24 mov %esi,(%esp)
putc(fd, c);
4d0: 88 55 e7 mov %dl,-0x19(%ebp)
write(fd, &c, 1);
4d3: e8 da fd ff ff call 2b2 <write>
for(i = 0; fmt[i]; i++){
4d8: 0f b6 53 ff movzbl -0x1(%ebx),%edx
4dc: 84 d2 test %dl,%dl
4de: 0f 85 76 ff ff ff jne 45a <printf+0x5a>
4e4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
}
}
}
4e8: 83 c4 3c add $0x3c,%esp
4eb: 5b pop %ebx
4ec: 5e pop %esi
4ed: 5f pop %edi
4ee: 5d pop %ebp
4ef: c3 ret
state = '%';
4f0: bf 25 00 00 00 mov $0x25,%edi
4f5: e9 51 ff ff ff jmp 44b <printf+0x4b>
4fa: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
printint(fd, *ap, 16, 0);
500: 8b 45 d4 mov -0x2c(%ebp),%eax
503: b9 10 00 00 00 mov $0x10,%ecx
state = 0;
508: 31 ff xor %edi,%edi
printint(fd, *ap, 16, 0);
50a: c7 04 24 00 00 00 00 movl $0x0,(%esp)
511: 8b 10 mov (%eax),%edx
513: 89 f0 mov %esi,%eax
515: e8 46 fe ff ff call 360 <printint>
ap++;
51a: 83 45 d4 04 addl $0x4,-0x2c(%ebp)
51e: e9 28 ff ff ff jmp 44b <printf+0x4b>
523: 90 nop
524: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
s = (char*)*ap;
528: 8b 45 d4 mov -0x2c(%ebp),%eax
ap++;
52b: 83 45 d4 04 addl $0x4,-0x2c(%ebp)
s = (char*)*ap;
52f: 8b 38 mov (%eax),%edi
s = "(null)";
531: b8 34 08 00 00 mov $0x834,%eax
536: 85 ff test %edi,%edi
538: 0f 44 f8 cmove %eax,%edi
while(*s != 0){
53b: 0f b6 07 movzbl (%edi),%eax
53e: 84 c0 test %al,%al
540: 74 2a je 56c <printf+0x16c>
542: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
548: 88 45 e3 mov %al,-0x1d(%ebp)
write(fd, &c, 1);
54b: 8d 45 e3 lea -0x1d(%ebp),%eax
s++;
54e: 83 c7 01 add $0x1,%edi
write(fd, &c, 1);
551: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
558: 00
559: 89 44 24 04 mov %eax,0x4(%esp)
55d: 89 34 24 mov %esi,(%esp)
560: e8 4d fd ff ff call 2b2 <write>
while(*s != 0){
565: 0f b6 07 movzbl (%edi),%eax
568: 84 c0 test %al,%al
56a: 75 dc jne 548 <printf+0x148>
state = 0;
56c: 31 ff xor %edi,%edi
56e: e9 d8 fe ff ff jmp 44b <printf+0x4b>
573: 90 nop
574: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
write(fd, &c, 1);
578: 8d 45 e5 lea -0x1b(%ebp),%eax
state = 0;
57b: 31 ff xor %edi,%edi
write(fd, &c, 1);
57d: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
584: 00
585: 89 44 24 04 mov %eax,0x4(%esp)
589: 89 34 24 mov %esi,(%esp)
58c: c6 45 e5 25 movb $0x25,-0x1b(%ebp)
590: e8 1d fd ff ff call 2b2 <write>
595: e9 b1 fe ff ff jmp 44b <printf+0x4b>
59a: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
printint(fd, *ap, 10, 1);
5a0: 8b 45 d4 mov -0x2c(%ebp),%eax
5a3: b9 0a 00 00 00 mov $0xa,%ecx
state = 0;
5a8: 66 31 ff xor %di,%di
printint(fd, *ap, 10, 1);
5ab: c7 04 24 01 00 00 00 movl $0x1,(%esp)
5b2: 8b 10 mov (%eax),%edx
5b4: 89 f0 mov %esi,%eax
5b6: e8 a5 fd ff ff call 360 <printint>
ap++;
5bb: 83 45 d4 04 addl $0x4,-0x2c(%ebp)
5bf: e9 87 fe ff ff jmp 44b <printf+0x4b>
putc(fd, *ap);
5c4: 8b 45 d4 mov -0x2c(%ebp),%eax
state = 0;
5c7: 31 ff xor %edi,%edi
putc(fd, *ap);
5c9: 8b 00 mov (%eax),%eax
write(fd, &c, 1);
5cb: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
5d2: 00
5d3: 89 34 24 mov %esi,(%esp)
putc(fd, *ap);
5d6: 88 45 e4 mov %al,-0x1c(%ebp)
write(fd, &c, 1);
5d9: 8d 45 e4 lea -0x1c(%ebp),%eax
5dc: 89 44 24 04 mov %eax,0x4(%esp)
5e0: e8 cd fc ff ff call 2b2 <write>
ap++;
5e5: 83 45 d4 04 addl $0x4,-0x2c(%ebp)
5e9: e9 5d fe ff ff jmp 44b <printf+0x4b>
5ee: 66 90 xchg %ax,%ax
000005f0 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
5f0: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
5f1: a1 38 0b 00 00 mov 0xb38,%eax
{
5f6: 89 e5 mov %esp,%ebp
5f8: 57 push %edi
5f9: 56 push %esi
5fa: 53 push %ebx
5fb: 8b 5d 08 mov 0x8(%ebp),%ebx
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
5fe: 8b 08 mov (%eax),%ecx
bp = (Header*)ap - 1;
600: 8d 53 f8 lea -0x8(%ebx),%edx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
603: 39 d0 cmp %edx,%eax
605: 72 11 jb 618 <free+0x28>
607: 90 nop
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
608: 39 c8 cmp %ecx,%eax
60a: 72 04 jb 610 <free+0x20>
60c: 39 ca cmp %ecx,%edx
60e: 72 10 jb 620 <free+0x30>
610: 89 c8 mov %ecx,%eax
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
612: 39 d0 cmp %edx,%eax
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
614: 8b 08 mov (%eax),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
616: 73 f0 jae 608 <free+0x18>
618: 39 ca cmp %ecx,%edx
61a: 72 04 jb 620 <free+0x30>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
61c: 39 c8 cmp %ecx,%eax
61e: 72 f0 jb 610 <free+0x20>
break;
if(bp + bp->s.size == p->s.ptr){
620: 8b 73 fc mov -0x4(%ebx),%esi
623: 8d 3c f2 lea (%edx,%esi,8),%edi
626: 39 cf cmp %ecx,%edi
628: 74 1e je 648 <free+0x58>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
62a: 89 4b f8 mov %ecx,-0x8(%ebx)
if(p + p->s.size == bp){
62d: 8b 48 04 mov 0x4(%eax),%ecx
630: 8d 34 c8 lea (%eax,%ecx,8),%esi
633: 39 f2 cmp %esi,%edx
635: 74 28 je 65f <free+0x6f>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
637: 89 10 mov %edx,(%eax)
freep = p;
639: a3 38 0b 00 00 mov %eax,0xb38
}
63e: 5b pop %ebx
63f: 5e pop %esi
640: 5f pop %edi
641: 5d pop %ebp
642: c3 ret
643: 90 nop
644: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
bp->s.size += p->s.ptr->s.size;
648: 03 71 04 add 0x4(%ecx),%esi
64b: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
64e: 8b 08 mov (%eax),%ecx
650: 8b 09 mov (%ecx),%ecx
652: 89 4b f8 mov %ecx,-0x8(%ebx)
if(p + p->s.size == bp){
655: 8b 48 04 mov 0x4(%eax),%ecx
658: 8d 34 c8 lea (%eax,%ecx,8),%esi
65b: 39 f2 cmp %esi,%edx
65d: 75 d8 jne 637 <free+0x47>
p->s.size += bp->s.size;
65f: 03 4b fc add -0x4(%ebx),%ecx
freep = p;
662: a3 38 0b 00 00 mov %eax,0xb38
p->s.size += bp->s.size;
667: 89 48 04 mov %ecx,0x4(%eax)
p->s.ptr = bp->s.ptr;
66a: 8b 53 f8 mov -0x8(%ebx),%edx
66d: 89 10 mov %edx,(%eax)
}
66f: 5b pop %ebx
670: 5e pop %esi
671: 5f pop %edi
672: 5d pop %ebp
673: c3 ret
674: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
67a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
00000680 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
680: 55 push %ebp
681: 89 e5 mov %esp,%ebp
683: 57 push %edi
684: 56 push %esi
685: 53 push %ebx
686: 83 ec 1c sub $0x1c,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
689: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
68c: 8b 1d 38 0b 00 00 mov 0xb38,%ebx
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
692: 8d 48 07 lea 0x7(%eax),%ecx
695: c1 e9 03 shr $0x3,%ecx
if((prevp = freep) == 0){
698: 85 db test %ebx,%ebx
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
69a: 8d 71 01 lea 0x1(%ecx),%esi
if((prevp = freep) == 0){
69d: 0f 84 9b 00 00 00 je 73e <malloc+0xbe>
6a3: 8b 13 mov (%ebx),%edx
6a5: 8b 7a 04 mov 0x4(%edx),%edi
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
6a8: 39 fe cmp %edi,%esi
6aa: 76 64 jbe 710 <malloc+0x90>
6ac: 8d 04 f5 00 00 00 00 lea 0x0(,%esi,8),%eax
if(nu < 4096)
6b3: bb 00 80 00 00 mov $0x8000,%ebx
6b8: 89 45 e4 mov %eax,-0x1c(%ebp)
6bb: eb 0e jmp 6cb <malloc+0x4b>
6bd: 8d 76 00 lea 0x0(%esi),%esi
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
6c0: 8b 02 mov (%edx),%eax
if(p->s.size >= nunits){
6c2: 8b 78 04 mov 0x4(%eax),%edi
6c5: 39 fe cmp %edi,%esi
6c7: 76 4f jbe 718 <malloc+0x98>
6c9: 89 c2 mov %eax,%edx
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
6cb: 3b 15 38 0b 00 00 cmp 0xb38,%edx
6d1: 75 ed jne 6c0 <malloc+0x40>
if(nu < 4096)
6d3: 8b 45 e4 mov -0x1c(%ebp),%eax
6d6: 81 fe 00 10 00 00 cmp $0x1000,%esi
6dc: bf 00 10 00 00 mov $0x1000,%edi
6e1: 0f 43 fe cmovae %esi,%edi
6e4: 0f 42 c3 cmovb %ebx,%eax
p = sbrk(nu * sizeof(Header));
6e7: 89 04 24 mov %eax,(%esp)
6ea: e8 2b fc ff ff call 31a <sbrk>
if(p == (char*)-1)
6ef: 83 f8 ff cmp $0xffffffff,%eax
6f2: 74 18 je 70c <malloc+0x8c>
hp->s.size = nu;
6f4: 89 78 04 mov %edi,0x4(%eax)
free((void*)(hp + 1));
6f7: 83 c0 08 add $0x8,%eax
6fa: 89 04 24 mov %eax,(%esp)
6fd: e8 ee fe ff ff call 5f0 <free>
return freep;
702: 8b 15 38 0b 00 00 mov 0xb38,%edx
if((p = morecore(nunits)) == 0)
708: 85 d2 test %edx,%edx
70a: 75 b4 jne 6c0 <malloc+0x40>
return 0;
70c: 31 c0 xor %eax,%eax
70e: eb 20 jmp 730 <malloc+0xb0>
if(p->s.size >= nunits){
710: 89 d0 mov %edx,%eax
712: 89 da mov %ebx,%edx
714: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
if(p->s.size == nunits)
718: 39 fe cmp %edi,%esi
71a: 74 1c je 738 <malloc+0xb8>
p->s.size -= nunits;
71c: 29 f7 sub %esi,%edi
71e: 89 78 04 mov %edi,0x4(%eax)
p += p->s.size;
721: 8d 04 f8 lea (%eax,%edi,8),%eax
p->s.size = nunits;
724: 89 70 04 mov %esi,0x4(%eax)
freep = prevp;
727: 89 15 38 0b 00 00 mov %edx,0xb38
return (void*)(p + 1);
72d: 83 c0 08 add $0x8,%eax
}
}
730: 83 c4 1c add $0x1c,%esp
733: 5b pop %ebx
734: 5e pop %esi
735: 5f pop %edi
736: 5d pop %ebp
737: c3 ret
prevp->s.ptr = p->s.ptr;
738: 8b 08 mov (%eax),%ecx
73a: 89 0a mov %ecx,(%edx)
73c: eb e9 jmp 727 <malloc+0xa7>
base.s.ptr = freep = prevp = &base;
73e: c7 05 38 0b 00 00 3c movl $0xb3c,0xb38
745: 0b 00 00
base.s.size = 0;
748: ba 3c 0b 00 00 mov $0xb3c,%edx
base.s.ptr = freep = prevp = &base;
74d: c7 05 3c 0b 00 00 3c movl $0xb3c,0xb3c
754: 0b 00 00
base.s.size = 0;
757: c7 05 40 0b 00 00 00 movl $0x0,0xb40
75e: 00 00 00
761: e9 46 ff ff ff jmp 6ac <malloc+0x2c>
766: 66 90 xchg %ax,%ax
768: 66 90 xchg %ax,%ax
76a: 66 90 xchg %ax,%ax
76c: 66 90 xchg %ax,%ax
76e: 66 90 xchg %ax,%ax
00000770 <thread_create>:
#include "mmu.h"
#include "spinlock.h"
struct lock_t lock;
void thread_create(void *(*start_routine)(void*), void *arg){
770: 55 push %ebp
771: 89 e5 mov %esp,%ebp
773: 53 push %ebx
774: 83 ec 14 sub $0x14,%esp
void *stack = malloc(PGSIZE*2);//allocate a block of memory for stack of thread
777: c7 04 24 00 20 00 00 movl $0x2000,(%esp)
77e: e8 fd fe ff ff call 680 <malloc>
783: 89 c3 mov %eax,%ebx
if((uint)stack % PGSIZE)
785: 25 ff 0f 00 00 and $0xfff,%eax
78a: 74 08 je 794 <thread_create+0x24>
stack = stack + (PGSIZE - (uint)stack % PGSIZE);
78c: 29 c3 sub %eax,%ebx
78e: 81 c3 00 10 00 00 add $0x1000,%ebx
int id;
id = clone(stack, PGSIZE*2);
794: c7 44 24 04 00 20 00 movl $0x2000,0x4(%esp)
79b: 00
79c: 89 1c 24 mov %ebx,(%esp)
79f: e8 a6 fb ff ff call 34a <clone>
// id == 0 means this process is a thread
if(id == 0){
7a4: 85 c0 test %eax,%eax
7a6: 74 06 je 7ae <thread_create+0x3e>
(*start_routine)(arg);
free(stack);
exit();
}
}
7a8: 83 c4 14 add $0x14,%esp
7ab: 5b pop %ebx
7ac: 5d pop %ebp
7ad: c3 ret
(*start_routine)(arg);
7ae: 8b 45 0c mov 0xc(%ebp),%eax
7b1: 89 04 24 mov %eax,(%esp)
7b4: ff 55 08 call *0x8(%ebp)
free(stack);
7b7: 89 1c 24 mov %ebx,(%esp)
7ba: e8 31 fe ff ff call 5f0 <free>
exit();
7bf: e8 ce fa ff ff call 292 <exit>
7c4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
7ca: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
000007d0 <lock_init>:
// initiate a lock
void lock_init(struct lock_t *lk){
7d0: 55 push %ebp
7d1: 89 e5 mov %esp,%ebp
lk->locked = 0;
7d3: 8b 45 08 mov 0x8(%ebp),%eax
7d6: c7 00 00 00 00 00 movl $0x0,(%eax)
}
7dc: 5d pop %ebp
7dd: c3 ret
7de: 66 90 xchg %ax,%ax
000007e0 <lock_acquire>:
void lock_acquire(struct lock_t *lk){
7e0: 55 push %ebp
xchg(volatile uint *addr, uint newval)
{
uint result;
// The + in "+m" denotes a read-modify-write operand.
asm volatile("lock; xchgl %0, %1" :
7e1: b9 01 00 00 00 mov $0x1,%ecx
7e6: 89 e5 mov %esp,%ebp
7e8: 8b 55 08 mov 0x8(%ebp),%edx
7eb: 90 nop
7ec: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
7f0: 89 c8 mov %ecx,%eax
7f2: f0 87 02 lock xchg %eax,(%edx)
while(xchg(&lk->locked, 1) != 0);//atmoic language
7f5: 85 c0 test %eax,%eax
7f7: 75 f7 jne 7f0 <lock_acquire+0x10>
}
7f9: 5d pop %ebp
7fa: c3 ret
7fb: 90 nop
7fc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000800 <lock_release>:
void lock_release(struct lock_t *lk){
800: 55 push %ebp
801: 31 c0 xor %eax,%eax
803: 89 e5 mov %esp,%ebp
805: 8b 55 08 mov 0x8(%ebp),%edx
808: f0 87 02 lock xchg %eax,(%edx)
xchg(&lk->locked, 0);
80b: 5d pop %ebp
80c: c3 ret
|
;
; ZX81 libraries
;
;--------------------------------------------------------------
; This code comes from the 'HRG_Tool'
; by Matthias Swatosch
; Original function name: "HRG_Tool_TXTcopy"
;--------------------------------------------------------------
;
; $Id: copytxt.asm,v 1.2 2015/01/19 01:32:52 pauloscustodio Exp $
;
;----------------------------------------------------------------
;
; HRG_Tool_TXTcopy
; hl = pointer to display array
;
; copies the textscreen (DFILE) into HRG
;
;----------------------------------------------------------------
PUBLIC copytxt
EXTERN base_graphics
copytxt:
ld (ovmode),hl
ld hl,(base_graphics)
ld de,($400C) ; D_FILE
inc de
IF FORzx81hrg64
ld b,8
ELSE
ld b,24
ENDIF
ld c,0
HRG_TXTcopyLoop:
ld a,(de)
or a
jr z,HRG_TXTcopyNextChar
cp 118
jr z,HRG_TXTcopyNextLine
push hl ; HL points to byte in HRG
push de ; A is character
push bc
cp $40 ; inverse?
push af
ld de,$1e00 ; start of characters in ROM
ld b,0
and $3f
ld c,a
or a
rl c ; multiply BC by 8
rl b
rl c
rl b
rl c
rl b
ex de,hl
add hl,bc
ex de,hl ; now DE is pointer to pixel code
ld c,$00 ; C stores invers character information
pop af ; inverse?
jr c,HRG_TXTcopyNormal
dec c ; if inverse character then C is $ff
HRG_TXTcopyNormal:
ld b,8 ; counter
HRG_TXTcopyLoop2:
ld a,(de)
xor c
ovmode: nop
nop
;or (hl) ; plot the character to HRG
ld (hl),a
push bc
ld bc,32
add hl,bc
pop bc
inc de
djnz HRG_TXTcopyLoop2
pop bc
pop de
pop hl
HRG_TXTcopyNextChar:
inc de
inc hl
jr HRG_TXTcopyLoop
HRG_TXTcopyNextLine:
inc c
inc de
ld hl,(base_graphics)
push bc
ld b,c
ld c,0
add hl,bc
pop bc
djnz HRG_TXTcopyLoop
ret
|
// This file is distributed under the BSD 3-Clause License. See LICENSE for details.
// YAML to YAML graph conversion
#include "import_verilog.hpp"
#include <fstream>
#include <iostream>
#include <regex>
//FIXME: consider replacing with a simple lex/yacc parser?
//This only parses
void Import_verilog::update() {
assert(false); //not implemented
fmt::print("update\n");
std::ifstream input_file(opack.file_path);
if(!input_file.good()) {
console->error("Unable to open technology file {}\n", opack.file_path);
}
input_file.close();
}
|
defop eval ; the ToS
pop ebx
pop eax
push ebx
jmp [eax+dict_entry_code]
defop doop ; the entry in eax
push eval_ip
mov eval_ip, [eax+dict_entry_data]
jmp [d_next+dict_entry_code]
defop next
mov eax, [eval_ip]
add eval_ip, ptrsize
call [eax+dict_entry_code]
jmp [d_next+dict_entry_code]
|
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 LeafLabs LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*****************************************************************************/
// Force init to be called *first*, i.e. before static object allocation.
// Otherwise, statically allocated objects that need libmaple may fail.
__attribute__(( constructor )) void premain() {
init();
}
int main(void) {
setup();
while (1) {
loop();
}
return 0;
}
|
Total: 819.30MB
ROUTINE ======================== main.(*Graph).buildAdjList
369.13MB 369.13MB (flat, cum) 45.05% of Total
. . 10ca6a0: MOVQ GS:0x30, CX ;graph.go:102
. . 10ca6a9: LEAQ -0x60(SP), AX
. . 10ca6ae: CMPQ 0x10(CX), AX
. . 10ca6b2: JBE 0x10cab5e
. . 10ca6b8: SUBQ $0xe0, SP
. . 10ca6bf: MOVQ BP, 0xd8(SP)
. . 10ca6c7: LEAQ 0xd8(SP), BP
. . 10ca6cf: XORL AX, AX
. . 10ca6d1: XORL CX, CX
. . 10ca6d3: JMP 0x10ca97f ;graph.go:104
. . 10ca6d8: MOVQ 0x88(SP), R10 ;graph.go:110
. . 10ca6e0: LEAQ 0x1(R10), R9
. . 10ca6e4: MOVQ 0x78(SP), R10
. . 10ca6e9: MOVQ 0x70(SP), R11
. . 10ca6ee: MOVQ 0x98(SP), R12
. . 10ca6f6: MOVQ 0x68(SP), R13
. . 10ca6fb: MOVQ 0xc0(SP), R14
. . 10ca703: MOVQ R10, AX
. . 10ca706: MOVQ 0x50(SP), CX ;graph.go:107
. . 10ca70b: MOVQ R11, DX ;graph.go:111
. . 10ca70e: MOVQ 0xe8(SP), BX
. . 10ca716: MOVQ R12, SI
. . 10ca719: MOVQ R13, DI
. . 10ca71c: MOVQ R14, R8 ;graph.go:110
. . 10ca71f: CMPQ AX, R9
. . 10ca722: JGE 0x10ca976
. . 10ca728: MOVQ 0(R8)(R9*8), R10
. . 10ca72c: MOVQ 0x8(BX), R11 ;graph.go:111
. . 10ca730: MOVQ 0(BX), R12
. . 10ca733: CMPQ R11, R10
. . 10ca736: JAE 0x10cab52
. . 10ca73c: MOVQ R9, 0x88(SP) ;graph.go:110
. . 10ca744: MOVQ R10, 0x58(SP)
. . 10ca749: LEAQ 0(R10)(R10*2), AX ;graph.go:111
. . 10ca74d: MOVQ AX, 0x80(SP)
. . 10ca755: MOVQ 0(R12)(AX*8), CX
. . 10ca759: MOVQ 0x10(R12)(AX*8), BX
. . 10ca75e: MOVQ 0x8(R12)(AX*8), R8
. . 10ca763: MOVQ SI, 0(SP)
. . 10ca767: MOVQ DI, 0x8(SP)
. . 10ca76c: MOVQ DX, 0x10(SP)
. . 10ca771: MOVQ CX, 0x18(SP)
. . 10ca776: MOVQ R8, 0x20(SP)
. . 10ca77b: MOVQ BX, 0x28(SP)
. . 10ca780: CALL main.distance(SB)
. . 10ca785: CMPQ $0x1, 0x30(SP)
. . 10ca78b: JNE 0x10ca95c
. . 10ca791: MOVQ 0xe8(SP), DX ;graph.go:112
. . 10ca799: MOVQ 0x18(DX), BX
. . 10ca79d: MOVQ 0x20(DX), CX
. . 10ca7a1: MOVQ 0x60(SP), AX
. . 10ca7a6: CMPQ CX, AX
. . 10ca7a9: JAE 0x10cab4d
. . 10ca7af: MOVQ 0x90(SP), SI
. . 10ca7b7: MOVQ 0x10(BX)(SI*8), DI
. . 10ca7bc: MOVQ 0x8(BX)(SI*8), R8
. . 10ca7c1: MOVQ 0(BX)(SI*8), R9
. . 10ca7c5: LEAQ 0x1(R8), R10
. . 10ca7c9: LEAQ 0(BX)(SI*8), R11
. . 10ca7cd: CMPQ DI, R10
. . 10ca7d0: JA 0x10ca8c5
. . 10ca7d6: LEAQ 0x1(R8), DI
. . 10ca7da: MOVQ DI, 0x8(BX)(SI*8)
. . 10ca7df: MOVQ 0x58(SP), BX
. . 10ca7e4: MOVQ BX, 0(R9)(R8*8)
. . 10ca7e8: MOVQ 0x20(DX), CX ;graph.go:113
. . 10ca7ec: MOVQ 0x18(DX), DI
. . 10ca7f0: CMPQ CX, BX
. . 10ca7f3: JAE 0x10cab45
. . 10ca7f9: MOVQ 0x80(SP), BX
. . 10ca801: MOVQ 0(DI)(BX*8), R8
. . 10ca805: MOVQ 0x10(DI)(BX*8), R9
. . 10ca80a: MOVQ 0x8(DI)(BX*8), R10
. . 10ca80f: LEAQ 0x1(R10), R11
. . 10ca813: LEAQ 0(DI)(BX*8), R12
. . 10ca817: CMPQ R9, R11
. . 10ca81a: JA 0x10ca82e
. . 10ca81c: LEAQ 0x1(R10), R9
. . 10ca820: MOVQ R9, 0x8(DI)(BX*8)
. . 10ca825: MOVQ AX, 0(R8)(R10*8)
. . 10ca829: JMP 0x10ca6d8
. . 10ca82e: MOVQ R12, 0xb8(SP)
. . 10ca836: MOVQ DI, 0xb0(SP)
. . 10ca83e: LEAQ runtime.types+86176(SB), AX
. . 10ca845: MOVQ AX, 0(SP)
. . 10ca849: MOVQ R8, 0x8(SP)
. . 10ca84e: MOVQ R10, 0x10(SP)
. . 10ca853: MOVQ R9, 0x18(SP)
. . 10ca858: MOVQ R11, 0x20(SP)
63.51MB 63.51MB 10ca85d: CALL runtime.growslice(SB) ;main.(*Graph).buildAdjList graph.go:113
. . 10ca862: MOVQ 0x28(SP), AX ;graph.go:113
. . 10ca867: MOVQ 0x30(SP), CX
. . 10ca86c: MOVQ 0x38(SP), DX
. . 10ca871: MOVQ 0x80(SP), BX
. . 10ca879: MOVQ 0xb0(SP), SI
. . 10ca881: MOVQ DX, 0x10(SI)(BX*8)
. . 10ca886: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca88d: JNE 0x10ca8b6
. . 10ca88f: MOVQ AX, 0(SI)(BX*8)
. . 10ca893: MOVQ 0xe8(SP), DX ;graph.go:111
. . 10ca89b: MOVQ SI, DI ;graph.go:113
. . 10ca89e: MOVQ CX, R10
. . 10ca8a1: MOVQ AX, R8
. . 10ca8a4: MOVQ 0x60(SP), AX
. . 10ca8a9: MOVQ 0x90(SP), SI ;graph.go:112
. . 10ca8b1: JMP 0x10ca81c ;graph.go:113
. . 10ca8b6: MOVQ 0xb8(SP), DI
. . 10ca8be: CALL runtime.gcWriteBarrier(SB)
. . 10ca8c3: JMP 0x10ca893
. . 10ca8c5: MOVQ BX, 0xa8(SP) ;graph.go:112
. . 10ca8cd: MOVQ R11, 0xa0(SP)
. . 10ca8d5: LEAQ runtime.types+86176(SB), AX
. . 10ca8dc: MOVQ AX, 0(SP)
. . 10ca8e0: MOVQ R9, 0x8(SP)
. . 10ca8e5: MOVQ R8, 0x10(SP)
. . 10ca8ea: MOVQ DI, 0x18(SP)
. . 10ca8ef: MOVQ R10, 0x20(SP)
80.52MB 80.52MB 10ca8f4: CALL runtime.growslice(SB) ;main.(*Graph).buildAdjList graph.go:112
. . 10ca8f9: MOVQ 0x28(SP), AX ;graph.go:112
. . 10ca8fe: MOVQ 0x30(SP), CX
. . 10ca903: MOVQ 0x38(SP), DX
. . 10ca908: MOVQ 0x90(SP), BX
. . 10ca910: MOVQ 0xa8(SP), SI
. . 10ca918: MOVQ DX, 0x10(SI)(BX*8)
. . 10ca91d: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca924: JNE 0x10ca94d
. . 10ca926: MOVQ AX, 0(SI)(BX*8)
. . 10ca92a: MOVQ 0xe8(SP), DX ;graph.go:113
. . 10ca932: MOVQ SI, BX ;graph.go:112
. . 10ca935: MOVQ 0x90(SP), SI
. . 10ca93d: MOVQ CX, R8
. . 10ca940: MOVQ AX, R9
. . 10ca943: MOVQ 0x60(SP), AX ;graph.go:113
. . 10ca948: JMP 0x10ca7d6 ;graph.go:112
. . 10ca94d: MOVQ 0xa0(SP), DI
. . 10ca955: CALL runtime.gcWriteBarrier(SB)
. . 10ca95a: JMP 0x10ca92a
. . 10ca95c: MOVQ 0x60(SP), AX ;graph.go:104
. . 10ca961: MOVQ 0xe8(SP), DX ;graph.go:111
. . 10ca969: MOVQ 0x90(SP), SI ;graph.go:112
. . 10ca971: JMP 0x10ca6d8 ;graph.go:110
. . 10ca976: MOVQ 0x60(SP), DX ;graph.go:104
. . 10ca97b: LEAQ 0x1(DX), AX
. . 10ca97f: MOVQ 0xe8(SP), DX
. . 10ca987: MOVQ 0x8(DX), BX
. . 10ca98b: MOVQ 0(DX), SI
. . 10ca98e: CMPQ BX, AX
. . 10ca991: JGE 0x10caaa0
. . 10ca997: MOVQ AX, 0x60(SP)
. . 10ca99c: MOVQ CX, 0x50(SP) ;graph.go:107
. . 10ca9a1: LEAQ 0(AX)(AX*2), CX ;graph.go:105
. . 10ca9a5: MOVQ CX, 0x90(SP)
. . 10ca9ad: MOVQ 0x10(SI)(CX*8), DX
. . 10ca9b2: MOVQ DX, 0x70(SP)
. . 10ca9b7: MOVQ 0x8(SI)(CX*8), BX
. . 10ca9bc: MOVQ BX, 0x68(SP)
. . 10ca9c1: MOVQ 0(SI)(CX*8), SI
. . 10ca9c5: MOVQ SI, 0x98(SP)
. . 10ca9cd: MOVQ 0xf0(SP), DI ;graph.go:106
. . 10ca9d5: MOVQ DI, 0(SP)
. . 10ca9d9: MOVQ SI, 0x8(SP)
. . 10ca9de: MOVQ BX, 0x10(SP)
. . 10ca9e3: MOVQ DX, 0x18(SP)
. . 10ca9e8: CALL main.(*index).nearCount(SB)
. . 10ca9ed: MOVQ 0x20(SP), AX
. . 10ca9f2: MOVQ AX, 0x78(SP)
. . 10ca9f7: LEAQ runtime.types+86176(SB), CX ;graph.go:108
. . 10ca9fe: MOVQ CX, 0(SP)
. . 10caa02: MOVQ AX, 0x8(SP)
. . 10caa07: MOVQ AX, 0x10(SP)
225.10MB 225.10MB 10caa0c: CALL runtime.makeslice(SB) ;main.(*Graph).buildAdjList graph.go:108
. . 10caa11: MOVQ 0x18(SP), AX ;graph.go:108
. . 10caa16: MOVQ AX, 0xc0(SP)
. . 10caa1e: MOVQ 0xf0(SP), CX ;graph.go:109
. . 10caa26: MOVQ CX, 0(SP)
. . 10caa2a: MOVQ 0x98(SP), DX
. . 10caa32: MOVQ DX, 0x8(SP)
. . 10caa37: MOVQ 0x68(SP), BX
. . 10caa3c: MOVQ BX, 0x10(SP)
. . 10caa41: MOVQ 0x70(SP), SI
. . 10caa46: MOVQ SI, 0x18(SP)
. . 10caa4b: MOVQ AX, 0x20(SP)
. . 10caa50: MOVQ 0x78(SP), DI
. . 10caa55: MOVQ DI, 0x28(SP)
. . 10caa5a: MOVQ DI, 0x30(SP)
. . 10caa5f: CALL main.(*index).near(SB)
. . 10caa64: MOVQ 0x78(SP), AX ;graph.go:107
. . 10caa69: MOVQ 0x50(SP), CX
. . 10caa6e: ADDQ AX, CX
. . 10caa71: MOVQ CX, 0x50(SP)
. . 10caa76: MOVQ 0x70(SP), DX ;graph.go:110
. . 10caa7b: MOVQ 0xe8(SP), BX
. . 10caa83: MOVQ 0x98(SP), SI
. . 10caa8b: MOVQ 0x68(SP), DI
. . 10caa90: MOVQ 0xc0(SP), R8
. . 10caa98: XORL R9, R9
. . 10caa9b: JMP 0x10ca71f
. . 10caaa0: XORPS X0, X0 ;graph.go:117
. . 10caaa3: CVTSI2SDQ CX, X0
. . 10caaa8: XORPS X1, X1
. . 10caaab: CVTSI2SDQ BX, X1
. . 10caab0: DIVSD X1, X0
. . 10caab4: MOVSD_XMM X0, 0(SP)
. . 10caab9: CALL runtime.convT64(SB)
. . 10caabe: MOVQ 0x8(SP), AX
. . 10caac3: XORPS X0, X0
. . 10caac6: MOVUPS X0, 0xc8(SP)
. . 10caace: LEAQ runtime.types+84448(SB), CX
. . 10caad5: MOVQ CX, 0xc8(SP)
. . 10caadd: MOVQ AX, 0xd0(SP)
. . 10caae5: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10caaec: LEAQ go.itab.*os.File,io.Writer(SB), CX
. . 10caaf3: MOVQ CX, 0(SP)
. . 10caaf7: MOVQ AX, 0x8(SP)
. . 10caafc: LEAQ go.string.*+3298(SB), AX
. . 10cab03: MOVQ AX, 0x10(SP)
. . 10cab08: MOVQ $0xa, 0x18(SP)
. . 10cab11: LEAQ 0xc8(SP), AX
. . 10cab19: MOVQ AX, 0x20(SP)
. . 10cab1e: MOVQ $0x1, 0x28(SP)
. . 10cab27: MOVQ $0x1, 0x30(SP)
. . 10cab30: CALL fmt.Fprintf(SB)
. . 10cab35: MOVQ 0xd8(SP), BP
. . 10cab3d: ADDQ $0xe0, SP
. . 10cab44: RET
. . 10cab45: MOVQ BX, AX ;graph.go:113
. . 10cab48: CALL runtime.panicIndex(SB)
. . 10cab4d: CALL runtime.panicIndex(SB) ;graph.go:112
. . 10cab52: MOVQ R10, AX ;graph.go:111
. . 10cab55: MOVQ R11, CX
. . 10cab58: CALL runtime.panicIndex(SB)
. . 10cab5d: NOPL
. . 10cab5e: CALL runtime.morestack_noctxt(SB) ;graph.go:102
. . 10cab63: JMP main.(*Graph).buildAdjList(SB)
. . 10cab68: INT $0x3
. . 10cab69: INT $0x3
. . 10cab6a: INT $0x3
. . 10cab6b: INT $0x3
. . 10cab6c: INT $0x3
. . 10cab6d: INT $0x3
. . 10cab6e: INT $0x3
ROUTINE ======================== main.(*index).add
102.50MB 102.50MB (flat, cum) 12.51% of Total
. . 10cc260: MOVQ GS:0x30, CX ;index.go:30
. . 10cc269: LEAQ -0x18(SP), AX
. . 10cc26e: CMPQ 0x10(CX), AX
. . 10cc272: JBE 0x10cc566
. . 10cc278: SUBQ $0x98, SP
. . 10cc27f: MOVQ BP, 0x90(SP)
. . 10cc287: LEAQ 0x90(SP), BP
. . 10cc28f: MOVQ 0xa0(SP), BX ;index.go:33
. . 10cc297: MOVQ 0x38(BX), DX
. . 10cc29b: MOVQ 0x28(BX), SI
. . 10cc29f: MOVQ 0xb8(SP), DI
. . 10cc2a7: LEAQ -0x1(DI), CX
. . 10cc2ab: CMPQ DX, CX
. . 10cc2ae: JA 0x10cc560
. . 10cc2b4: MOVQ CX, 0x58(SP)
. . 10cc2b9: MOVQ DX, 0x50(SP)
. . 10cc2be: MOVQ SI, 0x78(SP)
. . 10cc2c3: MOVQ 0xb0(SP), R8 ;index.go:34
. . 10cc2cb: XORL AX, AX
. . 10cc2cd: JMP 0x10cc322
. . 10cc2cf: LEAQ 0x1(R8), R10 ;index.go:40
. . 10cc2d3: MOVQ R10, 0x8(BX)(SI*8)
. . 10cc2d8: MOVQ 0xa8(SP), R10
. . 10cc2e0: MOVQ R10, 0(R9)(R8*8)
. . 10cc2e4: MOVQ 0x78(SP), R9 ;index.go:34
. . 10cc2e9: MOVQ 0x50(SP), R11
. . 10cc2ee: MOVQ 0x58(SP), R12
. . 10cc2f3: MOVQ 0xb8(SP), R13
. . 10cc2fb: MOVQ 0xb0(SP), R14
. . 10cc303: MOVQ 0x68(SP), R15
. . 10cc308: MOVQ R12, CX ;index.go:124
. . 10cc30b: MOVQ R11, DX ;index.go:123
. . 10cc30e: MOVQ 0xa0(SP), BX ;index.go:37
. . 10cc316: MOVQ R9, SI ;index.go:124
. . 10cc319: MOVQ R13, DI ;index.go:34
. . 10cc31c: MOVQ R14, R8 ;index.go:125
. . 10cc31f: MOVQ R15, AX ;index.go:34
. . 10cc322: CMPQ DI, AX
. . 10cc325: JGE 0x10cc533
. . 10cc32b: NOPL ;index.go:35
. . 10cc32c: CMPQ DX, AX ;index.go:123
. . 10cc32f: JA 0x10cc558
. . 10cc335: CMPQ CX, AX ;index.go:124
. . 10cc338: JA 0x10cc553
. . 10cc33e: MOVQ AX, 0x48(SP) ;index.go:34
. . 10cc343: SUBQ AX, CX ;index.go:124
. . 10cc346: MOVQ CX, 0x40(SP)
. . 10cc34b: SUBQ AX, DX
. . 10cc34e: NEGQ DX
. . 10cc351: SARQ $0x3f, DX
. . 10cc355: ANDQ AX, DX
. . 10cc358: ADDQ SI, DX
. . 10cc35b: MOVQ DX, 0x70(SP)
. . 10cc360: CMPQ R8, SI ;index.go:125
. . 10cc363: JE 0x10cc378
. . 10cc365: MOVQ SI, 0(SP)
. . 10cc369: MOVQ R8, 0x8(SP)
. . 10cc36e: MOVQ AX, 0x10(SP)
. . 10cc373: CALL runtime.memmove(SB)
. . 10cc378: MOVQ 0x48(SP), AX ;index.go:126
. . 10cc37d: INCQ AX
. . 10cc380: MOVQ AX, 0x68(SP)
. . 10cc385: MOVQ 0xb8(SP), CX
. . 10cc38d: SUBQ AX, CX
. . 10cc390: MOVQ 0x40(SP), BX
. . 10cc395: CMPQ CX, BX
. . 10cc398: CMOVG CX, BX
. . 10cc39c: MOVQ 0xc0(SP), CX
. . 10cc3a4: SUBQ AX, CX
. . 10cc3a7: NEGQ CX
. . 10cc3aa: SARQ $0x3f, CX
. . 10cc3ae: ANDQ AX, CX
. . 10cc3b1: MOVQ 0xb0(SP), DI
. . 10cc3b9: ADDQ DI, CX
. . 10cc3bc: MOVQ 0x70(SP), R8
. . 10cc3c1: CMPQ R8, CX
. . 10cc3c4: JNE 0x10cc51b
. . 10cc3ca: MOVQ 0xa0(SP), AX ;index.go:37
. . 10cc3d2: MOVQ 0(AX), CX
. . 10cc3d5: MOVQ 0x8(AX), DX
. . 10cc3d9: MOVQ 0x20(CX), CX
. . 10cc3dd: MOVQ DX, 0(SP)
. . 10cc3e1: CALL CX
. . 10cc3e3: MOVQ 0xa0(SP), AX ;index.go:38
. . 10cc3eb: MOVQ 0(AX), CX
. . 10cc3ee: MOVQ 0x8(AX), DX
. . 10cc3f2: MOVQ 0x40(CX), CX
. . 10cc3f6: MOVQ DX, 0(SP)
. . 10cc3fa: MOVQ 0x78(SP), DX
. . 10cc3ff: MOVQ DX, 0x8(SP)
. . 10cc404: MOVQ 0x58(SP), BX
. . 10cc409: MOVQ BX, 0x10(SP)
. . 10cc40e: MOVQ 0x50(SP), SI
. . 10cc413: MOVQ SI, 0x18(SP)
. . 10cc418: CALL CX
. . 10cc41a: MOVQ 0xa0(SP), AX ;index.go:39
. . 10cc422: MOVQ 0(AX), CX
. . 10cc425: MOVQ 0x8(AX), DX
. . 10cc429: MOVQ 0x38(CX), CX
. . 10cc42d: MOVQ DX, 0(SP)
. . 10cc431: CALL CX
. . 10cc433: MOVQ 0x8(SP), AX
. . 10cc438: MOVQ 0xa0(SP), CX
. . 10cc440: MOVQ 0x40(CX), DX
. . 10cc444: TESTQ DX, DX
. . 10cc447: JE 0x10cc54e
. . 10cc44d: MOVQ DX, BX
. . 10cc450: XORL DX, DX
. . 10cc452: DIVQ BX
. . 10cc455: MOVQ 0x10(CX), BX ;index.go:40
. . 10cc459: MOVQ 0x18(CX), SI
. . 10cc45d: CMPQ SI, DX
. . 10cc460: JAE 0x10cc543
. . 10cc466: LEAQ 0(DX)(DX*2), SI
. . 10cc46a: MOVQ 0x10(BX)(SI*8), DI
. . 10cc46f: MOVQ 0x8(BX)(SI*8), R8
. . 10cc474: MOVQ 0(BX)(SI*8), R9
. . 10cc478: LEAQ 0x1(R8), R10
. . 10cc47c: LEAQ 0(BX)(SI*8), R11
. . 10cc480: CMPQ DI, R10
. . 10cc483: JBE 0x10cc2cf
. . 10cc489: MOVQ BX, 0x88(SP)
. . 10cc491: MOVQ SI, 0x60(SP)
. . 10cc496: MOVQ R11, 0x80(SP)
. . 10cc49e: LEAQ runtime.types+86176(SB), AX
. . 10cc4a5: MOVQ AX, 0(SP)
. . 10cc4a9: MOVQ R9, 0x8(SP)
. . 10cc4ae: MOVQ R8, 0x10(SP)
. . 10cc4b3: MOVQ DI, 0x18(SP)
. . 10cc4b8: MOVQ R10, 0x20(SP)
102.50MB 102.50MB 10cc4bd: CALL runtime.growslice(SB) ;main.(*index).add index.go:40
. . 10cc4c2: MOVQ 0x28(SP), AX ;index.go:40
. . 10cc4c7: MOVQ 0x30(SP), CX
. . 10cc4cc: MOVQ 0x38(SP), DX
. . 10cc4d1: MOVQ 0x60(SP), BX
. . 10cc4d6: MOVQ 0x88(SP), SI
. . 10cc4de: MOVQ DX, 0x10(SI)(BX*8)
. . 10cc4e3: CMPL $0x0, runtime.writeBarrier(SB)
. . 10cc4ea: JNE 0x10cc50c
. . 10cc4ec: MOVQ AX, 0(SI)(BX*8)
. . 10cc4f0: MOVQ CX, R8
. . 10cc4f3: MOVQ AX, R9
. . 10cc4f6: MOVQ 0xa0(SP), CX ;index.go:37
. . 10cc4fe: MOVQ BX, DX ;index.go:40
. . 10cc501: MOVQ SI, BX
. . 10cc504: MOVQ DX, SI
. . 10cc507: JMP 0x10cc2cf
. . 10cc50c: MOVQ 0x80(SP), DI
. . 10cc514: CALL runtime.gcWriteBarrier(SB)
. . 10cc519: JMP 0x10cc4f0
. . 10cc51b: MOVQ R8, 0(SP) ;index.go:126
. . 10cc51f: MOVQ CX, 0x8(SP)
. . 10cc524: MOVQ BX, 0x10(SP)
. . 10cc529: CALL runtime.memmove(SB)
. . 10cc52e: JMP 0x10cc3ca
. . 10cc533: MOVQ 0x90(SP), BP
. . 10cc53b: ADDQ $0x98, SP
. . 10cc542: RET
. . 10cc543: MOVQ DX, AX ;index.go:40
. . 10cc546: MOVQ SI, CX
. . 10cc549: CALL runtime.panicIndexU(SB)
. . 10cc54e: CALL runtime.panicdivide(SB) ;index.go:39
. . 10cc553: CALL runtime.panicSliceB(SB) ;index.go:124
. . 10cc558: MOVQ AX, CX ;index.go:123
. . 10cc55b: CALL runtime.panicSliceAcap(SB)
. . 10cc560: CALL runtime.panicSliceAcap(SB) ;index.go:33
. . 10cc565: NOPL
. . 10cc566: CALL runtime.morestack_noctxt(SB) ;index.go:30
. . 10cc56b: ?
. . 10cc56c: LOCK CLD
. . 10cc56e: ?
ROUTINE ======================== main.LoadDictionary
153.94MB 817.58MB (flat, cum) 99.79% of Total
. . 10c9e10: MOVQ GS:0x30, CX ;graph.go:39
. . 10c9e19: LEAQ 0xfffffec0(SP), AX
. . 10c9e21: CMPQ 0x10(CX), AX
. . 10c9e25: JBE 0x10ca691
. . 10c9e2b: SUBQ $0x1c0, SP
. . 10c9e32: MOVQ BP, 0x1b8(SP)
. . 10c9e3a: LEAQ 0x1b8(SP), BP
. . 10c9e42: MOVQ $0x0, 0x1f8(SP)
. . 10c9e4e: NOPL ;graph.go:40
. . 10c9e4f: MOVQ 0x1d8(SP), AX ;stats.go:42
. . 10c9e57: MOVQ AX, 0(SP)
. . 10c9e5b: CALL runtime.convT64(SB)
. . 10c9e60: MOVQ main.stats+8(SB), AX
. . 10c9e67: MOVQ main.stats(SB), CX
. . 10c9e6e: LEAQ 0x1(AX), DX
. . 10c9e72: MOVQ main.stats+16(SB), BX
. . 10c9e79: MOVQ 0x8(SP), SI
. . 10c9e7e: CMPQ BX, DX
. . 10c9e81: JA 0x10ca612
. . 10c9e87: LEAQ 0x1(AX), DX
. . 10c9e8b: MOVQ DX, main.stats+8(SB)
. . 10c9e92: SHLQ $0x5, AX
. . 10c9e96: MOVQ $0xb, 0x8(CX)(AX*1)
. . 10c9e9f: LEAQ go.itab.main.intStat,main.statValue(SB), DX
. . 10c9ea6: MOVQ DX, 0x10(CX)(AX*1)
. . 10c9eab: LEAQ 0(CX)(AX*1), DI
. . 10c9eaf: LEAQ 0(CX)(AX*1), DX
. . 10c9eb3: LEAQ 0x18(DX), DX
. . 10c9eb7: CMPL $0x0, runtime.writeBarrier(SB)
. . 10c9ebe: JNE 0x10ca5f6
. . 10c9ec4: LEAQ go.string.*+3958(SB), DX
. . 10c9ecb: MOVQ DX, 0(CX)(AX*1)
. . 10c9ecf: MOVQ SI, 0x18(CX)(AX*1)
. . 10c9ed4: LEAQ go.string.*+6121(SB), AX ;graph.go:41
. . 10c9edb: MOVQ AX, 0(SP)
. . 10c9edf: MOVQ $0xe, 0x8(SP)
. . 10c9ee8: CALL main.newTimer(SB)
. . 10c9eed: MOVQ 0x10(SP), AX
. . 10c9ef2: MOVL $0x0, 0x68(SP)
. . 10c9efa: MOVQ AX, 0x80(SP)
. . 10c9f02: LEAQ 0x68(SP), AX
. . 10c9f07: MOVQ AX, 0(SP)
. . 10c9f0b: CALL runtime.deferprocStack(SB)
. . 10c9f10: TESTL AX, AX
. . 10c9f12: JNE 0x10ca5e0
. . 10c9f18: NOPL ;graph.go:42
. . 10c9f19: MOVQ 0x1c8(SP), AX ;file.go:280
. . 10c9f21: MOVQ AX, 0(SP)
. . 10c9f25: MOVQ 0x1d0(SP), AX
. . 10c9f2d: MOVQ AX, 0x8(SP)
. . 10c9f32: MOVQ $0x0, 0x10(SP)
. . 10c9f3b: MOVL $0x0, 0x18(SP)
. . 10c9f43: CALL os.OpenFile(SB)
. . 10c9f48: MOVQ 0x20(SP), AX
. . 10c9f4d: MOVQ AX, 0x118(SP)
. . 10c9f55: MOVQ 0x30(SP), CX
. . 10c9f5a: MOVQ 0x28(SP), DX
. . 10c9f5f: TESTQ DX, DX ;graph.go:43
. . 10c9f62: JE 0x10c9fa8
. . 10c9f64: JE 0x10c9f6a ;graph.go:44
. . 10c9f66: MOVQ 0x8(DX), DX
. . 10c9f6a: XORPS X0, X0
. . 10c9f6d: MOVUPS X0, 0x128(SP)
. . 10c9f75: MOVQ DX, 0x128(SP)
. . 10c9f7d: MOVQ CX, 0x130(SP)
. . 10c9f85: LEAQ 0x128(SP), AX
. . 10c9f8d: MOVQ AX, 0(SP)
. . 10c9f91: MOVQ $0x1, 0x8(SP)
. . 10c9f9a: MOVQ $0x1, 0x10(SP)
. . 10c9fa3: CALL log.Fatal(SB)
. . 10c9fa8: MOVL $0x18, 0xa0(SP) ;graph.go:46
. . 10c9fb3: LEAQ go.func.*+300(SB), AX
. . 10c9fba: MOVQ AX, 0xb8(SP)
. . 10c9fc2: MOVQ 0x118(SP), AX
. . 10c9fca: MOVQ AX, 0xd0(SP)
. . 10c9fd2: LEAQ 0xa0(SP), CX
. . 10c9fda: MOVQ CX, 0(SP)
. . 10c9fde: CALL runtime.deferprocStack(SB)
. . 10c9fe3: TESTL AX, AX
. . 10c9fe5: JNE 0x10ca5ca
. . 10c9feb: LEAQ runtime.types+158240(SB), AX ;graph.go:48
. . 10c9ff2: MOVQ AX, 0(SP)
. . 10c9ff6: CALL runtime.newobject(SB)
. . 10c9ffb: MOVQ 0x8(SP), AX
. . 10ca000: MOVQ AX, 0x120(SP)
. . 10ca008: LEAQ runtime.types+142368(SB), CX ;graph.go:49
. . 10ca00f: MOVQ CX, 0(SP)
. . 10ca013: XORPS X0, X0
. . 10ca016: MOVUPS X0, 0x8(SP)
. . 10ca01b: CALL runtime.makeslice(SB)
. . 10ca020: MOVQ 0x18(SP), AX
. . 10ca025: CMPL $0x0, runtime.writeBarrier(SB) ;graph.go:48
. . 10ca02c: JNE 0x10ca585
. . 10ca032: XORPS X0, X0
. . 10ca035: MOVQ 0x120(SP), CX
. . 10ca03d: MOVUPS X0, 0(CX)
. . 10ca040: MOVUPS X0, 0x10(CX)
. . 10ca044: MOVUPS X0, 0x20(CX)
. . 10ca048: MOVQ AX, 0(CX)
. . 10ca04b: NOPL ;graph.go:54
. . 10ca04c: LEAQ 0x138(SP), DI ;scan.go:87
. . 10ca054: MOVQ BP, -0x10(SP)
. . 10ca059: LEAQ -0x10(SP), BP
. . 10ca05e: CALL 0x10586ba
. . 10ca063: MOVQ 0(BP), BP
. . 10ca067: LEAQ 0x138(SP), DI
. . 10ca06f: MOVQ BP, -0x10(SP)
. . 10ca074: LEAQ -0x10(SP), BP
. . 10ca079: CALL 0x10586ba
. . 10ca07e: MOVQ 0(BP), BP
. . 10ca082: LEAQ go.itab.*os.File,io.Reader(SB), AX
. . 10ca089: MOVQ AX, 0x138(SP)
. . 10ca091: MOVQ 0x118(SP), AX
. . 10ca099: MOVQ AX, 0x140(SP)
. . 10ca0a1: LEAQ go.func.*+4(SB), AX
. . 10ca0a8: MOVQ AX, 0x148(SP)
. . 10ca0b0: MOVQ $0x10000, 0x150(SP)
. . 10ca0bc: XORL AX, AX
. . 10ca0be: JMP 0x10ca0c3 ;graph.go:55
. . 10ca0c0: MOVQ SI, AX ;graph.go:75
. . 10ca0c3: MOVQ AX, 0x48(SP)
. . 10ca0c8: LEAQ 0x138(SP), CX ;graph.go:55
. . 10ca0d0: MOVQ CX, 0(SP)
. . 10ca0d4: CALL bufio.(*Scanner).Scan(SB)
. . 10ca0d9: CMPB $0x0, 0x8(SP)
. . 10ca0de: JE 0x10ca221
. . 10ca0e4: NOPL ;graph.go:56
. . 10ca0e5: MOVQ 0x160(SP), AX ;scan.go:106
. . 10ca0ed: MOVQ AX, 0x40(SP)
. . 10ca0f2: MOVQ 0x158(SP), CX
. . 10ca0fa: MOVQ CX, 0x100(SP)
. . 10ca102: LEAQ runtime.types+89184(SB), DX ;graph.go:57
. . 10ca109: MOVQ DX, 0(SP)
. . 10ca10d: MOVQ AX, 0x8(SP)
. . 10ca112: MOVQ AX, 0x10(SP)
6MB 6MB 10ca117: CALL runtime.makeslice(SB) ;main.LoadDictionary graph.go:57
. . 10ca11c: MOVQ 0x18(SP), AX ;graph.go:57
. . 10ca121: MOVQ AX, 0x110(SP)
. . 10ca129: MOVQ 0x100(SP), CX ;graph.go:58
. . 10ca131: CMPQ CX, AX
. . 10ca134: JE 0x10ca14e
. . 10ca136: MOVQ AX, 0(SP)
. . 10ca13a: MOVQ CX, 0x8(SP)
. . 10ca13f: MOVQ 0x40(SP), CX
. . 10ca144: MOVQ CX, 0x10(SP)
. . 10ca149: CALL runtime.memmove(SB)
. . 10ca14e: MOVQ 0x120(SP), CX ;graph.go:59
. . 10ca156: MOVQ 0x10(CX), DX
. . 10ca15a: MOVQ 0x8(CX), BX
. . 10ca15e: LEAQ 0x1(BX), SI
. . 10ca162: MOVQ 0(CX), R8
. . 10ca165: CMPQ DX, SI
. . 10ca168: JA 0x10ca1c1
. . 10ca16a: LEAQ 0x1(BX), DX
. . 10ca16e: MOVQ DX, 0x8(CX)
. . 10ca172: LEAQ 0(BX)(BX*2), DX
. . 10ca176: MOVQ 0x40(SP), BX
. . 10ca17b: MOVQ BX, 0x8(R8)(DX*8)
. . 10ca180: MOVQ BX, 0x10(R8)(DX*8)
. . 10ca185: MOVQ 0x48(SP), SI ;graph.go:60
. . 10ca18a: CMPQ SI, BX
. . 10ca18d: CMOVG BX, SI ;graph.go:75
. . 10ca191: LEAQ 0(R8)(DX*8), DI ;graph.go:59
. . 10ca195: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca19c: JNE 0x10ca1af
. . 10ca19e: MOVQ 0x110(SP), AX
. . 10ca1a6: MOVQ AX, 0(R8)(DX*8)
. . 10ca1aa: JMP 0x10ca0c0
. . 10ca1af: MOVQ 0x110(SP), AX
. . 10ca1b7: CALL runtime.gcWriteBarrier(SB)
. . 10ca1bc: JMP 0x10ca0c0
. . 10ca1c1: LEAQ runtime.types+142368(SB), AX
. . 10ca1c8: MOVQ AX, 0(SP)
. . 10ca1cc: MOVQ R8, 0x8(SP)
. . 10ca1d1: MOVQ BX, 0x10(SP)
. . 10ca1d6: MOVQ DX, 0x18(SP)
. . 10ca1db: MOVQ SI, 0x20(SP)
125.05MB 125.05MB 10ca1e0: CALL runtime.growslice(SB) ;main.LoadDictionary graph.go:59
. . 10ca1e5: MOVQ 0x28(SP), AX ;graph.go:59
. . 10ca1ea: MOVQ 0x30(SP), CX
. . 10ca1ef: MOVQ 0x38(SP), DX
. . 10ca1f4: MOVQ 0x120(SP), DI
. . 10ca1fc: MOVQ DX, 0x10(DI)
. . 10ca200: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca207: JNE 0x10ca21a
. . 10ca209: MOVQ AX, 0(DI)
. . 10ca20c: MOVQ CX, BX
. . 10ca20f: MOVQ AX, R8
. . 10ca212: MOVQ DI, CX
. . 10ca215: JMP 0x10ca16a
. . 10ca21a: CALL runtime.gcWriteBarrier(SB)
. . 10ca21f: JMP 0x10ca20c
. . 10ca221: MOVQ 0x1f0(SP), AX ;graph.go:65
. . 10ca229: TESTQ AX, AX
. . 10ca22c: JNE 0x10ca527
. . 10ca232: MOVQ 0x120(SP), AX ;graph.go:69
. . 10ca23a: MOVQ 0x8(AX), CX
. . 10ca23e: MOVQ CX, 0x60(SP)
. . 10ca243: LEAQ runtime.types+77472(SB), DX
. . 10ca24a: MOVQ DX, 0(SP)
. . 10ca24e: MOVQ CX, 0x8(SP)
. . 10ca253: MOVQ CX, 0x10(SP)
22.89MB 22.89MB 10ca258: CALL runtime.makeslice(SB) ;main.LoadDictionary graph.go:69
. . 10ca25d: MOVQ 0x18(SP), AX ;graph.go:69
. . 10ca262: MOVQ 0x60(SP), CX
. . 10ca267: MOVQ 0x120(SP), DX
. . 10ca26f: MOVQ CX, 0x20(DX)
. . 10ca273: MOVQ CX, 0x28(DX)
. . 10ca277: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca27e: JNE 0x10ca519
. . 10ca284: MOVQ AX, 0x18(DX)
. . 10ca288: XORL AX, AX
. . 10ca28a: JMP 0x10ca29b ;graph.go:70
. . 10ca28c: LEAQ 0x1(SI), BX
. . 10ca290: MOVQ 0x60(SP), CX
. . 10ca295: MOVQ AX, DX ;graph.go:71
. . 10ca298: MOVQ BX, AX ;graph.go:70
. . 10ca29b: CMPQ CX, AX
. . 10ca29e: JGE 0x10ca31c
. . 10ca2a0: MOVQ AX, 0x58(SP)
. . 10ca2a5: LEAQ runtime.types+86176(SB), AX ;graph.go:71
. . 10ca2ac: MOVQ AX, 0(SP)
. . 10ca2b0: XORPS X0, X0
. . 10ca2b3: MOVUPS X0, 0x8(SP)
. . 10ca2b8: CALL runtime.makeslice(SB)
. . 10ca2bd: MOVQ 0x120(SP), AX
. . 10ca2c5: MOVQ 0x20(AX), CX
. . 10ca2c9: MOVQ 0x18(AX), DX
. . 10ca2cd: MOVQ 0x18(SP), BX
. . 10ca2d2: MOVQ 0x58(SP), SI
. . 10ca2d7: CMPQ CX, SI
. . 10ca2da: JAE 0x10ca688
. . 10ca2e0: LEAQ 0(SI)(SI*2), CX
. . 10ca2e4: MOVQ $0x0, 0x8(DX)(CX*8)
. . 10ca2ed: MOVQ $0x0, 0x10(DX)(CX*8)
. . 10ca2f6: LEAQ 0(DX)(CX*8), DI
. . 10ca2fa: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca301: JNE 0x10ca309
. . 10ca303: MOVQ BX, 0(DX)(CX*8)
. . 10ca307: JMP 0x10ca28c
. . 10ca309: MOVQ AX, CX ;graph.go:48
. . 10ca30c: MOVQ BX, AX ;graph.go:71
. . 10ca30f: CALL runtime.gcWriteBarrier(SB)
. . 10ca314: MOVQ CX, AX
. . 10ca317: JMP 0x10ca28c
. . 10ca31c: LEAQ go.string.*+3468(SB), AX ;graph.go:74
. . 10ca323: MOVQ AX, 0(SP)
. . 10ca327: MOVQ $0xa, 0x8(SP)
. . 10ca330: CALL main.newTimer(SB)
. . 10ca335: MOVQ 0x10(SP), AX
. . 10ca33a: MOVQ AX, 0xe8(SP)
. . 10ca342: MOVQ 0x1d8(SP), CX ;graph.go:75
. . 10ca34a: MOVQ CX, 0(SP)
. . 10ca34e: MOVQ 0x48(SP), CX
. . 10ca353: MOVQ CX, 0x8(SP)
. 192MB 10ca358: CALL main.newIndex(SB) ;main.LoadDictionary graph.go:75
. . 10ca35d: MOVQ 0x10(SP), AX ;graph.go:75
. . 10ca362: MOVQ AX, 0xf8(SP)
. . 10ca36a: MOVQ 0x120(SP), CX ;graph.go:76
. . 10ca372: MOVQ 0x8(CX), DX
. . 10ca376: MOVQ 0(CX), BX
. . 10ca379: TESTQ DX, DX
. . 10ca37c: JLE 0x10ca3e5
. . 10ca37e: MOVQ DX, 0x60(SP)
. . 10ca383: XORL SI, SI
. . 10ca385: JMP 0x10ca39e
. . 10ca387: MOVQ 0x108(SP), DX
. . 10ca38f: LEAQ 0x18(DX), BX
. . 10ca393: MOVQ AX, SI
. . 10ca396: MOVQ 0xf8(SP), AX ;graph.go:77
. . 10ca39e: MOVQ BX, 0x108(SP) ;graph.go:76
. . 10ca3a6: MOVQ SI, 0x50(SP)
. . 10ca3ab: MOVQ 0x8(BX), CX
. . 10ca3af: MOVQ 0(BX), DX
. . 10ca3b2: MOVQ 0x10(BX), DI
. . 10ca3b6: MOVQ AX, 0(SP) ;graph.go:77
. . 10ca3ba: MOVQ SI, 0x8(SP)
. . 10ca3bf: MOVQ DX, 0x10(SP)
. . 10ca3c4: MOVQ CX, 0x18(SP)
. . 10ca3c9: MOVQ DI, 0x20(SP)
. 102.50MB 10ca3ce: CALL main.(*index).add(SB) ;main.LoadDictionary graph.go:77
. . 10ca3d3: MOVQ 0x50(SP), AX ;graph.go:76
. . 10ca3d8: INCQ AX
. . 10ca3db: MOVQ 0x60(SP), CX
. . 10ca3e0: CMPQ CX, AX
. . 10ca3e3: JL 0x10ca387
. . 10ca3e5: MOVQ 0xe8(SP), DX ;graph.go:79
. . 10ca3ed: MOVQ 0(DX), AX
. . 10ca3f0: CALL AX
. . 10ca3f2: MOVZX 0x1e0(SP), AX ;graph.go:39
. . 10ca3fa: TESTL AL, AL
. . 10ca3fc: JNE 0x10ca503 ;graph.go:81
. . 10ca402: LEAQ go.string.*+4830(SB), AX ;graph.go:87
. . 10ca409: MOVQ AX, 0(SP)
. . 10ca40d: MOVQ $0xc, 0x8(SP)
. . 10ca416: CALL main.newTimer(SB)
. . 10ca41b: MOVQ 0x10(SP), AX
. . 10ca420: MOVQ AX, 0xf0(SP)
. . 10ca428: MOVQ 0x120(SP), CX ;graph.go:88
. . 10ca430: MOVQ CX, 0(SP)
. . 10ca434: MOVQ 0xf8(SP), DX
. . 10ca43c: MOVQ DX, 0x8(SP)
. 369.13MB 10ca441: CALL main.(*Graph).buildAdjList(SB) ;main.LoadDictionary graph.go:88
. . 10ca446: MOVQ 0xf0(SP), DX ;graph.go:89
. . 10ca44e: MOVQ 0(DX), AX
. . 10ca451: CALL AX
. . 10ca453: MOVQ 0x1f0(SP), AX ;graph.go:65
. . 10ca45b: TESTQ AX, AX
. . 10ca45e: JNE 0x10ca4a5 ;graph.go:91
. . 10ca460: MOVZX 0x1e1(SP), AX ;graph.go:39
. . 10ca468: TESTL AL, AL
. . 10ca46a: JNE 0x10ca492 ;graph.go:95
. . 10ca46c: MOVQ 0x120(SP), AX ;graph.go:99
. . 10ca474: MOVQ AX, 0x1f8(SP)
. . 10ca47c: NOPL
. . 10ca47d: CALL runtime.deferreturn(SB)
. . 10ca482: MOVQ 0x1b8(SP), BP
. . 10ca48a: ADDQ $0x1c0, SP
. . 10ca491: RET
. . 10ca492: MOVQ 0x120(SP), AX ;graph.go:96
. . 10ca49a: MOVQ AX, 0(SP)
. . 10ca49e: CALL main.adjListStats(SB)
. . 10ca4a3: JMP 0x10ca46c
. . 10ca4a5: MOVQ $0x0, 0(SP) ;graph.go:92
. . 10ca4ad: MOVQ 0x1e8(SP), CX
. . 10ca4b5: MOVQ CX, 0x8(SP)
. . 10ca4ba: MOVQ AX, 0x10(SP)
. . 10ca4bf: LEAQ go.string.*+2074(SB), AX
. . 10ca4c6: MOVQ AX, 0x18(SP)
. . 10ca4cb: MOVQ $0x8, 0x20(SP)
. . 10ca4d4: CALL runtime.concatstring2(SB)
. . 10ca4d9: MOVQ 0x30(SP), AX
. . 10ca4de: MOVQ 0x28(SP), CX
. . 10ca4e3: MOVQ 0x120(SP), DX
. . 10ca4eb: MOVQ DX, 0(SP)
. . 10ca4ef: MOVQ CX, 0x8(SP)
. . 10ca4f4: MOVQ AX, 0x10(SP)
. . 10ca4f9: CALL main.(*Graph).dumpAdjList(SB)
. . 10ca4fe: JMP 0x10ca460
. . 10ca503: MOVQ 0xf8(SP), AX ;graph.go:82
. . 10ca50b: MOVQ AX, 0(SP)
. . 10ca50f: CALL main.(*index).printStats(SB)
. . 10ca514: JMP 0x10ca402
. . 10ca519: LEAQ 0x18(DX), DI ;graph.go:69
. . 10ca51d: CALL runtime.gcWriteBarrier(SB)
. . 10ca522: JMP 0x10ca288
. . 10ca527: MOVQ $0x0, 0(SP) ;graph.go:66
. . 10ca52f: MOVQ 0x1e8(SP), CX
. . 10ca537: MOVQ CX, 0x8(SP)
. . 10ca53c: MOVQ AX, 0x10(SP)
. . 10ca541: LEAQ go.string.*+5483(SB), DX
. . 10ca548: MOVQ DX, 0x18(SP)
. . 10ca54d: MOVQ $0xd, 0x20(SP)
. . 10ca556: CALL runtime.concatstring2(SB)
. . 10ca55b: MOVQ 0x30(SP), AX
. . 10ca560: MOVQ 0x28(SP), CX
. . 10ca565: MOVQ 0x120(SP), DX
. . 10ca56d: MOVQ DX, 0(SP)
. . 10ca571: MOVQ CX, 0x8(SP)
. . 10ca576: MOVQ AX, 0x10(SP)
. . 10ca57b: CALL main.(*Graph).dumpVertices(SB)
. . 10ca580: JMP 0x10ca232
. . 10ca585: MOVQ AX, 0x110(SP) ;graph.go:49
. . 10ca58d: LEAQ runtime.types+158240(SB), AX ;graph.go:48
. . 10ca594: MOVQ AX, 0(SP)
. . 10ca598: MOVQ 0x120(SP), AX
. . 10ca5a0: MOVQ AX, 0x8(SP)
. . 10ca5a5: CALL runtime.typedmemclr(SB)
. . 10ca5aa: MOVQ 0x120(SP), DI
. . 10ca5b2: MOVQ 0x110(SP), AX
. . 10ca5ba: CALL runtime.gcWriteBarrier(SB)
. . 10ca5bf: MOVQ DI, CX ;graph.go:69
. . 10ca5c2: XORPS X0, X0 ;graph.go:49
. . 10ca5c5: JMP 0x10ca04b ;graph.go:48
. . 10ca5ca: NOPL ;graph.go:46
. . 10ca5cb: CALL runtime.deferreturn(SB)
. . 10ca5d0: MOVQ 0x1b8(SP), BP
. . 10ca5d8: ADDQ $0x1c0, SP
. . 10ca5df: RET
. . 10ca5e0: NOPL ;graph.go:41
. . 10ca5e1: CALL runtime.deferreturn(SB)
. . 10ca5e6: MOVQ 0x1b8(SP), BP
. . 10ca5ee: ADDQ $0x1c0, SP
. . 10ca5f5: RET
. . 10ca5f6: LEAQ go.string.*+3958(SB), AX ;stats.go:42
. . 10ca5fd: CALL runtime.gcWriteBarrier(SB)
. . 10ca602: MOVQ DX, DI
. . 10ca605: MOVQ SI, AX
. . 10ca608: CALL runtime.gcWriteBarrier(SB)
. . 10ca60d: JMP 0x10c9ed4
. . 10ca612: MOVQ SI, 0x110(SP)
. . 10ca61a: LEAQ runtime.types+158400(SB), SI
. . 10ca621: MOVQ SI, 0(SP)
. . 10ca625: MOVQ CX, 0x8(SP)
. . 10ca62a: MOVQ AX, 0x10(SP)
. . 10ca62f: MOVQ BX, 0x18(SP)
. . 10ca634: MOVQ DX, 0x20(SP)
. . 10ca639: CALL runtime.growslice(SB)
. . 10ca63e: MOVQ 0x28(SP), AX
. . 10ca643: MOVQ 0x30(SP), CX
. . 10ca648: MOVQ 0x38(SP), DX
. . 10ca64d: MOVQ DX, main.stats+16(SB)
. . 10ca654: CMPL $0x0, runtime.writeBarrier(SB)
. . 10ca65b: JNE 0x10ca67a
. . 10ca65d: MOVQ AX, main.stats(SB)
. . 10ca664: MOVQ 0x110(SP), SI
. . 10ca66c: MOVQ AX, DX
. . 10ca66f: MOVQ CX, AX
. . 10ca672: MOVQ DX, CX
. . 10ca675: JMP 0x10c9e87
. . 10ca67a: LEAQ main.stats(SB), DI
. . 10ca681: CALL runtime.gcWriteBarrier(SB)
. . 10ca686: JMP 0x10ca664
. . 10ca688: MOVQ SI, AX ;graph.go:71
. . 10ca68b: CALL runtime.panicIndex(SB)
. . 10ca690: NOPL
. . 10ca691: CALL runtime.morestack_noctxt(SB) ;graph.go:39
. . 10ca696: JMP main.LoadDictionary(SB)
. . 10ca69b: INT $0x3
. . 10ca69c: INT $0x3
. . 10ca69d: INT $0x3
. . 10ca69e: INT $0x3
ROUTINE ======================== main.main
0 819.30MB (flat, cum) 100% of Total
. . 10cda30: MOVQ GS:0x30, CX ;main.go:27
. . 10cda39: LEAQ 0xfffffd98(SP), AX
. . 10cda41: CMPQ 0x10(CX), AX
. . 10cda45: JBE 0x10ce76a
. . 10cda4b: SUBQ $0x2e8, SP
. . 10cda52: MOVQ BP, 0x2e0(SP)
. . 10cda5a: LEAQ 0x2e0(SP), BP
. . 10cda62: MOVQ os.Args+8(SB), CX ;main.go:28
. . 10cda69: MOVQ os.Args(SB), DX ;flag.go:996
. . 10cda70: MOVQ os.Args+16(SB), BX
. . 10cda77: CMPQ $0x1, CX
. . 10cda7b: JB 0x10ce75f
. . 10cda81: MOVQ flag.CommandLine(SB), AX
. . 10cda88: MOVQ AX, 0(SP)
. . 10cda8c: LEAQ -0x1(BX), AX
. . 10cda90: MOVQ AX, BX
. . 10cda93: NEGQ AX
. . 10cda96: SARQ $0x3f, AX
. . 10cda9a: ANDQ $0x10, AX
. . 10cda9e: ADDQ DX, AX
. . 10cdaa1: MOVQ AX, 0x8(SP)
. . 10cdaa6: LEAQ -0x1(CX), AX
. . 10cdaaa: MOVQ AX, 0x10(SP)
. . 10cdaaf: MOVQ BX, 0x18(SP)
. . 10cdab4: CALL flag.(*FlagSet).Parse(SB)
. . 10cdab9: MOVQ main.cpuprofile(SB), AX ;main.go:30
. . 10cdac0: MOVQ 0(AX), CX
. . 10cdac3: MOVQ 0x8(AX), AX
. . 10cdac7: TESTQ AX, AX
. . 10cdaca: JNE 0x10ce602
. . 10cdad0: MOVQ main.traceprofile(SB), AX ;main.go:40
. . 10cdad7: MOVQ 0(AX), CX
. . 10cdada: MOVQ 0x8(AX), AX
. . 10cdade: TESTQ AX, AX
. . 10cdae1: JNE 0x10ce4a0
. . 10cdae7: MOVQ main.dump(SB), AX ;main.go:50
. . 10cdaee: MOVQ 0x8(AX), CX
. . 10cdaf2: MOVQ 0(AX), AX
. . 10cdaf5: TESTQ CX, CX
. . 10cdaf8: JNE 0x10ce48d
. . 10cdafe: XORPS X0, X0 ;main.go:54
. . 10cdb01: MOVUPS X0, 0x250(SP)
. . 10cdb09: LEAQ runtime.types+88864(SB), AX
. . 10cdb10: MOVQ AX, 0x250(SP)
. . 10cdb18: LEAQ internal/bytealg.IndexString.args_stackmap+640(SB), CX
. . 10cdb1f: MOVQ CX, 0x258(SP)
. . 10cdb27: MOVQ os.Stdout(SB), CX ;print.go:274
. . 10cdb2e: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10cdb35: MOVQ DX, 0(SP)
. . 10cdb39: MOVQ CX, 0x8(SP)
. . 10cdb3e: LEAQ 0x250(SP), CX
. . 10cdb46: MOVQ CX, 0x10(SP)
. . 10cdb4b: MOVQ $0x1, 0x18(SP)
. . 10cdb54: MOVQ $0x1, 0x20(SP)
. . 10cdb5d: CALL fmt.Fprintln(SB)
. . 10cdb62: MOVQ main.dict(SB), AX ;main.go:55
. . 10cdb69: MOVQ main.numBuckets(SB), CX
. . 10cdb70: MOVQ main.indexStats(SB), DX
. . 10cdb77: MOVQ main.perfStats(SB), BX
. . 10cdb7e: MOVQ main.dump(SB), SI
. . 10cdb85: MOVQ 0x8(AX), DI
. . 10cdb89: MOVQ 0(AX), AX
. . 10cdb8c: MOVQ 0(CX), CX
. . 10cdb8f: MOVZX 0(DX), DX
. . 10cdb92: MOVZX 0(BX), BX
. . 10cdb95: MOVQ 0(SI), R8
. . 10cdb98: MOVQ 0x8(SI), SI
. . 10cdb9c: MOVQ AX, 0(SP)
. . 10cdba0: MOVQ DI, 0x8(SP)
. . 10cdba5: MOVQ CX, 0x10(SP)
. . 10cdbaa: MOVB DL, 0x18(SP)
. . 10cdbae: MOVB BL, 0x19(SP)
. . 10cdbb2: MOVQ R8, 0x20(SP)
. . 10cdbb7: MOVQ SI, 0x28(SP)
. 817.58MB 10cdbbc: CALL main.LoadDictionary(SB) ;main.main main.go:55
. . 10cdbc1: MOVQ 0x30(SP), AX ;main.go:55
. . 10cdbc6: MOVQ AX, 0x1d0(SP)
. . 10cdbce: MOVQ 0x8(AX), CX ;graph.go:304
. . 10cdbd2: MOVQ CX, 0x78(SP)
. . 10cdbd7: MOVQ AX, 0(SP) ;main.go:56
. . 10cdbdb: CALL main.(*Graph).EdgeCount(SB)
. . 10cdbe0: MOVQ 0x8(SP), AX
. . 10cdbe5: MOVQ AX, 0x70(SP)
. . 10cdbea: MOVQ 0x78(SP), CX
. . 10cdbef: MOVQ CX, 0(SP)
. . 10cdbf3: CALL runtime.convT64(SB)
. . 10cdbf8: MOVQ 0x8(SP), AX
. . 10cdbfd: MOVQ AX, 0x1f8(SP)
. . 10cdc05: MOVQ 0x70(SP), CX
. . 10cdc0a: MOVQ CX, 0(SP)
. . 10cdc0e: CALL runtime.convT64(SB)
. . 10cdc13: MOVQ 0x8(SP), AX
. . 10cdc18: XORPS X0, X0
. . 10cdc1b: MOVUPS X0, 0x2c0(SP)
. . 10cdc23: MOVUPS X0, 0x2d0(SP)
. . 10cdc2b: LEAQ runtime.types+86176(SB), CX
. . 10cdc32: MOVQ CX, 0x2c0(SP)
. . 10cdc3a: MOVQ 0x1f8(SP), DX
. . 10cdc42: MOVQ DX, 0x2c8(SP)
. . 10cdc4a: MOVQ CX, 0x2d0(SP)
. . 10cdc52: MOVQ AX, 0x2d8(SP)
. . 10cdc5a: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10cdc61: LEAQ go.itab.*os.File,io.Writer(SB), CX
. . 10cdc68: MOVQ CX, 0(SP)
. . 10cdc6c: MOVQ AX, 0x8(SP)
. . 10cdc71: LEAQ go.string.*+11078(SB), AX
. . 10cdc78: MOVQ AX, 0x10(SP)
. . 10cdc7d: MOVQ $0x14, 0x18(SP)
. . 10cdc86: LEAQ 0x2c0(SP), AX
. . 10cdc8e: MOVQ AX, 0x20(SP)
. . 10cdc93: MOVQ $0x2, 0x28(SP)
. . 10cdc9c: MOVQ $0x2, 0x30(SP)
. . 10cdca5: CALL fmt.Fprintf(SB)
. . 10cdcaa: MOVQ main.dictStats(SB), AX ;main.go:58
. . 10cdcb1: CMPB $0x0, 0(AX)
. . 10cdcb4: JNE 0x10ce46c
. . 10cdcba: MOVQ main.src(SB), AX ;main.go:62
. . 10cdcc1: MOVQ 0(AX), CX
. . 10cdcc4: MOVQ 0x8(AX), AX
. . 10cdcc8: TESTQ AX, AX
. . 10cdccb: JE 0x10cdcdf
. . 10cdccd: MOVQ main.dest(SB), DX
. . 10cdcd4: CMPQ $0x0, 0x8(DX)
. . 10cdcd9: JNE 0x10cdf0e
. . 10cdcdf: MOVQ main.printGraph(SB), AX ;main.go:86
. . 10cdce6: CMPB $0x0, 0(AX)
. . 10cdce9: JNE 0x10cdef8
. . 10cdcef: MOVQ main.csv(SB), AX ;main.go:90
. . 10cdcf6: CMPB $0x0, 0(AX)
. . 10cdcf9: JE 0x10cdeee
. . 10cdcff: MOVB $0x1, 0(SP) ;main.go:91
. . 10cdd03: CALL main.PrintStatsCSV(SB)
. . 10cdd08: MOVQ main.memprofile(SB), AX ;main.go:96
. . 10cdd0f: CMPQ $0x0, 0x8(AX)
. . 10cdd14: JNE 0x10cdd2c
. . 10cdd16: NOPL ;main.go:107
. . 10cdd17: CALL runtime.deferreturn(SB)
. . 10cdd1c: MOVQ 0x2e0(SP), BP
. . 10cdd24: ADDQ $0x2e8, SP
. . 10cdd2b: RET
. . 10cdd2c: CALL runtime.GC(SB) ;main.go:97
. . 10cdd31: MOVQ main.memprofile(SB), AX ;main.go:98
. . 10cdd38: MOVQ 0(AX), CX
. . 10cdd3b: MOVQ 0x8(AX), AX
. . 10cdd3f: MOVQ CX, 0(SP) ;file.go:289
. . 10cdd43: MOVQ AX, 0x8(SP)
. . 10cdd48: MOVQ $0x602, 0x10(SP)
. . 10cdd51: MOVL $0x1b6, 0x18(SP)
. . 10cdd59: CALL os.OpenFile(SB)
. . 10cdd5e: MOVQ 0x20(SP), AX
. . 10cdd63: MOVQ AX, 0x1f0(SP)
. . 10cdd6b: MOVQ 0x28(SP), CX
. . 10cdd70: MOVQ 0x30(SP), DX
. . 10cdd75: TESTQ CX, CX ;main.go:99
. . 10cdd78: JE 0x10cdde4
. . 10cdd7a: JE 0x10cdd80 ;main.go:100
. . 10cdd7c: MOVQ 0x8(CX), CX
. . 10cdd80: XORPS X0, X0
. . 10cdd83: MOVUPS X0, 0x260(SP)
. . 10cdd8b: MOVUPS X0, 0x270(SP)
. . 10cdd93: LEAQ runtime.types+88864(SB), AX
. . 10cdd9a: MOVQ AX, 0x260(SP)
. . 10cdda2: LEAQ internal/bytealg.IndexString.args_stackmap+672(SB), BX
. . 10cdda9: MOVQ BX, 0x268(SP)
. . 10cddb1: MOVQ CX, 0x270(SP)
. . 10cddb9: MOVQ DX, 0x278(SP)
. . 10cddc1: LEAQ 0x260(SP), CX
. . 10cddc9: MOVQ CX, 0(SP)
. . 10cddcd: MOVQ $0x2, 0x8(SP)
. . 10cddd6: MOVQ $0x2, 0x10(SP)
. . 10cdddf: CALL log.Fatal(SB)
. . 10cdde4: MOVL $0x18, 0xf0(SP) ;main.go:102
. . 10cddef: LEAQ go.func.*+300(SB), AX
. . 10cddf6: MOVQ AX, 0x108(SP)
. . 10cddfe: MOVQ 0x1f0(SP), AX
. . 10cde06: MOVQ AX, 0x120(SP)
. . 10cde0e: LEAQ 0xf0(SP), CX
. . 10cde16: MOVQ CX, 0(SP)
. . 10cde1a: CALL runtime.deferprocStack(SB)
. . 10cde1f: TESTL AX, AX
. . 10cde21: JNE 0x10cded8
. . 10cde27: NOPL ;pprof.go:522
. . 10cde28: LEAQ go.itab.*os.File,io.Writer(SB), AX ;pprof.go:533
. . 10cde2f: MOVQ AX, 0(SP)
. . 10cde33: MOVQ 0x1f0(SP), AX
. . 10cde3b: MOVQ AX, 0x8(SP)
. . 10cde40: MOVQ $0x0, 0x10(SP)
. . 10cde49: XORPS X0, X0
. . 10cde4c: MOVUPS X0, 0x18(SP)
. . 10cde51: CALL runtime/pprof.writeHeapInternal(SB)
. . 10cde56: MOVQ 0x28(SP), AX
. . 10cde5b: MOVQ 0x30(SP), CX
. . 10cde60: TESTQ AX, AX ;main.go:103
. . 10cde63: JE 0x10cdd16
. . 10cde69: JE 0x10cde6f ;main.go:104
. . 10cde6b: MOVQ 0x8(AX), AX
. . 10cde6f: XORPS X0, X0
. . 10cde72: MOVUPS X0, 0x260(SP)
. . 10cde7a: MOVUPS X0, 0x270(SP)
. . 10cde82: LEAQ runtime.types+88864(SB), DX
. . 10cde89: MOVQ DX, 0x260(SP)
. . 10cde91: LEAQ internal/bytealg.IndexString.args_stackmap+688(SB), DX
. . 10cde98: MOVQ DX, 0x268(SP)
. . 10cdea0: MOVQ AX, 0x270(SP)
. . 10cdea8: MOVQ CX, 0x278(SP)
. . 10cdeb0: LEAQ 0x260(SP), AX
. . 10cdeb8: MOVQ AX, 0(SP)
. . 10cdebc: MOVQ $0x2, 0x8(SP)
. . 10cdec5: MOVQ $0x2, 0x10(SP)
. . 10cdece: CALL log.Fatal(SB)
. . 10cded3: JMP 0x10cdd16
. . 10cded8: NOPL ;main.go:102
. . 10cded9: CALL runtime.deferreturn(SB)
. . 10cdede: MOVQ 0x2e0(SP), BP
. . 10cdee6: ADDQ $0x2e8, SP
. . 10cdeed: RET
. . 10cdeee: CALL main.PrintStats(SB) ;main.go:93
. . 10cdef3: JMP 0x10cdd08
. . 10cdef8: MOVQ 0x1d0(SP), AX ;main.go:87
. . 10cdf00: MOVQ AX, 0(SP)
. . 10cdf04: CALL main.(*Graph).PrintAdjList(SB)
. . 10cdf09: JMP 0x10cdcef
. . 10cdf0e: MOVQ CX, 0(SP) ;main.go:63
. . 10cdf12: MOVQ AX, 0x8(SP)
. . 10cdf17: CALL runtime.convTstring(SB)
. . 10cdf1c: MOVQ main.dest(SB), AX
. . 10cdf23: MOVQ 0x10(SP), CX
. . 10cdf28: MOVQ CX, 0x1f8(SP)
. . 10cdf30: MOVQ 0x8(AX), DX
. . 10cdf34: MOVQ 0(AX), AX
. . 10cdf37: MOVQ AX, 0(SP)
. . 10cdf3b: MOVQ DX, 0x8(SP)
. . 10cdf40: CALL runtime.convTstring(SB)
. . 10cdf45: MOVQ 0x10(SP), AX
. . 10cdf4a: XORPS X0, X0
. . 10cdf4d: MOVUPS X0, 0x2a0(SP)
. . 10cdf55: MOVUPS X0, 0x2b0(SP)
. . 10cdf5d: LEAQ runtime.types+88864(SB), CX
. . 10cdf64: MOVQ CX, 0x2a0(SP)
. . 10cdf6c: MOVQ 0x1f8(SP), DX
. . 10cdf74: MOVQ DX, 0x2a8(SP)
. . 10cdf7c: MOVQ CX, 0x2b0(SP)
. . 10cdf84: MOVQ AX, 0x2b8(SP)
. . 10cdf8c: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10cdf93: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10cdf9a: MOVQ DX, 0(SP)
. . 10cdf9e: MOVQ AX, 0x8(SP)
. . 10cdfa3: LEAQ go.string.*+16367(SB), AX
. . 10cdfaa: MOVQ AX, 0x10(SP)
. . 10cdfaf: MOVQ $0x1b, 0x18(SP)
. . 10cdfb8: LEAQ 0x2a0(SP), AX
. . 10cdfc0: MOVQ AX, 0x20(SP)
. . 10cdfc5: MOVQ $0x2, 0x28(SP)
. . 10cdfce: MOVQ $0x2, 0x30(SP)
. . 10cdfd7: CALL fmt.Fprintf(SB)
. . 10cdfdc: MOVQ main.src(SB), AX ;main.go:64
. . 10cdfe3: MOVQ 0x8(AX), CX
. . 10cdfe7: MOVQ 0(AX), AX
. . 10cdfea: MOVQ 0x1d0(SP), DX
. . 10cdff2: MOVQ DX, 0(SP)
. . 10cdff6: MOVQ AX, 0x8(SP)
. . 10cdffb: MOVQ CX, 0x10(SP)
. . 10ce000: CALL main.(*Graph).Find(SB)
. . 10ce005: MOVQ main.dest(SB), AX ;main.go:65
. . 10ce00c: MOVQ 0x18(SP), CX ;main.go:64
. . 10ce011: MOVQ CX, 0x58(SP)
. . 10ce016: MOVQ 0x8(AX), DX ;main.go:65
. . 10ce01a: MOVQ 0(AX), AX
. . 10ce01d: MOVQ 0x1d0(SP), BX
. . 10ce025: MOVQ BX, 0(SP)
. . 10ce029: MOVQ AX, 0x8(SP)
. . 10ce02e: MOVQ DX, 0x10(SP)
. . 10ce033: CALL main.(*Graph).Find(SB)
. . 10ce038: MOVQ 0x18(SP), AX
. . 10ce03d: MOVQ 0x58(SP), CX ;main.go:67
. . 10ce042: TESTQ CX, CX
. . 10ce045: JL 0x10ce311
. . 10ce04b: TESTQ AX, AX
. . 10ce04e: JL 0x10ce30e
. . 10ce054: XORPS X0, X0 ;main.go:77
. . 10ce057: MOVUPS X0, 0x220(SP)
. . 10ce05f: LEAQ runtime.types+88864(SB), AX
. . 10ce066: MOVQ AX, 0x220(SP)
. . 10ce06e: LEAQ internal/bytealg.IndexString.args_stackmap+656(SB), CX
. . 10ce075: MOVQ CX, 0x228(SP)
. . 10ce07d: MOVQ os.Stdout(SB), CX ;print.go:274
. . 10ce084: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10ce08b: MOVQ DX, 0(SP)
. . 10ce08f: MOVQ CX, 0x8(SP)
. . 10ce094: LEAQ 0x220(SP), CX
. . 10ce09c: MOVQ CX, 0x10(SP)
. . 10ce0a1: MOVQ $0x1, 0x18(SP)
. . 10ce0aa: MOVQ $0x1, 0x20(SP)
. . 10ce0b3: CALL fmt.Fprintln(SB)
. . 10ce0b8: MOVQ 0x1d0(SP), AX ;main.go:78
. . 10ce0c0: MOVQ AX, 0(SP)
. . 10ce0c4: MOVQ 0x58(SP), CX
. . 10ce0c9: MOVQ CX, 0x8(SP)
. . 10ce0ce: CALL main.(*Graph).AllPaths(SB)
. . 10ce0d3: MOVQ main.dest(SB), AX ;main.go:79
. . 10ce0da: MOVQ 0x10(SP), CX ;main.go:78
. . 10ce0df: MOVQ 0(AX), DX ;main.go:79
. . 10ce0e2: MOVQ 0x8(AX), AX
. . 10ce0e6: MOVQ CX, 0(SP)
. . 10ce0ea: MOVQ DX, 0x8(SP)
. . 10ce0ef: MOVQ AX, 0x10(SP)
. . 10ce0f4: CALL main.(*Paths).To(SB)
. . 10ce0f9: MOVQ 0x20(SP), AX
. . 10ce0fe: MOVQ AX, 0x60(SP)
. . 10ce103: MOVQ 0x18(SP), CX
. . 10ce108: MOVQ CX, 0x1c8(SP)
. . 10ce110: TESTQ AX, AX ;main.go:80
. . 10ce113: JE 0x10ce220
. . 10ce119: MOVQ 0x1d0(SP), DX ;main.go:83
. . 10ce121: XORL BX, BX
. . 10ce123: JMP 0x10ce1fe
. . 10ce128: MOVQ BX, 0x78(SP)
. . 10ce12d: LEAQ 0(SI)(SI*2), AX ;main.go:84
. . 10ce131: MOVQ 0x10(R8)(AX*8), CX
. . 10ce136: MOVQ 0x8(R8)(AX*8), DX
. . 10ce13b: MOVQ 0(R8)(AX*8), AX
. . 10ce13f: MOVQ $0x0, 0(SP)
. . 10ce147: MOVQ AX, 0x8(SP)
. . 10ce14c: MOVQ DX, 0x10(SP)
. . 10ce151: MOVQ CX, 0x18(SP)
. . 10ce156: CALL runtime.slicebytetostring(SB)
. . 10ce15b: MOVQ 0x20(SP), AX
. . 10ce160: MOVQ 0x28(SP), CX
. . 10ce165: MOVQ AX, 0(SP)
. . 10ce169: MOVQ CX, 0x8(SP)
. . 10ce16e: CALL runtime.convTstring(SB)
. . 10ce173: MOVQ 0x10(SP), AX
. . 10ce178: XORPS X0, X0
. . 10ce17b: MOVUPS X0, 0x210(SP)
. . 10ce183: LEAQ runtime.types+88864(SB), CX
. . 10ce18a: MOVQ CX, 0x210(SP)
. . 10ce192: MOVQ AX, 0x218(SP)
. . 10ce19a: MOVQ os.Stdout(SB), AX ;print.go:274
. . 10ce1a1: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10ce1a8: MOVQ DX, 0(SP)
. . 10ce1ac: MOVQ AX, 0x8(SP)
. . 10ce1b1: LEAQ 0x210(SP), AX
. . 10ce1b9: MOVQ AX, 0x10(SP)
. . 10ce1be: MOVQ $0x1, 0x18(SP)
. . 10ce1c7: MOVQ $0x1, 0x20(SP)
. . 10ce1d0: CALL fmt.Fprintln(SB)
. . 10ce1d5: MOVQ 0x78(SP), AX ;main.go:83
. . 10ce1da: LEAQ 0x1(AX), BX
. . 10ce1de: MOVQ 0x60(SP), AX
. . 10ce1e3: MOVQ 0x1d0(SP), CX
. . 10ce1eb: MOVQ 0x1c8(SP), DX
. . 10ce1f3: MOVQ DX, CX
. . 10ce1f6: MOVQ 0x1d0(SP), DX ;main.go:84
. . 10ce1fe: CMPQ AX, BX ;main.go:83
. . 10ce201: JGE 0x10cdcef
. . 10ce207: MOVQ 0(CX)(BX*8), SI
. . 10ce20b: MOVQ 0x8(DX), DI ;main.go:84
. . 10ce20f: MOVQ 0(DX), R8
. . 10ce212: CMPQ DI, SI
. . 10ce215: JB 0x10ce128
. . 10ce21b: JMP 0x10ce754
. . 10ce220: MOVQ main.src(SB), AX ;main.go:81
. . 10ce227: MOVQ 0(AX), CX
. . 10ce22a: MOVQ 0x8(AX), AX
. . 10ce22e: MOVQ CX, 0(SP)
. . 10ce232: MOVQ AX, 0x8(SP)
. . 10ce237: CALL runtime.convTstring(SB)
. . 10ce23c: MOVQ main.dest(SB), AX
. . 10ce243: MOVQ 0x10(SP), CX
. . 10ce248: MOVQ CX, 0x1f8(SP)
. . 10ce250: MOVQ 0x8(AX), DX
. . 10ce254: MOVQ 0(AX), AX
. . 10ce257: MOVQ AX, 0(SP)
. . 10ce25b: MOVQ DX, 0x8(SP)
. . 10ce260: CALL runtime.convTstring(SB)
. . 10ce265: MOVQ 0x10(SP), AX
. . 10ce26a: XORPS X0, X0
. . 10ce26d: MOVUPS X0, 0x280(SP)
. . 10ce275: MOVUPS X0, 0x290(SP)
. . 10ce27d: LEAQ runtime.types+88864(SB), CX
. . 10ce284: MOVQ CX, 0x280(SP)
. . 10ce28c: MOVQ 0x1f8(SP), DX
. . 10ce294: MOVQ DX, 0x288(SP)
. . 10ce29c: MOVQ CX, 0x290(SP)
. . 10ce2a4: MOVQ AX, 0x298(SP)
. . 10ce2ac: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10ce2b3: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10ce2ba: MOVQ DX, 0(SP)
. . 10ce2be: MOVQ AX, 0x8(SP)
. . 10ce2c3: LEAQ go.string.*+20133(SB), AX
. . 10ce2ca: MOVQ AX, 0x10(SP)
. . 10ce2cf: MOVQ $0x1f, 0x18(SP)
. . 10ce2d8: LEAQ 0x280(SP), AX
. . 10ce2e0: MOVQ AX, 0x20(SP)
. . 10ce2e5: MOVQ $0x2, 0x28(SP)
. . 10ce2ee: MOVQ $0x2, 0x30(SP)
. . 10ce2f7: CALL fmt.Fprintf(SB)
. . 10ce2fc: MOVQ 0x60(SP), AX ;main.go:83
. . 10ce301: MOVQ 0x1c8(SP), CX
. . 10ce309: JMP 0x10ce119
. . 10ce30e: TESTQ CX, CX ;main.go:67
. . 10ce311: JL 0x10ce3ca ;main.go:68
. . 10ce317: TESTQ AX, AX ;main.go:71
. . 10ce31a: JL 0x10ce332
. . 10ce31c: NOPL ;main.go:74
. . 10ce31d: CALL runtime.deferreturn(SB)
. . 10ce322: MOVQ 0x2e0(SP), BP
. . 10ce32a: ADDQ $0x2e8, SP
. . 10ce331: RET
. . 10ce332: MOVQ main.dest(SB), AX ;main.go:72
. . 10ce339: MOVQ 0x8(AX), CX
. . 10ce33d: MOVQ 0(AX), AX
. . 10ce340: MOVQ AX, 0(SP)
. . 10ce344: MOVQ CX, 0x8(SP)
. . 10ce349: CALL runtime.convTstring(SB)
. . 10ce34e: MOVQ 0x10(SP), AX
. . 10ce353: XORPS X0, X0
. . 10ce356: MOVUPS X0, 0x230(SP)
. . 10ce35e: LEAQ runtime.types+88864(SB), CX
. . 10ce365: MOVQ CX, 0x230(SP)
. . 10ce36d: MOVQ AX, 0x238(SP)
. . 10ce375: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10ce37c: LEAQ go.itab.*os.File,io.Writer(SB), CX
. . 10ce383: MOVQ CX, 0(SP)
. . 10ce387: MOVQ AX, 0x8(SP)
. . 10ce38c: LEAQ go.string.*+7974(SB), AX
. . 10ce393: MOVQ AX, 0x10(SP)
. . 10ce398: MOVQ $0x11, 0x18(SP)
. . 10ce3a1: LEAQ 0x230(SP), AX
. . 10ce3a9: MOVQ AX, 0x20(SP)
. . 10ce3ae: MOVQ $0x1, 0x28(SP)
. . 10ce3b7: MOVQ $0x1, 0x30(SP)
. . 10ce3c0: CALL fmt.Fprintf(SB)
. . 10ce3c5: JMP 0x10ce31c ;main.go:74
. . 10ce3ca: MOVQ AX, 0x50(SP) ;main.go:65
. . 10ce3cf: MOVQ main.src(SB), AX ;main.go:69
. . 10ce3d6: MOVQ 0x8(AX), CX
. . 10ce3da: MOVQ 0(AX), AX
. . 10ce3dd: MOVQ AX, 0(SP)
. . 10ce3e1: MOVQ CX, 0x8(SP)
. . 10ce3e6: CALL runtime.convTstring(SB)
. . 10ce3eb: MOVQ 0x10(SP), AX
. . 10ce3f0: XORPS X0, X0
. . 10ce3f3: MOVUPS X0, 0x240(SP)
. . 10ce3fb: LEAQ runtime.types+88864(SB), CX
. . 10ce402: MOVQ CX, 0x240(SP)
. . 10ce40a: MOVQ AX, 0x248(SP)
. . 10ce412: MOVQ os.Stdout(SB), AX ;print.go:213
. . 10ce419: LEAQ go.itab.*os.File,io.Writer(SB), DX
. . 10ce420: MOVQ DX, 0(SP)
. . 10ce424: MOVQ AX, 0x8(SP)
. . 10ce429: LEAQ go.string.*+7974(SB), AX
. . 10ce430: MOVQ AX, 0x10(SP)
. . 10ce435: MOVQ $0x11, 0x18(SP)
. . 10ce43e: LEAQ 0x240(SP), BX
. . 10ce446: MOVQ BX, 0x20(SP)
. . 10ce44b: MOVQ $0x1, 0x28(SP)
. . 10ce454: MOVQ $0x1, 0x30(SP)
. . 10ce45d: CALL fmt.Fprintf(SB)
. . 10ce462: MOVQ 0x50(SP), AX ;main.go:71
. . 10ce467: JMP 0x10ce317
. . 10ce46c: MOVQ main.dict(SB), AX ;main.go:59
. . 10ce473: MOVQ 0x8(AX), CX
. . 10ce477: MOVQ 0(AX), AX
. . 10ce47a: MOVQ AX, 0(SP)
. . 10ce47e: MOVQ CX, 0x8(SP)
. . 10ce483: CALL main.dictionaryStats(SB)
. . 10ce488: JMP 0x10cdcba
. . 10ce48d: MOVQ AX, 0(SP) ;main.go:51
. . 10ce491: MOVQ CX, 0x8(SP)
. . 10ce496: CALL main.createPathIfNotExists(SB)
. . 10ce49b: JMP 0x10cdafe
. . 10ce4a0: NOPL ;main.go:41
. . 10ce4a1: MOVQ CX, 0(SP) ;file.go:289
. . 10ce4a5: MOVQ AX, 0x8(SP)
. . 10ce4aa: MOVQ $0x602, 0x10(SP)
. . 10ce4b3: MOVL $0x1b6, 0x18(SP)
. . 10ce4bb: CALL os.OpenFile(SB)
. . 10ce4c0: MOVQ 0x20(SP), AX
. . 10ce4c5: MOVQ AX, 0x1d8(SP)
. . 10ce4cd: MOVQ 0x28(SP), CX
. . 10ce4d2: MOVQ 0x30(SP), DX
. . 10ce4d7: TESTQ CX, CX ;main.go:42
. . 10ce4da: JE 0x10ce546
. . 10ce4dc: JE 0x10ce4e2 ;main.go:43
. . 10ce4de: MOVQ 0x8(CX), CX
. . 10ce4e2: XORPS X0, X0
. . 10ce4e5: MOVUPS X0, 0x260(SP)
. . 10ce4ed: MOVUPS X0, 0x270(SP)
. . 10ce4f5: LEAQ runtime.types+88864(SB), AX
. . 10ce4fc: MOVQ AX, 0x260(SP)
. . 10ce504: LEAQ internal/bytealg.IndexString.args_stackmap+624(SB), BX
. . 10ce50b: MOVQ BX, 0x268(SP)
. . 10ce513: MOVQ CX, 0x270(SP)
. . 10ce51b: MOVQ DX, 0x278(SP)
. . 10ce523: LEAQ 0x260(SP), CX
. . 10ce52b: MOVQ CX, 0(SP)
. . 10ce52f: MOVQ $0x2, 0x8(SP)
. . 10ce538: MOVQ $0x2, 0x10(SP)
. . 10ce541: CALL log.Fatal(SB)
. . 10ce546: MOVL $0x18, 0x138(SP) ;main.go:45
. . 10ce551: LEAQ go.func.*+300(SB), AX
. . 10ce558: MOVQ AX, 0x150(SP)
. . 10ce560: MOVQ 0x1d8(SP), CX
. . 10ce568: MOVQ CX, 0x168(SP)
. . 10ce570: LEAQ 0x138(SP), DX
. . 10ce578: MOVQ DX, 0(SP)
. . 10ce57c: CALL runtime.deferprocStack(SB)
. . 10ce581: TESTL AX, AX
. . 10ce583: JNE 0x10ce5ec
. . 10ce585: LEAQ go.itab.*os.File,io.Writer(SB), AX ;main.go:46
. . 10ce58c: MOVQ AX, 0(SP)
. . 10ce590: MOVQ 0x1d8(SP), CX
. . 10ce598: MOVQ CX, 0x8(SP)
. . 10ce59d: CALL runtime/trace.Start(SB)
. . 10ce5a2: MOVL $0x0, 0x80(SP) ;main.go:47
. . 10ce5ad: LEAQ go.func.*+1604(SB), AX
. . 10ce5b4: MOVQ AX, 0x98(SP)
. . 10ce5bc: LEAQ 0x80(SP), AX
. . 10ce5c4: MOVQ AX, 0(SP)
. . 10ce5c8: CALL runtime.deferprocStack(SB)
. . 10ce5cd: TESTL AX, AX
. . 10ce5cf: JNE 0x10ce5d6
. . 10ce5d1: JMP 0x10cdae7
. . 10ce5d6: NOPL
. . 10ce5d7: CALL runtime.deferreturn(SB)
. . 10ce5dc: MOVQ 0x2e0(SP), BP
. . 10ce5e4: ADDQ $0x2e8, SP
. . 10ce5eb: RET
. . 10ce5ec: NOPL ;main.go:45
. . 10ce5ed: CALL runtime.deferreturn(SB)
. . 10ce5f2: MOVQ 0x2e0(SP), BP
. . 10ce5fa: ADDQ $0x2e8, SP
. . 10ce601: RET
. . 10ce602: NOPL ;main.go:31
. . 10ce603: MOVQ CX, 0(SP) ;file.go:289
. . 10ce607: MOVQ AX, 0x8(SP)
. . 10ce60c: MOVQ $0x602, 0x10(SP)
. . 10ce615: MOVL $0x1b6, 0x18(SP)
. . 10ce61d: CALL os.OpenFile(SB)
. . 10ce622: MOVQ 0x20(SP), AX
. . 10ce627: MOVQ AX, 0x1e0(SP)
. . 10ce62f: MOVQ 0x28(SP), CX
. . 10ce634: MOVQ CX, 0x68(SP)
. . 10ce639: MOVQ 0x30(SP), DX
. . 10ce63e: MOVQ DX, 0x1e8(SP)
. . 10ce646: MOVL $0x18, 0x180(SP) ;main.go:32
. . 10ce651: LEAQ go.func.*+300(SB), BX
. . 10ce658: MOVQ BX, 0x198(SP)
. . 10ce660: MOVQ AX, 0x1b0(SP)
. . 10ce668: LEAQ 0x180(SP), SI
. . 10ce670: MOVQ SI, 0(SP)
. . 10ce674: CALL runtime.deferprocStack(SB)
. . 10ce679: TESTL AX, AX
. . 10ce67b: JNE 0x10ce73e
. . 10ce681: MOVQ 0x68(SP), AX ;main.go:33
. . 10ce686: TESTQ AX, AX
. . 10ce689: JE 0x10ce6d7
. . 10ce68b: JE 0x10ce691 ;main.go:34
. . 10ce68d: MOVQ 0x8(AX), AX
. . 10ce691: XORPS X0, X0
. . 10ce694: MOVUPS X0, 0x200(SP)
. . 10ce69c: MOVQ AX, 0x200(SP)
. . 10ce6a4: MOVQ 0x1e8(SP), AX
. . 10ce6ac: MOVQ AX, 0x208(SP)
. . 10ce6b4: LEAQ 0x200(SP), AX
. . 10ce6bc: MOVQ AX, 0(SP)
. . 10ce6c0: MOVQ $0x1, 0x8(SP)
. . 10ce6c9: MOVQ $0x1, 0x10(SP)
. . 10ce6d2: CALL log.Fatal(SB)
. . 10ce6d7: LEAQ go.itab.*os.File,io.Writer(SB), AX ;main.go:36
. . 10ce6de: MOVQ AX, 0(SP)
. . 10ce6e2: MOVQ 0x1e0(SP), CX
. . 10ce6ea: MOVQ CX, 0x8(SP)
. 1.72MB 10ce6ef: CALL runtime/pprof.StartCPUProfile(SB) ;main.main main.go:36
. . 10ce6f4: MOVL $0x0, 0xb8(SP) ;main.go:37
. . 10ce6ff: LEAQ go.func.*+1572(SB), AX
. . 10ce706: MOVQ AX, 0xd0(SP)
. . 10ce70e: LEAQ 0xb8(SP), AX
. . 10ce716: MOVQ AX, 0(SP)
. . 10ce71a: CALL runtime.deferprocStack(SB)
. . 10ce71f: TESTL AX, AX
. . 10ce721: JNE 0x10ce728
. . 10ce723: JMP 0x10cdad0
. . 10ce728: NOPL
. . 10ce729: CALL runtime.deferreturn(SB)
. . 10ce72e: MOVQ 0x2e0(SP), BP
. . 10ce736: ADDQ $0x2e8, SP
. . 10ce73d: RET
. . 10ce73e: NOPL ;main.go:32
. . 10ce73f: CALL runtime.deferreturn(SB)
. . 10ce744: MOVQ 0x2e0(SP), BP
. . 10ce74c: ADDQ $0x2e8, SP
. . 10ce753: RET
. . 10ce754: MOVQ SI, AX ;main.go:84
. . 10ce757: MOVQ DI, CX
. . 10ce75a: CALL runtime.panicIndex(SB)
. . 10ce75f: MOVL $0x1, AX ;flag.go:996
. . 10ce764: CALL runtime.panicSliceB(SB)
. . 10ce769: NOPL
. . 10ce76a: CALL runtime.morestack_noctxt(SB) ;main.go:27
. . 10ce76f: JMP main.main(SB)
. . 10ce774: INT $0x3
. . 10ce775: INT $0x3
. . 10ce776: INT $0x3
. . 10ce777: INT $0x3
. . 10ce778: INT $0x3
. . 10ce779: INT $0x3
. . 10ce77a: INT $0x3
. . 10ce77b: INT $0x3
. . 10ce77c: INT $0x3
. . 10ce77d: INT $0x3
. . 10ce77e: INT $0x3
ROUTINE ======================== main.newIndex
192MB 192MB (flat, cum) 23.43% of Total
. . 10cc040: MOVQ GS:0x30, CX ;index.go:17
. . 10cc049: CMPQ 0x10(CX), SP
. . 10cc04d: JBE 0x10cc24e
. . 10cc053: SUBQ $0x48, SP
. . 10cc057: MOVQ BP, 0x40(SP)
. . 10cc05c: LEAQ 0x40(SP), BP
. . 10cc061: LEAQ runtime.types+77472(SB), AX ;index.go:18
. . 10cc068: MOVQ AX, 0(SP)
. . 10cc06c: MOVQ 0x50(SP), AX
. . 10cc071: MOVQ AX, 0x8(SP)
. . 10cc076: MOVQ AX, 0x10(SP)
192MB 192MB 10cc07b: CALL runtime.makeslice(SB) ;main.newIndex index.go:18
. . 10cc080: MOVQ 0x18(SP), AX ;index.go:18
. . 10cc085: MOVQ AX, 0x38(SP)
. . 10cc08a: XORL CX, CX
. . 10cc08c: JMP 0x10cc095 ;index.go:19
. . 10cc08e: LEAQ 0x1(AX), CX
. . 10cc092: MOVQ BX, AX ;index.go:20
. . 10cc095: MOVQ 0x50(SP), DX ;index.go:19
. . 10cc09a: CMPQ DX, CX
. . 10cc09d: JGE 0x10cc104
. . 10cc09f: MOVQ CX, 0x20(SP)
. . 10cc0a4: LEAQ runtime.types+86176(SB), AX ;index.go:20
. . 10cc0ab: MOVQ AX, 0(SP)
. . 10cc0af: XORPS X0, X0
. . 10cc0b2: MOVUPS X0, 0x8(SP)
. . 10cc0b7: CALL runtime.makeslice(SB)
. . 10cc0bc: MOVQ 0x20(SP), AX
. . 10cc0c1: LEAQ 0(AX)(AX*2), CX
. . 10cc0c5: MOVQ 0x18(SP), DX
. . 10cc0ca: MOVQ 0x38(SP), BX
. . 10cc0cf: MOVQ $0x0, 0x8(BX)(CX*8)
. . 10cc0d8: MOVQ $0x0, 0x10(BX)(CX*8)
. . 10cc0e1: LEAQ 0(BX)(CX*8), DI
. . 10cc0e5: CMPL $0x0, runtime.writeBarrier(SB)
. . 10cc0ec: JNE 0x10cc0f4
. . 10cc0ee: MOVQ DX, 0(BX)(CX*8)
. . 10cc0f2: JMP 0x10cc08e
. . 10cc0f4: MOVQ AX, CX ;index.go:19
. . 10cc0f7: MOVQ DX, AX ;index.go:20
. . 10cc0fa: CALL runtime.gcWriteBarrier(SB)
. . 10cc0ff: MOVQ CX, AX ;index.go:19
. . 10cc102: JMP 0x10cc08e ;index.go:20
. . 10cc104: NOPL ;murmur64.go:18
. . 10cc105: MOVL $0x0, 0(SP) ;murmur64.go:22
. . 10cc10c: CALL erichgess/wordladder/vendor/github.com/spaolacci/murmur3.New128WithSeed(SB)
. . 10cc111: MOVQ 0x10(SP), AX
. . 10cc116: MOVQ 0x8(SP), CX
. . 10cc11b: LEAQ go.itab.*erichgess/wordladder/vendor/github.com/spaolacci/murmur3.digest128,erichgess/wordladder/vendor/github.com/spaolacci/murmur3.Hash128(SB), DX
. . 10cc122: CMPQ DX, CX
. . 10cc125: JNE 0x10cc22c
. . 10cc12b: MOVQ AX, 0x28(SP)
. . 10cc130: LEAQ runtime.types+89184(SB), AX ;index.go:24
. . 10cc137: MOVQ AX, 0(SP)
. . 10cc13b: MOVQ $0x0, 0x8(SP)
. . 10cc144: MOVQ 0x58(SP), AX
. . 10cc149: MOVQ AX, 0x10(SP)
. . 10cc14e: CALL runtime.makeslice(SB)
. . 10cc153: MOVQ 0x18(SP), AX
. . 10cc158: MOVQ AX, 0x30(SP)
. . 10cc15d: LEAQ runtime.types+196608(SB), CX ;index.go:26
. . 10cc164: MOVQ CX, 0(SP)
. . 10cc168: CALL runtime.newobject(SB)
. . 10cc16d: MOVQ 0x8(SP), AX
;index.go:23
. . 10cc172: LEAQ go.itab.*erichgess/wordladder/vendor/github.com/spaolacci/murmur3.digest64,hash.Hash64(SB), CX
. . 10cc179: MOVQ CX, 0(AX)
. . 10cc17c: CMPL $0x0, runtime.writeBarrier(SB)
. . 10cc183: JNE 0x10cc213
. . 10cc189: MOVQ 0x28(SP), CX
. . 10cc18e: MOVQ CX, 0x8(AX)
. . 10cc192: MOVQ $0x0, 0x30(AX) ;index.go:24
. . 10cc19a: MOVQ 0x58(SP), CX
. . 10cc19f: MOVQ CX, 0x38(AX)
. . 10cc1a3: CMPL $0x0, runtime.writeBarrier(SB)
. . 10cc1aa: JNE 0x10cc1fd
. . 10cc1ac: MOVQ 0x30(SP), CX
. . 10cc1b1: MOVQ CX, 0x28(AX)
. . 10cc1b5: MOVQ 0x50(SP), CX ;index.go:25
. . 10cc1ba: MOVQ CX, 0x18(AX)
. . 10cc1be: MOVQ CX, 0x20(AX)
. . 10cc1c2: CMPL $0x0, runtime.writeBarrier(SB)
. . 10cc1c9: JNE 0x10cc1e7
. . 10cc1cb: MOVQ 0x38(SP), DX
. . 10cc1d0: MOVQ DX, 0x10(AX)
. . 10cc1d4: MOVQ CX, 0x40(AX) ;index.go:26
. . 10cc1d8: MOVQ AX, 0x60(SP) ;index.go:22
. . 10cc1dd: MOVQ 0x40(SP), BP
. . 10cc1e2: ADDQ $0x48, SP
. . 10cc1e6: RET
. . 10cc1e7: LEAQ 0x10(AX), DI ;index.go:25
. . 10cc1eb: MOVQ AX, DX ;index.go:26
. . 10cc1ee: MOVQ 0x38(SP), AX ;index.go:25
. . 10cc1f3: CALL runtime.gcWriteBarrier(SB)
. . 10cc1f8: MOVQ DX, AX ;index.go:26
. . 10cc1fb: JMP 0x10cc1d4 ;index.go:25
. . 10cc1fd: LEAQ 0x28(AX), DI ;index.go:24
. . 10cc201: MOVQ AX, CX ;index.go:26
. . 10cc204: MOVQ 0x30(SP), AX ;index.go:24
. . 10cc209: CALL runtime.gcWriteBarrier(SB)
. . 10cc20e: MOVQ CX, AX ;index.go:25
. . 10cc211: JMP 0x10cc1b5 ;index.go:24
. . 10cc213: LEAQ 0x8(AX), DI ;index.go:23
. . 10cc217: MOVQ AX, CX ;index.go:26
. . 10cc21a: MOVQ 0x28(SP), AX ;index.go:23
. . 10cc21f: CALL runtime.gcWriteBarrier(SB)
. . 10cc224: MOVQ CX, AX ;index.go:24
. . 10cc227: JMP 0x10cc192 ;index.go:23
. . 10cc22c: MOVQ CX, 0(SP) ;murmur64.go:22
. . 10cc230: LEAQ runtime.types+201504(SB), AX
. . 10cc237: MOVQ AX, 0x8(SP)
. . 10cc23c: LEAQ runtime.types+157120(SB), AX
. . 10cc243: MOVQ AX, 0x10(SP)
. . 10cc248: CALL runtime.panicdottypeI(SB)
. . 10cc24d: NOPL
. . 10cc24e: CALL runtime.morestack_noctxt(SB) ;index.go:17
. . 10cc253: JMP main.newIndex(SB)
. . 10cc258: INT $0x3
. . 10cc259: INT $0x3
. . 10cc25a: INT $0x3
. . 10cc25b: INT $0x3
. . 10cc25c: INT $0x3
. . 10cc25d: INT $0x3
. . 10cc25e: INT $0x3
ROUTINE ======================== runtime.main
0 819.30MB (flat, cum) 100% of Total
. . 102caf0: MOVQ GS:0x30, CX ;proc.go:113
. . 102caf9: CMPQ 0x10(CX), SP
. . 102cafd: JBE 0x102ce70
. . 102cb03: SUBQ $0x78, SP
. . 102cb07: MOVQ BP, 0x70(SP)
. . 102cb0c: LEAQ 0x70(SP), BP
. . 102cb11: MOVQ GS:0x30, AX ;proc.go:114
. . 102cb1a: MOVQ AX, 0x68(SP)
. . 102cb1f: MOVQ 0x30(AX), CX ;proc.go:118
. . 102cb23: MOVQ 0(CX), CX
. . 102cb26: MOVQ $0x0, 0x130(CX)
;proc.go:124
. . 102cb31: MOVQ $0x3b9aca00, runtime.maxstacksize(SB)
. . 102cb3c: MOVB $0x1, runtime.mainStarted(SB) ;proc.go:130
. . 102cb43: LEAQ go.func.*+956(SB), CX ;proc.go:133
. . 102cb4a: MOVQ CX, 0(SP)
. . 102cb4e: CALL runtime.systemstack(SB)
. . 102cb53: MOVQ GS:0x30, AX ;proc.go:3550
. . 102cb5c: MOVQ 0x30(AX), AX
. . 102cb60: NOPL ;proc.go:144
. . 102cb61: INCL 0x274(AX) ;proc.go:3550
. . 102cb67: MOVQ GS:0x30, AX ;proc.go:3511
. . 102cb70: MOVQ 0x30(AX), CX ;proc.go:3512
. . 102cb74: NOPL ;proc.go:3551
. . 102cb75: MOVQ AX, DX ;runtime2.go:254
. . 102cb78: MOVQ AX, 0x168(CX)
. . 102cb7f: MOVQ 0x30(DX), AX ;proc.go:3513
. . 102cb83: MOVQ AX, 0xd8(DX) ;runtime2.go:292
. . 102cb8a: MOVQ 0x68(SP), AX ;proc.go:146
. . 102cb8f: MOVQ 0x30(AX), AX
. . 102cb93: LEAQ runtime.m0(SB), CX
. . 102cb9a: CMPQ CX, AX
. . 102cb9d: JNE 0x102ce56
. . 102cba3: LEAQ runtime..inittask(SB), AX ;proc.go:150
. . 102cbaa: MOVQ AX, 0(SP)
. . 102cbae: CALL runtime.doInit(SB)
. . 102cbb3: CALL runtime.nanotime(SB) ;proc.go:151
. . 102cbb8: CMPQ $0x0, 0(SP)
. . 102cbbd: JE 0x102ce3d
. . 102cbc3: MOVB $0x1, 0x27(SP) ;proc.go:156
. . 102cbc8: MOVL $0x8, 0x30(SP) ;proc.go:157
. . 102cbd0: LEAQ go.func.*+964(SB), AX
. . 102cbd7: MOVQ AX, 0x48(SP)
. . 102cbdc: LEAQ 0x27(SP), AX
. . 102cbe1: MOVQ AX, 0x60(SP)
. . 102cbe6: LEAQ 0x30(SP), AX
. . 102cbeb: MOVQ AX, 0(SP)
. . 102cbef: CALL runtime.deferprocStack(SB)
. . 102cbf4: TESTL AX, AX
. . 102cbf6: JNE 0x102cdc9
. . 102cbfc: CALL runtime.nanotime(SB) ;proc.go:164
. . 102cc01: MOVQ 0(SP), AX
. . 102cc05: MOVQ AX, runtime.runtimeInitTime(SB)
. . 102cc0c: CALL runtime.gcenable(SB) ;proc.go:166
. . 102cc11: LEAQ runtime.types+83424(SB), AX ;proc.go:168
. . 102cc18: MOVQ AX, 0(SP)
. . 102cc1c: MOVQ $0x0, 0x8(SP)
. . 102cc25: CALL runtime.makechan(SB)
. . 102cc2a: MOVQ 0x10(SP), AX
. . 102cc2f: CMPL $0x0, runtime.writeBarrier(SB)
. . 102cc36: JNE 0x102cdb8
. . 102cc3c: MOVQ AX, runtime.main_init_done(SB)
. . 102cc43: CMPB $0x0, runtime.iscgo(SB) ;proc.go:169
. . 102cc4a: JE 0x102ccba
. . 102cc4c: CMPQ $0x0, __cgo_thread_start(SB) ;proc.go:170
. . 102cc54: JE 0x102ce24
. . 102cc5a: CMPQ $0x0, runtime._cgo_setenv(SB) ;proc.go:174
. . 102cc62: JE 0x102ce0b
. . 102cc68: CMPQ $0x0, runtime._cgo_unsetenv(SB) ;proc.go:177
. . 102cc70: JE 0x102cdf2
;proc.go:181
. . 102cc76: CMPQ $0x0, __cgo_notify_runtime_init_done(SB)
. . 102cc7e: JE 0x102cdd9
. . 102cc84: XORL AX, AX ;proc.go:1865
. . 102cc86: LEAQ runtime.newmHandoff+32(SB), CX
. . 102cc8d: MOVL $0x1, DX
. . 102cc92: LOCK CMPXCHGL DX, 0(CX)
. . 102cc96: SETE CL
. . 102cc99: TESTL CL, CL
. . 102cc9b: JNE 0x102cd9a
;proc.go:187
. . 102cca1: MOVQ __cgo_notify_runtime_init_done(SB), AX
. . 102cca8: MOVQ AX, 0(SP)
. . 102ccac: MOVQ $0x0, 0x8(SP)
. . 102ccb5: CALL runtime.cgocall(SB)
. . 102ccba: LEAQ main..inittask(SB), AX ;proc.go:190
. . 102ccc1: MOVQ AX, 0(SP)
. . 102ccc5: CALL runtime.doInit(SB)
. . 102ccca: MOVQ runtime.main_init_done(SB), AX ;proc.go:192
. . 102ccd1: MOVQ AX, 0(SP)
. . 102ccd5: CALL runtime.closechan(SB)
. . 102ccda: MOVB $0x0, 0x27(SP) ;proc.go:194
. . 102ccdf: CALL runtime.unlockOSThread(SB) ;proc.go:195
. . 102cce4: CMPB $0x0, runtime.isarchive(SB) ;proc.go:197
. . 102cceb: JNE 0x102cd8a
. . 102ccf1: CMPB $0x0, runtime.islibrary(SB)
. . 102ccf8: JNE 0x102cd8a
. . 102ccfe: MOVQ go.func.*+972(SB), AX ;proc.go:203
. . 102cd05: LEAQ go.func.*+972(SB), DX
. 819.30MB 102cd0c: CALL AX ;runtime.main proc.go:203
. . 102cd0e: MOVL runtime.runningPanicDefers(SB), AX ;proc.go:212
. . 102cd14: TESTL AX, AX
. . 102cd16: JE 0x102cd4c
. . 102cd18: XORL AX, AX
. . 102cd1a: JMP 0x102cd3a ;proc.go:214
. . 102cd1c: MOVQ AX, 0x28(SP)
. . 102cd21: NOPL ;proc.go:218
. . 102cd22: LEAQ go.func.*+900(SB), AX ;proc.go:269
. . 102cd29: MOVQ AX, 0(SP)
. . 102cd2d: CALL runtime.mcall(SB)
. . 102cd32: MOVQ 0x28(SP), AX ;proc.go:214
. . 102cd37: INCQ AX
. . 102cd3a: CMPQ $0x3e8, AX
. . 102cd40: JGE 0x102cd4c
. . 102cd42: MOVL runtime.runningPanicDefers(SB), CX ;proc.go:215
. . 102cd48: TESTL CX, CX
. . 102cd4a: JNE 0x102cd1c
. . 102cd4c: MOVL runtime.panicking(SB), AX ;proc.go:221
. . 102cd52: TESTL AX, AX
. . 102cd54: JNE 0x102cd6c
. . 102cd56: MOVL $0x0, 0(SP) ;proc.go:225
. . 102cd5d: CALL runtime.exit(SB)
. . 102cd62: XORL AX, AX ;proc.go:228
. . 102cd64: MOVL $0x0, 0(AX)
. . 102cd6a: JMP 0x102cd62
. . 102cd6c: XORPS X0, X0 ;proc.go:222
. . 102cd6f: MOVUPS X0, 0(SP)
. . 102cd73: MOVW $0x1008, 0x10(SP)
. . 102cd7a: MOVQ $0x1, 0x18(SP)
. . 102cd83: CALL runtime.gopark(SB)
. . 102cd88: JMP 0x102cd56
. . 102cd8a: NOPL ;proc.go:200
. . 102cd8b: CALL runtime.deferreturn(SB)
. . 102cd90: MOVQ 0x70(SP), BP
. . 102cd95: ADDQ $0x78, SP
. . 102cd99: RET
. . 102cd9a: LEAQ go.func.*+1516(SB), AX ;proc.go:1868
. . 102cda1: MOVQ AX, 0(SP)
. . 102cda5: MOVQ $0x0, 0x8(SP)
. . 102cdae: CALL runtime.newm(SB)
. . 102cdb3: JMP 0x102cca1 ;proc.go:186
. . 102cdb8: LEAQ runtime.main_init_done(SB), DI ;proc.go:168
. . 102cdbf: CALL runtime.gcWriteBarrier(SB)
. . 102cdc4: JMP 0x102cc43
. . 102cdc9: NOPL ;proc.go:157
. . 102cdca: CALL runtime.deferreturn(SB)
. . 102cdcf: MOVQ 0x70(SP), BP
. . 102cdd4: ADDQ $0x78, SP
. . 102cdd8: RET
. . 102cdd9: LEAQ go.string.*+25332(SB), AX ;proc.go:182
. . 102cde0: MOVQ AX, 0(SP)
. . 102cde4: MOVQ $0x25, 0x8(SP)
. . 102cded: CALL runtime.throw(SB)
. . 102cdf2: LEAQ go.string.*+11989(SB), AX ;proc.go:178
. . 102cdf9: MOVQ AX, 0(SP)
. . 102cdfd: MOVQ $0x15, 0x8(SP)
. . 102ce06: CALL runtime.throw(SB)
. . 102ce0b: LEAQ go.string.*+9904(SB), AX ;proc.go:175
. . 102ce12: MOVQ AX, 0(SP)
. . 102ce16: MOVQ $0x13, 0x8(SP)
. . 102ce1f: CALL runtime.throw(SB)
. . 102ce24: LEAQ go.string.*+15120(SB), AX ;proc.go:171
. . 102ce2b: MOVQ AX, 0(SP)
. . 102ce2f: MOVQ $0x19, 0x8(SP)
. . 102ce38: CALL runtime.throw(SB)
. . 102ce3d: LEAQ go.string.*+13965(SB), AX ;proc.go:152
. . 102ce44: MOVQ AX, 0(SP)
. . 102ce48: MOVQ $0x17, 0x8(SP)
. . 102ce51: CALL runtime.throw(SB)
. . 102ce56: LEAQ go.string.*+13084(SB), AX ;proc.go:147
. . 102ce5d: MOVQ AX, 0(SP)
. . 102ce61: MOVQ $0x16, 0x8(SP)
. . 102ce6a: CALL runtime.throw(SB)
. . 102ce6f: NOPL
. . 102ce70: CALL runtime.morestack_noctxt(SB) ;proc.go:113
. . 102ce75: JMP runtime.main(SB)
. . 102ce7a: INT $0x3
. . 102ce7b: INT $0x3
. . 102ce7c: INT $0x3
. . 102ce7d: INT $0x3
. . 102ce7e: INT $0x3
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r13
push %r14
push %r8
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WT_ht+0x126fe, %r14
nop
nop
nop
and $13708, %r8
mov (%r14), %r11w
nop
nop
nop
cmp %rdi, %rdi
lea addresses_D_ht+0x13721, %r12
nop
nop
nop
nop
add %r13, %r13
movb (%r12), %dl
nop
nop
xor $2922, %r13
lea addresses_A_ht+0xc8be, %rdx
and %r11, %r11
and $0xffffffffffffffc0, %rdx
vmovaps (%rdx), %ymm2
vextracti128 $0, %ymm2, %xmm2
vpextrq $0, %xmm2, %r8
nop
nop
nop
nop
nop
cmp %rdx, %rdx
lea addresses_D_ht+0x503e, %r8
nop
nop
nop
nop
sub %rdi, %rdi
movw $0x6162, (%r8)
dec %r8
lea addresses_UC_ht+0x70be, %r11
nop
nop
nop
nop
dec %rdx
mov $0x6162636465666768, %r13
movq %r13, %xmm4
and $0xffffffffffffffc0, %r11
movaps %xmm4, (%r11)
nop
nop
nop
nop
nop
xor $50447, %rdx
lea addresses_WC_ht+0x3bbe, %r12
nop
nop
nop
sub %r8, %r8
movb $0x61, (%r12)
nop
nop
nop
cmp $17585, %r11
lea addresses_A_ht+0x873e, %r14
nop
nop
nop
nop
sub %r12, %r12
mov (%r14), %edx
nop
nop
nop
nop
nop
cmp $59985, %r8
lea addresses_WT_ht+0x4f7e, %rsi
lea addresses_D_ht+0x190be, %rdi
nop
and %r11, %r11
mov $29, %rcx
rep movsq
nop
nop
nop
mfence
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r14
pop %r13
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r14
push %r8
push %rbp
push %rcx
push %rdi
push %rsi
// Store
lea addresses_WC+0x160be, %r10
nop
nop
dec %r8
mov $0x5152535455565758, %rbp
movq %rbp, %xmm3
vmovups %ymm3, (%r10)
nop
nop
nop
nop
nop
sub %rsi, %rsi
// REPMOV
lea addresses_WC+0x1e8be, %rsi
lea addresses_PSE+0x1bb1e, %rdi
add $39189, %r13
mov $35, %rcx
rep movsb
sub %rdi, %rdi
// Faulty Load
lea addresses_WC+0x1e8be, %r13
nop
nop
nop
nop
nop
sub %rcx, %rcx
movb (%r13), %r8b
lea oracles, %rcx
and $0xff, %r8
shlq $12, %r8
mov (%rcx,%r8,1), %r8
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r8
pop %r14
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 8}}
{'OP': 'REPM', 'src': {'same': True, 'congruent': 0, 'type': 'addresses_WC'}, 'dst': {'same': False, 'congruent': 4, 'type': 'addresses_PSE'}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_WC', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_WT_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 6}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 0}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_A_ht', 'NT': False, 'AVXalign': True, 'size': 32, 'congruent': 11}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_D_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 6}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': True, 'size': 16, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WC_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 8}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_A_ht', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 5}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 5, 'type': 'addresses_WT_ht'}, 'dst': {'same': False, 'congruent': 10, 'type': 'addresses_D_ht'}}
{'38': 21829}
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
*/
|
;
; Small C+ Runtime Library
;
; CP/M functions
;
; CPM Plus "userf" custom Amstrad calls, for Amstrad CPC & PCW and ZX Spectrum +3
;
;
; $Id: a_serialport.asm,v 1.2 2017-01-02 20:06:48 aralbrec Exp $
;
SECTION code_clib
PUBLIC a_serialport
PUBLIC _a_serialport
EXTERN subuserf
INCLUDE "target/cpc/def/amstrad_userf.def"
a_serialport:
_a_serialport:
call subuserf
defw CD_INFO
ld l,c
ld h,0
ret
|
;
; jidctfst.asm - fast integer IDCT (64-bit SSE2)
;
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
; Copyright (C) 2009, 2016, D. R. Commander.
;
; Based on the x86 SIMD extension for IJG JPEG library
; Copyright (C) 1999-2006, MIYASAKA Masaru.
; For conditions of distribution and use, see copyright notice in jsimdext.inc
;
; This file should be assembled with NASM (Netwide Assembler),
; can *not* be assembled with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler).
; NASM is available from http://nasm.sourceforge.net/ or
; http://sourceforge.net/project/showfiles.php?group_id=6208
;
; This file contains a fast, not so accurate integer implementation of
; the inverse DCT (Discrete Cosine Transform). The following code is
; based directly on the IJG's original jidctfst.c; see the jidctfst.c
; for more details.
;
; [TAB8]
%include "jsimdext.inc"
%include "jdct.inc"
; --------------------------------------------------------------------------
%define CONST_BITS 8 ; 14 is also OK.
%define PASS1_BITS 2
%if IFAST_SCALE_BITS != PASS1_BITS
%error "'IFAST_SCALE_BITS' must be equal to 'PASS1_BITS'."
%endif
%if CONST_BITS == 8
F_1_082 equ 277 ; FIX(1.082392200)
F_1_414 equ 362 ; FIX(1.414213562)
F_1_847 equ 473 ; FIX(1.847759065)
F_2_613 equ 669 ; FIX(2.613125930)
F_1_613 equ (F_2_613 - 256) ; FIX(2.613125930) - FIX(1)
%else
; NASM cannot do compile-time arithmetic on floating-point constants.
%define DESCALE(x, n) (((x) + (1 << ((n) - 1))) >> (n))
F_1_082 equ DESCALE(1162209775, 30 - CONST_BITS) ; FIX(1.082392200)
F_1_414 equ DESCALE(1518500249, 30 - CONST_BITS) ; FIX(1.414213562)
F_1_847 equ DESCALE(1984016188, 30 - CONST_BITS) ; FIX(1.847759065)
F_2_613 equ DESCALE(2805822602, 30 - CONST_BITS) ; FIX(2.613125930)
F_1_613 equ (F_2_613 - (1 << CONST_BITS)) ; FIX(2.613125930) - FIX(1)
%endif
; --------------------------------------------------------------------------
SECTION SEG_CONST
; PRE_MULTIPLY_SCALE_BITS <= 2 (to avoid overflow)
; CONST_BITS + CONST_SHIFT + PRE_MULTIPLY_SCALE_BITS == 16 (for pmulhw)
%define PRE_MULTIPLY_SCALE_BITS 2
%define CONST_SHIFT (16 - PRE_MULTIPLY_SCALE_BITS - CONST_BITS)
alignz 32
GLOBAL_DATA(jconst_idct_ifast_sse2)
EXTN(jconst_idct_ifast_sse2):
PW_F1414 times 8 dw F_1_414 << CONST_SHIFT
PW_F1847 times 8 dw F_1_847 << CONST_SHIFT
PW_MF1613 times 8 dw -F_1_613 << CONST_SHIFT
PW_F1082 times 8 dw F_1_082 << CONST_SHIFT
PB_CENTERJSAMP times 16 db CENTERJSAMPLE
alignz 32
; --------------------------------------------------------------------------
SECTION SEG_TEXT
BITS 64
;
; Perform dequantization and inverse DCT on one block of coefficients.
;
; GLOBAL(void)
; jsimd_idct_ifast_sse2(void *dct_table, JCOEFPTR coef_block,
; JSAMPARRAY output_buf, JDIMENSION output_col)
;
; r10 = jpeg_component_info *compptr
; r11 = JCOEFPTR coef_block
; r12 = JSAMPARRAY output_buf
; r13d = JDIMENSION output_col
%define original_rbp rbp + 0
%define wk(i) rbp - (WK_NUM - (i)) * SIZEOF_XMMWORD
; xmmword wk[WK_NUM]
%define WK_NUM 2
align 32
GLOBAL_FUNCTION(jsimd_idct_ifast_sse2)
EXTN(jsimd_idct_ifast_sse2):
push rbp
mov rax, rsp ; rax = original rbp
sub rsp, byte 4
and rsp, byte (-SIZEOF_XMMWORD) ; align to 128 bits
mov [rsp], rax
mov rbp, rsp ; rbp = aligned rbp
lea rsp, [wk(0)]
collect_args 4
; ---- Pass 1: process columns from input.
mov rdx, r10 ; quantptr
mov rsi, r11 ; inptr
%ifndef NO_ZERO_COLUMN_TEST_IFAST_SSE2
mov eax, DWORD [DWBLOCK(1,0,rsi,SIZEOF_JCOEF)]
or eax, DWORD [DWBLOCK(2,0,rsi,SIZEOF_JCOEF)]
jnz near .columnDCT
movdqa xmm0, XMMWORD [XMMBLOCK(1,0,rsi,SIZEOF_JCOEF)]
movdqa xmm1, XMMWORD [XMMBLOCK(2,0,rsi,SIZEOF_JCOEF)]
por xmm0, XMMWORD [XMMBLOCK(3,0,rsi,SIZEOF_JCOEF)]
por xmm1, XMMWORD [XMMBLOCK(4,0,rsi,SIZEOF_JCOEF)]
por xmm0, XMMWORD [XMMBLOCK(5,0,rsi,SIZEOF_JCOEF)]
por xmm1, XMMWORD [XMMBLOCK(6,0,rsi,SIZEOF_JCOEF)]
por xmm0, XMMWORD [XMMBLOCK(7,0,rsi,SIZEOF_JCOEF)]
por xmm1, xmm0
packsswb xmm1, xmm1
packsswb xmm1, xmm1
movd eax, xmm1
test rax, rax
jnz short .columnDCT
; -- AC terms all zero
movdqa xmm0, XMMWORD [XMMBLOCK(0,0,rsi,SIZEOF_JCOEF)]
pmullw xmm0, XMMWORD [XMMBLOCK(0,0,rdx,SIZEOF_ISLOW_MULT_TYPE)]
movdqa xmm7, xmm0 ; xmm0=in0=(00 01 02 03 04 05 06 07)
punpcklwd xmm0, xmm0 ; xmm0=(00 00 01 01 02 02 03 03)
punpckhwd xmm7, xmm7 ; xmm7=(04 04 05 05 06 06 07 07)
pshufd xmm6, xmm0, 0x00 ; xmm6=col0=(00 00 00 00 00 00 00 00)
pshufd xmm2, xmm0, 0x55 ; xmm2=col1=(01 01 01 01 01 01 01 01)
pshufd xmm5, xmm0, 0xAA ; xmm5=col2=(02 02 02 02 02 02 02 02)
pshufd xmm0, xmm0, 0xFF ; xmm0=col3=(03 03 03 03 03 03 03 03)
pshufd xmm1, xmm7, 0x00 ; xmm1=col4=(04 04 04 04 04 04 04 04)
pshufd xmm4, xmm7, 0x55 ; xmm4=col5=(05 05 05 05 05 05 05 05)
pshufd xmm3, xmm7, 0xAA ; xmm3=col6=(06 06 06 06 06 06 06 06)
pshufd xmm7, xmm7, 0xFF ; xmm7=col7=(07 07 07 07 07 07 07 07)
movdqa XMMWORD [wk(0)], xmm2 ; wk(0)=col1
movdqa XMMWORD [wk(1)], xmm0 ; wk(1)=col3
jmp near .column_end
%endif
.columnDCT:
; -- Even part
movdqa xmm0, XMMWORD [XMMBLOCK(0,0,rsi,SIZEOF_JCOEF)]
movdqa xmm1, XMMWORD [XMMBLOCK(2,0,rsi,SIZEOF_JCOEF)]
pmullw xmm0, XMMWORD [XMMBLOCK(0,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
pmullw xmm1, XMMWORD [XMMBLOCK(2,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
movdqa xmm2, XMMWORD [XMMBLOCK(4,0,rsi,SIZEOF_JCOEF)]
movdqa xmm3, XMMWORD [XMMBLOCK(6,0,rsi,SIZEOF_JCOEF)]
pmullw xmm2, XMMWORD [XMMBLOCK(4,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
pmullw xmm3, XMMWORD [XMMBLOCK(6,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
movdqa xmm4, xmm0
movdqa xmm5, xmm1
psubw xmm0, xmm2 ; xmm0=tmp11
psubw xmm1, xmm3
paddw xmm4, xmm2 ; xmm4=tmp10
paddw xmm5, xmm3 ; xmm5=tmp13
psllw xmm1, PRE_MULTIPLY_SCALE_BITS
pmulhw xmm1, [rel PW_F1414]
psubw xmm1, xmm5 ; xmm1=tmp12
movdqa xmm6, xmm4
movdqa xmm7, xmm0
psubw xmm4, xmm5 ; xmm4=tmp3
psubw xmm0, xmm1 ; xmm0=tmp2
paddw xmm6, xmm5 ; xmm6=tmp0
paddw xmm7, xmm1 ; xmm7=tmp1
movdqa XMMWORD [wk(1)], xmm4 ; wk(1)=tmp3
movdqa XMMWORD [wk(0)], xmm0 ; wk(0)=tmp2
; -- Odd part
movdqa xmm2, XMMWORD [XMMBLOCK(1,0,rsi,SIZEOF_JCOEF)]
movdqa xmm3, XMMWORD [XMMBLOCK(3,0,rsi,SIZEOF_JCOEF)]
pmullw xmm2, XMMWORD [XMMBLOCK(1,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
pmullw xmm3, XMMWORD [XMMBLOCK(3,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
movdqa xmm5, XMMWORD [XMMBLOCK(5,0,rsi,SIZEOF_JCOEF)]
movdqa xmm1, XMMWORD [XMMBLOCK(7,0,rsi,SIZEOF_JCOEF)]
pmullw xmm5, XMMWORD [XMMBLOCK(5,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
pmullw xmm1, XMMWORD [XMMBLOCK(7,0,rdx,SIZEOF_IFAST_MULT_TYPE)]
movdqa xmm4, xmm2
movdqa xmm0, xmm5
psubw xmm2, xmm1 ; xmm2=z12
psubw xmm5, xmm3 ; xmm5=z10
paddw xmm4, xmm1 ; xmm4=z11
paddw xmm0, xmm3 ; xmm0=z13
movdqa xmm1, xmm5 ; xmm1=z10(unscaled)
psllw xmm2, PRE_MULTIPLY_SCALE_BITS
psllw xmm5, PRE_MULTIPLY_SCALE_BITS
movdqa xmm3, xmm4
psubw xmm4, xmm0
paddw xmm3, xmm0 ; xmm3=tmp7
psllw xmm4, PRE_MULTIPLY_SCALE_BITS
pmulhw xmm4, [rel PW_F1414] ; xmm4=tmp11
; To avoid overflow...
;
; (Original)
; tmp12 = -2.613125930 * z10 + z5;
;
; (This implementation)
; tmp12 = (-1.613125930 - 1) * z10 + z5;
; = -1.613125930 * z10 - z10 + z5;
movdqa xmm0, xmm5
paddw xmm5, xmm2
pmulhw xmm5, [rel PW_F1847] ; xmm5=z5
pmulhw xmm0, [rel PW_MF1613]
pmulhw xmm2, [rel PW_F1082]
psubw xmm0, xmm1
psubw xmm2, xmm5 ; xmm2=tmp10
paddw xmm0, xmm5 ; xmm0=tmp12
; -- Final output stage
psubw xmm0, xmm3 ; xmm0=tmp6
movdqa xmm1, xmm6
movdqa xmm5, xmm7
paddw xmm6, xmm3 ; xmm6=data0=(00 01 02 03 04 05 06 07)
paddw xmm7, xmm0 ; xmm7=data1=(10 11 12 13 14 15 16 17)
psubw xmm1, xmm3 ; xmm1=data7=(70 71 72 73 74 75 76 77)
psubw xmm5, xmm0 ; xmm5=data6=(60 61 62 63 64 65 66 67)
psubw xmm4, xmm0 ; xmm4=tmp5
movdqa xmm3, xmm6 ; transpose coefficients(phase 1)
punpcklwd xmm6, xmm7 ; xmm6=(00 10 01 11 02 12 03 13)
punpckhwd xmm3, xmm7 ; xmm3=(04 14 05 15 06 16 07 17)
movdqa xmm0, xmm5 ; transpose coefficients(phase 1)
punpcklwd xmm5, xmm1 ; xmm5=(60 70 61 71 62 72 63 73)
punpckhwd xmm0, xmm1 ; xmm0=(64 74 65 75 66 76 67 77)
movdqa xmm7, XMMWORD [wk(0)] ; xmm7=tmp2
movdqa xmm1, XMMWORD [wk(1)] ; xmm1=tmp3
movdqa XMMWORD [wk(0)], xmm5 ; wk(0)=(60 70 61 71 62 72 63 73)
movdqa XMMWORD [wk(1)], xmm0 ; wk(1)=(64 74 65 75 66 76 67 77)
paddw xmm2, xmm4 ; xmm2=tmp4
movdqa xmm5, xmm7
movdqa xmm0, xmm1
paddw xmm7, xmm4 ; xmm7=data2=(20 21 22 23 24 25 26 27)
paddw xmm1, xmm2 ; xmm1=data4=(40 41 42 43 44 45 46 47)
psubw xmm5, xmm4 ; xmm5=data5=(50 51 52 53 54 55 56 57)
psubw xmm0, xmm2 ; xmm0=data3=(30 31 32 33 34 35 36 37)
movdqa xmm4, xmm7 ; transpose coefficients(phase 1)
punpcklwd xmm7, xmm0 ; xmm7=(20 30 21 31 22 32 23 33)
punpckhwd xmm4, xmm0 ; xmm4=(24 34 25 35 26 36 27 37)
movdqa xmm2, xmm1 ; transpose coefficients(phase 1)
punpcklwd xmm1, xmm5 ; xmm1=(40 50 41 51 42 52 43 53)
punpckhwd xmm2, xmm5 ; xmm2=(44 54 45 55 46 56 47 57)
movdqa xmm0, xmm3 ; transpose coefficients(phase 2)
punpckldq xmm3, xmm4 ; xmm3=(04 14 24 34 05 15 25 35)
punpckhdq xmm0, xmm4 ; xmm0=(06 16 26 36 07 17 27 37)
movdqa xmm5, xmm6 ; transpose coefficients(phase 2)
punpckldq xmm6, xmm7 ; xmm6=(00 10 20 30 01 11 21 31)
punpckhdq xmm5, xmm7 ; xmm5=(02 12 22 32 03 13 23 33)
movdqa xmm4, XMMWORD [wk(0)] ; xmm4=(60 70 61 71 62 72 63 73)
movdqa xmm7, XMMWORD [wk(1)] ; xmm7=(64 74 65 75 66 76 67 77)
movdqa XMMWORD [wk(0)], xmm3 ; wk(0)=(04 14 24 34 05 15 25 35)
movdqa XMMWORD [wk(1)], xmm0 ; wk(1)=(06 16 26 36 07 17 27 37)
movdqa xmm3, xmm1 ; transpose coefficients(phase 2)
punpckldq xmm1, xmm4 ; xmm1=(40 50 60 70 41 51 61 71)
punpckhdq xmm3, xmm4 ; xmm3=(42 52 62 72 43 53 63 73)
movdqa xmm0, xmm2 ; transpose coefficients(phase 2)
punpckldq xmm2, xmm7 ; xmm2=(44 54 64 74 45 55 65 75)
punpckhdq xmm0, xmm7 ; xmm0=(46 56 66 76 47 57 67 77)
movdqa xmm4, xmm6 ; transpose coefficients(phase 3)
punpcklqdq xmm6, xmm1 ; xmm6=col0=(00 10 20 30 40 50 60 70)
punpckhqdq xmm4, xmm1 ; xmm4=col1=(01 11 21 31 41 51 61 71)
movdqa xmm7, xmm5 ; transpose coefficients(phase 3)
punpcklqdq xmm5, xmm3 ; xmm5=col2=(02 12 22 32 42 52 62 72)
punpckhqdq xmm7, xmm3 ; xmm7=col3=(03 13 23 33 43 53 63 73)
movdqa xmm1, XMMWORD [wk(0)] ; xmm1=(04 14 24 34 05 15 25 35)
movdqa xmm3, XMMWORD [wk(1)] ; xmm3=(06 16 26 36 07 17 27 37)
movdqa XMMWORD [wk(0)], xmm4 ; wk(0)=col1
movdqa XMMWORD [wk(1)], xmm7 ; wk(1)=col3
movdqa xmm4, xmm1 ; transpose coefficients(phase 3)
punpcklqdq xmm1, xmm2 ; xmm1=col4=(04 14 24 34 44 54 64 74)
punpckhqdq xmm4, xmm2 ; xmm4=col5=(05 15 25 35 45 55 65 75)
movdqa xmm7, xmm3 ; transpose coefficients(phase 3)
punpcklqdq xmm3, xmm0 ; xmm3=col6=(06 16 26 36 46 56 66 76)
punpckhqdq xmm7, xmm0 ; xmm7=col7=(07 17 27 37 47 57 67 77)
.column_end:
; -- Prefetch the next coefficient block
prefetchnta [rsi + DCTSIZE2*SIZEOF_JCOEF + 0*32]
prefetchnta [rsi + DCTSIZE2*SIZEOF_JCOEF + 1*32]
prefetchnta [rsi + DCTSIZE2*SIZEOF_JCOEF + 2*32]
prefetchnta [rsi + DCTSIZE2*SIZEOF_JCOEF + 3*32]
; ---- Pass 2: process rows from work array, store into output array.
mov rax, [original_rbp]
mov rdi, r12 ; (JSAMPROW *)
mov eax, r13d
; -- Even part
; xmm6=col0, xmm5=col2, xmm1=col4, xmm3=col6
movdqa xmm2, xmm6
movdqa xmm0, xmm5
psubw xmm6, xmm1 ; xmm6=tmp11
psubw xmm5, xmm3
paddw xmm2, xmm1 ; xmm2=tmp10
paddw xmm0, xmm3 ; xmm0=tmp13
psllw xmm5, PRE_MULTIPLY_SCALE_BITS
pmulhw xmm5, [rel PW_F1414]
psubw xmm5, xmm0 ; xmm5=tmp12
movdqa xmm1, xmm2
movdqa xmm3, xmm6
psubw xmm2, xmm0 ; xmm2=tmp3
psubw xmm6, xmm5 ; xmm6=tmp2
paddw xmm1, xmm0 ; xmm1=tmp0
paddw xmm3, xmm5 ; xmm3=tmp1
movdqa xmm0, XMMWORD [wk(0)] ; xmm0=col1
movdqa xmm5, XMMWORD [wk(1)] ; xmm5=col3
movdqa XMMWORD [wk(0)], xmm2 ; wk(0)=tmp3
movdqa XMMWORD [wk(1)], xmm6 ; wk(1)=tmp2
; -- Odd part
; xmm0=col1, xmm5=col3, xmm4=col5, xmm7=col7
movdqa xmm2, xmm0
movdqa xmm6, xmm4
psubw xmm0, xmm7 ; xmm0=z12
psubw xmm4, xmm5 ; xmm4=z10
paddw xmm2, xmm7 ; xmm2=z11
paddw xmm6, xmm5 ; xmm6=z13
movdqa xmm7, xmm4 ; xmm7=z10(unscaled)
psllw xmm0, PRE_MULTIPLY_SCALE_BITS
psllw xmm4, PRE_MULTIPLY_SCALE_BITS
movdqa xmm5, xmm2
psubw xmm2, xmm6
paddw xmm5, xmm6 ; xmm5=tmp7
psllw xmm2, PRE_MULTIPLY_SCALE_BITS
pmulhw xmm2, [rel PW_F1414] ; xmm2=tmp11
; To avoid overflow...
;
; (Original)
; tmp12 = -2.613125930 * z10 + z5;
;
; (This implementation)
; tmp12 = (-1.613125930 - 1) * z10 + z5;
; = -1.613125930 * z10 - z10 + z5;
movdqa xmm6, xmm4
paddw xmm4, xmm0
pmulhw xmm4, [rel PW_F1847] ; xmm4=z5
pmulhw xmm6, [rel PW_MF1613]
pmulhw xmm0, [rel PW_F1082]
psubw xmm6, xmm7
psubw xmm0, xmm4 ; xmm0=tmp10
paddw xmm6, xmm4 ; xmm6=tmp12
; -- Final output stage
psubw xmm6, xmm5 ; xmm6=tmp6
movdqa xmm7, xmm1
movdqa xmm4, xmm3
paddw xmm1, xmm5 ; xmm1=data0=(00 10 20 30 40 50 60 70)
paddw xmm3, xmm6 ; xmm3=data1=(01 11 21 31 41 51 61 71)
psraw xmm1, (PASS1_BITS+3) ; descale
psraw xmm3, (PASS1_BITS+3) ; descale
psubw xmm7, xmm5 ; xmm7=data7=(07 17 27 37 47 57 67 77)
psubw xmm4, xmm6 ; xmm4=data6=(06 16 26 36 46 56 66 76)
psraw xmm7, (PASS1_BITS+3) ; descale
psraw xmm4, (PASS1_BITS+3) ; descale
psubw xmm2, xmm6 ; xmm2=tmp5
packsswb xmm1, xmm4 ; xmm1=(00 10 20 30 40 50 60 70 06 16 26 36 46 56 66 76)
packsswb xmm3, xmm7 ; xmm3=(01 11 21 31 41 51 61 71 07 17 27 37 47 57 67 77)
movdqa xmm5, XMMWORD [wk(1)] ; xmm5=tmp2
movdqa xmm6, XMMWORD [wk(0)] ; xmm6=tmp3
paddw xmm0, xmm2 ; xmm0=tmp4
movdqa xmm4, xmm5
movdqa xmm7, xmm6
paddw xmm5, xmm2 ; xmm5=data2=(02 12 22 32 42 52 62 72)
paddw xmm6, xmm0 ; xmm6=data4=(04 14 24 34 44 54 64 74)
psraw xmm5, (PASS1_BITS+3) ; descale
psraw xmm6, (PASS1_BITS+3) ; descale
psubw xmm4, xmm2 ; xmm4=data5=(05 15 25 35 45 55 65 75)
psubw xmm7, xmm0 ; xmm7=data3=(03 13 23 33 43 53 63 73)
psraw xmm4, (PASS1_BITS+3) ; descale
psraw xmm7, (PASS1_BITS+3) ; descale
movdqa xmm2, [rel PB_CENTERJSAMP] ; xmm2=[rel PB_CENTERJSAMP]
packsswb xmm5, xmm6 ; xmm5=(02 12 22 32 42 52 62 72 04 14 24 34 44 54 64 74)
packsswb xmm7, xmm4 ; xmm7=(03 13 23 33 43 53 63 73 05 15 25 35 45 55 65 75)
paddb xmm1, xmm2
paddb xmm3, xmm2
paddb xmm5, xmm2
paddb xmm7, xmm2
movdqa xmm0, xmm1 ; transpose coefficients(phase 1)
punpcklbw xmm1, xmm3 ; xmm1=(00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71)
punpckhbw xmm0, xmm3 ; xmm0=(06 07 16 17 26 27 36 37 46 47 56 57 66 67 76 77)
movdqa xmm6, xmm5 ; transpose coefficients(phase 1)
punpcklbw xmm5, xmm7 ; xmm5=(02 03 12 13 22 23 32 33 42 43 52 53 62 63 72 73)
punpckhbw xmm6, xmm7 ; xmm6=(04 05 14 15 24 25 34 35 44 45 54 55 64 65 74 75)
movdqa xmm4, xmm1 ; transpose coefficients(phase 2)
punpcklwd xmm1, xmm5 ; xmm1=(00 01 02 03 10 11 12 13 20 21 22 23 30 31 32 33)
punpckhwd xmm4, xmm5 ; xmm4=(40 41 42 43 50 51 52 53 60 61 62 63 70 71 72 73)
movdqa xmm2, xmm6 ; transpose coefficients(phase 2)
punpcklwd xmm6, xmm0 ; xmm6=(04 05 06 07 14 15 16 17 24 25 26 27 34 35 36 37)
punpckhwd xmm2, xmm0 ; xmm2=(44 45 46 47 54 55 56 57 64 65 66 67 74 75 76 77)
movdqa xmm3, xmm1 ; transpose coefficients(phase 3)
punpckldq xmm1, xmm6 ; xmm1=(00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17)
punpckhdq xmm3, xmm6 ; xmm3=(20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37)
movdqa xmm7, xmm4 ; transpose coefficients(phase 3)
punpckldq xmm4, xmm2 ; xmm4=(40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57)
punpckhdq xmm7, xmm2 ; xmm7=(60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77)
pshufd xmm5, xmm1, 0x4E ; xmm5=(10 11 12 13 14 15 16 17 00 01 02 03 04 05 06 07)
pshufd xmm0, xmm3, 0x4E ; xmm0=(30 31 32 33 34 35 36 37 20 21 22 23 24 25 26 27)
pshufd xmm6, xmm4, 0x4E ; xmm6=(50 51 52 53 54 55 56 57 40 41 42 43 44 45 46 47)
pshufd xmm2, xmm7, 0x4E ; xmm2=(70 71 72 73 74 75 76 77 60 61 62 63 64 65 66 67)
mov rdx, JSAMPROW [rdi+0*SIZEOF_JSAMPROW]
mov rsi, JSAMPROW [rdi+2*SIZEOF_JSAMPROW]
movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm1
movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm3
mov rdx, JSAMPROW [rdi+4*SIZEOF_JSAMPROW]
mov rsi, JSAMPROW [rdi+6*SIZEOF_JSAMPROW]
movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm4
movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm7
mov rdx, JSAMPROW [rdi+1*SIZEOF_JSAMPROW]
mov rsi, JSAMPROW [rdi+3*SIZEOF_JSAMPROW]
movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm5
movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm0
mov rdx, JSAMPROW [rdi+5*SIZEOF_JSAMPROW]
mov rsi, JSAMPROW [rdi+7*SIZEOF_JSAMPROW]
movq XMM_MMWORD [rdx+rax*SIZEOF_JSAMPLE], xmm6
movq XMM_MMWORD [rsi+rax*SIZEOF_JSAMPLE], xmm2
uncollect_args 4
mov rsp, rbp ; rsp <- aligned rbp
pop rsp ; rsp <- original rbp
pop rbp
ret
ret
; For some reason, the OS X linker does not honor the request to align the
; segment unless we do this.
align 32
|
//
// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
#pragma once
#include <arm_compute/core/CL/ICLTensor.h>
#include <arm_compute/core/ITensorInfo.h>
namespace armnn
{
class ICLTensorProxy : public arm_compute::ICLTensor
{
public:
ICLTensorProxy(arm_compute::ICLTensor* iclTensor) : m_DelegateTensor(iclTensor) {}
ICLTensorProxy(const ICLTensorProxy&) = delete;
ICLTensorProxy& operator=(const ICLTensorProxy&) = delete;
ICLTensorProxy(ICLTensorProxy&&) = default;
ICLTensorProxy& operator=(ICLTensorProxy&&) = default;
void set(arm_compute::ICLTensor* iclTensor)
{
if(iclTensor != nullptr)
{
m_DelegateTensor = iclTensor;
}
}
// Inherited methods overridden:
arm_compute::ITensorInfo* info() const
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->info();
}
arm_compute::ITensorInfo* info()
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->info();
}
uint8_t* buffer() const
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->buffer();
}
arm_compute::CLQuantization quantization() const
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->quantization();
}
const cl::Buffer& cl_buffer() const
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->cl_buffer();
}
protected:
uint8_t* do_map(cl::CommandQueue& q, bool blocking)
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
m_DelegateTensor->map(q, blocking);
return m_DelegateTensor->buffer();
}
void do_unmap(cl::CommandQueue& q)
{
ARM_COMPUTE_ERROR_ON(m_DelegateTensor == nullptr);
return m_DelegateTensor->unmap(q);
}
private:
arm_compute::ICLTensor* m_DelegateTensor{ nullptr };
};
} //namespace armnn |
// bslstl_stringstream.t.cpp -*-C++-*-
#include <bslstl_stringstream.h>
#include <bslstl_allocator.h>
#include <bslstl_string.h>
#include <bslma_allocator.h>
#include <bslma_default.h>
#include <bslma_defaultallocatorguard.h>
#include <bslma_testallocator.h>
#include <bslma_testallocatormonitor.h>
#include <bslmf_assert.h>
#include <bsls_bsltestutil.h>
#include <bsls_platform.h>
#include <bsltf_stdtestallocator.h>
#include <ios>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
//=============================================================================
// TEST PLAN
//-----------------------------------------------------------------------------
// Overview
// --------
// 'bsl::basic_stringstream' IS-A 'std::basic_iostream' that uses
// 'bsl::basic_stringbuf' as an input/output buffer. All of the functionality
// and state of a 'bsl::basic_stringstream' object are provided by base class
// sub-objects. Therefore, it is not necessary to test all of the
// functionality derived from 'std::basic_iostream'. It is sufficient to test
// that the various constructors initialize object state as expected, and that
// the manipulator and two accessors, all of which are trivial, work as
// expected.
//
// Note that the 'str' accessor may use the default allocator since it returns
// its string result by value; therefore, tests of allocator usage must take
// this into account.
//-----------------------------------------------------------------------------
// CREATORS
// [ 2] stringstream(const A& a = A());
// [ 4] stringstream(openmode mask, const A& a = A());
// [ 5] stringstream(const STRING& s, const A& a = A());
// [ 6] stringstream(const STRING& s, openmode mask, const A& a = A());
//
// MANIPULATORS
// [ 3] void str(const StringType& value);
//
// ACCESSORS
// [ 3] StringType str() const;
// [ 2] StreamBufType *rdbuf() const;
// ----------------------------------------------------------------------------
// [ 1] BREATHING TEST
// [ 8] USAGE EXAMPLE
// [ 7] CONCERN: Standard allocator can be used
// [ *] CONCERN: In no case does memory come from the global allocator.
//=============================================================================
// STANDARD BDE ASSERT TEST MACRO
//-----------------------------------------------------------------------------
// NOTE: THIS IS A LOW-LEVEL COMPONENT AND MAY NOT USE ANY C++ LIBRARY
// FUNCTIONS, INCLUDING IOSTREAMS.
static int testStatus = 0;
namespace {
void aSsErT(bool b, const char *s, int i) {
if (b) {
printf("Error " __FILE__ "(%d): %s (failed)\n", i, s);
if (testStatus >= 0 && testStatus <= 100) ++testStatus;
}
}
} // close unnamed namespace
//=============================================================================
// STANDARD BDE TEST DRIVER MACROS
//-----------------------------------------------------------------------------
#define ASSERT BSLS_BSLTESTUTIL_ASSERT
#define LOOP_ASSERT BSLS_BSLTESTUTIL_LOOP_ASSERT
#define LOOP0_ASSERT BSLS_BSLTESTUTIL_LOOP0_ASSERT
#define LOOP1_ASSERT BSLS_BSLTESTUTIL_LOOP1_ASSERT
#define LOOP2_ASSERT BSLS_BSLTESTUTIL_LOOP2_ASSERT
#define LOOP3_ASSERT BSLS_BSLTESTUTIL_LOOP3_ASSERT
#define LOOP4_ASSERT BSLS_BSLTESTUTIL_LOOP4_ASSERT
#define LOOP5_ASSERT BSLS_BSLTESTUTIL_LOOP5_ASSERT
#define LOOP6_ASSERT BSLS_BSLTESTUTIL_LOOP6_ASSERT
#define ASSERTV BSLS_BSLTESTUTIL_ASSERTV
#define Q BSLS_BSLTESTUTIL_Q // Quote identifier literally.
#define P BSLS_BSLTESTUTIL_P // Print identifier and value.
#define P_ BSLS_BSLTESTUTIL_P_ // P(X) without '\n'.
#define T_ BSLS_BSLTESTUTIL_T_ // Print a tab (w/o newline).
#define L_ BSLS_BSLTESTUTIL_L_ // current Line number
#define RUN_EACH_TYPE BSLTF_TEMPLATETESTFACILITY_RUN_EACH_TYPE
// ============================================================================
// NEGATIVE-TEST MACRO ABBREVIATIONS
// ----------------------------------------------------------------------------
#define ASSERT_SAFE_PASS(EXPR) BSLS_ASSERTTEST_ASSERT_SAFE_PASS(EXPR)
#define ASSERT_SAFE_FAIL(EXPR) BSLS_ASSERTTEST_ASSERT_SAFE_FAIL(EXPR)
#define ASSERT_PASS(EXPR) BSLS_ASSERTTEST_ASSERT_PASS(EXPR)
#define ASSERT_FAIL(EXPR) BSLS_ASSERTTEST_ASSERT_FAIL(EXPR)
#define ASSERT_OPT_PASS(EXPR) BSLS_ASSERTTEST_ASSERT_OPT_PASS(EXPR)
#define ASSERT_OPT_FAIL(EXPR) BSLS_ASSERTTEST_ASSERT_OPT_FAIL(EXPR)
// ============================================================================
// GLOBAL TEST VALUES
// ----------------------------------------------------------------------------
static bool verbose;
static bool veryVerbose;
static bool veryVeryVerbose;
static bool veryVeryVeryVerbose;
//=============================================================================
// GLOBAL TYPEDEFS/CONSTANTS FOR TESTING
//-----------------------------------------------------------------------------
typedef bsl::stringstream Obj;
typedef bsl::wstringstream WObj;
typedef std::ios_base IosBase;
typedef IosBase::openmode Mode;
// ============================================================================
// GLOBAL TEST DATA
// ----------------------------------------------------------------------------
// Define the length of a 'bsl::string' value long enough to ensure dynamic
// memory allocation.
const int LENGTH_OF_SUFFICIENTLY_LONG_STRING =
#ifdef BSLS_PLATFORM_CPU_32_BIT
33;
#else // 64_BIT
65;
#endif
BSLMF_ASSERT(LENGTH_OF_SUFFICIENTLY_LONG_STRING >
static_cast<int>(sizeof(bsl::string)));
struct StrlenDataRow {
int d_line; // source line number
int d_length; // string length
char d_mem; // expected allocation: 'Y', 'N', '?'
};
static
const StrlenDataRow STRLEN_DATA[] =
{
//LINE LENGTH MEM
//---- ---------------------------------- ---
{ L_, 0, 'N' },
{ L_, 1, 'N' },
{ L_, LENGTH_OF_SUFFICIENTLY_LONG_STRING, 'Y' }
};
const int NUM_STRLEN_DATA = sizeof STRLEN_DATA / sizeof *STRLEN_DATA;
struct OpenModeDataRow {
int d_line; // source line number
Mode d_mode;
};
static
const OpenModeDataRow OPENMODE_DATA[] =
{
//LINE OPENMODE
//---- ------------------------------------------
{ L_, IosBase::in },
{ L_, IosBase::out },
{ L_, IosBase::in | IosBase::out },
{ L_, IosBase::ate },
{ L_, IosBase::in | IosBase::ate },
{ L_, IosBase::out | IosBase::ate },
{ L_, IosBase::in | IosBase::out | IosBase::ate }
};
const int NUM_OPENMODE_DATA = sizeof OPENMODE_DATA / sizeof *OPENMODE_DATA;
//=============================================================================
// TEST FACILITIES
//-----------------------------------------------------------------------------
namespace {
template <class StringT>
void loadString(StringT *value, int length)
// Load into the specified 'value' a character string having the specified
// 'length'. The behavior is undefined unless 'length >= 0'.
{
value->resize(length);
for (int i = 0; i < length; ++i) {
(*value)[i] =
static_cast<typename StringT::value_type>('a' + (i % 26));
}
}
template <class StreamT, class BaseT, class StringT, class CharT>
void testCase2()
{
// ------------------------------------------------------------------------
// DEFAULT CTOR
// Ensure that we can use the default constructor to create an object
// having the expected default-constructed state, and use the primary
// manipulator to put that object into a state relevant for testing.
//
// Concerns:
//: 1 An object created with the constructor under test has the specified
//: allocator.
//:
//: 2 The constructor allocates no memory.
//:
//: 3 Excepting the 'str' accessor, any memory allocation is from the
//: object allocator.
//:
//: 4 Excepting the 'str' accessor, there is no temporary allocation from
//: any allocator.
//:
//: 5 The 'rdbuf' accessor returns the expected (non-null) value.
//:
//: 6 The string buffer is initially empty.
//:
//: 7 The object is created with mode 'ios_base::in | ios_base::out' in
//: effect.
//:
//: 8 Every object releases any allocated memory at destruction.
//
// Plan:
// The table-driven technique is used.
//
//: 1 For each value, 'S', in a small set of string values: (C-1..8)
//:
//: 1 For each allocator configuration: (C-1..8)
//:
//: 1 Create an object using the default constructor and verify no
//: memory is allocated. (C-2)
//:
//: 2 Use the 'rdbuf' accessor to verify that it returns the expected
//: (non-null) value. (C-5)
//:
//: 3 Use the 'str' accessor to verify the initial value of the buffer
//: (empty). (C-6)
//:
//: 4 For non-empty string values, invoke 'str(S)' and verify that the
//: correct allocator was used (if memory allocation is expected).
//: Additionally, verify the new value of the string buffer.
//: (C-1, 3)
//:
//: 5 Stream a character to the object (using the inherited '<<'
//: operator), then stream a character from the object (using the
//: inherited '>>' operator); verify that the results are as
//: expected. (C-7)
//:
//: 6 Verify no temporary memory is allocated from the object allocator
//: when supplied. (C-4)
//:
//: 7 Delete the object and verify all memory is deallocated. (C-8)
//
// Testing:
// stringstream(const A& a = A());
// StreamBufType *rdbuf() const;
// ------------------------------------------------------------------------
if (verbose) printf("\nDEFAULT CTOR"
"\n============\n");
using namespace BloombergLP;
for (int ti = 0; ti < NUM_STRLEN_DATA; ++ti) {
const int LENGTH = STRLEN_DATA[ti].d_length;
const char MEM = STRLEN_DATA[ti].d_mem;
for (char cfg = 'a'; cfg <= 'c'; ++cfg) {
const char CONFIG = cfg; // how we specify the allocator
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::TestAllocator fa("footprint", veryVeryVeryVerbose);
bslma::TestAllocator sa("supplied", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
if (veryVerbose) {
printf("\nTesting with various allocator configurations.\n");
}
StreamT *objPtr;
bslma::TestAllocator *objAllocatorPtr;
switch (CONFIG) {
case 'a': {
objPtr = new (fa) StreamT();
objAllocatorPtr = &da;
} break;
case 'b': {
objPtr = new (fa) StreamT(typename StreamT::allocator_type(0));
objAllocatorPtr = &da;
} break;
case 'c': {
objPtr = new (fa) StreamT(&sa);
objAllocatorPtr = &sa;
} break;
default: {
ASSERTV(CONFIG, !"Bad allocator config.");
return;
} break;
}
StreamT& mX = *objPtr; const StreamT& X = mX;
const BaseT& B = X;
bslma::TestAllocator& oa = *objAllocatorPtr;
bslma::TestAllocator& noa = 'c' != CONFIG ? sa : da;
// Verify no allocation from the object/non-object allocators.
ASSERTV(CONFIG, oa.numBlocksTotal(), 0 == oa.numBlocksTotal());
ASSERTV(CONFIG, noa.numBlocksTotal(), 0 == noa.numBlocksTotal());
ASSERTV(CONFIG, X.rdbuf());
ASSERTV(CONFIG, X.rdbuf() == B.rdbuf());
ASSERTV(CONFIG, X.str().empty());
bslma::TestAllocator scratch("scratch", veryVeryVeryVerbose);
StringT mS(&scratch); const StringT& S = mS;
loadString(&mS, LENGTH);
if (LENGTH > 0) {
bslma::TestAllocatorMonitor oam(&oa);
mX.str(S);
ASSERTV(CONFIG, ('Y' == MEM) == oam.isInUseUp());
oam.reset();
ASSERTV(CONFIG, X.str() == S);
if ('c' == CONFIG) {
ASSERTV(CONFIG, oam.isInUseSame());
}
}
mX << 'X';
if (S.empty()) { mS.resize(1); }
mS[0] = static_cast<CharT>('X');
ASSERTV(CONFIG, X.str() == S);
CharT c = 'Z';
mX >> c;
ASSERTV(CONFIG, 'X' == c);
ASSERTV(CONFIG, X.str() == S);
// Verify no temporary memory is allocated from the object
// allocator when supplied.
if ('c' == CONFIG) {
ASSERTV(CONFIG, oa.numBlocksTotal(), oa.numBlocksInUse(),
oa.numBlocksTotal() == oa.numBlocksInUse());
}
// Reclaim dynamically allocated object under test.
fa.deleteObject(objPtr);
// Verify all memory is released on object destruction.
ASSERTV(CONFIG, fa.numBlocksInUse(), 0 == fa.numBlocksInUse());
ASSERTV(CONFIG, oa.numBlocksInUse(), 0 == oa.numBlocksInUse());
ASSERTV(CONFIG, noa.numBlocksInUse(), 0 == noa.numBlocksInUse());
}
}
}
template <class StreamT, class BaseT, class StringT, class CharT>
void testCase3()
{
// ------------------------------------------------------------------------
// 'str' MANIPULATOR AND 'str' ACCESSOR
// Ensure that the 'str' manipulator and 'str' accessor work as expected.
//
// Concerns:
//: 1 The 'str' manipulator has the expected effect on the contents of the
//: string buffer.
//:
//: 2 The 'str' accessor correctly reports the contents of the string
//: buffer.
//
// Plan:
// The table-driven technique is used.
//
//: 1 For each value, 'S', in a small set of string values: (C-1..2)
//:
//: 1 Create an object using the default constructor (tested in case 2).
//:
//: 2 Use the 'str' accessor to verify the initial value of the buffer
//: (empty). (C-2)
//:
//: 3 Use the 'str' manipulator to set the buffer value to 'S'. (C-1)
//:
//: 4 Use the 'str' accessor to verify the new expected value of the
//: string buffer. (C-2)
//:
//: 5 For each value, 'T', in a small set of string values: (C-1..2)
//:
//: 1 Use the 'str' manipulator to set the buffer value to 'T'. (C-1)
//:
//: 2 Use the 'str' accessor to verify the new expected value of the
//: string buffer. (C-2)
//
// Testing:
// void str(const StringType& value);
// StringType str() const;
// ------------------------------------------------------------------------
if (verbose) printf("\n'str' MANIPULATOR AND 'str' ACCESSOR"
"\n====================================\n");
using namespace BloombergLP;
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
for (int ti = 0; ti < NUM_STRLEN_DATA; ++ti) {
const int LENGTH_TI = STRLEN_DATA[ti].d_length;
bslma::TestAllocator sa("supplied", veryVeryVeryVerbose);
StreamT mX(&sa); const StreamT& X = mX; ASSERT(X.str().empty());
StringT mS(&da); const StringT& S = mS;
loadString(&mS, LENGTH_TI);
mX.str(S); ASSERT(X.str() == S);
for (int tj = 0; tj < NUM_STRLEN_DATA; ++tj) {
const int LENGTH_TJ = STRLEN_DATA[tj].d_length;
StringT mT(&da); const StringT& T = mT;
loadString(&mT, LENGTH_TJ);
mX.str(T); ASSERT(X.str() == T);
}
}
}
template <class StreamT, class BaseT, class StringT, class CharT>
void testCase4()
{
// ------------------------------------------------------------------------
// OPENMODE CTOR
// Ensure that an object created using the constructor that takes an
// 'openmode' mask has the expected initial state, and use the primary
// manipulator to put that object into a state relevant for testing.
//
// Concerns:
//: 1 An object created with the constructor under test has the specified
//: allocator.
//:
//: 2 The constructor allocates no memory.
//:
//: 3 Excepting the 'str' accessor, any memory allocation is from the
//: object allocator.
//:
//: 4 Excepting the 'str' accessor, there is no temporary allocation from
//: any allocator.
//:
//: 5 The 'rdbuf' accessor returns the expected (non-null) value.
//:
//: 6 The string buffer is initially empty.
//:
//: 7 The object is created with the mode as specified in 'modeBitMask' in
//: effect.
//:
//: 8 Every object releases any allocated memory at destruction.
//
// Plan:
// The table-driven technique is used.
//
//: 1 For each value, 'M', in a representative set of mode bit-masks:
//: (C-1..8)
//:
//: 1 For each value, 'S', in a small set of string values: (C-1..8)
//:
//: 1 For each allocator configuration: (C-1..8)
//:
//: 1 Create an object, supplying 'M' to the constructor, and verify
//: no memory is allocated. (C-2)
//:
//: 2 Use the 'rdbuf' accessor to verify that it returns the expected
//: (non-null) value. (C-5)
//:
//: 3 Use the 'str' accessor to verify the initial value of the
//: buffer (empty). (C-6)
//:
//: 4 For non-empty string values, invoke 'str(S)' and verify that
//: the correct allocator was used (if memory allocation is
//: expected). Additionally, verify the new value of the string
//: buffer. (C-1, 3)
//:
//: 5 Stream a character to the object (using the inherited '<<'
//: operator), then stream a character from the object (using the
//: inherited '>>' operator); verify that the results are as
//: expected. (C-7)
//:
//: 6 Verify no temporary memory is allocated from the object
//: allocator when supplied. (C-4)
//:
//: 7 Delete the object and verify all memory is deallocated. (C-8)
//
// Testing:
// stringstream(openmode mask, const A& a = A());
// ------------------------------------------------------------------------
if (verbose) printf("\nOPENMODE CTOR"
"\n=============\n");
using namespace BloombergLP;
for (int ti = 0; ti < NUM_OPENMODE_DATA; ++ti) {
const Mode MODE = OPENMODE_DATA[ti].d_mode;
for (int tj = 0; tj < NUM_STRLEN_DATA; ++tj) {
const int LENGTH = STRLEN_DATA[tj].d_length;
const char MEM = STRLEN_DATA[tj].d_mem;
for (char cfg = 'a'; cfg <= 'c'; ++cfg) {
const char CONFIG = cfg; // how we specify the allocator
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::TestAllocator fa("footprint", veryVeryVeryVerbose);
bslma::TestAllocator sa("supplied", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
if (veryVerbose) {
printf(
"\nTesting with various allocator configurations.\n");
}
StreamT *objPtr;
bslma::TestAllocator *objAllocatorPtr;
switch (CONFIG) {
case 'a': {
objPtr = new (fa) StreamT(MODE);
objAllocatorPtr = &da;
} break;
case 'b': {
objPtr = new (fa) StreamT(
MODE,
typename StreamT::allocator_type(0));
objAllocatorPtr = &da;
} break;
case 'c': {
objPtr = new (fa) StreamT(MODE, &sa);
objAllocatorPtr = &sa;
} break;
default: {
ASSERTV(CONFIG, !"Bad allocator config.");
return;
} break;
}
StreamT& mX = *objPtr; const StreamT& X = mX;
const BaseT& B = X;
bslma::TestAllocator& oa = *objAllocatorPtr;
bslma::TestAllocator& noa = 'c' != CONFIG ? sa : da;
// Verify no allocation from the object/non-object allocators.
ASSERTV(CONFIG, oa.numBlocksTotal(),
0 == oa.numBlocksTotal());
ASSERTV(CONFIG, noa.numBlocksTotal(),
0 == noa.numBlocksTotal());
ASSERTV(CONFIG, X.rdbuf());
ASSERTV(CONFIG, X.rdbuf() == B.rdbuf());
ASSERTV(CONFIG, X.str().empty());
bslma::TestAllocator scratch("scratch", veryVeryVeryVerbose);
StringT mS(&scratch); const StringT& S = mS;
loadString(&mS, LENGTH);
if (LENGTH > 0) {
bslma::TestAllocatorMonitor oam(&oa);
mX.str(S);
ASSERTV(CONFIG, ('Y' == MEM) == oam.isInUseUp());
oam.reset();
ASSERTV(CONFIG, X.str() == S);
if ('c' == CONFIG) {
ASSERTV(CONFIG, oam.isInUseSame());
}
}
if ((MODE & IosBase::out) || !(MODE & IosBase::in)) {
mX << 'X'; // '>>' test is perturbed if 'out' not set
}
if (MODE & IosBase::out) {
if (MODE & IosBase::ate) {
mS.push_back(static_cast<CharT>('X'));
}
else {
if (S.empty()) { mS.resize(1); }
mS[0] = static_cast<CharT>('X');
}
}
ASSERTV(CONFIG, X.str() == S);
CharT c = 'Z';
mX >> c;
CharT EXPECTED;
if (MODE & IosBase::in) {
EXPECTED = (0 == LENGTH) && !(MODE & IosBase::out)
? 'Z'
: S[0];
}
else {
EXPECTED = 'Z';
}
ASSERTV(CONFIG, EXPECTED == c);
ASSERTV(CONFIG, X.str() == S);
// Verify no temporary memory is allocated from the object
// allocator when supplied.
if ('c' == CONFIG && !(MODE & IosBase::ate)) {
ASSERTV(CONFIG, oa.numBlocksTotal(), oa.numBlocksInUse(),
oa.numBlocksTotal() == oa.numBlocksInUse());
}
// Reclaim dynamically allocated object under test.
fa.deleteObject(objPtr);
// Verify all memory is released on object destruction.
ASSERTV(CONFIG, fa.numBlocksInUse(),
0 == fa.numBlocksInUse());
ASSERTV(CONFIG, oa.numBlocksInUse(),
0 == oa.numBlocksInUse());
ASSERTV(CONFIG, noa.numBlocksInUse(),
0 == noa.numBlocksInUse());
}
}
}
}
template <class StreamT, class BaseT, class StringT, class CharT>
void testCase5()
{
// ------------------------------------------------------------------------
// STRING CTOR
// Ensure that an object created using the constructor that takes a
// string value has the expected initial state.
//
// Concerns:
//: 1 An object created with the constructor under test has the specified
//: allocator.
//:
//: 2 The constructor allocates memory if and only if the string supplied
//: at construction is sufficiently long to guarantee memory allocation.
//:
//: 3 Excepting the 'str' accessor, any memory allocation is from the
//: object allocator.
//:
//: 4 Excepting the 'str' accessor, there is no temporary allocation from
//: any allocator.
//:
//: 5 The 'rdbuf' accessor returns the expected (non-null) value.
//:
//: 6 The string buffer initially has the same value as that of the string
//: supplied at construction.
//:
//: 7 The object is created with mode 'ios_base::in | ios_base::out' in
//: effect.
//:
//: 8 Every object releases any allocated memory at destruction.
//
// Plan:
// The table-driven technique is used.
//
//: 1 For each value, 'S', in a small set of string values: (C-1..8)
//:
//: 1 For each allocator configuration: (C-1..8)
//:
//: 1 Create an object, supplying 'S' to the constructor, and verify
//: that the correct allocator was used (if memory allocation is
//: expected). Additionally, verify the initial value of the string
//: buffer. (C-1..3, 6)
//:
//: 2 Use the 'rdbuf' accessor to verify that it returns the expected
//: (non-null) value. (C-5)
//:
//: 3 Stream a character to the object (using the inherited '<<'
//: operator), then stream a character from the object (using the
//: inherited '>>' operator); verify that the results are as
//: expected. (C-7)
//:
//: 4 Verify no temporary memory is allocated from the object allocator
//: when supplied. (C-4)
//:
//: 5 Delete the object and verify all memory is deallocated. (C-8)
//
// Testing:
// stringstream(const STRING& s, const A& a = A());
// ------------------------------------------------------------------------
if (verbose) printf("\nSTRING CTOR"
"\n===========\n");
using namespace BloombergLP;
for (int ti = 0; ti < NUM_STRLEN_DATA; ++ti) {
const int LENGTH = STRLEN_DATA[ti].d_length;
const char MEM = STRLEN_DATA[ti].d_mem;
for (char cfg = 'a'; cfg <= 'c'; ++cfg) {
const char CONFIG = cfg; // how we specify the allocator
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::TestAllocator fa("footprint", veryVeryVeryVerbose);
bslma::TestAllocator sa("supplied", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
if (veryVerbose) {
printf("\nTesting with various allocator configurations.\n");
}
StreamT *objPtr;
bslma::TestAllocator *objAllocatorPtr;
bslma::TestAllocator scratch("scratch", veryVeryVeryVerbose);
StringT mS(&scratch); const StringT& S = mS;
loadString(&mS, LENGTH);
switch (CONFIG) {
case 'a': {
objPtr = new (fa) StreamT(S);
objAllocatorPtr = &da;
} break;
case 'b': {
objPtr = new (fa) StreamT(S,
typename StreamT::allocator_type(0));
objAllocatorPtr = &da;
} break;
case 'c': {
objPtr = new (fa) StreamT(S, &sa);
objAllocatorPtr = &sa;
} break;
default: {
ASSERTV(CONFIG, !"Bad allocator config.");
return;
} break;
}
StreamT& mX = *objPtr; const StreamT& X = mX;
const BaseT& B = X;
bslma::TestAllocator& oa = *objAllocatorPtr;
bslma::TestAllocator& noa = 'c' != CONFIG ? sa : da;
// Verify allocations from the object/non-object allocators.
if ('N' == MEM) {
ASSERTV(CONFIG, oa.numBlocksTotal(),
0 == oa.numBlocksTotal());
ASSERTV(CONFIG, noa.numBlocksTotal(),
0 == noa.numBlocksTotal());
}
else {
ASSERTV(CONFIG, oa.numBlocksTotal(),
0 != oa.numBlocksTotal());
}
ASSERTV(CONFIG, X.rdbuf());
ASSERTV(CONFIG, X.rdbuf() == B.rdbuf());
ASSERTV(CONFIG, X.str() == S);
mX << 'X';
if (S.empty()) { mS.resize(1); }
mS[0] = static_cast<CharT>('X');
ASSERTV(CONFIG, X.str() == S);
CharT c = 'Z';
mX >> c;
ASSERTV(CONFIG, 'X' == c);
ASSERTV(CONFIG, X.str() == S);
// Verify no temporary memory is allocated from the object
// allocator when supplied.
if ('c' == CONFIG) {
ASSERTV(CONFIG, oa.numBlocksTotal(), oa.numBlocksInUse(),
oa.numBlocksTotal() == oa.numBlocksInUse());
}
// Reclaim dynamically allocated object under test.
fa.deleteObject(objPtr);
// Verify all memory is released on object destruction.
ASSERTV(CONFIG, fa.numBlocksInUse(), 0 == fa.numBlocksInUse());
ASSERTV(CONFIG, oa.numBlocksInUse(), 0 == oa.numBlocksInUse());
ASSERTV(CONFIG, noa.numBlocksInUse(), 0 == noa.numBlocksInUse());
}
}
}
template <class StreamT, class BaseT, class StringT, class CharT>
void testCase6()
{
// ------------------------------------------------------------------------
// STRING & OPENMODE CTOR
// Ensure that an object created using the constructor that takes a
// string value and 'openmode' mask has the expected initial state.
//
// Concerns:
//: 1 An object created with the constructor under test has the specified
//: allocator.
//:
//: 2 The constructor allocates memory if and only if the string supplied
//: at construction is sufficiently long to guarantee memory allocation.
//:
//: 3 Excepting the 'str' accessor, any memory allocation is from the
//: object allocator.
//:
//: 4 Excepting the 'str' accessor, there is no temporary allocation from
//: any allocator.
//:
//: 5 The 'rdbuf' accessor returns the expected (non-null) value.
//:
//: 6 The string buffer initially has the same value as that of the string
//: supplied at construction.
//:
//: 7 The object is created with the mode as specified in 'modeBitMask' in
//: effect.
//:
//: 8 Every object releases any allocated memory at destruction.
//
// Plan:
// The table-driven technique is used.
//
//: 1 For each value, 'M', in a representative set of mode bit-masks:
//: (C-1..8)
//:
//: 1 For each value, 'S', in a small set of string values: (C-1..8)
//:
//: 1 For each allocator configuration: (C-1..8)
//:
//: 1 Create an object, supplying 'S' and 'M' to the constructor, and
//: verify that the correct allocator was used (if memory
//: allocation is expected). Additionally, verify the initial
//: value of the string buffer. (C-1..3, 6)
//:
//: 2 Use the 'rdbuf' accessor to verify that it returns the expected
//: (non-null) value. (C-5)
//:
//: 3 Stream a character to the object (using the inherited '<<'
//: operator), then stream a character from the object (using the
//: inherited '>>' operator); verify that the results are as
//: expected. (C-7)
//:
//: 4 Verify no temporary memory is allocated from the object
//: allocator when supplied. (C-4)
//:
//: 5 Delete the object and verify all memory is deallocated. (C-8)
//
// Testing:
// stringstream(const STRING& s, openmode mask, const A& a = A());
// ------------------------------------------------------------------------
if (verbose) printf("\nSTRING & OPENMODE CTOR"
"\n======================\n");
using namespace BloombergLP;
for (int ti = 0; ti < NUM_OPENMODE_DATA; ++ti) {
const Mode MODE = OPENMODE_DATA[ti].d_mode;
for (int tj = 0; tj < NUM_STRLEN_DATA; ++tj) {
const int LENGTH = STRLEN_DATA[tj].d_length;
const char MEM = STRLEN_DATA[tj].d_mem;
for (char cfg = 'a'; cfg <= 'c'; ++cfg) {
const char CONFIG = cfg; // how we specify the allocator
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::TestAllocator fa("footprint", veryVeryVeryVerbose);
bslma::TestAllocator sa("supplied", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
if (veryVerbose) {
printf(
"\nTesting with various allocator configurations.\n");
}
StreamT *objPtr;
bslma::TestAllocator *objAllocatorPtr;
bslma::TestAllocator scratch("scratch", veryVeryVeryVerbose);
StringT mS(&scratch); const StringT& S = mS;
loadString(&mS, LENGTH);
switch (CONFIG) {
case 'a': {
objPtr = new (fa) StreamT(S, MODE);
objAllocatorPtr = &da;
} break;
case 'b': {
objPtr = new (fa) StreamT(
S,
MODE,
typename StreamT::allocator_type(0));
objAllocatorPtr = &da;
} break;
case 'c': {
objPtr = new (fa) StreamT(S, MODE, &sa);
objAllocatorPtr = &sa;
} break;
default: {
ASSERTV(CONFIG, !"Bad allocator config.");
return;
} break;
}
StreamT& mX = *objPtr; const StreamT& X = mX;
const BaseT& B = X;
bslma::TestAllocator& oa = *objAllocatorPtr;
bslma::TestAllocator& noa = 'c' != CONFIG ? sa : da;
// Verify allocations from the object/non-object allocators.
if ('N' == MEM) {
ASSERTV(CONFIG, oa.numBlocksTotal(),
0 == oa.numBlocksTotal());
ASSERTV(CONFIG, noa.numBlocksTotal(),
0 == noa.numBlocksTotal());
}
else {
ASSERTV(CONFIG, oa.numBlocksTotal(),
0 != oa.numBlocksTotal());
}
ASSERTV(CONFIG, X.rdbuf());
ASSERTV(CONFIG, X.rdbuf() == B.rdbuf());
ASSERTV(CONFIG, X.str() == S);
if ((MODE & IosBase::out) || !(MODE & IosBase::in)) {
mX << 'X'; // '>>' test is perturbed if 'out' not set
}
if (MODE & IosBase::out) {
if (MODE & IosBase::ate) {
mS.push_back(static_cast<CharT>('X'));
}
else {
if (S.empty()) { mS.resize(1); }
mS[0] = static_cast<CharT>('X');
}
}
ASSERTV(CONFIG, X.str() == S);
CharT c = 'Z';
mX >> c;
CharT EXPECTED;
if (MODE & IosBase::in) {
EXPECTED = (0 == LENGTH) && !(MODE & IosBase::out)
? 'Z'
: S[0];
}
else {
EXPECTED = 'Z';
}
ASSERTV(CONFIG, EXPECTED == c);
ASSERTV(CONFIG, X.str() == S);
// Verify no temporary memory is allocated from the object
// allocator when supplied.
if ('c' == CONFIG && !(MODE & IosBase::ate)) {
ASSERTV(CONFIG, oa.numBlocksTotal(), oa.numBlocksInUse(),
oa.numBlocksTotal() == oa.numBlocksInUse());
}
// Reclaim dynamically allocated object under test.
fa.deleteObject(objPtr);
// Verify all memory is released on object destruction.
ASSERTV(CONFIG, fa.numBlocksInUse(),
0 == fa.numBlocksInUse());
ASSERTV(CONFIG, oa.numBlocksInUse(),
0 == oa.numBlocksInUse());
ASSERTV(CONFIG, noa.numBlocksInUse(),
0 == noa.numBlocksInUse());
}
}
}
}
template <class CharT>
void testCase7()
{
// ------------------------------------------------------------------------
// CONCERN: Standard allocator can be used
//
// Concerns:
//: 1 An object can be created using a standard-compliant allocator.
//:
//: 2 The object can successfully obtain memory from that allocator.
//:
//: 3 There is no allocation from either the default or global allocator.
//
// Plan:
//: 1 For each of the four constructors, in turn:
//: 1 Create a 'bslma::TestAllocator' object, and install it as the
//: default allocator (note that a ubiquitous test allocator is already
//: installed as the global allocator).
//:
//: 2 Create an object, using the constructor under test, that uses a
//: standard-compliant allocator with minimal features. (C-1)
//:
//: 3 Use the 'str' accessor to verify the initial state of the string
//: buffer. (C-2)
//:
//: 4 In the case of the two constructors that do not take a string
//: value, use the 'str' manipulator to set the buffer value to 'S', a
//: string of sufficient length to guarantee memory allocation; use the
//: 'str' accessor to verify the new expected value of the string
//: buffer. (C-2)
//:
//: 5 Use the test allocator from P-1 to verify that no memory is ever
//: allocated from the default allocator. (C-3)
//
// Testing:
// CONCERN: Standard allocator can be used.
// ------------------------------------------------------------------------
if (verbose) printf("\nCONCERN: Standard allocator can be used"
"\n=======================================\n");
using namespace BloombergLP;
typedef bsltf::StdTestAllocator<CharT> StdAlloc;
typedef bsl::basic_stringstream<CharT, bsl::char_traits<CharT>, StdAlloc>
Stream;
typedef bsl::basic_string<CharT, bsl::char_traits<CharT>, StdAlloc> String;
const Mode MODE = IosBase::in | IosBase::out;
{
StdAlloc A;
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
String mS; const String& S = mS;
loadString(&mS, LENGTH_OF_SUFFICIENTLY_LONG_STRING);
Stream mX(A); const Stream& X = mX; ASSERT(X.str().empty());
mX.str(S); ASSERT(X.str() == S);
ASSERT(0 == da.numBlocksTotal());
}
{
StdAlloc A;
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
String mS; const String& S = mS;
loadString(&mS, LENGTH_OF_SUFFICIENTLY_LONG_STRING);
Stream mX(MODE, A); const Stream& X = mX; ASSERT(X.str().empty());
mX.str(S); ASSERT(X.str() == S);
ASSERT(0 == da.numBlocksTotal());
}
{
StdAlloc A;
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
String mS; const String& S = mS;
loadString(&mS, LENGTH_OF_SUFFICIENTLY_LONG_STRING);
Stream mX(S, A); const Stream& X = mX; ASSERT(X.str() == S);
ASSERT(0 == da.numBlocksTotal());
}
{
StdAlloc A;
bslma::TestAllocator da("default", veryVeryVeryVerbose);
bslma::DefaultAllocatorGuard dag(&da);
String mS; const String& S = mS;
loadString(&mS, LENGTH_OF_SUFFICIENTLY_LONG_STRING);
Stream mX(S, MODE, A); const Stream& X = mX; ASSERT(X.str() == S);
ASSERT(0 == da.numBlocksTotal());
}
}
} // close unnamed namespace
//=============================================================================
// USAGE EXAMPLE
//-----------------------------------------------------------------------------
namespace {
///Usage
///-----
// This section illustrates intended use of this component.
//
///Example 1: Basic Input and Output Operations
/// - - - - - - - - - - - - - - - - - - - - - -
// The following example demonstrates the use of 'bsl::stringstream' to read
// and write data of various types to a 'bsl::string' object.
//
// Suppose we want to implement a simplified converter between a pair of
// generic types, 'TYPE1' and 'TYPE2'. We use 'bsl::stringstream' to implement
// the 'lexicalCast' function. We write the data of type 'TYPE1' into the
// stream with 'operator<<' and then read it back as the data of 'TYPE2' with
// 'operator>>':
//..
template <class TYPE2, class TYPE1>
TYPE2 lexicalCast(const TYPE1& what)
{
bsl::stringstream converter;
converter << what;
TYPE2 val;
converter >> val;
return val;
}
//..
} // close unnamed namespace
//=============================================================================
// MAIN PROGRAM
//-----------------------------------------------------------------------------
int main(int argc, char *argv[])
{
int test = argc > 1 ? atoi(argv[1]) : 0;
verbose = argc > 2;
veryVerbose = argc > 3;
veryVeryVerbose = argc > 4;
veryVeryVeryVerbose = argc > 5;
using namespace BloombergLP;
// CONCERN: In no case does memory come from the global allocator.
bslma::TestAllocator globalAllocator("global", veryVeryVeryVerbose);
bslma::Default::setGlobalAllocator(&globalAllocator);
setbuf(stdout, NULL); // Use unbuffered output.
printf("TEST " __FILE__ " CASE %d\n", test);
switch (test) { case 0: // Zero is always the leading case.
case 9: {
// --------------------------------------------------------------------
// TESTING READ/WRITE/SEEK COMBINATIONS
//
// Concerns:
//: 1. Combination of read, write and seek operations doesn't affect
//: the consistency of the stream internal state.
//
// Plan:
//: 1. Write to the stream, change the input position, then obtain the
//: current stream input position and verify that it's consistent
//: with what has been written to the stream.
// --------------------------------------------------------------------
if (verbose) printf("\nTESTING READ/WRITE/SEEK COMBINATIONS"
"\n====================================\n");
bsl::stringstream inout;
// Outputting a string goes through stringbuf::xsputn, but outputting a
// character doesn't have to involve stringbuf and can be done just by
// bumping the internal streambuf output pointer, so we do both.
inout << "abc" << 'd' << 'e';
// Now verify that we can seek in this stream
inout.seekg(0, std::ios::beg);
inout.seekg(0, std::ios::end);
std::streamoff endPos = inout.tellg();
ASSERT(inout.good());
ASSERT(endPos == inout.str().size());
// Verify that we can seek in the empty stream
bsl::stringstream empty;
empty.seekg(0, std::ios::beg);
empty.seekg(0, std::ios::end);
empty.seekg(0, std::ios::cur);
empty.seekp(0, std::ios::beg);
empty.seekp(0, std::ios::end);
empty.seekp(0, std::ios::cur);
ASSERT(empty.good());
ASSERT(empty.tellg() == std::streampos(0));
ASSERT(empty.tellp() == std::streampos(0));
// Verify the output position after writing to a stream
bsl::stringstream out2;
bsl::string str2 =
"sufficiently long string longer than the short string buffer";
out2 << str2;
std::streamoff endPos2 = out2.tellp();
ASSERT(endPos2 == str2.size());
} break;
case 8: {
// --------------------------------------------------------------------
// USAGE EXAMPLE
// Extracted from component header file.
//
// Concerns:
//: 1 The usage example provided in the component header file compiles,
//: links, and runs as shown.
//
// Plan:
//: 1 Incorporate usage example from header into test driver, remove
//: leading comment characters, and replace 'assert' with 'ASSERT'.
//: (C-1)
//
// Testing:
// USAGE EXAMPLE
// --------------------------------------------------------------------
if (verbose) printf("\nUSAGE EXAMPLE"
"\n=============\n");
// Finally, we verify that the 'lexicalCast' function works on some simple test
// cases:
//..
ASSERT(lexicalCast<int>("1234") == 1234);
//
ASSERT(lexicalCast<short>("-5") == -5);
//
ASSERT(lexicalCast<bsl::string>("abc") == "abc");
//
ASSERT(lexicalCast<bsl::string>(1234) == "1234");
//
ASSERT(lexicalCast<short>(-5) == -5);
//..
} break;
case 7: {
testCase7<char>();
testCase7<wchar_t>();
} break;
case 6: {
testCase6<Obj, std::iostream, bsl::string, char>();
testCase6<WObj, std::wiostream, bsl::wstring, wchar_t>();
} break;
case 5: {
testCase5<Obj, std::iostream, bsl::string, char>();
testCase5<WObj, std::wiostream, bsl::wstring, wchar_t>();
} break;
case 4: {
testCase4<Obj, std::iostream, bsl::string, char>();
testCase4<WObj, std::wiostream, bsl::wstring, wchar_t>();
} break;
case 3: {
testCase3<Obj, std::iostream, bsl::string, char>();
testCase3<WObj, std::wiostream, bsl::wstring, wchar_t>();
} break;
case 2: {
testCase2<Obj, std::iostream, bsl::string, char>();
testCase2<WObj, std::wiostream, bsl::wstring, wchar_t>();
} break;
case 1: {
// --------------------------------------------------------------------
// BREATHING TEST
// Developers' Sandbox.
//
// Concerns:
// We want to exercise basic functionality.
//
// Plan:
// This "test" *exercises* basic functionality, but *tests* nothing.
// --------------------------------------------------------------------
if (verbose) printf("\nBREATHING TEST"
"\n==============\n");
Obj mX; const Obj& X = mX;
const std::iostream& B = X;
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str().empty());
const bsl::string S("ab");
mX.str(S);
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == S);
char c = 'x';
mX >> c;
ASSERT('a' == c);
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == S);
mX << 'c';
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == "cb");
mX >> c;
ASSERT('b' == c);
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == "cb");
const bsl::string T("x");
mX.str(T);
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == T);
mX << 'y';
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == "y");
mX >> c;
ASSERT('y' == c);
ASSERT(!X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == "y");
mX >> c;
ASSERT('y' == c);
ASSERT( X.eof());
ASSERT( X.rdbuf());
ASSERT( X.rdbuf() == B.rdbuf());
ASSERT( X.str() == "y");
} break;
default: {
fprintf(stderr, "WARNING: CASE `%d' NOT FOUND.\n", test);
testStatus = -1;
}
}
// CONCERN: In no case does memory come from the global allocator.
LOOP_ASSERT(globalAllocator.numBlocksTotal(),
0 == globalAllocator.numBlocksTotal());
if (testStatus > 0) {
fprintf(stderr, "Error, non-zero test status = %d.\n", testStatus);
}
return testStatus;
}
// ----------------------------------------------------------------------------
// Copyright (C) 2013 Bloomberg L.P.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to
// deal in the Software without restriction, including without limitation the
// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
// sell copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
// IN THE SOFTWARE.
// ----------------------------- END-OF-FILE ----------------------------------
|
loop: lda :x
add :y
sta :z
lda :y
sta :x
lda :z
sta :y
jc :exit
lda :z
out
jmp :loop
exit: hlt
x: 0
y: 1
z: 0
|
#include "LevinProtocol.h"
#include <System/TcpConnection.h>
using namespace CryptoNote;
namespace {
const uint64_t LEVIN_SIGNATURE = 0x0101010101012101LL; //Bender's nightmare
const uint32_t LEVIN_PACKET_REQUEST = 0x00000001;
const uint32_t LEVIN_PACKET_RESPONSE = 0x00000002;
const uint32_t LEVIN_DEFAULT_MAX_PACKET_SIZE = 100000000; //100MB by default
const uint32_t LEVIN_PROTOCOL_VER_1 = 1;
#pragma pack(push)
#pragma pack(1)
struct bucket_head2
{
uint64_t m_signature;
uint64_t m_cb;
bool m_have_to_return_data;
uint32_t m_command;
int32_t m_return_code;
uint32_t m_flags;
uint32_t m_protocol_version;
};
#pragma pack(pop)
}
bool LevinProtocol::Command::needReply() const {
return !(isNotify || isResponse);
}
LevinProtocol::LevinProtocol(System::TcpConnection& connection)
: m_conn(connection) {}
void LevinProtocol::sendMessage(uint32_t command, const BinaryArray& out, bool needResponse) {
bucket_head2 head = { 0 };
head.m_signature = LEVIN_SIGNATURE;
head.m_cb = out.size();
head.m_have_to_return_data = needResponse;
head.m_command = command;
head.m_protocol_version = LEVIN_PROTOCOL_VER_1;
head.m_flags = LEVIN_PACKET_REQUEST;
// write header and body in one operation
BinaryArray writeBuffer;
writeBuffer.reserve(sizeof(head) + out.size());
Common::VectorOutputStream stream(writeBuffer);
stream.writeSome(&head, sizeof(head));
stream.writeSome(out.data(), out.size());
writeStrict(writeBuffer.data(), writeBuffer.size());
}
bool LevinProtocol::readCommand(Command& cmd) {
bucket_head2 head = { 0 };
if (!readStrict(reinterpret_cast<uint8_t*>(&head), sizeof(head))) {
return false;
}
if (head.m_signature != LEVIN_SIGNATURE) {
throw std::runtime_error("Levin signature mismatch");
}
if (head.m_cb > LEVIN_DEFAULT_MAX_PACKET_SIZE) {
throw std::runtime_error("Levin packet size is too big");
}
BinaryArray buf;
if (head.m_cb != 0) {
buf.resize(head.m_cb);
if (!readStrict(&buf[0], head.m_cb)) {
return false;
}
}
cmd.command = head.m_command;
cmd.buf = std::move(buf);
cmd.isNotify = !head.m_have_to_return_data;
cmd.isResponse = (head.m_flags & LEVIN_PACKET_RESPONSE) == LEVIN_PACKET_RESPONSE;
return true;
}
void LevinProtocol::sendReply(uint32_t command, const BinaryArray& out, int32_t returnCode) {
bucket_head2 head = { 0 };
head.m_signature = LEVIN_SIGNATURE;
head.m_cb = out.size();
head.m_have_to_return_data = false;
head.m_command = command;
head.m_protocol_version = LEVIN_PROTOCOL_VER_1;
head.m_flags = LEVIN_PACKET_RESPONSE;
head.m_return_code = returnCode;
BinaryArray writeBuffer;
writeBuffer.reserve(sizeof(head) + out.size());
Common::VectorOutputStream stream(writeBuffer);
stream.writeSome(&head, sizeof(head));
stream.writeSome(out.data(), out.size());
writeStrict(writeBuffer.data(), writeBuffer.size());
}
void LevinProtocol::writeStrict(const uint8_t* ptr, size_t size) {
size_t offset = 0;
while (offset < size) {
offset += m_conn.write(ptr + offset, size - offset);
}
}
bool LevinProtocol::readStrict(uint8_t* ptr, size_t size) {
size_t offset = 0;
while (offset < size) {
size_t read = m_conn.read(ptr + offset, size - offset);
if (read == 0) {
return false;
}
offset += read;
}
return true;
}
|
#include<bits/stdc++.h>
using namespace std;
void by_value(int a){
a+=10;
}
void by_ref(int *a){
(*a)+=10;
}
int by_ref2(int &a){
a+=10;
}
int main(){
int x=40;
cout<<by_value(x)<<endl;
//x==40
cout<<by_ref(&x)<<endl;
//x==50
cout<<by_ref2(x)<<endl;
//x==60
return 0;
}
|
aLine 0
gNew currentPtr
gMove currentPtr, Root
gNewVPtr currentNext
gMoveNext currentNext, currentPtr
aLine 1
gBeq currentNext, null, 5
aLine 2
gMove currentPtr, currentNext
gMoveNext currentNext, currentNext
Jmp -5
aLine 4
nNew newNodePtr, {0:D}
aLine 5
nMoveRel newNodePtr, currentPtr, 90, -164.545
pSetNext currentPtr, newNodePtr
aLine 6
aStd
gDelete newNodePtr
gDelete currentPtr
gDelete currentNext
Halt |
MODULE MPLAYER
include "player_macros.asm"
K_KEY_NO_KEY EQU 0
K_KEY_UP EQU 1
K_KEY_UPRIGHT EQU 2
K_KEY_RIGHT EQU 3
K_KEY_DOWNRIGHT equ 4
K_KEY_DOWN EQU 5
K_KEY_DOWNLEFT equ 6
K_KEY_LEFT EQU 7
K_KEY_UPLEFT EQU 8
K_KEY_SPACE EQU 10
K_SHOOT_WAIT equ 8
K_FIREBALL_COST equ 13
K_SOLID_TILE equ 128
K_ITEMS_TILES EQU 32
K_ZOMBIES_TILES EQU 96
K_CHARGE_BULLETS_FREQUENCY equ 30
K_MAX_BULLETS_COUNT equ 24
K_COOL_GIRL_INCREMENT equ 2
K_LEFT_MARGIN_SCROLL equ 8*8+K_COOL_GIRL_INCREMENT
K_RIGHT_MARGIN_SCROLL equ 24*8
K_DOWN_MARGIN_SCROLL equ 18*8
K_UP_MARGIN_SCROLL equ 6*8+K_COOL_GIRL_INCREMENT
;====================================
;::MOVE_PLAYER
;====================================
MOVE_PLAYER
LD a, [MWORK.PLAYER_IMMUNITY]
CP 0
JP z, .TrateShoot
DEC a
LD [MWORK.PLAYER_IMMUNITY], a
LD a, [MWORK.PRE_GAME_OVER]
CP 1
RET z
.TrateShoot
MCHECK_M
LD a, [MWORK.PLAYER_SHOOT_WAIT]
CP 0
JP z, .CheckShoot
DEC a
LD [MWORK.PLAYER_SHOOT_WAIT], a
JP .CheckMove
.CheckShoot
MCHECK_SHOOT
.CheckMove
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PLAYER_PREVIOUS_Y], bc
XOR a
CALL GTSTCK
CP 0
JP nz, .CheckMoveTrate
LD a, 1
CALL GTSTCK
.CheckMoveTrate
LD [MWORK.PLAYER_KEY_PRESSED], a
CP K_KEY_NO_KEY
JP z, .NoKey
CP K_KEY_RIGHT
JP z, .SRight
CP K_KEY_LEFT
JP z, .SLeft
CP K_KEY_UP
JP z, .SUp
CP K_KEY_DOWN
JP z, .SDown
CP K_KEY_UPRIGHT
JP z, .UpRight
CP K_KEY_DOWNRIGHT
JP z, .DownRight
CP K_KEY_DOWNLEFT
JP z, .DownLeft
CP K_KEY_UPLEFT
JP z, .UpLeft
RET
.SRight
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveRightPlayer
RET
.SLeft
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveLeftPlayer
RET
.SUp
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveUpPlayer
RET
.SDown
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveDownPlayer
RET
.UpRight
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveUpRightPlayer
RET
.DownRight
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveDownRightPlayer
RET
.DownLeft
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveDownLeftPlayer
RET
.UpLeft
LD [MWORK.PLAYER_DIRECTION], a
CALL MoveUpLeftPlayer
RET
.NoKey
RET
;==================================
;::MoveUpRightPlayer
;==================================
MoveUpRightPlayer
CALL MoveUpPlayer
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PLAYER_PREVIOUS_Y], bc
CALL MoveRightPlayer
RET
;==================================
;::MoveDownRightPlayer
;==================================
MoveDownRightPlayer
CALL MoveDownPlayer
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PLAYER_PREVIOUS_Y], bc
CALL MoveRightPlayer
RET
;==================================
;::MoveDownLeftPlayer
;==================================
MoveDownLeftPlayer
CALL MoveDownPlayer
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PLAYER_PREVIOUS_Y], bc
CALL MoveLeftPlayer
RET
;==================================
;::MoveUpLeftPlayer
;==================================
MoveUpLeftPlayer
CALL MoveUpPlayer
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PLAYER_PREVIOUS_Y], bc
CALL MoveLeftPlayer
RET
;==================================
;::MoveRightPlayer
;==================================
MoveRightPlayer
LD a, [MWORK.PLAYER_X]
CP K_RIGHT_MARGIN_SCROLL
JP nc, .SCheckIfScroll
.SMovePlayer
;Move the player, not the camera.
LD a, [MWORK.CAMERA_TILE_X_RIGHT]
CP MSCREEN.K_MAP_MAX_RIGHT
JP c, .SMoveLess
.SDoMove
LD a, [MWORK.PLAYER_X]
ADD K_COOL_GIRL_INCREMENT
LD [MWORK.PLAYER_X], a
;Mira si puede ir
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, UndoMovement
RET
.SMoveLess ;Move without arrive to the max right
LD a, [MWORK.PLAYER_X]
CP 248-8
JP nc, UndoMovement
JP .SDoMove
.SCheckIfScroll
;Checks if the camera is at maximum right
LD a, [MWORK.CAMERA_TILE_X_RIGHT]
CP MSCREEN.K_MAP_MAX_RIGHT;-1
JP z, .SMovePlayer
;Checks if scroll causes background colision
LD bc, [MWORK.PLAYER_Y]
LD a, 8
ADD b
LD b, a
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, .UndoMovement
;Increments Interscroll counter
LD a, [MWORK.INTER_SCROLL_COUNTER_X]
ADD K_COOL_GIRL_INCREMENT
AND 7
LD [MWORK.INTER_SCROLL_COUNTER_X], a
CP 0
RET nz
;Do Scroll: Move camera on the right
LD a, K_KEY_RIGHT
LD [MWORK.CAMERA_CHANGED], a
LD a, [MWORK.CAMERA_TILE_X_LEFT]
INC a
LD [MWORK.CAMERA_TILE_X_LEFT], a
ADD MSCREEN.K_CAMERA_WIDTH-1
LD [MWORK.CAMERA_TILE_X_RIGHT], a
CALL MSCREEN.UPDATE_CAMERA
CALL SCROLL_ENTITIES
RET
.UndoMovement
LD a, 8 - K_COOL_GIRL_INCREMENT
LD [MWORK.INTER_SCROLL_COUNTER_X], a
JP UndoMovement
;==================================
;::MoveLeftPlayer
;==================================
MoveLeftPlayer
LD a, [MWORK.PLAYER_X]
CP K_LEFT_MARGIN_SCROLL
JP c, .SCheckIfScroll
.SMovePlayer
;Move the player, not the camera.
LD a, [MWORK.CAMERA_TILE_X_LEFT]
CP 1
JP nc, .SMoveLess
.SDoMove
LD a, [MWORK.PLAYER_X]
SUB K_COOL_GIRL_INCREMENT
LD [MWORK.PLAYER_X], a
;Mira si puede ir
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, UndoMovement
RET
.SMoveLess ;Move without arrive to the max left
LD a, [MWORK.PLAYER_X]
CP 16+8
JP c, UndoMovement
JP .SDoMove
.SCheckIfScroll
;Checks if the camera is at maximum left
LD a, [MWORK.CAMERA_TILE_X_LEFT]
CP 0 ;MAP_MAX_LEFT
JP z, .SDoMove ;.SMovePlayer
;Checks if scrolls causes background colision
LD bc, [MWORK.PLAYER_Y]
LD a, b
ADD -8
LD b, a
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, .UndoMovement
;Decrements Interscroll counter
LD a, [MWORK.INTER_SCROLL_COUNTER_X]
SUB K_COOL_GIRL_INCREMENT
AND 7
LD [MWORK.INTER_SCROLL_COUNTER_X], a
CP 0
RET nz
.DoScroll
;Move camera on the left
LD a, K_KEY_LEFT
LD [MWORK.CAMERA_CHANGED], a
LD a, [MWORK.CAMERA_TILE_X_LEFT]
DEC a
LD [MWORK.CAMERA_TILE_X_LEFT], a
ADD MSCREEN.K_CAMERA_WIDTH-1
LD [MWORK.CAMERA_TILE_X_RIGHT], a
CALL MSCREEN.UPDATE_CAMERA
CALL SCROLL_ENTITIES
RET
.UndoMovement
LD a, K_COOL_GIRL_INCREMENT
LD [MWORK.INTER_SCROLL_COUNTER_X], a
JP UndoMovement
;==================================
;::MoveDownPlayer
;==================================
MoveDownPlayer
LD a, [MWORK.PLAYER_Y]
CP K_DOWN_MARGIN_SCROLL
JP nc, .SCheckIfScroll
.SMovePlayer
;Move the player, not the camera.
LD a, [MWORK.CAMERA_TILE_Y_DOWN]
CP MSCREEN.K_MAP_MAX_DOWN
JP c, .SMoveLess
.SDoMove
LD a, [MWORK.PLAYER_Y]
ADD K_COOL_GIRL_INCREMENT
LD [MWORK.PLAYER_Y], a
;Miro si puede ir
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, UndoMovement
RET
.SMoveLess ;Move without arrive to the max down
LD a, [MWORK.PLAYER_Y]
CP 24*8-8*2
JP nc, UndoMovement
JP .SDoMove
.SCheckIfScroll
;Check if the camera is at maximum down
LD a, [MWORK.CAMERA_TILE_Y_DOWN]
CP MSCREEN.K_MAP_MAX_DOWN;-1
JP z, .SMovePlayer
;Checks if scrolls causes background colision
LD bc, [MWORK.PLAYER_Y]
LD a, 8
ADD c
LD c, a
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, .UndoMovement
;Increments Interscroll counter
LD a, [MWORK.INTER_SCROLL_COUNTER_Y]
ADD K_COOL_GIRL_INCREMENT
AND 7
LD [MWORK.INTER_SCROLL_COUNTER_Y], a
CP 0
RET nz
;.DoScroll
;Move camera down
LD a, K_KEY_DOWN
LD [MWORK.CAMERA_CHANGED], a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
INC a
LD [MWORK.CAMERA_TILE_Y_TOP], a
ADD MSCREEN.K_CAMERA_HEIGHT-1
LD [MWORK.CAMERA_TILE_Y_DOWN], a
CALL MSCREEN.UPDATE_CAMERA
CALL SCROLL_ENTITIES
RET
.UndoMovement
LD a, 8 - K_COOL_GIRL_INCREMENT
LD [MWORK.INTER_SCROLL_COUNTER_Y], a
JP UndoMovement
;==================================
;::MoveUpPlayer
;==================================
MoveUpPlayer
LD a, [MWORK.PLAYER_Y]
CP K_UP_MARGIN_SCROLL
JP c, .SCheckIfScroll
.SMovePlayer
;Move the player, not the camera.
LD a, [MWORK.CAMERA_TILE_Y_TOP]
CP 1
JP nc, .SMoveLess
.SDoMove
LD a, [MWORK.PLAYER_Y]
SUB K_COOL_GIRL_INCREMENT
LD [MWORK.PLAYER_Y], a
;Mira si puede ir
LD bc, [MWORK.PLAYER_Y]
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, UndoMovement
RET
.SMoveLess ;Move without arrive to the max top
LD a, [MWORK.PLAYER_Y]
CP MSCREEN.K_CAMERA_PIXELS_OFFSET_UP+8*3
JP c, UndoMovement
JP .SDoMove
.SCheckIfScroll
;Checks if the camera is at maximum left
LD a, [MWORK.CAMERA_TILE_Y_TOP]
CP 0 ;MAP_MAX_TOP
JP z, .SMovePlayer
;Checks if scrolls causes background colision
LD bc, [MWORK.PLAYER_Y]
LD a, -8
ADD c
LD c, a
LD [MWORK.PARAM_CAN_GO_Y], bc
CALL CAN_GO
JP nz, .UndoMovement
;Decrements Interscroll counter
LD a, [MWORK.INTER_SCROLL_COUNTER_Y]
SUB K_COOL_GIRL_INCREMENT
AND 7
LD [MWORK.INTER_SCROLL_COUNTER_Y], a
CP 0
RET nz
.DoScroll
;Move camera up
LD a, K_KEY_UP
LD [MWORK.CAMERA_CHANGED], a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
DEC a
LD [MWORK.CAMERA_TILE_Y_TOP], a
ADD MSCREEN.K_CAMERA_HEIGHT-1
LD [MWORK.CAMERA_TILE_Y_DOWN], a
CALL MSCREEN.UPDATE_CAMERA
CALL SCROLL_ENTITIES
RET
.UndoMovement
LD a, K_COOL_GIRL_INCREMENT
LD [MWORK.INTER_SCROLL_COUNTER_Y], a
JP UndoMovement
;=======================================================
;::UndoMovement
;========================================================
UndoMovement
LD bc, [MWORK.PLAYER_PREVIOUS_Y]
LD [MWORK.PLAYER_Y], bc
RET
;=======================================================
;::CAN_GO
;========================================================
CAN_GO
LD bc, [MWORK.PARAM_CAN_GO_Y]
CALL MSUPPORT.YX_TO_OFFSET
LD hl, MWORK.CAMERA_SCREEN
ADD hl, de
LD a, [hl]
CP 32
JP c, .Continue
CP 96
JP c, CollisionWithEnte
.Continue
; Si X%8=0 ...
LD a, [MWORK.PARAM_CAN_GO_X]
AND 7
CP 0
JP z, .ModX0
; Si X%8 != 0 mira la Y
LD a, [MWORK.PARAM_CAN_GO_Y]
AND 7
CP 0
JP z, .ModXNo0Y0
.ModXNo0YNo0 ; Mira actual, siguiente y anterior en X y en Y
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, -32
ADD hl, bc ;Linea superior
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, 64
ADD hl, bc ;Linea inferior a la central
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
JP RetYes
.ModXNo0Y0 ; //X%8 != 0 y Y%8=0-> Mira actual, siguiente y anterior
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, -32
ADD hl, bc ;Linea superior
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
JP RetYes
.ModX0 ;//X%8=0. Mira la Y...
LD a, [MWORK.PARAM_CAN_GO_Y]
AND 7
CP 0
JP z, .ModXY0
.ModX0YNo0 ;//X%8 = 0 y Y%8 != 0 -> Mira los actuales y los anteriores en X y actuales, anteriores y posteriores en Y
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, -32
ADD hl, bc ; Linea superior
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, 64
ADD hl, bc ; Linea inferior a la central
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
JP RetYes
.ModXY0 ;//X%8=0 y Y%8=0 -> Mira los actuales y los anteriores
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
DEC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
LD bc, -32
ADD hl, bc
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
INC hl
LD a, [hl]
CP K_SOLID_TILE
JP nc, RetNo
JP RetYes
RetYes
XOR a
CP 0
RET
CollisionWithEnte
RetNo
XOR a
CP 1
RET
;===================================
;::SET_PLAYER_FRAME
;===================================
SET_PLAYER_FRAME
LD a, [MWORK.PLAYER_IMMUNITY]
CP 0
JP z, .Continue
LD a, [MWORK.ANIMATION_TICK]
AND 7
CP 4
RET c
.Continue
LD a, [MWORK.PRE_GAME_OVER]
CP 1
CALL z, CHECK_GAME_OVER
CALL ENTITY.GET_NEXT_INDEX_SPRITE_DE
CALL ENTITY.GET_NEXT_INDEX_SPRITE_HL
LD bc, [MWORK.PLAYER_Y]
LD a, -8
ADD c
LD [de], a ;Y
LD [hl], a ;Y
INC de ;Positions on X
INC hl
LD a, -8
ADD b
LD [de], a ;X
LD [hl], a ;X
INC de ;Positions on frame
INC hl
PUSH de
PUSH hl
;Set Frame
LD a, [MWORK.PLAYER_DIRECTION]
DEC a
LD l, a
XOR a
SRL l
RRA
LD h, l
LD l, a ;hl=a*128
LD bc, MDATA.SPRITE_GIRL_0
ADD hl, bc
;Check animation Frame
LD a, [MWORK.PLAYER_KEY_PRESSED]
CP K_KEY_NO_KEY
JP z, .SetFrame
LD a, [MWORK.ANIMATION_TICK]
AND 8
CP 0
JP z, .SetFrame
LD bc, 64
ADD hl, bc
.SetFrame
LD [MWORK.PLAYER_PATTERN], hl
POP hl ;Retrieve frame position
POP de
LD [hl], 0
LD a, 4
LD [de], a
INC hl ;Positions on color
INC de
LD [hl], 6
LD a, 15
LD [de], a
.SetFrameContinue
RET
;=====================================
;::CHECK_GAME_OVER
;=====================================
CHECK_GAME_OVER
LD A, [MWORK.PLAYER_IMMUNITY]
CP 2
RET NC
POP BC ;RET
JP MGAME.SHOW_GAME_OVER
;=================================
;::ADD_NEW_NORMAL_PLAYER_SHOOT
;=================================
ADD_NEW_NORMAL_PLAYER_SHOOT
LD a, [MWORK.CURRENT_NUMBER_OF_SHOOTS]
INC a
LD [MWORK.CURRENT_NUMBER_OF_SHOOTS], a
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_DIRECTION]
CP K_KEY_UP
JP z, .SUp
CP K_KEY_UPRIGHT
JP z, .SUpRight
CP K_KEY_RIGHT
JP z, .SRight
CP K_KEY_DOWNRIGHT
JP z, .SDownRight
CP K_KEY_DOWN
JP z, .SDown
CP K_KEY_DOWNLEFT
JP z, .SDownLeft
CP K_KEY_LEFT
JP z, .SLeft
.SUpLeft
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], -8
RET
.SUp
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 0
RET
.SUpRight
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 8
RET
.SRight
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], 8
RET
.SDownRight
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 8
RET
.SDown
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 0
RET
.SDownLeft
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], -8
RET
.SLeft
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], -8
RET
;=========================================
;::SCROLL_ENTITIES
;=========================================
SCROLL_ENTITIES
PUSH ix
LD ix, MWORK.LIST_ENTITIES_DATA
.LoopScrollEntity
;Scroll Entity In camera
LD a, [ix]
CP 0
JP z, .NextEntity
LD a, [ix+ENTITY.K_OFFSET_IS_VISIBLE]
CP 1
JP z, .TrateVisibleEntity
; Trate no visible entity
LD a, [MWORK.CAMERA_CHANGED]
CP K_KEY_RIGHT
JP z, .NoVisibleEntityRight
CP K_KEY_LEFT
JP z, .NoVisibleEntityLeft
CP K_KEY_UP
JP z, .NoVisibleEntityUp
JP .NoVisibleEntityDown
.NoVisibleEntityRight
MCHECK_IF_VISIBLE
JP .TrateNotToVisible
.NoVisibleEntityLeft
MCHECK_IF_VISIBLE
JP .TrateNotToVisible
.NoVisibleEntityUp
MCHECK_IF_VISIBLE
JP .TrateNotToVisible
.NoVisibleEntityDown
MCHECK_IF_VISIBLE
JP .TrateNotToVisible
.TrateNotToVisible
LD [ix+ENTITY.K_OFFSET_IS_VISIBLE], 1
LD a, [MWORK.CAMERA_TILE_X_LEFT]
LD b, a
LD a, [ix+ENTITY.K_OFFSET_MAP_X]
SUB b
SLA a
SLA a
SLA a
LD [ix+ENTITY.K_OFFSET_X], a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
LD b, a
LD a, [ix+ENTITY.K_OFFSET_MAP_Y]
SUB b
SLA a
SLA a
SLA a
ADD MSCREEN.K_CAMERA_LINES_OFFSET_UP*8
LD [ix+ENTITY.K_OFFSET_Y], a
JP .NextEntity
;Trate visible entities
.TrateVisibleEntity
LD a, [MWORK.CAMERA_CHANGED]
CP K_KEY_RIGHT
JP z, .ScrollEntityRight
CP K_KEY_LEFT
JP z, .ScrollEntityLeft
CP K_KEY_UP
JP z, .ScrollEntityUp
JP .ScrollEntityDown
.ScrollEntityRight
LD [ix+ENTITY.K_OFFSET_NOVISIBLE_COUNTER], 0
LD a, [ix+ENTITY.K_OFFSET_X]
CP 8
JP z, .TrateVisibleToNotByLeft
SUB 8
LD [ix+ENTITY.K_OFFSET_X], a
JP .NextEntity
.ScrollEntityLeft
LD [ix+ENTITY.K_OFFSET_NOVISIBLE_COUNTER], 0
LD a, [ix+ENTITY.K_OFFSET_X]
CP 31*8
JP z, .TrateVisibleToNotByRight
ADD 8
LD [ix+ENTITY.K_OFFSET_X], a
JP .NextEntity
.ScrollEntityUp
LD [ix+ENTITY.K_OFFSET_NOVISIBLE_COUNTER], 0
LD a, [ix+ENTITY.K_OFFSET_Y]
CP 23*8
JP z, .TrateVisibleToNotByDown
ADD 8
LD [ix+ENTITY.K_OFFSET_Y], a
JP .NextEntity
.ScrollEntityDown
LD [ix+ENTITY.K_OFFSET_NOVISIBLE_COUNTER], 0
LD a, [ix+ENTITY.K_OFFSET_Y]
CP (MSCREEN.K_CAMERA_LINES_OFFSET_UP)*8+8
JP z, .TrateVisibleToNotByUp
SUB 8
LD [ix+ENTITY.K_OFFSET_Y], a
JP .NextEntity
.TrateVisibleToNotByUp
LD [ix+ENTITY.K_OFFSET_IS_VISIBLE], 0
LD a, [ix+ENTITY.K_OFFSET_X]
SRL a
SRL a
SRL a
LD b, a
LD a, [MWORK.CAMERA_TILE_X_LEFT]
ADD b
LD [ix+ENTITY.K_OFFSET_MAP_X], a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
LD [ix+ENTITY.K_OFFSET_MAP_Y], a
JP .NextEntity
.TrateVisibleToNotByDown
LD [ix+ENTITY.K_OFFSET_IS_VISIBLE], 0
LD a, [ix+ENTITY.K_OFFSET_X]
SRL a
SRL a
SRL a
LD b, a
LD a, [MWORK.CAMERA_TILE_X_LEFT]
ADD b
LD [ix+ENTITY.K_OFFSET_MAP_X], a
LD a, [MWORK.CAMERA_TILE_Y_DOWN]
INC a
LD [ix+ENTITY.K_OFFSET_MAP_Y], a
JP .NextEntity
.TrateVisibleToNotByLeft
LD [ix+ENTITY.K_OFFSET_IS_VISIBLE], 0
LD a, [MWORK.CAMERA_TILE_X_LEFT]
LD [ix+ENTITY.K_OFFSET_MAP_X], a
LD a, [ix+ENTITY.K_OFFSET_Y]
SRL a
SRL a
SRL a
SUB MSCREEN.K_CAMERA_LINES_OFFSET_UP
LD b, a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
ADD b
LD [ix+ENTITY.K_OFFSET_MAP_Y], a
JP .NextEntity
.TrateVisibleToNotByRight
LD [ix+ENTITY.K_OFFSET_IS_VISIBLE], 0
LD a, [MWORK.CAMERA_TILE_X_RIGHT]
INC a
LD [ix+ENTITY.K_OFFSET_MAP_X], a
LD a, [ix+ENTITY.K_OFFSET_Y]
SRL a
SRL a
SRL a
SUB MSCREEN.K_CAMERA_LINES_OFFSET_UP
LD b, a
LD a, [MWORK.CAMERA_TILE_Y_TOP]
ADD b
LD [ix+ENTITY.K_OFFSET_MAP_Y], a
.NextEntity
LD bc, MWORK.K_DATA_PER_ENTITY
ADD ix, bc
LD a, [ix]
CP MWORK.K_EOF
JP z, .Ret
JP .LoopScrollEntity
.Ret
POP ix
RET
;============================
;::CHARGE_BULLETS
;============================
CHARGE_BULLETS
LD a, [MWORK.CHARGE_BULLETS_COUNTER]
INC a
LD [MWORK.CHARGE_BULLETS_COUNTER], a
CP K_CHARGE_BULLETS_FREQUENCY
RET nz
XOR a
LD [MWORK.CHARGE_BULLETS_COUNTER], a
LD a, [MWORK.PLAYER_BULLETS]
CP K_MAX_BULLETS_COUNT
RET nc
INC a
LD [MWORK.PLAYER_BULLETS], a
RET
;=================================
;::ADD_NEW_PLAYER_DOUBLE_SHOOT
;=================================
ADD_NEW_PLAYER_DOUBLE_SHOOT
LD a, [MWORK.CURRENT_NUMBER_OF_SHOOTS]
CP 0
RET nz
ADD 2
LD [MWORK.CURRENT_NUMBER_OF_SHOOTS], a
LD a, [MWORK.PLAYER_DIRECTION]
CP K_KEY_UP
JP z, .SUp
CP K_KEY_UPRIGHT
JP z, .SUpRight
CP K_KEY_RIGHT
JP z, .SRight
CP K_KEY_DOWNRIGHT
JP z, .SDownRight
CP K_KEY_DOWN
JP z, .SDown
CP K_KEY_DOWNLEFT
JP z, .SDownLeft
CP K_KEY_LEFT
JP z, .SLeft
.SUpLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7-6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
SUB 6
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], -8
RET
.SUp
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
SUB 4
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 0
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
ADD 4
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 0
ret
.SUpRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7-6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
ADD 6
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 8
RET
.SRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
SUB 2
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], 8
RET
.SDownRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
ADD 6
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 8
RET
.SDown
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
ADD 4
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 0
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
SUB 4
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 0
RET
.SDownLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
SUB 6
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], -8
RET
.SLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 6
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
SUB 2
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], -8
RET
;=================================
;::ADD_NEW_PLAYER_TRIPLE_SHOOT
;=================================
ADD_NEW_PLAYER_TRIPLE_SHOOT
LD a, [MWORK.CURRENT_NUMBER_OF_SHOOTS]
CP 0
RET nz
LD a, 3
LD [MWORK.CURRENT_NUMBER_OF_SHOOTS], a
LD a, [MWORK.PLAYER_DIRECTION]
CP K_KEY_UP
JP z, .SUp
CP K_KEY_UPRIGHT
JP z, .SUpRight
CP K_KEY_RIGHT
JP z, .SRight
CP K_KEY_DOWNRIGHT
JP z, .SDownRight
CP K_KEY_DOWN
JP z, .SDown
CP K_KEY_DOWNLEFT
JP z, .SDownLeft
CP K_KEY_LEFT
JP z, .SLeft
.SUpLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -10
INC hl
LD [hl], -6
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -6
INC hl
LD [hl], -10
RET
.SUp
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 0
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], -2
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 2
RET
.SUpRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -8
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -10
INC hl
LD [hl], 6
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 7
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -6
INC hl
LD [hl], 10
RET
.SRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -2
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 2
INC hl
LD [hl], 8
RET
.SDownRight
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 10
INC hl
LD [hl], 6
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 6
INC hl
LD [hl], 10
RET
.SDown
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 0
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], 2
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], -2
RET
.SDownLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 8
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 10
INC hl
LD [hl], -6
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 6
INC hl
LD [hl], -10
RET
.SLeft
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 0
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], -2
INC hl
LD [hl], -8
CALL ENTITY.GET_NEXT_EMPTY_INDESTRUCTIBLE_IN_GAME
LD [hl], ENTITY.K_ENTITY_PLAYER_SHOOT
INC hl
LD [hl], 1 ;IsVisible
INC hl
LD a, [MWORK.PLAYER_Y]
ADD 3
LD [hl], a
INC hl
LD a, [MWORK.PLAYER_X]
LD [hl], a
INC hl
LD [hl], 2
INC hl
LD [hl], -8
RET
ENDMODULE |
TITLE InputForParserGROUP4
LEA 0,87 (3)
LX 1, +124 (0)
STX 2, -93 (1)
LEA 3, X"39 (2)
LX 0, +X"C23 (3)
STX 1, -X"23D (0)
LEA 2, O"3723 (1)
LX 3, +O"3243 (2)
STX 0, -O"42 (3)
LEA 1, B"10101101 (0)
LX 2, +B"11010 (1)
STX 3, -B"10010111 (2)
LEA 0, (3)
END
|
; ==== STM32F30x PERIPHERALS =================================
;
; CTU Prague, FEL, Department of Measurement
;
; ------------------------------------------------------------
;
; Generated from "STM32F30x.svd"
;
; SVD parsing library (c) Paul Osborne, 2015-2016
; https://github.com/posborne/cmsis-svd
; ASM building script (c) Ondrej Hruska, 2016
;
; ============================================================
; ---- GPIOA -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOA base address:
GPIOA_BASE EQU 0x48000000
; GPIOA registers:
GPIOA_MODER EQU (GPIOA_BASE + 0x0) ; GPIO port mode register
GPIOA_OTYPER EQU (GPIOA_BASE + 0x4) ; GPIO port output type register
GPIOA_OSPEEDR EQU (GPIOA_BASE + 0x8) ; GPIO port output speed register
GPIOA_PUPDR EQU (GPIOA_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOA_IDR EQU (GPIOA_BASE + 0x10) ; GPIO port input data register
GPIOA_ODR EQU (GPIOA_BASE + 0x14) ; GPIO port output data register
GPIOA_BSRR EQU (GPIOA_BASE + 0x18) ; GPIO port bit set/reset register
GPIOA_LCKR EQU (GPIOA_BASE + 0x1c) ; GPIO port configuration lock register
GPIOA_AFRL EQU (GPIOA_BASE + 0x20) ; GPIO alternate function low register
GPIOA_AFRH EQU (GPIOA_BASE + 0x24) ; GPIO alternate function high register
GPIOA_BRR EQU (GPIOA_BASE + 0x28) ; Port bit reset register
; GPIOA_MODER fields:
GPIO_MODER_MODER15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER15_ofs EQU 30
GPIO_MODER_MODER15_len EQU 2
GPIO_MODER_MODER14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER14_ofs EQU 28
GPIO_MODER_MODER14_len EQU 2
GPIO_MODER_MODER13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER13_ofs EQU 26
GPIO_MODER_MODER13_len EQU 2
GPIO_MODER_MODER12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER12_ofs EQU 24
GPIO_MODER_MODER12_len EQU 2
GPIO_MODER_MODER11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER11_ofs EQU 22
GPIO_MODER_MODER11_len EQU 2
GPIO_MODER_MODER10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER10_ofs EQU 20
GPIO_MODER_MODER10_len EQU 2
GPIO_MODER_MODER9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER9_ofs EQU 18
GPIO_MODER_MODER9_len EQU 2
GPIO_MODER_MODER8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER8_ofs EQU 16
GPIO_MODER_MODER8_len EQU 2
GPIO_MODER_MODER7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER7_ofs EQU 14
GPIO_MODER_MODER7_len EQU 2
GPIO_MODER_MODER6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER6_ofs EQU 12
GPIO_MODER_MODER6_len EQU 2
GPIO_MODER_MODER5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER5_ofs EQU 10
GPIO_MODER_MODER5_len EQU 2
GPIO_MODER_MODER4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER4_ofs EQU 8
GPIO_MODER_MODER4_len EQU 2
GPIO_MODER_MODER3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER3_ofs EQU 6
GPIO_MODER_MODER3_len EQU 2
GPIO_MODER_MODER2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER2_ofs EQU 4
GPIO_MODER_MODER2_len EQU 2
GPIO_MODER_MODER1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER1_ofs EQU 2
GPIO_MODER_MODER1_len EQU 2
GPIO_MODER_MODER0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER0_ofs EQU 0
GPIO_MODER_MODER0_len EQU 2
; GPIOA_OTYPER fields:
GPIO_OTYPER_OT15 EQU 0x00008000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT15_ofs EQU 15
GPIO_OTYPER_OT15_len EQU 1
GPIO_OTYPER_OT14 EQU 0x00004000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT14_ofs EQU 14
GPIO_OTYPER_OT14_len EQU 1
GPIO_OTYPER_OT13 EQU 0x00002000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT13_ofs EQU 13
GPIO_OTYPER_OT13_len EQU 1
GPIO_OTYPER_OT12 EQU 0x00001000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT12_ofs EQU 12
GPIO_OTYPER_OT12_len EQU 1
GPIO_OTYPER_OT11 EQU 0x00000800 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT11_ofs EQU 11
GPIO_OTYPER_OT11_len EQU 1
GPIO_OTYPER_OT10 EQU 0x00000400 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT10_ofs EQU 10
GPIO_OTYPER_OT10_len EQU 1
GPIO_OTYPER_OT9 EQU 0x00000200 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT9_ofs EQU 9
GPIO_OTYPER_OT9_len EQU 1
GPIO_OTYPER_OT8 EQU 0x00000100 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT8_ofs EQU 8
GPIO_OTYPER_OT8_len EQU 1
GPIO_OTYPER_OT7 EQU 0x00000080 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT7_ofs EQU 7
GPIO_OTYPER_OT7_len EQU 1
GPIO_OTYPER_OT6 EQU 0x00000040 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT6_ofs EQU 6
GPIO_OTYPER_OT6_len EQU 1
GPIO_OTYPER_OT5 EQU 0x00000020 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT5_ofs EQU 5
GPIO_OTYPER_OT5_len EQU 1
GPIO_OTYPER_OT4 EQU 0x00000010 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT4_ofs EQU 4
GPIO_OTYPER_OT4_len EQU 1
GPIO_OTYPER_OT3 EQU 0x00000008 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT3_ofs EQU 3
GPIO_OTYPER_OT3_len EQU 1
GPIO_OTYPER_OT2 EQU 0x00000004 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT2_ofs EQU 2
GPIO_OTYPER_OT2_len EQU 1
GPIO_OTYPER_OT1 EQU 0x00000002 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT1_ofs EQU 1
GPIO_OTYPER_OT1_len EQU 1
GPIO_OTYPER_OT0 EQU 0x00000001 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT0_ofs EQU 0
GPIO_OTYPER_OT0_len EQU 1
; GPIOA_OSPEEDR fields:
GPIO_OSPEEDR_OSPEEDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR15_ofs EQU 30
GPIO_OSPEEDR_OSPEEDR15_len EQU 2
GPIO_OSPEEDR_OSPEEDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR14_ofs EQU 28
GPIO_OSPEEDR_OSPEEDR14_len EQU 2
GPIO_OSPEEDR_OSPEEDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR13_ofs EQU 26
GPIO_OSPEEDR_OSPEEDR13_len EQU 2
GPIO_OSPEEDR_OSPEEDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR12_ofs EQU 24
GPIO_OSPEEDR_OSPEEDR12_len EQU 2
GPIO_OSPEEDR_OSPEEDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR11_ofs EQU 22
GPIO_OSPEEDR_OSPEEDR11_len EQU 2
GPIO_OSPEEDR_OSPEEDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR10_ofs EQU 20
GPIO_OSPEEDR_OSPEEDR10_len EQU 2
GPIO_OSPEEDR_OSPEEDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR9_ofs EQU 18
GPIO_OSPEEDR_OSPEEDR9_len EQU 2
GPIO_OSPEEDR_OSPEEDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR8_ofs EQU 16
GPIO_OSPEEDR_OSPEEDR8_len EQU 2
GPIO_OSPEEDR_OSPEEDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR7_ofs EQU 14
GPIO_OSPEEDR_OSPEEDR7_len EQU 2
GPIO_OSPEEDR_OSPEEDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR6_ofs EQU 12
GPIO_OSPEEDR_OSPEEDR6_len EQU 2
GPIO_OSPEEDR_OSPEEDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR5_ofs EQU 10
GPIO_OSPEEDR_OSPEEDR5_len EQU 2
GPIO_OSPEEDR_OSPEEDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR4_ofs EQU 8
GPIO_OSPEEDR_OSPEEDR4_len EQU 2
GPIO_OSPEEDR_OSPEEDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR3_ofs EQU 6
GPIO_OSPEEDR_OSPEEDR3_len EQU 2
GPIO_OSPEEDR_OSPEEDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR2_ofs EQU 4
GPIO_OSPEEDR_OSPEEDR2_len EQU 2
GPIO_OSPEEDR_OSPEEDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR1_ofs EQU 2
GPIO_OSPEEDR_OSPEEDR1_len EQU 2
GPIO_OSPEEDR_OSPEEDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR0_ofs EQU 0
GPIO_OSPEEDR_OSPEEDR0_len EQU 2
; GPIOA_PUPDR fields:
GPIO_PUPDR_PUPDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR15_ofs EQU 30
GPIO_PUPDR_PUPDR15_len EQU 2
GPIO_PUPDR_PUPDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR14_ofs EQU 28
GPIO_PUPDR_PUPDR14_len EQU 2
GPIO_PUPDR_PUPDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR13_ofs EQU 26
GPIO_PUPDR_PUPDR13_len EQU 2
GPIO_PUPDR_PUPDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR12_ofs EQU 24
GPIO_PUPDR_PUPDR12_len EQU 2
GPIO_PUPDR_PUPDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR11_ofs EQU 22
GPIO_PUPDR_PUPDR11_len EQU 2
GPIO_PUPDR_PUPDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR10_ofs EQU 20
GPIO_PUPDR_PUPDR10_len EQU 2
GPIO_PUPDR_PUPDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR9_ofs EQU 18
GPIO_PUPDR_PUPDR9_len EQU 2
GPIO_PUPDR_PUPDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR8_ofs EQU 16
GPIO_PUPDR_PUPDR8_len EQU 2
GPIO_PUPDR_PUPDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR7_ofs EQU 14
GPIO_PUPDR_PUPDR7_len EQU 2
GPIO_PUPDR_PUPDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR6_ofs EQU 12
GPIO_PUPDR_PUPDR6_len EQU 2
GPIO_PUPDR_PUPDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR5_ofs EQU 10
GPIO_PUPDR_PUPDR5_len EQU 2
GPIO_PUPDR_PUPDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR4_ofs EQU 8
GPIO_PUPDR_PUPDR4_len EQU 2
GPIO_PUPDR_PUPDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR3_ofs EQU 6
GPIO_PUPDR_PUPDR3_len EQU 2
GPIO_PUPDR_PUPDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR2_ofs EQU 4
GPIO_PUPDR_PUPDR2_len EQU 2
GPIO_PUPDR_PUPDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR1_ofs EQU 2
GPIO_PUPDR_PUPDR1_len EQU 2
GPIO_PUPDR_PUPDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR0_ofs EQU 0
GPIO_PUPDR_PUPDR0_len EQU 2
; GPIOA_IDR fields:
GPIO_IDR_IDR15 EQU 0x00008000 ; Port input data (y = 0..15)
GPIO_IDR_IDR15_ofs EQU 15
GPIO_IDR_IDR15_len EQU 1
GPIO_IDR_IDR14 EQU 0x00004000 ; Port input data (y = 0..15)
GPIO_IDR_IDR14_ofs EQU 14
GPIO_IDR_IDR14_len EQU 1
GPIO_IDR_IDR13 EQU 0x00002000 ; Port input data (y = 0..15)
GPIO_IDR_IDR13_ofs EQU 13
GPIO_IDR_IDR13_len EQU 1
GPIO_IDR_IDR12 EQU 0x00001000 ; Port input data (y = 0..15)
GPIO_IDR_IDR12_ofs EQU 12
GPIO_IDR_IDR12_len EQU 1
GPIO_IDR_IDR11 EQU 0x00000800 ; Port input data (y = 0..15)
GPIO_IDR_IDR11_ofs EQU 11
GPIO_IDR_IDR11_len EQU 1
GPIO_IDR_IDR10 EQU 0x00000400 ; Port input data (y = 0..15)
GPIO_IDR_IDR10_ofs EQU 10
GPIO_IDR_IDR10_len EQU 1
GPIO_IDR_IDR9 EQU 0x00000200 ; Port input data (y = 0..15)
GPIO_IDR_IDR9_ofs EQU 9
GPIO_IDR_IDR9_len EQU 1
GPIO_IDR_IDR8 EQU 0x00000100 ; Port input data (y = 0..15)
GPIO_IDR_IDR8_ofs EQU 8
GPIO_IDR_IDR8_len EQU 1
GPIO_IDR_IDR7 EQU 0x00000080 ; Port input data (y = 0..15)
GPIO_IDR_IDR7_ofs EQU 7
GPIO_IDR_IDR7_len EQU 1
GPIO_IDR_IDR6 EQU 0x00000040 ; Port input data (y = 0..15)
GPIO_IDR_IDR6_ofs EQU 6
GPIO_IDR_IDR6_len EQU 1
GPIO_IDR_IDR5 EQU 0x00000020 ; Port input data (y = 0..15)
GPIO_IDR_IDR5_ofs EQU 5
GPIO_IDR_IDR5_len EQU 1
GPIO_IDR_IDR4 EQU 0x00000010 ; Port input data (y = 0..15)
GPIO_IDR_IDR4_ofs EQU 4
GPIO_IDR_IDR4_len EQU 1
GPIO_IDR_IDR3 EQU 0x00000008 ; Port input data (y = 0..15)
GPIO_IDR_IDR3_ofs EQU 3
GPIO_IDR_IDR3_len EQU 1
GPIO_IDR_IDR2 EQU 0x00000004 ; Port input data (y = 0..15)
GPIO_IDR_IDR2_ofs EQU 2
GPIO_IDR_IDR2_len EQU 1
GPIO_IDR_IDR1 EQU 0x00000002 ; Port input data (y = 0..15)
GPIO_IDR_IDR1_ofs EQU 1
GPIO_IDR_IDR1_len EQU 1
GPIO_IDR_IDR0 EQU 0x00000001 ; Port input data (y = 0..15)
GPIO_IDR_IDR0_ofs EQU 0
GPIO_IDR_IDR0_len EQU 1
; GPIOA_ODR fields:
GPIO_ODR_ODR15 EQU 0x00008000 ; Port output data (y = 0..15)
GPIO_ODR_ODR15_ofs EQU 15
GPIO_ODR_ODR15_len EQU 1
GPIO_ODR_ODR14 EQU 0x00004000 ; Port output data (y = 0..15)
GPIO_ODR_ODR14_ofs EQU 14
GPIO_ODR_ODR14_len EQU 1
GPIO_ODR_ODR13 EQU 0x00002000 ; Port output data (y = 0..15)
GPIO_ODR_ODR13_ofs EQU 13
GPIO_ODR_ODR13_len EQU 1
GPIO_ODR_ODR12 EQU 0x00001000 ; Port output data (y = 0..15)
GPIO_ODR_ODR12_ofs EQU 12
GPIO_ODR_ODR12_len EQU 1
GPIO_ODR_ODR11 EQU 0x00000800 ; Port output data (y = 0..15)
GPIO_ODR_ODR11_ofs EQU 11
GPIO_ODR_ODR11_len EQU 1
GPIO_ODR_ODR10 EQU 0x00000400 ; Port output data (y = 0..15)
GPIO_ODR_ODR10_ofs EQU 10
GPIO_ODR_ODR10_len EQU 1
GPIO_ODR_ODR9 EQU 0x00000200 ; Port output data (y = 0..15)
GPIO_ODR_ODR9_ofs EQU 9
GPIO_ODR_ODR9_len EQU 1
GPIO_ODR_ODR8 EQU 0x00000100 ; Port output data (y = 0..15)
GPIO_ODR_ODR8_ofs EQU 8
GPIO_ODR_ODR8_len EQU 1
GPIO_ODR_ODR7 EQU 0x00000080 ; Port output data (y = 0..15)
GPIO_ODR_ODR7_ofs EQU 7
GPIO_ODR_ODR7_len EQU 1
GPIO_ODR_ODR6 EQU 0x00000040 ; Port output data (y = 0..15)
GPIO_ODR_ODR6_ofs EQU 6
GPIO_ODR_ODR6_len EQU 1
GPIO_ODR_ODR5 EQU 0x00000020 ; Port output data (y = 0..15)
GPIO_ODR_ODR5_ofs EQU 5
GPIO_ODR_ODR5_len EQU 1
GPIO_ODR_ODR4 EQU 0x00000010 ; Port output data (y = 0..15)
GPIO_ODR_ODR4_ofs EQU 4
GPIO_ODR_ODR4_len EQU 1
GPIO_ODR_ODR3 EQU 0x00000008 ; Port output data (y = 0..15)
GPIO_ODR_ODR3_ofs EQU 3
GPIO_ODR_ODR3_len EQU 1
GPIO_ODR_ODR2 EQU 0x00000004 ; Port output data (y = 0..15)
GPIO_ODR_ODR2_ofs EQU 2
GPIO_ODR_ODR2_len EQU 1
GPIO_ODR_ODR1 EQU 0x00000002 ; Port output data (y = 0..15)
GPIO_ODR_ODR1_ofs EQU 1
GPIO_ODR_ODR1_len EQU 1
GPIO_ODR_ODR0 EQU 0x00000001 ; Port output data (y = 0..15)
GPIO_ODR_ODR0_ofs EQU 0
GPIO_ODR_ODR0_len EQU 1
; GPIOA_BSRR fields:
GPIO_BSRR_BR15 EQU 0x80000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR15_ofs EQU 31
GPIO_BSRR_BR15_len EQU 1
GPIO_BSRR_BR14 EQU 0x40000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR14_ofs EQU 30
GPIO_BSRR_BR14_len EQU 1
GPIO_BSRR_BR13 EQU 0x20000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR13_ofs EQU 29
GPIO_BSRR_BR13_len EQU 1
GPIO_BSRR_BR12 EQU 0x10000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR12_ofs EQU 28
GPIO_BSRR_BR12_len EQU 1
GPIO_BSRR_BR11 EQU 0x08000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR11_ofs EQU 27
GPIO_BSRR_BR11_len EQU 1
GPIO_BSRR_BR10 EQU 0x04000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR10_ofs EQU 26
GPIO_BSRR_BR10_len EQU 1
GPIO_BSRR_BR9 EQU 0x02000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR9_ofs EQU 25
GPIO_BSRR_BR9_len EQU 1
GPIO_BSRR_BR8 EQU 0x01000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR8_ofs EQU 24
GPIO_BSRR_BR8_len EQU 1
GPIO_BSRR_BR7 EQU 0x00800000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR7_ofs EQU 23
GPIO_BSRR_BR7_len EQU 1
GPIO_BSRR_BR6 EQU 0x00400000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR6_ofs EQU 22
GPIO_BSRR_BR6_len EQU 1
GPIO_BSRR_BR5 EQU 0x00200000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR5_ofs EQU 21
GPIO_BSRR_BR5_len EQU 1
GPIO_BSRR_BR4 EQU 0x00100000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR4_ofs EQU 20
GPIO_BSRR_BR4_len EQU 1
GPIO_BSRR_BR3 EQU 0x00080000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR3_ofs EQU 19
GPIO_BSRR_BR3_len EQU 1
GPIO_BSRR_BR2 EQU 0x00040000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR2_ofs EQU 18
GPIO_BSRR_BR2_len EQU 1
GPIO_BSRR_BR1 EQU 0x00020000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR1_ofs EQU 17
GPIO_BSRR_BR1_len EQU 1
GPIO_BSRR_BR0 EQU 0x00010000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BR0_ofs EQU 16
GPIO_BSRR_BR0_len EQU 1
GPIO_BSRR_BS15 EQU 0x00008000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS15_ofs EQU 15
GPIO_BSRR_BS15_len EQU 1
GPIO_BSRR_BS14 EQU 0x00004000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS14_ofs EQU 14
GPIO_BSRR_BS14_len EQU 1
GPIO_BSRR_BS13 EQU 0x00002000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS13_ofs EQU 13
GPIO_BSRR_BS13_len EQU 1
GPIO_BSRR_BS12 EQU 0x00001000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS12_ofs EQU 12
GPIO_BSRR_BS12_len EQU 1
GPIO_BSRR_BS11 EQU 0x00000800 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS11_ofs EQU 11
GPIO_BSRR_BS11_len EQU 1
GPIO_BSRR_BS10 EQU 0x00000400 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS10_ofs EQU 10
GPIO_BSRR_BS10_len EQU 1
GPIO_BSRR_BS9 EQU 0x00000200 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS9_ofs EQU 9
GPIO_BSRR_BS9_len EQU 1
GPIO_BSRR_BS8 EQU 0x00000100 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS8_ofs EQU 8
GPIO_BSRR_BS8_len EQU 1
GPIO_BSRR_BS7 EQU 0x00000080 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS7_ofs EQU 7
GPIO_BSRR_BS7_len EQU 1
GPIO_BSRR_BS6 EQU 0x00000040 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS6_ofs EQU 6
GPIO_BSRR_BS6_len EQU 1
GPIO_BSRR_BS5 EQU 0x00000020 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS5_ofs EQU 5
GPIO_BSRR_BS5_len EQU 1
GPIO_BSRR_BS4 EQU 0x00000010 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS4_ofs EQU 4
GPIO_BSRR_BS4_len EQU 1
GPIO_BSRR_BS3 EQU 0x00000008 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS3_ofs EQU 3
GPIO_BSRR_BS3_len EQU 1
GPIO_BSRR_BS2 EQU 0x00000004 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS2_ofs EQU 2
GPIO_BSRR_BS2_len EQU 1
GPIO_BSRR_BS1 EQU 0x00000002 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS1_ofs EQU 1
GPIO_BSRR_BS1_len EQU 1
GPIO_BSRR_BS0 EQU 0x00000001 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS0_ofs EQU 0
GPIO_BSRR_BS0_len EQU 1
; GPIOA_LCKR fields:
GPIO_LCKR_LCKK EQU 0x00010000 ; Lok Key
GPIO_LCKR_LCKK_ofs EQU 16
GPIO_LCKR_LCKK_len EQU 1
GPIO_LCKR_LCK15 EQU 0x00008000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK15_ofs EQU 15
GPIO_LCKR_LCK15_len EQU 1
GPIO_LCKR_LCK14 EQU 0x00004000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK14_ofs EQU 14
GPIO_LCKR_LCK14_len EQU 1
GPIO_LCKR_LCK13 EQU 0x00002000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK13_ofs EQU 13
GPIO_LCKR_LCK13_len EQU 1
GPIO_LCKR_LCK12 EQU 0x00001000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK12_ofs EQU 12
GPIO_LCKR_LCK12_len EQU 1
GPIO_LCKR_LCK11 EQU 0x00000800 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK11_ofs EQU 11
GPIO_LCKR_LCK11_len EQU 1
GPIO_LCKR_LCK10 EQU 0x00000400 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK10_ofs EQU 10
GPIO_LCKR_LCK10_len EQU 1
GPIO_LCKR_LCK9 EQU 0x00000200 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK9_ofs EQU 9
GPIO_LCKR_LCK9_len EQU 1
GPIO_LCKR_LCK8 EQU 0x00000100 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK8_ofs EQU 8
GPIO_LCKR_LCK8_len EQU 1
GPIO_LCKR_LCK7 EQU 0x00000080 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK7_ofs EQU 7
GPIO_LCKR_LCK7_len EQU 1
GPIO_LCKR_LCK6 EQU 0x00000040 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK6_ofs EQU 6
GPIO_LCKR_LCK6_len EQU 1
GPIO_LCKR_LCK5 EQU 0x00000020 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK5_ofs EQU 5
GPIO_LCKR_LCK5_len EQU 1
GPIO_LCKR_LCK4 EQU 0x00000010 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK4_ofs EQU 4
GPIO_LCKR_LCK4_len EQU 1
GPIO_LCKR_LCK3 EQU 0x00000008 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK3_ofs EQU 3
GPIO_LCKR_LCK3_len EQU 1
GPIO_LCKR_LCK2 EQU 0x00000004 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK2_ofs EQU 2
GPIO_LCKR_LCK2_len EQU 1
GPIO_LCKR_LCK1 EQU 0x00000002 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK1_ofs EQU 1
GPIO_LCKR_LCK1_len EQU 1
GPIO_LCKR_LCK0 EQU 0x00000001 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK0_ofs EQU 0
GPIO_LCKR_LCK0_len EQU 1
; GPIOA_AFRL fields:
GPIO_AFRL_AFRL7 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL7_ofs EQU 28
GPIO_AFRL_AFRL7_len EQU 4
GPIO_AFRL_AFRL6 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL6_ofs EQU 24
GPIO_AFRL_AFRL6_len EQU 4
GPIO_AFRL_AFRL5 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL5_ofs EQU 20
GPIO_AFRL_AFRL5_len EQU 4
GPIO_AFRL_AFRL4 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL4_ofs EQU 16
GPIO_AFRL_AFRL4_len EQU 4
GPIO_AFRL_AFRL3 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL3_ofs EQU 12
GPIO_AFRL_AFRL3_len EQU 4
GPIO_AFRL_AFRL2 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL2_ofs EQU 8
GPIO_AFRL_AFRL2_len EQU 4
GPIO_AFRL_AFRL1 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL1_ofs EQU 4
GPIO_AFRL_AFRL1_len EQU 4
GPIO_AFRL_AFRL0 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL0_ofs EQU 0
GPIO_AFRL_AFRL0_len EQU 4
; GPIOA_AFRH fields:
GPIO_AFRH_AFRH15 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH15_ofs EQU 28
GPIO_AFRH_AFRH15_len EQU 4
GPIO_AFRH_AFRH14 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH14_ofs EQU 24
GPIO_AFRH_AFRH14_len EQU 4
GPIO_AFRH_AFRH13 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH13_ofs EQU 20
GPIO_AFRH_AFRH13_len EQU 4
GPIO_AFRH_AFRH12 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH12_ofs EQU 16
GPIO_AFRH_AFRH12_len EQU 4
GPIO_AFRH_AFRH11 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH11_ofs EQU 12
GPIO_AFRH_AFRH11_len EQU 4
GPIO_AFRH_AFRH10 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH10_ofs EQU 8
GPIO_AFRH_AFRH10_len EQU 4
GPIO_AFRH_AFRH9 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH9_ofs EQU 4
GPIO_AFRH_AFRH9_len EQU 4
GPIO_AFRH_AFRH8 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH8_ofs EQU 0
GPIO_AFRH_AFRH8_len EQU 4
; GPIOA_BRR fields:
GPIO_BRR_BR0 EQU 0x00000001 ; Port x Reset bit y
GPIO_BRR_BR0_ofs EQU 0
GPIO_BRR_BR0_len EQU 1
GPIO_BRR_BR1 EQU 0x00000002 ; Port x Reset bit y
GPIO_BRR_BR1_ofs EQU 1
GPIO_BRR_BR1_len EQU 1
GPIO_BRR_BR2 EQU 0x00000004 ; Port x Reset bit y
GPIO_BRR_BR2_ofs EQU 2
GPIO_BRR_BR2_len EQU 1
GPIO_BRR_BR3 EQU 0x00000008 ; Port x Reset bit y
GPIO_BRR_BR3_ofs EQU 3
GPIO_BRR_BR3_len EQU 1
GPIO_BRR_BR4 EQU 0x00000010 ; Port x Reset bit y
GPIO_BRR_BR4_ofs EQU 4
GPIO_BRR_BR4_len EQU 1
GPIO_BRR_BR5 EQU 0x00000020 ; Port x Reset bit y
GPIO_BRR_BR5_ofs EQU 5
GPIO_BRR_BR5_len EQU 1
GPIO_BRR_BR6 EQU 0x00000040 ; Port x Reset bit y
GPIO_BRR_BR6_ofs EQU 6
GPIO_BRR_BR6_len EQU 1
GPIO_BRR_BR7 EQU 0x00000080 ; Port x Reset bit y
GPIO_BRR_BR7_ofs EQU 7
GPIO_BRR_BR7_len EQU 1
GPIO_BRR_BR8 EQU 0x00000100 ; Port x Reset bit y
GPIO_BRR_BR8_ofs EQU 8
GPIO_BRR_BR8_len EQU 1
GPIO_BRR_BR9 EQU 0x00000200 ; Port x Reset bit y
GPIO_BRR_BR9_ofs EQU 9
GPIO_BRR_BR9_len EQU 1
GPIO_BRR_BR10 EQU 0x00000400 ; Port x Reset bit y
GPIO_BRR_BR10_ofs EQU 10
GPIO_BRR_BR10_len EQU 1
GPIO_BRR_BR11 EQU 0x00000800 ; Port x Reset bit y
GPIO_BRR_BR11_ofs EQU 11
GPIO_BRR_BR11_len EQU 1
GPIO_BRR_BR12 EQU 0x00001000 ; Port x Reset bit y
GPIO_BRR_BR12_ofs EQU 12
GPIO_BRR_BR12_len EQU 1
GPIO_BRR_BR13 EQU 0x00002000 ; Port x Reset bit y
GPIO_BRR_BR13_ofs EQU 13
GPIO_BRR_BR13_len EQU 1
GPIO_BRR_BR14 EQU 0x00004000 ; Port x Reset bit y
GPIO_BRR_BR14_ofs EQU 14
GPIO_BRR_BR14_len EQU 1
GPIO_BRR_BR15 EQU 0x00008000 ; Port x Reset bit y
GPIO_BRR_BR15_ofs EQU 15
GPIO_BRR_BR15_len EQU 1
; ---- GPIOB -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOB base address:
GPIOB_BASE EQU 0x48000400
; GPIOB registers:
GPIOB_MODER EQU (GPIOB_BASE + 0x0) ; GPIO port mode register
GPIOB_OTYPER EQU (GPIOB_BASE + 0x4) ; GPIO port output type register
GPIOB_OSPEEDR EQU (GPIOB_BASE + 0x8) ; GPIO port output speed register
GPIOB_PUPDR EQU (GPIOB_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOB_IDR EQU (GPIOB_BASE + 0x10) ; GPIO port input data register
GPIOB_ODR EQU (GPIOB_BASE + 0x14) ; GPIO port output data register
GPIOB_BSRR EQU (GPIOB_BASE + 0x18) ; GPIO port bit set/reset register
GPIOB_LCKR EQU (GPIOB_BASE + 0x1c) ; GPIO port configuration lock register
GPIOB_AFRL EQU (GPIOB_BASE + 0x20) ; GPIO alternate function low register
GPIOB_AFRH EQU (GPIOB_BASE + 0x24) ; GPIO alternate function high register
GPIOB_BRR EQU (GPIOB_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOC -------------------------------------------------
; Desc: None
; GPIOC base address:
GPIOC_BASE EQU 0x48000800
; GPIOC registers:
GPIOC_MODER EQU (GPIOC_BASE + 0x0) ; GPIO port mode register
GPIOC_OTYPER EQU (GPIOC_BASE + 0x4) ; GPIO port output type register
GPIOC_OSPEEDR EQU (GPIOC_BASE + 0x8) ; GPIO port output speed register
GPIOC_PUPDR EQU (GPIOC_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOC_IDR EQU (GPIOC_BASE + 0x10) ; GPIO port input data register
GPIOC_ODR EQU (GPIOC_BASE + 0x14) ; GPIO port output data register
GPIOC_BSRR EQU (GPIOC_BASE + 0x18) ; GPIO port bit set/reset register
GPIOC_LCKR EQU (GPIOC_BASE + 0x1c) ; GPIO port configuration lock register
GPIOC_AFRL EQU (GPIOC_BASE + 0x20) ; GPIO alternate function low register
GPIOC_AFRH EQU (GPIOC_BASE + 0x24) ; GPIO alternate function high register
GPIOC_BRR EQU (GPIOC_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOD -------------------------------------------------
; Desc: None
; GPIOD base address:
GPIOD_BASE EQU 0x48000c00
; GPIOD registers:
GPIOD_MODER EQU (GPIOD_BASE + 0x0) ; GPIO port mode register
GPIOD_OTYPER EQU (GPIOD_BASE + 0x4) ; GPIO port output type register
GPIOD_OSPEEDR EQU (GPIOD_BASE + 0x8) ; GPIO port output speed register
GPIOD_PUPDR EQU (GPIOD_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOD_IDR EQU (GPIOD_BASE + 0x10) ; GPIO port input data register
GPIOD_ODR EQU (GPIOD_BASE + 0x14) ; GPIO port output data register
GPIOD_BSRR EQU (GPIOD_BASE + 0x18) ; GPIO port bit set/reset register
GPIOD_LCKR EQU (GPIOD_BASE + 0x1c) ; GPIO port configuration lock register
GPIOD_AFRL EQU (GPIOD_BASE + 0x20) ; GPIO alternate function low register
GPIOD_AFRH EQU (GPIOD_BASE + 0x24) ; GPIO alternate function high register
GPIOD_BRR EQU (GPIOD_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOE -------------------------------------------------
; Desc: None
; GPIOE base address:
GPIOE_BASE EQU 0x48001000
; GPIOE registers:
GPIOE_MODER EQU (GPIOE_BASE + 0x0) ; GPIO port mode register
GPIOE_OTYPER EQU (GPIOE_BASE + 0x4) ; GPIO port output type register
GPIOE_OSPEEDR EQU (GPIOE_BASE + 0x8) ; GPIO port output speed register
GPIOE_PUPDR EQU (GPIOE_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOE_IDR EQU (GPIOE_BASE + 0x10) ; GPIO port input data register
GPIOE_ODR EQU (GPIOE_BASE + 0x14) ; GPIO port output data register
GPIOE_BSRR EQU (GPIOE_BASE + 0x18) ; GPIO port bit set/reset register
GPIOE_LCKR EQU (GPIOE_BASE + 0x1c) ; GPIO port configuration lock register
GPIOE_AFRL EQU (GPIOE_BASE + 0x20) ; GPIO alternate function low register
GPIOE_AFRH EQU (GPIOE_BASE + 0x24) ; GPIO alternate function high register
GPIOE_BRR EQU (GPIOE_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOF -------------------------------------------------
; Desc: None
; GPIOF base address:
GPIOF_BASE EQU 0x48001400
; GPIOF registers:
GPIOF_MODER EQU (GPIOF_BASE + 0x0) ; GPIO port mode register
GPIOF_OTYPER EQU (GPIOF_BASE + 0x4) ; GPIO port output type register
GPIOF_OSPEEDR EQU (GPIOF_BASE + 0x8) ; GPIO port output speed register
GPIOF_PUPDR EQU (GPIOF_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOF_IDR EQU (GPIOF_BASE + 0x10) ; GPIO port input data register
GPIOF_ODR EQU (GPIOF_BASE + 0x14) ; GPIO port output data register
GPIOF_BSRR EQU (GPIOF_BASE + 0x18) ; GPIO port bit set/reset register
GPIOF_LCKR EQU (GPIOF_BASE + 0x1c) ; GPIO port configuration lock register
GPIOF_AFRL EQU (GPIOF_BASE + 0x20) ; GPIO alternate function low register
GPIOF_AFRH EQU (GPIOF_BASE + 0x24) ; GPIO alternate function high register
GPIOF_BRR EQU (GPIOF_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- TSC ---------------------------------------------------
; Desc: Touch sensing controller
; TSC base address:
TSC_BASE EQU 0x40024000
; TSC registers:
TSC_CR EQU (TSC_BASE + 0x0) ; control register
TSC_IER EQU (TSC_BASE + 0x4) ; interrupt enable register
TSC_ICR EQU (TSC_BASE + 0x8) ; interrupt clear register
TSC_ISR EQU (TSC_BASE + 0xc) ; interrupt status register
TSC_IOHCR EQU (TSC_BASE + 0x10) ; I/O hysteresis control register
TSC_IOASCR EQU (TSC_BASE + 0x18) ; I/O analog switch control register
TSC_IOSCR EQU (TSC_BASE + 0x20) ; I/O sampling control register
TSC_IOCCR EQU (TSC_BASE + 0x28) ; I/O channel control register
TSC_IOGCSR EQU (TSC_BASE + 0x30) ; I/O group control status register
TSC_IOG1CR EQU (TSC_BASE + 0x34) ; I/O group x counter register
TSC_IOG2CR EQU (TSC_BASE + 0x38) ; I/O group x counter register
TSC_IOG3CR EQU (TSC_BASE + 0x3c) ; I/O group x counter register
TSC_IOG4CR EQU (TSC_BASE + 0x40) ; I/O group x counter register
TSC_IOG5CR EQU (TSC_BASE + 0x44) ; I/O group x counter register
TSC_IOG6CR EQU (TSC_BASE + 0x48) ; I/O group x counter register
TSC_IOG7CR EQU (TSC_BASE + 0x4c) ; I/O group x counter register
TSC_IOG8CR EQU (TSC_BASE + 0x50) ; I/O group x counter register
; TSC_CR fields:
TSC_CR_CTPH EQU 0xf0000000 ; Charge transfer pulse high
TSC_CR_CTPH_ofs EQU 28
TSC_CR_CTPH_len EQU 4
TSC_CR_CTPL EQU 0x0f000000 ; Charge transfer pulse low
TSC_CR_CTPL_ofs EQU 24
TSC_CR_CTPL_len EQU 4
TSC_CR_SSD EQU 0x00fe0000 ; Spread spectrum deviation
TSC_CR_SSD_ofs EQU 17
TSC_CR_SSD_len EQU 7
TSC_CR_SSE EQU 0x00010000 ; Spread spectrum enable
TSC_CR_SSE_ofs EQU 16
TSC_CR_SSE_len EQU 1
TSC_CR_SSPSC EQU 0x00008000 ; Spread spectrum prescaler
TSC_CR_SSPSC_ofs EQU 15
TSC_CR_SSPSC_len EQU 1
TSC_CR_PGPSC EQU 0x00007000 ; pulse generator prescaler
TSC_CR_PGPSC_ofs EQU 12
TSC_CR_PGPSC_len EQU 3
TSC_CR_MCV EQU 0x000000e0 ; Max count value
TSC_CR_MCV_ofs EQU 5
TSC_CR_MCV_len EQU 3
TSC_CR_IODEF EQU 0x00000010 ; I/O Default mode
TSC_CR_IODEF_ofs EQU 4
TSC_CR_IODEF_len EQU 1
TSC_CR_SYNCPOL EQU 0x00000008 ; Synchronization pin polarity
TSC_CR_SYNCPOL_ofs EQU 3
TSC_CR_SYNCPOL_len EQU 1
TSC_CR_AM EQU 0x00000004 ; Acquisition mode
TSC_CR_AM_ofs EQU 2
TSC_CR_AM_len EQU 1
TSC_CR_START EQU 0x00000002 ; Start a new acquisition
TSC_CR_START_ofs EQU 1
TSC_CR_START_len EQU 1
TSC_CR_TSCE EQU 0x00000001 ; Touch sensing controller enable
TSC_CR_TSCE_ofs EQU 0
TSC_CR_TSCE_len EQU 1
; TSC_IER fields:
TSC_IER_MCEIE EQU 0x00000002 ; Max count error interrupt enable
TSC_IER_MCEIE_ofs EQU 1
TSC_IER_MCEIE_len EQU 1
TSC_IER_EOAIE EQU 0x00000001 ; End of acquisition interrupt enable
TSC_IER_EOAIE_ofs EQU 0
TSC_IER_EOAIE_len EQU 1
; TSC_ICR fields:
TSC_ICR_MCEIC EQU 0x00000002 ; Max count error interrupt clear
TSC_ICR_MCEIC_ofs EQU 1
TSC_ICR_MCEIC_len EQU 1
TSC_ICR_EOAIC EQU 0x00000001 ; End of acquisition interrupt clear
TSC_ICR_EOAIC_ofs EQU 0
TSC_ICR_EOAIC_len EQU 1
; TSC_ISR fields:
TSC_ISR_MCEF EQU 0x00000002 ; Max count error flag
TSC_ISR_MCEF_ofs EQU 1
TSC_ISR_MCEF_len EQU 1
TSC_ISR_EOAF EQU 0x00000001 ; End of acquisition flag
TSC_ISR_EOAF_ofs EQU 0
TSC_ISR_EOAF_len EQU 1
; TSC_IOHCR fields:
TSC_IOHCR_G1_IO1 EQU 0x00000001 ; G1_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO1_ofs EQU 0
TSC_IOHCR_G1_IO1_len EQU 1
TSC_IOHCR_G1_IO2 EQU 0x00000002 ; G1_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO2_ofs EQU 1
TSC_IOHCR_G1_IO2_len EQU 1
TSC_IOHCR_G1_IO3 EQU 0x00000004 ; G1_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO3_ofs EQU 2
TSC_IOHCR_G1_IO3_len EQU 1
TSC_IOHCR_G1_IO4 EQU 0x00000008 ; G1_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO4_ofs EQU 3
TSC_IOHCR_G1_IO4_len EQU 1
TSC_IOHCR_G2_IO1 EQU 0x00000010 ; G2_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO1_ofs EQU 4
TSC_IOHCR_G2_IO1_len EQU 1
TSC_IOHCR_G2_IO2 EQU 0x00000020 ; G2_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO2_ofs EQU 5
TSC_IOHCR_G2_IO2_len EQU 1
TSC_IOHCR_G2_IO3 EQU 0x00000040 ; G2_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO3_ofs EQU 6
TSC_IOHCR_G2_IO3_len EQU 1
TSC_IOHCR_G2_IO4 EQU 0x00000080 ; G2_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO4_ofs EQU 7
TSC_IOHCR_G2_IO4_len EQU 1
TSC_IOHCR_G3_IO1 EQU 0x00000100 ; G3_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO1_ofs EQU 8
TSC_IOHCR_G3_IO1_len EQU 1
TSC_IOHCR_G3_IO2 EQU 0x00000200 ; G3_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO2_ofs EQU 9
TSC_IOHCR_G3_IO2_len EQU 1
TSC_IOHCR_G3_IO3 EQU 0x00000400 ; G3_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO3_ofs EQU 10
TSC_IOHCR_G3_IO3_len EQU 1
TSC_IOHCR_G3_IO4 EQU 0x00000800 ; G3_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO4_ofs EQU 11
TSC_IOHCR_G3_IO4_len EQU 1
TSC_IOHCR_G4_IO1 EQU 0x00001000 ; G4_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO1_ofs EQU 12
TSC_IOHCR_G4_IO1_len EQU 1
TSC_IOHCR_G4_IO2 EQU 0x00002000 ; G4_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO2_ofs EQU 13
TSC_IOHCR_G4_IO2_len EQU 1
TSC_IOHCR_G4_IO3 EQU 0x00004000 ; G4_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO3_ofs EQU 14
TSC_IOHCR_G4_IO3_len EQU 1
TSC_IOHCR_G4_IO4 EQU 0x00008000 ; G4_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO4_ofs EQU 15
TSC_IOHCR_G4_IO4_len EQU 1
TSC_IOHCR_G5_IO1 EQU 0x00010000 ; G5_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO1_ofs EQU 16
TSC_IOHCR_G5_IO1_len EQU 1
TSC_IOHCR_G5_IO2 EQU 0x00020000 ; G5_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO2_ofs EQU 17
TSC_IOHCR_G5_IO2_len EQU 1
TSC_IOHCR_G5_IO3 EQU 0x00040000 ; G5_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO3_ofs EQU 18
TSC_IOHCR_G5_IO3_len EQU 1
TSC_IOHCR_G5_IO4 EQU 0x00080000 ; G5_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO4_ofs EQU 19
TSC_IOHCR_G5_IO4_len EQU 1
TSC_IOHCR_G6_IO1 EQU 0x00100000 ; G6_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO1_ofs EQU 20
TSC_IOHCR_G6_IO1_len EQU 1
TSC_IOHCR_G6_IO2 EQU 0x00200000 ; G6_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO2_ofs EQU 21
TSC_IOHCR_G6_IO2_len EQU 1
TSC_IOHCR_G6_IO3 EQU 0x00400000 ; G6_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO3_ofs EQU 22
TSC_IOHCR_G6_IO3_len EQU 1
TSC_IOHCR_G6_IO4 EQU 0x00800000 ; G6_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO4_ofs EQU 23
TSC_IOHCR_G6_IO4_len EQU 1
TSC_IOHCR_G7_IO1 EQU 0x01000000 ; G7_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO1_ofs EQU 24
TSC_IOHCR_G7_IO1_len EQU 1
TSC_IOHCR_G7_IO2 EQU 0x02000000 ; G7_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO2_ofs EQU 25
TSC_IOHCR_G7_IO2_len EQU 1
TSC_IOHCR_G7_IO3 EQU 0x04000000 ; G7_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO3_ofs EQU 26
TSC_IOHCR_G7_IO3_len EQU 1
TSC_IOHCR_G7_IO4 EQU 0x08000000 ; G7_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO4_ofs EQU 27
TSC_IOHCR_G7_IO4_len EQU 1
TSC_IOHCR_G8_IO1 EQU 0x10000000 ; G8_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO1_ofs EQU 28
TSC_IOHCR_G8_IO1_len EQU 1
TSC_IOHCR_G8_IO2 EQU 0x20000000 ; G8_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO2_ofs EQU 29
TSC_IOHCR_G8_IO2_len EQU 1
TSC_IOHCR_G8_IO3 EQU 0x40000000 ; G8_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO3_ofs EQU 30
TSC_IOHCR_G8_IO3_len EQU 1
TSC_IOHCR_G8_IO4 EQU 0x80000000 ; G8_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO4_ofs EQU 31
TSC_IOHCR_G8_IO4_len EQU 1
; TSC_IOASCR fields:
TSC_IOASCR_G1_IO1 EQU 0x00000001 ; G1_IO1 analog switch enable
TSC_IOASCR_G1_IO1_ofs EQU 0
TSC_IOASCR_G1_IO1_len EQU 1
TSC_IOASCR_G1_IO2 EQU 0x00000002 ; G1_IO2 analog switch enable
TSC_IOASCR_G1_IO2_ofs EQU 1
TSC_IOASCR_G1_IO2_len EQU 1
TSC_IOASCR_G1_IO3 EQU 0x00000004 ; G1_IO3 analog switch enable
TSC_IOASCR_G1_IO3_ofs EQU 2
TSC_IOASCR_G1_IO3_len EQU 1
TSC_IOASCR_G1_IO4 EQU 0x00000008 ; G1_IO4 analog switch enable
TSC_IOASCR_G1_IO4_ofs EQU 3
TSC_IOASCR_G1_IO4_len EQU 1
TSC_IOASCR_G2_IO1 EQU 0x00000010 ; G2_IO1 analog switch enable
TSC_IOASCR_G2_IO1_ofs EQU 4
TSC_IOASCR_G2_IO1_len EQU 1
TSC_IOASCR_G2_IO2 EQU 0x00000020 ; G2_IO2 analog switch enable
TSC_IOASCR_G2_IO2_ofs EQU 5
TSC_IOASCR_G2_IO2_len EQU 1
TSC_IOASCR_G2_IO3 EQU 0x00000040 ; G2_IO3 analog switch enable
TSC_IOASCR_G2_IO3_ofs EQU 6
TSC_IOASCR_G2_IO3_len EQU 1
TSC_IOASCR_G2_IO4 EQU 0x00000080 ; G2_IO4 analog switch enable
TSC_IOASCR_G2_IO4_ofs EQU 7
TSC_IOASCR_G2_IO4_len EQU 1
TSC_IOASCR_G3_IO1 EQU 0x00000100 ; G3_IO1 analog switch enable
TSC_IOASCR_G3_IO1_ofs EQU 8
TSC_IOASCR_G3_IO1_len EQU 1
TSC_IOASCR_G3_IO2 EQU 0x00000200 ; G3_IO2 analog switch enable
TSC_IOASCR_G3_IO2_ofs EQU 9
TSC_IOASCR_G3_IO2_len EQU 1
TSC_IOASCR_G3_IO3 EQU 0x00000400 ; G3_IO3 analog switch enable
TSC_IOASCR_G3_IO3_ofs EQU 10
TSC_IOASCR_G3_IO3_len EQU 1
TSC_IOASCR_G3_IO4 EQU 0x00000800 ; G3_IO4 analog switch enable
TSC_IOASCR_G3_IO4_ofs EQU 11
TSC_IOASCR_G3_IO4_len EQU 1
TSC_IOASCR_G4_IO1 EQU 0x00001000 ; G4_IO1 analog switch enable
TSC_IOASCR_G4_IO1_ofs EQU 12
TSC_IOASCR_G4_IO1_len EQU 1
TSC_IOASCR_G4_IO2 EQU 0x00002000 ; G4_IO2 analog switch enable
TSC_IOASCR_G4_IO2_ofs EQU 13
TSC_IOASCR_G4_IO2_len EQU 1
TSC_IOASCR_G4_IO3 EQU 0x00004000 ; G4_IO3 analog switch enable
TSC_IOASCR_G4_IO3_ofs EQU 14
TSC_IOASCR_G4_IO3_len EQU 1
TSC_IOASCR_G4_IO4 EQU 0x00008000 ; G4_IO4 analog switch enable
TSC_IOASCR_G4_IO4_ofs EQU 15
TSC_IOASCR_G4_IO4_len EQU 1
TSC_IOASCR_G5_IO1 EQU 0x00010000 ; G5_IO1 analog switch enable
TSC_IOASCR_G5_IO1_ofs EQU 16
TSC_IOASCR_G5_IO1_len EQU 1
TSC_IOASCR_G5_IO2 EQU 0x00020000 ; G5_IO2 analog switch enable
TSC_IOASCR_G5_IO2_ofs EQU 17
TSC_IOASCR_G5_IO2_len EQU 1
TSC_IOASCR_G5_IO3 EQU 0x00040000 ; G5_IO3 analog switch enable
TSC_IOASCR_G5_IO3_ofs EQU 18
TSC_IOASCR_G5_IO3_len EQU 1
TSC_IOASCR_G5_IO4 EQU 0x00080000 ; G5_IO4 analog switch enable
TSC_IOASCR_G5_IO4_ofs EQU 19
TSC_IOASCR_G5_IO4_len EQU 1
TSC_IOASCR_G6_IO1 EQU 0x00100000 ; G6_IO1 analog switch enable
TSC_IOASCR_G6_IO1_ofs EQU 20
TSC_IOASCR_G6_IO1_len EQU 1
TSC_IOASCR_G6_IO2 EQU 0x00200000 ; G6_IO2 analog switch enable
TSC_IOASCR_G6_IO2_ofs EQU 21
TSC_IOASCR_G6_IO2_len EQU 1
TSC_IOASCR_G6_IO3 EQU 0x00400000 ; G6_IO3 analog switch enable
TSC_IOASCR_G6_IO3_ofs EQU 22
TSC_IOASCR_G6_IO3_len EQU 1
TSC_IOASCR_G6_IO4 EQU 0x00800000 ; G6_IO4 analog switch enable
TSC_IOASCR_G6_IO4_ofs EQU 23
TSC_IOASCR_G6_IO4_len EQU 1
TSC_IOASCR_G7_IO1 EQU 0x01000000 ; G7_IO1 analog switch enable
TSC_IOASCR_G7_IO1_ofs EQU 24
TSC_IOASCR_G7_IO1_len EQU 1
TSC_IOASCR_G7_IO2 EQU 0x02000000 ; G7_IO2 analog switch enable
TSC_IOASCR_G7_IO2_ofs EQU 25
TSC_IOASCR_G7_IO2_len EQU 1
TSC_IOASCR_G7_IO3 EQU 0x04000000 ; G7_IO3 analog switch enable
TSC_IOASCR_G7_IO3_ofs EQU 26
TSC_IOASCR_G7_IO3_len EQU 1
TSC_IOASCR_G7_IO4 EQU 0x08000000 ; G7_IO4 analog switch enable
TSC_IOASCR_G7_IO4_ofs EQU 27
TSC_IOASCR_G7_IO4_len EQU 1
TSC_IOASCR_G8_IO1 EQU 0x10000000 ; G8_IO1 analog switch enable
TSC_IOASCR_G8_IO1_ofs EQU 28
TSC_IOASCR_G8_IO1_len EQU 1
TSC_IOASCR_G8_IO2 EQU 0x20000000 ; G8_IO2 analog switch enable
TSC_IOASCR_G8_IO2_ofs EQU 29
TSC_IOASCR_G8_IO2_len EQU 1
TSC_IOASCR_G8_IO3 EQU 0x40000000 ; G8_IO3 analog switch enable
TSC_IOASCR_G8_IO3_ofs EQU 30
TSC_IOASCR_G8_IO3_len EQU 1
TSC_IOASCR_G8_IO4 EQU 0x80000000 ; G8_IO4 analog switch enable
TSC_IOASCR_G8_IO4_ofs EQU 31
TSC_IOASCR_G8_IO4_len EQU 1
; TSC_IOSCR fields:
TSC_IOSCR_G1_IO1 EQU 0x00000001 ; G1_IO1 sampling mode
TSC_IOSCR_G1_IO1_ofs EQU 0
TSC_IOSCR_G1_IO1_len EQU 1
TSC_IOSCR_G1_IO2 EQU 0x00000002 ; G1_IO2 sampling mode
TSC_IOSCR_G1_IO2_ofs EQU 1
TSC_IOSCR_G1_IO2_len EQU 1
TSC_IOSCR_G1_IO3 EQU 0x00000004 ; G1_IO3 sampling mode
TSC_IOSCR_G1_IO3_ofs EQU 2
TSC_IOSCR_G1_IO3_len EQU 1
TSC_IOSCR_G1_IO4 EQU 0x00000008 ; G1_IO4 sampling mode
TSC_IOSCR_G1_IO4_ofs EQU 3
TSC_IOSCR_G1_IO4_len EQU 1
TSC_IOSCR_G2_IO1 EQU 0x00000010 ; G2_IO1 sampling mode
TSC_IOSCR_G2_IO1_ofs EQU 4
TSC_IOSCR_G2_IO1_len EQU 1
TSC_IOSCR_G2_IO2 EQU 0x00000020 ; G2_IO2 sampling mode
TSC_IOSCR_G2_IO2_ofs EQU 5
TSC_IOSCR_G2_IO2_len EQU 1
TSC_IOSCR_G2_IO3 EQU 0x00000040 ; G2_IO3 sampling mode
TSC_IOSCR_G2_IO3_ofs EQU 6
TSC_IOSCR_G2_IO3_len EQU 1
TSC_IOSCR_G2_IO4 EQU 0x00000080 ; G2_IO4 sampling mode
TSC_IOSCR_G2_IO4_ofs EQU 7
TSC_IOSCR_G2_IO4_len EQU 1
TSC_IOSCR_G3_IO1 EQU 0x00000100 ; G3_IO1 sampling mode
TSC_IOSCR_G3_IO1_ofs EQU 8
TSC_IOSCR_G3_IO1_len EQU 1
TSC_IOSCR_G3_IO2 EQU 0x00000200 ; G3_IO2 sampling mode
TSC_IOSCR_G3_IO2_ofs EQU 9
TSC_IOSCR_G3_IO2_len EQU 1
TSC_IOSCR_G3_IO3 EQU 0x00000400 ; G3_IO3 sampling mode
TSC_IOSCR_G3_IO3_ofs EQU 10
TSC_IOSCR_G3_IO3_len EQU 1
TSC_IOSCR_G3_IO4 EQU 0x00000800 ; G3_IO4 sampling mode
TSC_IOSCR_G3_IO4_ofs EQU 11
TSC_IOSCR_G3_IO4_len EQU 1
TSC_IOSCR_G4_IO1 EQU 0x00001000 ; G4_IO1 sampling mode
TSC_IOSCR_G4_IO1_ofs EQU 12
TSC_IOSCR_G4_IO1_len EQU 1
TSC_IOSCR_G4_IO2 EQU 0x00002000 ; G4_IO2 sampling mode
TSC_IOSCR_G4_IO2_ofs EQU 13
TSC_IOSCR_G4_IO2_len EQU 1
TSC_IOSCR_G4_IO3 EQU 0x00004000 ; G4_IO3 sampling mode
TSC_IOSCR_G4_IO3_ofs EQU 14
TSC_IOSCR_G4_IO3_len EQU 1
TSC_IOSCR_G4_IO4 EQU 0x00008000 ; G4_IO4 sampling mode
TSC_IOSCR_G4_IO4_ofs EQU 15
TSC_IOSCR_G4_IO4_len EQU 1
TSC_IOSCR_G5_IO1 EQU 0x00010000 ; G5_IO1 sampling mode
TSC_IOSCR_G5_IO1_ofs EQU 16
TSC_IOSCR_G5_IO1_len EQU 1
TSC_IOSCR_G5_IO2 EQU 0x00020000 ; G5_IO2 sampling mode
TSC_IOSCR_G5_IO2_ofs EQU 17
TSC_IOSCR_G5_IO2_len EQU 1
TSC_IOSCR_G5_IO3 EQU 0x00040000 ; G5_IO3 sampling mode
TSC_IOSCR_G5_IO3_ofs EQU 18
TSC_IOSCR_G5_IO3_len EQU 1
TSC_IOSCR_G5_IO4 EQU 0x00080000 ; G5_IO4 sampling mode
TSC_IOSCR_G5_IO4_ofs EQU 19
TSC_IOSCR_G5_IO4_len EQU 1
TSC_IOSCR_G6_IO1 EQU 0x00100000 ; G6_IO1 sampling mode
TSC_IOSCR_G6_IO1_ofs EQU 20
TSC_IOSCR_G6_IO1_len EQU 1
TSC_IOSCR_G6_IO2 EQU 0x00200000 ; G6_IO2 sampling mode
TSC_IOSCR_G6_IO2_ofs EQU 21
TSC_IOSCR_G6_IO2_len EQU 1
TSC_IOSCR_G6_IO3 EQU 0x00400000 ; G6_IO3 sampling mode
TSC_IOSCR_G6_IO3_ofs EQU 22
TSC_IOSCR_G6_IO3_len EQU 1
TSC_IOSCR_G6_IO4 EQU 0x00800000 ; G6_IO4 sampling mode
TSC_IOSCR_G6_IO4_ofs EQU 23
TSC_IOSCR_G6_IO4_len EQU 1
TSC_IOSCR_G7_IO1 EQU 0x01000000 ; G7_IO1 sampling mode
TSC_IOSCR_G7_IO1_ofs EQU 24
TSC_IOSCR_G7_IO1_len EQU 1
TSC_IOSCR_G7_IO2 EQU 0x02000000 ; G7_IO2 sampling mode
TSC_IOSCR_G7_IO2_ofs EQU 25
TSC_IOSCR_G7_IO2_len EQU 1
TSC_IOSCR_G7_IO3 EQU 0x04000000 ; G7_IO3 sampling mode
TSC_IOSCR_G7_IO3_ofs EQU 26
TSC_IOSCR_G7_IO3_len EQU 1
TSC_IOSCR_G7_IO4 EQU 0x08000000 ; G7_IO4 sampling mode
TSC_IOSCR_G7_IO4_ofs EQU 27
TSC_IOSCR_G7_IO4_len EQU 1
TSC_IOSCR_G8_IO1 EQU 0x10000000 ; G8_IO1 sampling mode
TSC_IOSCR_G8_IO1_ofs EQU 28
TSC_IOSCR_G8_IO1_len EQU 1
TSC_IOSCR_G8_IO2 EQU 0x20000000 ; G8_IO2 sampling mode
TSC_IOSCR_G8_IO2_ofs EQU 29
TSC_IOSCR_G8_IO2_len EQU 1
TSC_IOSCR_G8_IO3 EQU 0x40000000 ; G8_IO3 sampling mode
TSC_IOSCR_G8_IO3_ofs EQU 30
TSC_IOSCR_G8_IO3_len EQU 1
TSC_IOSCR_G8_IO4 EQU 0x80000000 ; G8_IO4 sampling mode
TSC_IOSCR_G8_IO4_ofs EQU 31
TSC_IOSCR_G8_IO4_len EQU 1
; TSC_IOCCR fields:
TSC_IOCCR_G1_IO1 EQU 0x00000001 ; G1_IO1 channel mode
TSC_IOCCR_G1_IO1_ofs EQU 0
TSC_IOCCR_G1_IO1_len EQU 1
TSC_IOCCR_G1_IO2 EQU 0x00000002 ; G1_IO2 channel mode
TSC_IOCCR_G1_IO2_ofs EQU 1
TSC_IOCCR_G1_IO2_len EQU 1
TSC_IOCCR_G1_IO3 EQU 0x00000004 ; G1_IO3 channel mode
TSC_IOCCR_G1_IO3_ofs EQU 2
TSC_IOCCR_G1_IO3_len EQU 1
TSC_IOCCR_G1_IO4 EQU 0x00000008 ; G1_IO4 channel mode
TSC_IOCCR_G1_IO4_ofs EQU 3
TSC_IOCCR_G1_IO4_len EQU 1
TSC_IOCCR_G2_IO1 EQU 0x00000010 ; G2_IO1 channel mode
TSC_IOCCR_G2_IO1_ofs EQU 4
TSC_IOCCR_G2_IO1_len EQU 1
TSC_IOCCR_G2_IO2 EQU 0x00000020 ; G2_IO2 channel mode
TSC_IOCCR_G2_IO2_ofs EQU 5
TSC_IOCCR_G2_IO2_len EQU 1
TSC_IOCCR_G2_IO3 EQU 0x00000040 ; G2_IO3 channel mode
TSC_IOCCR_G2_IO3_ofs EQU 6
TSC_IOCCR_G2_IO3_len EQU 1
TSC_IOCCR_G2_IO4 EQU 0x00000080 ; G2_IO4 channel mode
TSC_IOCCR_G2_IO4_ofs EQU 7
TSC_IOCCR_G2_IO4_len EQU 1
TSC_IOCCR_G3_IO1 EQU 0x00000100 ; G3_IO1 channel mode
TSC_IOCCR_G3_IO1_ofs EQU 8
TSC_IOCCR_G3_IO1_len EQU 1
TSC_IOCCR_G3_IO2 EQU 0x00000200 ; G3_IO2 channel mode
TSC_IOCCR_G3_IO2_ofs EQU 9
TSC_IOCCR_G3_IO2_len EQU 1
TSC_IOCCR_G3_IO3 EQU 0x00000400 ; G3_IO3 channel mode
TSC_IOCCR_G3_IO3_ofs EQU 10
TSC_IOCCR_G3_IO3_len EQU 1
TSC_IOCCR_G3_IO4 EQU 0x00000800 ; G3_IO4 channel mode
TSC_IOCCR_G3_IO4_ofs EQU 11
TSC_IOCCR_G3_IO4_len EQU 1
TSC_IOCCR_G4_IO1 EQU 0x00001000 ; G4_IO1 channel mode
TSC_IOCCR_G4_IO1_ofs EQU 12
TSC_IOCCR_G4_IO1_len EQU 1
TSC_IOCCR_G4_IO2 EQU 0x00002000 ; G4_IO2 channel mode
TSC_IOCCR_G4_IO2_ofs EQU 13
TSC_IOCCR_G4_IO2_len EQU 1
TSC_IOCCR_G4_IO3 EQU 0x00004000 ; G4_IO3 channel mode
TSC_IOCCR_G4_IO3_ofs EQU 14
TSC_IOCCR_G4_IO3_len EQU 1
TSC_IOCCR_G4_IO4 EQU 0x00008000 ; G4_IO4 channel mode
TSC_IOCCR_G4_IO4_ofs EQU 15
TSC_IOCCR_G4_IO4_len EQU 1
TSC_IOCCR_G5_IO1 EQU 0x00010000 ; G5_IO1 channel mode
TSC_IOCCR_G5_IO1_ofs EQU 16
TSC_IOCCR_G5_IO1_len EQU 1
TSC_IOCCR_G5_IO2 EQU 0x00020000 ; G5_IO2 channel mode
TSC_IOCCR_G5_IO2_ofs EQU 17
TSC_IOCCR_G5_IO2_len EQU 1
TSC_IOCCR_G5_IO3 EQU 0x00040000 ; G5_IO3 channel mode
TSC_IOCCR_G5_IO3_ofs EQU 18
TSC_IOCCR_G5_IO3_len EQU 1
TSC_IOCCR_G5_IO4 EQU 0x00080000 ; G5_IO4 channel mode
TSC_IOCCR_G5_IO4_ofs EQU 19
TSC_IOCCR_G5_IO4_len EQU 1
TSC_IOCCR_G6_IO1 EQU 0x00100000 ; G6_IO1 channel mode
TSC_IOCCR_G6_IO1_ofs EQU 20
TSC_IOCCR_G6_IO1_len EQU 1
TSC_IOCCR_G6_IO2 EQU 0x00200000 ; G6_IO2 channel mode
TSC_IOCCR_G6_IO2_ofs EQU 21
TSC_IOCCR_G6_IO2_len EQU 1
TSC_IOCCR_G6_IO3 EQU 0x00400000 ; G6_IO3 channel mode
TSC_IOCCR_G6_IO3_ofs EQU 22
TSC_IOCCR_G6_IO3_len EQU 1
TSC_IOCCR_G6_IO4 EQU 0x00800000 ; G6_IO4 channel mode
TSC_IOCCR_G6_IO4_ofs EQU 23
TSC_IOCCR_G6_IO4_len EQU 1
TSC_IOCCR_G7_IO1 EQU 0x01000000 ; G7_IO1 channel mode
TSC_IOCCR_G7_IO1_ofs EQU 24
TSC_IOCCR_G7_IO1_len EQU 1
TSC_IOCCR_G7_IO2 EQU 0x02000000 ; G7_IO2 channel mode
TSC_IOCCR_G7_IO2_ofs EQU 25
TSC_IOCCR_G7_IO2_len EQU 1
TSC_IOCCR_G7_IO3 EQU 0x04000000 ; G7_IO3 channel mode
TSC_IOCCR_G7_IO3_ofs EQU 26
TSC_IOCCR_G7_IO3_len EQU 1
TSC_IOCCR_G7_IO4 EQU 0x08000000 ; G7_IO4 channel mode
TSC_IOCCR_G7_IO4_ofs EQU 27
TSC_IOCCR_G7_IO4_len EQU 1
TSC_IOCCR_G8_IO1 EQU 0x10000000 ; G8_IO1 channel mode
TSC_IOCCR_G8_IO1_ofs EQU 28
TSC_IOCCR_G8_IO1_len EQU 1
TSC_IOCCR_G8_IO2 EQU 0x20000000 ; G8_IO2 channel mode
TSC_IOCCR_G8_IO2_ofs EQU 29
TSC_IOCCR_G8_IO2_len EQU 1
TSC_IOCCR_G8_IO3 EQU 0x40000000 ; G8_IO3 channel mode
TSC_IOCCR_G8_IO3_ofs EQU 30
TSC_IOCCR_G8_IO3_len EQU 1
TSC_IOCCR_G8_IO4 EQU 0x80000000 ; G8_IO4 channel mode
TSC_IOCCR_G8_IO4_ofs EQU 31
TSC_IOCCR_G8_IO4_len EQU 1
; TSC_IOGCSR fields:
TSC_IOGCSR_G8S EQU 0x00800000 ; Analog I/O group x status
TSC_IOGCSR_G8S_ofs EQU 23
TSC_IOGCSR_G8S_len EQU 1
TSC_IOGCSR_G7S EQU 0x00400000 ; Analog I/O group x status
TSC_IOGCSR_G7S_ofs EQU 22
TSC_IOGCSR_G7S_len EQU 1
TSC_IOGCSR_G6S EQU 0x00200000 ; Analog I/O group x status
TSC_IOGCSR_G6S_ofs EQU 21
TSC_IOGCSR_G6S_len EQU 1
TSC_IOGCSR_G5S EQU 0x00100000 ; Analog I/O group x status
TSC_IOGCSR_G5S_ofs EQU 20
TSC_IOGCSR_G5S_len EQU 1
TSC_IOGCSR_G4S EQU 0x00080000 ; Analog I/O group x status
TSC_IOGCSR_G4S_ofs EQU 19
TSC_IOGCSR_G4S_len EQU 1
TSC_IOGCSR_G3S EQU 0x00040000 ; Analog I/O group x status
TSC_IOGCSR_G3S_ofs EQU 18
TSC_IOGCSR_G3S_len EQU 1
TSC_IOGCSR_G2S EQU 0x00020000 ; Analog I/O group x status
TSC_IOGCSR_G2S_ofs EQU 17
TSC_IOGCSR_G2S_len EQU 1
TSC_IOGCSR_G1S EQU 0x00010000 ; Analog I/O group x status
TSC_IOGCSR_G1S_ofs EQU 16
TSC_IOGCSR_G1S_len EQU 1
TSC_IOGCSR_G8E EQU 0x00000080 ; Analog I/O group x enable
TSC_IOGCSR_G8E_ofs EQU 7
TSC_IOGCSR_G8E_len EQU 1
TSC_IOGCSR_G7E EQU 0x00000040 ; Analog I/O group x enable
TSC_IOGCSR_G7E_ofs EQU 6
TSC_IOGCSR_G7E_len EQU 1
TSC_IOGCSR_G6E EQU 0x00000020 ; Analog I/O group x enable
TSC_IOGCSR_G6E_ofs EQU 5
TSC_IOGCSR_G6E_len EQU 1
TSC_IOGCSR_G5E EQU 0x00000010 ; Analog I/O group x enable
TSC_IOGCSR_G5E_ofs EQU 4
TSC_IOGCSR_G5E_len EQU 1
TSC_IOGCSR_G4E EQU 0x00000008 ; Analog I/O group x enable
TSC_IOGCSR_G4E_ofs EQU 3
TSC_IOGCSR_G4E_len EQU 1
TSC_IOGCSR_G3E EQU 0x00000004 ; Analog I/O group x enable
TSC_IOGCSR_G3E_ofs EQU 2
TSC_IOGCSR_G3E_len EQU 1
TSC_IOGCSR_G2E EQU 0x00000002 ; Analog I/O group x enable
TSC_IOGCSR_G2E_ofs EQU 1
TSC_IOGCSR_G2E_len EQU 1
TSC_IOGCSR_G1E EQU 0x00000001 ; Analog I/O group x enable
TSC_IOGCSR_G1E_ofs EQU 0
TSC_IOGCSR_G1E_len EQU 1
; TSC_IOG1CR fields:
TSC_IOG1CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG1CR_CNT_ofs EQU 0
TSC_IOG1CR_CNT_len EQU 14
; TSC_IOG2CR fields:
TSC_IOG2CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG2CR_CNT_ofs EQU 0
TSC_IOG2CR_CNT_len EQU 14
; TSC_IOG3CR fields:
TSC_IOG3CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG3CR_CNT_ofs EQU 0
TSC_IOG3CR_CNT_len EQU 14
; TSC_IOG4CR fields:
TSC_IOG4CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG4CR_CNT_ofs EQU 0
TSC_IOG4CR_CNT_len EQU 14
; TSC_IOG5CR fields:
TSC_IOG5CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG5CR_CNT_ofs EQU 0
TSC_IOG5CR_CNT_len EQU 14
; TSC_IOG6CR fields:
TSC_IOG6CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG6CR_CNT_ofs EQU 0
TSC_IOG6CR_CNT_len EQU 14
; TSC_IOG7CR fields:
TSC_IOG7CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG7CR_CNT_ofs EQU 0
TSC_IOG7CR_CNT_len EQU 14
; TSC_IOG8CR fields:
TSC_IOG8CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG8CR_CNT_ofs EQU 0
TSC_IOG8CR_CNT_len EQU 14
; ---- CRC ---------------------------------------------------
; Desc: cyclic redundancy check calculation unit
; CRC base address:
CRC_BASE EQU 0x40023000
; CRC registers:
CRC_DR EQU (CRC_BASE + 0x0) ; Data register
CRC_IDR EQU (CRC_BASE + 0x4) ; Independent data register
CRC_CR EQU (CRC_BASE + 0x8) ; Control register
CRC_INIT EQU (CRC_BASE + 0x10) ; Initial CRC value
CRC_POL EQU (CRC_BASE + 0x14) ; CRC polynomial
; CRC_DR fields:
CRC_DR_DR EQU 0xffffffff ; Data register bits
CRC_DR_DR_ofs EQU 0
CRC_DR_DR_len EQU 32
; CRC_IDR fields:
CRC_IDR_IDR EQU 0x000000ff ; General-purpose 8-bit data register bits
CRC_IDR_IDR_ofs EQU 0
CRC_IDR_IDR_len EQU 8
; CRC_CR fields:
CRC_CR_RESET EQU 0x00000001 ; reset bit
CRC_CR_RESET_ofs EQU 0
CRC_CR_RESET_len EQU 1
CRC_CR_POLYSIZE EQU 0x00000018 ; Polynomial size
CRC_CR_POLYSIZE_ofs EQU 3
CRC_CR_POLYSIZE_len EQU 2
CRC_CR_REV_IN EQU 0x00000060 ; Reverse input data
CRC_CR_REV_IN_ofs EQU 5
CRC_CR_REV_IN_len EQU 2
CRC_CR_REV_OUT EQU 0x00000080 ; Reverse output data
CRC_CR_REV_OUT_ofs EQU 7
CRC_CR_REV_OUT_len EQU 1
; CRC_INIT fields:
CRC_INIT_INIT EQU 0xffffffff ; Programmable initial CRC value
CRC_INIT_INIT_ofs EQU 0
CRC_INIT_INIT_len EQU 32
; CRC_POL fields:
CRC_POL_POL EQU 0xffffffff ; Programmable polynomial
CRC_POL_POL_ofs EQU 0
CRC_POL_POL_len EQU 32
; ---- Flash -------------------------------------------------
; Desc: Flash
; Flash base address:
FLASH_BASE EQU 0x40022000
; Flash registers:
FLASH_ACR EQU (FLASH_BASE + 0x0) ; Flash access control register
FLASH_KEYR EQU (FLASH_BASE + 0x4) ; Flash key register
FLASH_OPTKEYR EQU (FLASH_BASE + 0x8) ; Flash option key register
FLASH_SR EQU (FLASH_BASE + 0xc) ; Flash status register
FLASH_CR EQU (FLASH_BASE + 0x10) ; Flash control register
FLASH_AR EQU (FLASH_BASE + 0x14) ; Flash address register
FLASH_OBR EQU (FLASH_BASE + 0x1c) ; Option byte register
FLASH_WRPR EQU (FLASH_BASE + 0x20) ; Write protection register
; FLASH_ACR fields:
FLASH_ACR_LATENCY EQU 0x00000007 ; LATENCY
FLASH_ACR_LATENCY_ofs EQU 0
FLASH_ACR_LATENCY_len EQU 3
FLASH_ACR_PRFTBE EQU 0x00000010 ; PRFTBE
FLASH_ACR_PRFTBE_ofs EQU 4
FLASH_ACR_PRFTBE_len EQU 1
FLASH_ACR_PRFTBS EQU 0x00000020 ; PRFTBS
FLASH_ACR_PRFTBS_ofs EQU 5
FLASH_ACR_PRFTBS_len EQU 1
; FLASH_KEYR fields:
FLASH_KEYR_FKEYR EQU 0xffffffff ; Flash Key
FLASH_KEYR_FKEYR_ofs EQU 0
FLASH_KEYR_FKEYR_len EQU 32
; FLASH_OPTKEYR fields:
FLASH_OPTKEYR_OPTKEYR EQU 0xffffffff ; Option byte key
FLASH_OPTKEYR_OPTKEYR_ofs EQU 0
FLASH_OPTKEYR_OPTKEYR_len EQU 32
; FLASH_SR fields:
FLASH_SR_EOP EQU 0x00000020 ; End of operation
FLASH_SR_EOP_ofs EQU 5
FLASH_SR_EOP_len EQU 1
FLASH_SR_WRPRT EQU 0x00000010 ; Write protection error
FLASH_SR_WRPRT_ofs EQU 4
FLASH_SR_WRPRT_len EQU 1
FLASH_SR_PGERR EQU 0x00000004 ; Programming error
FLASH_SR_PGERR_ofs EQU 2
FLASH_SR_PGERR_len EQU 1
FLASH_SR_BSY EQU 0x00000001 ; Busy
FLASH_SR_BSY_ofs EQU 0
FLASH_SR_BSY_len EQU 1
; FLASH_CR fields:
FLASH_CR_FORCE_OPTLOAD EQU 0x00002000 ; Force option byte loading
FLASH_CR_FORCE_OPTLOAD_ofs EQU 13
FLASH_CR_FORCE_OPTLOAD_len EQU 1
FLASH_CR_EOPIE EQU 0x00001000 ; End of operation interrupt enable
FLASH_CR_EOPIE_ofs EQU 12
FLASH_CR_EOPIE_len EQU 1
FLASH_CR_ERRIE EQU 0x00000400 ; Error interrupt enable
FLASH_CR_ERRIE_ofs EQU 10
FLASH_CR_ERRIE_len EQU 1
FLASH_CR_OPTWRE EQU 0x00000200 ; Option bytes write enable
FLASH_CR_OPTWRE_ofs EQU 9
FLASH_CR_OPTWRE_len EQU 1
FLASH_CR_LOCK EQU 0x00000080 ; Lock
FLASH_CR_LOCK_ofs EQU 7
FLASH_CR_LOCK_len EQU 1
FLASH_CR_STRT EQU 0x00000040 ; Start
FLASH_CR_STRT_ofs EQU 6
FLASH_CR_STRT_len EQU 1
FLASH_CR_OPTER EQU 0x00000020 ; Option byte erase
FLASH_CR_OPTER_ofs EQU 5
FLASH_CR_OPTER_len EQU 1
FLASH_CR_OPTPG EQU 0x00000010 ; Option byte programming
FLASH_CR_OPTPG_ofs EQU 4
FLASH_CR_OPTPG_len EQU 1
FLASH_CR_MER EQU 0x00000004 ; Mass erase
FLASH_CR_MER_ofs EQU 2
FLASH_CR_MER_len EQU 1
FLASH_CR_PER EQU 0x00000002 ; Page erase
FLASH_CR_PER_ofs EQU 1
FLASH_CR_PER_len EQU 1
FLASH_CR_PG EQU 0x00000001 ; Programming
FLASH_CR_PG_ofs EQU 0
FLASH_CR_PG_len EQU 1
; FLASH_AR fields:
FLASH_AR_FAR EQU 0xffffffff ; Flash address
FLASH_AR_FAR_ofs EQU 0
FLASH_AR_FAR_len EQU 32
; FLASH_OBR fields:
FLASH_OBR_OPTERR EQU 0x00000001 ; Option byte error
FLASH_OBR_OPTERR_ofs EQU 0
FLASH_OBR_OPTERR_len EQU 1
FLASH_OBR_LEVEL1_PROT EQU 0x00000002 ; Level 1 protection status
FLASH_OBR_LEVEL1_PROT_ofs EQU 1
FLASH_OBR_LEVEL1_PROT_len EQU 1
FLASH_OBR_LEVEL2_PROT EQU 0x00000004 ; Level 2 protection status
FLASH_OBR_LEVEL2_PROT_ofs EQU 2
FLASH_OBR_LEVEL2_PROT_len EQU 1
FLASH_OBR_WDG_SW EQU 0x00000100 ; WDG_SW
FLASH_OBR_WDG_SW_ofs EQU 8
FLASH_OBR_WDG_SW_len EQU 1
FLASH_OBR_nRST_STOP EQU 0x00000200 ; nRST_STOP
FLASH_OBR_nRST_STOP_ofs EQU 9
FLASH_OBR_nRST_STOP_len EQU 1
FLASH_OBR_nRST_STDBY EQU 0x00000400 ; nRST_STDBY
FLASH_OBR_nRST_STDBY_ofs EQU 10
FLASH_OBR_nRST_STDBY_len EQU 1
FLASH_OBR_BOOT1 EQU 0x00001000 ; BOOT1
FLASH_OBR_BOOT1_ofs EQU 12
FLASH_OBR_BOOT1_len EQU 1
FLASH_OBR_VDDA_MONITOR EQU 0x00002000 ; VDDA_MONITOR
FLASH_OBR_VDDA_MONITOR_ofs EQU 13
FLASH_OBR_VDDA_MONITOR_len EQU 1
FLASH_OBR_SRAM_PARITY_CHECK EQU 0x00004000 ; SRAM_PARITY_CHECK
FLASH_OBR_SRAM_PARITY_CHECK_ofs EQU 14
FLASH_OBR_SRAM_PARITY_CHECK_len EQU 1
FLASH_OBR_Data0 EQU 0x00ff0000 ; Data0
FLASH_OBR_Data0_ofs EQU 16
FLASH_OBR_Data0_len EQU 8
FLASH_OBR_Data1 EQU 0xff000000 ; Data1
FLASH_OBR_Data1_ofs EQU 24
FLASH_OBR_Data1_len EQU 8
; FLASH_WRPR fields:
FLASH_WRPR_WRP EQU 0xffffffff ; Write protect
FLASH_WRPR_WRP_ofs EQU 0
FLASH_WRPR_WRP_len EQU 32
; ---- RCC ---------------------------------------------------
; Desc: Reset and clock control
; RCC base address:
RCC_BASE EQU 0x40021000
; RCC registers:
RCC_CR EQU (RCC_BASE + 0x0) ; Clock control register
RCC_CFGR EQU (RCC_BASE + 0x4) ; Clock configuration register (RCC_CFGR)
RCC_CIR EQU (RCC_BASE + 0x8) ; Clock interrupt register (RCC_CIR)
RCC_APB2RSTR EQU (RCC_BASE + 0xc) ; APB2 peripheral reset register (RCC_APB2RSTR)
RCC_APB1RSTR EQU (RCC_BASE + 0x10) ; APB1 peripheral reset register (RCC_APB1RSTR)
RCC_AHBENR EQU (RCC_BASE + 0x14) ; AHB Peripheral Clock enable register (RCC_AHBENR)
RCC_APB2ENR EQU (RCC_BASE + 0x18) ; APB2 peripheral clock enable register (RCC_APB2ENR)
RCC_APB1ENR EQU (RCC_BASE + 0x1c) ; APB1 peripheral clock enable register (RCC_APB1ENR)
RCC_BDCR EQU (RCC_BASE + 0x20) ; Backup domain control register (RCC_BDCR)
RCC_CSR EQU (RCC_BASE + 0x24) ; Control/status register (RCC_CSR)
RCC_AHBRSTR EQU (RCC_BASE + 0x28) ; AHB peripheral reset register
RCC_CFGR2 EQU (RCC_BASE + 0x2c) ; Clock configuration register 2
RCC_CFGR3 EQU (RCC_BASE + 0x30) ; Clock configuration register 3
; RCC_CR fields:
RCC_CR_HSION EQU 0x00000001 ; Internal High Speed clock enable
RCC_CR_HSION_ofs EQU 0
RCC_CR_HSION_len EQU 1
RCC_CR_HSIRDY EQU 0x00000002 ; Internal High Speed clock ready flag
RCC_CR_HSIRDY_ofs EQU 1
RCC_CR_HSIRDY_len EQU 1
RCC_CR_HSITRIM EQU 0x000000f8 ; Internal High Speed clock trimming
RCC_CR_HSITRIM_ofs EQU 3
RCC_CR_HSITRIM_len EQU 5
RCC_CR_HSICAL EQU 0x0000ff00 ; Internal High Speed clock Calibration
RCC_CR_HSICAL_ofs EQU 8
RCC_CR_HSICAL_len EQU 8
RCC_CR_HSEON EQU 0x00010000 ; External High Speed clock enable
RCC_CR_HSEON_ofs EQU 16
RCC_CR_HSEON_len EQU 1
RCC_CR_HSERDY EQU 0x00020000 ; External High Speed clock ready flag
RCC_CR_HSERDY_ofs EQU 17
RCC_CR_HSERDY_len EQU 1
RCC_CR_HSEBYP EQU 0x00040000 ; External High Speed clock Bypass
RCC_CR_HSEBYP_ofs EQU 18
RCC_CR_HSEBYP_len EQU 1
RCC_CR_CSSON EQU 0x00080000 ; Clock Security System enable
RCC_CR_CSSON_ofs EQU 19
RCC_CR_CSSON_len EQU 1
RCC_CR_PLLON EQU 0x01000000 ; PLL enable
RCC_CR_PLLON_ofs EQU 24
RCC_CR_PLLON_len EQU 1
RCC_CR_PLLRDY EQU 0x02000000 ; PLL clock ready flag
RCC_CR_PLLRDY_ofs EQU 25
RCC_CR_PLLRDY_len EQU 1
; RCC_CFGR fields:
RCC_CFGR_SW EQU 0x00000003 ; System clock Switch
RCC_CFGR_SW_ofs EQU 0
RCC_CFGR_SW_len EQU 2
RCC_CFGR_SWS EQU 0x0000000c ; System Clock Switch Status
RCC_CFGR_SWS_ofs EQU 2
RCC_CFGR_SWS_len EQU 2
RCC_CFGR_HPRE EQU 0x000000f0 ; AHB prescaler
RCC_CFGR_HPRE_ofs EQU 4
RCC_CFGR_HPRE_len EQU 4
RCC_CFGR_PPRE1 EQU 0x00000700 ; APB Low speed prescaler (APB1)
RCC_CFGR_PPRE1_ofs EQU 8
RCC_CFGR_PPRE1_len EQU 3
RCC_CFGR_PPRE2 EQU 0x00003800 ; APB high speed prescaler (APB2)
RCC_CFGR_PPRE2_ofs EQU 11
RCC_CFGR_PPRE2_len EQU 3
RCC_CFGR_PLLSRC EQU 0x00010000 ; PLL entry clock source
RCC_CFGR_PLLSRC_ofs EQU 16
RCC_CFGR_PLLSRC_len EQU 1
RCC_CFGR_PLLXTPRE EQU 0x00020000 ; HSE divider for PLL entry
RCC_CFGR_PLLXTPRE_ofs EQU 17
RCC_CFGR_PLLXTPRE_len EQU 1
RCC_CFGR_PLLMUL EQU 0x003c0000 ; PLL Multiplication Factor
RCC_CFGR_PLLMUL_ofs EQU 18
RCC_CFGR_PLLMUL_len EQU 4
RCC_CFGR_USBPRES EQU 0x00400000 ; USB prescaler
RCC_CFGR_USBPRES_ofs EQU 22
RCC_CFGR_USBPRES_len EQU 1
RCC_CFGR_MCO EQU 0x07000000 ; Microcontroller clock output
RCC_CFGR_MCO_ofs EQU 24
RCC_CFGR_MCO_len EQU 3
RCC_CFGR_MCOF EQU 0x10000000 ; Microcontroller Clock Output Flag
RCC_CFGR_MCOF_ofs EQU 28
RCC_CFGR_MCOF_len EQU 1
RCC_CFGR_I2SSRC EQU 0x00800000 ; I2S external clock source selection
RCC_CFGR_I2SSRC_ofs EQU 23
RCC_CFGR_I2SSRC_len EQU 1
; RCC_CIR fields:
RCC_CIR_LSIRDYF EQU 0x00000001 ; LSI Ready Interrupt flag
RCC_CIR_LSIRDYF_ofs EQU 0
RCC_CIR_LSIRDYF_len EQU 1
RCC_CIR_LSERDYF EQU 0x00000002 ; LSE Ready Interrupt flag
RCC_CIR_LSERDYF_ofs EQU 1
RCC_CIR_LSERDYF_len EQU 1
RCC_CIR_HSIRDYF EQU 0x00000004 ; HSI Ready Interrupt flag
RCC_CIR_HSIRDYF_ofs EQU 2
RCC_CIR_HSIRDYF_len EQU 1
RCC_CIR_HSERDYF EQU 0x00000008 ; HSE Ready Interrupt flag
RCC_CIR_HSERDYF_ofs EQU 3
RCC_CIR_HSERDYF_len EQU 1
RCC_CIR_PLLRDYF EQU 0x00000010 ; PLL Ready Interrupt flag
RCC_CIR_PLLRDYF_ofs EQU 4
RCC_CIR_PLLRDYF_len EQU 1
RCC_CIR_CSSF EQU 0x00000080 ; Clock Security System Interrupt flag
RCC_CIR_CSSF_ofs EQU 7
RCC_CIR_CSSF_len EQU 1
RCC_CIR_LSIRDYIE EQU 0x00000100 ; LSI Ready Interrupt Enable
RCC_CIR_LSIRDYIE_ofs EQU 8
RCC_CIR_LSIRDYIE_len EQU 1
RCC_CIR_LSERDYIE EQU 0x00000200 ; LSE Ready Interrupt Enable
RCC_CIR_LSERDYIE_ofs EQU 9
RCC_CIR_LSERDYIE_len EQU 1
RCC_CIR_HSIRDYIE EQU 0x00000400 ; HSI Ready Interrupt Enable
RCC_CIR_HSIRDYIE_ofs EQU 10
RCC_CIR_HSIRDYIE_len EQU 1
RCC_CIR_HSERDYIE EQU 0x00000800 ; HSE Ready Interrupt Enable
RCC_CIR_HSERDYIE_ofs EQU 11
RCC_CIR_HSERDYIE_len EQU 1
RCC_CIR_PLLRDYIE EQU 0x00001000 ; PLL Ready Interrupt Enable
RCC_CIR_PLLRDYIE_ofs EQU 12
RCC_CIR_PLLRDYIE_len EQU 1
RCC_CIR_LSIRDYC EQU 0x00010000 ; LSI Ready Interrupt Clear
RCC_CIR_LSIRDYC_ofs EQU 16
RCC_CIR_LSIRDYC_len EQU 1
RCC_CIR_LSERDYC EQU 0x00020000 ; LSE Ready Interrupt Clear
RCC_CIR_LSERDYC_ofs EQU 17
RCC_CIR_LSERDYC_len EQU 1
RCC_CIR_HSIRDYC EQU 0x00040000 ; HSI Ready Interrupt Clear
RCC_CIR_HSIRDYC_ofs EQU 18
RCC_CIR_HSIRDYC_len EQU 1
RCC_CIR_HSERDYC EQU 0x00080000 ; HSE Ready Interrupt Clear
RCC_CIR_HSERDYC_ofs EQU 19
RCC_CIR_HSERDYC_len EQU 1
RCC_CIR_PLLRDYC EQU 0x00100000 ; PLL Ready Interrupt Clear
RCC_CIR_PLLRDYC_ofs EQU 20
RCC_CIR_PLLRDYC_len EQU 1
RCC_CIR_CSSC EQU 0x00800000 ; Clock security system interrupt clear
RCC_CIR_CSSC_ofs EQU 23
RCC_CIR_CSSC_len EQU 1
; RCC_APB2RSTR fields:
RCC_APB2RSTR_SYSCFGRST EQU 0x00000001 ; SYSCFG and COMP reset
RCC_APB2RSTR_SYSCFGRST_ofs EQU 0
RCC_APB2RSTR_SYSCFGRST_len EQU 1
RCC_APB2RSTR_TIM1RST EQU 0x00000800 ; TIM1 timer reset
RCC_APB2RSTR_TIM1RST_ofs EQU 11
RCC_APB2RSTR_TIM1RST_len EQU 1
RCC_APB2RSTR_SPI1RST EQU 0x00001000 ; SPI 1 reset
RCC_APB2RSTR_SPI1RST_ofs EQU 12
RCC_APB2RSTR_SPI1RST_len EQU 1
RCC_APB2RSTR_TIM8RST EQU 0x00002000 ; TIM8 timer reset
RCC_APB2RSTR_TIM8RST_ofs EQU 13
RCC_APB2RSTR_TIM8RST_len EQU 1
RCC_APB2RSTR_USART1RST EQU 0x00004000 ; USART1 reset
RCC_APB2RSTR_USART1RST_ofs EQU 14
RCC_APB2RSTR_USART1RST_len EQU 1
RCC_APB2RSTR_TIM15RST EQU 0x00010000 ; TIM15 timer reset
RCC_APB2RSTR_TIM15RST_ofs EQU 16
RCC_APB2RSTR_TIM15RST_len EQU 1
RCC_APB2RSTR_TIM16RST EQU 0x00020000 ; TIM16 timer reset
RCC_APB2RSTR_TIM16RST_ofs EQU 17
RCC_APB2RSTR_TIM16RST_len EQU 1
RCC_APB2RSTR_TIM17RST EQU 0x00040000 ; TIM17 timer reset
RCC_APB2RSTR_TIM17RST_ofs EQU 18
RCC_APB2RSTR_TIM17RST_len EQU 1
; RCC_APB1RSTR fields:
RCC_APB1RSTR_TIM2RST EQU 0x00000001 ; Timer 2 reset
RCC_APB1RSTR_TIM2RST_ofs EQU 0
RCC_APB1RSTR_TIM2RST_len EQU 1
RCC_APB1RSTR_TIM3RST EQU 0x00000002 ; Timer 3 reset
RCC_APB1RSTR_TIM3RST_ofs EQU 1
RCC_APB1RSTR_TIM3RST_len EQU 1
RCC_APB1RSTR_TIM4RST EQU 0x00000004 ; Timer 14 reset
RCC_APB1RSTR_TIM4RST_ofs EQU 2
RCC_APB1RSTR_TIM4RST_len EQU 1
RCC_APB1RSTR_TIM6RST EQU 0x00000010 ; Timer 6 reset
RCC_APB1RSTR_TIM6RST_ofs EQU 4
RCC_APB1RSTR_TIM6RST_len EQU 1
RCC_APB1RSTR_TIM7RST EQU 0x00000020 ; Timer 7 reset
RCC_APB1RSTR_TIM7RST_ofs EQU 5
RCC_APB1RSTR_TIM7RST_len EQU 1
RCC_APB1RSTR_WWDGRST EQU 0x00000800 ; Window watchdog reset
RCC_APB1RSTR_WWDGRST_ofs EQU 11
RCC_APB1RSTR_WWDGRST_len EQU 1
RCC_APB1RSTR_SPI2RST EQU 0x00004000 ; SPI2 reset
RCC_APB1RSTR_SPI2RST_ofs EQU 14
RCC_APB1RSTR_SPI2RST_len EQU 1
RCC_APB1RSTR_SPI3RST EQU 0x00008000 ; SPI3 reset
RCC_APB1RSTR_SPI3RST_ofs EQU 15
RCC_APB1RSTR_SPI3RST_len EQU 1
RCC_APB1RSTR_USART2RST EQU 0x00020000 ; USART 2 reset
RCC_APB1RSTR_USART2RST_ofs EQU 17
RCC_APB1RSTR_USART2RST_len EQU 1
RCC_APB1RSTR_USART3RST EQU 0x00040000 ; USART3 reset
RCC_APB1RSTR_USART3RST_ofs EQU 18
RCC_APB1RSTR_USART3RST_len EQU 1
RCC_APB1RSTR_UART4RST EQU 0x00080000 ; UART 4 reset
RCC_APB1RSTR_UART4RST_ofs EQU 19
RCC_APB1RSTR_UART4RST_len EQU 1
RCC_APB1RSTR_UART5RST EQU 0x00100000 ; UART 5 reset
RCC_APB1RSTR_UART5RST_ofs EQU 20
RCC_APB1RSTR_UART5RST_len EQU 1
RCC_APB1RSTR_I2C1RST EQU 0x00200000 ; I2C1 reset
RCC_APB1RSTR_I2C1RST_ofs EQU 21
RCC_APB1RSTR_I2C1RST_len EQU 1
RCC_APB1RSTR_I2C2RST EQU 0x00400000 ; I2C2 reset
RCC_APB1RSTR_I2C2RST_ofs EQU 22
RCC_APB1RSTR_I2C2RST_len EQU 1
RCC_APB1RSTR_USBRST EQU 0x00800000 ; USB reset
RCC_APB1RSTR_USBRST_ofs EQU 23
RCC_APB1RSTR_USBRST_len EQU 1
RCC_APB1RSTR_CANRST EQU 0x02000000 ; CAN reset
RCC_APB1RSTR_CANRST_ofs EQU 25
RCC_APB1RSTR_CANRST_len EQU 1
RCC_APB1RSTR_PWRRST EQU 0x10000000 ; Power interface reset
RCC_APB1RSTR_PWRRST_ofs EQU 28
RCC_APB1RSTR_PWRRST_len EQU 1
RCC_APB1RSTR_DACRST EQU 0x20000000 ; DAC interface reset
RCC_APB1RSTR_DACRST_ofs EQU 29
RCC_APB1RSTR_DACRST_len EQU 1
; RCC_AHBENR fields:
RCC_AHBENR_DMAEN EQU 0x00000001 ; DMA1 clock enable
RCC_AHBENR_DMAEN_ofs EQU 0
RCC_AHBENR_DMAEN_len EQU 1
RCC_AHBENR_DMA2EN EQU 0x00000002 ; DMA2 clock enable
RCC_AHBENR_DMA2EN_ofs EQU 1
RCC_AHBENR_DMA2EN_len EQU 1
RCC_AHBENR_SRAMEN EQU 0x00000004 ; SRAM interface clock enable
RCC_AHBENR_SRAMEN_ofs EQU 2
RCC_AHBENR_SRAMEN_len EQU 1
RCC_AHBENR_FLITFEN EQU 0x00000010 ; FLITF clock enable
RCC_AHBENR_FLITFEN_ofs EQU 4
RCC_AHBENR_FLITFEN_len EQU 1
RCC_AHBENR_CRCEN EQU 0x00000040 ; CRC clock enable
RCC_AHBENR_CRCEN_ofs EQU 6
RCC_AHBENR_CRCEN_len EQU 1
RCC_AHBENR_IOPAEN EQU 0x00020000 ; I/O port A clock enable
RCC_AHBENR_IOPAEN_ofs EQU 17
RCC_AHBENR_IOPAEN_len EQU 1
RCC_AHBENR_IOPBEN EQU 0x00040000 ; I/O port B clock enable
RCC_AHBENR_IOPBEN_ofs EQU 18
RCC_AHBENR_IOPBEN_len EQU 1
RCC_AHBENR_IOPCEN EQU 0x00080000 ; I/O port C clock enable
RCC_AHBENR_IOPCEN_ofs EQU 19
RCC_AHBENR_IOPCEN_len EQU 1
RCC_AHBENR_IOPDEN EQU 0x00100000 ; I/O port D clock enable
RCC_AHBENR_IOPDEN_ofs EQU 20
RCC_AHBENR_IOPDEN_len EQU 1
RCC_AHBENR_IOPEEN EQU 0x00200000 ; I/O port E clock enable
RCC_AHBENR_IOPEEN_ofs EQU 21
RCC_AHBENR_IOPEEN_len EQU 1
RCC_AHBENR_IOPFEN EQU 0x00400000 ; I/O port F clock enable
RCC_AHBENR_IOPFEN_ofs EQU 22
RCC_AHBENR_IOPFEN_len EQU 1
RCC_AHBENR_TSCEN EQU 0x01000000 ; Touch sensing controller clock enable
RCC_AHBENR_TSCEN_ofs EQU 24
RCC_AHBENR_TSCEN_len EQU 1
RCC_AHBENR_ADC12EN EQU 0x10000000 ; ADC1 and ADC2 clock enable
RCC_AHBENR_ADC12EN_ofs EQU 28
RCC_AHBENR_ADC12EN_len EQU 1
RCC_AHBENR_ADC34EN EQU 0x20000000 ; ADC3 and ADC4 clock enable
RCC_AHBENR_ADC34EN_ofs EQU 29
RCC_AHBENR_ADC34EN_len EQU 1
; RCC_APB2ENR fields:
RCC_APB2ENR_SYSCFGEN EQU 0x00000001 ; SYSCFG clock enable
RCC_APB2ENR_SYSCFGEN_ofs EQU 0
RCC_APB2ENR_SYSCFGEN_len EQU 1
RCC_APB2ENR_TIM1EN EQU 0x00000800 ; TIM1 Timer clock enable
RCC_APB2ENR_TIM1EN_ofs EQU 11
RCC_APB2ENR_TIM1EN_len EQU 1
RCC_APB2ENR_SPI1EN EQU 0x00001000 ; SPI 1 clock enable
RCC_APB2ENR_SPI1EN_ofs EQU 12
RCC_APB2ENR_SPI1EN_len EQU 1
RCC_APB2ENR_TIM8EN EQU 0x00002000 ; TIM8 Timer clock enable
RCC_APB2ENR_TIM8EN_ofs EQU 13
RCC_APB2ENR_TIM8EN_len EQU 1
RCC_APB2ENR_USART1EN EQU 0x00004000 ; USART1 clock enable
RCC_APB2ENR_USART1EN_ofs EQU 14
RCC_APB2ENR_USART1EN_len EQU 1
RCC_APB2ENR_TIM15EN EQU 0x00010000 ; TIM15 timer clock enable
RCC_APB2ENR_TIM15EN_ofs EQU 16
RCC_APB2ENR_TIM15EN_len EQU 1
RCC_APB2ENR_TIM16EN EQU 0x00020000 ; TIM16 timer clock enable
RCC_APB2ENR_TIM16EN_ofs EQU 17
RCC_APB2ENR_TIM16EN_len EQU 1
RCC_APB2ENR_TIM17EN EQU 0x00040000 ; TIM17 timer clock enable
RCC_APB2ENR_TIM17EN_ofs EQU 18
RCC_APB2ENR_TIM17EN_len EQU 1
; RCC_APB1ENR fields:
RCC_APB1ENR_TIM2EN EQU 0x00000001 ; Timer 2 clock enable
RCC_APB1ENR_TIM2EN_ofs EQU 0
RCC_APB1ENR_TIM2EN_len EQU 1
RCC_APB1ENR_TIM3EN EQU 0x00000002 ; Timer 3 clock enable
RCC_APB1ENR_TIM3EN_ofs EQU 1
RCC_APB1ENR_TIM3EN_len EQU 1
RCC_APB1ENR_TIM4EN EQU 0x00000004 ; Timer 4 clock enable
RCC_APB1ENR_TIM4EN_ofs EQU 2
RCC_APB1ENR_TIM4EN_len EQU 1
RCC_APB1ENR_TIM6EN EQU 0x00000010 ; Timer 6 clock enable
RCC_APB1ENR_TIM6EN_ofs EQU 4
RCC_APB1ENR_TIM6EN_len EQU 1
RCC_APB1ENR_TIM7EN EQU 0x00000020 ; Timer 7 clock enable
RCC_APB1ENR_TIM7EN_ofs EQU 5
RCC_APB1ENR_TIM7EN_len EQU 1
RCC_APB1ENR_WWDGEN EQU 0x00000800 ; Window watchdog clock enable
RCC_APB1ENR_WWDGEN_ofs EQU 11
RCC_APB1ENR_WWDGEN_len EQU 1
RCC_APB1ENR_SPI2EN EQU 0x00004000 ; SPI 2 clock enable
RCC_APB1ENR_SPI2EN_ofs EQU 14
RCC_APB1ENR_SPI2EN_len EQU 1
RCC_APB1ENR_SPI3EN EQU 0x00008000 ; SPI 3 clock enable
RCC_APB1ENR_SPI3EN_ofs EQU 15
RCC_APB1ENR_SPI3EN_len EQU 1
RCC_APB1ENR_USART2EN EQU 0x00020000 ; USART 2 clock enable
RCC_APB1ENR_USART2EN_ofs EQU 17
RCC_APB1ENR_USART2EN_len EQU 1
RCC_APB1ENR_I2C1EN EQU 0x00200000 ; I2C 1 clock enable
RCC_APB1ENR_I2C1EN_ofs EQU 21
RCC_APB1ENR_I2C1EN_len EQU 1
RCC_APB1ENR_I2C2EN EQU 0x00400000 ; I2C 2 clock enable
RCC_APB1ENR_I2C2EN_ofs EQU 22
RCC_APB1ENR_I2C2EN_len EQU 1
RCC_APB1ENR_USBEN EQU 0x00800000 ; USB clock enable
RCC_APB1ENR_USBEN_ofs EQU 23
RCC_APB1ENR_USBEN_len EQU 1
RCC_APB1ENR_CANEN EQU 0x02000000 ; CAN clock enable
RCC_APB1ENR_CANEN_ofs EQU 25
RCC_APB1ENR_CANEN_len EQU 1
RCC_APB1ENR_PWREN EQU 0x10000000 ; Power interface clock enable
RCC_APB1ENR_PWREN_ofs EQU 28
RCC_APB1ENR_PWREN_len EQU 1
RCC_APB1ENR_DACEN EQU 0x20000000 ; DAC interface clock enable
RCC_APB1ENR_DACEN_ofs EQU 29
RCC_APB1ENR_DACEN_len EQU 1
; RCC_BDCR fields:
RCC_BDCR_LSEON EQU 0x00000001 ; External Low Speed oscillator enable
RCC_BDCR_LSEON_ofs EQU 0
RCC_BDCR_LSEON_len EQU 1
RCC_BDCR_LSERDY EQU 0x00000002 ; External Low Speed oscillator ready
RCC_BDCR_LSERDY_ofs EQU 1
RCC_BDCR_LSERDY_len EQU 1
RCC_BDCR_LSEBYP EQU 0x00000004 ; External Low Speed oscillator bypass
RCC_BDCR_LSEBYP_ofs EQU 2
RCC_BDCR_LSEBYP_len EQU 1
RCC_BDCR_LSEDRV EQU 0x00000018 ; LSE oscillator drive capability
RCC_BDCR_LSEDRV_ofs EQU 3
RCC_BDCR_LSEDRV_len EQU 2
RCC_BDCR_RTCSEL EQU 0x00000300 ; RTC clock source selection
RCC_BDCR_RTCSEL_ofs EQU 8
RCC_BDCR_RTCSEL_len EQU 2
RCC_BDCR_RTCEN EQU 0x00008000 ; RTC clock enable
RCC_BDCR_RTCEN_ofs EQU 15
RCC_BDCR_RTCEN_len EQU 1
RCC_BDCR_BDRST EQU 0x00010000 ; Backup domain software reset
RCC_BDCR_BDRST_ofs EQU 16
RCC_BDCR_BDRST_len EQU 1
; RCC_CSR fields:
RCC_CSR_LSION EQU 0x00000001 ; Internal low speed oscillator enable
RCC_CSR_LSION_ofs EQU 0
RCC_CSR_LSION_len EQU 1
RCC_CSR_LSIRDY EQU 0x00000002 ; Internal low speed oscillator ready
RCC_CSR_LSIRDY_ofs EQU 1
RCC_CSR_LSIRDY_len EQU 1
RCC_CSR_RMVF EQU 0x01000000 ; Remove reset flag
RCC_CSR_RMVF_ofs EQU 24
RCC_CSR_RMVF_len EQU 1
RCC_CSR_OBLRSTF EQU 0x02000000 ; Option byte loader reset flag
RCC_CSR_OBLRSTF_ofs EQU 25
RCC_CSR_OBLRSTF_len EQU 1
RCC_CSR_PINRSTF EQU 0x04000000 ; PIN reset flag
RCC_CSR_PINRSTF_ofs EQU 26
RCC_CSR_PINRSTF_len EQU 1
RCC_CSR_PORRSTF EQU 0x08000000 ; POR/PDR reset flag
RCC_CSR_PORRSTF_ofs EQU 27
RCC_CSR_PORRSTF_len EQU 1
RCC_CSR_SFTRSTF EQU 0x10000000 ; Software reset flag
RCC_CSR_SFTRSTF_ofs EQU 28
RCC_CSR_SFTRSTF_len EQU 1
RCC_CSR_IWDGRSTF EQU 0x20000000 ; Independent watchdog reset flag
RCC_CSR_IWDGRSTF_ofs EQU 29
RCC_CSR_IWDGRSTF_len EQU 1
RCC_CSR_WWDGRSTF EQU 0x40000000 ; Window watchdog reset flag
RCC_CSR_WWDGRSTF_ofs EQU 30
RCC_CSR_WWDGRSTF_len EQU 1
RCC_CSR_LPWRRSTF EQU 0x80000000 ; Low-power reset flag
RCC_CSR_LPWRRSTF_ofs EQU 31
RCC_CSR_LPWRRSTF_len EQU 1
; RCC_AHBRSTR fields:
RCC_AHBRSTR_IOPARST EQU 0x00020000 ; I/O port A reset
RCC_AHBRSTR_IOPARST_ofs EQU 17
RCC_AHBRSTR_IOPARST_len EQU 1
RCC_AHBRSTR_IOPBRST EQU 0x00040000 ; I/O port B reset
RCC_AHBRSTR_IOPBRST_ofs EQU 18
RCC_AHBRSTR_IOPBRST_len EQU 1
RCC_AHBRSTR_IOPCRST EQU 0x00080000 ; I/O port C reset
RCC_AHBRSTR_IOPCRST_ofs EQU 19
RCC_AHBRSTR_IOPCRST_len EQU 1
RCC_AHBRSTR_IOPDRST EQU 0x00100000 ; I/O port D reset
RCC_AHBRSTR_IOPDRST_ofs EQU 20
RCC_AHBRSTR_IOPDRST_len EQU 1
RCC_AHBRSTR_IOPERST EQU 0x00200000 ; I/O port E reset
RCC_AHBRSTR_IOPERST_ofs EQU 21
RCC_AHBRSTR_IOPERST_len EQU 1
RCC_AHBRSTR_IOPFRST EQU 0x00400000 ; I/O port F reset
RCC_AHBRSTR_IOPFRST_ofs EQU 22
RCC_AHBRSTR_IOPFRST_len EQU 1
RCC_AHBRSTR_TSCRST EQU 0x01000000 ; Touch sensing controller reset
RCC_AHBRSTR_TSCRST_ofs EQU 24
RCC_AHBRSTR_TSCRST_len EQU 1
RCC_AHBRSTR_ADC12RST EQU 0x10000000 ; ADC1 and ADC2 reset
RCC_AHBRSTR_ADC12RST_ofs EQU 28
RCC_AHBRSTR_ADC12RST_len EQU 1
RCC_AHBRSTR_ADC34RST EQU 0x20000000 ; ADC3 and ADC4 reset
RCC_AHBRSTR_ADC34RST_ofs EQU 29
RCC_AHBRSTR_ADC34RST_len EQU 1
; RCC_CFGR2 fields:
RCC_CFGR2_PREDIV EQU 0x0000000f ; PREDIV division factor
RCC_CFGR2_PREDIV_ofs EQU 0
RCC_CFGR2_PREDIV_len EQU 4
RCC_CFGR2_ADC12PRES EQU 0x000001f0 ; ADC1 and ADC2 prescaler
RCC_CFGR2_ADC12PRES_ofs EQU 4
RCC_CFGR2_ADC12PRES_len EQU 5
RCC_CFGR2_ADC34PRES EQU 0x00003e00 ; ADC3 and ADC4 prescaler
RCC_CFGR2_ADC34PRES_ofs EQU 9
RCC_CFGR2_ADC34PRES_len EQU 5
; RCC_CFGR3 fields:
RCC_CFGR3_USART1SW EQU 0x00000003 ; USART1 clock source selection
RCC_CFGR3_USART1SW_ofs EQU 0
RCC_CFGR3_USART1SW_len EQU 2
RCC_CFGR3_I2C1SW EQU 0x00000010 ; I2C1 clock source selection
RCC_CFGR3_I2C1SW_ofs EQU 4
RCC_CFGR3_I2C1SW_len EQU 1
RCC_CFGR3_I2C2SW EQU 0x00000020 ; I2C2 clock source selection
RCC_CFGR3_I2C2SW_ofs EQU 5
RCC_CFGR3_I2C2SW_len EQU 1
RCC_CFGR3_USART2SW EQU 0x00030000 ; USART2 clock source selection
RCC_CFGR3_USART2SW_ofs EQU 16
RCC_CFGR3_USART2SW_len EQU 2
RCC_CFGR3_USART3SW EQU 0x000c0000 ; USART3 clock source selection
RCC_CFGR3_USART3SW_ofs EQU 18
RCC_CFGR3_USART3SW_len EQU 2
RCC_CFGR3_TIM1SW EQU 0x00000100 ; Timer1 clock source selection
RCC_CFGR3_TIM1SW_ofs EQU 8
RCC_CFGR3_TIM1SW_len EQU 1
RCC_CFGR3_TIM8SW EQU 0x00000200 ; Timer8 clock source selection
RCC_CFGR3_TIM8SW_ofs EQU 9
RCC_CFGR3_TIM8SW_len EQU 1
RCC_CFGR3_UART4SW EQU 0x00300000 ; UART4 clock source selection
RCC_CFGR3_UART4SW_ofs EQU 20
RCC_CFGR3_UART4SW_len EQU 2
RCC_CFGR3_UART5SW EQU 0x00c00000 ; UART5 clock source selection
RCC_CFGR3_UART5SW_ofs EQU 22
RCC_CFGR3_UART5SW_len EQU 2
; ---- DMA1 --------------------------------------------------
; Desc: DMA controller 1
; DMA1 base address:
DMA1_BASE EQU 0x40020000
; DMA1 registers:
DMA1_ISR EQU (DMA1_BASE + 0x0) ; DMA interrupt status register (DMA_ISR)
DMA1_IFCR EQU (DMA1_BASE + 0x4) ; DMA interrupt flag clear register (DMA_IFCR)
DMA1_CCR1 EQU (DMA1_BASE + 0x8) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR1 EQU (DMA1_BASE + 0xc) ; DMA channel 1 number of data register
DMA1_CPAR1 EQU (DMA1_BASE + 0x10) ; DMA channel 1 peripheral address register
DMA1_CMAR1 EQU (DMA1_BASE + 0x14) ; DMA channel 1 memory address register
DMA1_CCR2 EQU (DMA1_BASE + 0x1c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR2 EQU (DMA1_BASE + 0x20) ; DMA channel 2 number of data register
DMA1_CPAR2 EQU (DMA1_BASE + 0x24) ; DMA channel 2 peripheral address register
DMA1_CMAR2 EQU (DMA1_BASE + 0x28) ; DMA channel 2 memory address register
DMA1_CCR3 EQU (DMA1_BASE + 0x30) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR3 EQU (DMA1_BASE + 0x34) ; DMA channel 3 number of data register
DMA1_CPAR3 EQU (DMA1_BASE + 0x38) ; DMA channel 3 peripheral address register
DMA1_CMAR3 EQU (DMA1_BASE + 0x3c) ; DMA channel 3 memory address register
DMA1_CCR4 EQU (DMA1_BASE + 0x44) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR4 EQU (DMA1_BASE + 0x48) ; DMA channel 4 number of data register
DMA1_CPAR4 EQU (DMA1_BASE + 0x4c) ; DMA channel 4 peripheral address register
DMA1_CMAR4 EQU (DMA1_BASE + 0x50) ; DMA channel 4 memory address register
DMA1_CCR5 EQU (DMA1_BASE + 0x58) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR5 EQU (DMA1_BASE + 0x5c) ; DMA channel 5 number of data register
DMA1_CPAR5 EQU (DMA1_BASE + 0x60) ; DMA channel 5 peripheral address register
DMA1_CMAR5 EQU (DMA1_BASE + 0x64) ; DMA channel 5 memory address register
DMA1_CCR6 EQU (DMA1_BASE + 0x6c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR6 EQU (DMA1_BASE + 0x70) ; DMA channel 6 number of data register
DMA1_CPAR6 EQU (DMA1_BASE + 0x74) ; DMA channel 6 peripheral address register
DMA1_CMAR6 EQU (DMA1_BASE + 0x78) ; DMA channel 6 memory address register
DMA1_CCR7 EQU (DMA1_BASE + 0x80) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR7 EQU (DMA1_BASE + 0x84) ; DMA channel 7 number of data register
DMA1_CPAR7 EQU (DMA1_BASE + 0x88) ; DMA channel 7 peripheral address register
DMA1_CMAR7 EQU (DMA1_BASE + 0x8c) ; DMA channel 7 memory address register
; DMA1_ISR fields:
DMA1_ISR_GIF1 EQU 0x00000001 ; Channel 1 Global interrupt flag
DMA1_ISR_GIF1_ofs EQU 0
DMA1_ISR_GIF1_len EQU 1
DMA1_ISR_TCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete flag
DMA1_ISR_TCIF1_ofs EQU 1
DMA1_ISR_TCIF1_len EQU 1
DMA1_ISR_HTIF1 EQU 0x00000004 ; Channel 1 Half Transfer Complete flag
DMA1_ISR_HTIF1_ofs EQU 2
DMA1_ISR_HTIF1_len EQU 1
DMA1_ISR_TEIF1 EQU 0x00000008 ; Channel 1 Transfer Error flag
DMA1_ISR_TEIF1_ofs EQU 3
DMA1_ISR_TEIF1_len EQU 1
DMA1_ISR_GIF2 EQU 0x00000010 ; Channel 2 Global interrupt flag
DMA1_ISR_GIF2_ofs EQU 4
DMA1_ISR_GIF2_len EQU 1
DMA1_ISR_TCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete flag
DMA1_ISR_TCIF2_ofs EQU 5
DMA1_ISR_TCIF2_len EQU 1
DMA1_ISR_HTIF2 EQU 0x00000040 ; Channel 2 Half Transfer Complete flag
DMA1_ISR_HTIF2_ofs EQU 6
DMA1_ISR_HTIF2_len EQU 1
DMA1_ISR_TEIF2 EQU 0x00000080 ; Channel 2 Transfer Error flag
DMA1_ISR_TEIF2_ofs EQU 7
DMA1_ISR_TEIF2_len EQU 1
DMA1_ISR_GIF3 EQU 0x00000100 ; Channel 3 Global interrupt flag
DMA1_ISR_GIF3_ofs EQU 8
DMA1_ISR_GIF3_len EQU 1
DMA1_ISR_TCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete flag
DMA1_ISR_TCIF3_ofs EQU 9
DMA1_ISR_TCIF3_len EQU 1
DMA1_ISR_HTIF3 EQU 0x00000400 ; Channel 3 Half Transfer Complete flag
DMA1_ISR_HTIF3_ofs EQU 10
DMA1_ISR_HTIF3_len EQU 1
DMA1_ISR_TEIF3 EQU 0x00000800 ; Channel 3 Transfer Error flag
DMA1_ISR_TEIF3_ofs EQU 11
DMA1_ISR_TEIF3_len EQU 1
DMA1_ISR_GIF4 EQU 0x00001000 ; Channel 4 Global interrupt flag
DMA1_ISR_GIF4_ofs EQU 12
DMA1_ISR_GIF4_len EQU 1
DMA1_ISR_TCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete flag
DMA1_ISR_TCIF4_ofs EQU 13
DMA1_ISR_TCIF4_len EQU 1
DMA1_ISR_HTIF4 EQU 0x00004000 ; Channel 4 Half Transfer Complete flag
DMA1_ISR_HTIF4_ofs EQU 14
DMA1_ISR_HTIF4_len EQU 1
DMA1_ISR_TEIF4 EQU 0x00008000 ; Channel 4 Transfer Error flag
DMA1_ISR_TEIF4_ofs EQU 15
DMA1_ISR_TEIF4_len EQU 1
DMA1_ISR_GIF5 EQU 0x00010000 ; Channel 5 Global interrupt flag
DMA1_ISR_GIF5_ofs EQU 16
DMA1_ISR_GIF5_len EQU 1
DMA1_ISR_TCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete flag
DMA1_ISR_TCIF5_ofs EQU 17
DMA1_ISR_TCIF5_len EQU 1
DMA1_ISR_HTIF5 EQU 0x00040000 ; Channel 5 Half Transfer Complete flag
DMA1_ISR_HTIF5_ofs EQU 18
DMA1_ISR_HTIF5_len EQU 1
DMA1_ISR_TEIF5 EQU 0x00080000 ; Channel 5 Transfer Error flag
DMA1_ISR_TEIF5_ofs EQU 19
DMA1_ISR_TEIF5_len EQU 1
DMA1_ISR_GIF6 EQU 0x00100000 ; Channel 6 Global interrupt flag
DMA1_ISR_GIF6_ofs EQU 20
DMA1_ISR_GIF6_len EQU 1
DMA1_ISR_TCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete flag
DMA1_ISR_TCIF6_ofs EQU 21
DMA1_ISR_TCIF6_len EQU 1
DMA1_ISR_HTIF6 EQU 0x00400000 ; Channel 6 Half Transfer Complete flag
DMA1_ISR_HTIF6_ofs EQU 22
DMA1_ISR_HTIF6_len EQU 1
DMA1_ISR_TEIF6 EQU 0x00800000 ; Channel 6 Transfer Error flag
DMA1_ISR_TEIF6_ofs EQU 23
DMA1_ISR_TEIF6_len EQU 1
DMA1_ISR_GIF7 EQU 0x01000000 ; Channel 7 Global interrupt flag
DMA1_ISR_GIF7_ofs EQU 24
DMA1_ISR_GIF7_len EQU 1
DMA1_ISR_TCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete flag
DMA1_ISR_TCIF7_ofs EQU 25
DMA1_ISR_TCIF7_len EQU 1
DMA1_ISR_HTIF7 EQU 0x04000000 ; Channel 7 Half Transfer Complete flag
DMA1_ISR_HTIF7_ofs EQU 26
DMA1_ISR_HTIF7_len EQU 1
DMA1_ISR_TEIF7 EQU 0x08000000 ; Channel 7 Transfer Error flag
DMA1_ISR_TEIF7_ofs EQU 27
DMA1_ISR_TEIF7_len EQU 1
; DMA1_IFCR fields:
DMA1_IFCR_CGIF1 EQU 0x00000001 ; Channel 1 Global interrupt clear
DMA1_IFCR_CGIF1_ofs EQU 0
DMA1_IFCR_CGIF1_len EQU 1
DMA1_IFCR_CTCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete clear
DMA1_IFCR_CTCIF1_ofs EQU 1
DMA1_IFCR_CTCIF1_len EQU 1
DMA1_IFCR_CHTIF1 EQU 0x00000004 ; Channel 1 Half Transfer clear
DMA1_IFCR_CHTIF1_ofs EQU 2
DMA1_IFCR_CHTIF1_len EQU 1
DMA1_IFCR_CTEIF1 EQU 0x00000008 ; Channel 1 Transfer Error clear
DMA1_IFCR_CTEIF1_ofs EQU 3
DMA1_IFCR_CTEIF1_len EQU 1
DMA1_IFCR_CGIF2 EQU 0x00000010 ; Channel 2 Global interrupt clear
DMA1_IFCR_CGIF2_ofs EQU 4
DMA1_IFCR_CGIF2_len EQU 1
DMA1_IFCR_CTCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete clear
DMA1_IFCR_CTCIF2_ofs EQU 5
DMA1_IFCR_CTCIF2_len EQU 1
DMA1_IFCR_CHTIF2 EQU 0x00000040 ; Channel 2 Half Transfer clear
DMA1_IFCR_CHTIF2_ofs EQU 6
DMA1_IFCR_CHTIF2_len EQU 1
DMA1_IFCR_CTEIF2 EQU 0x00000080 ; Channel 2 Transfer Error clear
DMA1_IFCR_CTEIF2_ofs EQU 7
DMA1_IFCR_CTEIF2_len EQU 1
DMA1_IFCR_CGIF3 EQU 0x00000100 ; Channel 3 Global interrupt clear
DMA1_IFCR_CGIF3_ofs EQU 8
DMA1_IFCR_CGIF3_len EQU 1
DMA1_IFCR_CTCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete clear
DMA1_IFCR_CTCIF3_ofs EQU 9
DMA1_IFCR_CTCIF3_len EQU 1
DMA1_IFCR_CHTIF3 EQU 0x00000400 ; Channel 3 Half Transfer clear
DMA1_IFCR_CHTIF3_ofs EQU 10
DMA1_IFCR_CHTIF3_len EQU 1
DMA1_IFCR_CTEIF3 EQU 0x00000800 ; Channel 3 Transfer Error clear
DMA1_IFCR_CTEIF3_ofs EQU 11
DMA1_IFCR_CTEIF3_len EQU 1
DMA1_IFCR_CGIF4 EQU 0x00001000 ; Channel 4 Global interrupt clear
DMA1_IFCR_CGIF4_ofs EQU 12
DMA1_IFCR_CGIF4_len EQU 1
DMA1_IFCR_CTCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete clear
DMA1_IFCR_CTCIF4_ofs EQU 13
DMA1_IFCR_CTCIF4_len EQU 1
DMA1_IFCR_CHTIF4 EQU 0x00004000 ; Channel 4 Half Transfer clear
DMA1_IFCR_CHTIF4_ofs EQU 14
DMA1_IFCR_CHTIF4_len EQU 1
DMA1_IFCR_CTEIF4 EQU 0x00008000 ; Channel 4 Transfer Error clear
DMA1_IFCR_CTEIF4_ofs EQU 15
DMA1_IFCR_CTEIF4_len EQU 1
DMA1_IFCR_CGIF5 EQU 0x00010000 ; Channel 5 Global interrupt clear
DMA1_IFCR_CGIF5_ofs EQU 16
DMA1_IFCR_CGIF5_len EQU 1
DMA1_IFCR_CTCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete clear
DMA1_IFCR_CTCIF5_ofs EQU 17
DMA1_IFCR_CTCIF5_len EQU 1
DMA1_IFCR_CHTIF5 EQU 0x00040000 ; Channel 5 Half Transfer clear
DMA1_IFCR_CHTIF5_ofs EQU 18
DMA1_IFCR_CHTIF5_len EQU 1
DMA1_IFCR_CTEIF5 EQU 0x00080000 ; Channel 5 Transfer Error clear
DMA1_IFCR_CTEIF5_ofs EQU 19
DMA1_IFCR_CTEIF5_len EQU 1
DMA1_IFCR_CGIF6 EQU 0x00100000 ; Channel 6 Global interrupt clear
DMA1_IFCR_CGIF6_ofs EQU 20
DMA1_IFCR_CGIF6_len EQU 1
DMA1_IFCR_CTCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete clear
DMA1_IFCR_CTCIF6_ofs EQU 21
DMA1_IFCR_CTCIF6_len EQU 1
DMA1_IFCR_CHTIF6 EQU 0x00400000 ; Channel 6 Half Transfer clear
DMA1_IFCR_CHTIF6_ofs EQU 22
DMA1_IFCR_CHTIF6_len EQU 1
DMA1_IFCR_CTEIF6 EQU 0x00800000 ; Channel 6 Transfer Error clear
DMA1_IFCR_CTEIF6_ofs EQU 23
DMA1_IFCR_CTEIF6_len EQU 1
DMA1_IFCR_CGIF7 EQU 0x01000000 ; Channel 7 Global interrupt clear
DMA1_IFCR_CGIF7_ofs EQU 24
DMA1_IFCR_CGIF7_len EQU 1
DMA1_IFCR_CTCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete clear
DMA1_IFCR_CTCIF7_ofs EQU 25
DMA1_IFCR_CTCIF7_len EQU 1
DMA1_IFCR_CHTIF7 EQU 0x04000000 ; Channel 7 Half Transfer clear
DMA1_IFCR_CHTIF7_ofs EQU 26
DMA1_IFCR_CHTIF7_len EQU 1
DMA1_IFCR_CTEIF7 EQU 0x08000000 ; Channel 7 Transfer Error clear
DMA1_IFCR_CTEIF7_ofs EQU 27
DMA1_IFCR_CTEIF7_len EQU 1
; DMA1_CCR1 fields:
DMA1_CCR1_EN EQU 0x00000001 ; Channel enable
DMA1_CCR1_EN_ofs EQU 0
DMA1_CCR1_EN_len EQU 1
DMA1_CCR1_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR1_TCIE_ofs EQU 1
DMA1_CCR1_TCIE_len EQU 1
DMA1_CCR1_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR1_HTIE_ofs EQU 2
DMA1_CCR1_HTIE_len EQU 1
DMA1_CCR1_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR1_TEIE_ofs EQU 3
DMA1_CCR1_TEIE_len EQU 1
DMA1_CCR1_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR1_DIR_ofs EQU 4
DMA1_CCR1_DIR_len EQU 1
DMA1_CCR1_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR1_CIRC_ofs EQU 5
DMA1_CCR1_CIRC_len EQU 1
DMA1_CCR1_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR1_PINC_ofs EQU 6
DMA1_CCR1_PINC_len EQU 1
DMA1_CCR1_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR1_MINC_ofs EQU 7
DMA1_CCR1_MINC_len EQU 1
DMA1_CCR1_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR1_PSIZE_ofs EQU 8
DMA1_CCR1_PSIZE_len EQU 2
DMA1_CCR1_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR1_MSIZE_ofs EQU 10
DMA1_CCR1_MSIZE_len EQU 2
DMA1_CCR1_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR1_PL_ofs EQU 12
DMA1_CCR1_PL_len EQU 2
DMA1_CCR1_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR1_MEM2MEM_ofs EQU 14
DMA1_CCR1_MEM2MEM_len EQU 1
; DMA1_CNDTR1 fields:
DMA1_CNDTR1_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR1_NDT_ofs EQU 0
DMA1_CNDTR1_NDT_len EQU 16
; DMA1_CPAR1 fields:
DMA1_CPAR1_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR1_PA_ofs EQU 0
DMA1_CPAR1_PA_len EQU 32
; DMA1_CMAR1 fields:
DMA1_CMAR1_MA EQU 0xffffffff ; Memory address
DMA1_CMAR1_MA_ofs EQU 0
DMA1_CMAR1_MA_len EQU 32
; DMA1_CCR2 fields:
DMA1_CCR2_EN EQU 0x00000001 ; Channel enable
DMA1_CCR2_EN_ofs EQU 0
DMA1_CCR2_EN_len EQU 1
DMA1_CCR2_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR2_TCIE_ofs EQU 1
DMA1_CCR2_TCIE_len EQU 1
DMA1_CCR2_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR2_HTIE_ofs EQU 2
DMA1_CCR2_HTIE_len EQU 1
DMA1_CCR2_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR2_TEIE_ofs EQU 3
DMA1_CCR2_TEIE_len EQU 1
DMA1_CCR2_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR2_DIR_ofs EQU 4
DMA1_CCR2_DIR_len EQU 1
DMA1_CCR2_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR2_CIRC_ofs EQU 5
DMA1_CCR2_CIRC_len EQU 1
DMA1_CCR2_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR2_PINC_ofs EQU 6
DMA1_CCR2_PINC_len EQU 1
DMA1_CCR2_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR2_MINC_ofs EQU 7
DMA1_CCR2_MINC_len EQU 1
DMA1_CCR2_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR2_PSIZE_ofs EQU 8
DMA1_CCR2_PSIZE_len EQU 2
DMA1_CCR2_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR2_MSIZE_ofs EQU 10
DMA1_CCR2_MSIZE_len EQU 2
DMA1_CCR2_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR2_PL_ofs EQU 12
DMA1_CCR2_PL_len EQU 2
DMA1_CCR2_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR2_MEM2MEM_ofs EQU 14
DMA1_CCR2_MEM2MEM_len EQU 1
; DMA1_CNDTR2 fields:
DMA1_CNDTR2_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR2_NDT_ofs EQU 0
DMA1_CNDTR2_NDT_len EQU 16
; DMA1_CPAR2 fields:
DMA1_CPAR2_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR2_PA_ofs EQU 0
DMA1_CPAR2_PA_len EQU 32
; DMA1_CMAR2 fields:
DMA1_CMAR2_MA EQU 0xffffffff ; Memory address
DMA1_CMAR2_MA_ofs EQU 0
DMA1_CMAR2_MA_len EQU 32
; DMA1_CCR3 fields:
DMA1_CCR3_EN EQU 0x00000001 ; Channel enable
DMA1_CCR3_EN_ofs EQU 0
DMA1_CCR3_EN_len EQU 1
DMA1_CCR3_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR3_TCIE_ofs EQU 1
DMA1_CCR3_TCIE_len EQU 1
DMA1_CCR3_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR3_HTIE_ofs EQU 2
DMA1_CCR3_HTIE_len EQU 1
DMA1_CCR3_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR3_TEIE_ofs EQU 3
DMA1_CCR3_TEIE_len EQU 1
DMA1_CCR3_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR3_DIR_ofs EQU 4
DMA1_CCR3_DIR_len EQU 1
DMA1_CCR3_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR3_CIRC_ofs EQU 5
DMA1_CCR3_CIRC_len EQU 1
DMA1_CCR3_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR3_PINC_ofs EQU 6
DMA1_CCR3_PINC_len EQU 1
DMA1_CCR3_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR3_MINC_ofs EQU 7
DMA1_CCR3_MINC_len EQU 1
DMA1_CCR3_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR3_PSIZE_ofs EQU 8
DMA1_CCR3_PSIZE_len EQU 2
DMA1_CCR3_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR3_MSIZE_ofs EQU 10
DMA1_CCR3_MSIZE_len EQU 2
DMA1_CCR3_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR3_PL_ofs EQU 12
DMA1_CCR3_PL_len EQU 2
DMA1_CCR3_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR3_MEM2MEM_ofs EQU 14
DMA1_CCR3_MEM2MEM_len EQU 1
; DMA1_CNDTR3 fields:
DMA1_CNDTR3_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR3_NDT_ofs EQU 0
DMA1_CNDTR3_NDT_len EQU 16
; DMA1_CPAR3 fields:
DMA1_CPAR3_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR3_PA_ofs EQU 0
DMA1_CPAR3_PA_len EQU 32
; DMA1_CMAR3 fields:
DMA1_CMAR3_MA EQU 0xffffffff ; Memory address
DMA1_CMAR3_MA_ofs EQU 0
DMA1_CMAR3_MA_len EQU 32
; DMA1_CCR4 fields:
DMA1_CCR4_EN EQU 0x00000001 ; Channel enable
DMA1_CCR4_EN_ofs EQU 0
DMA1_CCR4_EN_len EQU 1
DMA1_CCR4_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR4_TCIE_ofs EQU 1
DMA1_CCR4_TCIE_len EQU 1
DMA1_CCR4_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR4_HTIE_ofs EQU 2
DMA1_CCR4_HTIE_len EQU 1
DMA1_CCR4_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR4_TEIE_ofs EQU 3
DMA1_CCR4_TEIE_len EQU 1
DMA1_CCR4_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR4_DIR_ofs EQU 4
DMA1_CCR4_DIR_len EQU 1
DMA1_CCR4_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR4_CIRC_ofs EQU 5
DMA1_CCR4_CIRC_len EQU 1
DMA1_CCR4_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR4_PINC_ofs EQU 6
DMA1_CCR4_PINC_len EQU 1
DMA1_CCR4_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR4_MINC_ofs EQU 7
DMA1_CCR4_MINC_len EQU 1
DMA1_CCR4_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR4_PSIZE_ofs EQU 8
DMA1_CCR4_PSIZE_len EQU 2
DMA1_CCR4_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR4_MSIZE_ofs EQU 10
DMA1_CCR4_MSIZE_len EQU 2
DMA1_CCR4_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR4_PL_ofs EQU 12
DMA1_CCR4_PL_len EQU 2
DMA1_CCR4_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR4_MEM2MEM_ofs EQU 14
DMA1_CCR4_MEM2MEM_len EQU 1
; DMA1_CNDTR4 fields:
DMA1_CNDTR4_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR4_NDT_ofs EQU 0
DMA1_CNDTR4_NDT_len EQU 16
; DMA1_CPAR4 fields:
DMA1_CPAR4_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR4_PA_ofs EQU 0
DMA1_CPAR4_PA_len EQU 32
; DMA1_CMAR4 fields:
DMA1_CMAR4_MA EQU 0xffffffff ; Memory address
DMA1_CMAR4_MA_ofs EQU 0
DMA1_CMAR4_MA_len EQU 32
; DMA1_CCR5 fields:
DMA1_CCR5_EN EQU 0x00000001 ; Channel enable
DMA1_CCR5_EN_ofs EQU 0
DMA1_CCR5_EN_len EQU 1
DMA1_CCR5_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR5_TCIE_ofs EQU 1
DMA1_CCR5_TCIE_len EQU 1
DMA1_CCR5_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR5_HTIE_ofs EQU 2
DMA1_CCR5_HTIE_len EQU 1
DMA1_CCR5_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR5_TEIE_ofs EQU 3
DMA1_CCR5_TEIE_len EQU 1
DMA1_CCR5_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR5_DIR_ofs EQU 4
DMA1_CCR5_DIR_len EQU 1
DMA1_CCR5_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR5_CIRC_ofs EQU 5
DMA1_CCR5_CIRC_len EQU 1
DMA1_CCR5_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR5_PINC_ofs EQU 6
DMA1_CCR5_PINC_len EQU 1
DMA1_CCR5_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR5_MINC_ofs EQU 7
DMA1_CCR5_MINC_len EQU 1
DMA1_CCR5_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR5_PSIZE_ofs EQU 8
DMA1_CCR5_PSIZE_len EQU 2
DMA1_CCR5_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR5_MSIZE_ofs EQU 10
DMA1_CCR5_MSIZE_len EQU 2
DMA1_CCR5_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR5_PL_ofs EQU 12
DMA1_CCR5_PL_len EQU 2
DMA1_CCR5_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR5_MEM2MEM_ofs EQU 14
DMA1_CCR5_MEM2MEM_len EQU 1
; DMA1_CNDTR5 fields:
DMA1_CNDTR5_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR5_NDT_ofs EQU 0
DMA1_CNDTR5_NDT_len EQU 16
; DMA1_CPAR5 fields:
DMA1_CPAR5_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR5_PA_ofs EQU 0
DMA1_CPAR5_PA_len EQU 32
; DMA1_CMAR5 fields:
DMA1_CMAR5_MA EQU 0xffffffff ; Memory address
DMA1_CMAR5_MA_ofs EQU 0
DMA1_CMAR5_MA_len EQU 32
; DMA1_CCR6 fields:
DMA1_CCR6_EN EQU 0x00000001 ; Channel enable
DMA1_CCR6_EN_ofs EQU 0
DMA1_CCR6_EN_len EQU 1
DMA1_CCR6_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR6_TCIE_ofs EQU 1
DMA1_CCR6_TCIE_len EQU 1
DMA1_CCR6_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR6_HTIE_ofs EQU 2
DMA1_CCR6_HTIE_len EQU 1
DMA1_CCR6_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR6_TEIE_ofs EQU 3
DMA1_CCR6_TEIE_len EQU 1
DMA1_CCR6_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR6_DIR_ofs EQU 4
DMA1_CCR6_DIR_len EQU 1
DMA1_CCR6_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR6_CIRC_ofs EQU 5
DMA1_CCR6_CIRC_len EQU 1
DMA1_CCR6_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR6_PINC_ofs EQU 6
DMA1_CCR6_PINC_len EQU 1
DMA1_CCR6_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR6_MINC_ofs EQU 7
DMA1_CCR6_MINC_len EQU 1
DMA1_CCR6_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR6_PSIZE_ofs EQU 8
DMA1_CCR6_PSIZE_len EQU 2
DMA1_CCR6_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR6_MSIZE_ofs EQU 10
DMA1_CCR6_MSIZE_len EQU 2
DMA1_CCR6_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR6_PL_ofs EQU 12
DMA1_CCR6_PL_len EQU 2
DMA1_CCR6_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR6_MEM2MEM_ofs EQU 14
DMA1_CCR6_MEM2MEM_len EQU 1
; DMA1_CNDTR6 fields:
DMA1_CNDTR6_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR6_NDT_ofs EQU 0
DMA1_CNDTR6_NDT_len EQU 16
; DMA1_CPAR6 fields:
DMA1_CPAR6_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR6_PA_ofs EQU 0
DMA1_CPAR6_PA_len EQU 32
; DMA1_CMAR6 fields:
DMA1_CMAR6_MA EQU 0xffffffff ; Memory address
DMA1_CMAR6_MA_ofs EQU 0
DMA1_CMAR6_MA_len EQU 32
; DMA1_CCR7 fields:
DMA1_CCR7_EN EQU 0x00000001 ; Channel enable
DMA1_CCR7_EN_ofs EQU 0
DMA1_CCR7_EN_len EQU 1
DMA1_CCR7_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR7_TCIE_ofs EQU 1
DMA1_CCR7_TCIE_len EQU 1
DMA1_CCR7_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR7_HTIE_ofs EQU 2
DMA1_CCR7_HTIE_len EQU 1
DMA1_CCR7_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR7_TEIE_ofs EQU 3
DMA1_CCR7_TEIE_len EQU 1
DMA1_CCR7_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR7_DIR_ofs EQU 4
DMA1_CCR7_DIR_len EQU 1
DMA1_CCR7_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR7_CIRC_ofs EQU 5
DMA1_CCR7_CIRC_len EQU 1
DMA1_CCR7_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR7_PINC_ofs EQU 6
DMA1_CCR7_PINC_len EQU 1
DMA1_CCR7_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR7_MINC_ofs EQU 7
DMA1_CCR7_MINC_len EQU 1
DMA1_CCR7_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR7_PSIZE_ofs EQU 8
DMA1_CCR7_PSIZE_len EQU 2
DMA1_CCR7_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR7_MSIZE_ofs EQU 10
DMA1_CCR7_MSIZE_len EQU 2
DMA1_CCR7_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR7_PL_ofs EQU 12
DMA1_CCR7_PL_len EQU 2
DMA1_CCR7_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR7_MEM2MEM_ofs EQU 14
DMA1_CCR7_MEM2MEM_len EQU 1
; DMA1_CNDTR7 fields:
DMA1_CNDTR7_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR7_NDT_ofs EQU 0
DMA1_CNDTR7_NDT_len EQU 16
; DMA1_CPAR7 fields:
DMA1_CPAR7_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR7_PA_ofs EQU 0
DMA1_CPAR7_PA_len EQU 32
; DMA1_CMAR7 fields:
DMA1_CMAR7_MA EQU 0xffffffff ; Memory address
DMA1_CMAR7_MA_ofs EQU 0
DMA1_CMAR7_MA_len EQU 32
; ---- DMA2 --------------------------------------------------
; Desc: None
; DMA2 base address:
DMA2_BASE EQU 0x40020400
; DMA2 registers:
; ---- TIM2 --------------------------------------------------
; Desc: General purpose timer
; TIM2 base address:
TIM2_BASE EQU 0x40000000
; TIM2 registers:
TIM2_CR1 EQU (TIM2_BASE + 0x0) ; control register 1
TIM2_CR2 EQU (TIM2_BASE + 0x4) ; control register 2
TIM2_SMCR EQU (TIM2_BASE + 0x8) ; slave mode control register
TIM2_DIER EQU (TIM2_BASE + 0xc) ; DMA/Interrupt enable register
TIM2_SR EQU (TIM2_BASE + 0x10) ; status register
TIM2_EGR EQU (TIM2_BASE + 0x14) ; event generation register
TIM2_CCMR1_Output EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (output mode)
TIM2_CCMR1_Input EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM2_CCMR2_Output EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (output mode)
TIM2_CCMR2_Input EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM2_CCER EQU (TIM2_BASE + 0x20) ; capture/compare enable register
TIM2_CNT EQU (TIM2_BASE + 0x24) ; counter
TIM2_PSC EQU (TIM2_BASE + 0x28) ; prescaler
TIM2_ARR EQU (TIM2_BASE + 0x2c) ; auto-reload register
TIM2_CCR1 EQU (TIM2_BASE + 0x34) ; capture/compare register 1
TIM2_CCR2 EQU (TIM2_BASE + 0x38) ; capture/compare register 2
TIM2_CCR3 EQU (TIM2_BASE + 0x3c) ; capture/compare register 3
TIM2_CCR4 EQU (TIM2_BASE + 0x40) ; capture/compare register 4
TIM2_DCR EQU (TIM2_BASE + 0x48) ; DMA control register
TIM2_DMAR EQU (TIM2_BASE + 0x4c) ; DMA address for full transfer
; TIM2_CR1 fields:
TIM2_CR1_CEN EQU 0x00000001 ; Counter enable
TIM2_CR1_CEN_ofs EQU 0
TIM2_CR1_CEN_len EQU 1
TIM2_CR1_UDIS EQU 0x00000002 ; Update disable
TIM2_CR1_UDIS_ofs EQU 1
TIM2_CR1_UDIS_len EQU 1
TIM2_CR1_URS EQU 0x00000004 ; Update request source
TIM2_CR1_URS_ofs EQU 2
TIM2_CR1_URS_len EQU 1
TIM2_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM2_CR1_OPM_ofs EQU 3
TIM2_CR1_OPM_len EQU 1
TIM2_CR1_DIR EQU 0x00000010 ; Direction
TIM2_CR1_DIR_ofs EQU 4
TIM2_CR1_DIR_len EQU 1
TIM2_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM2_CR1_CMS_ofs EQU 5
TIM2_CR1_CMS_len EQU 2
TIM2_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM2_CR1_ARPE_ofs EQU 7
TIM2_CR1_ARPE_len EQU 1
TIM2_CR1_CKD EQU 0x00000300 ; Clock division
TIM2_CR1_CKD_ofs EQU 8
TIM2_CR1_CKD_len EQU 2
TIM2_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM2_CR1_UIFREMAP_ofs EQU 11
TIM2_CR1_UIFREMAP_len EQU 1
; TIM2_CR2 fields:
TIM2_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM2_CR2_TI1S_ofs EQU 7
TIM2_CR2_TI1S_len EQU 1
TIM2_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM2_CR2_MMS_ofs EQU 4
TIM2_CR2_MMS_len EQU 3
TIM2_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM2_CR2_CCDS_ofs EQU 3
TIM2_CR2_CCDS_len EQU 1
; TIM2_SMCR fields:
TIM2_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM2_SMCR_SMS_ofs EQU 0
TIM2_SMCR_SMS_len EQU 3
TIM2_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM2_SMCR_OCCS_ofs EQU 3
TIM2_SMCR_OCCS_len EQU 1
TIM2_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM2_SMCR_TS_ofs EQU 4
TIM2_SMCR_TS_len EQU 3
TIM2_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM2_SMCR_MSM_ofs EQU 7
TIM2_SMCR_MSM_len EQU 1
TIM2_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM2_SMCR_ETF_ofs EQU 8
TIM2_SMCR_ETF_len EQU 4
TIM2_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM2_SMCR_ETPS_ofs EQU 12
TIM2_SMCR_ETPS_len EQU 2
TIM2_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM2_SMCR_ECE_ofs EQU 14
TIM2_SMCR_ECE_len EQU 1
TIM2_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM2_SMCR_ETP_ofs EQU 15
TIM2_SMCR_ETP_len EQU 1
TIM2_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit3
TIM2_SMCR_SMS_3_ofs EQU 16
TIM2_SMCR_SMS_3_len EQU 1
; TIM2_DIER fields:
TIM2_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM2_DIER_TDE_ofs EQU 14
TIM2_DIER_TDE_len EQU 1
TIM2_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM2_DIER_CC4DE_ofs EQU 12
TIM2_DIER_CC4DE_len EQU 1
TIM2_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM2_DIER_CC3DE_ofs EQU 11
TIM2_DIER_CC3DE_len EQU 1
TIM2_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM2_DIER_CC2DE_ofs EQU 10
TIM2_DIER_CC2DE_len EQU 1
TIM2_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM2_DIER_CC1DE_ofs EQU 9
TIM2_DIER_CC1DE_len EQU 1
TIM2_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM2_DIER_UDE_ofs EQU 8
TIM2_DIER_UDE_len EQU 1
TIM2_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM2_DIER_TIE_ofs EQU 6
TIM2_DIER_TIE_len EQU 1
TIM2_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM2_DIER_CC4IE_ofs EQU 4
TIM2_DIER_CC4IE_len EQU 1
TIM2_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM2_DIER_CC3IE_ofs EQU 3
TIM2_DIER_CC3IE_len EQU 1
TIM2_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM2_DIER_CC2IE_ofs EQU 2
TIM2_DIER_CC2IE_len EQU 1
TIM2_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM2_DIER_CC1IE_ofs EQU 1
TIM2_DIER_CC1IE_len EQU 1
TIM2_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM2_DIER_UIE_ofs EQU 0
TIM2_DIER_UIE_len EQU 1
; TIM2_SR fields:
TIM2_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM2_SR_CC4OF_ofs EQU 12
TIM2_SR_CC4OF_len EQU 1
TIM2_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM2_SR_CC3OF_ofs EQU 11
TIM2_SR_CC3OF_len EQU 1
TIM2_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM2_SR_CC2OF_ofs EQU 10
TIM2_SR_CC2OF_len EQU 1
TIM2_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM2_SR_CC1OF_ofs EQU 9
TIM2_SR_CC1OF_len EQU 1
TIM2_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM2_SR_TIF_ofs EQU 6
TIM2_SR_TIF_len EQU 1
TIM2_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM2_SR_CC4IF_ofs EQU 4
TIM2_SR_CC4IF_len EQU 1
TIM2_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM2_SR_CC3IF_ofs EQU 3
TIM2_SR_CC3IF_len EQU 1
TIM2_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM2_SR_CC2IF_ofs EQU 2
TIM2_SR_CC2IF_len EQU 1
TIM2_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM2_SR_CC1IF_ofs EQU 1
TIM2_SR_CC1IF_len EQU 1
TIM2_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM2_SR_UIF_ofs EQU 0
TIM2_SR_UIF_len EQU 1
; TIM2_EGR fields:
TIM2_EGR_TG EQU 0x00000040 ; Trigger generation
TIM2_EGR_TG_ofs EQU 6
TIM2_EGR_TG_len EQU 1
TIM2_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM2_EGR_CC4G_ofs EQU 4
TIM2_EGR_CC4G_len EQU 1
TIM2_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM2_EGR_CC3G_ofs EQU 3
TIM2_EGR_CC3G_len EQU 1
TIM2_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM2_EGR_CC2G_ofs EQU 2
TIM2_EGR_CC2G_len EQU 1
TIM2_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM2_EGR_CC1G_ofs EQU 1
TIM2_EGR_CC1G_len EQU 1
TIM2_EGR_UG EQU 0x00000001 ; Update generation
TIM2_EGR_UG_ofs EQU 0
TIM2_EGR_UG_len EQU 1
; TIM2_CCMR1_Output fields:
TIM2_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Output_CC1S_ofs EQU 0
TIM2_CCMR1_Output_CC1S_len EQU 2
TIM2_CCMR1_Output_OC1FE EQU 0x00000004 ; Output compare 1 fast enable
TIM2_CCMR1_Output_OC1FE_ofs EQU 2
TIM2_CCMR1_Output_OC1FE_len EQU 1
TIM2_CCMR1_Output_OC1PE EQU 0x00000008 ; Output compare 1 preload enable
TIM2_CCMR1_Output_OC1PE_ofs EQU 3
TIM2_CCMR1_Output_OC1PE_len EQU 1
TIM2_CCMR1_Output_OC1M EQU 0x00000070 ; Output compare 1 mode
TIM2_CCMR1_Output_OC1M_ofs EQU 4
TIM2_CCMR1_Output_OC1M_len EQU 3
TIM2_CCMR1_Output_OC1CE EQU 0x00000080 ; Output compare 1 clear enable
TIM2_CCMR1_Output_OC1CE_ofs EQU 7
TIM2_CCMR1_Output_OC1CE_len EQU 1
TIM2_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM2_CCMR1_Output_CC2S_ofs EQU 8
TIM2_CCMR1_Output_CC2S_len EQU 2
TIM2_CCMR1_Output_OC2FE EQU 0x00000400 ; Output compare 2 fast enable
TIM2_CCMR1_Output_OC2FE_ofs EQU 10
TIM2_CCMR1_Output_OC2FE_len EQU 1
TIM2_CCMR1_Output_OC2PE EQU 0x00000800 ; Output compare 2 preload enable
TIM2_CCMR1_Output_OC2PE_ofs EQU 11
TIM2_CCMR1_Output_OC2PE_len EQU 1
TIM2_CCMR1_Output_OC2M EQU 0x00007000 ; Output compare 2 mode
TIM2_CCMR1_Output_OC2M_ofs EQU 12
TIM2_CCMR1_Output_OC2M_len EQU 3
TIM2_CCMR1_Output_OC2CE EQU 0x00008000 ; Output compare 2 clear enable
TIM2_CCMR1_Output_OC2CE_ofs EQU 15
TIM2_CCMR1_Output_OC2CE_len EQU 1
TIM2_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output compare 1 mode bit 3
TIM2_CCMR1_Output_OC1M_3_ofs EQU 16
TIM2_CCMR1_Output_OC1M_3_len EQU 1
TIM2_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output compare 2 mode bit 3
TIM2_CCMR1_Output_OC2M_3_ofs EQU 24
TIM2_CCMR1_Output_OC2M_3_len EQU 1
; TIM2_CCMR1_Input fields:
TIM2_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM2_CCMR1_Input_IC2F_ofs EQU 12
TIM2_CCMR1_Input_IC2F_len EQU 4
TIM2_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM2_CCMR1_Input_IC2PSC_ofs EQU 10
TIM2_CCMR1_Input_IC2PSC_len EQU 2
TIM2_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/compare 2 selection
TIM2_CCMR1_Input_CC2S_ofs EQU 8
TIM2_CCMR1_Input_CC2S_len EQU 2
TIM2_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM2_CCMR1_Input_IC1F_ofs EQU 4
TIM2_CCMR1_Input_IC1F_len EQU 4
TIM2_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM2_CCMR1_Input_IC1PSC_ofs EQU 2
TIM2_CCMR1_Input_IC1PSC_len EQU 2
TIM2_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Input_CC1S_ofs EQU 0
TIM2_CCMR1_Input_CC1S_len EQU 2
; TIM2_CCMR2_Output fields:
TIM2_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Output_CC3S_ofs EQU 0
TIM2_CCMR2_Output_CC3S_len EQU 2
TIM2_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM2_CCMR2_Output_OC3FE_ofs EQU 2
TIM2_CCMR2_Output_OC3FE_len EQU 1
TIM2_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM2_CCMR2_Output_OC3PE_ofs EQU 3
TIM2_CCMR2_Output_OC3PE_len EQU 1
TIM2_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM2_CCMR2_Output_OC3M_ofs EQU 4
TIM2_CCMR2_Output_OC3M_len EQU 3
TIM2_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM2_CCMR2_Output_OC3CE_ofs EQU 7
TIM2_CCMR2_Output_OC3CE_len EQU 1
TIM2_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Output_CC4S_ofs EQU 8
TIM2_CCMR2_Output_CC4S_len EQU 2
TIM2_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM2_CCMR2_Output_OC4FE_ofs EQU 10
TIM2_CCMR2_Output_OC4FE_len EQU 1
TIM2_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM2_CCMR2_Output_OC4PE_ofs EQU 11
TIM2_CCMR2_Output_OC4PE_len EQU 1
TIM2_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM2_CCMR2_Output_OC4M_ofs EQU 12
TIM2_CCMR2_Output_OC4M_len EQU 3
TIM2_CCMR2_Output_O24CE EQU 0x00008000 ; Output compare 4 clear enable
TIM2_CCMR2_Output_O24CE_ofs EQU 15
TIM2_CCMR2_Output_O24CE_len EQU 1
TIM2_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output compare 3 mode bit3
TIM2_CCMR2_Output_OC3M_3_ofs EQU 16
TIM2_CCMR2_Output_OC3M_3_len EQU 1
TIM2_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output compare 4 mode bit3
TIM2_CCMR2_Output_OC4M_3_ofs EQU 24
TIM2_CCMR2_Output_OC4M_3_len EQU 1
; TIM2_CCMR2_Input fields:
TIM2_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM2_CCMR2_Input_IC4F_ofs EQU 12
TIM2_CCMR2_Input_IC4F_len EQU 4
TIM2_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM2_CCMR2_Input_IC4PSC_ofs EQU 10
TIM2_CCMR2_Input_IC4PSC_len EQU 2
TIM2_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Input_CC4S_ofs EQU 8
TIM2_CCMR2_Input_CC4S_len EQU 2
TIM2_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM2_CCMR2_Input_IC3F_ofs EQU 4
TIM2_CCMR2_Input_IC3F_len EQU 4
TIM2_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM2_CCMR2_Input_IC3PSC_ofs EQU 2
TIM2_CCMR2_Input_IC3PSC_len EQU 2
TIM2_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Input_CC3S_ofs EQU 0
TIM2_CCMR2_Input_CC3S_len EQU 2
; TIM2_CCER fields:
TIM2_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM2_CCER_CC1E_ofs EQU 0
TIM2_CCER_CC1E_len EQU 1
TIM2_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1P_ofs EQU 1
TIM2_CCER_CC1P_len EQU 1
TIM2_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1NP_ofs EQU 3
TIM2_CCER_CC1NP_len EQU 1
TIM2_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM2_CCER_CC2E_ofs EQU 4
TIM2_CCER_CC2E_len EQU 1
TIM2_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2P_ofs EQU 5
TIM2_CCER_CC2P_len EQU 1
TIM2_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2NP_ofs EQU 7
TIM2_CCER_CC2NP_len EQU 1
TIM2_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM2_CCER_CC3E_ofs EQU 8
TIM2_CCER_CC3E_len EQU 1
TIM2_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3P_ofs EQU 9
TIM2_CCER_CC3P_len EQU 1
TIM2_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3NP_ofs EQU 11
TIM2_CCER_CC3NP_len EQU 1
TIM2_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM2_CCER_CC4E_ofs EQU 12
TIM2_CCER_CC4E_len EQU 1
TIM2_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4P_ofs EQU 13
TIM2_CCER_CC4P_len EQU 1
TIM2_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4NP_ofs EQU 15
TIM2_CCER_CC4NP_len EQU 1
; TIM2_CNT fields:
TIM2_CNT_CNTL EQU 0x0000ffff ; Low counter value
TIM2_CNT_CNTL_ofs EQU 0
TIM2_CNT_CNTL_len EQU 16
TIM2_CNT_CNTH EQU 0x7fff0000 ; High counter value
TIM2_CNT_CNTH_ofs EQU 16
TIM2_CNT_CNTH_len EQU 15
TIM2_CNT_CNT_or_UIFCPY EQU 0x80000000 ; if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
TIM2_CNT_CNT_or_UIFCPY_ofs EQU 31
TIM2_CNT_CNT_or_UIFCPY_len EQU 1
; TIM2_PSC fields:
TIM2_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM2_PSC_PSC_ofs EQU 0
TIM2_PSC_PSC_len EQU 16
; TIM2_ARR fields:
TIM2_ARR_ARRL EQU 0x0000ffff ; Low Auto-reload value
TIM2_ARR_ARRL_ofs EQU 0
TIM2_ARR_ARRL_len EQU 16
TIM2_ARR_ARRH EQU 0xffff0000 ; High Auto-reload value
TIM2_ARR_ARRH_ofs EQU 16
TIM2_ARR_ARRH_len EQU 16
; TIM2_CCR1 fields:
TIM2_CCR1_CCR1L EQU 0x0000ffff ; Low Capture/Compare 1 value
TIM2_CCR1_CCR1L_ofs EQU 0
TIM2_CCR1_CCR1L_len EQU 16
TIM2_CCR1_CCR1H EQU 0xffff0000 ; High Capture/Compare 1 value (on TIM2)
TIM2_CCR1_CCR1H_ofs EQU 16
TIM2_CCR1_CCR1H_len EQU 16
; TIM2_CCR2 fields:
TIM2_CCR2_CCR2L EQU 0x0000ffff ; Low Capture/Compare 2 value
TIM2_CCR2_CCR2L_ofs EQU 0
TIM2_CCR2_CCR2L_len EQU 16
TIM2_CCR2_CCR2H EQU 0xffff0000 ; High Capture/Compare 2 value (on TIM2)
TIM2_CCR2_CCR2H_ofs EQU 16
TIM2_CCR2_CCR2H_len EQU 16
; TIM2_CCR3 fields:
TIM2_CCR3_CCR3L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR3_CCR3L_ofs EQU 0
TIM2_CCR3_CCR3L_len EQU 16
TIM2_CCR3_CCR3H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR3_CCR3H_ofs EQU 16
TIM2_CCR3_CCR3H_len EQU 16
; TIM2_CCR4 fields:
TIM2_CCR4_CCR4L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR4_CCR4L_ofs EQU 0
TIM2_CCR4_CCR4L_len EQU 16
TIM2_CCR4_CCR4H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR4_CCR4H_ofs EQU 16
TIM2_CCR4_CCR4H_len EQU 16
; TIM2_DCR fields:
TIM2_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM2_DCR_DBL_ofs EQU 8
TIM2_DCR_DBL_len EQU 5
TIM2_DCR_DBA EQU 0x0000001f ; DMA base address
TIM2_DCR_DBA_ofs EQU 0
TIM2_DCR_DBA_len EQU 5
; TIM2_DMAR fields:
TIM2_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM2_DMAR_DMAB_ofs EQU 0
TIM2_DMAR_DMAB_len EQU 16
; ---- TIM3 --------------------------------------------------
; Desc: None
; TIM3 base address:
TIM3_BASE EQU 0x40000400
; TIM3 registers:
; ---- TIM4 --------------------------------------------------
; Desc: None
; TIM4 base address:
TIM4_BASE EQU 0x40000800
; TIM4 registers:
; ---- TIM15 -------------------------------------------------
; Desc: General purpose timers
; TIM15 base address:
TIM15_BASE EQU 0x40014000
; TIM15 registers:
TIM15_CR1 EQU (TIM15_BASE + 0x0) ; control register 1
TIM15_CR2 EQU (TIM15_BASE + 0x4) ; control register 2
TIM15_SMCR EQU (TIM15_BASE + 0x8) ; slave mode control register
TIM15_DIER EQU (TIM15_BASE + 0xc) ; DMA/Interrupt enable register
TIM15_SR EQU (TIM15_BASE + 0x10) ; status register
TIM15_EGR EQU (TIM15_BASE + 0x14) ; event generation register
TIM15_CCMR1_Output EQU (TIM15_BASE + 0x18) ; capture/compare mode register (output mode)
TIM15_CCMR1_Input EQU (TIM15_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM15_CCER EQU (TIM15_BASE + 0x20) ; capture/compare enable register
TIM15_CNT EQU (TIM15_BASE + 0x24) ; counter
TIM15_PSC EQU (TIM15_BASE + 0x28) ; prescaler
TIM15_ARR EQU (TIM15_BASE + 0x2c) ; auto-reload register
TIM15_RCR EQU (TIM15_BASE + 0x30) ; repetition counter register
TIM15_CCR1 EQU (TIM15_BASE + 0x34) ; capture/compare register 1
TIM15_CCR2 EQU (TIM15_BASE + 0x38) ; capture/compare register 2
TIM15_BDTR EQU (TIM15_BASE + 0x44) ; break and dead-time register
TIM15_DCR EQU (TIM15_BASE + 0x48) ; DMA control register
TIM15_DMAR EQU (TIM15_BASE + 0x4c) ; DMA address for full transfer
; TIM15_CR1 fields:
TIM15_CR1_CEN EQU 0x00000001 ; Counter enable
TIM15_CR1_CEN_ofs EQU 0
TIM15_CR1_CEN_len EQU 1
TIM15_CR1_UDIS EQU 0x00000002 ; Update disable
TIM15_CR1_UDIS_ofs EQU 1
TIM15_CR1_UDIS_len EQU 1
TIM15_CR1_URS EQU 0x00000004 ; Update request source
TIM15_CR1_URS_ofs EQU 2
TIM15_CR1_URS_len EQU 1
TIM15_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM15_CR1_OPM_ofs EQU 3
TIM15_CR1_OPM_len EQU 1
TIM15_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM15_CR1_ARPE_ofs EQU 7
TIM15_CR1_ARPE_len EQU 1
TIM15_CR1_CKD EQU 0x00000300 ; Clock division
TIM15_CR1_CKD_ofs EQU 8
TIM15_CR1_CKD_len EQU 2
TIM15_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM15_CR1_UIFREMAP_ofs EQU 11
TIM15_CR1_UIFREMAP_len EQU 1
; TIM15_CR2 fields:
TIM15_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM15_CR2_CCPC_ofs EQU 0
TIM15_CR2_CCPC_len EQU 1
TIM15_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM15_CR2_CCUS_ofs EQU 2
TIM15_CR2_CCUS_len EQU 1
TIM15_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM15_CR2_CCDS_ofs EQU 3
TIM15_CR2_CCDS_len EQU 1
TIM15_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM15_CR2_MMS_ofs EQU 4
TIM15_CR2_MMS_len EQU 3
TIM15_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM15_CR2_TI1S_ofs EQU 7
TIM15_CR2_TI1S_len EQU 1
TIM15_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM15_CR2_OIS1_ofs EQU 8
TIM15_CR2_OIS1_len EQU 1
TIM15_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM15_CR2_OIS1N_ofs EQU 9
TIM15_CR2_OIS1N_len EQU 1
TIM15_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM15_CR2_OIS2_ofs EQU 10
TIM15_CR2_OIS2_len EQU 1
; TIM15_SMCR fields:
TIM15_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM15_SMCR_SMS_ofs EQU 0
TIM15_SMCR_SMS_len EQU 3
TIM15_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM15_SMCR_TS_ofs EQU 4
TIM15_SMCR_TS_len EQU 3
TIM15_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM15_SMCR_MSM_ofs EQU 7
TIM15_SMCR_MSM_len EQU 1
TIM15_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit 3
TIM15_SMCR_SMS_3_ofs EQU 16
TIM15_SMCR_SMS_3_len EQU 1
; TIM15_DIER fields:
TIM15_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM15_DIER_UIE_ofs EQU 0
TIM15_DIER_UIE_len EQU 1
TIM15_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM15_DIER_CC1IE_ofs EQU 1
TIM15_DIER_CC1IE_len EQU 1
TIM15_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM15_DIER_CC2IE_ofs EQU 2
TIM15_DIER_CC2IE_len EQU 1
TIM15_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM15_DIER_COMIE_ofs EQU 5
TIM15_DIER_COMIE_len EQU 1
TIM15_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM15_DIER_TIE_ofs EQU 6
TIM15_DIER_TIE_len EQU 1
TIM15_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM15_DIER_BIE_ofs EQU 7
TIM15_DIER_BIE_len EQU 1
TIM15_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM15_DIER_UDE_ofs EQU 8
TIM15_DIER_UDE_len EQU 1
TIM15_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM15_DIER_CC1DE_ofs EQU 9
TIM15_DIER_CC1DE_len EQU 1
TIM15_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM15_DIER_CC2DE_ofs EQU 10
TIM15_DIER_CC2DE_len EQU 1
TIM15_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM15_DIER_COMDE_ofs EQU 13
TIM15_DIER_COMDE_len EQU 1
TIM15_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM15_DIER_TDE_ofs EQU 14
TIM15_DIER_TDE_len EQU 1
; TIM15_SR fields:
TIM15_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM15_SR_CC2OF_ofs EQU 10
TIM15_SR_CC2OF_len EQU 1
TIM15_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM15_SR_CC1OF_ofs EQU 9
TIM15_SR_CC1OF_len EQU 1
TIM15_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM15_SR_BIF_ofs EQU 7
TIM15_SR_BIF_len EQU 1
TIM15_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM15_SR_TIF_ofs EQU 6
TIM15_SR_TIF_len EQU 1
TIM15_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM15_SR_COMIF_ofs EQU 5
TIM15_SR_COMIF_len EQU 1
TIM15_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM15_SR_CC2IF_ofs EQU 2
TIM15_SR_CC2IF_len EQU 1
TIM15_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM15_SR_CC1IF_ofs EQU 1
TIM15_SR_CC1IF_len EQU 1
TIM15_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM15_SR_UIF_ofs EQU 0
TIM15_SR_UIF_len EQU 1
; TIM15_EGR fields:
TIM15_EGR_BG EQU 0x00000080 ; Break generation
TIM15_EGR_BG_ofs EQU 7
TIM15_EGR_BG_len EQU 1
TIM15_EGR_TG EQU 0x00000040 ; Trigger generation
TIM15_EGR_TG_ofs EQU 6
TIM15_EGR_TG_len EQU 1
TIM15_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM15_EGR_COMG_ofs EQU 5
TIM15_EGR_COMG_len EQU 1
TIM15_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM15_EGR_CC2G_ofs EQU 2
TIM15_EGR_CC2G_len EQU 1
TIM15_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM15_EGR_CC1G_ofs EQU 1
TIM15_EGR_CC1G_len EQU 1
TIM15_EGR_UG EQU 0x00000001 ; Update generation
TIM15_EGR_UG_ofs EQU 0
TIM15_EGR_UG_len EQU 1
; TIM15_CCMR1_Output fields:
TIM15_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Output_CC1S_ofs EQU 0
TIM15_CCMR1_Output_CC1S_len EQU 2
TIM15_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM15_CCMR1_Output_OC1FE_ofs EQU 2
TIM15_CCMR1_Output_OC1FE_len EQU 1
TIM15_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM15_CCMR1_Output_OC1PE_ofs EQU 3
TIM15_CCMR1_Output_OC1PE_len EQU 1
TIM15_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM15_CCMR1_Output_OC1M_ofs EQU 4
TIM15_CCMR1_Output_OC1M_len EQU 3
TIM15_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Output_CC2S_ofs EQU 8
TIM15_CCMR1_Output_CC2S_len EQU 2
TIM15_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM15_CCMR1_Output_OC2FE_ofs EQU 10
TIM15_CCMR1_Output_OC2FE_len EQU 1
TIM15_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM15_CCMR1_Output_OC2PE_ofs EQU 11
TIM15_CCMR1_Output_OC2PE_len EQU 1
TIM15_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM15_CCMR1_Output_OC2M_ofs EQU 12
TIM15_CCMR1_Output_OC2M_len EQU 3
TIM15_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM15_CCMR1_Output_OC1M_3_ofs EQU 16
TIM15_CCMR1_Output_OC1M_3_len EQU 1
TIM15_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM15_CCMR1_Output_OC2M_3_ofs EQU 24
TIM15_CCMR1_Output_OC2M_3_len EQU 1
; TIM15_CCMR1_Input fields:
TIM15_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM15_CCMR1_Input_IC2F_ofs EQU 12
TIM15_CCMR1_Input_IC2F_len EQU 4
TIM15_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM15_CCMR1_Input_IC2PSC_ofs EQU 10
TIM15_CCMR1_Input_IC2PSC_len EQU 2
TIM15_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Input_CC2S_ofs EQU 8
TIM15_CCMR1_Input_CC2S_len EQU 2
TIM15_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM15_CCMR1_Input_IC1F_ofs EQU 4
TIM15_CCMR1_Input_IC1F_len EQU 4
TIM15_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM15_CCMR1_Input_IC1PSC_ofs EQU 2
TIM15_CCMR1_Input_IC1PSC_len EQU 2
TIM15_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Input_CC1S_ofs EQU 0
TIM15_CCMR1_Input_CC1S_len EQU 2
; TIM15_CCER fields:
TIM15_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2NP_ofs EQU 7
TIM15_CCER_CC2NP_len EQU 1
TIM15_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2P_ofs EQU 5
TIM15_CCER_CC2P_len EQU 1
TIM15_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM15_CCER_CC2E_ofs EQU 4
TIM15_CCER_CC2E_len EQU 1
TIM15_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1NP_ofs EQU 3
TIM15_CCER_CC1NP_len EQU 1
TIM15_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM15_CCER_CC1NE_ofs EQU 2
TIM15_CCER_CC1NE_len EQU 1
TIM15_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1P_ofs EQU 1
TIM15_CCER_CC1P_len EQU 1
TIM15_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM15_CCER_CC1E_ofs EQU 0
TIM15_CCER_CC1E_len EQU 1
; TIM15_CNT fields:
TIM15_CNT_CNT EQU 0x0000ffff ; counter value
TIM15_CNT_CNT_ofs EQU 0
TIM15_CNT_CNT_len EQU 16
TIM15_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM15_CNT_UIFCPY_ofs EQU 31
TIM15_CNT_UIFCPY_len EQU 1
; TIM15_PSC fields:
TIM15_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM15_PSC_PSC_ofs EQU 0
TIM15_PSC_PSC_len EQU 16
; TIM15_ARR fields:
TIM15_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM15_ARR_ARR_ofs EQU 0
TIM15_ARR_ARR_len EQU 16
; TIM15_RCR fields:
TIM15_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM15_RCR_REP_ofs EQU 0
TIM15_RCR_REP_len EQU 8
; TIM15_CCR1 fields:
TIM15_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM15_CCR1_CCR1_ofs EQU 0
TIM15_CCR1_CCR1_len EQU 16
; TIM15_CCR2 fields:
TIM15_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM15_CCR2_CCR2_ofs EQU 0
TIM15_CCR2_CCR2_len EQU 16
; TIM15_BDTR fields:
TIM15_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM15_BDTR_MOE_ofs EQU 15
TIM15_BDTR_MOE_len EQU 1
TIM15_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM15_BDTR_AOE_ofs EQU 14
TIM15_BDTR_AOE_len EQU 1
TIM15_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM15_BDTR_BKP_ofs EQU 13
TIM15_BDTR_BKP_len EQU 1
TIM15_BDTR_BKE EQU 0x00001000 ; Break enable
TIM15_BDTR_BKE_ofs EQU 12
TIM15_BDTR_BKE_len EQU 1
TIM15_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM15_BDTR_OSSR_ofs EQU 11
TIM15_BDTR_OSSR_len EQU 1
TIM15_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM15_BDTR_OSSI_ofs EQU 10
TIM15_BDTR_OSSI_len EQU 1
TIM15_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM15_BDTR_LOCK_ofs EQU 8
TIM15_BDTR_LOCK_len EQU 2
TIM15_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM15_BDTR_DTG_ofs EQU 0
TIM15_BDTR_DTG_len EQU 8
TIM15_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM15_BDTR_BKF_ofs EQU 16
TIM15_BDTR_BKF_len EQU 4
; TIM15_DCR fields:
TIM15_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM15_DCR_DBL_ofs EQU 8
TIM15_DCR_DBL_len EQU 5
TIM15_DCR_DBA EQU 0x0000001f ; DMA base address
TIM15_DCR_DBA_ofs EQU 0
TIM15_DCR_DBA_len EQU 5
; TIM15_DMAR fields:
TIM15_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM15_DMAR_DMAB_ofs EQU 0
TIM15_DMAR_DMAB_len EQU 16
; ---- TIM16 -------------------------------------------------
; Desc: General-purpose-timers
; TIM16 base address:
TIM16_BASE EQU 0x40014400
; TIM16 registers:
TIM16_CR1 EQU (TIM16_BASE + 0x0) ; control register 1
TIM16_CR2 EQU (TIM16_BASE + 0x4) ; control register 2
TIM16_DIER EQU (TIM16_BASE + 0xc) ; DMA/Interrupt enable register
TIM16_SR EQU (TIM16_BASE + 0x10) ; status register
TIM16_EGR EQU (TIM16_BASE + 0x14) ; event generation register
TIM16_CCMR1_Output EQU (TIM16_BASE + 0x18) ; capture/compare mode register (output mode)
TIM16_CCMR1_Input EQU (TIM16_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM16_CCER EQU (TIM16_BASE + 0x20) ; capture/compare enable register
TIM16_CNT EQU (TIM16_BASE + 0x24) ; counter
TIM16_PSC EQU (TIM16_BASE + 0x28) ; prescaler
TIM16_ARR EQU (TIM16_BASE + 0x2c) ; auto-reload register
TIM16_RCR EQU (TIM16_BASE + 0x30) ; repetition counter register
TIM16_CCR1 EQU (TIM16_BASE + 0x34) ; capture/compare register 1
TIM16_BDTR EQU (TIM16_BASE + 0x44) ; break and dead-time register
TIM16_DCR EQU (TIM16_BASE + 0x48) ; DMA control register
TIM16_DMAR EQU (TIM16_BASE + 0x4c) ; DMA address for full transfer
TIM16_OR EQU (TIM16_BASE + 0x50) ; option register
; TIM16_CR1 fields:
TIM16_CR1_CEN EQU 0x00000001 ; Counter enable
TIM16_CR1_CEN_ofs EQU 0
TIM16_CR1_CEN_len EQU 1
TIM16_CR1_UDIS EQU 0x00000002 ; Update disable
TIM16_CR1_UDIS_ofs EQU 1
TIM16_CR1_UDIS_len EQU 1
TIM16_CR1_URS EQU 0x00000004 ; Update request source
TIM16_CR1_URS_ofs EQU 2
TIM16_CR1_URS_len EQU 1
TIM16_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM16_CR1_OPM_ofs EQU 3
TIM16_CR1_OPM_len EQU 1
TIM16_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM16_CR1_ARPE_ofs EQU 7
TIM16_CR1_ARPE_len EQU 1
TIM16_CR1_CKD EQU 0x00000300 ; Clock division
TIM16_CR1_CKD_ofs EQU 8
TIM16_CR1_CKD_len EQU 2
TIM16_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM16_CR1_UIFREMAP_ofs EQU 11
TIM16_CR1_UIFREMAP_len EQU 1
; TIM16_CR2 fields:
TIM16_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM16_CR2_OIS1N_ofs EQU 9
TIM16_CR2_OIS1N_len EQU 1
TIM16_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM16_CR2_OIS1_ofs EQU 8
TIM16_CR2_OIS1_len EQU 1
TIM16_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM16_CR2_CCDS_ofs EQU 3
TIM16_CR2_CCDS_len EQU 1
TIM16_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM16_CR2_CCUS_ofs EQU 2
TIM16_CR2_CCUS_len EQU 1
TIM16_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM16_CR2_CCPC_ofs EQU 0
TIM16_CR2_CCPC_len EQU 1
; TIM16_DIER fields:
TIM16_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM16_DIER_UIE_ofs EQU 0
TIM16_DIER_UIE_len EQU 1
TIM16_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM16_DIER_CC1IE_ofs EQU 1
TIM16_DIER_CC1IE_len EQU 1
TIM16_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM16_DIER_COMIE_ofs EQU 5
TIM16_DIER_COMIE_len EQU 1
TIM16_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM16_DIER_TIE_ofs EQU 6
TIM16_DIER_TIE_len EQU 1
TIM16_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM16_DIER_BIE_ofs EQU 7
TIM16_DIER_BIE_len EQU 1
TIM16_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM16_DIER_UDE_ofs EQU 8
TIM16_DIER_UDE_len EQU 1
TIM16_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM16_DIER_CC1DE_ofs EQU 9
TIM16_DIER_CC1DE_len EQU 1
TIM16_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM16_DIER_COMDE_ofs EQU 13
TIM16_DIER_COMDE_len EQU 1
TIM16_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM16_DIER_TDE_ofs EQU 14
TIM16_DIER_TDE_len EQU 1
; TIM16_SR fields:
TIM16_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM16_SR_CC1OF_ofs EQU 9
TIM16_SR_CC1OF_len EQU 1
TIM16_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM16_SR_BIF_ofs EQU 7
TIM16_SR_BIF_len EQU 1
TIM16_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM16_SR_TIF_ofs EQU 6
TIM16_SR_TIF_len EQU 1
TIM16_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM16_SR_COMIF_ofs EQU 5
TIM16_SR_COMIF_len EQU 1
TIM16_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM16_SR_CC1IF_ofs EQU 1
TIM16_SR_CC1IF_len EQU 1
TIM16_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM16_SR_UIF_ofs EQU 0
TIM16_SR_UIF_len EQU 1
; TIM16_EGR fields:
TIM16_EGR_BG EQU 0x00000080 ; Break generation
TIM16_EGR_BG_ofs EQU 7
TIM16_EGR_BG_len EQU 1
TIM16_EGR_TG EQU 0x00000040 ; Trigger generation
TIM16_EGR_TG_ofs EQU 6
TIM16_EGR_TG_len EQU 1
TIM16_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM16_EGR_COMG_ofs EQU 5
TIM16_EGR_COMG_len EQU 1
TIM16_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM16_EGR_CC1G_ofs EQU 1
TIM16_EGR_CC1G_len EQU 1
TIM16_EGR_UG EQU 0x00000001 ; Update generation
TIM16_EGR_UG_ofs EQU 0
TIM16_EGR_UG_len EQU 1
; TIM16_CCMR1_Output fields:
TIM16_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Output_CC1S_ofs EQU 0
TIM16_CCMR1_Output_CC1S_len EQU 2
TIM16_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM16_CCMR1_Output_OC1FE_ofs EQU 2
TIM16_CCMR1_Output_OC1FE_len EQU 1
TIM16_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM16_CCMR1_Output_OC1PE_ofs EQU 3
TIM16_CCMR1_Output_OC1PE_len EQU 1
TIM16_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_ofs EQU 4
TIM16_CCMR1_Output_OC1M_len EQU 3
TIM16_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_3_ofs EQU 16
TIM16_CCMR1_Output_OC1M_3_len EQU 1
; TIM16_CCMR1_Input fields:
TIM16_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM16_CCMR1_Input_IC1F_ofs EQU 4
TIM16_CCMR1_Input_IC1F_len EQU 4
TIM16_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM16_CCMR1_Input_IC1PSC_ofs EQU 2
TIM16_CCMR1_Input_IC1PSC_len EQU 2
TIM16_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Input_CC1S_ofs EQU 0
TIM16_CCMR1_Input_CC1S_len EQU 2
; TIM16_CCER fields:
TIM16_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1NP_ofs EQU 3
TIM16_CCER_CC1NP_len EQU 1
TIM16_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM16_CCER_CC1NE_ofs EQU 2
TIM16_CCER_CC1NE_len EQU 1
TIM16_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1P_ofs EQU 1
TIM16_CCER_CC1P_len EQU 1
TIM16_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM16_CCER_CC1E_ofs EQU 0
TIM16_CCER_CC1E_len EQU 1
; TIM16_CNT fields:
TIM16_CNT_CNT EQU 0x0000ffff ; counter value
TIM16_CNT_CNT_ofs EQU 0
TIM16_CNT_CNT_len EQU 16
TIM16_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM16_CNT_UIFCPY_ofs EQU 31
TIM16_CNT_UIFCPY_len EQU 1
; TIM16_PSC fields:
TIM16_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM16_PSC_PSC_ofs EQU 0
TIM16_PSC_PSC_len EQU 16
; TIM16_ARR fields:
TIM16_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM16_ARR_ARR_ofs EQU 0
TIM16_ARR_ARR_len EQU 16
; TIM16_RCR fields:
TIM16_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM16_RCR_REP_ofs EQU 0
TIM16_RCR_REP_len EQU 8
; TIM16_CCR1 fields:
TIM16_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM16_CCR1_CCR1_ofs EQU 0
TIM16_CCR1_CCR1_len EQU 16
; TIM16_BDTR fields:
TIM16_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM16_BDTR_DTG_ofs EQU 0
TIM16_BDTR_DTG_len EQU 8
TIM16_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM16_BDTR_LOCK_ofs EQU 8
TIM16_BDTR_LOCK_len EQU 2
TIM16_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM16_BDTR_OSSI_ofs EQU 10
TIM16_BDTR_OSSI_len EQU 1
TIM16_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM16_BDTR_OSSR_ofs EQU 11
TIM16_BDTR_OSSR_len EQU 1
TIM16_BDTR_BKE EQU 0x00001000 ; Break enable
TIM16_BDTR_BKE_ofs EQU 12
TIM16_BDTR_BKE_len EQU 1
TIM16_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM16_BDTR_BKP_ofs EQU 13
TIM16_BDTR_BKP_len EQU 1
TIM16_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM16_BDTR_AOE_ofs EQU 14
TIM16_BDTR_AOE_len EQU 1
TIM16_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM16_BDTR_MOE_ofs EQU 15
TIM16_BDTR_MOE_len EQU 1
TIM16_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM16_BDTR_BKF_ofs EQU 16
TIM16_BDTR_BKF_len EQU 4
; TIM16_DCR fields:
TIM16_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM16_DCR_DBL_ofs EQU 8
TIM16_DCR_DBL_len EQU 5
TIM16_DCR_DBA EQU 0x0000001f ; DMA base address
TIM16_DCR_DBA_ofs EQU 0
TIM16_DCR_DBA_len EQU 5
; TIM16_DMAR fields:
TIM16_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM16_DMAR_DMAB_ofs EQU 0
TIM16_DMAR_DMAB_len EQU 16
; TIM16_OR fields:
; ---- TIM17 -------------------------------------------------
; Desc: General purpose timer
; TIM17 base address:
TIM17_BASE EQU 0x40014800
; TIM17 registers:
TIM17_CR1 EQU (TIM17_BASE + 0x0) ; control register 1
TIM17_CR2 EQU (TIM17_BASE + 0x4) ; control register 2
TIM17_DIER EQU (TIM17_BASE + 0xc) ; DMA/Interrupt enable register
TIM17_SR EQU (TIM17_BASE + 0x10) ; status register
TIM17_EGR EQU (TIM17_BASE + 0x14) ; event generation register
TIM17_CCMR1_Output EQU (TIM17_BASE + 0x18) ; capture/compare mode register (output mode)
TIM17_CCMR1_Input EQU (TIM17_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM17_CCER EQU (TIM17_BASE + 0x20) ; capture/compare enable register
TIM17_CNT EQU (TIM17_BASE + 0x24) ; counter
TIM17_PSC EQU (TIM17_BASE + 0x28) ; prescaler
TIM17_ARR EQU (TIM17_BASE + 0x2c) ; auto-reload register
TIM17_RCR EQU (TIM17_BASE + 0x30) ; repetition counter register
TIM17_CCR1 EQU (TIM17_BASE + 0x34) ; capture/compare register 1
TIM17_BDTR EQU (TIM17_BASE + 0x44) ; break and dead-time register
TIM17_DCR EQU (TIM17_BASE + 0x48) ; DMA control register
TIM17_DMAR EQU (TIM17_BASE + 0x4c) ; DMA address for full transfer
; TIM17_CR1 fields:
TIM17_CR1_CEN EQU 0x00000001 ; Counter enable
TIM17_CR1_CEN_ofs EQU 0
TIM17_CR1_CEN_len EQU 1
TIM17_CR1_UDIS EQU 0x00000002 ; Update disable
TIM17_CR1_UDIS_ofs EQU 1
TIM17_CR1_UDIS_len EQU 1
TIM17_CR1_URS EQU 0x00000004 ; Update request source
TIM17_CR1_URS_ofs EQU 2
TIM17_CR1_URS_len EQU 1
TIM17_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM17_CR1_OPM_ofs EQU 3
TIM17_CR1_OPM_len EQU 1
TIM17_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM17_CR1_ARPE_ofs EQU 7
TIM17_CR1_ARPE_len EQU 1
TIM17_CR1_CKD EQU 0x00000300 ; Clock division
TIM17_CR1_CKD_ofs EQU 8
TIM17_CR1_CKD_len EQU 2
TIM17_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM17_CR1_UIFREMAP_ofs EQU 11
TIM17_CR1_UIFREMAP_len EQU 1
; TIM17_CR2 fields:
TIM17_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM17_CR2_OIS1N_ofs EQU 9
TIM17_CR2_OIS1N_len EQU 1
TIM17_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM17_CR2_OIS1_ofs EQU 8
TIM17_CR2_OIS1_len EQU 1
TIM17_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM17_CR2_CCDS_ofs EQU 3
TIM17_CR2_CCDS_len EQU 1
TIM17_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM17_CR2_CCUS_ofs EQU 2
TIM17_CR2_CCUS_len EQU 1
TIM17_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM17_CR2_CCPC_ofs EQU 0
TIM17_CR2_CCPC_len EQU 1
; TIM17_DIER fields:
TIM17_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM17_DIER_UIE_ofs EQU 0
TIM17_DIER_UIE_len EQU 1
TIM17_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM17_DIER_CC1IE_ofs EQU 1
TIM17_DIER_CC1IE_len EQU 1
TIM17_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM17_DIER_COMIE_ofs EQU 5
TIM17_DIER_COMIE_len EQU 1
TIM17_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM17_DIER_TIE_ofs EQU 6
TIM17_DIER_TIE_len EQU 1
TIM17_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM17_DIER_BIE_ofs EQU 7
TIM17_DIER_BIE_len EQU 1
TIM17_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM17_DIER_UDE_ofs EQU 8
TIM17_DIER_UDE_len EQU 1
TIM17_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM17_DIER_CC1DE_ofs EQU 9
TIM17_DIER_CC1DE_len EQU 1
TIM17_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM17_DIER_COMDE_ofs EQU 13
TIM17_DIER_COMDE_len EQU 1
TIM17_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM17_DIER_TDE_ofs EQU 14
TIM17_DIER_TDE_len EQU 1
; TIM17_SR fields:
TIM17_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM17_SR_CC1OF_ofs EQU 9
TIM17_SR_CC1OF_len EQU 1
TIM17_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM17_SR_BIF_ofs EQU 7
TIM17_SR_BIF_len EQU 1
TIM17_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM17_SR_TIF_ofs EQU 6
TIM17_SR_TIF_len EQU 1
TIM17_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM17_SR_COMIF_ofs EQU 5
TIM17_SR_COMIF_len EQU 1
TIM17_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM17_SR_CC1IF_ofs EQU 1
TIM17_SR_CC1IF_len EQU 1
TIM17_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM17_SR_UIF_ofs EQU 0
TIM17_SR_UIF_len EQU 1
; TIM17_EGR fields:
TIM17_EGR_BG EQU 0x00000080 ; Break generation
TIM17_EGR_BG_ofs EQU 7
TIM17_EGR_BG_len EQU 1
TIM17_EGR_TG EQU 0x00000040 ; Trigger generation
TIM17_EGR_TG_ofs EQU 6
TIM17_EGR_TG_len EQU 1
TIM17_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM17_EGR_COMG_ofs EQU 5
TIM17_EGR_COMG_len EQU 1
TIM17_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM17_EGR_CC1G_ofs EQU 1
TIM17_EGR_CC1G_len EQU 1
TIM17_EGR_UG EQU 0x00000001 ; Update generation
TIM17_EGR_UG_ofs EQU 0
TIM17_EGR_UG_len EQU 1
; TIM17_CCMR1_Output fields:
TIM17_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Output_CC1S_ofs EQU 0
TIM17_CCMR1_Output_CC1S_len EQU 2
TIM17_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM17_CCMR1_Output_OC1FE_ofs EQU 2
TIM17_CCMR1_Output_OC1FE_len EQU 1
TIM17_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM17_CCMR1_Output_OC1PE_ofs EQU 3
TIM17_CCMR1_Output_OC1PE_len EQU 1
TIM17_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_ofs EQU 4
TIM17_CCMR1_Output_OC1M_len EQU 3
TIM17_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_3_ofs EQU 16
TIM17_CCMR1_Output_OC1M_3_len EQU 1
; TIM17_CCMR1_Input fields:
TIM17_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM17_CCMR1_Input_IC1F_ofs EQU 4
TIM17_CCMR1_Input_IC1F_len EQU 4
TIM17_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM17_CCMR1_Input_IC1PSC_ofs EQU 2
TIM17_CCMR1_Input_IC1PSC_len EQU 2
TIM17_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Input_CC1S_ofs EQU 0
TIM17_CCMR1_Input_CC1S_len EQU 2
; TIM17_CCER fields:
TIM17_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1NP_ofs EQU 3
TIM17_CCER_CC1NP_len EQU 1
TIM17_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM17_CCER_CC1NE_ofs EQU 2
TIM17_CCER_CC1NE_len EQU 1
TIM17_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1P_ofs EQU 1
TIM17_CCER_CC1P_len EQU 1
TIM17_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM17_CCER_CC1E_ofs EQU 0
TIM17_CCER_CC1E_len EQU 1
; TIM17_CNT fields:
TIM17_CNT_CNT EQU 0x0000ffff ; counter value
TIM17_CNT_CNT_ofs EQU 0
TIM17_CNT_CNT_len EQU 16
TIM17_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM17_CNT_UIFCPY_ofs EQU 31
TIM17_CNT_UIFCPY_len EQU 1
; TIM17_PSC fields:
TIM17_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM17_PSC_PSC_ofs EQU 0
TIM17_PSC_PSC_len EQU 16
; TIM17_ARR fields:
TIM17_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM17_ARR_ARR_ofs EQU 0
TIM17_ARR_ARR_len EQU 16
; TIM17_RCR fields:
TIM17_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM17_RCR_REP_ofs EQU 0
TIM17_RCR_REP_len EQU 8
; TIM17_CCR1 fields:
TIM17_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM17_CCR1_CCR1_ofs EQU 0
TIM17_CCR1_CCR1_len EQU 16
; TIM17_BDTR fields:
TIM17_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM17_BDTR_DTG_ofs EQU 0
TIM17_BDTR_DTG_len EQU 8
TIM17_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM17_BDTR_LOCK_ofs EQU 8
TIM17_BDTR_LOCK_len EQU 2
TIM17_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM17_BDTR_OSSI_ofs EQU 10
TIM17_BDTR_OSSI_len EQU 1
TIM17_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM17_BDTR_OSSR_ofs EQU 11
TIM17_BDTR_OSSR_len EQU 1
TIM17_BDTR_BKE EQU 0x00001000 ; Break enable
TIM17_BDTR_BKE_ofs EQU 12
TIM17_BDTR_BKE_len EQU 1
TIM17_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM17_BDTR_BKP_ofs EQU 13
TIM17_BDTR_BKP_len EQU 1
TIM17_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM17_BDTR_AOE_ofs EQU 14
TIM17_BDTR_AOE_len EQU 1
TIM17_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM17_BDTR_MOE_ofs EQU 15
TIM17_BDTR_MOE_len EQU 1
TIM17_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM17_BDTR_BKF_ofs EQU 16
TIM17_BDTR_BKF_len EQU 4
; TIM17_DCR fields:
TIM17_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM17_DCR_DBL_ofs EQU 8
TIM17_DCR_DBL_len EQU 5
TIM17_DCR_DBA EQU 0x0000001f ; DMA base address
TIM17_DCR_DBA_ofs EQU 0
TIM17_DCR_DBA_len EQU 5
; TIM17_DMAR fields:
TIM17_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM17_DMAR_DMAB_ofs EQU 0
TIM17_DMAR_DMAB_len EQU 16
; ---- USART1 ------------------------------------------------
; Desc: Universal synchronous asynchronous receiver transmitter
; USART1 base address:
USART1_BASE EQU 0x40013800
; USART1 registers:
USART1_CR1 EQU (USART1_BASE + 0x0) ; Control register 1
USART1_CR2 EQU (USART1_BASE + 0x4) ; Control register 2
USART1_CR3 EQU (USART1_BASE + 0x8) ; Control register 3
USART1_BRR EQU (USART1_BASE + 0xc) ; Baud rate register
USART1_GTPR EQU (USART1_BASE + 0x10) ; Guard time and prescaler register
USART1_RTOR EQU (USART1_BASE + 0x14) ; Receiver timeout register
USART1_RQR EQU (USART1_BASE + 0x18) ; Request register
USART1_ISR EQU (USART1_BASE + 0x1c) ; Interrupt & status register
USART1_ICR EQU (USART1_BASE + 0x20) ; Interrupt flag clear register
USART1_RDR EQU (USART1_BASE + 0x24) ; Receive data register
USART1_TDR EQU (USART1_BASE + 0x28) ; Transmit data register
; USART1_CR1 fields:
USART_CR1_EOBIE EQU 0x08000000 ; End of Block interrupt enable
USART_CR1_EOBIE_ofs EQU 27
USART_CR1_EOBIE_len EQU 1
USART_CR1_RTOIE EQU 0x04000000 ; Receiver timeout interrupt enable
USART_CR1_RTOIE_ofs EQU 26
USART_CR1_RTOIE_len EQU 1
USART_CR1_DEAT EQU 0x03e00000 ; Driver Enable assertion time
USART_CR1_DEAT_ofs EQU 21
USART_CR1_DEAT_len EQU 5
USART_CR1_DEDT EQU 0x001f0000 ; Driver Enable deassertion time
USART_CR1_DEDT_ofs EQU 16
USART_CR1_DEDT_len EQU 5
USART_CR1_OVER8 EQU 0x00008000 ; Oversampling mode
USART_CR1_OVER8_ofs EQU 15
USART_CR1_OVER8_len EQU 1
USART_CR1_CMIE EQU 0x00004000 ; Character match interrupt enable
USART_CR1_CMIE_ofs EQU 14
USART_CR1_CMIE_len EQU 1
USART_CR1_MME EQU 0x00002000 ; Mute mode enable
USART_CR1_MME_ofs EQU 13
USART_CR1_MME_len EQU 1
USART_CR1_M EQU 0x00001000 ; Word length
USART_CR1_M_ofs EQU 12
USART_CR1_M_len EQU 1
USART_CR1_WAKE EQU 0x00000800 ; Receiver wakeup method
USART_CR1_WAKE_ofs EQU 11
USART_CR1_WAKE_len EQU 1
USART_CR1_PCE EQU 0x00000400 ; Parity control enable
USART_CR1_PCE_ofs EQU 10
USART_CR1_PCE_len EQU 1
USART_CR1_PS EQU 0x00000200 ; Parity selection
USART_CR1_PS_ofs EQU 9
USART_CR1_PS_len EQU 1
USART_CR1_PEIE EQU 0x00000100 ; PE interrupt enable
USART_CR1_PEIE_ofs EQU 8
USART_CR1_PEIE_len EQU 1
USART_CR1_TXEIE EQU 0x00000080 ; interrupt enable
USART_CR1_TXEIE_ofs EQU 7
USART_CR1_TXEIE_len EQU 1
USART_CR1_TCIE EQU 0x00000040 ; Transmission complete interrupt enable
USART_CR1_TCIE_ofs EQU 6
USART_CR1_TCIE_len EQU 1
USART_CR1_RXNEIE EQU 0x00000020 ; RXNE interrupt enable
USART_CR1_RXNEIE_ofs EQU 5
USART_CR1_RXNEIE_len EQU 1
USART_CR1_IDLEIE EQU 0x00000010 ; IDLE interrupt enable
USART_CR1_IDLEIE_ofs EQU 4
USART_CR1_IDLEIE_len EQU 1
USART_CR1_TE EQU 0x00000008 ; Transmitter enable
USART_CR1_TE_ofs EQU 3
USART_CR1_TE_len EQU 1
USART_CR1_RE EQU 0x00000004 ; Receiver enable
USART_CR1_RE_ofs EQU 2
USART_CR1_RE_len EQU 1
USART_CR1_UESM EQU 0x00000002 ; USART enable in Stop mode
USART_CR1_UESM_ofs EQU 1
USART_CR1_UESM_len EQU 1
USART_CR1_UE EQU 0x00000001 ; USART enable
USART_CR1_UE_ofs EQU 0
USART_CR1_UE_len EQU 1
; USART1_CR2 fields:
USART_CR2_ADD4 EQU 0xf0000000 ; Address of the USART node
USART_CR2_ADD4_ofs EQU 28
USART_CR2_ADD4_len EQU 4
USART_CR2_ADD0 EQU 0x0f000000 ; Address of the USART node
USART_CR2_ADD0_ofs EQU 24
USART_CR2_ADD0_len EQU 4
USART_CR2_RTOEN EQU 0x00800000 ; Receiver timeout enable
USART_CR2_RTOEN_ofs EQU 23
USART_CR2_RTOEN_len EQU 1
USART_CR2_ABRMOD EQU 0x00600000 ; Auto baud rate mode
USART_CR2_ABRMOD_ofs EQU 21
USART_CR2_ABRMOD_len EQU 2
USART_CR2_ABREN EQU 0x00100000 ; Auto baud rate enable
USART_CR2_ABREN_ofs EQU 20
USART_CR2_ABREN_len EQU 1
USART_CR2_MSBFIRST EQU 0x00080000 ; Most significant bit first
USART_CR2_MSBFIRST_ofs EQU 19
USART_CR2_MSBFIRST_len EQU 1
USART_CR2_DATAINV EQU 0x00040000 ; Binary data inversion
USART_CR2_DATAINV_ofs EQU 18
USART_CR2_DATAINV_len EQU 1
USART_CR2_TXINV EQU 0x00020000 ; TX pin active level inversion
USART_CR2_TXINV_ofs EQU 17
USART_CR2_TXINV_len EQU 1
USART_CR2_RXINV EQU 0x00010000 ; RX pin active level inversion
USART_CR2_RXINV_ofs EQU 16
USART_CR2_RXINV_len EQU 1
USART_CR2_SWAP EQU 0x00008000 ; Swap TX/RX pins
USART_CR2_SWAP_ofs EQU 15
USART_CR2_SWAP_len EQU 1
USART_CR2_LINEN EQU 0x00004000 ; LIN mode enable
USART_CR2_LINEN_ofs EQU 14
USART_CR2_LINEN_len EQU 1
USART_CR2_STOP EQU 0x00003000 ; STOP bits
USART_CR2_STOP_ofs EQU 12
USART_CR2_STOP_len EQU 2
USART_CR2_CLKEN EQU 0x00000800 ; Clock enable
USART_CR2_CLKEN_ofs EQU 11
USART_CR2_CLKEN_len EQU 1
USART_CR2_CPOL EQU 0x00000400 ; Clock polarity
USART_CR2_CPOL_ofs EQU 10
USART_CR2_CPOL_len EQU 1
USART_CR2_CPHA EQU 0x00000200 ; Clock phase
USART_CR2_CPHA_ofs EQU 9
USART_CR2_CPHA_len EQU 1
USART_CR2_LBCL EQU 0x00000100 ; Last bit clock pulse
USART_CR2_LBCL_ofs EQU 8
USART_CR2_LBCL_len EQU 1
USART_CR2_LBDIE EQU 0x00000040 ; LIN break detection interrupt enable
USART_CR2_LBDIE_ofs EQU 6
USART_CR2_LBDIE_len EQU 1
USART_CR2_LBDL EQU 0x00000020 ; LIN break detection length
USART_CR2_LBDL_ofs EQU 5
USART_CR2_LBDL_len EQU 1
USART_CR2_ADDM7 EQU 0x00000010 ; 7-bit Address Detection/4-bit Address Detection
USART_CR2_ADDM7_ofs EQU 4
USART_CR2_ADDM7_len EQU 1
; USART1_CR3 fields:
USART_CR3_WUFIE EQU 0x00400000 ; Wakeup from Stop mode interrupt enable
USART_CR3_WUFIE_ofs EQU 22
USART_CR3_WUFIE_len EQU 1
USART_CR3_WUS EQU 0x00300000 ; Wakeup from Stop mode interrupt flag selection
USART_CR3_WUS_ofs EQU 20
USART_CR3_WUS_len EQU 2
USART_CR3_SCARCNT EQU 0x000e0000 ; Smartcard auto-retry count
USART_CR3_SCARCNT_ofs EQU 17
USART_CR3_SCARCNT_len EQU 3
USART_CR3_DEP EQU 0x00008000 ; Driver enable polarity selection
USART_CR3_DEP_ofs EQU 15
USART_CR3_DEP_len EQU 1
USART_CR3_DEM EQU 0x00004000 ; Driver enable mode
USART_CR3_DEM_ofs EQU 14
USART_CR3_DEM_len EQU 1
USART_CR3_DDRE EQU 0x00002000 ; DMA Disable on Reception Error
USART_CR3_DDRE_ofs EQU 13
USART_CR3_DDRE_len EQU 1
USART_CR3_OVRDIS EQU 0x00001000 ; Overrun Disable
USART_CR3_OVRDIS_ofs EQU 12
USART_CR3_OVRDIS_len EQU 1
USART_CR3_ONEBIT EQU 0x00000800 ; One sample bit method enable
USART_CR3_ONEBIT_ofs EQU 11
USART_CR3_ONEBIT_len EQU 1
USART_CR3_CTSIE EQU 0x00000400 ; CTS interrupt enable
USART_CR3_CTSIE_ofs EQU 10
USART_CR3_CTSIE_len EQU 1
USART_CR3_CTSE EQU 0x00000200 ; CTS enable
USART_CR3_CTSE_ofs EQU 9
USART_CR3_CTSE_len EQU 1
USART_CR3_RTSE EQU 0x00000100 ; RTS enable
USART_CR3_RTSE_ofs EQU 8
USART_CR3_RTSE_len EQU 1
USART_CR3_DMAT EQU 0x00000080 ; DMA enable transmitter
USART_CR3_DMAT_ofs EQU 7
USART_CR3_DMAT_len EQU 1
USART_CR3_DMAR EQU 0x00000040 ; DMA enable receiver
USART_CR3_DMAR_ofs EQU 6
USART_CR3_DMAR_len EQU 1
USART_CR3_SCEN EQU 0x00000020 ; Smartcard mode enable
USART_CR3_SCEN_ofs EQU 5
USART_CR3_SCEN_len EQU 1
USART_CR3_NACK EQU 0x00000010 ; Smartcard NACK enable
USART_CR3_NACK_ofs EQU 4
USART_CR3_NACK_len EQU 1
USART_CR3_HDSEL EQU 0x00000008 ; Half-duplex selection
USART_CR3_HDSEL_ofs EQU 3
USART_CR3_HDSEL_len EQU 1
USART_CR3_IRLP EQU 0x00000004 ; IrDA low-power
USART_CR3_IRLP_ofs EQU 2
USART_CR3_IRLP_len EQU 1
USART_CR3_IREN EQU 0x00000002 ; IrDA mode enable
USART_CR3_IREN_ofs EQU 1
USART_CR3_IREN_len EQU 1
USART_CR3_EIE EQU 0x00000001 ; Error interrupt enable
USART_CR3_EIE_ofs EQU 0
USART_CR3_EIE_len EQU 1
; USART1_BRR fields:
USART_BRR_DIV_Mantissa EQU 0x0000fff0 ; mantissa of USARTDIV
USART_BRR_DIV_Mantissa_ofs EQU 4
USART_BRR_DIV_Mantissa_len EQU 12
USART_BRR_DIV_Fraction EQU 0x0000000f ; fraction of USARTDIV
USART_BRR_DIV_Fraction_ofs EQU 0
USART_BRR_DIV_Fraction_len EQU 4
; USART1_GTPR fields:
USART_GTPR_GT EQU 0x0000ff00 ; Guard time value
USART_GTPR_GT_ofs EQU 8
USART_GTPR_GT_len EQU 8
USART_GTPR_PSC EQU 0x000000ff ; Prescaler value
USART_GTPR_PSC_ofs EQU 0
USART_GTPR_PSC_len EQU 8
; USART1_RTOR fields:
USART_RTOR_BLEN EQU 0xff000000 ; Block Length
USART_RTOR_BLEN_ofs EQU 24
USART_RTOR_BLEN_len EQU 8
USART_RTOR_RTO EQU 0x00ffffff ; Receiver timeout value
USART_RTOR_RTO_ofs EQU 0
USART_RTOR_RTO_len EQU 24
; USART1_RQR fields:
USART_RQR_TXFRQ EQU 0x00000010 ; Transmit data flush request
USART_RQR_TXFRQ_ofs EQU 4
USART_RQR_TXFRQ_len EQU 1
USART_RQR_RXFRQ EQU 0x00000008 ; Receive data flush request
USART_RQR_RXFRQ_ofs EQU 3
USART_RQR_RXFRQ_len EQU 1
USART_RQR_MMRQ EQU 0x00000004 ; Mute mode request
USART_RQR_MMRQ_ofs EQU 2
USART_RQR_MMRQ_len EQU 1
USART_RQR_SBKRQ EQU 0x00000002 ; Send break request
USART_RQR_SBKRQ_ofs EQU 1
USART_RQR_SBKRQ_len EQU 1
USART_RQR_ABRRQ EQU 0x00000001 ; Auto baud rate request
USART_RQR_ABRRQ_ofs EQU 0
USART_RQR_ABRRQ_len EQU 1
; USART1_ISR fields:
USART_ISR_REACK EQU 0x00400000 ; Receive enable acknowledge flag
USART_ISR_REACK_ofs EQU 22
USART_ISR_REACK_len EQU 1
USART_ISR_TEACK EQU 0x00200000 ; Transmit enable acknowledge flag
USART_ISR_TEACK_ofs EQU 21
USART_ISR_TEACK_len EQU 1
USART_ISR_WUF EQU 0x00100000 ; Wakeup from Stop mode flag
USART_ISR_WUF_ofs EQU 20
USART_ISR_WUF_len EQU 1
USART_ISR_RWU EQU 0x00080000 ; Receiver wakeup from Mute mode
USART_ISR_RWU_ofs EQU 19
USART_ISR_RWU_len EQU 1
USART_ISR_SBKF EQU 0x00040000 ; Send break flag
USART_ISR_SBKF_ofs EQU 18
USART_ISR_SBKF_len EQU 1
USART_ISR_CMF EQU 0x00020000 ; character match flag
USART_ISR_CMF_ofs EQU 17
USART_ISR_CMF_len EQU 1
USART_ISR_BUSY EQU 0x00010000 ; Busy flag
USART_ISR_BUSY_ofs EQU 16
USART_ISR_BUSY_len EQU 1
USART_ISR_ABRF EQU 0x00008000 ; Auto baud rate flag
USART_ISR_ABRF_ofs EQU 15
USART_ISR_ABRF_len EQU 1
USART_ISR_ABRE EQU 0x00004000 ; Auto baud rate error
USART_ISR_ABRE_ofs EQU 14
USART_ISR_ABRE_len EQU 1
USART_ISR_EOBF EQU 0x00001000 ; End of block flag
USART_ISR_EOBF_ofs EQU 12
USART_ISR_EOBF_len EQU 1
USART_ISR_RTOF EQU 0x00000800 ; Receiver timeout
USART_ISR_RTOF_ofs EQU 11
USART_ISR_RTOF_len EQU 1
USART_ISR_CTS EQU 0x00000400 ; CTS flag
USART_ISR_CTS_ofs EQU 10
USART_ISR_CTS_len EQU 1
USART_ISR_CTSIF EQU 0x00000200 ; CTS interrupt flag
USART_ISR_CTSIF_ofs EQU 9
USART_ISR_CTSIF_len EQU 1
USART_ISR_LBDF EQU 0x00000100 ; LIN break detection flag
USART_ISR_LBDF_ofs EQU 8
USART_ISR_LBDF_len EQU 1
USART_ISR_TXE EQU 0x00000080 ; Transmit data register empty
USART_ISR_TXE_ofs EQU 7
USART_ISR_TXE_len EQU 1
USART_ISR_TC EQU 0x00000040 ; Transmission complete
USART_ISR_TC_ofs EQU 6
USART_ISR_TC_len EQU 1
USART_ISR_RXNE EQU 0x00000020 ; Read data register not empty
USART_ISR_RXNE_ofs EQU 5
USART_ISR_RXNE_len EQU 1
USART_ISR_IDLE EQU 0x00000010 ; Idle line detected
USART_ISR_IDLE_ofs EQU 4
USART_ISR_IDLE_len EQU 1
USART_ISR_ORE EQU 0x00000008 ; Overrun error
USART_ISR_ORE_ofs EQU 3
USART_ISR_ORE_len EQU 1
USART_ISR_NF EQU 0x00000004 ; Noise detected flag
USART_ISR_NF_ofs EQU 2
USART_ISR_NF_len EQU 1
USART_ISR_FE EQU 0x00000002 ; Framing error
USART_ISR_FE_ofs EQU 1
USART_ISR_FE_len EQU 1
USART_ISR_PE EQU 0x00000001 ; Parity error
USART_ISR_PE_ofs EQU 0
USART_ISR_PE_len EQU 1
; USART1_ICR fields:
USART_ICR_WUCF EQU 0x00100000 ; Wakeup from Stop mode clear flag
USART_ICR_WUCF_ofs EQU 20
USART_ICR_WUCF_len EQU 1
USART_ICR_CMCF EQU 0x00020000 ; Character match clear flag
USART_ICR_CMCF_ofs EQU 17
USART_ICR_CMCF_len EQU 1
USART_ICR_EOBCF EQU 0x00001000 ; End of timeout clear flag
USART_ICR_EOBCF_ofs EQU 12
USART_ICR_EOBCF_len EQU 1
USART_ICR_RTOCF EQU 0x00000800 ; Receiver timeout clear flag
USART_ICR_RTOCF_ofs EQU 11
USART_ICR_RTOCF_len EQU 1
USART_ICR_CTSCF EQU 0x00000200 ; CTS clear flag
USART_ICR_CTSCF_ofs EQU 9
USART_ICR_CTSCF_len EQU 1
USART_ICR_LBDCF EQU 0x00000100 ; LIN break detection clear flag
USART_ICR_LBDCF_ofs EQU 8
USART_ICR_LBDCF_len EQU 1
USART_ICR_TCCF EQU 0x00000040 ; Transmission complete clear flag
USART_ICR_TCCF_ofs EQU 6
USART_ICR_TCCF_len EQU 1
USART_ICR_IDLECF EQU 0x00000010 ; Idle line detected clear flag
USART_ICR_IDLECF_ofs EQU 4
USART_ICR_IDLECF_len EQU 1
USART_ICR_ORECF EQU 0x00000008 ; Overrun error clear flag
USART_ICR_ORECF_ofs EQU 3
USART_ICR_ORECF_len EQU 1
USART_ICR_NCF EQU 0x00000004 ; Noise detected clear flag
USART_ICR_NCF_ofs EQU 2
USART_ICR_NCF_len EQU 1
USART_ICR_FECF EQU 0x00000002 ; Framing error clear flag
USART_ICR_FECF_ofs EQU 1
USART_ICR_FECF_len EQU 1
USART_ICR_PECF EQU 0x00000001 ; Parity error clear flag
USART_ICR_PECF_ofs EQU 0
USART_ICR_PECF_len EQU 1
; USART1_RDR fields:
USART_RDR_RDR EQU 0x000001ff ; Receive data value
USART_RDR_RDR_ofs EQU 0
USART_RDR_RDR_len EQU 9
; USART1_TDR fields:
USART_TDR_TDR EQU 0x000001ff ; Transmit data value
USART_TDR_TDR_ofs EQU 0
USART_TDR_TDR_len EQU 9
; ---- USART2 ------------------------------------------------
; Desc: None
; USART2 base address:
USART2_BASE EQU 0x40004400
; USART2 registers:
USART2_CR1 EQU (USART2_BASE + 0x0) ; Control register 1
USART2_CR2 EQU (USART2_BASE + 0x4) ; Control register 2
USART2_CR3 EQU (USART2_BASE + 0x8) ; Control register 3
USART2_BRR EQU (USART2_BASE + 0xc) ; Baud rate register
USART2_GTPR EQU (USART2_BASE + 0x10) ; Guard time and prescaler register
USART2_RTOR EQU (USART2_BASE + 0x14) ; Receiver timeout register
USART2_RQR EQU (USART2_BASE + 0x18) ; Request register
USART2_ISR EQU (USART2_BASE + 0x1c) ; Interrupt & status register
USART2_ICR EQU (USART2_BASE + 0x20) ; Interrupt flag clear register
USART2_RDR EQU (USART2_BASE + 0x24) ; Receive data register
USART2_TDR EQU (USART2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- USART3 ------------------------------------------------
; Desc: None
; USART3 base address:
USART3_BASE EQU 0x40004800
; USART3 registers:
USART3_CR1 EQU (USART3_BASE + 0x0) ; Control register 1
USART3_CR2 EQU (USART3_BASE + 0x4) ; Control register 2
USART3_CR3 EQU (USART3_BASE + 0x8) ; Control register 3
USART3_BRR EQU (USART3_BASE + 0xc) ; Baud rate register
USART3_GTPR EQU (USART3_BASE + 0x10) ; Guard time and prescaler register
USART3_RTOR EQU (USART3_BASE + 0x14) ; Receiver timeout register
USART3_RQR EQU (USART3_BASE + 0x18) ; Request register
USART3_ISR EQU (USART3_BASE + 0x1c) ; Interrupt & status register
USART3_ICR EQU (USART3_BASE + 0x20) ; Interrupt flag clear register
USART3_RDR EQU (USART3_BASE + 0x24) ; Receive data register
USART3_TDR EQU (USART3_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- UART4 -------------------------------------------------
; Desc: None
; UART4 base address:
UART4_BASE EQU 0x40004c00
; UART4 registers:
; ---- UART5 -------------------------------------------------
; Desc: None
; UART5 base address:
UART5_BASE EQU 0x40005000
; UART5 registers:
; ---- SPI1 --------------------------------------------------
; Desc: Serial peripheral interface/Inter-IC sound
; SPI1 base address:
SPI1_BASE EQU 0x40013000
; SPI1 registers:
SPI1_CR1 EQU (SPI1_BASE + 0x0) ; control register 1
SPI1_CR2 EQU (SPI1_BASE + 0x4) ; control register 2
SPI1_SR EQU (SPI1_BASE + 0x8) ; status register
SPI1_DR EQU (SPI1_BASE + 0xc) ; data register
SPI1_CRCPR EQU (SPI1_BASE + 0x10) ; CRC polynomial register
SPI1_RXCRCR EQU (SPI1_BASE + 0x14) ; RX CRC register
SPI1_TXCRCR EQU (SPI1_BASE + 0x18) ; TX CRC register
SPI1_I2SCFGR EQU (SPI1_BASE + 0x1c) ; I2S configuration register
SPI1_I2SPR EQU (SPI1_BASE + 0x20) ; I2S prescaler register
; SPI1_CR1 fields:
SPI1_CR1_BIDIMODE EQU 0x00008000 ; Bidirectional data mode enable
SPI1_CR1_BIDIMODE_ofs EQU 15
SPI1_CR1_BIDIMODE_len EQU 1
SPI1_CR1_BIDIOE EQU 0x00004000 ; Output enable in bidirectional mode
SPI1_CR1_BIDIOE_ofs EQU 14
SPI1_CR1_BIDIOE_len EQU 1
SPI1_CR1_CRCEN EQU 0x00002000 ; Hardware CRC calculation enable
SPI1_CR1_CRCEN_ofs EQU 13
SPI1_CR1_CRCEN_len EQU 1
SPI1_CR1_CRCNEXT EQU 0x00001000 ; CRC transfer next
SPI1_CR1_CRCNEXT_ofs EQU 12
SPI1_CR1_CRCNEXT_len EQU 1
SPI1_CR1_DFF EQU 0x00000800 ; Data frame format
SPI1_CR1_DFF_ofs EQU 11
SPI1_CR1_DFF_len EQU 1
SPI1_CR1_RXONLY EQU 0x00000400 ; Receive only
SPI1_CR1_RXONLY_ofs EQU 10
SPI1_CR1_RXONLY_len EQU 1
SPI1_CR1_SSM EQU 0x00000200 ; Software slave management
SPI1_CR1_SSM_ofs EQU 9
SPI1_CR1_SSM_len EQU 1
SPI1_CR1_SSI EQU 0x00000100 ; Internal slave select
SPI1_CR1_SSI_ofs EQU 8
SPI1_CR1_SSI_len EQU 1
SPI1_CR1_LSBFIRST EQU 0x00000080 ; Frame format
SPI1_CR1_LSBFIRST_ofs EQU 7
SPI1_CR1_LSBFIRST_len EQU 1
SPI1_CR1_SPE EQU 0x00000040 ; SPI enable
SPI1_CR1_SPE_ofs EQU 6
SPI1_CR1_SPE_len EQU 1
SPI1_CR1_BR EQU 0x00000038 ; Baud rate control
SPI1_CR1_BR_ofs EQU 3
SPI1_CR1_BR_len EQU 3
SPI1_CR1_MSTR EQU 0x00000004 ; Master selection
SPI1_CR1_MSTR_ofs EQU 2
SPI1_CR1_MSTR_len EQU 1
SPI1_CR1_CPOL EQU 0x00000002 ; Clock polarity
SPI1_CR1_CPOL_ofs EQU 1
SPI1_CR1_CPOL_len EQU 1
SPI1_CR1_CPHA EQU 0x00000001 ; Clock phase
SPI1_CR1_CPHA_ofs EQU 0
SPI1_CR1_CPHA_len EQU 1
; SPI1_CR2 fields:
SPI1_CR2_RXDMAEN EQU 0x00000001 ; Rx buffer DMA enable
SPI1_CR2_RXDMAEN_ofs EQU 0
SPI1_CR2_RXDMAEN_len EQU 1
SPI1_CR2_TXDMAEN EQU 0x00000002 ; Tx buffer DMA enable
SPI1_CR2_TXDMAEN_ofs EQU 1
SPI1_CR2_TXDMAEN_len EQU 1
SPI1_CR2_SSOE EQU 0x00000004 ; SS output enable
SPI1_CR2_SSOE_ofs EQU 2
SPI1_CR2_SSOE_len EQU 1
SPI1_CR2_NSSP EQU 0x00000008 ; NSS pulse management
SPI1_CR2_NSSP_ofs EQU 3
SPI1_CR2_NSSP_len EQU 1
SPI1_CR2_FRF EQU 0x00000010 ; Frame format
SPI1_CR2_FRF_ofs EQU 4
SPI1_CR2_FRF_len EQU 1
SPI1_CR2_ERRIE EQU 0x00000020 ; Error interrupt enable
SPI1_CR2_ERRIE_ofs EQU 5
SPI1_CR2_ERRIE_len EQU 1
SPI1_CR2_RXNEIE EQU 0x00000040 ; RX buffer not empty interrupt enable
SPI1_CR2_RXNEIE_ofs EQU 6
SPI1_CR2_RXNEIE_len EQU 1
SPI1_CR2_TXEIE EQU 0x00000080 ; Tx buffer empty interrupt enable
SPI1_CR2_TXEIE_ofs EQU 7
SPI1_CR2_TXEIE_len EQU 1
SPI1_CR2_DS EQU 0x00000f00 ; Data size
SPI1_CR2_DS_ofs EQU 8
SPI1_CR2_DS_len EQU 4
SPI1_CR2_FRXTH EQU 0x00001000 ; FIFO reception threshold
SPI1_CR2_FRXTH_ofs EQU 12
SPI1_CR2_FRXTH_len EQU 1
SPI1_CR2_LDMA_RX EQU 0x00002000 ; Last DMA transfer for reception
SPI1_CR2_LDMA_RX_ofs EQU 13
SPI1_CR2_LDMA_RX_len EQU 1
SPI1_CR2_LDMA_TX EQU 0x00004000 ; Last DMA transfer for transmission
SPI1_CR2_LDMA_TX_ofs EQU 14
SPI1_CR2_LDMA_TX_len EQU 1
; SPI1_SR fields:
SPI1_SR_RXNE EQU 0x00000001 ; Receive buffer not empty
SPI1_SR_RXNE_ofs EQU 0
SPI1_SR_RXNE_len EQU 1
SPI1_SR_TXE EQU 0x00000002 ; Transmit buffer empty
SPI1_SR_TXE_ofs EQU 1
SPI1_SR_TXE_len EQU 1
SPI1_SR_CHSIDE EQU 0x00000004 ; Channel side
SPI1_SR_CHSIDE_ofs EQU 2
SPI1_SR_CHSIDE_len EQU 1
SPI1_SR_UDR EQU 0x00000008 ; Underrun flag
SPI1_SR_UDR_ofs EQU 3
SPI1_SR_UDR_len EQU 1
SPI1_SR_CRCERR EQU 0x00000010 ; CRC error flag
SPI1_SR_CRCERR_ofs EQU 4
SPI1_SR_CRCERR_len EQU 1
SPI1_SR_MODF EQU 0x00000020 ; Mode fault
SPI1_SR_MODF_ofs EQU 5
SPI1_SR_MODF_len EQU 1
SPI1_SR_OVR EQU 0x00000040 ; Overrun flag
SPI1_SR_OVR_ofs EQU 6
SPI1_SR_OVR_len EQU 1
SPI1_SR_BSY EQU 0x00000080 ; Busy flag
SPI1_SR_BSY_ofs EQU 7
SPI1_SR_BSY_len EQU 1
SPI1_SR_TIFRFE EQU 0x00000100 ; TI frame format error
SPI1_SR_TIFRFE_ofs EQU 8
SPI1_SR_TIFRFE_len EQU 1
SPI1_SR_FRLVL EQU 0x00000600 ; FIFO reception level
SPI1_SR_FRLVL_ofs EQU 9
SPI1_SR_FRLVL_len EQU 2
SPI1_SR_FTLVL EQU 0x00001800 ; FIFO transmission level
SPI1_SR_FTLVL_ofs EQU 11
SPI1_SR_FTLVL_len EQU 2
; SPI1_DR fields:
SPI1_DR_DR EQU 0x0000ffff ; Data register
SPI1_DR_DR_ofs EQU 0
SPI1_DR_DR_len EQU 16
; SPI1_CRCPR fields:
SPI1_CRCPR_CRCPOLY EQU 0x0000ffff ; CRC polynomial register
SPI1_CRCPR_CRCPOLY_ofs EQU 0
SPI1_CRCPR_CRCPOLY_len EQU 16
; SPI1_RXCRCR fields:
SPI1_RXCRCR_RxCRC EQU 0x0000ffff ; Rx CRC register
SPI1_RXCRCR_RxCRC_ofs EQU 0
SPI1_RXCRCR_RxCRC_len EQU 16
; SPI1_TXCRCR fields:
SPI1_TXCRCR_TxCRC EQU 0x0000ffff ; Tx CRC register
SPI1_TXCRCR_TxCRC_ofs EQU 0
SPI1_TXCRCR_TxCRC_len EQU 16
; SPI1_I2SCFGR fields:
SPI1_I2SCFGR_I2SMOD EQU 0x00000800 ; I2S mode selection
SPI1_I2SCFGR_I2SMOD_ofs EQU 11
SPI1_I2SCFGR_I2SMOD_len EQU 1
SPI1_I2SCFGR_I2SE EQU 0x00000400 ; I2S Enable
SPI1_I2SCFGR_I2SE_ofs EQU 10
SPI1_I2SCFGR_I2SE_len EQU 1
SPI1_I2SCFGR_I2SCFG EQU 0x00000300 ; I2S configuration mode
SPI1_I2SCFGR_I2SCFG_ofs EQU 8
SPI1_I2SCFGR_I2SCFG_len EQU 2
SPI1_I2SCFGR_PCMSYNC EQU 0x00000080 ; PCM frame synchronization
SPI1_I2SCFGR_PCMSYNC_ofs EQU 7
SPI1_I2SCFGR_PCMSYNC_len EQU 1
SPI1_I2SCFGR_I2SSTD EQU 0x00000030 ; I2S standard selection
SPI1_I2SCFGR_I2SSTD_ofs EQU 4
SPI1_I2SCFGR_I2SSTD_len EQU 2
SPI1_I2SCFGR_CKPOL EQU 0x00000008 ; Steady state clock polarity
SPI1_I2SCFGR_CKPOL_ofs EQU 3
SPI1_I2SCFGR_CKPOL_len EQU 1
SPI1_I2SCFGR_DATLEN EQU 0x00000006 ; Data length to be transferred
SPI1_I2SCFGR_DATLEN_ofs EQU 1
SPI1_I2SCFGR_DATLEN_len EQU 2
SPI1_I2SCFGR_CHLEN EQU 0x00000001 ; Channel length (number of bits per audio channel)
SPI1_I2SCFGR_CHLEN_ofs EQU 0
SPI1_I2SCFGR_CHLEN_len EQU 1
; SPI1_I2SPR fields:
SPI1_I2SPR_MCKOE EQU 0x00000200 ; Master clock output enable
SPI1_I2SPR_MCKOE_ofs EQU 9
SPI1_I2SPR_MCKOE_len EQU 1
SPI1_I2SPR_ODD EQU 0x00000100 ; Odd factor for the prescaler
SPI1_I2SPR_ODD_ofs EQU 8
SPI1_I2SPR_ODD_len EQU 1
SPI1_I2SPR_I2SDIV EQU 0x000000ff ; I2S Linear prescaler
SPI1_I2SPR_I2SDIV_ofs EQU 0
SPI1_I2SPR_I2SDIV_len EQU 8
; ---- SPI2 --------------------------------------------------
; Desc: None
; SPI2 base address:
SPI2_BASE EQU 0x40003800
; SPI2 registers:
; ---- SPI3 --------------------------------------------------
; Desc: None
; SPI3 base address:
SPI3_BASE EQU 0x40003c00
; SPI3 registers:
; ---- I2S2ext -----------------------------------------------
; Desc: None
; I2S2ext base address:
I2S2ext_BASE EQU 0x40003400
; I2S2ext registers:
; ---- I2S3ext -----------------------------------------------
; Desc: None
; I2S3ext base address:
I2S3ext_BASE EQU 0x40004000
; I2S3ext registers:
; ---- EXTI --------------------------------------------------
; Desc: External interrupt/event controller
; EXTI base address:
EXTI_BASE EQU 0x40010400
; EXTI registers:
EXTI_IMR1 EQU (EXTI_BASE + 0x0) ; Interrupt mask register
EXTI_EMR1 EQU (EXTI_BASE + 0x4) ; Event mask register
EXTI_RTSR1 EQU (EXTI_BASE + 0x8) ; Rising Trigger selection register
EXTI_FTSR1 EQU (EXTI_BASE + 0xc) ; Falling Trigger selection register
EXTI_SWIER1 EQU (EXTI_BASE + 0x10) ; Software interrupt event register
EXTI_PR1 EQU (EXTI_BASE + 0x14) ; Pending register
EXTI_IMR2 EQU (EXTI_BASE + 0x18) ; Interrupt mask register
EXTI_EMR2 EQU (EXTI_BASE + 0x1c) ; Event mask register
EXTI_RTSR2 EQU (EXTI_BASE + 0x20) ; Rising Trigger selection register
EXTI_FTSR2 EQU (EXTI_BASE + 0x24) ; Falling Trigger selection register
EXTI_SWIER2 EQU (EXTI_BASE + 0x28) ; Software interrupt event register
EXTI_PR2 EQU (EXTI_BASE + 0x2c) ; Pending register
; EXTI_IMR1 fields:
EXTI_IMR1_MR0 EQU 0x00000001 ; Interrupt Mask on line 0
EXTI_IMR1_MR0_ofs EQU 0
EXTI_IMR1_MR0_len EQU 1
EXTI_IMR1_MR1 EQU 0x00000002 ; Interrupt Mask on line 1
EXTI_IMR1_MR1_ofs EQU 1
EXTI_IMR1_MR1_len EQU 1
EXTI_IMR1_MR2 EQU 0x00000004 ; Interrupt Mask on line 2
EXTI_IMR1_MR2_ofs EQU 2
EXTI_IMR1_MR2_len EQU 1
EXTI_IMR1_MR3 EQU 0x00000008 ; Interrupt Mask on line 3
EXTI_IMR1_MR3_ofs EQU 3
EXTI_IMR1_MR3_len EQU 1
EXTI_IMR1_MR4 EQU 0x00000010 ; Interrupt Mask on line 4
EXTI_IMR1_MR4_ofs EQU 4
EXTI_IMR1_MR4_len EQU 1
EXTI_IMR1_MR5 EQU 0x00000020 ; Interrupt Mask on line 5
EXTI_IMR1_MR5_ofs EQU 5
EXTI_IMR1_MR5_len EQU 1
EXTI_IMR1_MR6 EQU 0x00000040 ; Interrupt Mask on line 6
EXTI_IMR1_MR6_ofs EQU 6
EXTI_IMR1_MR6_len EQU 1
EXTI_IMR1_MR7 EQU 0x00000080 ; Interrupt Mask on line 7
EXTI_IMR1_MR7_ofs EQU 7
EXTI_IMR1_MR7_len EQU 1
EXTI_IMR1_MR8 EQU 0x00000100 ; Interrupt Mask on line 8
EXTI_IMR1_MR8_ofs EQU 8
EXTI_IMR1_MR8_len EQU 1
EXTI_IMR1_MR9 EQU 0x00000200 ; Interrupt Mask on line 9
EXTI_IMR1_MR9_ofs EQU 9
EXTI_IMR1_MR9_len EQU 1
EXTI_IMR1_MR10 EQU 0x00000400 ; Interrupt Mask on line 10
EXTI_IMR1_MR10_ofs EQU 10
EXTI_IMR1_MR10_len EQU 1
EXTI_IMR1_MR11 EQU 0x00000800 ; Interrupt Mask on line 11
EXTI_IMR1_MR11_ofs EQU 11
EXTI_IMR1_MR11_len EQU 1
EXTI_IMR1_MR12 EQU 0x00001000 ; Interrupt Mask on line 12
EXTI_IMR1_MR12_ofs EQU 12
EXTI_IMR1_MR12_len EQU 1
EXTI_IMR1_MR13 EQU 0x00002000 ; Interrupt Mask on line 13
EXTI_IMR1_MR13_ofs EQU 13
EXTI_IMR1_MR13_len EQU 1
EXTI_IMR1_MR14 EQU 0x00004000 ; Interrupt Mask on line 14
EXTI_IMR1_MR14_ofs EQU 14
EXTI_IMR1_MR14_len EQU 1
EXTI_IMR1_MR15 EQU 0x00008000 ; Interrupt Mask on line 15
EXTI_IMR1_MR15_ofs EQU 15
EXTI_IMR1_MR15_len EQU 1
EXTI_IMR1_MR16 EQU 0x00010000 ; Interrupt Mask on line 16
EXTI_IMR1_MR16_ofs EQU 16
EXTI_IMR1_MR16_len EQU 1
EXTI_IMR1_MR17 EQU 0x00020000 ; Interrupt Mask on line 17
EXTI_IMR1_MR17_ofs EQU 17
EXTI_IMR1_MR17_len EQU 1
EXTI_IMR1_MR18 EQU 0x00040000 ; Interrupt Mask on line 18
EXTI_IMR1_MR18_ofs EQU 18
EXTI_IMR1_MR18_len EQU 1
EXTI_IMR1_MR19 EQU 0x00080000 ; Interrupt Mask on line 19
EXTI_IMR1_MR19_ofs EQU 19
EXTI_IMR1_MR19_len EQU 1
EXTI_IMR1_MR20 EQU 0x00100000 ; Interrupt Mask on line 20
EXTI_IMR1_MR20_ofs EQU 20
EXTI_IMR1_MR20_len EQU 1
EXTI_IMR1_MR21 EQU 0x00200000 ; Interrupt Mask on line 21
EXTI_IMR1_MR21_ofs EQU 21
EXTI_IMR1_MR21_len EQU 1
EXTI_IMR1_MR22 EQU 0x00400000 ; Interrupt Mask on line 22
EXTI_IMR1_MR22_ofs EQU 22
EXTI_IMR1_MR22_len EQU 1
EXTI_IMR1_MR23 EQU 0x00800000 ; Interrupt Mask on line 23
EXTI_IMR1_MR23_ofs EQU 23
EXTI_IMR1_MR23_len EQU 1
EXTI_IMR1_MR24 EQU 0x01000000 ; Interrupt Mask on line 24
EXTI_IMR1_MR24_ofs EQU 24
EXTI_IMR1_MR24_len EQU 1
EXTI_IMR1_MR25 EQU 0x02000000 ; Interrupt Mask on line 25
EXTI_IMR1_MR25_ofs EQU 25
EXTI_IMR1_MR25_len EQU 1
EXTI_IMR1_MR26 EQU 0x04000000 ; Interrupt Mask on line 26
EXTI_IMR1_MR26_ofs EQU 26
EXTI_IMR1_MR26_len EQU 1
EXTI_IMR1_MR27 EQU 0x08000000 ; Interrupt Mask on line 27
EXTI_IMR1_MR27_ofs EQU 27
EXTI_IMR1_MR27_len EQU 1
EXTI_IMR1_MR28 EQU 0x10000000 ; Interrupt Mask on line 28
EXTI_IMR1_MR28_ofs EQU 28
EXTI_IMR1_MR28_len EQU 1
EXTI_IMR1_MR29 EQU 0x20000000 ; Interrupt Mask on line 29
EXTI_IMR1_MR29_ofs EQU 29
EXTI_IMR1_MR29_len EQU 1
EXTI_IMR1_MR30 EQU 0x40000000 ; Interrupt Mask on line 30
EXTI_IMR1_MR30_ofs EQU 30
EXTI_IMR1_MR30_len EQU 1
EXTI_IMR1_MR31 EQU 0x80000000 ; Interrupt Mask on line 31
EXTI_IMR1_MR31_ofs EQU 31
EXTI_IMR1_MR31_len EQU 1
; EXTI_EMR1 fields:
EXTI_EMR1_MR0 EQU 0x00000001 ; Event Mask on line 0
EXTI_EMR1_MR0_ofs EQU 0
EXTI_EMR1_MR0_len EQU 1
EXTI_EMR1_MR1 EQU 0x00000002 ; Event Mask on line 1
EXTI_EMR1_MR1_ofs EQU 1
EXTI_EMR1_MR1_len EQU 1
EXTI_EMR1_MR2 EQU 0x00000004 ; Event Mask on line 2
EXTI_EMR1_MR2_ofs EQU 2
EXTI_EMR1_MR2_len EQU 1
EXTI_EMR1_MR3 EQU 0x00000008 ; Event Mask on line 3
EXTI_EMR1_MR3_ofs EQU 3
EXTI_EMR1_MR3_len EQU 1
EXTI_EMR1_MR4 EQU 0x00000010 ; Event Mask on line 4
EXTI_EMR1_MR4_ofs EQU 4
EXTI_EMR1_MR4_len EQU 1
EXTI_EMR1_MR5 EQU 0x00000020 ; Event Mask on line 5
EXTI_EMR1_MR5_ofs EQU 5
EXTI_EMR1_MR5_len EQU 1
EXTI_EMR1_MR6 EQU 0x00000040 ; Event Mask on line 6
EXTI_EMR1_MR6_ofs EQU 6
EXTI_EMR1_MR6_len EQU 1
EXTI_EMR1_MR7 EQU 0x00000080 ; Event Mask on line 7
EXTI_EMR1_MR7_ofs EQU 7
EXTI_EMR1_MR7_len EQU 1
EXTI_EMR1_MR8 EQU 0x00000100 ; Event Mask on line 8
EXTI_EMR1_MR8_ofs EQU 8
EXTI_EMR1_MR8_len EQU 1
EXTI_EMR1_MR9 EQU 0x00000200 ; Event Mask on line 9
EXTI_EMR1_MR9_ofs EQU 9
EXTI_EMR1_MR9_len EQU 1
EXTI_EMR1_MR10 EQU 0x00000400 ; Event Mask on line 10
EXTI_EMR1_MR10_ofs EQU 10
EXTI_EMR1_MR10_len EQU 1
EXTI_EMR1_MR11 EQU 0x00000800 ; Event Mask on line 11
EXTI_EMR1_MR11_ofs EQU 11
EXTI_EMR1_MR11_len EQU 1
EXTI_EMR1_MR12 EQU 0x00001000 ; Event Mask on line 12
EXTI_EMR1_MR12_ofs EQU 12
EXTI_EMR1_MR12_len EQU 1
EXTI_EMR1_MR13 EQU 0x00002000 ; Event Mask on line 13
EXTI_EMR1_MR13_ofs EQU 13
EXTI_EMR1_MR13_len EQU 1
EXTI_EMR1_MR14 EQU 0x00004000 ; Event Mask on line 14
EXTI_EMR1_MR14_ofs EQU 14
EXTI_EMR1_MR14_len EQU 1
EXTI_EMR1_MR15 EQU 0x00008000 ; Event Mask on line 15
EXTI_EMR1_MR15_ofs EQU 15
EXTI_EMR1_MR15_len EQU 1
EXTI_EMR1_MR16 EQU 0x00010000 ; Event Mask on line 16
EXTI_EMR1_MR16_ofs EQU 16
EXTI_EMR1_MR16_len EQU 1
EXTI_EMR1_MR17 EQU 0x00020000 ; Event Mask on line 17
EXTI_EMR1_MR17_ofs EQU 17
EXTI_EMR1_MR17_len EQU 1
EXTI_EMR1_MR18 EQU 0x00040000 ; Event Mask on line 18
EXTI_EMR1_MR18_ofs EQU 18
EXTI_EMR1_MR18_len EQU 1
EXTI_EMR1_MR19 EQU 0x00080000 ; Event Mask on line 19
EXTI_EMR1_MR19_ofs EQU 19
EXTI_EMR1_MR19_len EQU 1
EXTI_EMR1_MR20 EQU 0x00100000 ; Event Mask on line 20
EXTI_EMR1_MR20_ofs EQU 20
EXTI_EMR1_MR20_len EQU 1
EXTI_EMR1_MR21 EQU 0x00200000 ; Event Mask on line 21
EXTI_EMR1_MR21_ofs EQU 21
EXTI_EMR1_MR21_len EQU 1
EXTI_EMR1_MR22 EQU 0x00400000 ; Event Mask on line 22
EXTI_EMR1_MR22_ofs EQU 22
EXTI_EMR1_MR22_len EQU 1
EXTI_EMR1_MR23 EQU 0x00800000 ; Event Mask on line 23
EXTI_EMR1_MR23_ofs EQU 23
EXTI_EMR1_MR23_len EQU 1
EXTI_EMR1_MR24 EQU 0x01000000 ; Event Mask on line 24
EXTI_EMR1_MR24_ofs EQU 24
EXTI_EMR1_MR24_len EQU 1
EXTI_EMR1_MR25 EQU 0x02000000 ; Event Mask on line 25
EXTI_EMR1_MR25_ofs EQU 25
EXTI_EMR1_MR25_len EQU 1
EXTI_EMR1_MR26 EQU 0x04000000 ; Event Mask on line 26
EXTI_EMR1_MR26_ofs EQU 26
EXTI_EMR1_MR26_len EQU 1
EXTI_EMR1_MR27 EQU 0x08000000 ; Event Mask on line 27
EXTI_EMR1_MR27_ofs EQU 27
EXTI_EMR1_MR27_len EQU 1
EXTI_EMR1_MR28 EQU 0x10000000 ; Event Mask on line 28
EXTI_EMR1_MR28_ofs EQU 28
EXTI_EMR1_MR28_len EQU 1
EXTI_EMR1_MR29 EQU 0x20000000 ; Event Mask on line 29
EXTI_EMR1_MR29_ofs EQU 29
EXTI_EMR1_MR29_len EQU 1
EXTI_EMR1_MR30 EQU 0x40000000 ; Event Mask on line 30
EXTI_EMR1_MR30_ofs EQU 30
EXTI_EMR1_MR30_len EQU 1
EXTI_EMR1_MR31 EQU 0x80000000 ; Event Mask on line 31
EXTI_EMR1_MR31_ofs EQU 31
EXTI_EMR1_MR31_len EQU 1
; EXTI_RTSR1 fields:
EXTI_RTSR1_TR0 EQU 0x00000001 ; Rising trigger event configuration of line 0
EXTI_RTSR1_TR0_ofs EQU 0
EXTI_RTSR1_TR0_len EQU 1
EXTI_RTSR1_TR1 EQU 0x00000002 ; Rising trigger event configuration of line 1
EXTI_RTSR1_TR1_ofs EQU 1
EXTI_RTSR1_TR1_len EQU 1
EXTI_RTSR1_TR2 EQU 0x00000004 ; Rising trigger event configuration of line 2
EXTI_RTSR1_TR2_ofs EQU 2
EXTI_RTSR1_TR2_len EQU 1
EXTI_RTSR1_TR3 EQU 0x00000008 ; Rising trigger event configuration of line 3
EXTI_RTSR1_TR3_ofs EQU 3
EXTI_RTSR1_TR3_len EQU 1
EXTI_RTSR1_TR4 EQU 0x00000010 ; Rising trigger event configuration of line 4
EXTI_RTSR1_TR4_ofs EQU 4
EXTI_RTSR1_TR4_len EQU 1
EXTI_RTSR1_TR5 EQU 0x00000020 ; Rising trigger event configuration of line 5
EXTI_RTSR1_TR5_ofs EQU 5
EXTI_RTSR1_TR5_len EQU 1
EXTI_RTSR1_TR6 EQU 0x00000040 ; Rising trigger event configuration of line 6
EXTI_RTSR1_TR6_ofs EQU 6
EXTI_RTSR1_TR6_len EQU 1
EXTI_RTSR1_TR7 EQU 0x00000080 ; Rising trigger event configuration of line 7
EXTI_RTSR1_TR7_ofs EQU 7
EXTI_RTSR1_TR7_len EQU 1
EXTI_RTSR1_TR8 EQU 0x00000100 ; Rising trigger event configuration of line 8
EXTI_RTSR1_TR8_ofs EQU 8
EXTI_RTSR1_TR8_len EQU 1
EXTI_RTSR1_TR9 EQU 0x00000200 ; Rising trigger event configuration of line 9
EXTI_RTSR1_TR9_ofs EQU 9
EXTI_RTSR1_TR9_len EQU 1
EXTI_RTSR1_TR10 EQU 0x00000400 ; Rising trigger event configuration of line 10
EXTI_RTSR1_TR10_ofs EQU 10
EXTI_RTSR1_TR10_len EQU 1
EXTI_RTSR1_TR11 EQU 0x00000800 ; Rising trigger event configuration of line 11
EXTI_RTSR1_TR11_ofs EQU 11
EXTI_RTSR1_TR11_len EQU 1
EXTI_RTSR1_TR12 EQU 0x00001000 ; Rising trigger event configuration of line 12
EXTI_RTSR1_TR12_ofs EQU 12
EXTI_RTSR1_TR12_len EQU 1
EXTI_RTSR1_TR13 EQU 0x00002000 ; Rising trigger event configuration of line 13
EXTI_RTSR1_TR13_ofs EQU 13
EXTI_RTSR1_TR13_len EQU 1
EXTI_RTSR1_TR14 EQU 0x00004000 ; Rising trigger event configuration of line 14
EXTI_RTSR1_TR14_ofs EQU 14
EXTI_RTSR1_TR14_len EQU 1
EXTI_RTSR1_TR15 EQU 0x00008000 ; Rising trigger event configuration of line 15
EXTI_RTSR1_TR15_ofs EQU 15
EXTI_RTSR1_TR15_len EQU 1
EXTI_RTSR1_TR16 EQU 0x00010000 ; Rising trigger event configuration of line 16
EXTI_RTSR1_TR16_ofs EQU 16
EXTI_RTSR1_TR16_len EQU 1
EXTI_RTSR1_TR17 EQU 0x00020000 ; Rising trigger event configuration of line 17
EXTI_RTSR1_TR17_ofs EQU 17
EXTI_RTSR1_TR17_len EQU 1
EXTI_RTSR1_TR18 EQU 0x00040000 ; Rising trigger event configuration of line 18
EXTI_RTSR1_TR18_ofs EQU 18
EXTI_RTSR1_TR18_len EQU 1
EXTI_RTSR1_TR19 EQU 0x00080000 ; Rising trigger event configuration of line 19
EXTI_RTSR1_TR19_ofs EQU 19
EXTI_RTSR1_TR19_len EQU 1
EXTI_RTSR1_TR20 EQU 0x00100000 ; Rising trigger event configuration of line 20
EXTI_RTSR1_TR20_ofs EQU 20
EXTI_RTSR1_TR20_len EQU 1
EXTI_RTSR1_TR21 EQU 0x00200000 ; Rising trigger event configuration of line 21
EXTI_RTSR1_TR21_ofs EQU 21
EXTI_RTSR1_TR21_len EQU 1
EXTI_RTSR1_TR22 EQU 0x00400000 ; Rising trigger event configuration of line 22
EXTI_RTSR1_TR22_ofs EQU 22
EXTI_RTSR1_TR22_len EQU 1
EXTI_RTSR1_TR29 EQU 0x20000000 ; Rising trigger event configuration of line 29
EXTI_RTSR1_TR29_ofs EQU 29
EXTI_RTSR1_TR29_len EQU 1
EXTI_RTSR1_TR30 EQU 0x40000000 ; Rising trigger event configuration of line 30
EXTI_RTSR1_TR30_ofs EQU 30
EXTI_RTSR1_TR30_len EQU 1
EXTI_RTSR1_TR31 EQU 0x80000000 ; Rising trigger event configuration of line 31
EXTI_RTSR1_TR31_ofs EQU 31
EXTI_RTSR1_TR31_len EQU 1
; EXTI_FTSR1 fields:
EXTI_FTSR1_TR0 EQU 0x00000001 ; Falling trigger event configuration of line 0
EXTI_FTSR1_TR0_ofs EQU 0
EXTI_FTSR1_TR0_len EQU 1
EXTI_FTSR1_TR1 EQU 0x00000002 ; Falling trigger event configuration of line 1
EXTI_FTSR1_TR1_ofs EQU 1
EXTI_FTSR1_TR1_len EQU 1
EXTI_FTSR1_TR2 EQU 0x00000004 ; Falling trigger event configuration of line 2
EXTI_FTSR1_TR2_ofs EQU 2
EXTI_FTSR1_TR2_len EQU 1
EXTI_FTSR1_TR3 EQU 0x00000008 ; Falling trigger event configuration of line 3
EXTI_FTSR1_TR3_ofs EQU 3
EXTI_FTSR1_TR3_len EQU 1
EXTI_FTSR1_TR4 EQU 0x00000010 ; Falling trigger event configuration of line 4
EXTI_FTSR1_TR4_ofs EQU 4
EXTI_FTSR1_TR4_len EQU 1
EXTI_FTSR1_TR5 EQU 0x00000020 ; Falling trigger event configuration of line 5
EXTI_FTSR1_TR5_ofs EQU 5
EXTI_FTSR1_TR5_len EQU 1
EXTI_FTSR1_TR6 EQU 0x00000040 ; Falling trigger event configuration of line 6
EXTI_FTSR1_TR6_ofs EQU 6
EXTI_FTSR1_TR6_len EQU 1
EXTI_FTSR1_TR7 EQU 0x00000080 ; Falling trigger event configuration of line 7
EXTI_FTSR1_TR7_ofs EQU 7
EXTI_FTSR1_TR7_len EQU 1
EXTI_FTSR1_TR8 EQU 0x00000100 ; Falling trigger event configuration of line 8
EXTI_FTSR1_TR8_ofs EQU 8
EXTI_FTSR1_TR8_len EQU 1
EXTI_FTSR1_TR9 EQU 0x00000200 ; Falling trigger event configuration of line 9
EXTI_FTSR1_TR9_ofs EQU 9
EXTI_FTSR1_TR9_len EQU 1
EXTI_FTSR1_TR10 EQU 0x00000400 ; Falling trigger event configuration of line 10
EXTI_FTSR1_TR10_ofs EQU 10
EXTI_FTSR1_TR10_len EQU 1
EXTI_FTSR1_TR11 EQU 0x00000800 ; Falling trigger event configuration of line 11
EXTI_FTSR1_TR11_ofs EQU 11
EXTI_FTSR1_TR11_len EQU 1
EXTI_FTSR1_TR12 EQU 0x00001000 ; Falling trigger event configuration of line 12
EXTI_FTSR1_TR12_ofs EQU 12
EXTI_FTSR1_TR12_len EQU 1
EXTI_FTSR1_TR13 EQU 0x00002000 ; Falling trigger event configuration of line 13
EXTI_FTSR1_TR13_ofs EQU 13
EXTI_FTSR1_TR13_len EQU 1
EXTI_FTSR1_TR14 EQU 0x00004000 ; Falling trigger event configuration of line 14
EXTI_FTSR1_TR14_ofs EQU 14
EXTI_FTSR1_TR14_len EQU 1
EXTI_FTSR1_TR15 EQU 0x00008000 ; Falling trigger event configuration of line 15
EXTI_FTSR1_TR15_ofs EQU 15
EXTI_FTSR1_TR15_len EQU 1
EXTI_FTSR1_TR16 EQU 0x00010000 ; Falling trigger event configuration of line 16
EXTI_FTSR1_TR16_ofs EQU 16
EXTI_FTSR1_TR16_len EQU 1
EXTI_FTSR1_TR17 EQU 0x00020000 ; Falling trigger event configuration of line 17
EXTI_FTSR1_TR17_ofs EQU 17
EXTI_FTSR1_TR17_len EQU 1
EXTI_FTSR1_TR18 EQU 0x00040000 ; Falling trigger event configuration of line 18
EXTI_FTSR1_TR18_ofs EQU 18
EXTI_FTSR1_TR18_len EQU 1
EXTI_FTSR1_TR19 EQU 0x00080000 ; Falling trigger event configuration of line 19
EXTI_FTSR1_TR19_ofs EQU 19
EXTI_FTSR1_TR19_len EQU 1
EXTI_FTSR1_TR20 EQU 0x00100000 ; Falling trigger event configuration of line 20
EXTI_FTSR1_TR20_ofs EQU 20
EXTI_FTSR1_TR20_len EQU 1
EXTI_FTSR1_TR21 EQU 0x00200000 ; Falling trigger event configuration of line 21
EXTI_FTSR1_TR21_ofs EQU 21
EXTI_FTSR1_TR21_len EQU 1
EXTI_FTSR1_TR22 EQU 0x00400000 ; Falling trigger event configuration of line 22
EXTI_FTSR1_TR22_ofs EQU 22
EXTI_FTSR1_TR22_len EQU 1
EXTI_FTSR1_TR29 EQU 0x20000000 ; Falling trigger event configuration of line 29
EXTI_FTSR1_TR29_ofs EQU 29
EXTI_FTSR1_TR29_len EQU 1
EXTI_FTSR1_TR30 EQU 0x40000000 ; Falling trigger event configuration of line 30.
EXTI_FTSR1_TR30_ofs EQU 30
EXTI_FTSR1_TR30_len EQU 1
EXTI_FTSR1_TR31 EQU 0x80000000 ; Falling trigger event configuration of line 31
EXTI_FTSR1_TR31_ofs EQU 31
EXTI_FTSR1_TR31_len EQU 1
; EXTI_SWIER1 fields:
EXTI_SWIER1_SWIER0 EQU 0x00000001 ; Software Interrupt on line 0
EXTI_SWIER1_SWIER0_ofs EQU 0
EXTI_SWIER1_SWIER0_len EQU 1
EXTI_SWIER1_SWIER1 EQU 0x00000002 ; Software Interrupt on line 1
EXTI_SWIER1_SWIER1_ofs EQU 1
EXTI_SWIER1_SWIER1_len EQU 1
EXTI_SWIER1_SWIER2 EQU 0x00000004 ; Software Interrupt on line 2
EXTI_SWIER1_SWIER2_ofs EQU 2
EXTI_SWIER1_SWIER2_len EQU 1
EXTI_SWIER1_SWIER3 EQU 0x00000008 ; Software Interrupt on line 3
EXTI_SWIER1_SWIER3_ofs EQU 3
EXTI_SWIER1_SWIER3_len EQU 1
EXTI_SWIER1_SWIER4 EQU 0x00000010 ; Software Interrupt on line 4
EXTI_SWIER1_SWIER4_ofs EQU 4
EXTI_SWIER1_SWIER4_len EQU 1
EXTI_SWIER1_SWIER5 EQU 0x00000020 ; Software Interrupt on line 5
EXTI_SWIER1_SWIER5_ofs EQU 5
EXTI_SWIER1_SWIER5_len EQU 1
EXTI_SWIER1_SWIER6 EQU 0x00000040 ; Software Interrupt on line 6
EXTI_SWIER1_SWIER6_ofs EQU 6
EXTI_SWIER1_SWIER6_len EQU 1
EXTI_SWIER1_SWIER7 EQU 0x00000080 ; Software Interrupt on line 7
EXTI_SWIER1_SWIER7_ofs EQU 7
EXTI_SWIER1_SWIER7_len EQU 1
EXTI_SWIER1_SWIER8 EQU 0x00000100 ; Software Interrupt on line 8
EXTI_SWIER1_SWIER8_ofs EQU 8
EXTI_SWIER1_SWIER8_len EQU 1
EXTI_SWIER1_SWIER9 EQU 0x00000200 ; Software Interrupt on line 9
EXTI_SWIER1_SWIER9_ofs EQU 9
EXTI_SWIER1_SWIER9_len EQU 1
EXTI_SWIER1_SWIER10 EQU 0x00000400 ; Software Interrupt on line 10
EXTI_SWIER1_SWIER10_ofs EQU 10
EXTI_SWIER1_SWIER10_len EQU 1
EXTI_SWIER1_SWIER11 EQU 0x00000800 ; Software Interrupt on line 11
EXTI_SWIER1_SWIER11_ofs EQU 11
EXTI_SWIER1_SWIER11_len EQU 1
EXTI_SWIER1_SWIER12 EQU 0x00001000 ; Software Interrupt on line 12
EXTI_SWIER1_SWIER12_ofs EQU 12
EXTI_SWIER1_SWIER12_len EQU 1
EXTI_SWIER1_SWIER13 EQU 0x00002000 ; Software Interrupt on line 13
EXTI_SWIER1_SWIER13_ofs EQU 13
EXTI_SWIER1_SWIER13_len EQU 1
EXTI_SWIER1_SWIER14 EQU 0x00004000 ; Software Interrupt on line 14
EXTI_SWIER1_SWIER14_ofs EQU 14
EXTI_SWIER1_SWIER14_len EQU 1
EXTI_SWIER1_SWIER15 EQU 0x00008000 ; Software Interrupt on line 15
EXTI_SWIER1_SWIER15_ofs EQU 15
EXTI_SWIER1_SWIER15_len EQU 1
EXTI_SWIER1_SWIER16 EQU 0x00010000 ; Software Interrupt on line 16
EXTI_SWIER1_SWIER16_ofs EQU 16
EXTI_SWIER1_SWIER16_len EQU 1
EXTI_SWIER1_SWIER17 EQU 0x00020000 ; Software Interrupt on line 17
EXTI_SWIER1_SWIER17_ofs EQU 17
EXTI_SWIER1_SWIER17_len EQU 1
EXTI_SWIER1_SWIER18 EQU 0x00040000 ; Software Interrupt on line 18
EXTI_SWIER1_SWIER18_ofs EQU 18
EXTI_SWIER1_SWIER18_len EQU 1
EXTI_SWIER1_SWIER19 EQU 0x00080000 ; Software Interrupt on line 19
EXTI_SWIER1_SWIER19_ofs EQU 19
EXTI_SWIER1_SWIER19_len EQU 1
EXTI_SWIER1_SWIER20 EQU 0x00100000 ; Software Interrupt on line 20
EXTI_SWIER1_SWIER20_ofs EQU 20
EXTI_SWIER1_SWIER20_len EQU 1
EXTI_SWIER1_SWIER21 EQU 0x00200000 ; Software Interrupt on line 21
EXTI_SWIER1_SWIER21_ofs EQU 21
EXTI_SWIER1_SWIER21_len EQU 1
EXTI_SWIER1_SWIER22 EQU 0x00400000 ; Software Interrupt on line 22
EXTI_SWIER1_SWIER22_ofs EQU 22
EXTI_SWIER1_SWIER22_len EQU 1
EXTI_SWIER1_SWIER29 EQU 0x20000000 ; Software Interrupt on line 29
EXTI_SWIER1_SWIER29_ofs EQU 29
EXTI_SWIER1_SWIER29_len EQU 1
EXTI_SWIER1_SWIER30 EQU 0x40000000 ; Software Interrupt on line 309
EXTI_SWIER1_SWIER30_ofs EQU 30
EXTI_SWIER1_SWIER30_len EQU 1
EXTI_SWIER1_SWIER31 EQU 0x80000000 ; Software Interrupt on line 319
EXTI_SWIER1_SWIER31_ofs EQU 31
EXTI_SWIER1_SWIER31_len EQU 1
; EXTI_PR1 fields:
EXTI_PR1_PR0 EQU 0x00000001 ; Pending bit 0
EXTI_PR1_PR0_ofs EQU 0
EXTI_PR1_PR0_len EQU 1
EXTI_PR1_PR1 EQU 0x00000002 ; Pending bit 1
EXTI_PR1_PR1_ofs EQU 1
EXTI_PR1_PR1_len EQU 1
EXTI_PR1_PR2 EQU 0x00000004 ; Pending bit 2
EXTI_PR1_PR2_ofs EQU 2
EXTI_PR1_PR2_len EQU 1
EXTI_PR1_PR3 EQU 0x00000008 ; Pending bit 3
EXTI_PR1_PR3_ofs EQU 3
EXTI_PR1_PR3_len EQU 1
EXTI_PR1_PR4 EQU 0x00000010 ; Pending bit 4
EXTI_PR1_PR4_ofs EQU 4
EXTI_PR1_PR4_len EQU 1
EXTI_PR1_PR5 EQU 0x00000020 ; Pending bit 5
EXTI_PR1_PR5_ofs EQU 5
EXTI_PR1_PR5_len EQU 1
EXTI_PR1_PR6 EQU 0x00000040 ; Pending bit 6
EXTI_PR1_PR6_ofs EQU 6
EXTI_PR1_PR6_len EQU 1
EXTI_PR1_PR7 EQU 0x00000080 ; Pending bit 7
EXTI_PR1_PR7_ofs EQU 7
EXTI_PR1_PR7_len EQU 1
EXTI_PR1_PR8 EQU 0x00000100 ; Pending bit 8
EXTI_PR1_PR8_ofs EQU 8
EXTI_PR1_PR8_len EQU 1
EXTI_PR1_PR9 EQU 0x00000200 ; Pending bit 9
EXTI_PR1_PR9_ofs EQU 9
EXTI_PR1_PR9_len EQU 1
EXTI_PR1_PR10 EQU 0x00000400 ; Pending bit 10
EXTI_PR1_PR10_ofs EQU 10
EXTI_PR1_PR10_len EQU 1
EXTI_PR1_PR11 EQU 0x00000800 ; Pending bit 11
EXTI_PR1_PR11_ofs EQU 11
EXTI_PR1_PR11_len EQU 1
EXTI_PR1_PR12 EQU 0x00001000 ; Pending bit 12
EXTI_PR1_PR12_ofs EQU 12
EXTI_PR1_PR12_len EQU 1
EXTI_PR1_PR13 EQU 0x00002000 ; Pending bit 13
EXTI_PR1_PR13_ofs EQU 13
EXTI_PR1_PR13_len EQU 1
EXTI_PR1_PR14 EQU 0x00004000 ; Pending bit 14
EXTI_PR1_PR14_ofs EQU 14
EXTI_PR1_PR14_len EQU 1
EXTI_PR1_PR15 EQU 0x00008000 ; Pending bit 15
EXTI_PR1_PR15_ofs EQU 15
EXTI_PR1_PR15_len EQU 1
EXTI_PR1_PR16 EQU 0x00010000 ; Pending bit 16
EXTI_PR1_PR16_ofs EQU 16
EXTI_PR1_PR16_len EQU 1
EXTI_PR1_PR17 EQU 0x00020000 ; Pending bit 17
EXTI_PR1_PR17_ofs EQU 17
EXTI_PR1_PR17_len EQU 1
EXTI_PR1_PR18 EQU 0x00040000 ; Pending bit 18
EXTI_PR1_PR18_ofs EQU 18
EXTI_PR1_PR18_len EQU 1
EXTI_PR1_PR19 EQU 0x00080000 ; Pending bit 19
EXTI_PR1_PR19_ofs EQU 19
EXTI_PR1_PR19_len EQU 1
EXTI_PR1_PR20 EQU 0x00100000 ; Pending bit 20
EXTI_PR1_PR20_ofs EQU 20
EXTI_PR1_PR20_len EQU 1
EXTI_PR1_PR21 EQU 0x00200000 ; Pending bit 21
EXTI_PR1_PR21_ofs EQU 21
EXTI_PR1_PR21_len EQU 1
EXTI_PR1_PR22 EQU 0x00400000 ; Pending bit 22
EXTI_PR1_PR22_ofs EQU 22
EXTI_PR1_PR22_len EQU 1
EXTI_PR1_PR29 EQU 0x20000000 ; Pending bit 29
EXTI_PR1_PR29_ofs EQU 29
EXTI_PR1_PR29_len EQU 1
EXTI_PR1_PR30 EQU 0x40000000 ; Pending bit 30
EXTI_PR1_PR30_ofs EQU 30
EXTI_PR1_PR30_len EQU 1
EXTI_PR1_PR31 EQU 0x80000000 ; Pending bit 31
EXTI_PR1_PR31_ofs EQU 31
EXTI_PR1_PR31_len EQU 1
; EXTI_IMR2 fields:
EXTI_IMR2_MR32 EQU 0x00000001 ; Interrupt Mask on external/internal line 32
EXTI_IMR2_MR32_ofs EQU 0
EXTI_IMR2_MR32_len EQU 1
EXTI_IMR2_MR33 EQU 0x00000002 ; Interrupt Mask on external/internal line 33
EXTI_IMR2_MR33_ofs EQU 1
EXTI_IMR2_MR33_len EQU 1
EXTI_IMR2_MR34 EQU 0x00000004 ; Interrupt Mask on external/internal line 34
EXTI_IMR2_MR34_ofs EQU 2
EXTI_IMR2_MR34_len EQU 1
EXTI_IMR2_MR35 EQU 0x00000008 ; Interrupt Mask on external/internal line 35
EXTI_IMR2_MR35_ofs EQU 3
EXTI_IMR2_MR35_len EQU 1
; EXTI_EMR2 fields:
EXTI_EMR2_MR32 EQU 0x00000001 ; Event mask on external/internal line 32
EXTI_EMR2_MR32_ofs EQU 0
EXTI_EMR2_MR32_len EQU 1
EXTI_EMR2_MR33 EQU 0x00000002 ; Event mask on external/internal line 33
EXTI_EMR2_MR33_ofs EQU 1
EXTI_EMR2_MR33_len EQU 1
EXTI_EMR2_MR34 EQU 0x00000004 ; Event mask on external/internal line 34
EXTI_EMR2_MR34_ofs EQU 2
EXTI_EMR2_MR34_len EQU 1
EXTI_EMR2_MR35 EQU 0x00000008 ; Event mask on external/internal line 35
EXTI_EMR2_MR35_ofs EQU 3
EXTI_EMR2_MR35_len EQU 1
; EXTI_RTSR2 fields:
EXTI_RTSR2_TR32 EQU 0x00000001 ; Rising trigger event configuration bit of line 32
EXTI_RTSR2_TR32_ofs EQU 0
EXTI_RTSR2_TR32_len EQU 1
EXTI_RTSR2_TR33 EQU 0x00000002 ; Rising trigger event configuration bit of line 33
EXTI_RTSR2_TR33_ofs EQU 1
EXTI_RTSR2_TR33_len EQU 1
; EXTI_FTSR2 fields:
EXTI_FTSR2_TR32 EQU 0x00000001 ; Falling trigger event configuration bit of line 32
EXTI_FTSR2_TR32_ofs EQU 0
EXTI_FTSR2_TR32_len EQU 1
EXTI_FTSR2_TR33 EQU 0x00000002 ; Falling trigger event configuration bit of line 33
EXTI_FTSR2_TR33_ofs EQU 1
EXTI_FTSR2_TR33_len EQU 1
; EXTI_SWIER2 fields:
EXTI_SWIER2_SWIER32 EQU 0x00000001 ; Software interrupt on line 32
EXTI_SWIER2_SWIER32_ofs EQU 0
EXTI_SWIER2_SWIER32_len EQU 1
EXTI_SWIER2_SWIER33 EQU 0x00000002 ; Software interrupt on line 33
EXTI_SWIER2_SWIER33_ofs EQU 1
EXTI_SWIER2_SWIER33_len EQU 1
; EXTI_PR2 fields:
EXTI_PR2_PR32 EQU 0x00000001 ; Pending bit on line 32
EXTI_PR2_PR32_ofs EQU 0
EXTI_PR2_PR32_len EQU 1
EXTI_PR2_PR33 EQU 0x00000002 ; Pending bit on line 33
EXTI_PR2_PR33_ofs EQU 1
EXTI_PR2_PR33_len EQU 1
; ---- COMP --------------------------------------------------
; Desc: Comparator
; COMP base address:
COMP_BASE EQU 0x4001001c
; COMP registers:
COMP_COMP1_CSR EQU (COMP_BASE + 0x0) ; control and status register
COMP_COMP2_CSR EQU (COMP_BASE + 0x4) ; control and status register
COMP_COMP3_CSR EQU (COMP_BASE + 0x8) ; control and status register
COMP_COMP4_CSR EQU (COMP_BASE + 0xc) ; control and status register
COMP_COMP5_CSR EQU (COMP_BASE + 0x10) ; control and status register
COMP_COMP6_CSR EQU (COMP_BASE + 0x14) ; control and status register
COMP_COMP7_CSR EQU (COMP_BASE + 0x18) ; control and status register
; COMP_COMP1_CSR fields:
COMP_COMP1_CSR_COMP1EN EQU 0x00000001 ; Comparator 1 enable
COMP_COMP1_CSR_COMP1EN_ofs EQU 0
COMP_COMP1_CSR_COMP1EN_len EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC EQU 0x00000002 ; COMP1_INP_DAC
COMP_COMP1_CSR_COMP1_INP_DAC_ofs EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC_len EQU 1
COMP_COMP1_CSR_COMP1MODE EQU 0x0000000c ; Comparator 1 mode
COMP_COMP1_CSR_COMP1MODE_ofs EQU 2
COMP_COMP1_CSR_COMP1MODE_len EQU 2
COMP_COMP1_CSR_COMP1INSEL EQU 0x00000070 ; Comparator 1 inverting input selection
COMP_COMP1_CSR_COMP1INSEL_ofs EQU 4
COMP_COMP1_CSR_COMP1INSEL_len EQU 3
COMP_COMP1_CSR_COMP1_OUT_SEL EQU 0x00003c00 ; Comparator 1 output selection
COMP_COMP1_CSR_COMP1_OUT_SEL_ofs EQU 10
COMP_COMP1_CSR_COMP1_OUT_SEL_len EQU 4
COMP_COMP1_CSR_COMP1POL EQU 0x00008000 ; Comparator 1 output polarity
COMP_COMP1_CSR_COMP1POL_ofs EQU 15
COMP_COMP1_CSR_COMP1POL_len EQU 1
COMP_COMP1_CSR_COMP1HYST EQU 0x00030000 ; Comparator 1 hysteresis
COMP_COMP1_CSR_COMP1HYST_ofs EQU 16
COMP_COMP1_CSR_COMP1HYST_len EQU 2
COMP_COMP1_CSR_COMP1_BLANKING EQU 0x001c0000 ; Comparator 1 blanking source
COMP_COMP1_CSR_COMP1_BLANKING_ofs EQU 18
COMP_COMP1_CSR_COMP1_BLANKING_len EQU 3
COMP_COMP1_CSR_COMP1OUT EQU 0x40000000 ; Comparator 1 output
COMP_COMP1_CSR_COMP1OUT_ofs EQU 30
COMP_COMP1_CSR_COMP1OUT_len EQU 1
COMP_COMP1_CSR_COMP1LOCK EQU 0x80000000 ; Comparator 1 lock
COMP_COMP1_CSR_COMP1LOCK_ofs EQU 31
COMP_COMP1_CSR_COMP1LOCK_len EQU 1
; COMP_COMP2_CSR fields:
COMP_COMP2_CSR_COMP2EN EQU 0x00000001 ; Comparator 2 enable
COMP_COMP2_CSR_COMP2EN_ofs EQU 0
COMP_COMP2_CSR_COMP2EN_len EQU 1
COMP_COMP2_CSR_COMP2MODE EQU 0x0000000c ; Comparator 2 mode
COMP_COMP2_CSR_COMP2MODE_ofs EQU 2
COMP_COMP2_CSR_COMP2MODE_len EQU 2
COMP_COMP2_CSR_COMP2INSEL EQU 0x00000070 ; Comparator 2 inverting input selection
COMP_COMP2_CSR_COMP2INSEL_ofs EQU 4
COMP_COMP2_CSR_COMP2INSEL_len EQU 3
COMP_COMP2_CSR_COMP2INPSEL EQU 0x00000080 ; Comparator 2 non inverted input selection
COMP_COMP2_CSR_COMP2INPSEL_ofs EQU 7
COMP_COMP2_CSR_COMP2INPSEL_len EQU 1
COMP_COMP2_CSR_COMP2INMSEL EQU 0x00000200 ; Comparator 1inverting input selection
COMP_COMP2_CSR_COMP2INMSEL_ofs EQU 9
COMP_COMP2_CSR_COMP2INMSEL_len EQU 1
COMP_COMP2_CSR_COMP2_OUT_SEL EQU 0x00003c00 ; Comparator 2 output selection
COMP_COMP2_CSR_COMP2_OUT_SEL_ofs EQU 10
COMP_COMP2_CSR_COMP2_OUT_SEL_len EQU 4
COMP_COMP2_CSR_COMP2POL EQU 0x00008000 ; Comparator 2 output polarity
COMP_COMP2_CSR_COMP2POL_ofs EQU 15
COMP_COMP2_CSR_COMP2POL_len EQU 1
COMP_COMP2_CSR_COMP2HYST EQU 0x00030000 ; Comparator 2 hysteresis
COMP_COMP2_CSR_COMP2HYST_ofs EQU 16
COMP_COMP2_CSR_COMP2HYST_len EQU 2
COMP_COMP2_CSR_COMP2_BLANKING EQU 0x001c0000 ; Comparator 2 blanking source
COMP_COMP2_CSR_COMP2_BLANKING_ofs EQU 18
COMP_COMP2_CSR_COMP2_BLANKING_len EQU 3
COMP_COMP2_CSR_COMP2OUT EQU 0x40000000 ; Comparator 2 output
COMP_COMP2_CSR_COMP2OUT_ofs EQU 30
COMP_COMP2_CSR_COMP2OUT_len EQU 1
COMP_COMP2_CSR_COMP2LOCK EQU 0x80000000 ; Comparator 2 lock
COMP_COMP2_CSR_COMP2LOCK_ofs EQU 31
COMP_COMP2_CSR_COMP2LOCK_len EQU 1
; COMP_COMP3_CSR fields:
COMP_COMP3_CSR_COMP3EN EQU 0x00000001 ; Comparator 3 enable
COMP_COMP3_CSR_COMP3EN_ofs EQU 0
COMP_COMP3_CSR_COMP3EN_len EQU 1
COMP_COMP3_CSR_COMP3MODE EQU 0x0000000c ; Comparator 3 mode
COMP_COMP3_CSR_COMP3MODE_ofs EQU 2
COMP_COMP3_CSR_COMP3MODE_len EQU 2
COMP_COMP3_CSR_COMP3INSEL EQU 0x00000070 ; Comparator 3 inverting input selection
COMP_COMP3_CSR_COMP3INSEL_ofs EQU 4
COMP_COMP3_CSR_COMP3INSEL_len EQU 3
COMP_COMP3_CSR_COMP3INPSEL EQU 0x00000080 ; Comparator 3 non inverted input selection
COMP_COMP3_CSR_COMP3INPSEL_ofs EQU 7
COMP_COMP3_CSR_COMP3INPSEL_len EQU 1
COMP_COMP3_CSR_COMP3_OUT_SEL EQU 0x00003c00 ; Comparator 3 output selection
COMP_COMP3_CSR_COMP3_OUT_SEL_ofs EQU 10
COMP_COMP3_CSR_COMP3_OUT_SEL_len EQU 4
COMP_COMP3_CSR_COMP3POL EQU 0x00008000 ; Comparator 3 output polarity
COMP_COMP3_CSR_COMP3POL_ofs EQU 15
COMP_COMP3_CSR_COMP3POL_len EQU 1
COMP_COMP3_CSR_COMP3HYST EQU 0x00030000 ; Comparator 3 hysteresis
COMP_COMP3_CSR_COMP3HYST_ofs EQU 16
COMP_COMP3_CSR_COMP3HYST_len EQU 2
COMP_COMP3_CSR_COMP3_BLANKING EQU 0x001c0000 ; Comparator 3 blanking source
COMP_COMP3_CSR_COMP3_BLANKING_ofs EQU 18
COMP_COMP3_CSR_COMP3_BLANKING_len EQU 3
COMP_COMP3_CSR_COMP3OUT EQU 0x40000000 ; Comparator 3 output
COMP_COMP3_CSR_COMP3OUT_ofs EQU 30
COMP_COMP3_CSR_COMP3OUT_len EQU 1
COMP_COMP3_CSR_COMP3LOCK EQU 0x80000000 ; Comparator 3 lock
COMP_COMP3_CSR_COMP3LOCK_ofs EQU 31
COMP_COMP3_CSR_COMP3LOCK_len EQU 1
; COMP_COMP4_CSR fields:
COMP_COMP4_CSR_COMP4EN EQU 0x00000001 ; Comparator 4 enable
COMP_COMP4_CSR_COMP4EN_ofs EQU 0
COMP_COMP4_CSR_COMP4EN_len EQU 1
COMP_COMP4_CSR_COMP4MODE EQU 0x0000000c ; Comparator 4 mode
COMP_COMP4_CSR_COMP4MODE_ofs EQU 2
COMP_COMP4_CSR_COMP4MODE_len EQU 2
COMP_COMP4_CSR_COMP4INSEL EQU 0x00000070 ; Comparator 4 inverting input selection
COMP_COMP4_CSR_COMP4INSEL_ofs EQU 4
COMP_COMP4_CSR_COMP4INSEL_len EQU 3
COMP_COMP4_CSR_COMP4INPSEL EQU 0x00000080 ; Comparator 4 non inverted input selection
COMP_COMP4_CSR_COMP4INPSEL_ofs EQU 7
COMP_COMP4_CSR_COMP4INPSEL_len EQU 1
COMP_COMP4_CSR_COM4WINMODE EQU 0x00000200 ; Comparator 4 window mode
COMP_COMP4_CSR_COM4WINMODE_ofs EQU 9
COMP_COMP4_CSR_COM4WINMODE_len EQU 1
COMP_COMP4_CSR_COMP4_OUT_SEL EQU 0x00003c00 ; Comparator 4 output selection
COMP_COMP4_CSR_COMP4_OUT_SEL_ofs EQU 10
COMP_COMP4_CSR_COMP4_OUT_SEL_len EQU 4
COMP_COMP4_CSR_COMP4POL EQU 0x00008000 ; Comparator 4 output polarity
COMP_COMP4_CSR_COMP4POL_ofs EQU 15
COMP_COMP4_CSR_COMP4POL_len EQU 1
COMP_COMP4_CSR_COMP4HYST EQU 0x00030000 ; Comparator 4 hysteresis
COMP_COMP4_CSR_COMP4HYST_ofs EQU 16
COMP_COMP4_CSR_COMP4HYST_len EQU 2
COMP_COMP4_CSR_COMP4_BLANKING EQU 0x001c0000 ; Comparator 4 blanking source
COMP_COMP4_CSR_COMP4_BLANKING_ofs EQU 18
COMP_COMP4_CSR_COMP4_BLANKING_len EQU 3
COMP_COMP4_CSR_COMP4OUT EQU 0x40000000 ; Comparator 4 output
COMP_COMP4_CSR_COMP4OUT_ofs EQU 30
COMP_COMP4_CSR_COMP4OUT_len EQU 1
COMP_COMP4_CSR_COMP4LOCK EQU 0x80000000 ; Comparator 4 lock
COMP_COMP4_CSR_COMP4LOCK_ofs EQU 31
COMP_COMP4_CSR_COMP4LOCK_len EQU 1
; COMP_COMP5_CSR fields:
COMP_COMP5_CSR_COMP5EN EQU 0x00000001 ; Comparator 5 enable
COMP_COMP5_CSR_COMP5EN_ofs EQU 0
COMP_COMP5_CSR_COMP5EN_len EQU 1
COMP_COMP5_CSR_COMP5MODE EQU 0x0000000c ; Comparator 5 mode
COMP_COMP5_CSR_COMP5MODE_ofs EQU 2
COMP_COMP5_CSR_COMP5MODE_len EQU 2
COMP_COMP5_CSR_COMP5INSEL EQU 0x00000070 ; Comparator 5 inverting input selection
COMP_COMP5_CSR_COMP5INSEL_ofs EQU 4
COMP_COMP5_CSR_COMP5INSEL_len EQU 3
COMP_COMP5_CSR_COMP5INPSEL EQU 0x00000080 ; Comparator 5 non inverted input selection
COMP_COMP5_CSR_COMP5INPSEL_ofs EQU 7
COMP_COMP5_CSR_COMP5INPSEL_len EQU 1
COMP_COMP5_CSR_COMP5_OUT_SEL EQU 0x00003c00 ; Comparator 5 output selection
COMP_COMP5_CSR_COMP5_OUT_SEL_ofs EQU 10
COMP_COMP5_CSR_COMP5_OUT_SEL_len EQU 4
COMP_COMP5_CSR_COMP5POL EQU 0x00008000 ; Comparator 5 output polarity
COMP_COMP5_CSR_COMP5POL_ofs EQU 15
COMP_COMP5_CSR_COMP5POL_len EQU 1
COMP_COMP5_CSR_COMP5HYST EQU 0x00030000 ; Comparator 5 hysteresis
COMP_COMP5_CSR_COMP5HYST_ofs EQU 16
COMP_COMP5_CSR_COMP5HYST_len EQU 2
COMP_COMP5_CSR_COMP5_BLANKING EQU 0x001c0000 ; Comparator 5 blanking source
COMP_COMP5_CSR_COMP5_BLANKING_ofs EQU 18
COMP_COMP5_CSR_COMP5_BLANKING_len EQU 3
COMP_COMP5_CSR_COMP5OUT EQU 0x40000000 ; Comparator51 output
COMP_COMP5_CSR_COMP5OUT_ofs EQU 30
COMP_COMP5_CSR_COMP5OUT_len EQU 1
COMP_COMP5_CSR_COMP5LOCK EQU 0x80000000 ; Comparator 5 lock
COMP_COMP5_CSR_COMP5LOCK_ofs EQU 31
COMP_COMP5_CSR_COMP5LOCK_len EQU 1
; COMP_COMP6_CSR fields:
COMP_COMP6_CSR_COMP6EN EQU 0x00000001 ; Comparator 6 enable
COMP_COMP6_CSR_COMP6EN_ofs EQU 0
COMP_COMP6_CSR_COMP6EN_len EQU 1
COMP_COMP6_CSR_COMP6MODE EQU 0x0000000c ; Comparator 6 mode
COMP_COMP6_CSR_COMP6MODE_ofs EQU 2
COMP_COMP6_CSR_COMP6MODE_len EQU 2
COMP_COMP6_CSR_COMP6INSEL EQU 0x00000070 ; Comparator 6 inverting input selection
COMP_COMP6_CSR_COMP6INSEL_ofs EQU 4
COMP_COMP6_CSR_COMP6INSEL_len EQU 3
COMP_COMP6_CSR_COMP6INPSEL EQU 0x00000080 ; Comparator 6 non inverted input selection
COMP_COMP6_CSR_COMP6INPSEL_ofs EQU 7
COMP_COMP6_CSR_COMP6INPSEL_len EQU 1
COMP_COMP6_CSR_COM6WINMODE EQU 0x00000200 ; Comparator 6 window mode
COMP_COMP6_CSR_COM6WINMODE_ofs EQU 9
COMP_COMP6_CSR_COM6WINMODE_len EQU 1
COMP_COMP6_CSR_COMP6_OUT_SEL EQU 0x00003c00 ; Comparator 6 output selection
COMP_COMP6_CSR_COMP6_OUT_SEL_ofs EQU 10
COMP_COMP6_CSR_COMP6_OUT_SEL_len EQU 4
COMP_COMP6_CSR_COMP6POL EQU 0x00008000 ; Comparator 6 output polarity
COMP_COMP6_CSR_COMP6POL_ofs EQU 15
COMP_COMP6_CSR_COMP6POL_len EQU 1
COMP_COMP6_CSR_COMP6HYST EQU 0x00030000 ; Comparator 6 hysteresis
COMP_COMP6_CSR_COMP6HYST_ofs EQU 16
COMP_COMP6_CSR_COMP6HYST_len EQU 2
COMP_COMP6_CSR_COMP6_BLANKING EQU 0x001c0000 ; Comparator 6 blanking source
COMP_COMP6_CSR_COMP6_BLANKING_ofs EQU 18
COMP_COMP6_CSR_COMP6_BLANKING_len EQU 3
COMP_COMP6_CSR_COMP6OUT EQU 0x40000000 ; Comparator 6 output
COMP_COMP6_CSR_COMP6OUT_ofs EQU 30
COMP_COMP6_CSR_COMP6OUT_len EQU 1
COMP_COMP6_CSR_COMP6LOCK EQU 0x80000000 ; Comparator 6 lock
COMP_COMP6_CSR_COMP6LOCK_ofs EQU 31
COMP_COMP6_CSR_COMP6LOCK_len EQU 1
; COMP_COMP7_CSR fields:
COMP_COMP7_CSR_COMP7EN EQU 0x00000001 ; Comparator 7 enable
COMP_COMP7_CSR_COMP7EN_ofs EQU 0
COMP_COMP7_CSR_COMP7EN_len EQU 1
COMP_COMP7_CSR_COMP7MODE EQU 0x0000000c ; Comparator 7 mode
COMP_COMP7_CSR_COMP7MODE_ofs EQU 2
COMP_COMP7_CSR_COMP7MODE_len EQU 2
COMP_COMP7_CSR_COMP7INSEL EQU 0x00000070 ; Comparator 7 inverting input selection
COMP_COMP7_CSR_COMP7INSEL_ofs EQU 4
COMP_COMP7_CSR_COMP7INSEL_len EQU 3
COMP_COMP7_CSR_COMP7INPSEL EQU 0x00000080 ; Comparator 7 non inverted input selection
COMP_COMP7_CSR_COMP7INPSEL_ofs EQU 7
COMP_COMP7_CSR_COMP7INPSEL_len EQU 1
COMP_COMP7_CSR_COMP7_OUT_SEL EQU 0x00003c00 ; Comparator 7 output selection
COMP_COMP7_CSR_COMP7_OUT_SEL_ofs EQU 10
COMP_COMP7_CSR_COMP7_OUT_SEL_len EQU 4
COMP_COMP7_CSR_COMP7POL EQU 0x00008000 ; Comparator 7 output polarity
COMP_COMP7_CSR_COMP7POL_ofs EQU 15
COMP_COMP7_CSR_COMP7POL_len EQU 1
COMP_COMP7_CSR_COMP7HYST EQU 0x00030000 ; Comparator 7 hysteresis
COMP_COMP7_CSR_COMP7HYST_ofs EQU 16
COMP_COMP7_CSR_COMP7HYST_len EQU 2
COMP_COMP7_CSR_COMP7_BLANKING EQU 0x001c0000 ; Comparator 7 blanking source
COMP_COMP7_CSR_COMP7_BLANKING_ofs EQU 18
COMP_COMP7_CSR_COMP7_BLANKING_len EQU 3
COMP_COMP7_CSR_COMP7OUT EQU 0x40000000 ; Comparator 7 output
COMP_COMP7_CSR_COMP7OUT_ofs EQU 30
COMP_COMP7_CSR_COMP7OUT_len EQU 1
COMP_COMP7_CSR_COMP7LOCK EQU 0x80000000 ; Comparator 7 lock
COMP_COMP7_CSR_COMP7LOCK_ofs EQU 31
COMP_COMP7_CSR_COMP7LOCK_len EQU 1
; ---- PWR ---------------------------------------------------
; Desc: Power control
; PWR base address:
PWR_BASE EQU 0x40007000
; PWR registers:
PWR_CR EQU (PWR_BASE + 0x0) ; power control register
PWR_CSR EQU (PWR_BASE + 0x4) ; power control/status register
; PWR_CR fields:
PWR_CR_LPDS EQU 0x00000001 ; Low-power deep sleep
PWR_CR_LPDS_ofs EQU 0
PWR_CR_LPDS_len EQU 1
PWR_CR_PDDS EQU 0x00000002 ; Power down deepsleep
PWR_CR_PDDS_ofs EQU 1
PWR_CR_PDDS_len EQU 1
PWR_CR_CWUF EQU 0x00000004 ; Clear wakeup flag
PWR_CR_CWUF_ofs EQU 2
PWR_CR_CWUF_len EQU 1
PWR_CR_CSBF EQU 0x00000008 ; Clear standby flag
PWR_CR_CSBF_ofs EQU 3
PWR_CR_CSBF_len EQU 1
PWR_CR_PVDE EQU 0x00000010 ; Power voltage detector enable
PWR_CR_PVDE_ofs EQU 4
PWR_CR_PVDE_len EQU 1
PWR_CR_PLS EQU 0x000000e0 ; PVD level selection
PWR_CR_PLS_ofs EQU 5
PWR_CR_PLS_len EQU 3
PWR_CR_DBP EQU 0x00000100 ; Disable backup domain write protection
PWR_CR_DBP_ofs EQU 8
PWR_CR_DBP_len EQU 1
; PWR_CSR fields:
PWR_CSR_WUF EQU 0x00000001 ; Wakeup flag
PWR_CSR_WUF_ofs EQU 0
PWR_CSR_WUF_len EQU 1
PWR_CSR_SBF EQU 0x00000002 ; Standby flag
PWR_CSR_SBF_ofs EQU 1
PWR_CSR_SBF_len EQU 1
PWR_CSR_PVDO EQU 0x00000004 ; PVD output
PWR_CSR_PVDO_ofs EQU 2
PWR_CSR_PVDO_len EQU 1
PWR_CSR_EWUP1 EQU 0x00000100 ; Enable WKUP1 pin
PWR_CSR_EWUP1_ofs EQU 8
PWR_CSR_EWUP1_len EQU 1
PWR_CSR_EWUP2 EQU 0x00000200 ; Enable WKUP2 pin
PWR_CSR_EWUP2_ofs EQU 9
PWR_CSR_EWUP2_len EQU 1
; ---- CAN ---------------------------------------------------
; Desc: Controller area network
; CAN base address:
CAN_BASE EQU 0x40006400
; CAN registers:
CAN_MCR EQU (CAN_BASE + 0x0) ; master control register
CAN_MSR EQU (CAN_BASE + 0x4) ; master status register
CAN_TSR EQU (CAN_BASE + 0x8) ; transmit status register
CAN_RF0R EQU (CAN_BASE + 0xc) ; receive FIFO 0 register
CAN_RF1R EQU (CAN_BASE + 0x10) ; receive FIFO 1 register
CAN_IER EQU (CAN_BASE + 0x14) ; interrupt enable register
CAN_ESR EQU (CAN_BASE + 0x18) ; error status register
CAN_BTR EQU (CAN_BASE + 0x1c) ; bit timing register
CAN_TI0R EQU (CAN_BASE + 0x180) ; TX mailbox identifier register
CAN_TDT0R EQU (CAN_BASE + 0x184) ; mailbox data length control and time stamp register
CAN_TDL0R EQU (CAN_BASE + 0x188) ; mailbox data low register
CAN_TDH0R EQU (CAN_BASE + 0x18c) ; mailbox data high register
CAN_TI1R EQU (CAN_BASE + 0x190) ; TX mailbox identifier register
CAN_TDT1R EQU (CAN_BASE + 0x194) ; mailbox data length control and time stamp register
CAN_TDL1R EQU (CAN_BASE + 0x198) ; mailbox data low register
CAN_TDH1R EQU (CAN_BASE + 0x19c) ; mailbox data high register
CAN_TI2R EQU (CAN_BASE + 0x1a0) ; TX mailbox identifier register
CAN_TDT2R EQU (CAN_BASE + 0x1a4) ; mailbox data length control and time stamp register
CAN_TDL2R EQU (CAN_BASE + 0x1a8) ; mailbox data low register
CAN_TDH2R EQU (CAN_BASE + 0x1ac) ; mailbox data high register
CAN_RI0R EQU (CAN_BASE + 0x1b0) ; receive FIFO mailbox identifier register
CAN_RDT0R EQU (CAN_BASE + 0x1b4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL0R EQU (CAN_BASE + 0x1b8) ; receive FIFO mailbox data low register
CAN_RDH0R EQU (CAN_BASE + 0x1bc) ; receive FIFO mailbox data high register
CAN_RI1R EQU (CAN_BASE + 0x1c0) ; receive FIFO mailbox identifier register
CAN_RDT1R EQU (CAN_BASE + 0x1c4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL1R EQU (CAN_BASE + 0x1c8) ; receive FIFO mailbox data low register
CAN_RDH1R EQU (CAN_BASE + 0x1cc) ; receive FIFO mailbox data high register
CAN_FMR EQU (CAN_BASE + 0x200) ; filter master register
CAN_FM1R EQU (CAN_BASE + 0x204) ; filter mode register
CAN_FS1R EQU (CAN_BASE + 0x20c) ; filter scale register
CAN_FFA1R EQU (CAN_BASE + 0x214) ; filter FIFO assignment register
CAN_FA1R EQU (CAN_BASE + 0x21c) ; CAN filter activation register
CAN_F0R1 EQU (CAN_BASE + 0x240) ; Filter bank 0 register 1
CAN_F0R2 EQU (CAN_BASE + 0x244) ; Filter bank 0 register 2
CAN_F1R1 EQU (CAN_BASE + 0x248) ; Filter bank 1 register 1
CAN_F1R2 EQU (CAN_BASE + 0x24c) ; Filter bank 1 register 2
CAN_F2R1 EQU (CAN_BASE + 0x250) ; Filter bank 2 register 1
CAN_F2R2 EQU (CAN_BASE + 0x254) ; Filter bank 2 register 2
CAN_F3R1 EQU (CAN_BASE + 0x258) ; Filter bank 3 register 1
CAN_F3R2 EQU (CAN_BASE + 0x25c) ; Filter bank 3 register 2
CAN_F4R1 EQU (CAN_BASE + 0x260) ; Filter bank 4 register 1
CAN_F4R2 EQU (CAN_BASE + 0x264) ; Filter bank 4 register 2
CAN_F5R1 EQU (CAN_BASE + 0x268) ; Filter bank 5 register 1
CAN_F5R2 EQU (CAN_BASE + 0x26c) ; Filter bank 5 register 2
CAN_F6R1 EQU (CAN_BASE + 0x270) ; Filter bank 6 register 1
CAN_F6R2 EQU (CAN_BASE + 0x274) ; Filter bank 6 register 2
CAN_F7R1 EQU (CAN_BASE + 0x278) ; Filter bank 7 register 1
CAN_F7R2 EQU (CAN_BASE + 0x27c) ; Filter bank 7 register 2
CAN_F8R1 EQU (CAN_BASE + 0x280) ; Filter bank 8 register 1
CAN_F8R2 EQU (CAN_BASE + 0x284) ; Filter bank 8 register 2
CAN_F9R1 EQU (CAN_BASE + 0x288) ; Filter bank 9 register 1
CAN_F9R2 EQU (CAN_BASE + 0x28c) ; Filter bank 9 register 2
CAN_F10R1 EQU (CAN_BASE + 0x290) ; Filter bank 10 register 1
CAN_F10R2 EQU (CAN_BASE + 0x294) ; Filter bank 10 register 2
CAN_F11R1 EQU (CAN_BASE + 0x298) ; Filter bank 11 register 1
CAN_F11R2 EQU (CAN_BASE + 0x29c) ; Filter bank 11 register 2
CAN_F12R1 EQU (CAN_BASE + 0x2a0) ; Filter bank 4 register 1
CAN_F12R2 EQU (CAN_BASE + 0x2a4) ; Filter bank 12 register 2
CAN_F13R1 EQU (CAN_BASE + 0x2a8) ; Filter bank 13 register 1
CAN_F13R2 EQU (CAN_BASE + 0x2ac) ; Filter bank 13 register 2
CAN_F14R1 EQU (CAN_BASE + 0x2b0) ; Filter bank 14 register 1
CAN_F14R2 EQU (CAN_BASE + 0x2b4) ; Filter bank 14 register 2
CAN_F15R1 EQU (CAN_BASE + 0x2b8) ; Filter bank 15 register 1
CAN_F15R2 EQU (CAN_BASE + 0x2bc) ; Filter bank 15 register 2
CAN_F16R1 EQU (CAN_BASE + 0x2c0) ; Filter bank 16 register 1
CAN_F16R2 EQU (CAN_BASE + 0x2c4) ; Filter bank 16 register 2
CAN_F17R1 EQU (CAN_BASE + 0x2c8) ; Filter bank 17 register 1
CAN_F17R2 EQU (CAN_BASE + 0x2cc) ; Filter bank 17 register 2
CAN_F18R1 EQU (CAN_BASE + 0x2d0) ; Filter bank 18 register 1
CAN_F18R2 EQU (CAN_BASE + 0x2d4) ; Filter bank 18 register 2
CAN_F19R1 EQU (CAN_BASE + 0x2d8) ; Filter bank 19 register 1
CAN_F19R2 EQU (CAN_BASE + 0x2dc) ; Filter bank 19 register 2
CAN_F20R1 EQU (CAN_BASE + 0x2e0) ; Filter bank 20 register 1
CAN_F20R2 EQU (CAN_BASE + 0x2e4) ; Filter bank 20 register 2
CAN_F21R1 EQU (CAN_BASE + 0x2e8) ; Filter bank 21 register 1
CAN_F21R2 EQU (CAN_BASE + 0x2ec) ; Filter bank 21 register 2
CAN_F22R1 EQU (CAN_BASE + 0x2f0) ; Filter bank 22 register 1
CAN_F22R2 EQU (CAN_BASE + 0x2f4) ; Filter bank 22 register 2
CAN_F23R1 EQU (CAN_BASE + 0x2f8) ; Filter bank 23 register 1
CAN_F23R2 EQU (CAN_BASE + 0x2fc) ; Filter bank 23 register 2
CAN_F24R1 EQU (CAN_BASE + 0x300) ; Filter bank 24 register 1
CAN_F24R2 EQU (CAN_BASE + 0x304) ; Filter bank 24 register 2
CAN_F25R1 EQU (CAN_BASE + 0x308) ; Filter bank 25 register 1
CAN_F25R2 EQU (CAN_BASE + 0x30c) ; Filter bank 25 register 2
CAN_F26R1 EQU (CAN_BASE + 0x310) ; Filter bank 26 register 1
CAN_F26R2 EQU (CAN_BASE + 0x314) ; Filter bank 26 register 2
CAN_F27R1 EQU (CAN_BASE + 0x318) ; Filter bank 27 register 1
CAN_F27R2 EQU (CAN_BASE + 0x31c) ; Filter bank 27 register 2
; CAN_MCR fields:
CAN_MCR_DBF EQU 0x00010000 ; DBF
CAN_MCR_DBF_ofs EQU 16
CAN_MCR_DBF_len EQU 1
CAN_MCR_RESET EQU 0x00008000 ; RESET
CAN_MCR_RESET_ofs EQU 15
CAN_MCR_RESET_len EQU 1
CAN_MCR_TTCM EQU 0x00000080 ; TTCM
CAN_MCR_TTCM_ofs EQU 7
CAN_MCR_TTCM_len EQU 1
CAN_MCR_ABOM EQU 0x00000040 ; ABOM
CAN_MCR_ABOM_ofs EQU 6
CAN_MCR_ABOM_len EQU 1
CAN_MCR_AWUM EQU 0x00000020 ; AWUM
CAN_MCR_AWUM_ofs EQU 5
CAN_MCR_AWUM_len EQU 1
CAN_MCR_NART EQU 0x00000010 ; NART
CAN_MCR_NART_ofs EQU 4
CAN_MCR_NART_len EQU 1
CAN_MCR_RFLM EQU 0x00000008 ; RFLM
CAN_MCR_RFLM_ofs EQU 3
CAN_MCR_RFLM_len EQU 1
CAN_MCR_TXFP EQU 0x00000004 ; TXFP
CAN_MCR_TXFP_ofs EQU 2
CAN_MCR_TXFP_len EQU 1
CAN_MCR_SLEEP EQU 0x00000002 ; SLEEP
CAN_MCR_SLEEP_ofs EQU 1
CAN_MCR_SLEEP_len EQU 1
CAN_MCR_INRQ EQU 0x00000001 ; INRQ
CAN_MCR_INRQ_ofs EQU 0
CAN_MCR_INRQ_len EQU 1
; CAN_MSR fields:
CAN_MSR_RX EQU 0x00000800 ; RX
CAN_MSR_RX_ofs EQU 11
CAN_MSR_RX_len EQU 1
CAN_MSR_SAMP EQU 0x00000400 ; SAMP
CAN_MSR_SAMP_ofs EQU 10
CAN_MSR_SAMP_len EQU 1
CAN_MSR_RXM EQU 0x00000200 ; RXM
CAN_MSR_RXM_ofs EQU 9
CAN_MSR_RXM_len EQU 1
CAN_MSR_TXM EQU 0x00000100 ; TXM
CAN_MSR_TXM_ofs EQU 8
CAN_MSR_TXM_len EQU 1
CAN_MSR_SLAKI EQU 0x00000010 ; SLAKI
CAN_MSR_SLAKI_ofs EQU 4
CAN_MSR_SLAKI_len EQU 1
CAN_MSR_WKUI EQU 0x00000008 ; WKUI
CAN_MSR_WKUI_ofs EQU 3
CAN_MSR_WKUI_len EQU 1
CAN_MSR_ERRI EQU 0x00000004 ; ERRI
CAN_MSR_ERRI_ofs EQU 2
CAN_MSR_ERRI_len EQU 1
CAN_MSR_SLAK EQU 0x00000002 ; SLAK
CAN_MSR_SLAK_ofs EQU 1
CAN_MSR_SLAK_len EQU 1
CAN_MSR_INAK EQU 0x00000001 ; INAK
CAN_MSR_INAK_ofs EQU 0
CAN_MSR_INAK_len EQU 1
; CAN_TSR fields:
CAN_TSR_LOW2 EQU 0x80000000 ; Lowest priority flag for mailbox 2
CAN_TSR_LOW2_ofs EQU 31
CAN_TSR_LOW2_len EQU 1
CAN_TSR_LOW1 EQU 0x40000000 ; Lowest priority flag for mailbox 1
CAN_TSR_LOW1_ofs EQU 30
CAN_TSR_LOW1_len EQU 1
CAN_TSR_LOW0 EQU 0x20000000 ; Lowest priority flag for mailbox 0
CAN_TSR_LOW0_ofs EQU 29
CAN_TSR_LOW0_len EQU 1
CAN_TSR_TME2 EQU 0x10000000 ; Lowest priority flag for mailbox 2
CAN_TSR_TME2_ofs EQU 28
CAN_TSR_TME2_len EQU 1
CAN_TSR_TME1 EQU 0x08000000 ; Lowest priority flag for mailbox 1
CAN_TSR_TME1_ofs EQU 27
CAN_TSR_TME1_len EQU 1
CAN_TSR_TME0 EQU 0x04000000 ; Lowest priority flag for mailbox 0
CAN_TSR_TME0_ofs EQU 26
CAN_TSR_TME0_len EQU 1
CAN_TSR_CODE EQU 0x03000000 ; CODE
CAN_TSR_CODE_ofs EQU 24
CAN_TSR_CODE_len EQU 2
CAN_TSR_ABRQ2 EQU 0x00800000 ; ABRQ2
CAN_TSR_ABRQ2_ofs EQU 23
CAN_TSR_ABRQ2_len EQU 1
CAN_TSR_TERR2 EQU 0x00080000 ; TERR2
CAN_TSR_TERR2_ofs EQU 19
CAN_TSR_TERR2_len EQU 1
CAN_TSR_ALST2 EQU 0x00040000 ; ALST2
CAN_TSR_ALST2_ofs EQU 18
CAN_TSR_ALST2_len EQU 1
CAN_TSR_TXOK2 EQU 0x00020000 ; TXOK2
CAN_TSR_TXOK2_ofs EQU 17
CAN_TSR_TXOK2_len EQU 1
CAN_TSR_RQCP2 EQU 0x00010000 ; RQCP2
CAN_TSR_RQCP2_ofs EQU 16
CAN_TSR_RQCP2_len EQU 1
CAN_TSR_ABRQ1 EQU 0x00008000 ; ABRQ1
CAN_TSR_ABRQ1_ofs EQU 15
CAN_TSR_ABRQ1_len EQU 1
CAN_TSR_TERR1 EQU 0x00000800 ; TERR1
CAN_TSR_TERR1_ofs EQU 11
CAN_TSR_TERR1_len EQU 1
CAN_TSR_ALST1 EQU 0x00000400 ; ALST1
CAN_TSR_ALST1_ofs EQU 10
CAN_TSR_ALST1_len EQU 1
CAN_TSR_TXOK1 EQU 0x00000200 ; TXOK1
CAN_TSR_TXOK1_ofs EQU 9
CAN_TSR_TXOK1_len EQU 1
CAN_TSR_RQCP1 EQU 0x00000100 ; RQCP1
CAN_TSR_RQCP1_ofs EQU 8
CAN_TSR_RQCP1_len EQU 1
CAN_TSR_ABRQ0 EQU 0x00000080 ; ABRQ0
CAN_TSR_ABRQ0_ofs EQU 7
CAN_TSR_ABRQ0_len EQU 1
CAN_TSR_TERR0 EQU 0x00000008 ; TERR0
CAN_TSR_TERR0_ofs EQU 3
CAN_TSR_TERR0_len EQU 1
CAN_TSR_ALST0 EQU 0x00000004 ; ALST0
CAN_TSR_ALST0_ofs EQU 2
CAN_TSR_ALST0_len EQU 1
CAN_TSR_TXOK0 EQU 0x00000002 ; TXOK0
CAN_TSR_TXOK0_ofs EQU 1
CAN_TSR_TXOK0_len EQU 1
CAN_TSR_RQCP0 EQU 0x00000001 ; RQCP0
CAN_TSR_RQCP0_ofs EQU 0
CAN_TSR_RQCP0_len EQU 1
; CAN_RF0R fields:
CAN_RF0R_RFOM0 EQU 0x00000020 ; RFOM0
CAN_RF0R_RFOM0_ofs EQU 5
CAN_RF0R_RFOM0_len EQU 1
CAN_RF0R_FOVR0 EQU 0x00000010 ; FOVR0
CAN_RF0R_FOVR0_ofs EQU 4
CAN_RF0R_FOVR0_len EQU 1
CAN_RF0R_FULL0 EQU 0x00000008 ; FULL0
CAN_RF0R_FULL0_ofs EQU 3
CAN_RF0R_FULL0_len EQU 1
CAN_RF0R_FMP0 EQU 0x00000003 ; FMP0
CAN_RF0R_FMP0_ofs EQU 0
CAN_RF0R_FMP0_len EQU 2
; CAN_RF1R fields:
CAN_RF1R_RFOM1 EQU 0x00000020 ; RFOM1
CAN_RF1R_RFOM1_ofs EQU 5
CAN_RF1R_RFOM1_len EQU 1
CAN_RF1R_FOVR1 EQU 0x00000010 ; FOVR1
CAN_RF1R_FOVR1_ofs EQU 4
CAN_RF1R_FOVR1_len EQU 1
CAN_RF1R_FULL1 EQU 0x00000008 ; FULL1
CAN_RF1R_FULL1_ofs EQU 3
CAN_RF1R_FULL1_len EQU 1
CAN_RF1R_FMP1 EQU 0x00000003 ; FMP1
CAN_RF1R_FMP1_ofs EQU 0
CAN_RF1R_FMP1_len EQU 2
; CAN_IER fields:
CAN_IER_SLKIE EQU 0x00020000 ; SLKIE
CAN_IER_SLKIE_ofs EQU 17
CAN_IER_SLKIE_len EQU 1
CAN_IER_WKUIE EQU 0x00010000 ; WKUIE
CAN_IER_WKUIE_ofs EQU 16
CAN_IER_WKUIE_len EQU 1
CAN_IER_ERRIE EQU 0x00008000 ; ERRIE
CAN_IER_ERRIE_ofs EQU 15
CAN_IER_ERRIE_len EQU 1
CAN_IER_LECIE EQU 0x00000800 ; LECIE
CAN_IER_LECIE_ofs EQU 11
CAN_IER_LECIE_len EQU 1
CAN_IER_BOFIE EQU 0x00000400 ; BOFIE
CAN_IER_BOFIE_ofs EQU 10
CAN_IER_BOFIE_len EQU 1
CAN_IER_EPVIE EQU 0x00000200 ; EPVIE
CAN_IER_EPVIE_ofs EQU 9
CAN_IER_EPVIE_len EQU 1
CAN_IER_EWGIE EQU 0x00000100 ; EWGIE
CAN_IER_EWGIE_ofs EQU 8
CAN_IER_EWGIE_len EQU 1
CAN_IER_FOVIE1 EQU 0x00000040 ; FOVIE1
CAN_IER_FOVIE1_ofs EQU 6
CAN_IER_FOVIE1_len EQU 1
CAN_IER_FFIE1 EQU 0x00000020 ; FFIE1
CAN_IER_FFIE1_ofs EQU 5
CAN_IER_FFIE1_len EQU 1
CAN_IER_FMPIE1 EQU 0x00000010 ; FMPIE1
CAN_IER_FMPIE1_ofs EQU 4
CAN_IER_FMPIE1_len EQU 1
CAN_IER_FOVIE0 EQU 0x00000008 ; FOVIE0
CAN_IER_FOVIE0_ofs EQU 3
CAN_IER_FOVIE0_len EQU 1
CAN_IER_FFIE0 EQU 0x00000004 ; FFIE0
CAN_IER_FFIE0_ofs EQU 2
CAN_IER_FFIE0_len EQU 1
CAN_IER_FMPIE0 EQU 0x00000002 ; FMPIE0
CAN_IER_FMPIE0_ofs EQU 1
CAN_IER_FMPIE0_len EQU 1
CAN_IER_TMEIE EQU 0x00000001 ; TMEIE
CAN_IER_TMEIE_ofs EQU 0
CAN_IER_TMEIE_len EQU 1
; CAN_ESR fields:
CAN_ESR_REC EQU 0xff000000 ; REC
CAN_ESR_REC_ofs EQU 24
CAN_ESR_REC_len EQU 8
CAN_ESR_TEC EQU 0x00ff0000 ; TEC
CAN_ESR_TEC_ofs EQU 16
CAN_ESR_TEC_len EQU 8
CAN_ESR_LEC EQU 0x00000070 ; LEC
CAN_ESR_LEC_ofs EQU 4
CAN_ESR_LEC_len EQU 3
CAN_ESR_BOFF EQU 0x00000004 ; BOFF
CAN_ESR_BOFF_ofs EQU 2
CAN_ESR_BOFF_len EQU 1
CAN_ESR_EPVF EQU 0x00000002 ; EPVF
CAN_ESR_EPVF_ofs EQU 1
CAN_ESR_EPVF_len EQU 1
CAN_ESR_EWGF EQU 0x00000001 ; EWGF
CAN_ESR_EWGF_ofs EQU 0
CAN_ESR_EWGF_len EQU 1
; CAN_BTR fields:
CAN_BTR_SILM EQU 0x80000000 ; SILM
CAN_BTR_SILM_ofs EQU 31
CAN_BTR_SILM_len EQU 1
CAN_BTR_LBKM EQU 0x40000000 ; LBKM
CAN_BTR_LBKM_ofs EQU 30
CAN_BTR_LBKM_len EQU 1
CAN_BTR_SJW EQU 0x03000000 ; SJW
CAN_BTR_SJW_ofs EQU 24
CAN_BTR_SJW_len EQU 2
CAN_BTR_TS2 EQU 0x00700000 ; TS2
CAN_BTR_TS2_ofs EQU 20
CAN_BTR_TS2_len EQU 3
CAN_BTR_TS1 EQU 0x000f0000 ; TS1
CAN_BTR_TS1_ofs EQU 16
CAN_BTR_TS1_len EQU 4
CAN_BTR_BRP EQU 0x000003ff ; BRP
CAN_BTR_BRP_ofs EQU 0
CAN_BTR_BRP_len EQU 10
; CAN_TI0R fields:
CAN_TI0R_STID EQU 0xffe00000 ; STID
CAN_TI0R_STID_ofs EQU 21
CAN_TI0R_STID_len EQU 11
CAN_TI0R_EXID EQU 0x001ffff8 ; EXID
CAN_TI0R_EXID_ofs EQU 3
CAN_TI0R_EXID_len EQU 18
CAN_TI0R_IDE EQU 0x00000004 ; IDE
CAN_TI0R_IDE_ofs EQU 2
CAN_TI0R_IDE_len EQU 1
CAN_TI0R_RTR EQU 0x00000002 ; RTR
CAN_TI0R_RTR_ofs EQU 1
CAN_TI0R_RTR_len EQU 1
CAN_TI0R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI0R_TXRQ_ofs EQU 0
CAN_TI0R_TXRQ_len EQU 1
; CAN_TDT0R fields:
CAN_TDT0R_TIME EQU 0xffff0000 ; TIME
CAN_TDT0R_TIME_ofs EQU 16
CAN_TDT0R_TIME_len EQU 16
CAN_TDT0R_TGT EQU 0x00000100 ; TGT
CAN_TDT0R_TGT_ofs EQU 8
CAN_TDT0R_TGT_len EQU 1
CAN_TDT0R_DLC EQU 0x0000000f ; DLC
CAN_TDT0R_DLC_ofs EQU 0
CAN_TDT0R_DLC_len EQU 4
; CAN_TDL0R fields:
CAN_TDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL0R_DATA3_ofs EQU 24
CAN_TDL0R_DATA3_len EQU 8
CAN_TDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL0R_DATA2_ofs EQU 16
CAN_TDL0R_DATA2_len EQU 8
CAN_TDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL0R_DATA1_ofs EQU 8
CAN_TDL0R_DATA1_len EQU 8
CAN_TDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL0R_DATA0_ofs EQU 0
CAN_TDL0R_DATA0_len EQU 8
; CAN_TDH0R fields:
CAN_TDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH0R_DATA7_ofs EQU 24
CAN_TDH0R_DATA7_len EQU 8
CAN_TDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH0R_DATA6_ofs EQU 16
CAN_TDH0R_DATA6_len EQU 8
CAN_TDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH0R_DATA5_ofs EQU 8
CAN_TDH0R_DATA5_len EQU 8
CAN_TDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH0R_DATA4_ofs EQU 0
CAN_TDH0R_DATA4_len EQU 8
; CAN_TI1R fields:
CAN_TI1R_STID EQU 0xffe00000 ; STID
CAN_TI1R_STID_ofs EQU 21
CAN_TI1R_STID_len EQU 11
CAN_TI1R_EXID EQU 0x001ffff8 ; EXID
CAN_TI1R_EXID_ofs EQU 3
CAN_TI1R_EXID_len EQU 18
CAN_TI1R_IDE EQU 0x00000004 ; IDE
CAN_TI1R_IDE_ofs EQU 2
CAN_TI1R_IDE_len EQU 1
CAN_TI1R_RTR EQU 0x00000002 ; RTR
CAN_TI1R_RTR_ofs EQU 1
CAN_TI1R_RTR_len EQU 1
CAN_TI1R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI1R_TXRQ_ofs EQU 0
CAN_TI1R_TXRQ_len EQU 1
; CAN_TDT1R fields:
CAN_TDT1R_TIME EQU 0xffff0000 ; TIME
CAN_TDT1R_TIME_ofs EQU 16
CAN_TDT1R_TIME_len EQU 16
CAN_TDT1R_TGT EQU 0x00000100 ; TGT
CAN_TDT1R_TGT_ofs EQU 8
CAN_TDT1R_TGT_len EQU 1
CAN_TDT1R_DLC EQU 0x0000000f ; DLC
CAN_TDT1R_DLC_ofs EQU 0
CAN_TDT1R_DLC_len EQU 4
; CAN_TDL1R fields:
CAN_TDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL1R_DATA3_ofs EQU 24
CAN_TDL1R_DATA3_len EQU 8
CAN_TDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL1R_DATA2_ofs EQU 16
CAN_TDL1R_DATA2_len EQU 8
CAN_TDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL1R_DATA1_ofs EQU 8
CAN_TDL1R_DATA1_len EQU 8
CAN_TDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL1R_DATA0_ofs EQU 0
CAN_TDL1R_DATA0_len EQU 8
; CAN_TDH1R fields:
CAN_TDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH1R_DATA7_ofs EQU 24
CAN_TDH1R_DATA7_len EQU 8
CAN_TDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH1R_DATA6_ofs EQU 16
CAN_TDH1R_DATA6_len EQU 8
CAN_TDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH1R_DATA5_ofs EQU 8
CAN_TDH1R_DATA5_len EQU 8
CAN_TDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH1R_DATA4_ofs EQU 0
CAN_TDH1R_DATA4_len EQU 8
; CAN_TI2R fields:
CAN_TI2R_STID EQU 0xffe00000 ; STID
CAN_TI2R_STID_ofs EQU 21
CAN_TI2R_STID_len EQU 11
CAN_TI2R_EXID EQU 0x001ffff8 ; EXID
CAN_TI2R_EXID_ofs EQU 3
CAN_TI2R_EXID_len EQU 18
CAN_TI2R_IDE EQU 0x00000004 ; IDE
CAN_TI2R_IDE_ofs EQU 2
CAN_TI2R_IDE_len EQU 1
CAN_TI2R_RTR EQU 0x00000002 ; RTR
CAN_TI2R_RTR_ofs EQU 1
CAN_TI2R_RTR_len EQU 1
CAN_TI2R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI2R_TXRQ_ofs EQU 0
CAN_TI2R_TXRQ_len EQU 1
; CAN_TDT2R fields:
CAN_TDT2R_TIME EQU 0xffff0000 ; TIME
CAN_TDT2R_TIME_ofs EQU 16
CAN_TDT2R_TIME_len EQU 16
CAN_TDT2R_TGT EQU 0x00000100 ; TGT
CAN_TDT2R_TGT_ofs EQU 8
CAN_TDT2R_TGT_len EQU 1
CAN_TDT2R_DLC EQU 0x0000000f ; DLC
CAN_TDT2R_DLC_ofs EQU 0
CAN_TDT2R_DLC_len EQU 4
; CAN_TDL2R fields:
CAN_TDL2R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL2R_DATA3_ofs EQU 24
CAN_TDL2R_DATA3_len EQU 8
CAN_TDL2R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL2R_DATA2_ofs EQU 16
CAN_TDL2R_DATA2_len EQU 8
CAN_TDL2R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL2R_DATA1_ofs EQU 8
CAN_TDL2R_DATA1_len EQU 8
CAN_TDL2R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL2R_DATA0_ofs EQU 0
CAN_TDL2R_DATA0_len EQU 8
; CAN_TDH2R fields:
CAN_TDH2R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH2R_DATA7_ofs EQU 24
CAN_TDH2R_DATA7_len EQU 8
CAN_TDH2R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH2R_DATA6_ofs EQU 16
CAN_TDH2R_DATA6_len EQU 8
CAN_TDH2R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH2R_DATA5_ofs EQU 8
CAN_TDH2R_DATA5_len EQU 8
CAN_TDH2R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH2R_DATA4_ofs EQU 0
CAN_TDH2R_DATA4_len EQU 8
; CAN_RI0R fields:
CAN_RI0R_STID EQU 0xffe00000 ; STID
CAN_RI0R_STID_ofs EQU 21
CAN_RI0R_STID_len EQU 11
CAN_RI0R_EXID EQU 0x001ffff8 ; EXID
CAN_RI0R_EXID_ofs EQU 3
CAN_RI0R_EXID_len EQU 18
CAN_RI0R_IDE EQU 0x00000004 ; IDE
CAN_RI0R_IDE_ofs EQU 2
CAN_RI0R_IDE_len EQU 1
CAN_RI0R_RTR EQU 0x00000002 ; RTR
CAN_RI0R_RTR_ofs EQU 1
CAN_RI0R_RTR_len EQU 1
; CAN_RDT0R fields:
CAN_RDT0R_TIME EQU 0xffff0000 ; TIME
CAN_RDT0R_TIME_ofs EQU 16
CAN_RDT0R_TIME_len EQU 16
CAN_RDT0R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT0R_FMI_ofs EQU 8
CAN_RDT0R_FMI_len EQU 8
CAN_RDT0R_DLC EQU 0x0000000f ; DLC
CAN_RDT0R_DLC_ofs EQU 0
CAN_RDT0R_DLC_len EQU 4
; CAN_RDL0R fields:
CAN_RDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL0R_DATA3_ofs EQU 24
CAN_RDL0R_DATA3_len EQU 8
CAN_RDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL0R_DATA2_ofs EQU 16
CAN_RDL0R_DATA2_len EQU 8
CAN_RDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL0R_DATA1_ofs EQU 8
CAN_RDL0R_DATA1_len EQU 8
CAN_RDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL0R_DATA0_ofs EQU 0
CAN_RDL0R_DATA0_len EQU 8
; CAN_RDH0R fields:
CAN_RDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH0R_DATA7_ofs EQU 24
CAN_RDH0R_DATA7_len EQU 8
CAN_RDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH0R_DATA6_ofs EQU 16
CAN_RDH0R_DATA6_len EQU 8
CAN_RDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH0R_DATA5_ofs EQU 8
CAN_RDH0R_DATA5_len EQU 8
CAN_RDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH0R_DATA4_ofs EQU 0
CAN_RDH0R_DATA4_len EQU 8
; CAN_RI1R fields:
CAN_RI1R_STID EQU 0xffe00000 ; STID
CAN_RI1R_STID_ofs EQU 21
CAN_RI1R_STID_len EQU 11
CAN_RI1R_EXID EQU 0x001ffff8 ; EXID
CAN_RI1R_EXID_ofs EQU 3
CAN_RI1R_EXID_len EQU 18
CAN_RI1R_IDE EQU 0x00000004 ; IDE
CAN_RI1R_IDE_ofs EQU 2
CAN_RI1R_IDE_len EQU 1
CAN_RI1R_RTR EQU 0x00000002 ; RTR
CAN_RI1R_RTR_ofs EQU 1
CAN_RI1R_RTR_len EQU 1
; CAN_RDT1R fields:
CAN_RDT1R_TIME EQU 0xffff0000 ; TIME
CAN_RDT1R_TIME_ofs EQU 16
CAN_RDT1R_TIME_len EQU 16
CAN_RDT1R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT1R_FMI_ofs EQU 8
CAN_RDT1R_FMI_len EQU 8
CAN_RDT1R_DLC EQU 0x0000000f ; DLC
CAN_RDT1R_DLC_ofs EQU 0
CAN_RDT1R_DLC_len EQU 4
; CAN_RDL1R fields:
CAN_RDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL1R_DATA3_ofs EQU 24
CAN_RDL1R_DATA3_len EQU 8
CAN_RDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL1R_DATA2_ofs EQU 16
CAN_RDL1R_DATA2_len EQU 8
CAN_RDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL1R_DATA1_ofs EQU 8
CAN_RDL1R_DATA1_len EQU 8
CAN_RDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL1R_DATA0_ofs EQU 0
CAN_RDL1R_DATA0_len EQU 8
; CAN_RDH1R fields:
CAN_RDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH1R_DATA7_ofs EQU 24
CAN_RDH1R_DATA7_len EQU 8
CAN_RDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH1R_DATA6_ofs EQU 16
CAN_RDH1R_DATA6_len EQU 8
CAN_RDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH1R_DATA5_ofs EQU 8
CAN_RDH1R_DATA5_len EQU 8
CAN_RDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH1R_DATA4_ofs EQU 0
CAN_RDH1R_DATA4_len EQU 8
; CAN_FMR fields:
CAN_FMR_CAN2SB EQU 0x00003f00 ; CAN2 start bank
CAN_FMR_CAN2SB_ofs EQU 8
CAN_FMR_CAN2SB_len EQU 6
CAN_FMR_FINIT EQU 0x00000001 ; Filter init mode
CAN_FMR_FINIT_ofs EQU 0
CAN_FMR_FINIT_len EQU 1
; CAN_FM1R fields:
CAN_FM1R_FBM0 EQU 0x00000001 ; Filter mode
CAN_FM1R_FBM0_ofs EQU 0
CAN_FM1R_FBM0_len EQU 1
CAN_FM1R_FBM1 EQU 0x00000002 ; Filter mode
CAN_FM1R_FBM1_ofs EQU 1
CAN_FM1R_FBM1_len EQU 1
CAN_FM1R_FBM2 EQU 0x00000004 ; Filter mode
CAN_FM1R_FBM2_ofs EQU 2
CAN_FM1R_FBM2_len EQU 1
CAN_FM1R_FBM3 EQU 0x00000008 ; Filter mode
CAN_FM1R_FBM3_ofs EQU 3
CAN_FM1R_FBM3_len EQU 1
CAN_FM1R_FBM4 EQU 0x00000010 ; Filter mode
CAN_FM1R_FBM4_ofs EQU 4
CAN_FM1R_FBM4_len EQU 1
CAN_FM1R_FBM5 EQU 0x00000020 ; Filter mode
CAN_FM1R_FBM5_ofs EQU 5
CAN_FM1R_FBM5_len EQU 1
CAN_FM1R_FBM6 EQU 0x00000040 ; Filter mode
CAN_FM1R_FBM6_ofs EQU 6
CAN_FM1R_FBM6_len EQU 1
CAN_FM1R_FBM7 EQU 0x00000080 ; Filter mode
CAN_FM1R_FBM7_ofs EQU 7
CAN_FM1R_FBM7_len EQU 1
CAN_FM1R_FBM8 EQU 0x00000100 ; Filter mode
CAN_FM1R_FBM8_ofs EQU 8
CAN_FM1R_FBM8_len EQU 1
CAN_FM1R_FBM9 EQU 0x00000200 ; Filter mode
CAN_FM1R_FBM9_ofs EQU 9
CAN_FM1R_FBM9_len EQU 1
CAN_FM1R_FBM10 EQU 0x00000400 ; Filter mode
CAN_FM1R_FBM10_ofs EQU 10
CAN_FM1R_FBM10_len EQU 1
CAN_FM1R_FBM11 EQU 0x00000800 ; Filter mode
CAN_FM1R_FBM11_ofs EQU 11
CAN_FM1R_FBM11_len EQU 1
CAN_FM1R_FBM12 EQU 0x00001000 ; Filter mode
CAN_FM1R_FBM12_ofs EQU 12
CAN_FM1R_FBM12_len EQU 1
CAN_FM1R_FBM13 EQU 0x00002000 ; Filter mode
CAN_FM1R_FBM13_ofs EQU 13
CAN_FM1R_FBM13_len EQU 1
CAN_FM1R_FBM14 EQU 0x00004000 ; Filter mode
CAN_FM1R_FBM14_ofs EQU 14
CAN_FM1R_FBM14_len EQU 1
CAN_FM1R_FBM15 EQU 0x00008000 ; Filter mode
CAN_FM1R_FBM15_ofs EQU 15
CAN_FM1R_FBM15_len EQU 1
CAN_FM1R_FBM16 EQU 0x00010000 ; Filter mode
CAN_FM1R_FBM16_ofs EQU 16
CAN_FM1R_FBM16_len EQU 1
CAN_FM1R_FBM17 EQU 0x00020000 ; Filter mode
CAN_FM1R_FBM17_ofs EQU 17
CAN_FM1R_FBM17_len EQU 1
CAN_FM1R_FBM18 EQU 0x00040000 ; Filter mode
CAN_FM1R_FBM18_ofs EQU 18
CAN_FM1R_FBM18_len EQU 1
CAN_FM1R_FBM19 EQU 0x00080000 ; Filter mode
CAN_FM1R_FBM19_ofs EQU 19
CAN_FM1R_FBM19_len EQU 1
CAN_FM1R_FBM20 EQU 0x00100000 ; Filter mode
CAN_FM1R_FBM20_ofs EQU 20
CAN_FM1R_FBM20_len EQU 1
CAN_FM1R_FBM21 EQU 0x00200000 ; Filter mode
CAN_FM1R_FBM21_ofs EQU 21
CAN_FM1R_FBM21_len EQU 1
CAN_FM1R_FBM22 EQU 0x00400000 ; Filter mode
CAN_FM1R_FBM22_ofs EQU 22
CAN_FM1R_FBM22_len EQU 1
CAN_FM1R_FBM23 EQU 0x00800000 ; Filter mode
CAN_FM1R_FBM23_ofs EQU 23
CAN_FM1R_FBM23_len EQU 1
CAN_FM1R_FBM24 EQU 0x01000000 ; Filter mode
CAN_FM1R_FBM24_ofs EQU 24
CAN_FM1R_FBM24_len EQU 1
CAN_FM1R_FBM25 EQU 0x02000000 ; Filter mode
CAN_FM1R_FBM25_ofs EQU 25
CAN_FM1R_FBM25_len EQU 1
CAN_FM1R_FBM26 EQU 0x04000000 ; Filter mode
CAN_FM1R_FBM26_ofs EQU 26
CAN_FM1R_FBM26_len EQU 1
CAN_FM1R_FBM27 EQU 0x08000000 ; Filter mode
CAN_FM1R_FBM27_ofs EQU 27
CAN_FM1R_FBM27_len EQU 1
; CAN_FS1R fields:
CAN_FS1R_FSC0 EQU 0x00000001 ; Filter scale configuration
CAN_FS1R_FSC0_ofs EQU 0
CAN_FS1R_FSC0_len EQU 1
CAN_FS1R_FSC1 EQU 0x00000002 ; Filter scale configuration
CAN_FS1R_FSC1_ofs EQU 1
CAN_FS1R_FSC1_len EQU 1
CAN_FS1R_FSC2 EQU 0x00000004 ; Filter scale configuration
CAN_FS1R_FSC2_ofs EQU 2
CAN_FS1R_FSC2_len EQU 1
CAN_FS1R_FSC3 EQU 0x00000008 ; Filter scale configuration
CAN_FS1R_FSC3_ofs EQU 3
CAN_FS1R_FSC3_len EQU 1
CAN_FS1R_FSC4 EQU 0x00000010 ; Filter scale configuration
CAN_FS1R_FSC4_ofs EQU 4
CAN_FS1R_FSC4_len EQU 1
CAN_FS1R_FSC5 EQU 0x00000020 ; Filter scale configuration
CAN_FS1R_FSC5_ofs EQU 5
CAN_FS1R_FSC5_len EQU 1
CAN_FS1R_FSC6 EQU 0x00000040 ; Filter scale configuration
CAN_FS1R_FSC6_ofs EQU 6
CAN_FS1R_FSC6_len EQU 1
CAN_FS1R_FSC7 EQU 0x00000080 ; Filter scale configuration
CAN_FS1R_FSC7_ofs EQU 7
CAN_FS1R_FSC7_len EQU 1
CAN_FS1R_FSC8 EQU 0x00000100 ; Filter scale configuration
CAN_FS1R_FSC8_ofs EQU 8
CAN_FS1R_FSC8_len EQU 1
CAN_FS1R_FSC9 EQU 0x00000200 ; Filter scale configuration
CAN_FS1R_FSC9_ofs EQU 9
CAN_FS1R_FSC9_len EQU 1
CAN_FS1R_FSC10 EQU 0x00000400 ; Filter scale configuration
CAN_FS1R_FSC10_ofs EQU 10
CAN_FS1R_FSC10_len EQU 1
CAN_FS1R_FSC11 EQU 0x00000800 ; Filter scale configuration
CAN_FS1R_FSC11_ofs EQU 11
CAN_FS1R_FSC11_len EQU 1
CAN_FS1R_FSC12 EQU 0x00001000 ; Filter scale configuration
CAN_FS1R_FSC12_ofs EQU 12
CAN_FS1R_FSC12_len EQU 1
CAN_FS1R_FSC13 EQU 0x00002000 ; Filter scale configuration
CAN_FS1R_FSC13_ofs EQU 13
CAN_FS1R_FSC13_len EQU 1
CAN_FS1R_FSC14 EQU 0x00004000 ; Filter scale configuration
CAN_FS1R_FSC14_ofs EQU 14
CAN_FS1R_FSC14_len EQU 1
CAN_FS1R_FSC15 EQU 0x00008000 ; Filter scale configuration
CAN_FS1R_FSC15_ofs EQU 15
CAN_FS1R_FSC15_len EQU 1
CAN_FS1R_FSC16 EQU 0x00010000 ; Filter scale configuration
CAN_FS1R_FSC16_ofs EQU 16
CAN_FS1R_FSC16_len EQU 1
CAN_FS1R_FSC17 EQU 0x00020000 ; Filter scale configuration
CAN_FS1R_FSC17_ofs EQU 17
CAN_FS1R_FSC17_len EQU 1
CAN_FS1R_FSC18 EQU 0x00040000 ; Filter scale configuration
CAN_FS1R_FSC18_ofs EQU 18
CAN_FS1R_FSC18_len EQU 1
CAN_FS1R_FSC19 EQU 0x00080000 ; Filter scale configuration
CAN_FS1R_FSC19_ofs EQU 19
CAN_FS1R_FSC19_len EQU 1
CAN_FS1R_FSC20 EQU 0x00100000 ; Filter scale configuration
CAN_FS1R_FSC20_ofs EQU 20
CAN_FS1R_FSC20_len EQU 1
CAN_FS1R_FSC21 EQU 0x00200000 ; Filter scale configuration
CAN_FS1R_FSC21_ofs EQU 21
CAN_FS1R_FSC21_len EQU 1
CAN_FS1R_FSC22 EQU 0x00400000 ; Filter scale configuration
CAN_FS1R_FSC22_ofs EQU 22
CAN_FS1R_FSC22_len EQU 1
CAN_FS1R_FSC23 EQU 0x00800000 ; Filter scale configuration
CAN_FS1R_FSC23_ofs EQU 23
CAN_FS1R_FSC23_len EQU 1
CAN_FS1R_FSC24 EQU 0x01000000 ; Filter scale configuration
CAN_FS1R_FSC24_ofs EQU 24
CAN_FS1R_FSC24_len EQU 1
CAN_FS1R_FSC25 EQU 0x02000000 ; Filter scale configuration
CAN_FS1R_FSC25_ofs EQU 25
CAN_FS1R_FSC25_len EQU 1
CAN_FS1R_FSC26 EQU 0x04000000 ; Filter scale configuration
CAN_FS1R_FSC26_ofs EQU 26
CAN_FS1R_FSC26_len EQU 1
CAN_FS1R_FSC27 EQU 0x08000000 ; Filter scale configuration
CAN_FS1R_FSC27_ofs EQU 27
CAN_FS1R_FSC27_len EQU 1
; CAN_FFA1R fields:
CAN_FFA1R_FFA0 EQU 0x00000001 ; Filter FIFO assignment for filter 0
CAN_FFA1R_FFA0_ofs EQU 0
CAN_FFA1R_FFA0_len EQU 1
CAN_FFA1R_FFA1 EQU 0x00000002 ; Filter FIFO assignment for filter 1
CAN_FFA1R_FFA1_ofs EQU 1
CAN_FFA1R_FFA1_len EQU 1
CAN_FFA1R_FFA2 EQU 0x00000004 ; Filter FIFO assignment for filter 2
CAN_FFA1R_FFA2_ofs EQU 2
CAN_FFA1R_FFA2_len EQU 1
CAN_FFA1R_FFA3 EQU 0x00000008 ; Filter FIFO assignment for filter 3
CAN_FFA1R_FFA3_ofs EQU 3
CAN_FFA1R_FFA3_len EQU 1
CAN_FFA1R_FFA4 EQU 0x00000010 ; Filter FIFO assignment for filter 4
CAN_FFA1R_FFA4_ofs EQU 4
CAN_FFA1R_FFA4_len EQU 1
CAN_FFA1R_FFA5 EQU 0x00000020 ; Filter FIFO assignment for filter 5
CAN_FFA1R_FFA5_ofs EQU 5
CAN_FFA1R_FFA5_len EQU 1
CAN_FFA1R_FFA6 EQU 0x00000040 ; Filter FIFO assignment for filter 6
CAN_FFA1R_FFA6_ofs EQU 6
CAN_FFA1R_FFA6_len EQU 1
CAN_FFA1R_FFA7 EQU 0x00000080 ; Filter FIFO assignment for filter 7
CAN_FFA1R_FFA7_ofs EQU 7
CAN_FFA1R_FFA7_len EQU 1
CAN_FFA1R_FFA8 EQU 0x00000100 ; Filter FIFO assignment for filter 8
CAN_FFA1R_FFA8_ofs EQU 8
CAN_FFA1R_FFA8_len EQU 1
CAN_FFA1R_FFA9 EQU 0x00000200 ; Filter FIFO assignment for filter 9
CAN_FFA1R_FFA9_ofs EQU 9
CAN_FFA1R_FFA9_len EQU 1
CAN_FFA1R_FFA10 EQU 0x00000400 ; Filter FIFO assignment for filter 10
CAN_FFA1R_FFA10_ofs EQU 10
CAN_FFA1R_FFA10_len EQU 1
CAN_FFA1R_FFA11 EQU 0x00000800 ; Filter FIFO assignment for filter 11
CAN_FFA1R_FFA11_ofs EQU 11
CAN_FFA1R_FFA11_len EQU 1
CAN_FFA1R_FFA12 EQU 0x00001000 ; Filter FIFO assignment for filter 12
CAN_FFA1R_FFA12_ofs EQU 12
CAN_FFA1R_FFA12_len EQU 1
CAN_FFA1R_FFA13 EQU 0x00002000 ; Filter FIFO assignment for filter 13
CAN_FFA1R_FFA13_ofs EQU 13
CAN_FFA1R_FFA13_len EQU 1
CAN_FFA1R_FFA14 EQU 0x00004000 ; Filter FIFO assignment for filter 14
CAN_FFA1R_FFA14_ofs EQU 14
CAN_FFA1R_FFA14_len EQU 1
CAN_FFA1R_FFA15 EQU 0x00008000 ; Filter FIFO assignment for filter 15
CAN_FFA1R_FFA15_ofs EQU 15
CAN_FFA1R_FFA15_len EQU 1
CAN_FFA1R_FFA16 EQU 0x00010000 ; Filter FIFO assignment for filter 16
CAN_FFA1R_FFA16_ofs EQU 16
CAN_FFA1R_FFA16_len EQU 1
CAN_FFA1R_FFA17 EQU 0x00020000 ; Filter FIFO assignment for filter 17
CAN_FFA1R_FFA17_ofs EQU 17
CAN_FFA1R_FFA17_len EQU 1
CAN_FFA1R_FFA18 EQU 0x00040000 ; Filter FIFO assignment for filter 18
CAN_FFA1R_FFA18_ofs EQU 18
CAN_FFA1R_FFA18_len EQU 1
CAN_FFA1R_FFA19 EQU 0x00080000 ; Filter FIFO assignment for filter 19
CAN_FFA1R_FFA19_ofs EQU 19
CAN_FFA1R_FFA19_len EQU 1
CAN_FFA1R_FFA20 EQU 0x00100000 ; Filter FIFO assignment for filter 20
CAN_FFA1R_FFA20_ofs EQU 20
CAN_FFA1R_FFA20_len EQU 1
CAN_FFA1R_FFA21 EQU 0x00200000 ; Filter FIFO assignment for filter 21
CAN_FFA1R_FFA21_ofs EQU 21
CAN_FFA1R_FFA21_len EQU 1
CAN_FFA1R_FFA22 EQU 0x00400000 ; Filter FIFO assignment for filter 22
CAN_FFA1R_FFA22_ofs EQU 22
CAN_FFA1R_FFA22_len EQU 1
CAN_FFA1R_FFA23 EQU 0x00800000 ; Filter FIFO assignment for filter 23
CAN_FFA1R_FFA23_ofs EQU 23
CAN_FFA1R_FFA23_len EQU 1
CAN_FFA1R_FFA24 EQU 0x01000000 ; Filter FIFO assignment for filter 24
CAN_FFA1R_FFA24_ofs EQU 24
CAN_FFA1R_FFA24_len EQU 1
CAN_FFA1R_FFA25 EQU 0x02000000 ; Filter FIFO assignment for filter 25
CAN_FFA1R_FFA25_ofs EQU 25
CAN_FFA1R_FFA25_len EQU 1
CAN_FFA1R_FFA26 EQU 0x04000000 ; Filter FIFO assignment for filter 26
CAN_FFA1R_FFA26_ofs EQU 26
CAN_FFA1R_FFA26_len EQU 1
CAN_FFA1R_FFA27 EQU 0x08000000 ; Filter FIFO assignment for filter 27
CAN_FFA1R_FFA27_ofs EQU 27
CAN_FFA1R_FFA27_len EQU 1
; CAN_FA1R fields:
CAN_FA1R_FACT0 EQU 0x00000001 ; Filter active
CAN_FA1R_FACT0_ofs EQU 0
CAN_FA1R_FACT0_len EQU 1
CAN_FA1R_FACT1 EQU 0x00000002 ; Filter active
CAN_FA1R_FACT1_ofs EQU 1
CAN_FA1R_FACT1_len EQU 1
CAN_FA1R_FACT2 EQU 0x00000004 ; Filter active
CAN_FA1R_FACT2_ofs EQU 2
CAN_FA1R_FACT2_len EQU 1
CAN_FA1R_FACT3 EQU 0x00000008 ; Filter active
CAN_FA1R_FACT3_ofs EQU 3
CAN_FA1R_FACT3_len EQU 1
CAN_FA1R_FACT4 EQU 0x00000010 ; Filter active
CAN_FA1R_FACT4_ofs EQU 4
CAN_FA1R_FACT4_len EQU 1
CAN_FA1R_FACT5 EQU 0x00000020 ; Filter active
CAN_FA1R_FACT5_ofs EQU 5
CAN_FA1R_FACT5_len EQU 1
CAN_FA1R_FACT6 EQU 0x00000040 ; Filter active
CAN_FA1R_FACT6_ofs EQU 6
CAN_FA1R_FACT6_len EQU 1
CAN_FA1R_FACT7 EQU 0x00000080 ; Filter active
CAN_FA1R_FACT7_ofs EQU 7
CAN_FA1R_FACT7_len EQU 1
CAN_FA1R_FACT8 EQU 0x00000100 ; Filter active
CAN_FA1R_FACT8_ofs EQU 8
CAN_FA1R_FACT8_len EQU 1
CAN_FA1R_FACT9 EQU 0x00000200 ; Filter active
CAN_FA1R_FACT9_ofs EQU 9
CAN_FA1R_FACT9_len EQU 1
CAN_FA1R_FACT10 EQU 0x00000400 ; Filter active
CAN_FA1R_FACT10_ofs EQU 10
CAN_FA1R_FACT10_len EQU 1
CAN_FA1R_FACT11 EQU 0x00000800 ; Filter active
CAN_FA1R_FACT11_ofs EQU 11
CAN_FA1R_FACT11_len EQU 1
CAN_FA1R_FACT12 EQU 0x00001000 ; Filter active
CAN_FA1R_FACT12_ofs EQU 12
CAN_FA1R_FACT12_len EQU 1
CAN_FA1R_FACT13 EQU 0x00002000 ; Filter active
CAN_FA1R_FACT13_ofs EQU 13
CAN_FA1R_FACT13_len EQU 1
CAN_FA1R_FACT14 EQU 0x00004000 ; Filter active
CAN_FA1R_FACT14_ofs EQU 14
CAN_FA1R_FACT14_len EQU 1
CAN_FA1R_FACT15 EQU 0x00008000 ; Filter active
CAN_FA1R_FACT15_ofs EQU 15
CAN_FA1R_FACT15_len EQU 1
CAN_FA1R_FACT16 EQU 0x00010000 ; Filter active
CAN_FA1R_FACT16_ofs EQU 16
CAN_FA1R_FACT16_len EQU 1
CAN_FA1R_FACT17 EQU 0x00020000 ; Filter active
CAN_FA1R_FACT17_ofs EQU 17
CAN_FA1R_FACT17_len EQU 1
CAN_FA1R_FACT18 EQU 0x00040000 ; Filter active
CAN_FA1R_FACT18_ofs EQU 18
CAN_FA1R_FACT18_len EQU 1
CAN_FA1R_FACT19 EQU 0x00080000 ; Filter active
CAN_FA1R_FACT19_ofs EQU 19
CAN_FA1R_FACT19_len EQU 1
CAN_FA1R_FACT20 EQU 0x00100000 ; Filter active
CAN_FA1R_FACT20_ofs EQU 20
CAN_FA1R_FACT20_len EQU 1
CAN_FA1R_FACT21 EQU 0x00200000 ; Filter active
CAN_FA1R_FACT21_ofs EQU 21
CAN_FA1R_FACT21_len EQU 1
CAN_FA1R_FACT22 EQU 0x00400000 ; Filter active
CAN_FA1R_FACT22_ofs EQU 22
CAN_FA1R_FACT22_len EQU 1
CAN_FA1R_FACT23 EQU 0x00800000 ; Filter active
CAN_FA1R_FACT23_ofs EQU 23
CAN_FA1R_FACT23_len EQU 1
CAN_FA1R_FACT24 EQU 0x01000000 ; Filter active
CAN_FA1R_FACT24_ofs EQU 24
CAN_FA1R_FACT24_len EQU 1
CAN_FA1R_FACT25 EQU 0x02000000 ; Filter active
CAN_FA1R_FACT25_ofs EQU 25
CAN_FA1R_FACT25_len EQU 1
CAN_FA1R_FACT26 EQU 0x04000000 ; Filter active
CAN_FA1R_FACT26_ofs EQU 26
CAN_FA1R_FACT26_len EQU 1
CAN_FA1R_FACT27 EQU 0x08000000 ; Filter active
CAN_FA1R_FACT27_ofs EQU 27
CAN_FA1R_FACT27_len EQU 1
; CAN_F0R1 fields:
CAN_F0R1_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R1_FB0_ofs EQU 0
CAN_F0R1_FB0_len EQU 1
CAN_F0R1_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R1_FB1_ofs EQU 1
CAN_F0R1_FB1_len EQU 1
CAN_F0R1_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R1_FB2_ofs EQU 2
CAN_F0R1_FB2_len EQU 1
CAN_F0R1_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R1_FB3_ofs EQU 3
CAN_F0R1_FB3_len EQU 1
CAN_F0R1_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R1_FB4_ofs EQU 4
CAN_F0R1_FB4_len EQU 1
CAN_F0R1_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R1_FB5_ofs EQU 5
CAN_F0R1_FB5_len EQU 1
CAN_F0R1_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R1_FB6_ofs EQU 6
CAN_F0R1_FB6_len EQU 1
CAN_F0R1_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R1_FB7_ofs EQU 7
CAN_F0R1_FB7_len EQU 1
CAN_F0R1_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R1_FB8_ofs EQU 8
CAN_F0R1_FB8_len EQU 1
CAN_F0R1_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R1_FB9_ofs EQU 9
CAN_F0R1_FB9_len EQU 1
CAN_F0R1_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R1_FB10_ofs EQU 10
CAN_F0R1_FB10_len EQU 1
CAN_F0R1_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R1_FB11_ofs EQU 11
CAN_F0R1_FB11_len EQU 1
CAN_F0R1_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R1_FB12_ofs EQU 12
CAN_F0R1_FB12_len EQU 1
CAN_F0R1_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R1_FB13_ofs EQU 13
CAN_F0R1_FB13_len EQU 1
CAN_F0R1_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R1_FB14_ofs EQU 14
CAN_F0R1_FB14_len EQU 1
CAN_F0R1_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R1_FB15_ofs EQU 15
CAN_F0R1_FB15_len EQU 1
CAN_F0R1_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R1_FB16_ofs EQU 16
CAN_F0R1_FB16_len EQU 1
CAN_F0R1_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R1_FB17_ofs EQU 17
CAN_F0R1_FB17_len EQU 1
CAN_F0R1_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R1_FB18_ofs EQU 18
CAN_F0R1_FB18_len EQU 1
CAN_F0R1_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R1_FB19_ofs EQU 19
CAN_F0R1_FB19_len EQU 1
CAN_F0R1_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R1_FB20_ofs EQU 20
CAN_F0R1_FB20_len EQU 1
CAN_F0R1_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R1_FB21_ofs EQU 21
CAN_F0R1_FB21_len EQU 1
CAN_F0R1_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R1_FB22_ofs EQU 22
CAN_F0R1_FB22_len EQU 1
CAN_F0R1_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R1_FB23_ofs EQU 23
CAN_F0R1_FB23_len EQU 1
CAN_F0R1_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R1_FB24_ofs EQU 24
CAN_F0R1_FB24_len EQU 1
CAN_F0R1_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R1_FB25_ofs EQU 25
CAN_F0R1_FB25_len EQU 1
CAN_F0R1_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R1_FB26_ofs EQU 26
CAN_F0R1_FB26_len EQU 1
CAN_F0R1_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R1_FB27_ofs EQU 27
CAN_F0R1_FB27_len EQU 1
CAN_F0R1_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R1_FB28_ofs EQU 28
CAN_F0R1_FB28_len EQU 1
CAN_F0R1_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R1_FB29_ofs EQU 29
CAN_F0R1_FB29_len EQU 1
CAN_F0R1_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R1_FB30_ofs EQU 30
CAN_F0R1_FB30_len EQU 1
CAN_F0R1_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R1_FB31_ofs EQU 31
CAN_F0R1_FB31_len EQU 1
; CAN_F0R2 fields:
CAN_F0R2_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R2_FB0_ofs EQU 0
CAN_F0R2_FB0_len EQU 1
CAN_F0R2_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R2_FB1_ofs EQU 1
CAN_F0R2_FB1_len EQU 1
CAN_F0R2_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R2_FB2_ofs EQU 2
CAN_F0R2_FB2_len EQU 1
CAN_F0R2_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R2_FB3_ofs EQU 3
CAN_F0R2_FB3_len EQU 1
CAN_F0R2_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R2_FB4_ofs EQU 4
CAN_F0R2_FB4_len EQU 1
CAN_F0R2_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R2_FB5_ofs EQU 5
CAN_F0R2_FB5_len EQU 1
CAN_F0R2_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R2_FB6_ofs EQU 6
CAN_F0R2_FB6_len EQU 1
CAN_F0R2_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R2_FB7_ofs EQU 7
CAN_F0R2_FB7_len EQU 1
CAN_F0R2_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R2_FB8_ofs EQU 8
CAN_F0R2_FB8_len EQU 1
CAN_F0R2_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R2_FB9_ofs EQU 9
CAN_F0R2_FB9_len EQU 1
CAN_F0R2_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R2_FB10_ofs EQU 10
CAN_F0R2_FB10_len EQU 1
CAN_F0R2_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R2_FB11_ofs EQU 11
CAN_F0R2_FB11_len EQU 1
CAN_F0R2_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R2_FB12_ofs EQU 12
CAN_F0R2_FB12_len EQU 1
CAN_F0R2_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R2_FB13_ofs EQU 13
CAN_F0R2_FB13_len EQU 1
CAN_F0R2_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R2_FB14_ofs EQU 14
CAN_F0R2_FB14_len EQU 1
CAN_F0R2_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R2_FB15_ofs EQU 15
CAN_F0R2_FB15_len EQU 1
CAN_F0R2_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R2_FB16_ofs EQU 16
CAN_F0R2_FB16_len EQU 1
CAN_F0R2_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R2_FB17_ofs EQU 17
CAN_F0R2_FB17_len EQU 1
CAN_F0R2_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R2_FB18_ofs EQU 18
CAN_F0R2_FB18_len EQU 1
CAN_F0R2_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R2_FB19_ofs EQU 19
CAN_F0R2_FB19_len EQU 1
CAN_F0R2_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R2_FB20_ofs EQU 20
CAN_F0R2_FB20_len EQU 1
CAN_F0R2_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R2_FB21_ofs EQU 21
CAN_F0R2_FB21_len EQU 1
CAN_F0R2_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R2_FB22_ofs EQU 22
CAN_F0R2_FB22_len EQU 1
CAN_F0R2_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R2_FB23_ofs EQU 23
CAN_F0R2_FB23_len EQU 1
CAN_F0R2_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R2_FB24_ofs EQU 24
CAN_F0R2_FB24_len EQU 1
CAN_F0R2_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R2_FB25_ofs EQU 25
CAN_F0R2_FB25_len EQU 1
CAN_F0R2_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R2_FB26_ofs EQU 26
CAN_F0R2_FB26_len EQU 1
CAN_F0R2_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R2_FB27_ofs EQU 27
CAN_F0R2_FB27_len EQU 1
CAN_F0R2_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R2_FB28_ofs EQU 28
CAN_F0R2_FB28_len EQU 1
CAN_F0R2_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R2_FB29_ofs EQU 29
CAN_F0R2_FB29_len EQU 1
CAN_F0R2_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R2_FB30_ofs EQU 30
CAN_F0R2_FB30_len EQU 1
CAN_F0R2_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R2_FB31_ofs EQU 31
CAN_F0R2_FB31_len EQU 1
; CAN_F1R1 fields:
CAN_FiRx_FB0 EQU 0x00000001 ; Filter bits
CAN_FiRx_FB0_ofs EQU 0
CAN_FiRx_FB0_len EQU 1
CAN_FiRx_FB1 EQU 0x00000002 ; Filter bits
CAN_FiRx_FB1_ofs EQU 1
CAN_FiRx_FB1_len EQU 1
CAN_FiRx_FB2 EQU 0x00000004 ; Filter bits
CAN_FiRx_FB2_ofs EQU 2
CAN_FiRx_FB2_len EQU 1
CAN_FiRx_FB3 EQU 0x00000008 ; Filter bits
CAN_FiRx_FB3_ofs EQU 3
CAN_FiRx_FB3_len EQU 1
CAN_FiRx_FB4 EQU 0x00000010 ; Filter bits
CAN_FiRx_FB4_ofs EQU 4
CAN_FiRx_FB4_len EQU 1
CAN_FiRx_FB5 EQU 0x00000020 ; Filter bits
CAN_FiRx_FB5_ofs EQU 5
CAN_FiRx_FB5_len EQU 1
CAN_FiRx_FB6 EQU 0x00000040 ; Filter bits
CAN_FiRx_FB6_ofs EQU 6
CAN_FiRx_FB6_len EQU 1
CAN_FiRx_FB7 EQU 0x00000080 ; Filter bits
CAN_FiRx_FB7_ofs EQU 7
CAN_FiRx_FB7_len EQU 1
CAN_FiRx_FB8 EQU 0x00000100 ; Filter bits
CAN_FiRx_FB8_ofs EQU 8
CAN_FiRx_FB8_len EQU 1
CAN_FiRx_FB9 EQU 0x00000200 ; Filter bits
CAN_FiRx_FB9_ofs EQU 9
CAN_FiRx_FB9_len EQU 1
CAN_FiRx_FB10 EQU 0x00000400 ; Filter bits
CAN_FiRx_FB10_ofs EQU 10
CAN_FiRx_FB10_len EQU 1
CAN_FiRx_FB11 EQU 0x00000800 ; Filter bits
CAN_FiRx_FB11_ofs EQU 11
CAN_FiRx_FB11_len EQU 1
CAN_FiRx_FB12 EQU 0x00001000 ; Filter bits
CAN_FiRx_FB12_ofs EQU 12
CAN_FiRx_FB12_len EQU 1
CAN_FiRx_FB13 EQU 0x00002000 ; Filter bits
CAN_FiRx_FB13_ofs EQU 13
CAN_FiRx_FB13_len EQU 1
CAN_FiRx_FB14 EQU 0x00004000 ; Filter bits
CAN_FiRx_FB14_ofs EQU 14
CAN_FiRx_FB14_len EQU 1
CAN_FiRx_FB15 EQU 0x00008000 ; Filter bits
CAN_FiRx_FB15_ofs EQU 15
CAN_FiRx_FB15_len EQU 1
CAN_FiRx_FB16 EQU 0x00010000 ; Filter bits
CAN_FiRx_FB16_ofs EQU 16
CAN_FiRx_FB16_len EQU 1
CAN_FiRx_FB17 EQU 0x00020000 ; Filter bits
CAN_FiRx_FB17_ofs EQU 17
CAN_FiRx_FB17_len EQU 1
CAN_FiRx_FB18 EQU 0x00040000 ; Filter bits
CAN_FiRx_FB18_ofs EQU 18
CAN_FiRx_FB18_len EQU 1
CAN_FiRx_FB19 EQU 0x00080000 ; Filter bits
CAN_FiRx_FB19_ofs EQU 19
CAN_FiRx_FB19_len EQU 1
CAN_FiRx_FB20 EQU 0x00100000 ; Filter bits
CAN_FiRx_FB20_ofs EQU 20
CAN_FiRx_FB20_len EQU 1
CAN_FiRx_FB21 EQU 0x00200000 ; Filter bits
CAN_FiRx_FB21_ofs EQU 21
CAN_FiRx_FB21_len EQU 1
CAN_FiRx_FB22 EQU 0x00400000 ; Filter bits
CAN_FiRx_FB22_ofs EQU 22
CAN_FiRx_FB22_len EQU 1
CAN_FiRx_FB23 EQU 0x00800000 ; Filter bits
CAN_FiRx_FB23_ofs EQU 23
CAN_FiRx_FB23_len EQU 1
CAN_FiRx_FB24 EQU 0x01000000 ; Filter bits
CAN_FiRx_FB24_ofs EQU 24
CAN_FiRx_FB24_len EQU 1
CAN_FiRx_FB25 EQU 0x02000000 ; Filter bits
CAN_FiRx_FB25_ofs EQU 25
CAN_FiRx_FB25_len EQU 1
CAN_FiRx_FB26 EQU 0x04000000 ; Filter bits
CAN_FiRx_FB26_ofs EQU 26
CAN_FiRx_FB26_len EQU 1
CAN_FiRx_FB27 EQU 0x08000000 ; Filter bits
CAN_FiRx_FB27_ofs EQU 27
CAN_FiRx_FB27_len EQU 1
CAN_FiRx_FB28 EQU 0x10000000 ; Filter bits
CAN_FiRx_FB28_ofs EQU 28
CAN_FiRx_FB28_len EQU 1
CAN_FiRx_FB29 EQU 0x20000000 ; Filter bits
CAN_FiRx_FB29_ofs EQU 29
CAN_FiRx_FB29_len EQU 1
CAN_FiRx_FB30 EQU 0x40000000 ; Filter bits
CAN_FiRx_FB30_ofs EQU 30
CAN_FiRx_FB30_len EQU 1
CAN_FiRx_FB31 EQU 0x80000000 ; Filter bits
CAN_FiRx_FB31_ofs EQU 31
CAN_FiRx_FB31_len EQU 1
; ---- USB_FS ------------------------------------------------
; Desc: Universal serial bus full-speed device interface
; USB_FS base address:
USB_FS_BASE EQU 0x40005c00
; USB_FS registers:
USB_FS_USB_EP0R EQU (USB_FS_BASE + 0x0) ; endpoint 0 register
USB_FS_USB_EP1R EQU (USB_FS_BASE + 0x4) ; endpoint 1 register
USB_FS_USB_EP2R EQU (USB_FS_BASE + 0x8) ; endpoint 2 register
USB_FS_USB_EP3R EQU (USB_FS_BASE + 0xc) ; endpoint 3 register
USB_FS_USB_EP4R EQU (USB_FS_BASE + 0x10) ; endpoint 4 register
USB_FS_USB_EP5R EQU (USB_FS_BASE + 0x14) ; endpoint 5 register
USB_FS_USB_EP6R EQU (USB_FS_BASE + 0x18) ; endpoint 6 register
USB_FS_USB_EP7R EQU (USB_FS_BASE + 0x1c) ; endpoint 7 register
USB_FS_USB_CNTR EQU (USB_FS_BASE + 0x40) ; control register
USB_FS_ISTR EQU (USB_FS_BASE + 0x44) ; interrupt status register
USB_FS_FNR EQU (USB_FS_BASE + 0x48) ; frame number register
USB_FS_DADDR EQU (USB_FS_BASE + 0x4c) ; device address
USB_FS_BTABLE EQU (USB_FS_BASE + 0x50) ; Buffer table address
; USB_FS_USB_EP0R fields:
USB_FS_USB_EP0R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP0R_EA_ofs EQU 0
USB_FS_USB_EP0R_EA_len EQU 4
USB_FS_USB_EP0R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP0R_STAT_TX_ofs EQU 4
USB_FS_USB_EP0R_STAT_TX_len EQU 2
USB_FS_USB_EP0R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP0R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP0R_DTOG_TX_len EQU 1
USB_FS_USB_EP0R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP0R_CTR_TX_ofs EQU 7
USB_FS_USB_EP0R_CTR_TX_len EQU 1
USB_FS_USB_EP0R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP0R_EP_KIND_ofs EQU 8
USB_FS_USB_EP0R_EP_KIND_len EQU 1
USB_FS_USB_EP0R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP0R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP0R_EP_TYPE_len EQU 2
USB_FS_USB_EP0R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP0R_SETUP_ofs EQU 11
USB_FS_USB_EP0R_SETUP_len EQU 1
USB_FS_USB_EP0R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP0R_STAT_RX_ofs EQU 12
USB_FS_USB_EP0R_STAT_RX_len EQU 2
USB_FS_USB_EP0R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP0R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP0R_DTOG_RX_len EQU 1
USB_FS_USB_EP0R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP0R_CTR_RX_ofs EQU 15
USB_FS_USB_EP0R_CTR_RX_len EQU 1
; USB_FS_USB_EP1R fields:
USB_FS_USB_EP1R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP1R_EA_ofs EQU 0
USB_FS_USB_EP1R_EA_len EQU 4
USB_FS_USB_EP1R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP1R_STAT_TX_ofs EQU 4
USB_FS_USB_EP1R_STAT_TX_len EQU 2
USB_FS_USB_EP1R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP1R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP1R_DTOG_TX_len EQU 1
USB_FS_USB_EP1R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP1R_CTR_TX_ofs EQU 7
USB_FS_USB_EP1R_CTR_TX_len EQU 1
USB_FS_USB_EP1R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP1R_EP_KIND_ofs EQU 8
USB_FS_USB_EP1R_EP_KIND_len EQU 1
USB_FS_USB_EP1R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP1R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP1R_EP_TYPE_len EQU 2
USB_FS_USB_EP1R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP1R_SETUP_ofs EQU 11
USB_FS_USB_EP1R_SETUP_len EQU 1
USB_FS_USB_EP1R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP1R_STAT_RX_ofs EQU 12
USB_FS_USB_EP1R_STAT_RX_len EQU 2
USB_FS_USB_EP1R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP1R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP1R_DTOG_RX_len EQU 1
USB_FS_USB_EP1R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP1R_CTR_RX_ofs EQU 15
USB_FS_USB_EP1R_CTR_RX_len EQU 1
; USB_FS_USB_EP2R fields:
USB_FS_USB_EP2R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP2R_EA_ofs EQU 0
USB_FS_USB_EP2R_EA_len EQU 4
USB_FS_USB_EP2R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP2R_STAT_TX_ofs EQU 4
USB_FS_USB_EP2R_STAT_TX_len EQU 2
USB_FS_USB_EP2R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP2R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP2R_DTOG_TX_len EQU 1
USB_FS_USB_EP2R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP2R_CTR_TX_ofs EQU 7
USB_FS_USB_EP2R_CTR_TX_len EQU 1
USB_FS_USB_EP2R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP2R_EP_KIND_ofs EQU 8
USB_FS_USB_EP2R_EP_KIND_len EQU 1
USB_FS_USB_EP2R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP2R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP2R_EP_TYPE_len EQU 2
USB_FS_USB_EP2R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP2R_SETUP_ofs EQU 11
USB_FS_USB_EP2R_SETUP_len EQU 1
USB_FS_USB_EP2R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP2R_STAT_RX_ofs EQU 12
USB_FS_USB_EP2R_STAT_RX_len EQU 2
USB_FS_USB_EP2R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP2R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP2R_DTOG_RX_len EQU 1
USB_FS_USB_EP2R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP2R_CTR_RX_ofs EQU 15
USB_FS_USB_EP2R_CTR_RX_len EQU 1
; USB_FS_USB_EP3R fields:
USB_FS_USB_EP3R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP3R_EA_ofs EQU 0
USB_FS_USB_EP3R_EA_len EQU 4
USB_FS_USB_EP3R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP3R_STAT_TX_ofs EQU 4
USB_FS_USB_EP3R_STAT_TX_len EQU 2
USB_FS_USB_EP3R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP3R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP3R_DTOG_TX_len EQU 1
USB_FS_USB_EP3R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP3R_CTR_TX_ofs EQU 7
USB_FS_USB_EP3R_CTR_TX_len EQU 1
USB_FS_USB_EP3R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP3R_EP_KIND_ofs EQU 8
USB_FS_USB_EP3R_EP_KIND_len EQU 1
USB_FS_USB_EP3R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP3R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP3R_EP_TYPE_len EQU 2
USB_FS_USB_EP3R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP3R_SETUP_ofs EQU 11
USB_FS_USB_EP3R_SETUP_len EQU 1
USB_FS_USB_EP3R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP3R_STAT_RX_ofs EQU 12
USB_FS_USB_EP3R_STAT_RX_len EQU 2
USB_FS_USB_EP3R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP3R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP3R_DTOG_RX_len EQU 1
USB_FS_USB_EP3R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP3R_CTR_RX_ofs EQU 15
USB_FS_USB_EP3R_CTR_RX_len EQU 1
; USB_FS_USB_EP4R fields:
USB_FS_USB_EP4R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP4R_EA_ofs EQU 0
USB_FS_USB_EP4R_EA_len EQU 4
USB_FS_USB_EP4R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP4R_STAT_TX_ofs EQU 4
USB_FS_USB_EP4R_STAT_TX_len EQU 2
USB_FS_USB_EP4R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP4R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP4R_DTOG_TX_len EQU 1
USB_FS_USB_EP4R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP4R_CTR_TX_ofs EQU 7
USB_FS_USB_EP4R_CTR_TX_len EQU 1
USB_FS_USB_EP4R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP4R_EP_KIND_ofs EQU 8
USB_FS_USB_EP4R_EP_KIND_len EQU 1
USB_FS_USB_EP4R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP4R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP4R_EP_TYPE_len EQU 2
USB_FS_USB_EP4R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP4R_SETUP_ofs EQU 11
USB_FS_USB_EP4R_SETUP_len EQU 1
USB_FS_USB_EP4R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP4R_STAT_RX_ofs EQU 12
USB_FS_USB_EP4R_STAT_RX_len EQU 2
USB_FS_USB_EP4R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP4R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP4R_DTOG_RX_len EQU 1
USB_FS_USB_EP4R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP4R_CTR_RX_ofs EQU 15
USB_FS_USB_EP4R_CTR_RX_len EQU 1
; USB_FS_USB_EP5R fields:
USB_FS_USB_EP5R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP5R_EA_ofs EQU 0
USB_FS_USB_EP5R_EA_len EQU 4
USB_FS_USB_EP5R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP5R_STAT_TX_ofs EQU 4
USB_FS_USB_EP5R_STAT_TX_len EQU 2
USB_FS_USB_EP5R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP5R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP5R_DTOG_TX_len EQU 1
USB_FS_USB_EP5R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP5R_CTR_TX_ofs EQU 7
USB_FS_USB_EP5R_CTR_TX_len EQU 1
USB_FS_USB_EP5R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP5R_EP_KIND_ofs EQU 8
USB_FS_USB_EP5R_EP_KIND_len EQU 1
USB_FS_USB_EP5R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP5R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP5R_EP_TYPE_len EQU 2
USB_FS_USB_EP5R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP5R_SETUP_ofs EQU 11
USB_FS_USB_EP5R_SETUP_len EQU 1
USB_FS_USB_EP5R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP5R_STAT_RX_ofs EQU 12
USB_FS_USB_EP5R_STAT_RX_len EQU 2
USB_FS_USB_EP5R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP5R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP5R_DTOG_RX_len EQU 1
USB_FS_USB_EP5R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP5R_CTR_RX_ofs EQU 15
USB_FS_USB_EP5R_CTR_RX_len EQU 1
; USB_FS_USB_EP6R fields:
USB_FS_USB_EP6R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP6R_EA_ofs EQU 0
USB_FS_USB_EP6R_EA_len EQU 4
USB_FS_USB_EP6R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP6R_STAT_TX_ofs EQU 4
USB_FS_USB_EP6R_STAT_TX_len EQU 2
USB_FS_USB_EP6R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP6R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP6R_DTOG_TX_len EQU 1
USB_FS_USB_EP6R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP6R_CTR_TX_ofs EQU 7
USB_FS_USB_EP6R_CTR_TX_len EQU 1
USB_FS_USB_EP6R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP6R_EP_KIND_ofs EQU 8
USB_FS_USB_EP6R_EP_KIND_len EQU 1
USB_FS_USB_EP6R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP6R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP6R_EP_TYPE_len EQU 2
USB_FS_USB_EP6R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP6R_SETUP_ofs EQU 11
USB_FS_USB_EP6R_SETUP_len EQU 1
USB_FS_USB_EP6R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP6R_STAT_RX_ofs EQU 12
USB_FS_USB_EP6R_STAT_RX_len EQU 2
USB_FS_USB_EP6R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP6R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP6R_DTOG_RX_len EQU 1
USB_FS_USB_EP6R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP6R_CTR_RX_ofs EQU 15
USB_FS_USB_EP6R_CTR_RX_len EQU 1
; USB_FS_USB_EP7R fields:
USB_FS_USB_EP7R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP7R_EA_ofs EQU 0
USB_FS_USB_EP7R_EA_len EQU 4
USB_FS_USB_EP7R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP7R_STAT_TX_ofs EQU 4
USB_FS_USB_EP7R_STAT_TX_len EQU 2
USB_FS_USB_EP7R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP7R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP7R_DTOG_TX_len EQU 1
USB_FS_USB_EP7R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP7R_CTR_TX_ofs EQU 7
USB_FS_USB_EP7R_CTR_TX_len EQU 1
USB_FS_USB_EP7R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP7R_EP_KIND_ofs EQU 8
USB_FS_USB_EP7R_EP_KIND_len EQU 1
USB_FS_USB_EP7R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP7R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP7R_EP_TYPE_len EQU 2
USB_FS_USB_EP7R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP7R_SETUP_ofs EQU 11
USB_FS_USB_EP7R_SETUP_len EQU 1
USB_FS_USB_EP7R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP7R_STAT_RX_ofs EQU 12
USB_FS_USB_EP7R_STAT_RX_len EQU 2
USB_FS_USB_EP7R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP7R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP7R_DTOG_RX_len EQU 1
USB_FS_USB_EP7R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP7R_CTR_RX_ofs EQU 15
USB_FS_USB_EP7R_CTR_RX_len EQU 1
; USB_FS_USB_CNTR fields:
USB_FS_USB_CNTR_FRES EQU 0x00000001 ; Force USB Reset
USB_FS_USB_CNTR_FRES_ofs EQU 0
USB_FS_USB_CNTR_FRES_len EQU 1
USB_FS_USB_CNTR_PDWN EQU 0x00000002 ; Power down
USB_FS_USB_CNTR_PDWN_ofs EQU 1
USB_FS_USB_CNTR_PDWN_len EQU 1
USB_FS_USB_CNTR_LPMODE EQU 0x00000004 ; Low-power mode
USB_FS_USB_CNTR_LPMODE_ofs EQU 2
USB_FS_USB_CNTR_LPMODE_len EQU 1
USB_FS_USB_CNTR_FSUSP EQU 0x00000008 ; Force suspend
USB_FS_USB_CNTR_FSUSP_ofs EQU 3
USB_FS_USB_CNTR_FSUSP_len EQU 1
USB_FS_USB_CNTR_RESUME EQU 0x00000010 ; Resume request
USB_FS_USB_CNTR_RESUME_ofs EQU 4
USB_FS_USB_CNTR_RESUME_len EQU 1
USB_FS_USB_CNTR_ESOFM EQU 0x00000100 ; Expected start of frame interrupt mask
USB_FS_USB_CNTR_ESOFM_ofs EQU 8
USB_FS_USB_CNTR_ESOFM_len EQU 1
USB_FS_USB_CNTR_SOFM EQU 0x00000200 ; Start of frame interrupt mask
USB_FS_USB_CNTR_SOFM_ofs EQU 9
USB_FS_USB_CNTR_SOFM_len EQU 1
USB_FS_USB_CNTR_RESETM EQU 0x00000400 ; USB reset interrupt mask
USB_FS_USB_CNTR_RESETM_ofs EQU 10
USB_FS_USB_CNTR_RESETM_len EQU 1
USB_FS_USB_CNTR_SUSPM EQU 0x00000800 ; Suspend mode interrupt mask
USB_FS_USB_CNTR_SUSPM_ofs EQU 11
USB_FS_USB_CNTR_SUSPM_len EQU 1
USB_FS_USB_CNTR_WKUPM EQU 0x00001000 ; Wakeup interrupt mask
USB_FS_USB_CNTR_WKUPM_ofs EQU 12
USB_FS_USB_CNTR_WKUPM_len EQU 1
USB_FS_USB_CNTR_ERRM EQU 0x00002000 ; Error interrupt mask
USB_FS_USB_CNTR_ERRM_ofs EQU 13
USB_FS_USB_CNTR_ERRM_len EQU 1
USB_FS_USB_CNTR_PMAOVRM EQU 0x00004000 ; Packet memory area over / underrun interrupt mask
USB_FS_USB_CNTR_PMAOVRM_ofs EQU 14
USB_FS_USB_CNTR_PMAOVRM_len EQU 1
USB_FS_USB_CNTR_CTRM EQU 0x00008000 ; Correct transfer interrupt mask
USB_FS_USB_CNTR_CTRM_ofs EQU 15
USB_FS_USB_CNTR_CTRM_len EQU 1
; USB_FS_ISTR fields:
USB_FS_ISTR_EP_ID EQU 0x0000000f ; Endpoint Identifier
USB_FS_ISTR_EP_ID_ofs EQU 0
USB_FS_ISTR_EP_ID_len EQU 4
USB_FS_ISTR_DIR EQU 0x00000010 ; Direction of transaction
USB_FS_ISTR_DIR_ofs EQU 4
USB_FS_ISTR_DIR_len EQU 1
USB_FS_ISTR_ESOF EQU 0x00000100 ; Expected start frame
USB_FS_ISTR_ESOF_ofs EQU 8
USB_FS_ISTR_ESOF_len EQU 1
USB_FS_ISTR_SOF EQU 0x00000200 ; start of frame
USB_FS_ISTR_SOF_ofs EQU 9
USB_FS_ISTR_SOF_len EQU 1
USB_FS_ISTR_RESET EQU 0x00000400 ; reset request
USB_FS_ISTR_RESET_ofs EQU 10
USB_FS_ISTR_RESET_len EQU 1
USB_FS_ISTR_SUSP EQU 0x00000800 ; Suspend mode request
USB_FS_ISTR_SUSP_ofs EQU 11
USB_FS_ISTR_SUSP_len EQU 1
USB_FS_ISTR_WKUP EQU 0x00001000 ; Wakeup
USB_FS_ISTR_WKUP_ofs EQU 12
USB_FS_ISTR_WKUP_len EQU 1
USB_FS_ISTR_ERR EQU 0x00002000 ; Error
USB_FS_ISTR_ERR_ofs EQU 13
USB_FS_ISTR_ERR_len EQU 1
USB_FS_ISTR_PMAOVR EQU 0x00004000 ; Packet memory area over / underrun
USB_FS_ISTR_PMAOVR_ofs EQU 14
USB_FS_ISTR_PMAOVR_len EQU 1
USB_FS_ISTR_CTR EQU 0x00008000 ; Correct transfer
USB_FS_ISTR_CTR_ofs EQU 15
USB_FS_ISTR_CTR_len EQU 1
; USB_FS_FNR fields:
USB_FS_FNR_FN EQU 0x000007ff ; Frame number
USB_FS_FNR_FN_ofs EQU 0
USB_FS_FNR_FN_len EQU 11
USB_FS_FNR_LSOF EQU 0x00001800 ; Lost SOF
USB_FS_FNR_LSOF_ofs EQU 11
USB_FS_FNR_LSOF_len EQU 2
USB_FS_FNR_LCK EQU 0x00002000 ; Locked
USB_FS_FNR_LCK_ofs EQU 13
USB_FS_FNR_LCK_len EQU 1
USB_FS_FNR_RXDM EQU 0x00004000 ; Receive data - line status
USB_FS_FNR_RXDM_ofs EQU 14
USB_FS_FNR_RXDM_len EQU 1
USB_FS_FNR_RXDP EQU 0x00008000 ; Receive data + line status
USB_FS_FNR_RXDP_ofs EQU 15
USB_FS_FNR_RXDP_len EQU 1
; USB_FS_DADDR fields:
USB_FS_DADDR_ADD EQU 0x00000001 ; Device address
USB_FS_DADDR_ADD_ofs EQU 0
USB_FS_DADDR_ADD_len EQU 1
USB_FS_DADDR_ADD1 EQU 0x00000002 ; Device address
USB_FS_DADDR_ADD1_ofs EQU 1
USB_FS_DADDR_ADD1_len EQU 1
USB_FS_DADDR_ADD2 EQU 0x00000004 ; Device address
USB_FS_DADDR_ADD2_ofs EQU 2
USB_FS_DADDR_ADD2_len EQU 1
USB_FS_DADDR_ADD3 EQU 0x00000008 ; Device address
USB_FS_DADDR_ADD3_ofs EQU 3
USB_FS_DADDR_ADD3_len EQU 1
USB_FS_DADDR_ADD4 EQU 0x00000010 ; Device address
USB_FS_DADDR_ADD4_ofs EQU 4
USB_FS_DADDR_ADD4_len EQU 1
USB_FS_DADDR_ADD5 EQU 0x00000020 ; Device address
USB_FS_DADDR_ADD5_ofs EQU 5
USB_FS_DADDR_ADD5_len EQU 1
USB_FS_DADDR_ADD6 EQU 0x00000040 ; Device address
USB_FS_DADDR_ADD6_ofs EQU 6
USB_FS_DADDR_ADD6_len EQU 1
USB_FS_DADDR_EF EQU 0x00000080 ; Enable function
USB_FS_DADDR_EF_ofs EQU 7
USB_FS_DADDR_EF_len EQU 1
; USB_FS_BTABLE fields:
USB_FS_BTABLE_BTABLE EQU 0x0000fff8 ; Buffer table
USB_FS_BTABLE_BTABLE_ofs EQU 3
USB_FS_BTABLE_BTABLE_len EQU 13
; ---- I2C1 --------------------------------------------------
; Desc: Inter-integrated circuit
; I2C1 base address:
I2C1_BASE EQU 0x40005400
; I2C1 registers:
I2C1_CR1 EQU (I2C1_BASE + 0x0) ; Control register 1
I2C1_CR2 EQU (I2C1_BASE + 0x4) ; Control register 2
I2C1_OAR1 EQU (I2C1_BASE + 0x8) ; Own address register 1
I2C1_OAR2 EQU (I2C1_BASE + 0xc) ; Own address register 2
I2C1_TIMINGR EQU (I2C1_BASE + 0x10) ; Timing register
I2C1_TIMEOUTR EQU (I2C1_BASE + 0x14) ; Status register 1
I2C1_ISR EQU (I2C1_BASE + 0x18) ; Interrupt and Status register
I2C1_ICR EQU (I2C1_BASE + 0x1c) ; Interrupt clear register
I2C1_PECR EQU (I2C1_BASE + 0x20) ; PEC register
I2C1_RXDR EQU (I2C1_BASE + 0x24) ; Receive data register
I2C1_TXDR EQU (I2C1_BASE + 0x28) ; Transmit data register
; I2C1_CR1 fields:
I2C_CR1_PE EQU 0x00000001 ; Peripheral enable
I2C_CR1_PE_ofs EQU 0
I2C_CR1_PE_len EQU 1
I2C_CR1_TXIE EQU 0x00000002 ; TX Interrupt enable
I2C_CR1_TXIE_ofs EQU 1
I2C_CR1_TXIE_len EQU 1
I2C_CR1_RXIE EQU 0x00000004 ; RX Interrupt enable
I2C_CR1_RXIE_ofs EQU 2
I2C_CR1_RXIE_len EQU 1
I2C_CR1_ADDRIE EQU 0x00000008 ; Address match interrupt enable (slave only)
I2C_CR1_ADDRIE_ofs EQU 3
I2C_CR1_ADDRIE_len EQU 1
I2C_CR1_NACKIE EQU 0x00000010 ; Not acknowledge received interrupt enable
I2C_CR1_NACKIE_ofs EQU 4
I2C_CR1_NACKIE_len EQU 1
I2C_CR1_STOPIE EQU 0x00000020 ; STOP detection Interrupt enable
I2C_CR1_STOPIE_ofs EQU 5
I2C_CR1_STOPIE_len EQU 1
I2C_CR1_TCIE EQU 0x00000040 ; Transfer Complete interrupt enable
I2C_CR1_TCIE_ofs EQU 6
I2C_CR1_TCIE_len EQU 1
I2C_CR1_ERRIE EQU 0x00000080 ; Error interrupts enable
I2C_CR1_ERRIE_ofs EQU 7
I2C_CR1_ERRIE_len EQU 1
I2C_CR1_DNF EQU 0x00000f00 ; Digital noise filter
I2C_CR1_DNF_ofs EQU 8
I2C_CR1_DNF_len EQU 4
I2C_CR1_ANFOFF EQU 0x00001000 ; Analog noise filter OFF
I2C_CR1_ANFOFF_ofs EQU 12
I2C_CR1_ANFOFF_len EQU 1
I2C_CR1_SWRST EQU 0x00002000 ; Software reset
I2C_CR1_SWRST_ofs EQU 13
I2C_CR1_SWRST_len EQU 1
I2C_CR1_TXDMAEN EQU 0x00004000 ; DMA transmission requests enable
I2C_CR1_TXDMAEN_ofs EQU 14
I2C_CR1_TXDMAEN_len EQU 1
I2C_CR1_RXDMAEN EQU 0x00008000 ; DMA reception requests enable
I2C_CR1_RXDMAEN_ofs EQU 15
I2C_CR1_RXDMAEN_len EQU 1
I2C_CR1_SBC EQU 0x00010000 ; Slave byte control
I2C_CR1_SBC_ofs EQU 16
I2C_CR1_SBC_len EQU 1
I2C_CR1_NOSTRETCH EQU 0x00020000 ; Clock stretching disable
I2C_CR1_NOSTRETCH_ofs EQU 17
I2C_CR1_NOSTRETCH_len EQU 1
I2C_CR1_WUPEN EQU 0x00040000 ; Wakeup from STOP enable
I2C_CR1_WUPEN_ofs EQU 18
I2C_CR1_WUPEN_len EQU 1
I2C_CR1_GCEN EQU 0x00080000 ; General call enable
I2C_CR1_GCEN_ofs EQU 19
I2C_CR1_GCEN_len EQU 1
I2C_CR1_SMBHEN EQU 0x00100000 ; SMBus Host address enable
I2C_CR1_SMBHEN_ofs EQU 20
I2C_CR1_SMBHEN_len EQU 1
I2C_CR1_SMBDEN EQU 0x00200000 ; SMBus Device Default address enable
I2C_CR1_SMBDEN_ofs EQU 21
I2C_CR1_SMBDEN_len EQU 1
I2C_CR1_ALERTEN EQU 0x00400000 ; SMBUS alert enable
I2C_CR1_ALERTEN_ofs EQU 22
I2C_CR1_ALERTEN_len EQU 1
I2C_CR1_PECEN EQU 0x00800000 ; PEC enable
I2C_CR1_PECEN_ofs EQU 23
I2C_CR1_PECEN_len EQU 1
; I2C1_CR2 fields:
I2C_CR2_PECBYTE EQU 0x04000000 ; Packet error checking byte
I2C_CR2_PECBYTE_ofs EQU 26
I2C_CR2_PECBYTE_len EQU 1
I2C_CR2_AUTOEND EQU 0x02000000 ; Automatic end mode (master mode)
I2C_CR2_AUTOEND_ofs EQU 25
I2C_CR2_AUTOEND_len EQU 1
I2C_CR2_RELOAD EQU 0x01000000 ; NBYTES reload mode
I2C_CR2_RELOAD_ofs EQU 24
I2C_CR2_RELOAD_len EQU 1
I2C_CR2_NBYTES EQU 0x00ff0000 ; Number of bytes
I2C_CR2_NBYTES_ofs EQU 16
I2C_CR2_NBYTES_len EQU 8
I2C_CR2_NACK EQU 0x00008000 ; NACK generation (slave mode)
I2C_CR2_NACK_ofs EQU 15
I2C_CR2_NACK_len EQU 1
I2C_CR2_STOP EQU 0x00004000 ; Stop generation (master mode)
I2C_CR2_STOP_ofs EQU 14
I2C_CR2_STOP_len EQU 1
I2C_CR2_START EQU 0x00002000 ; Start generation
I2C_CR2_START_ofs EQU 13
I2C_CR2_START_len EQU 1
I2C_CR2_HEAD10R EQU 0x00001000 ; 10-bit address header only read direction (master receiver mode)
I2C_CR2_HEAD10R_ofs EQU 12
I2C_CR2_HEAD10R_len EQU 1
I2C_CR2_ADD10 EQU 0x00000800 ; 10-bit addressing mode (master mode)
I2C_CR2_ADD10_ofs EQU 11
I2C_CR2_ADD10_len EQU 1
I2C_CR2_RD_WRN EQU 0x00000400 ; Transfer direction (master mode)
I2C_CR2_RD_WRN_ofs EQU 10
I2C_CR2_RD_WRN_len EQU 1
I2C_CR2_SADD8 EQU 0x00000300 ; Slave address bit 9:8 (master mode)
I2C_CR2_SADD8_ofs EQU 8
I2C_CR2_SADD8_len EQU 2
I2C_CR2_SADD1 EQU 0x000000fe ; Slave address bit 7:1 (master mode)
I2C_CR2_SADD1_ofs EQU 1
I2C_CR2_SADD1_len EQU 7
I2C_CR2_SADD0 EQU 0x00000001 ; Slave address bit 0 (master mode)
I2C_CR2_SADD0_ofs EQU 0
I2C_CR2_SADD0_len EQU 1
; I2C1_OAR1 fields:
I2C_OAR1_OA1_0 EQU 0x00000001 ; Interface address
I2C_OAR1_OA1_0_ofs EQU 0
I2C_OAR1_OA1_0_len EQU 1
I2C_OAR1_OA1_1 EQU 0x000000fe ; Interface address
I2C_OAR1_OA1_1_ofs EQU 1
I2C_OAR1_OA1_1_len EQU 7
I2C_OAR1_OA1_8 EQU 0x00000300 ; Interface address
I2C_OAR1_OA1_8_ofs EQU 8
I2C_OAR1_OA1_8_len EQU 2
I2C_OAR1_OA1MODE EQU 0x00000400 ; Own Address 1 10-bit mode
I2C_OAR1_OA1MODE_ofs EQU 10
I2C_OAR1_OA1MODE_len EQU 1
I2C_OAR1_OA1EN EQU 0x00008000 ; Own Address 1 enable
I2C_OAR1_OA1EN_ofs EQU 15
I2C_OAR1_OA1EN_len EQU 1
; I2C1_OAR2 fields:
I2C_OAR2_OA2 EQU 0x000000fe ; Interface address
I2C_OAR2_OA2_ofs EQU 1
I2C_OAR2_OA2_len EQU 7
I2C_OAR2_OA2MSK EQU 0x00000700 ; Own Address 2 masks
I2C_OAR2_OA2MSK_ofs EQU 8
I2C_OAR2_OA2MSK_len EQU 3
I2C_OAR2_OA2EN EQU 0x00008000 ; Own Address 2 enable
I2C_OAR2_OA2EN_ofs EQU 15
I2C_OAR2_OA2EN_len EQU 1
; I2C1_TIMINGR fields:
I2C_TIMINGR_SCLL EQU 0x000000ff ; SCL low period (master mode)
I2C_TIMINGR_SCLL_ofs EQU 0
I2C_TIMINGR_SCLL_len EQU 8
I2C_TIMINGR_SCLH EQU 0x0000ff00 ; SCL high period (master mode)
I2C_TIMINGR_SCLH_ofs EQU 8
I2C_TIMINGR_SCLH_len EQU 8
I2C_TIMINGR_SDADEL EQU 0x000f0000 ; Data hold time
I2C_TIMINGR_SDADEL_ofs EQU 16
I2C_TIMINGR_SDADEL_len EQU 4
I2C_TIMINGR_SCLDEL EQU 0x00f00000 ; Data setup time
I2C_TIMINGR_SCLDEL_ofs EQU 20
I2C_TIMINGR_SCLDEL_len EQU 4
I2C_TIMINGR_PRESC EQU 0xf0000000 ; Timing prescaler
I2C_TIMINGR_PRESC_ofs EQU 28
I2C_TIMINGR_PRESC_len EQU 4
; I2C1_TIMEOUTR fields:
I2C_TIMEOUTR_TIMEOUTA EQU 0x00000fff ; Bus timeout A
I2C_TIMEOUTR_TIMEOUTA_ofs EQU 0
I2C_TIMEOUTR_TIMEOUTA_len EQU 12
I2C_TIMEOUTR_TIDLE EQU 0x00001000 ; Idle clock timeout detection
I2C_TIMEOUTR_TIDLE_ofs EQU 12
I2C_TIMEOUTR_TIDLE_len EQU 1
I2C_TIMEOUTR_TIMOUTEN EQU 0x00008000 ; Clock timeout enable
I2C_TIMEOUTR_TIMOUTEN_ofs EQU 15
I2C_TIMEOUTR_TIMOUTEN_len EQU 1
I2C_TIMEOUTR_TIMEOUTB EQU 0x0fff0000 ; Bus timeout B
I2C_TIMEOUTR_TIMEOUTB_ofs EQU 16
I2C_TIMEOUTR_TIMEOUTB_len EQU 12
I2C_TIMEOUTR_TEXTEN EQU 0x80000000 ; Extended clock timeout enable
I2C_TIMEOUTR_TEXTEN_ofs EQU 31
I2C_TIMEOUTR_TEXTEN_len EQU 1
; I2C1_ISR fields:
I2C_ISR_ADDCODE EQU 0x00fe0000 ; Address match code (Slave mode)
I2C_ISR_ADDCODE_ofs EQU 17
I2C_ISR_ADDCODE_len EQU 7
I2C_ISR_DIR EQU 0x00010000 ; Transfer direction (Slave mode)
I2C_ISR_DIR_ofs EQU 16
I2C_ISR_DIR_len EQU 1
I2C_ISR_BUSY EQU 0x00008000 ; Bus busy
I2C_ISR_BUSY_ofs EQU 15
I2C_ISR_BUSY_len EQU 1
I2C_ISR_ALERT EQU 0x00002000 ; SMBus alert
I2C_ISR_ALERT_ofs EQU 13
I2C_ISR_ALERT_len EQU 1
I2C_ISR_TIMEOUT EQU 0x00001000 ; Timeout or t_low detection flag
I2C_ISR_TIMEOUT_ofs EQU 12
I2C_ISR_TIMEOUT_len EQU 1
I2C_ISR_PECERR EQU 0x00000800 ; PEC Error in reception
I2C_ISR_PECERR_ofs EQU 11
I2C_ISR_PECERR_len EQU 1
I2C_ISR_OVR EQU 0x00000400 ; Overrun/Underrun (slave mode)
I2C_ISR_OVR_ofs EQU 10
I2C_ISR_OVR_len EQU 1
I2C_ISR_ARLO EQU 0x00000200 ; Arbitration lost
I2C_ISR_ARLO_ofs EQU 9
I2C_ISR_ARLO_len EQU 1
I2C_ISR_BERR EQU 0x00000100 ; Bus error
I2C_ISR_BERR_ofs EQU 8
I2C_ISR_BERR_len EQU 1
I2C_ISR_TCR EQU 0x00000080 ; Transfer Complete Reload
I2C_ISR_TCR_ofs EQU 7
I2C_ISR_TCR_len EQU 1
I2C_ISR_TC EQU 0x00000040 ; Transfer Complete (master mode)
I2C_ISR_TC_ofs EQU 6
I2C_ISR_TC_len EQU 1
I2C_ISR_STOPF EQU 0x00000020 ; Stop detection flag
I2C_ISR_STOPF_ofs EQU 5
I2C_ISR_STOPF_len EQU 1
I2C_ISR_NACKF EQU 0x00000010 ; Not acknowledge received flag
I2C_ISR_NACKF_ofs EQU 4
I2C_ISR_NACKF_len EQU 1
I2C_ISR_ADDR EQU 0x00000008 ; Address matched (slave mode)
I2C_ISR_ADDR_ofs EQU 3
I2C_ISR_ADDR_len EQU 1
I2C_ISR_RXNE EQU 0x00000004 ; Receive data register not empty (receivers)
I2C_ISR_RXNE_ofs EQU 2
I2C_ISR_RXNE_len EQU 1
I2C_ISR_TXIS EQU 0x00000002 ; Transmit interrupt status (transmitters)
I2C_ISR_TXIS_ofs EQU 1
I2C_ISR_TXIS_len EQU 1
I2C_ISR_TXE EQU 0x00000001 ; Transmit data register empty (transmitters)
I2C_ISR_TXE_ofs EQU 0
I2C_ISR_TXE_len EQU 1
; I2C1_ICR fields:
I2C_ICR_ALERTCF EQU 0x00002000 ; Alert flag clear
I2C_ICR_ALERTCF_ofs EQU 13
I2C_ICR_ALERTCF_len EQU 1
I2C_ICR_TIMOUTCF EQU 0x00001000 ; Timeout detection flag clear
I2C_ICR_TIMOUTCF_ofs EQU 12
I2C_ICR_TIMOUTCF_len EQU 1
I2C_ICR_PECCF EQU 0x00000800 ; PEC Error flag clear
I2C_ICR_PECCF_ofs EQU 11
I2C_ICR_PECCF_len EQU 1
I2C_ICR_OVRCF EQU 0x00000400 ; Overrun/Underrun flag clear
I2C_ICR_OVRCF_ofs EQU 10
I2C_ICR_OVRCF_len EQU 1
I2C_ICR_ARLOCF EQU 0x00000200 ; Arbitration lost flag clear
I2C_ICR_ARLOCF_ofs EQU 9
I2C_ICR_ARLOCF_len EQU 1
I2C_ICR_BERRCF EQU 0x00000100 ; Bus error flag clear
I2C_ICR_BERRCF_ofs EQU 8
I2C_ICR_BERRCF_len EQU 1
I2C_ICR_STOPCF EQU 0x00000020 ; Stop detection flag clear
I2C_ICR_STOPCF_ofs EQU 5
I2C_ICR_STOPCF_len EQU 1
I2C_ICR_NACKCF EQU 0x00000010 ; Not Acknowledge flag clear
I2C_ICR_NACKCF_ofs EQU 4
I2C_ICR_NACKCF_len EQU 1
I2C_ICR_ADDRCF EQU 0x00000008 ; Address Matched flag clear
I2C_ICR_ADDRCF_ofs EQU 3
I2C_ICR_ADDRCF_len EQU 1
; I2C1_PECR fields:
I2C_PECR_PEC EQU 0x000000ff ; Packet error checking register
I2C_PECR_PEC_ofs EQU 0
I2C_PECR_PEC_len EQU 8
; I2C1_RXDR fields:
I2C_RXDR_RXDATA EQU 0x000000ff ; 8-bit receive data
I2C_RXDR_RXDATA_ofs EQU 0
I2C_RXDR_RXDATA_len EQU 8
; I2C1_TXDR fields:
I2C_TXDR_TXDATA EQU 0x000000ff ; 8-bit transmit data
I2C_TXDR_TXDATA_ofs EQU 0
I2C_TXDR_TXDATA_len EQU 8
; ---- I2C2 --------------------------------------------------
; Desc: None
; I2C2 base address:
I2C2_BASE EQU 0x40005800
; I2C2 registers:
I2C2_CR1 EQU (I2C2_BASE + 0x0) ; Control register 1
I2C2_CR2 EQU (I2C2_BASE + 0x4) ; Control register 2
I2C2_OAR1 EQU (I2C2_BASE + 0x8) ; Own address register 1
I2C2_OAR2 EQU (I2C2_BASE + 0xc) ; Own address register 2
I2C2_TIMINGR EQU (I2C2_BASE + 0x10) ; Timing register
I2C2_TIMEOUTR EQU (I2C2_BASE + 0x14) ; Status register 1
I2C2_ISR EQU (I2C2_BASE + 0x18) ; Interrupt and Status register
I2C2_ICR EQU (I2C2_BASE + 0x1c) ; Interrupt clear register
I2C2_PECR EQU (I2C2_BASE + 0x20) ; PEC register
I2C2_RXDR EQU (I2C2_BASE + 0x24) ; Receive data register
I2C2_TXDR EQU (I2C2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- IWDG --------------------------------------------------
; Desc: Independent watchdog
; IWDG base address:
IWDG_BASE EQU 0x40003000
; IWDG registers:
IWDG_KR EQU (IWDG_BASE + 0x0) ; Key register
IWDG_PR EQU (IWDG_BASE + 0x4) ; Prescaler register
IWDG_RLR EQU (IWDG_BASE + 0x8) ; Reload register
IWDG_SR EQU (IWDG_BASE + 0xc) ; Status register
IWDG_WINR EQU (IWDG_BASE + 0x10) ; Window register
; IWDG_KR fields:
IWDG_KR_KEY EQU 0x0000ffff ; Key value
IWDG_KR_KEY_ofs EQU 0
IWDG_KR_KEY_len EQU 16
; IWDG_PR fields:
IWDG_PR_PR EQU 0x00000007 ; Prescaler divider
IWDG_PR_PR_ofs EQU 0
IWDG_PR_PR_len EQU 3
; IWDG_RLR fields:
IWDG_RLR_RL EQU 0x00000fff ; Watchdog counter reload value
IWDG_RLR_RL_ofs EQU 0
IWDG_RLR_RL_len EQU 12
; IWDG_SR fields:
IWDG_SR_PVU EQU 0x00000001 ; Watchdog prescaler value update
IWDG_SR_PVU_ofs EQU 0
IWDG_SR_PVU_len EQU 1
IWDG_SR_RVU EQU 0x00000002 ; Watchdog counter reload value update
IWDG_SR_RVU_ofs EQU 1
IWDG_SR_RVU_len EQU 1
IWDG_SR_WVU EQU 0x00000004 ; Watchdog counter window value update
IWDG_SR_WVU_ofs EQU 2
IWDG_SR_WVU_len EQU 1
; IWDG_WINR fields:
IWDG_WINR_WIN EQU 0x00000fff ; Watchdog counter window value
IWDG_WINR_WIN_ofs EQU 0
IWDG_WINR_WIN_len EQU 12
; ---- WWDG --------------------------------------------------
; Desc: Window watchdog
; WWDG base address:
WWDG_BASE EQU 0x40002c00
; WWDG registers:
WWDG_CR EQU (WWDG_BASE + 0x0) ; Control register
WWDG_CFR EQU (WWDG_BASE + 0x4) ; Configuration register
WWDG_SR EQU (WWDG_BASE + 0x8) ; Status register
; WWDG_CR fields:
WWDG_CR_T EQU 0x0000007f ; 7-bit counter
WWDG_CR_T_ofs EQU 0
WWDG_CR_T_len EQU 7
WWDG_CR_WDGA EQU 0x00000080 ; Activation bit
WWDG_CR_WDGA_ofs EQU 7
WWDG_CR_WDGA_len EQU 1
; WWDG_CFR fields:
WWDG_CFR_EWI EQU 0x00000200 ; Early wakeup interrupt
WWDG_CFR_EWI_ofs EQU 9
WWDG_CFR_EWI_len EQU 1
WWDG_CFR_WDGTB EQU 0x00000180 ; Timer base
WWDG_CFR_WDGTB_ofs EQU 7
WWDG_CFR_WDGTB_len EQU 2
WWDG_CFR_W EQU 0x0000007f ; 7-bit window value
WWDG_CFR_W_ofs EQU 0
WWDG_CFR_W_len EQU 7
; WWDG_SR fields:
WWDG_SR_EWIF EQU 0x00000001 ; Early wakeup interrupt flag
WWDG_SR_EWIF_ofs EQU 0
WWDG_SR_EWIF_len EQU 1
; ---- RTC ---------------------------------------------------
; Desc: Real-time clock
; RTC base address:
RTC_BASE EQU 0x40002800
; RTC registers:
RTC_TR EQU (RTC_BASE + 0x0) ; time register
RTC_DR EQU (RTC_BASE + 0x4) ; date register
RTC_CR EQU (RTC_BASE + 0x8) ; control register
RTC_ISR EQU (RTC_BASE + 0xc) ; initialization and status register
RTC_PRER EQU (RTC_BASE + 0x10) ; prescaler register
RTC_WUTR EQU (RTC_BASE + 0x14) ; wakeup timer register
RTC_ALRMAR EQU (RTC_BASE + 0x1c) ; alarm A register
RTC_ALRMBR EQU (RTC_BASE + 0x20) ; alarm B register
RTC_WPR EQU (RTC_BASE + 0x24) ; write protection register
RTC_SSR EQU (RTC_BASE + 0x28) ; sub second register
RTC_SHIFTR EQU (RTC_BASE + 0x2c) ; shift control register
RTC_TSTR EQU (RTC_BASE + 0x30) ; time stamp time register
RTC_TSDR EQU (RTC_BASE + 0x34) ; time stamp date register
RTC_TSSSR EQU (RTC_BASE + 0x38) ; timestamp sub second register
RTC_CALR EQU (RTC_BASE + 0x3c) ; calibration register
RTC_TAFCR EQU (RTC_BASE + 0x40) ; tamper and alternate function configuration register
RTC_ALRMASSR EQU (RTC_BASE + 0x44) ; alarm A sub second register
RTC_ALRMBSSR EQU (RTC_BASE + 0x48) ; alarm B sub second register
RTC_BKP0R EQU (RTC_BASE + 0x50) ; backup register
RTC_BKP1R EQU (RTC_BASE + 0x54) ; backup register
RTC_BKP2R EQU (RTC_BASE + 0x58) ; backup register
RTC_BKP3R EQU (RTC_BASE + 0x5c) ; backup register
RTC_BKP4R EQU (RTC_BASE + 0x60) ; backup register
RTC_BKP5R EQU (RTC_BASE + 0x64) ; backup register
RTC_BKP6R EQU (RTC_BASE + 0x68) ; backup register
RTC_BKP7R EQU (RTC_BASE + 0x6c) ; backup register
RTC_BKP8R EQU (RTC_BASE + 0x70) ; backup register
RTC_BKP9R EQU (RTC_BASE + 0x74) ; backup register
RTC_BKP10R EQU (RTC_BASE + 0x78) ; backup register
RTC_BKP11R EQU (RTC_BASE + 0x7c) ; backup register
RTC_BKP12R EQU (RTC_BASE + 0x80) ; backup register
RTC_BKP13R EQU (RTC_BASE + 0x84) ; backup register
RTC_BKP14R EQU (RTC_BASE + 0x88) ; backup register
RTC_BKP15R EQU (RTC_BASE + 0x8c) ; backup register
RTC_BKP16R EQU (RTC_BASE + 0x90) ; backup register
RTC_BKP17R EQU (RTC_BASE + 0x94) ; backup register
RTC_BKP18R EQU (RTC_BASE + 0x98) ; backup register
RTC_BKP19R EQU (RTC_BASE + 0x9c) ; backup register
RTC_BKP20R EQU (RTC_BASE + 0xa0) ; backup register
RTC_BKP21R EQU (RTC_BASE + 0xa4) ; backup register
RTC_BKP22R EQU (RTC_BASE + 0xa8) ; backup register
RTC_BKP23R EQU (RTC_BASE + 0xac) ; backup register
RTC_BKP24R EQU (RTC_BASE + 0xb0) ; backup register
RTC_BKP25R EQU (RTC_BASE + 0xb4) ; backup register
RTC_BKP26R EQU (RTC_BASE + 0xb8) ; backup register
RTC_BKP27R EQU (RTC_BASE + 0xbc) ; backup register
RTC_BKP28R EQU (RTC_BASE + 0xc0) ; backup register
RTC_BKP29R EQU (RTC_BASE + 0xc4) ; backup register
RTC_BKP30R EQU (RTC_BASE + 0xc8) ; backup register
RTC_BKP31R EQU (RTC_BASE + 0xcc) ; backup register
; RTC_TR fields:
RTC_TR_PM EQU 0x00400000 ; AM/PM notation
RTC_TR_PM_ofs EQU 22
RTC_TR_PM_len EQU 1
RTC_TR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TR_HT_ofs EQU 20
RTC_TR_HT_len EQU 2
RTC_TR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TR_HU_ofs EQU 16
RTC_TR_HU_len EQU 4
RTC_TR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TR_MNT_ofs EQU 12
RTC_TR_MNT_len EQU 3
RTC_TR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TR_MNU_ofs EQU 8
RTC_TR_MNU_len EQU 4
RTC_TR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TR_ST_ofs EQU 4
RTC_TR_ST_len EQU 3
RTC_TR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TR_SU_ofs EQU 0
RTC_TR_SU_len EQU 4
; RTC_DR fields:
RTC_DR_YT EQU 0x00f00000 ; Year tens in BCD format
RTC_DR_YT_ofs EQU 20
RTC_DR_YT_len EQU 4
RTC_DR_YU EQU 0x000f0000 ; Year units in BCD format
RTC_DR_YU_ofs EQU 16
RTC_DR_YU_len EQU 4
RTC_DR_WDU EQU 0x0000e000 ; Week day units
RTC_DR_WDU_ofs EQU 13
RTC_DR_WDU_len EQU 3
RTC_DR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_DR_MT_ofs EQU 12
RTC_DR_MT_len EQU 1
RTC_DR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_DR_MU_ofs EQU 8
RTC_DR_MU_len EQU 4
RTC_DR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_DR_DT_ofs EQU 4
RTC_DR_DT_len EQU 2
RTC_DR_DU EQU 0x0000000f ; Date units in BCD format
RTC_DR_DU_ofs EQU 0
RTC_DR_DU_len EQU 4
; RTC_CR fields:
RTC_CR_WCKSEL EQU 0x00000007 ; Wakeup clock selection
RTC_CR_WCKSEL_ofs EQU 0
RTC_CR_WCKSEL_len EQU 3
RTC_CR_TSEDGE EQU 0x00000008 ; Time-stamp event active edge
RTC_CR_TSEDGE_ofs EQU 3
RTC_CR_TSEDGE_len EQU 1
RTC_CR_REFCKON EQU 0x00000010 ; Reference clock detection enable (50 or 60 Hz)
RTC_CR_REFCKON_ofs EQU 4
RTC_CR_REFCKON_len EQU 1
RTC_CR_BYPSHAD EQU 0x00000020 ; Bypass the shadow registers
RTC_CR_BYPSHAD_ofs EQU 5
RTC_CR_BYPSHAD_len EQU 1
RTC_CR_FMT EQU 0x00000040 ; Hour format
RTC_CR_FMT_ofs EQU 6
RTC_CR_FMT_len EQU 1
RTC_CR_ALRAE EQU 0x00000100 ; Alarm A enable
RTC_CR_ALRAE_ofs EQU 8
RTC_CR_ALRAE_len EQU 1
RTC_CR_ALRBE EQU 0x00000200 ; Alarm B enable
RTC_CR_ALRBE_ofs EQU 9
RTC_CR_ALRBE_len EQU 1
RTC_CR_WUTE EQU 0x00000400 ; Wakeup timer enable
RTC_CR_WUTE_ofs EQU 10
RTC_CR_WUTE_len EQU 1
RTC_CR_TSE EQU 0x00000800 ; Time stamp enable
RTC_CR_TSE_ofs EQU 11
RTC_CR_TSE_len EQU 1
RTC_CR_ALRAIE EQU 0x00001000 ; Alarm A interrupt enable
RTC_CR_ALRAIE_ofs EQU 12
RTC_CR_ALRAIE_len EQU 1
RTC_CR_ALRBIE EQU 0x00002000 ; Alarm B interrupt enable
RTC_CR_ALRBIE_ofs EQU 13
RTC_CR_ALRBIE_len EQU 1
RTC_CR_WUTIE EQU 0x00004000 ; Wakeup timer interrupt enable
RTC_CR_WUTIE_ofs EQU 14
RTC_CR_WUTIE_len EQU 1
RTC_CR_TSIE EQU 0x00008000 ; Time-stamp interrupt enable
RTC_CR_TSIE_ofs EQU 15
RTC_CR_TSIE_len EQU 1
RTC_CR_ADD1H EQU 0x00010000 ; Add 1 hour (summer time change)
RTC_CR_ADD1H_ofs EQU 16
RTC_CR_ADD1H_len EQU 1
RTC_CR_SUB1H EQU 0x00020000 ; Subtract 1 hour (winter time change)
RTC_CR_SUB1H_ofs EQU 17
RTC_CR_SUB1H_len EQU 1
RTC_CR_BKP EQU 0x00040000 ; Backup
RTC_CR_BKP_ofs EQU 18
RTC_CR_BKP_len EQU 1
RTC_CR_COSEL EQU 0x00080000 ; Calibration output selection
RTC_CR_COSEL_ofs EQU 19
RTC_CR_COSEL_len EQU 1
RTC_CR_POL EQU 0x00100000 ; Output polarity
RTC_CR_POL_ofs EQU 20
RTC_CR_POL_len EQU 1
RTC_CR_OSEL EQU 0x00600000 ; Output selection
RTC_CR_OSEL_ofs EQU 21
RTC_CR_OSEL_len EQU 2
RTC_CR_COE EQU 0x00800000 ; Calibration output enable
RTC_CR_COE_ofs EQU 23
RTC_CR_COE_len EQU 1
; RTC_ISR fields:
RTC_ISR_ALRAWF EQU 0x00000001 ; Alarm A write flag
RTC_ISR_ALRAWF_ofs EQU 0
RTC_ISR_ALRAWF_len EQU 1
RTC_ISR_ALRBWF EQU 0x00000002 ; Alarm B write flag
RTC_ISR_ALRBWF_ofs EQU 1
RTC_ISR_ALRBWF_len EQU 1
RTC_ISR_WUTWF EQU 0x00000004 ; Wakeup timer write flag
RTC_ISR_WUTWF_ofs EQU 2
RTC_ISR_WUTWF_len EQU 1
RTC_ISR_SHPF EQU 0x00000008 ; Shift operation pending
RTC_ISR_SHPF_ofs EQU 3
RTC_ISR_SHPF_len EQU 1
RTC_ISR_INITS EQU 0x00000010 ; Initialization status flag
RTC_ISR_INITS_ofs EQU 4
RTC_ISR_INITS_len EQU 1
RTC_ISR_RSF EQU 0x00000020 ; Registers synchronization flag
RTC_ISR_RSF_ofs EQU 5
RTC_ISR_RSF_len EQU 1
RTC_ISR_INITF EQU 0x00000040 ; Initialization flag
RTC_ISR_INITF_ofs EQU 6
RTC_ISR_INITF_len EQU 1
RTC_ISR_INIT EQU 0x00000080 ; Initialization mode
RTC_ISR_INIT_ofs EQU 7
RTC_ISR_INIT_len EQU 1
RTC_ISR_ALRAF EQU 0x00000100 ; Alarm A flag
RTC_ISR_ALRAF_ofs EQU 8
RTC_ISR_ALRAF_len EQU 1
RTC_ISR_ALRBF EQU 0x00000200 ; Alarm B flag
RTC_ISR_ALRBF_ofs EQU 9
RTC_ISR_ALRBF_len EQU 1
RTC_ISR_WUTF EQU 0x00000400 ; Wakeup timer flag
RTC_ISR_WUTF_ofs EQU 10
RTC_ISR_WUTF_len EQU 1
RTC_ISR_TSF EQU 0x00000800 ; Time-stamp flag
RTC_ISR_TSF_ofs EQU 11
RTC_ISR_TSF_len EQU 1
RTC_ISR_TSOVF EQU 0x00001000 ; Time-stamp overflow flag
RTC_ISR_TSOVF_ofs EQU 12
RTC_ISR_TSOVF_len EQU 1
RTC_ISR_TAMP1F EQU 0x00002000 ; Tamper detection flag
RTC_ISR_TAMP1F_ofs EQU 13
RTC_ISR_TAMP1F_len EQU 1
RTC_ISR_TAMP2F EQU 0x00004000 ; RTC_TAMP2 detection flag
RTC_ISR_TAMP2F_ofs EQU 14
RTC_ISR_TAMP2F_len EQU 1
RTC_ISR_TAMP3F EQU 0x00008000 ; RTC_TAMP3 detection flag
RTC_ISR_TAMP3F_ofs EQU 15
RTC_ISR_TAMP3F_len EQU 1
RTC_ISR_RECALPF EQU 0x00010000 ; Recalibration pending Flag
RTC_ISR_RECALPF_ofs EQU 16
RTC_ISR_RECALPF_len EQU 1
; RTC_PRER fields:
RTC_PRER_PREDIV_A EQU 0x007f0000 ; Asynchronous prescaler factor
RTC_PRER_PREDIV_A_ofs EQU 16
RTC_PRER_PREDIV_A_len EQU 7
RTC_PRER_PREDIV_S EQU 0x00007fff ; Synchronous prescaler factor
RTC_PRER_PREDIV_S_ofs EQU 0
RTC_PRER_PREDIV_S_len EQU 15
; RTC_WUTR fields:
RTC_WUTR_WUT EQU 0x0000ffff ; Wakeup auto-reload value bits
RTC_WUTR_WUT_ofs EQU 0
RTC_WUTR_WUT_len EQU 16
; RTC_ALRMAR fields:
RTC_ALRMAR_MSK4 EQU 0x80000000 ; Alarm A date mask
RTC_ALRMAR_MSK4_ofs EQU 31
RTC_ALRMAR_MSK4_len EQU 1
RTC_ALRMAR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMAR_WDSEL_ofs EQU 30
RTC_ALRMAR_WDSEL_len EQU 1
RTC_ALRMAR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMAR_DT_ofs EQU 28
RTC_ALRMAR_DT_len EQU 2
RTC_ALRMAR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMAR_DU_ofs EQU 24
RTC_ALRMAR_DU_len EQU 4
RTC_ALRMAR_MSK3 EQU 0x00800000 ; Alarm A hours mask
RTC_ALRMAR_MSK3_ofs EQU 23
RTC_ALRMAR_MSK3_len EQU 1
RTC_ALRMAR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMAR_PM_ofs EQU 22
RTC_ALRMAR_PM_len EQU 1
RTC_ALRMAR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMAR_HT_ofs EQU 20
RTC_ALRMAR_HT_len EQU 2
RTC_ALRMAR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMAR_HU_ofs EQU 16
RTC_ALRMAR_HU_len EQU 4
RTC_ALRMAR_MSK2 EQU 0x00008000 ; Alarm A minutes mask
RTC_ALRMAR_MSK2_ofs EQU 15
RTC_ALRMAR_MSK2_len EQU 1
RTC_ALRMAR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMAR_MNT_ofs EQU 12
RTC_ALRMAR_MNT_len EQU 3
RTC_ALRMAR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMAR_MNU_ofs EQU 8
RTC_ALRMAR_MNU_len EQU 4
RTC_ALRMAR_MSK1 EQU 0x00000080 ; Alarm A seconds mask
RTC_ALRMAR_MSK1_ofs EQU 7
RTC_ALRMAR_MSK1_len EQU 1
RTC_ALRMAR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMAR_ST_ofs EQU 4
RTC_ALRMAR_ST_len EQU 3
RTC_ALRMAR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMAR_SU_ofs EQU 0
RTC_ALRMAR_SU_len EQU 4
; RTC_ALRMBR fields:
RTC_ALRMBR_MSK4 EQU 0x80000000 ; Alarm B date mask
RTC_ALRMBR_MSK4_ofs EQU 31
RTC_ALRMBR_MSK4_len EQU 1
RTC_ALRMBR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMBR_WDSEL_ofs EQU 30
RTC_ALRMBR_WDSEL_len EQU 1
RTC_ALRMBR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMBR_DT_ofs EQU 28
RTC_ALRMBR_DT_len EQU 2
RTC_ALRMBR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMBR_DU_ofs EQU 24
RTC_ALRMBR_DU_len EQU 4
RTC_ALRMBR_MSK3 EQU 0x00800000 ; Alarm B hours mask
RTC_ALRMBR_MSK3_ofs EQU 23
RTC_ALRMBR_MSK3_len EQU 1
RTC_ALRMBR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMBR_PM_ofs EQU 22
RTC_ALRMBR_PM_len EQU 1
RTC_ALRMBR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMBR_HT_ofs EQU 20
RTC_ALRMBR_HT_len EQU 2
RTC_ALRMBR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMBR_HU_ofs EQU 16
RTC_ALRMBR_HU_len EQU 4
RTC_ALRMBR_MSK2 EQU 0x00008000 ; Alarm B minutes mask
RTC_ALRMBR_MSK2_ofs EQU 15
RTC_ALRMBR_MSK2_len EQU 1
RTC_ALRMBR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMBR_MNT_ofs EQU 12
RTC_ALRMBR_MNT_len EQU 3
RTC_ALRMBR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMBR_MNU_ofs EQU 8
RTC_ALRMBR_MNU_len EQU 4
RTC_ALRMBR_MSK1 EQU 0x00000080 ; Alarm B seconds mask
RTC_ALRMBR_MSK1_ofs EQU 7
RTC_ALRMBR_MSK1_len EQU 1
RTC_ALRMBR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMBR_ST_ofs EQU 4
RTC_ALRMBR_ST_len EQU 3
RTC_ALRMBR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMBR_SU_ofs EQU 0
RTC_ALRMBR_SU_len EQU 4
; RTC_WPR fields:
RTC_WPR_KEY EQU 0x000000ff ; Write protection key
RTC_WPR_KEY_ofs EQU 0
RTC_WPR_KEY_len EQU 8
; RTC_SSR fields:
RTC_SSR_SS EQU 0x0000ffff ; Sub second value
RTC_SSR_SS_ofs EQU 0
RTC_SSR_SS_len EQU 16
; RTC_SHIFTR fields:
RTC_SHIFTR_ADD1S EQU 0x80000000 ; Add one second
RTC_SHIFTR_ADD1S_ofs EQU 31
RTC_SHIFTR_ADD1S_len EQU 1
RTC_SHIFTR_SUBFS EQU 0x00007fff ; Subtract a fraction of a second
RTC_SHIFTR_SUBFS_ofs EQU 0
RTC_SHIFTR_SUBFS_len EQU 15
; RTC_TSTR fields:
RTC_TSTR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TSTR_SU_ofs EQU 0
RTC_TSTR_SU_len EQU 4
RTC_TSTR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TSTR_ST_ofs EQU 4
RTC_TSTR_ST_len EQU 3
RTC_TSTR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TSTR_MNU_ofs EQU 8
RTC_TSTR_MNU_len EQU 4
RTC_TSTR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TSTR_MNT_ofs EQU 12
RTC_TSTR_MNT_len EQU 3
RTC_TSTR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TSTR_HU_ofs EQU 16
RTC_TSTR_HU_len EQU 4
RTC_TSTR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TSTR_HT_ofs EQU 20
RTC_TSTR_HT_len EQU 2
RTC_TSTR_PM EQU 0x00400000 ; AM/PM notation
RTC_TSTR_PM_ofs EQU 22
RTC_TSTR_PM_len EQU 1
; RTC_TSDR fields:
RTC_TSDR_WDU EQU 0x0000e000 ; Week day units
RTC_TSDR_WDU_ofs EQU 13
RTC_TSDR_WDU_len EQU 3
RTC_TSDR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_TSDR_MT_ofs EQU 12
RTC_TSDR_MT_len EQU 1
RTC_TSDR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_TSDR_MU_ofs EQU 8
RTC_TSDR_MU_len EQU 4
RTC_TSDR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_TSDR_DT_ofs EQU 4
RTC_TSDR_DT_len EQU 2
RTC_TSDR_DU EQU 0x0000000f ; Date units in BCD format
RTC_TSDR_DU_ofs EQU 0
RTC_TSDR_DU_len EQU 4
; RTC_TSSSR fields:
RTC_TSSSR_SS EQU 0x0000ffff ; Sub second value
RTC_TSSSR_SS_ofs EQU 0
RTC_TSSSR_SS_len EQU 16
; RTC_CALR fields:
RTC_CALR_CALP EQU 0x00008000 ; Increase frequency of RTC by 488.5 ppm
RTC_CALR_CALP_ofs EQU 15
RTC_CALR_CALP_len EQU 1
RTC_CALR_CALW8 EQU 0x00004000 ; Use an 8-second calibration cycle period
RTC_CALR_CALW8_ofs EQU 14
RTC_CALR_CALW8_len EQU 1
RTC_CALR_CALW16 EQU 0x00002000 ; Use a 16-second calibration cycle period
RTC_CALR_CALW16_ofs EQU 13
RTC_CALR_CALW16_len EQU 1
RTC_CALR_CALM EQU 0x000001ff ; Calibration minus
RTC_CALR_CALM_ofs EQU 0
RTC_CALR_CALM_len EQU 9
; RTC_TAFCR fields:
RTC_TAFCR_TAMP1E EQU 0x00000001 ; Tamper 1 detection enable
RTC_TAFCR_TAMP1E_ofs EQU 0
RTC_TAFCR_TAMP1E_len EQU 1
RTC_TAFCR_TAMP1TRG EQU 0x00000002 ; Active level for tamper 1
RTC_TAFCR_TAMP1TRG_ofs EQU 1
RTC_TAFCR_TAMP1TRG_len EQU 1
RTC_TAFCR_TAMPIE EQU 0x00000004 ; Tamper interrupt enable
RTC_TAFCR_TAMPIE_ofs EQU 2
RTC_TAFCR_TAMPIE_len EQU 1
RTC_TAFCR_TAMP2E EQU 0x00000008 ; Tamper 2 detection enable
RTC_TAFCR_TAMP2E_ofs EQU 3
RTC_TAFCR_TAMP2E_len EQU 1
RTC_TAFCR_TAMP2TRG EQU 0x00000010 ; Active level for tamper 2
RTC_TAFCR_TAMP2TRG_ofs EQU 4
RTC_TAFCR_TAMP2TRG_len EQU 1
RTC_TAFCR_TAMP3E EQU 0x00000020 ; Tamper 3 detection enable
RTC_TAFCR_TAMP3E_ofs EQU 5
RTC_TAFCR_TAMP3E_len EQU 1
RTC_TAFCR_TAMP3TRG EQU 0x00000040 ; Active level for tamper 3
RTC_TAFCR_TAMP3TRG_ofs EQU 6
RTC_TAFCR_TAMP3TRG_len EQU 1
RTC_TAFCR_TAMPTS EQU 0x00000080 ; Activate timestamp on tamper detection event
RTC_TAFCR_TAMPTS_ofs EQU 7
RTC_TAFCR_TAMPTS_len EQU 1
RTC_TAFCR_TAMPFREQ EQU 0x00000700 ; Tamper sampling frequency
RTC_TAFCR_TAMPFREQ_ofs EQU 8
RTC_TAFCR_TAMPFREQ_len EQU 3
RTC_TAFCR_TAMPFLT EQU 0x00001800 ; Tamper filter count
RTC_TAFCR_TAMPFLT_ofs EQU 11
RTC_TAFCR_TAMPFLT_len EQU 2
RTC_TAFCR_TAMPPRCH EQU 0x00006000 ; Tamper precharge duration
RTC_TAFCR_TAMPPRCH_ofs EQU 13
RTC_TAFCR_TAMPPRCH_len EQU 2
RTC_TAFCR_TAMPPUDIS EQU 0x00008000 ; TAMPER pull-up disable
RTC_TAFCR_TAMPPUDIS_ofs EQU 15
RTC_TAFCR_TAMPPUDIS_len EQU 1
RTC_TAFCR_PC13VALUE EQU 0x00040000 ; PC13 value
RTC_TAFCR_PC13VALUE_ofs EQU 18
RTC_TAFCR_PC13VALUE_len EQU 1
RTC_TAFCR_PC13MODE EQU 0x00080000 ; PC13 mode
RTC_TAFCR_PC13MODE_ofs EQU 19
RTC_TAFCR_PC13MODE_len EQU 1
RTC_TAFCR_PC14VALUE EQU 0x00100000 ; PC14 value
RTC_TAFCR_PC14VALUE_ofs EQU 20
RTC_TAFCR_PC14VALUE_len EQU 1
RTC_TAFCR_PC14MODE EQU 0x00200000 ; PC 14 mode
RTC_TAFCR_PC14MODE_ofs EQU 21
RTC_TAFCR_PC14MODE_len EQU 1
RTC_TAFCR_PC15VALUE EQU 0x00400000 ; PC15 value
RTC_TAFCR_PC15VALUE_ofs EQU 22
RTC_TAFCR_PC15VALUE_len EQU 1
RTC_TAFCR_PC15MODE EQU 0x00800000 ; PC15 mode
RTC_TAFCR_PC15MODE_ofs EQU 23
RTC_TAFCR_PC15MODE_len EQU 1
; RTC_ALRMASSR fields:
RTC_ALRMASSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMASSR_MASKSS_ofs EQU 24
RTC_ALRMASSR_MASKSS_len EQU 4
RTC_ALRMASSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMASSR_SS_ofs EQU 0
RTC_ALRMASSR_SS_len EQU 15
; RTC_ALRMBSSR fields:
RTC_ALRMBSSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMBSSR_MASKSS_ofs EQU 24
RTC_ALRMBSSR_MASKSS_len EQU 4
RTC_ALRMBSSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMBSSR_SS_ofs EQU 0
RTC_ALRMBSSR_SS_len EQU 15
; RTC_BKP0R fields:
RTC_BKP0R_BKP EQU 0xffffffff ; BKP
RTC_BKP0R_BKP_ofs EQU 0
RTC_BKP0R_BKP_len EQU 32
; RTC_BKP1R fields:
RTC_BKP1R_BKP EQU 0xffffffff ; BKP
RTC_BKP1R_BKP_ofs EQU 0
RTC_BKP1R_BKP_len EQU 32
; RTC_BKP2R fields:
RTC_BKP2R_BKP EQU 0xffffffff ; BKP
RTC_BKP2R_BKP_ofs EQU 0
RTC_BKP2R_BKP_len EQU 32
; RTC_BKP3R fields:
RTC_BKP3R_BKP EQU 0xffffffff ; BKP
RTC_BKP3R_BKP_ofs EQU 0
RTC_BKP3R_BKP_len EQU 32
; RTC_BKP4R fields:
RTC_BKP4R_BKP EQU 0xffffffff ; BKP
RTC_BKP4R_BKP_ofs EQU 0
RTC_BKP4R_BKP_len EQU 32
; RTC_BKP5R fields:
RTC_BKP5R_BKP EQU 0xffffffff ; BKP
RTC_BKP5R_BKP_ofs EQU 0
RTC_BKP5R_BKP_len EQU 32
; RTC_BKP6R fields:
RTC_BKP6R_BKP EQU 0xffffffff ; BKP
RTC_BKP6R_BKP_ofs EQU 0
RTC_BKP6R_BKP_len EQU 32
; RTC_BKP7R fields:
RTC_BKP7R_BKP EQU 0xffffffff ; BKP
RTC_BKP7R_BKP_ofs EQU 0
RTC_BKP7R_BKP_len EQU 32
; RTC_BKP8R fields:
RTC_BKP8R_BKP EQU 0xffffffff ; BKP
RTC_BKP8R_BKP_ofs EQU 0
RTC_BKP8R_BKP_len EQU 32
; RTC_BKP9R fields:
RTC_BKP9R_BKP EQU 0xffffffff ; BKP
RTC_BKP9R_BKP_ofs EQU 0
RTC_BKP9R_BKP_len EQU 32
; RTC_BKP10R fields:
RTC_BKP10R_BKP EQU 0xffffffff ; BKP
RTC_BKP10R_BKP_ofs EQU 0
RTC_BKP10R_BKP_len EQU 32
; RTC_BKP11R fields:
RTC_BKP11R_BKP EQU 0xffffffff ; BKP
RTC_BKP11R_BKP_ofs EQU 0
RTC_BKP11R_BKP_len EQU 32
; RTC_BKP12R fields:
RTC_BKP12R_BKP EQU 0xffffffff ; BKP
RTC_BKP12R_BKP_ofs EQU 0
RTC_BKP12R_BKP_len EQU 32
; RTC_BKP13R fields:
RTC_BKP13R_BKP EQU 0xffffffff ; BKP
RTC_BKP13R_BKP_ofs EQU 0
RTC_BKP13R_BKP_len EQU 32
; RTC_BKP14R fields:
RTC_BKP14R_BKP EQU 0xffffffff ; BKP
RTC_BKP14R_BKP_ofs EQU 0
RTC_BKP14R_BKP_len EQU 32
; RTC_BKP15R fields:
RTC_BKP15R_BKP EQU 0xffffffff ; BKP
RTC_BKP15R_BKP_ofs EQU 0
RTC_BKP15R_BKP_len EQU 32
; RTC_BKP16R fields:
RTC_BKP16R_BKP EQU 0xffffffff ; BKP
RTC_BKP16R_BKP_ofs EQU 0
RTC_BKP16R_BKP_len EQU 32
; RTC_BKP17R fields:
RTC_BKP17R_BKP EQU 0xffffffff ; BKP
RTC_BKP17R_BKP_ofs EQU 0
RTC_BKP17R_BKP_len EQU 32
; RTC_BKP18R fields:
RTC_BKP18R_BKP EQU 0xffffffff ; BKP
RTC_BKP18R_BKP_ofs EQU 0
RTC_BKP18R_BKP_len EQU 32
; RTC_BKP19R fields:
RTC_BKP19R_BKP EQU 0xffffffff ; BKP
RTC_BKP19R_BKP_ofs EQU 0
RTC_BKP19R_BKP_len EQU 32
; RTC_BKP20R fields:
RTC_BKP20R_BKP EQU 0xffffffff ; BKP
RTC_BKP20R_BKP_ofs EQU 0
RTC_BKP20R_BKP_len EQU 32
; RTC_BKP21R fields:
RTC_BKP21R_BKP EQU 0xffffffff ; BKP
RTC_BKP21R_BKP_ofs EQU 0
RTC_BKP21R_BKP_len EQU 32
; RTC_BKP22R fields:
RTC_BKP22R_BKP EQU 0xffffffff ; BKP
RTC_BKP22R_BKP_ofs EQU 0
RTC_BKP22R_BKP_len EQU 32
; RTC_BKP23R fields:
RTC_BKP23R_BKP EQU 0xffffffff ; BKP
RTC_BKP23R_BKP_ofs EQU 0
RTC_BKP23R_BKP_len EQU 32
; RTC_BKP24R fields:
RTC_BKP24R_BKP EQU 0xffffffff ; BKP
RTC_BKP24R_BKP_ofs EQU 0
RTC_BKP24R_BKP_len EQU 32
; RTC_BKP25R fields:
RTC_BKP25R_BKP EQU 0xffffffff ; BKP
RTC_BKP25R_BKP_ofs EQU 0
RTC_BKP25R_BKP_len EQU 32
; RTC_BKP26R fields:
RTC_BKP26R_BKP EQU 0xffffffff ; BKP
RTC_BKP26R_BKP_ofs EQU 0
RTC_BKP26R_BKP_len EQU 32
; RTC_BKP27R fields:
RTC_BKP27R_BKP EQU 0xffffffff ; BKP
RTC_BKP27R_BKP_ofs EQU 0
RTC_BKP27R_BKP_len EQU 32
; RTC_BKP28R fields:
RTC_BKP28R_BKP EQU 0xffffffff ; BKP
RTC_BKP28R_BKP_ofs EQU 0
RTC_BKP28R_BKP_len EQU 32
; RTC_BKP29R fields:
RTC_BKP29R_BKP EQU 0xffffffff ; BKP
RTC_BKP29R_BKP_ofs EQU 0
RTC_BKP29R_BKP_len EQU 32
; RTC_BKP30R fields:
RTC_BKP30R_BKP EQU 0xffffffff ; BKP
RTC_BKP30R_BKP_ofs EQU 0
RTC_BKP30R_BKP_len EQU 32
; RTC_BKP31R fields:
RTC_BKP31R_BKP EQU 0xffffffff ; BKP
RTC_BKP31R_BKP_ofs EQU 0
RTC_BKP31R_BKP_len EQU 32
; ---- TIM6 --------------------------------------------------
; Desc: Basic timers
; TIM6 base address:
TIM6_BASE EQU 0x40001000
; TIM6 registers:
TIM6_CR1 EQU (TIM6_BASE + 0x0) ; control register 1
TIM6_CR2 EQU (TIM6_BASE + 0x4) ; control register 2
TIM6_DIER EQU (TIM6_BASE + 0xc) ; DMA/Interrupt enable register
TIM6_SR EQU (TIM6_BASE + 0x10) ; status register
TIM6_EGR EQU (TIM6_BASE + 0x14) ; event generation register
TIM6_CNT EQU (TIM6_BASE + 0x24) ; counter
TIM6_PSC EQU (TIM6_BASE + 0x28) ; prescaler
TIM6_ARR EQU (TIM6_BASE + 0x2c) ; auto-reload register
; TIM6_CR1 fields:
TIM6_CR1_CEN EQU 0x00000001 ; Counter enable
TIM6_CR1_CEN_ofs EQU 0
TIM6_CR1_CEN_len EQU 1
TIM6_CR1_UDIS EQU 0x00000002 ; Update disable
TIM6_CR1_UDIS_ofs EQU 1
TIM6_CR1_UDIS_len EQU 1
TIM6_CR1_URS EQU 0x00000004 ; Update request source
TIM6_CR1_URS_ofs EQU 2
TIM6_CR1_URS_len EQU 1
TIM6_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM6_CR1_OPM_ofs EQU 3
TIM6_CR1_OPM_len EQU 1
TIM6_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM6_CR1_ARPE_ofs EQU 7
TIM6_CR1_ARPE_len EQU 1
TIM6_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM6_CR1_UIFREMAP_ofs EQU 11
TIM6_CR1_UIFREMAP_len EQU 1
; TIM6_CR2 fields:
TIM6_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM6_CR2_MMS_ofs EQU 4
TIM6_CR2_MMS_len EQU 3
; TIM6_DIER fields:
TIM6_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM6_DIER_UDE_ofs EQU 8
TIM6_DIER_UDE_len EQU 1
TIM6_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM6_DIER_UIE_ofs EQU 0
TIM6_DIER_UIE_len EQU 1
; TIM6_SR fields:
TIM6_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM6_SR_UIF_ofs EQU 0
TIM6_SR_UIF_len EQU 1
; TIM6_EGR fields:
TIM6_EGR_UG EQU 0x00000001 ; Update generation
TIM6_EGR_UG_ofs EQU 0
TIM6_EGR_UG_len EQU 1
; TIM6_CNT fields:
TIM6_CNT_CNT EQU 0x0000ffff ; Low counter value
TIM6_CNT_CNT_ofs EQU 0
TIM6_CNT_CNT_len EQU 16
TIM6_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM6_CNT_UIFCPY_ofs EQU 31
TIM6_CNT_UIFCPY_len EQU 1
; TIM6_PSC fields:
TIM6_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM6_PSC_PSC_ofs EQU 0
TIM6_PSC_PSC_len EQU 16
; TIM6_ARR fields:
TIM6_ARR_ARR EQU 0x0000ffff ; Low Auto-reload value
TIM6_ARR_ARR_ofs EQU 0
TIM6_ARR_ARR_len EQU 16
; ---- TIM7 --------------------------------------------------
; Desc: None
; TIM7 base address:
TIM7_BASE EQU 0x40001400
; TIM7 registers:
; ---- DAC ---------------------------------------------------
; Desc: Digital-to-analog converter
; DAC base address:
DAC_BASE EQU 0x40007400
; DAC registers:
DAC_CR EQU (DAC_BASE + 0x0) ; control register
DAC_SWTRIGR EQU (DAC_BASE + 0x4) ; software trigger register
DAC_DHR12R1 EQU (DAC_BASE + 0x8) ; channel1 12-bit right-aligned data holding register
DAC_DHR12L1 EQU (DAC_BASE + 0xc) ; channel1 12-bit left aligned data holding register
DAC_DHR8R1 EQU (DAC_BASE + 0x10) ; channel1 8-bit right aligned data holding register
DAC_DHR12R2 EQU (DAC_BASE + 0x14) ; channel2 12-bit right aligned data holding register
DAC_DHR12L2 EQU (DAC_BASE + 0x18) ; channel2 12-bit left aligned data holding register
DAC_DHR8R2 EQU (DAC_BASE + 0x1c) ; channel2 8-bit right-aligned data holding register
DAC_DHR12RD EQU (DAC_BASE + 0x20) ; Dual DAC 12-bit right-aligned data holding register
DAC_DHR12LD EQU (DAC_BASE + 0x24) ; DUAL DAC 12-bit left aligned data holding register
DAC_DHR8RD EQU (DAC_BASE + 0x28) ; DUAL DAC 8-bit right aligned data holding register
DAC_DOR1 EQU (DAC_BASE + 0x2c) ; channel1 data output register
DAC_DOR2 EQU (DAC_BASE + 0x30) ; channel2 data output register
DAC_SR EQU (DAC_BASE + 0x34) ; status register
; DAC_CR fields:
DAC_CR_DMAUDRIE2 EQU 0x20000000 ; DAC channel2 DMA underrun interrupt enable
DAC_CR_DMAUDRIE2_ofs EQU 29
DAC_CR_DMAUDRIE2_len EQU 1
DAC_CR_DMAEN2 EQU 0x10000000 ; DAC channel2 DMA enable
DAC_CR_DMAEN2_ofs EQU 28
DAC_CR_DMAEN2_len EQU 1
DAC_CR_MAMP2 EQU 0x0f000000 ; DAC channel2 mask/amplitude selector
DAC_CR_MAMP2_ofs EQU 24
DAC_CR_MAMP2_len EQU 4
DAC_CR_WAVE2 EQU 0x00c00000 ; DAC channel2 noise/triangle wave generation enable
DAC_CR_WAVE2_ofs EQU 22
DAC_CR_WAVE2_len EQU 2
DAC_CR_TSEL2 EQU 0x00380000 ; DAC channel2 trigger selection
DAC_CR_TSEL2_ofs EQU 19
DAC_CR_TSEL2_len EQU 3
DAC_CR_TEN2 EQU 0x00040000 ; DAC channel2 trigger enable
DAC_CR_TEN2_ofs EQU 18
DAC_CR_TEN2_len EQU 1
DAC_CR_BOFF2 EQU 0x00020000 ; DAC channel2 output buffer disable
DAC_CR_BOFF2_ofs EQU 17
DAC_CR_BOFF2_len EQU 1
DAC_CR_EN2 EQU 0x00010000 ; DAC channel2 enable
DAC_CR_EN2_ofs EQU 16
DAC_CR_EN2_len EQU 1
DAC_CR_DMAUDRIE1 EQU 0x00002000 ; DAC channel1 DMA Underrun Interrupt enable
DAC_CR_DMAUDRIE1_ofs EQU 13
DAC_CR_DMAUDRIE1_len EQU 1
DAC_CR_DMAEN1 EQU 0x00001000 ; DAC channel1 DMA enable
DAC_CR_DMAEN1_ofs EQU 12
DAC_CR_DMAEN1_len EQU 1
DAC_CR_MAMP1 EQU 0x00000f00 ; DAC channel1 mask/amplitude selector
DAC_CR_MAMP1_ofs EQU 8
DAC_CR_MAMP1_len EQU 4
DAC_CR_WAVE1 EQU 0x000000c0 ; DAC channel1 noise/triangle wave generation enable
DAC_CR_WAVE1_ofs EQU 6
DAC_CR_WAVE1_len EQU 2
DAC_CR_TSEL1 EQU 0x00000038 ; DAC channel1 trigger selection
DAC_CR_TSEL1_ofs EQU 3
DAC_CR_TSEL1_len EQU 3
DAC_CR_TEN1 EQU 0x00000004 ; DAC channel1 trigger enable
DAC_CR_TEN1_ofs EQU 2
DAC_CR_TEN1_len EQU 1
DAC_CR_BOFF1 EQU 0x00000002 ; DAC channel1 output buffer disable
DAC_CR_BOFF1_ofs EQU 1
DAC_CR_BOFF1_len EQU 1
DAC_CR_EN1 EQU 0x00000001 ; DAC channel1 enable
DAC_CR_EN1_ofs EQU 0
DAC_CR_EN1_len EQU 1
; DAC_SWTRIGR fields:
DAC_SWTRIGR_SWTRIG2 EQU 0x00000002 ; DAC channel2 software trigger
DAC_SWTRIGR_SWTRIG2_ofs EQU 1
DAC_SWTRIGR_SWTRIG2_len EQU 1
DAC_SWTRIGR_SWTRIG1 EQU 0x00000001 ; DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG1_ofs EQU 0
DAC_SWTRIGR_SWTRIG1_len EQU 1
; DAC_DHR12R1 fields:
DAC_DHR12R1_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12R1_DACC1DHR_ofs EQU 0
DAC_DHR12R1_DACC1DHR_len EQU 12
; DAC_DHR12L1 fields:
DAC_DHR12L1_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12L1_DACC1DHR_ofs EQU 4
DAC_DHR12L1_DACC1DHR_len EQU 12
; DAC_DHR8R1 fields:
DAC_DHR8R1_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8R1_DACC1DHR_ofs EQU 0
DAC_DHR8R1_DACC1DHR_len EQU 8
; DAC_DHR12R2 fields:
DAC_DHR12R2_DACC2DHR EQU 0x00000fff ; DAC channel2 12-bit right-aligned data
DAC_DHR12R2_DACC2DHR_ofs EQU 0
DAC_DHR12R2_DACC2DHR_len EQU 12
; DAC_DHR12L2 fields:
DAC_DHR12L2_DACC2DHR EQU 0x0000fff0 ; DAC channel2 12-bit left-aligned data
DAC_DHR12L2_DACC2DHR_ofs EQU 4
DAC_DHR12L2_DACC2DHR_len EQU 12
; DAC_DHR8R2 fields:
DAC_DHR8R2_DACC2DHR EQU 0x000000ff ; DAC channel2 8-bit right-aligned data
DAC_DHR8R2_DACC2DHR_ofs EQU 0
DAC_DHR8R2_DACC2DHR_len EQU 8
; DAC_DHR12RD fields:
DAC_DHR12RD_DACC2DHR EQU 0x0fff0000 ; DAC channel2 12-bit right-aligned data
DAC_DHR12RD_DACC2DHR_ofs EQU 16
DAC_DHR12RD_DACC2DHR_len EQU 12
DAC_DHR12RD_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12RD_DACC1DHR_ofs EQU 0
DAC_DHR12RD_DACC1DHR_len EQU 12
; DAC_DHR12LD fields:
DAC_DHR12LD_DACC2DHR EQU 0xfff00000 ; DAC channel2 12-bit left-aligned data
DAC_DHR12LD_DACC2DHR_ofs EQU 20
DAC_DHR12LD_DACC2DHR_len EQU 12
DAC_DHR12LD_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12LD_DACC1DHR_ofs EQU 4
DAC_DHR12LD_DACC1DHR_len EQU 12
; DAC_DHR8RD fields:
DAC_DHR8RD_DACC2DHR EQU 0x0000ff00 ; DAC channel2 8-bit right-aligned data
DAC_DHR8RD_DACC2DHR_ofs EQU 8
DAC_DHR8RD_DACC2DHR_len EQU 8
DAC_DHR8RD_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8RD_DACC1DHR_ofs EQU 0
DAC_DHR8RD_DACC1DHR_len EQU 8
; DAC_DOR1 fields:
DAC_DOR1_DACC1DOR EQU 0x00000fff ; DAC channel1 data output
DAC_DOR1_DACC1DOR_ofs EQU 0
DAC_DOR1_DACC1DOR_len EQU 12
; DAC_DOR2 fields:
DAC_DOR2_DACC2DOR EQU 0x00000fff ; DAC channel2 data output
DAC_DOR2_DACC2DOR_ofs EQU 0
DAC_DOR2_DACC2DOR_len EQU 12
; DAC_SR fields:
DAC_SR_DMAUDR2 EQU 0x20000000 ; DAC channel2 DMA underrun flag
DAC_SR_DMAUDR2_ofs EQU 29
DAC_SR_DMAUDR2_len EQU 1
DAC_SR_DMAUDR1 EQU 0x00002000 ; DAC channel1 DMA underrun flag
DAC_SR_DMAUDR1_ofs EQU 13
DAC_SR_DMAUDR1_len EQU 1
; ---- NVIC --------------------------------------------------
; Desc: Nested Vectored Interrupt Controller
; NVIC base address:
NVIC_BASE EQU 0xe000e000
; NVIC registers:
NVIC_ICTR EQU (NVIC_BASE + 0x4) ; Interrupt Controller Type Register
NVIC_STIR EQU (NVIC_BASE + 0xf00) ; Software Triggered Interrupt Register
NVIC_ISER0 EQU (NVIC_BASE + 0x100) ; Interrupt Set-Enable Register
NVIC_ISER1 EQU (NVIC_BASE + 0x104) ; Interrupt Set-Enable Register
NVIC_ISER2 EQU (NVIC_BASE + 0x108) ; Interrupt Set-Enable Register
NVIC_ICER0 EQU (NVIC_BASE + 0x180) ; Interrupt Clear-Enable Register
NVIC_ICER1 EQU (NVIC_BASE + 0x184) ; Interrupt Clear-Enable Register
NVIC_ICER2 EQU (NVIC_BASE + 0x188) ; Interrupt Clear-Enable Register
NVIC_ISPR0 EQU (NVIC_BASE + 0x200) ; Interrupt Set-Pending Register
NVIC_ISPR1 EQU (NVIC_BASE + 0x204) ; Interrupt Set-Pending Register
NVIC_ISPR2 EQU (NVIC_BASE + 0x208) ; Interrupt Set-Pending Register
NVIC_ICPR0 EQU (NVIC_BASE + 0x280) ; Interrupt Clear-Pending Register
NVIC_ICPR1 EQU (NVIC_BASE + 0x284) ; Interrupt Clear-Pending Register
NVIC_ICPR2 EQU (NVIC_BASE + 0x288) ; Interrupt Clear-Pending Register
NVIC_IABR0 EQU (NVIC_BASE + 0x300) ; Interrupt Active Bit Register
NVIC_IABR1 EQU (NVIC_BASE + 0x304) ; Interrupt Active Bit Register
NVIC_IABR2 EQU (NVIC_BASE + 0x308) ; Interrupt Active Bit Register
NVIC_IPR0 EQU (NVIC_BASE + 0x400) ; Interrupt Priority Register
NVIC_IPR1 EQU (NVIC_BASE + 0x404) ; Interrupt Priority Register
NVIC_IPR2 EQU (NVIC_BASE + 0x408) ; Interrupt Priority Register
NVIC_IPR3 EQU (NVIC_BASE + 0x40c) ; Interrupt Priority Register
NVIC_IPR4 EQU (NVIC_BASE + 0x410) ; Interrupt Priority Register
NVIC_IPR5 EQU (NVIC_BASE + 0x414) ; Interrupt Priority Register
NVIC_IPR6 EQU (NVIC_BASE + 0x418) ; Interrupt Priority Register
NVIC_IPR7 EQU (NVIC_BASE + 0x41c) ; Interrupt Priority Register
NVIC_IPR8 EQU (NVIC_BASE + 0x420) ; Interrupt Priority Register
NVIC_IPR9 EQU (NVIC_BASE + 0x424) ; Interrupt Priority Register
NVIC_IPR10 EQU (NVIC_BASE + 0x428) ; Interrupt Priority Register
NVIC_IPR11 EQU (NVIC_BASE + 0x42c) ; Interrupt Priority Register
NVIC_IPR12 EQU (NVIC_BASE + 0x430) ; Interrupt Priority Register
NVIC_IPR13 EQU (NVIC_BASE + 0x434) ; Interrupt Priority Register
NVIC_IPR14 EQU (NVIC_BASE + 0x438) ; Interrupt Priority Register
NVIC_IPR15 EQU (NVIC_BASE + 0x43c) ; Interrupt Priority Register
NVIC_IPR16 EQU (NVIC_BASE + 0x440) ; Interrupt Priority Register
NVIC_IPR17 EQU (NVIC_BASE + 0x444) ; Interrupt Priority Register
NVIC_IPR18 EQU (NVIC_BASE + 0x448) ; Interrupt Priority Register
NVIC_IPR19 EQU (NVIC_BASE + 0x44c) ; Interrupt Priority Register
NVIC_IPR20 EQU (NVIC_BASE + 0x450) ; Interrupt Priority Register
; NVIC_ICTR fields:
NVIC_ICTR_INTLINESNUM EQU 0x0000000f ; Total number of interrupt lines in groups
NVIC_ICTR_INTLINESNUM_ofs EQU 0
NVIC_ICTR_INTLINESNUM_len EQU 4
; NVIC_STIR fields:
NVIC_STIR_INTID EQU 0x000001ff ; interrupt to be triggered
NVIC_STIR_INTID_ofs EQU 0
NVIC_STIR_INTID_len EQU 9
; NVIC_ISERx fields:
NVIC_ISERx_SETENA EQU 0xffffffff ; SETENA
NVIC_ISERx_SETENA_ofs EQU 0
NVIC_ISERx_SETENA_len EQU 32
; NVIC_ICERx fields:
NVIC_ICERx_CLRENA EQU 0xffffffff ; CLRENA
NVIC_ICERx_CLRENA_ofs EQU 0
NVIC_ICERx_CLRENA_len EQU 32
; NVIC_ISPR0 fields:
NVIC_ISPRx_SETPEND EQU 0xffffffff ; SETPEND
NVIC_ISPRx_SETPEND_ofs EQU 0
NVIC_ISPRx_SETPEND_len EQU 32
; NVIC_ICPRx fields:
NVIC_ICPRx_CLRPEND EQU 0xffffffff ; CLRPEND
NVIC_ICPRx_CLRPEND_ofs EQU 0
NVIC_ICPRx_CLRPEND_len EQU 32
; NVIC_IABRx fields:
NVIC_IABRx_ACTIVE EQU 0xffffffff ; ACTIVE
NVIC_IABRx_ACTIVE_ofs EQU 0
NVIC_IABRx_ACTIVE_len EQU 32
; NVIC_IPRx fields:
NVIC_IPRx_IPR_N0 EQU 0x000000ff ; IPR_N0
NVIC_IPRx_IPR_N0_ofs EQU 0
NVIC_IPRx_IPR_N0_len EQU 8
NVIC_IPRx_IPR_N1 EQU 0x0000ff00 ; IPR_N1
NVIC_IPRx_IPR_N1_ofs EQU 8
NVIC_IPRx_IPR_N1_len EQU 8
NVIC_IPRx_IPR_N2 EQU 0x00ff0000 ; IPR_N2
NVIC_IPRx_IPR_N2_ofs EQU 16
NVIC_IPRx_IPR_N2_len EQU 8
NVIC_IPRx_IPR_N3 EQU 0xff000000 ; IPR_N3
NVIC_IPRx_IPR_N3_ofs EQU 24
NVIC_IPRx_IPR_N3_len EQU 8
; ---- FPU ---------------------------------------------------
; Desc: Floting point unit
; FPU base address:
FPU_BASE EQU 0xe000ed88
; FPU registers:
FPU_CPACR EQU (FPU_BASE + 0x0) ; Coprocessor Access Control Register
FPU_FPCCR EQU (FPU_BASE + 0x1ac) ; FP Context Control Register
FPU_FPCAR EQU (FPU_BASE + 0x1b0) ; FP Context Address Register
FPU_FPDSCR EQU (FPU_BASE + 0x1b4) ; FP Default Status Control Register
FPU_MVFR0 EQU (FPU_BASE + 0x1b8) ; Media and VFP Feature Register 0
FPU_MVFR1 EQU (FPU_BASE + 0x1bc) ; Media and VFP Feature Register 1
; FPU_CPACR fields:
FPU_CPACR_CP0 EQU 0x00000001 ; Access privileges for coprocessor 0
FPU_CPACR_CP0_ofs EQU 0
FPU_CPACR_CP0_len EQU 1
FPU_CPACR_CP1 EQU 0x00000004 ; Access privileges for coprocessor 1
FPU_CPACR_CP1_ofs EQU 2
FPU_CPACR_CP1_len EQU 1
FPU_CPACR_CP2 EQU 0x00000010 ; Access privileges for coprocessor 2
FPU_CPACR_CP2_ofs EQU 4
FPU_CPACR_CP2_len EQU 1
FPU_CPACR_CP3 EQU 0x00000040 ; Access privileges for coprocessor 3
FPU_CPACR_CP3_ofs EQU 6
FPU_CPACR_CP3_len EQU 1
FPU_CPACR_CP4 EQU 0x00000100 ; Access privileges for coprocessor 4
FPU_CPACR_CP4_ofs EQU 8
FPU_CPACR_CP4_len EQU 1
FPU_CPACR_CP5 EQU 0x00000400 ; Access privileges for coprocessor 5
FPU_CPACR_CP5_ofs EQU 10
FPU_CPACR_CP5_len EQU 1
FPU_CPACR_CP6 EQU 0x00003000 ; Access privileges for coprocessor 6
FPU_CPACR_CP6_ofs EQU 12
FPU_CPACR_CP6_len EQU 2
FPU_CPACR_CP7 EQU 0x00004000 ; Access privileges for coprocessor 7
FPU_CPACR_CP7_ofs EQU 14
FPU_CPACR_CP7_len EQU 1
FPU_CPACR_CP10 EQU 0x00100000 ; Access privileges for coprocessor 10
FPU_CPACR_CP10_ofs EQU 20
FPU_CPACR_CP10_len EQU 1
FPU_CPACR_CP11 EQU 0x00400000 ; Access privileges for coprocessor 11
FPU_CPACR_CP11_ofs EQU 22
FPU_CPACR_CP11_len EQU 1
; FPU_FPCCR fields:
FPU_FPCCR_LSPACT EQU 0x00000001 ; LSPACT
FPU_FPCCR_LSPACT_ofs EQU 0
FPU_FPCCR_LSPACT_len EQU 1
FPU_FPCCR_USER EQU 0x00000002 ; USER
FPU_FPCCR_USER_ofs EQU 1
FPU_FPCCR_USER_len EQU 1
FPU_FPCCR_THREAD EQU 0x00000008 ; THREAD
FPU_FPCCR_THREAD_ofs EQU 3
FPU_FPCCR_THREAD_len EQU 1
FPU_FPCCR_HFRDY EQU 0x00000010 ; HFRDY
FPU_FPCCR_HFRDY_ofs EQU 4
FPU_FPCCR_HFRDY_len EQU 1
FPU_FPCCR_MMRDY EQU 0x00000020 ; MMRDY
FPU_FPCCR_MMRDY_ofs EQU 5
FPU_FPCCR_MMRDY_len EQU 1
FPU_FPCCR_BFRDY EQU 0x00000040 ; BFRDY
FPU_FPCCR_BFRDY_ofs EQU 6
FPU_FPCCR_BFRDY_len EQU 1
FPU_FPCCR_MONRDY EQU 0x00000100 ; MONRDY
FPU_FPCCR_MONRDY_ofs EQU 8
FPU_FPCCR_MONRDY_len EQU 1
FPU_FPCCR_LSPEN EQU 0x40000000 ; LSPEN
FPU_FPCCR_LSPEN_ofs EQU 30
FPU_FPCCR_LSPEN_len EQU 1
FPU_FPCCR_ASPEN EQU 0x80000000 ; ASPEN
FPU_FPCCR_ASPEN_ofs EQU 31
FPU_FPCCR_ASPEN_len EQU 1
; FPU_FPCAR fields:
FPU_FPCAR_ADDRESS EQU 0xfffffff8 ; ADDRESS
FPU_FPCAR_ADDRESS_ofs EQU 3
FPU_FPCAR_ADDRESS_len EQU 29
; FPU_FPDSCR fields:
FPU_FPDSCR_RMode EQU 0x00c00000 ; RMode
FPU_FPDSCR_RMode_ofs EQU 22
FPU_FPDSCR_RMode_len EQU 2
FPU_FPDSCR_FZ EQU 0x01000000 ; FZ
FPU_FPDSCR_FZ_ofs EQU 24
FPU_FPDSCR_FZ_len EQU 1
FPU_FPDSCR_DN EQU 0x02000000 ; DN
FPU_FPDSCR_DN_ofs EQU 25
FPU_FPDSCR_DN_len EQU 1
FPU_FPDSCR_AHP EQU 0x04000000 ; AHP
FPU_FPDSCR_AHP_ofs EQU 26
FPU_FPDSCR_AHP_len EQU 1
; FPU_MVFR0 fields:
FPU_MVFR0_A_SIMD EQU 0x0000000f ; A_SIMD registers
FPU_MVFR0_A_SIMD_ofs EQU 0
FPU_MVFR0_A_SIMD_len EQU 4
FPU_MVFR0_Single_precision EQU 0x000000f0 ; Single_precision
FPU_MVFR0_Single_precision_ofs EQU 4
FPU_MVFR0_Single_precision_len EQU 4
FPU_MVFR0_Double_precision EQU 0x00000f00 ; Double_precision
FPU_MVFR0_Double_precision_ofs EQU 8
FPU_MVFR0_Double_precision_len EQU 4
FPU_MVFR0_FP_exception_trapping EQU 0x0000f000 ; FP exception trapping
FPU_MVFR0_FP_exception_trapping_ofs EQU 12
FPU_MVFR0_FP_exception_trapping_len EQU 4
FPU_MVFR0_Divide EQU 0x000f0000 ; Divide
FPU_MVFR0_Divide_ofs EQU 16
FPU_MVFR0_Divide_len EQU 4
FPU_MVFR0_Square_root EQU 0x00f00000 ; Square root
FPU_MVFR0_Square_root_ofs EQU 20
FPU_MVFR0_Square_root_len EQU 4
FPU_MVFR0_Short_vectors EQU 0x0f000000 ; Short vectors
FPU_MVFR0_Short_vectors_ofs EQU 24
FPU_MVFR0_Short_vectors_len EQU 4
FPU_MVFR0_FP_rounding_modes EQU 0xf0000000 ; FP rounding modes
FPU_MVFR0_FP_rounding_modes_ofs EQU 28
FPU_MVFR0_FP_rounding_modes_len EQU 4
; FPU_MVFR1 fields:
FPU_MVFR1_FtZ_mode EQU 0x0000000f ; FtZ mode
FPU_MVFR1_FtZ_mode_ofs EQU 0
FPU_MVFR1_FtZ_mode_len EQU 4
FPU_MVFR1_D_NaN_mode EQU 0x000000f0 ; D_NaN mode
FPU_MVFR1_D_NaN_mode_ofs EQU 4
FPU_MVFR1_D_NaN_mode_len EQU 4
FPU_MVFR1_FP_HPFP EQU 0x0f000000 ; FP HPFP
FPU_MVFR1_FP_HPFP_ofs EQU 24
FPU_MVFR1_FP_HPFP_len EQU 4
FPU_MVFR1_FP_fused_MAC EQU 0xf0000000 ; FP fused MAC
FPU_MVFR1_FP_fused_MAC_ofs EQU 28
FPU_MVFR1_FP_fused_MAC_len EQU 4
; ---- DBGMCU ------------------------------------------------
; Desc: Debug support
; DBGMCU base address:
DBGMCU_BASE EQU 0xe0042000
; DBGMCU registers:
DBGMCU_IDCODE EQU (DBGMCU_BASE + 0x0) ; MCU Device ID Code Register
DBGMCU_CR EQU (DBGMCU_BASE + 0x4) ; Debug MCU Configuration Register
DBGMCU_APB1FZ EQU (DBGMCU_BASE + 0x8) ; APB Low Freeze Register
DBGMCU_APB2FZ EQU (DBGMCU_BASE + 0xc) ; APB High Freeze Register
; DBGMCU_IDCODE fields:
DBGMCU_IDCODE_DEV_ID EQU 0x00000fff ; Device Identifier
DBGMCU_IDCODE_DEV_ID_ofs EQU 0
DBGMCU_IDCODE_DEV_ID_len EQU 12
DBGMCU_IDCODE_REV_ID EQU 0xffff0000 ; Revision Identifier
DBGMCU_IDCODE_REV_ID_ofs EQU 16
DBGMCU_IDCODE_REV_ID_len EQU 16
; DBGMCU_CR fields:
DBGMCU_CR_DBG_SLEEP EQU 0x00000001 ; Debug Sleep mode
DBGMCU_CR_DBG_SLEEP_ofs EQU 0
DBGMCU_CR_DBG_SLEEP_len EQU 1
DBGMCU_CR_DBG_STOP EQU 0x00000002 ; Debug Stop Mode
DBGMCU_CR_DBG_STOP_ofs EQU 1
DBGMCU_CR_DBG_STOP_len EQU 1
DBGMCU_CR_DBG_STANDBY EQU 0x00000004 ; Debug Standby Mode
DBGMCU_CR_DBG_STANDBY_ofs EQU 2
DBGMCU_CR_DBG_STANDBY_len EQU 1
DBGMCU_CR_TRACE_IOEN EQU 0x00000020 ; Trace pin assignment control
DBGMCU_CR_TRACE_IOEN_ofs EQU 5
DBGMCU_CR_TRACE_IOEN_len EQU 1
DBGMCU_CR_TRACE_MODE EQU 0x000000c0 ; Trace pin assignment control
DBGMCU_CR_TRACE_MODE_ofs EQU 6
DBGMCU_CR_TRACE_MODE_len EQU 2
; DBGMCU_APB1FZ fields:
DBGMCU_APB1FZ_DBG_TIM2_STOP EQU 0x00000001 ; Debug Timer 2 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM2_STOP_ofs EQU 0
DBGMCU_APB1FZ_DBG_TIM2_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP EQU 0x00000002 ; Debug Timer 3 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM3_STOP_ofs EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM4_STOP EQU 0x00000004 ; Debug Timer 4 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM4_STOP_ofs EQU 2
DBGMCU_APB1FZ_DBG_TIM4_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM5_STOP EQU 0x00000008 ; Debug Timer 5 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM5_STOP_ofs EQU 3
DBGMCU_APB1FZ_DBG_TIM5_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM6_STOP EQU 0x00000010 ; Debug Timer 6 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM6_STOP_ofs EQU 4
DBGMCU_APB1FZ_DBG_TIM6_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM7_STOP EQU 0x00000020 ; Debug Timer 7 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM7_STOP_ofs EQU 5
DBGMCU_APB1FZ_DBG_TIM7_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM12_STOP EQU 0x00000040 ; Debug Timer 12 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM12_STOP_ofs EQU 6
DBGMCU_APB1FZ_DBG_TIM12_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM13_STOP EQU 0x00000080 ; Debug Timer 13 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM13_STOP_ofs EQU 7
DBGMCU_APB1FZ_DBG_TIM13_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIMER14_STOP EQU 0x00000100 ; Debug Timer 14 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIMER14_STOP_ofs EQU 8
DBGMCU_APB1FZ_DBG_TIMER14_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM18_STOP EQU 0x00000200 ; Debug Timer 18 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM18_STOP_ofs EQU 9
DBGMCU_APB1FZ_DBG_TIM18_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_RTC_STOP EQU 0x00000400 ; Debug RTC stopped when Core is halted
DBGMCU_APB1FZ_DBG_RTC_STOP_ofs EQU 10
DBGMCU_APB1FZ_DBG_RTC_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_WWDG_STOP EQU 0x00000800 ; Debug Window Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_WWDG_STOP_ofs EQU 11
DBGMCU_APB1FZ_DBG_WWDG_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_IWDG_STOP EQU 0x00001000 ; Debug Independent Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_IWDG_STOP_ofs EQU 12
DBGMCU_APB1FZ_DBG_IWDG_STOP_len EQU 1
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT EQU 0x00200000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_ofs EQU 21
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT EQU 0x00400000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_ofs EQU 22
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_DBG_CAN_STOP EQU 0x02000000 ; Debug CAN stopped when core is halted
DBGMCU_APB1FZ_DBG_CAN_STOP_ofs EQU 25
DBGMCU_APB1FZ_DBG_CAN_STOP_len EQU 1
; DBGMCU_APB2FZ fields:
DBGMCU_APB2FZ_DBG_TIM15_STOP EQU 0x00000004 ; Debug Timer 15 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM15_STOP_ofs EQU 2
DBGMCU_APB2FZ_DBG_TIM15_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM16_STOP EQU 0x00000008 ; Debug Timer 16 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM16_STOP_ofs EQU 3
DBGMCU_APB2FZ_DBG_TIM16_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM17_STO EQU 0x00000010 ; Debug Timer 17 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM17_STO_ofs EQU 4
DBGMCU_APB2FZ_DBG_TIM17_STO_len EQU 1
DBGMCU_APB2FZ_DBG_TIM19_STOP EQU 0x00000020 ; Debug Timer 19 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM19_STOP_ofs EQU 5
DBGMCU_APB2FZ_DBG_TIM19_STOP_len EQU 1
; ---- TIM1 --------------------------------------------------
; Desc: Advanced timer
; TIM1 base address:
TIM1_BASE EQU 0x40012c00
; TIM1 registers:
TIM1_CR1 EQU (TIM1_BASE + 0x0) ; control register 1
TIM1_CR2 EQU (TIM1_BASE + 0x4) ; control register 2
TIM1_SMCR EQU (TIM1_BASE + 0x8) ; slave mode control register
TIM1_DIER EQU (TIM1_BASE + 0xc) ; DMA/Interrupt enable register
TIM1_SR EQU (TIM1_BASE + 0x10) ; status register
TIM1_EGR EQU (TIM1_BASE + 0x14) ; event generation register
TIM1_CCMR1_Output EQU (TIM1_BASE + 0x18) ; capture/compare mode register (output mode)
TIM1_CCMR1_Input EQU (TIM1_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM1_CCMR2_Output EQU (TIM1_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM1_CCMR2_Input EQU (TIM1_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM1_CCER EQU (TIM1_BASE + 0x20) ; capture/compare enable register
TIM1_CNT EQU (TIM1_BASE + 0x24) ; counter
TIM1_PSC EQU (TIM1_BASE + 0x28) ; prescaler
TIM1_ARR EQU (TIM1_BASE + 0x2c) ; auto-reload register
TIM1_RCR EQU (TIM1_BASE + 0x30) ; repetition counter register
TIM1_CCR1 EQU (TIM1_BASE + 0x34) ; capture/compare register 1
TIM1_CCR2 EQU (TIM1_BASE + 0x38) ; capture/compare register 2
TIM1_CCR3 EQU (TIM1_BASE + 0x3c) ; capture/compare register 3
TIM1_CCR4 EQU (TIM1_BASE + 0x40) ; capture/compare register 4
TIM1_BDTR EQU (TIM1_BASE + 0x44) ; break and dead-time register
TIM1_DCR EQU (TIM1_BASE + 0x48) ; DMA control register
TIM1_DMAR EQU (TIM1_BASE + 0x4c) ; DMA address for full transfer
TIM1_CCMR3_Output EQU (TIM1_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM1_CCR5 EQU (TIM1_BASE + 0x58) ; capture/compare register 5
TIM1_CCR6 EQU (TIM1_BASE + 0x5c) ; capture/compare register 6
TIM1_OR EQU (TIM1_BASE + 0x60) ; option registers
; TIM1_CR1 fields:
TIM1_CR1_CEN EQU 0x00000001 ; Counter enable
TIM1_CR1_CEN_ofs EQU 0
TIM1_CR1_CEN_len EQU 1
TIM1_CR1_UDIS EQU 0x00000002 ; Update disable
TIM1_CR1_UDIS_ofs EQU 1
TIM1_CR1_UDIS_len EQU 1
TIM1_CR1_URS EQU 0x00000004 ; Update request source
TIM1_CR1_URS_ofs EQU 2
TIM1_CR1_URS_len EQU 1
TIM1_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM1_CR1_OPM_ofs EQU 3
TIM1_CR1_OPM_len EQU 1
TIM1_CR1_DIR EQU 0x00000010 ; Direction
TIM1_CR1_DIR_ofs EQU 4
TIM1_CR1_DIR_len EQU 1
TIM1_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM1_CR1_CMS_ofs EQU 5
TIM1_CR1_CMS_len EQU 2
TIM1_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM1_CR1_ARPE_ofs EQU 7
TIM1_CR1_ARPE_len EQU 1
TIM1_CR1_CKD EQU 0x00000300 ; Clock division
TIM1_CR1_CKD_ofs EQU 8
TIM1_CR1_CKD_len EQU 2
TIM1_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM1_CR1_UIFREMAP_ofs EQU 11
TIM1_CR1_UIFREMAP_len EQU 1
; TIM1_CR2 fields:
TIM1_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM1_CR2_CCPC_ofs EQU 0
TIM1_CR2_CCPC_len EQU 1
TIM1_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM1_CR2_CCUS_ofs EQU 2
TIM1_CR2_CCUS_len EQU 1
TIM1_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM1_CR2_CCDS_ofs EQU 3
TIM1_CR2_CCDS_len EQU 1
TIM1_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM1_CR2_MMS_ofs EQU 4
TIM1_CR2_MMS_len EQU 3
TIM1_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM1_CR2_TI1S_ofs EQU 7
TIM1_CR2_TI1S_len EQU 1
TIM1_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM1_CR2_OIS1_ofs EQU 8
TIM1_CR2_OIS1_len EQU 1
TIM1_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM1_CR2_OIS1N_ofs EQU 9
TIM1_CR2_OIS1N_len EQU 1
TIM1_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM1_CR2_OIS2_ofs EQU 10
TIM1_CR2_OIS2_len EQU 1
TIM1_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM1_CR2_OIS2N_ofs EQU 11
TIM1_CR2_OIS2N_len EQU 1
TIM1_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM1_CR2_OIS3_ofs EQU 12
TIM1_CR2_OIS3_len EQU 1
TIM1_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM1_CR2_OIS3N_ofs EQU 13
TIM1_CR2_OIS3N_len EQU 1
TIM1_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM1_CR2_OIS4_ofs EQU 14
TIM1_CR2_OIS4_len EQU 1
TIM1_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM1_CR2_OIS5_ofs EQU 16
TIM1_CR2_OIS5_len EQU 1
TIM1_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM1_CR2_OIS6_ofs EQU 18
TIM1_CR2_OIS6_len EQU 1
TIM1_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM1_CR2_MMS2_ofs EQU 20
TIM1_CR2_MMS2_len EQU 4
; TIM1_SMCR fields:
TIM1_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM1_SMCR_SMS_ofs EQU 0
TIM1_SMCR_SMS_len EQU 3
TIM1_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM1_SMCR_OCCS_ofs EQU 3
TIM1_SMCR_OCCS_len EQU 1
TIM1_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM1_SMCR_TS_ofs EQU 4
TIM1_SMCR_TS_len EQU 3
TIM1_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM1_SMCR_MSM_ofs EQU 7
TIM1_SMCR_MSM_len EQU 1
TIM1_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM1_SMCR_ETF_ofs EQU 8
TIM1_SMCR_ETF_len EQU 4
TIM1_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM1_SMCR_ETPS_ofs EQU 12
TIM1_SMCR_ETPS_len EQU 2
TIM1_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM1_SMCR_ECE_ofs EQU 14
TIM1_SMCR_ECE_len EQU 1
TIM1_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM1_SMCR_ETP_ofs EQU 15
TIM1_SMCR_ETP_len EQU 1
TIM1_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM1_SMCR_SMS3_ofs EQU 16
TIM1_SMCR_SMS3_len EQU 1
; TIM1_DIER fields:
TIM1_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM1_DIER_TDE_ofs EQU 14
TIM1_DIER_TDE_len EQU 1
TIM1_DIER_COMDE EQU 0x00002000 ; Reserved
TIM1_DIER_COMDE_ofs EQU 13
TIM1_DIER_COMDE_len EQU 1
TIM1_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM1_DIER_CC4DE_ofs EQU 12
TIM1_DIER_CC4DE_len EQU 1
TIM1_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM1_DIER_CC3DE_ofs EQU 11
TIM1_DIER_CC3DE_len EQU 1
TIM1_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM1_DIER_CC2DE_ofs EQU 10
TIM1_DIER_CC2DE_len EQU 1
TIM1_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM1_DIER_CC1DE_ofs EQU 9
TIM1_DIER_CC1DE_len EQU 1
TIM1_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM1_DIER_UDE_ofs EQU 8
TIM1_DIER_UDE_len EQU 1
TIM1_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM1_DIER_BIE_ofs EQU 7
TIM1_DIER_BIE_len EQU 1
TIM1_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM1_DIER_TIE_ofs EQU 6
TIM1_DIER_TIE_len EQU 1
TIM1_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM1_DIER_COMIE_ofs EQU 5
TIM1_DIER_COMIE_len EQU 1
TIM1_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM1_DIER_CC4IE_ofs EQU 4
TIM1_DIER_CC4IE_len EQU 1
TIM1_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM1_DIER_CC3IE_ofs EQU 3
TIM1_DIER_CC3IE_len EQU 1
TIM1_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM1_DIER_CC2IE_ofs EQU 2
TIM1_DIER_CC2IE_len EQU 1
TIM1_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM1_DIER_CC1IE_ofs EQU 1
TIM1_DIER_CC1IE_len EQU 1
TIM1_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM1_DIER_UIE_ofs EQU 0
TIM1_DIER_UIE_len EQU 1
; TIM1_SR fields:
TIM1_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM1_SR_UIF_ofs EQU 0
TIM1_SR_UIF_len EQU 1
TIM1_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM1_SR_CC1IF_ofs EQU 1
TIM1_SR_CC1IF_len EQU 1
TIM1_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM1_SR_CC2IF_ofs EQU 2
TIM1_SR_CC2IF_len EQU 1
TIM1_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM1_SR_CC3IF_ofs EQU 3
TIM1_SR_CC3IF_len EQU 1
TIM1_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM1_SR_CC4IF_ofs EQU 4
TIM1_SR_CC4IF_len EQU 1
TIM1_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM1_SR_COMIF_ofs EQU 5
TIM1_SR_COMIF_len EQU 1
TIM1_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM1_SR_TIF_ofs EQU 6
TIM1_SR_TIF_len EQU 1
TIM1_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM1_SR_BIF_ofs EQU 7
TIM1_SR_BIF_len EQU 1
TIM1_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM1_SR_B2IF_ofs EQU 8
TIM1_SR_B2IF_len EQU 1
TIM1_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM1_SR_CC1OF_ofs EQU 9
TIM1_SR_CC1OF_len EQU 1
TIM1_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM1_SR_CC2OF_ofs EQU 10
TIM1_SR_CC2OF_len EQU 1
TIM1_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM1_SR_CC3OF_ofs EQU 11
TIM1_SR_CC3OF_len EQU 1
TIM1_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM1_SR_CC4OF_ofs EQU 12
TIM1_SR_CC4OF_len EQU 1
TIM1_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM1_SR_C5IF_ofs EQU 16
TIM1_SR_C5IF_len EQU 1
TIM1_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM1_SR_C6IF_ofs EQU 17
TIM1_SR_C6IF_len EQU 1
; TIM1_EGR fields:
TIM1_EGR_UG EQU 0x00000001 ; Update generation
TIM1_EGR_UG_ofs EQU 0
TIM1_EGR_UG_len EQU 1
TIM1_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM1_EGR_CC1G_ofs EQU 1
TIM1_EGR_CC1G_len EQU 1
TIM1_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM1_EGR_CC2G_ofs EQU 2
TIM1_EGR_CC2G_len EQU 1
TIM1_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM1_EGR_CC3G_ofs EQU 3
TIM1_EGR_CC3G_len EQU 1
TIM1_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM1_EGR_CC4G_ofs EQU 4
TIM1_EGR_CC4G_len EQU 1
TIM1_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM1_EGR_COMG_ofs EQU 5
TIM1_EGR_COMG_len EQU 1
TIM1_EGR_TG EQU 0x00000040 ; Trigger generation
TIM1_EGR_TG_ofs EQU 6
TIM1_EGR_TG_len EQU 1
TIM1_EGR_BG EQU 0x00000080 ; Break generation
TIM1_EGR_BG_ofs EQU 7
TIM1_EGR_BG_len EQU 1
TIM1_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM1_EGR_B2G_ofs EQU 8
TIM1_EGR_B2G_len EQU 1
; TIM1_CCMR1_Output fields:
TIM1_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM1_CCMR1_Output_OC2CE_ofs EQU 15
TIM1_CCMR1_Output_OC2CE_len EQU 1
TIM1_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM1_CCMR1_Output_OC2M_ofs EQU 12
TIM1_CCMR1_Output_OC2M_len EQU 3
TIM1_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM1_CCMR1_Output_OC2PE_ofs EQU 11
TIM1_CCMR1_Output_OC2PE_len EQU 1
TIM1_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM1_CCMR1_Output_OC2FE_ofs EQU 10
TIM1_CCMR1_Output_OC2FE_len EQU 1
TIM1_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Output_CC2S_ofs EQU 8
TIM1_CCMR1_Output_CC2S_len EQU 2
TIM1_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM1_CCMR1_Output_OC1CE_ofs EQU 7
TIM1_CCMR1_Output_OC1CE_len EQU 1
TIM1_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM1_CCMR1_Output_OC1M_ofs EQU 4
TIM1_CCMR1_Output_OC1M_len EQU 3
TIM1_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM1_CCMR1_Output_OC1PE_ofs EQU 3
TIM1_CCMR1_Output_OC1PE_len EQU 1
TIM1_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM1_CCMR1_Output_OC1FE_ofs EQU 2
TIM1_CCMR1_Output_OC1FE_len EQU 1
TIM1_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Output_CC1S_ofs EQU 0
TIM1_CCMR1_Output_CC1S_len EQU 2
TIM1_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM1_CCMR1_Output_OC1M_3_ofs EQU 16
TIM1_CCMR1_Output_OC1M_3_len EQU 1
TIM1_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM1_CCMR1_Output_OC2M_3_ofs EQU 24
TIM1_CCMR1_Output_OC2M_3_len EQU 1
; TIM1_CCMR1_Input fields:
TIM1_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM1_CCMR1_Input_IC2F_ofs EQU 12
TIM1_CCMR1_Input_IC2F_len EQU 4
TIM1_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM1_CCMR1_Input_IC2PCS_ofs EQU 10
TIM1_CCMR1_Input_IC2PCS_len EQU 2
TIM1_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Input_CC2S_ofs EQU 8
TIM1_CCMR1_Input_CC2S_len EQU 2
TIM1_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM1_CCMR1_Input_IC1F_ofs EQU 4
TIM1_CCMR1_Input_IC1F_len EQU 4
TIM1_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM1_CCMR1_Input_IC1PCS_ofs EQU 2
TIM1_CCMR1_Input_IC1PCS_len EQU 2
TIM1_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Input_CC1S_ofs EQU 0
TIM1_CCMR1_Input_CC1S_len EQU 2
; TIM1_CCMR2_Output fields:
TIM1_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM1_CCMR2_Output_OC4CE_ofs EQU 15
TIM1_CCMR2_Output_OC4CE_len EQU 1
TIM1_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM1_CCMR2_Output_OC4M_ofs EQU 12
TIM1_CCMR2_Output_OC4M_len EQU 3
TIM1_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM1_CCMR2_Output_OC4PE_ofs EQU 11
TIM1_CCMR2_Output_OC4PE_len EQU 1
TIM1_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM1_CCMR2_Output_OC4FE_ofs EQU 10
TIM1_CCMR2_Output_OC4FE_len EQU 1
TIM1_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Output_CC4S_ofs EQU 8
TIM1_CCMR2_Output_CC4S_len EQU 2
TIM1_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM1_CCMR2_Output_OC3CE_ofs EQU 7
TIM1_CCMR2_Output_OC3CE_len EQU 1
TIM1_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM1_CCMR2_Output_OC3M_ofs EQU 4
TIM1_CCMR2_Output_OC3M_len EQU 3
TIM1_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM1_CCMR2_Output_OC3PE_ofs EQU 3
TIM1_CCMR2_Output_OC3PE_len EQU 1
TIM1_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM1_CCMR2_Output_OC3FE_ofs EQU 2
TIM1_CCMR2_Output_OC3FE_len EQU 1
TIM1_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM1_CCMR2_Output_CC3S_ofs EQU 0
TIM1_CCMR2_Output_CC3S_len EQU 2
TIM1_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM1_CCMR2_Output_OC3M_3_ofs EQU 16
TIM1_CCMR2_Output_OC3M_3_len EQU 1
TIM1_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM1_CCMR2_Output_OC4M_3_ofs EQU 24
TIM1_CCMR2_Output_OC4M_3_len EQU 1
; TIM1_CCMR2_Input fields:
TIM1_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM1_CCMR2_Input_IC4F_ofs EQU 12
TIM1_CCMR2_Input_IC4F_len EQU 4
TIM1_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM1_CCMR2_Input_IC4PSC_ofs EQU 10
TIM1_CCMR2_Input_IC4PSC_len EQU 2
TIM1_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Input_CC4S_ofs EQU 8
TIM1_CCMR2_Input_CC4S_len EQU 2
TIM1_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM1_CCMR2_Input_IC3F_ofs EQU 4
TIM1_CCMR2_Input_IC3F_len EQU 4
TIM1_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM1_CCMR2_Input_IC3PSC_ofs EQU 2
TIM1_CCMR2_Input_IC3PSC_len EQU 2
TIM1_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM1_CCMR2_Input_CC3S_ofs EQU 0
TIM1_CCMR2_Input_CC3S_len EQU 2
; TIM1_CCER fields:
TIM1_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM1_CCER_CC1E_ofs EQU 0
TIM1_CCER_CC1E_len EQU 1
TIM1_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1P_ofs EQU 1
TIM1_CCER_CC1P_len EQU 1
TIM1_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM1_CCER_CC1NE_ofs EQU 2
TIM1_CCER_CC1NE_len EQU 1
TIM1_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1NP_ofs EQU 3
TIM1_CCER_CC1NP_len EQU 1
TIM1_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM1_CCER_CC2E_ofs EQU 4
TIM1_CCER_CC2E_len EQU 1
TIM1_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2P_ofs EQU 5
TIM1_CCER_CC2P_len EQU 1
TIM1_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM1_CCER_CC2NE_ofs EQU 6
TIM1_CCER_CC2NE_len EQU 1
TIM1_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2NP_ofs EQU 7
TIM1_CCER_CC2NP_len EQU 1
TIM1_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM1_CCER_CC3E_ofs EQU 8
TIM1_CCER_CC3E_len EQU 1
TIM1_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3P_ofs EQU 9
TIM1_CCER_CC3P_len EQU 1
TIM1_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM1_CCER_CC3NE_ofs EQU 10
TIM1_CCER_CC3NE_len EQU 1
TIM1_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3NP_ofs EQU 11
TIM1_CCER_CC3NP_len EQU 1
TIM1_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM1_CCER_CC4E_ofs EQU 12
TIM1_CCER_CC4E_len EQU 1
TIM1_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC4P_ofs EQU 13
TIM1_CCER_CC4P_len EQU 1
TIM1_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM1_CCER_CC4NP_ofs EQU 15
TIM1_CCER_CC4NP_len EQU 1
TIM1_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM1_CCER_CC5E_ofs EQU 16
TIM1_CCER_CC5E_len EQU 1
TIM1_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM1_CCER_CC5P_ofs EQU 17
TIM1_CCER_CC5P_len EQU 1
TIM1_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM1_CCER_CC6E_ofs EQU 20
TIM1_CCER_CC6E_len EQU 1
TIM1_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM1_CCER_CC6P_ofs EQU 21
TIM1_CCER_CC6P_len EQU 1
; TIM1_CNT fields:
TIM1_CNT_CNT EQU 0x0000ffff ; counter value
TIM1_CNT_CNT_ofs EQU 0
TIM1_CNT_CNT_len EQU 16
TIM1_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM1_CNT_UIFCPY_ofs EQU 31
TIM1_CNT_UIFCPY_len EQU 1
; TIM1_PSC fields:
TIM1_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM1_PSC_PSC_ofs EQU 0
TIM1_PSC_PSC_len EQU 16
; TIM1_ARR fields:
TIM1_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM1_ARR_ARR_ofs EQU 0
TIM1_ARR_ARR_len EQU 16
; TIM1_RCR fields:
TIM1_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM1_RCR_REP_ofs EQU 0
TIM1_RCR_REP_len EQU 16
; TIM1_CCR1 fields:
TIM1_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM1_CCR1_CCR1_ofs EQU 0
TIM1_CCR1_CCR1_len EQU 16
; TIM1_CCR2 fields:
TIM1_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM1_CCR2_CCR2_ofs EQU 0
TIM1_CCR2_CCR2_len EQU 16
; TIM1_CCR3 fields:
TIM1_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR3_CCR3_ofs EQU 0
TIM1_CCR3_CCR3_len EQU 16
; TIM1_CCR4 fields:
TIM1_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR4_CCR4_ofs EQU 0
TIM1_CCR4_CCR4_len EQU 16
; TIM1_BDTR fields:
TIM1_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM1_BDTR_DTG_ofs EQU 0
TIM1_BDTR_DTG_len EQU 8
TIM1_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM1_BDTR_LOCK_ofs EQU 8
TIM1_BDTR_LOCK_len EQU 2
TIM1_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM1_BDTR_OSSI_ofs EQU 10
TIM1_BDTR_OSSI_len EQU 1
TIM1_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM1_BDTR_OSSR_ofs EQU 11
TIM1_BDTR_OSSR_len EQU 1
TIM1_BDTR_BKE EQU 0x00001000 ; Break enable
TIM1_BDTR_BKE_ofs EQU 12
TIM1_BDTR_BKE_len EQU 1
TIM1_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM1_BDTR_BKP_ofs EQU 13
TIM1_BDTR_BKP_len EQU 1
TIM1_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM1_BDTR_AOE_ofs EQU 14
TIM1_BDTR_AOE_len EQU 1
TIM1_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM1_BDTR_MOE_ofs EQU 15
TIM1_BDTR_MOE_len EQU 1
TIM1_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM1_BDTR_BKF_ofs EQU 16
TIM1_BDTR_BKF_len EQU 4
TIM1_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM1_BDTR_BK2F_ofs EQU 20
TIM1_BDTR_BK2F_len EQU 4
TIM1_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM1_BDTR_BK2E_ofs EQU 24
TIM1_BDTR_BK2E_len EQU 1
TIM1_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM1_BDTR_BK2P_ofs EQU 25
TIM1_BDTR_BK2P_len EQU 1
; TIM1_DCR fields:
TIM1_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM1_DCR_DBL_ofs EQU 8
TIM1_DCR_DBL_len EQU 5
TIM1_DCR_DBA EQU 0x0000001f ; DMA base address
TIM1_DCR_DBA_ofs EQU 0
TIM1_DCR_DBA_len EQU 5
; TIM1_DMAR fields:
TIM1_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM1_DMAR_DMAB_ofs EQU 0
TIM1_DMAR_DMAB_len EQU 16
; TIM1_CCMR3_Output fields:
TIM1_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM1_CCMR3_Output_OC5FE_ofs EQU 2
TIM1_CCMR3_Output_OC5FE_len EQU 1
TIM1_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM1_CCMR3_Output_OC5PE_ofs EQU 3
TIM1_CCMR3_Output_OC5PE_len EQU 1
TIM1_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM1_CCMR3_Output_OC5M_ofs EQU 4
TIM1_CCMR3_Output_OC5M_len EQU 3
TIM1_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM1_CCMR3_Output_OC5CE_ofs EQU 7
TIM1_CCMR3_Output_OC5CE_len EQU 1
TIM1_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM1_CCMR3_Output_OC6FE_ofs EQU 10
TIM1_CCMR3_Output_OC6FE_len EQU 1
TIM1_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM1_CCMR3_Output_OC6PE_ofs EQU 11
TIM1_CCMR3_Output_OC6PE_len EQU 1
TIM1_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM1_CCMR3_Output_OC6M_ofs EQU 12
TIM1_CCMR3_Output_OC6M_len EQU 3
TIM1_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM1_CCMR3_Output_OC6CE_ofs EQU 15
TIM1_CCMR3_Output_OC6CE_len EQU 1
TIM1_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM1_CCMR3_Output_OC5M_3_ofs EQU 16
TIM1_CCMR3_Output_OC5M_3_len EQU 1
TIM1_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM1_CCMR3_Output_OC6M_3_ofs EQU 24
TIM1_CCMR3_Output_OC6M_3_len EQU 1
; TIM1_CCR5 fields:
TIM1_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM1_CCR5_CCR5_ofs EQU 0
TIM1_CCR5_CCR5_len EQU 16
TIM1_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM1_CCR5_GC5C1_ofs EQU 29
TIM1_CCR5_GC5C1_len EQU 1
TIM1_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM1_CCR5_GC5C2_ofs EQU 30
TIM1_CCR5_GC5C2_len EQU 1
TIM1_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM1_CCR5_GC5C3_ofs EQU 31
TIM1_CCR5_GC5C3_len EQU 1
; TIM1_CCR6 fields:
TIM1_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM1_CCR6_CCR6_ofs EQU 0
TIM1_CCR6_CCR6_len EQU 16
; TIM1_OR fields:
TIM1_OR_TIM1_ETR_ADC1_RMP EQU 0x00000003 ; TIM1_ETR_ADC1 remapping capability
TIM1_OR_TIM1_ETR_ADC1_RMP_ofs EQU 0
TIM1_OR_TIM1_ETR_ADC1_RMP_len EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP EQU 0x0000000c ; TIM1_ETR_ADC4 remapping capability
TIM1_OR_TIM1_ETR_ADC4_RMP_ofs EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP_len EQU 2
; ---- TIM8 --------------------------------------------------
; Desc: Advanced-timers
; TIM8 base address:
TIM8_BASE EQU 0x40013400
; TIM8 registers:
TIM8_CR1 EQU (TIM8_BASE + 0x0) ; control register 1
TIM8_CR2 EQU (TIM8_BASE + 0x4) ; control register 2
TIM8_SMCR EQU (TIM8_BASE + 0x8) ; slave mode control register
TIM8_DIER EQU (TIM8_BASE + 0xc) ; DMA/Interrupt enable register
TIM8_SR EQU (TIM8_BASE + 0x10) ; status register
TIM8_EGR EQU (TIM8_BASE + 0x14) ; event generation register
TIM8_CCMR1_Output EQU (TIM8_BASE + 0x18) ; capture/compare mode register (output mode)
TIM8_CCMR1_Input EQU (TIM8_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM8_CCMR2_Output EQU (TIM8_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM8_CCMR2_Input EQU (TIM8_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM8_CCER EQU (TIM8_BASE + 0x20) ; capture/compare enable register
TIM8_CNT EQU (TIM8_BASE + 0x24) ; counter
TIM8_PSC EQU (TIM8_BASE + 0x28) ; prescaler
TIM8_ARR EQU (TIM8_BASE + 0x2c) ; auto-reload register
TIM8_RCR EQU (TIM8_BASE + 0x30) ; repetition counter register
TIM8_CCR1 EQU (TIM8_BASE + 0x34) ; capture/compare register 1
TIM8_CCR2 EQU (TIM8_BASE + 0x38) ; capture/compare register 2
TIM8_CCR3 EQU (TIM8_BASE + 0x3c) ; capture/compare register 3
TIM8_CCR4 EQU (TIM8_BASE + 0x40) ; capture/compare register 4
TIM8_BDTR EQU (TIM8_BASE + 0x44) ; break and dead-time register
TIM8_DCR EQU (TIM8_BASE + 0x48) ; DMA control register
TIM8_DMAR EQU (TIM8_BASE + 0x4c) ; DMA address for full transfer
TIM8_CCMR3_Output EQU (TIM8_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM8_CCR5 EQU (TIM8_BASE + 0x58) ; capture/compare register 5
TIM8_CCR6 EQU (TIM8_BASE + 0x5c) ; capture/compare register 6
TIM8_OR EQU (TIM8_BASE + 0x60) ; option registers
; TIM8_CR1 fields:
TIM8_CR1_CEN EQU 0x00000001 ; Counter enable
TIM8_CR1_CEN_ofs EQU 0
TIM8_CR1_CEN_len EQU 1
TIM8_CR1_UDIS EQU 0x00000002 ; Update disable
TIM8_CR1_UDIS_ofs EQU 1
TIM8_CR1_UDIS_len EQU 1
TIM8_CR1_URS EQU 0x00000004 ; Update request source
TIM8_CR1_URS_ofs EQU 2
TIM8_CR1_URS_len EQU 1
TIM8_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM8_CR1_OPM_ofs EQU 3
TIM8_CR1_OPM_len EQU 1
TIM8_CR1_DIR EQU 0x00000010 ; Direction
TIM8_CR1_DIR_ofs EQU 4
TIM8_CR1_DIR_len EQU 1
TIM8_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM8_CR1_CMS_ofs EQU 5
TIM8_CR1_CMS_len EQU 2
TIM8_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM8_CR1_ARPE_ofs EQU 7
TIM8_CR1_ARPE_len EQU 1
TIM8_CR1_CKD EQU 0x00000300 ; Clock division
TIM8_CR1_CKD_ofs EQU 8
TIM8_CR1_CKD_len EQU 2
TIM8_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM8_CR1_UIFREMAP_ofs EQU 11
TIM8_CR1_UIFREMAP_len EQU 1
; TIM8_CR2 fields:
TIM8_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM8_CR2_CCPC_ofs EQU 0
TIM8_CR2_CCPC_len EQU 1
TIM8_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM8_CR2_CCUS_ofs EQU 2
TIM8_CR2_CCUS_len EQU 1
TIM8_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM8_CR2_CCDS_ofs EQU 3
TIM8_CR2_CCDS_len EQU 1
TIM8_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM8_CR2_MMS_ofs EQU 4
TIM8_CR2_MMS_len EQU 3
TIM8_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM8_CR2_TI1S_ofs EQU 7
TIM8_CR2_TI1S_len EQU 1
TIM8_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM8_CR2_OIS1_ofs EQU 8
TIM8_CR2_OIS1_len EQU 1
TIM8_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM8_CR2_OIS1N_ofs EQU 9
TIM8_CR2_OIS1N_len EQU 1
TIM8_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM8_CR2_OIS2_ofs EQU 10
TIM8_CR2_OIS2_len EQU 1
TIM8_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM8_CR2_OIS2N_ofs EQU 11
TIM8_CR2_OIS2N_len EQU 1
TIM8_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM8_CR2_OIS3_ofs EQU 12
TIM8_CR2_OIS3_len EQU 1
TIM8_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM8_CR2_OIS3N_ofs EQU 13
TIM8_CR2_OIS3N_len EQU 1
TIM8_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM8_CR2_OIS4_ofs EQU 14
TIM8_CR2_OIS4_len EQU 1
TIM8_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM8_CR2_OIS5_ofs EQU 16
TIM8_CR2_OIS5_len EQU 1
TIM8_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM8_CR2_OIS6_ofs EQU 18
TIM8_CR2_OIS6_len EQU 1
TIM8_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM8_CR2_MMS2_ofs EQU 20
TIM8_CR2_MMS2_len EQU 4
; TIM8_SMCR fields:
TIM8_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM8_SMCR_SMS_ofs EQU 0
TIM8_SMCR_SMS_len EQU 3
TIM8_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM8_SMCR_OCCS_ofs EQU 3
TIM8_SMCR_OCCS_len EQU 1
TIM8_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM8_SMCR_TS_ofs EQU 4
TIM8_SMCR_TS_len EQU 3
TIM8_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM8_SMCR_MSM_ofs EQU 7
TIM8_SMCR_MSM_len EQU 1
TIM8_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM8_SMCR_ETF_ofs EQU 8
TIM8_SMCR_ETF_len EQU 4
TIM8_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM8_SMCR_ETPS_ofs EQU 12
TIM8_SMCR_ETPS_len EQU 2
TIM8_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM8_SMCR_ECE_ofs EQU 14
TIM8_SMCR_ECE_len EQU 1
TIM8_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM8_SMCR_ETP_ofs EQU 15
TIM8_SMCR_ETP_len EQU 1
TIM8_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM8_SMCR_SMS3_ofs EQU 16
TIM8_SMCR_SMS3_len EQU 1
; TIM8_DIER fields:
TIM8_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM8_DIER_TDE_ofs EQU 14
TIM8_DIER_TDE_len EQU 1
TIM8_DIER_COMDE EQU 0x00002000 ; Reserved
TIM8_DIER_COMDE_ofs EQU 13
TIM8_DIER_COMDE_len EQU 1
TIM8_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM8_DIER_CC4DE_ofs EQU 12
TIM8_DIER_CC4DE_len EQU 1
TIM8_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM8_DIER_CC3DE_ofs EQU 11
TIM8_DIER_CC3DE_len EQU 1
TIM8_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM8_DIER_CC2DE_ofs EQU 10
TIM8_DIER_CC2DE_len EQU 1
TIM8_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM8_DIER_CC1DE_ofs EQU 9
TIM8_DIER_CC1DE_len EQU 1
TIM8_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM8_DIER_UDE_ofs EQU 8
TIM8_DIER_UDE_len EQU 1
TIM8_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM8_DIER_BIE_ofs EQU 7
TIM8_DIER_BIE_len EQU 1
TIM8_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM8_DIER_TIE_ofs EQU 6
TIM8_DIER_TIE_len EQU 1
TIM8_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM8_DIER_COMIE_ofs EQU 5
TIM8_DIER_COMIE_len EQU 1
TIM8_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM8_DIER_CC4IE_ofs EQU 4
TIM8_DIER_CC4IE_len EQU 1
TIM8_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM8_DIER_CC3IE_ofs EQU 3
TIM8_DIER_CC3IE_len EQU 1
TIM8_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM8_DIER_CC2IE_ofs EQU 2
TIM8_DIER_CC2IE_len EQU 1
TIM8_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM8_DIER_CC1IE_ofs EQU 1
TIM8_DIER_CC1IE_len EQU 1
TIM8_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM8_DIER_UIE_ofs EQU 0
TIM8_DIER_UIE_len EQU 1
; TIM8_SR fields:
TIM8_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM8_SR_UIF_ofs EQU 0
TIM8_SR_UIF_len EQU 1
TIM8_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM8_SR_CC1IF_ofs EQU 1
TIM8_SR_CC1IF_len EQU 1
TIM8_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM8_SR_CC2IF_ofs EQU 2
TIM8_SR_CC2IF_len EQU 1
TIM8_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM8_SR_CC3IF_ofs EQU 3
TIM8_SR_CC3IF_len EQU 1
TIM8_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM8_SR_CC4IF_ofs EQU 4
TIM8_SR_CC4IF_len EQU 1
TIM8_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM8_SR_COMIF_ofs EQU 5
TIM8_SR_COMIF_len EQU 1
TIM8_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM8_SR_TIF_ofs EQU 6
TIM8_SR_TIF_len EQU 1
TIM8_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM8_SR_BIF_ofs EQU 7
TIM8_SR_BIF_len EQU 1
TIM8_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM8_SR_B2IF_ofs EQU 8
TIM8_SR_B2IF_len EQU 1
TIM8_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM8_SR_CC1OF_ofs EQU 9
TIM8_SR_CC1OF_len EQU 1
TIM8_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM8_SR_CC2OF_ofs EQU 10
TIM8_SR_CC2OF_len EQU 1
TIM8_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM8_SR_CC3OF_ofs EQU 11
TIM8_SR_CC3OF_len EQU 1
TIM8_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM8_SR_CC4OF_ofs EQU 12
TIM8_SR_CC4OF_len EQU 1
TIM8_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM8_SR_C5IF_ofs EQU 16
TIM8_SR_C5IF_len EQU 1
TIM8_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM8_SR_C6IF_ofs EQU 17
TIM8_SR_C6IF_len EQU 1
; TIM8_EGR fields:
TIM8_EGR_UG EQU 0x00000001 ; Update generation
TIM8_EGR_UG_ofs EQU 0
TIM8_EGR_UG_len EQU 1
TIM8_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM8_EGR_CC1G_ofs EQU 1
TIM8_EGR_CC1G_len EQU 1
TIM8_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM8_EGR_CC2G_ofs EQU 2
TIM8_EGR_CC2G_len EQU 1
TIM8_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM8_EGR_CC3G_ofs EQU 3
TIM8_EGR_CC3G_len EQU 1
TIM8_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM8_EGR_CC4G_ofs EQU 4
TIM8_EGR_CC4G_len EQU 1
TIM8_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM8_EGR_COMG_ofs EQU 5
TIM8_EGR_COMG_len EQU 1
TIM8_EGR_TG EQU 0x00000040 ; Trigger generation
TIM8_EGR_TG_ofs EQU 6
TIM8_EGR_TG_len EQU 1
TIM8_EGR_BG EQU 0x00000080 ; Break generation
TIM8_EGR_BG_ofs EQU 7
TIM8_EGR_BG_len EQU 1
TIM8_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM8_EGR_B2G_ofs EQU 8
TIM8_EGR_B2G_len EQU 1
; TIM8_CCMR1_Output fields:
TIM8_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM8_CCMR1_Output_OC2CE_ofs EQU 15
TIM8_CCMR1_Output_OC2CE_len EQU 1
TIM8_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM8_CCMR1_Output_OC2M_ofs EQU 12
TIM8_CCMR1_Output_OC2M_len EQU 3
TIM8_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM8_CCMR1_Output_OC2PE_ofs EQU 11
TIM8_CCMR1_Output_OC2PE_len EQU 1
TIM8_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM8_CCMR1_Output_OC2FE_ofs EQU 10
TIM8_CCMR1_Output_OC2FE_len EQU 1
TIM8_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Output_CC2S_ofs EQU 8
TIM8_CCMR1_Output_CC2S_len EQU 2
TIM8_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM8_CCMR1_Output_OC1CE_ofs EQU 7
TIM8_CCMR1_Output_OC1CE_len EQU 1
TIM8_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM8_CCMR1_Output_OC1M_ofs EQU 4
TIM8_CCMR1_Output_OC1M_len EQU 3
TIM8_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM8_CCMR1_Output_OC1PE_ofs EQU 3
TIM8_CCMR1_Output_OC1PE_len EQU 1
TIM8_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM8_CCMR1_Output_OC1FE_ofs EQU 2
TIM8_CCMR1_Output_OC1FE_len EQU 1
TIM8_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Output_CC1S_ofs EQU 0
TIM8_CCMR1_Output_CC1S_len EQU 2
TIM8_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM8_CCMR1_Output_OC1M_3_ofs EQU 16
TIM8_CCMR1_Output_OC1M_3_len EQU 1
TIM8_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM8_CCMR1_Output_OC2M_3_ofs EQU 24
TIM8_CCMR1_Output_OC2M_3_len EQU 1
; TIM8_CCMR1_Input fields:
TIM8_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM8_CCMR1_Input_IC2F_ofs EQU 12
TIM8_CCMR1_Input_IC2F_len EQU 4
TIM8_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM8_CCMR1_Input_IC2PCS_ofs EQU 10
TIM8_CCMR1_Input_IC2PCS_len EQU 2
TIM8_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Input_CC2S_ofs EQU 8
TIM8_CCMR1_Input_CC2S_len EQU 2
TIM8_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM8_CCMR1_Input_IC1F_ofs EQU 4
TIM8_CCMR1_Input_IC1F_len EQU 4
TIM8_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM8_CCMR1_Input_IC1PCS_ofs EQU 2
TIM8_CCMR1_Input_IC1PCS_len EQU 2
TIM8_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Input_CC1S_ofs EQU 0
TIM8_CCMR1_Input_CC1S_len EQU 2
; TIM8_CCMR2_Output fields:
TIM8_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM8_CCMR2_Output_OC4CE_ofs EQU 15
TIM8_CCMR2_Output_OC4CE_len EQU 1
TIM8_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM8_CCMR2_Output_OC4M_ofs EQU 12
TIM8_CCMR2_Output_OC4M_len EQU 3
TIM8_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM8_CCMR2_Output_OC4PE_ofs EQU 11
TIM8_CCMR2_Output_OC4PE_len EQU 1
TIM8_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM8_CCMR2_Output_OC4FE_ofs EQU 10
TIM8_CCMR2_Output_OC4FE_len EQU 1
TIM8_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Output_CC4S_ofs EQU 8
TIM8_CCMR2_Output_CC4S_len EQU 2
TIM8_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM8_CCMR2_Output_OC3CE_ofs EQU 7
TIM8_CCMR2_Output_OC3CE_len EQU 1
TIM8_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM8_CCMR2_Output_OC3M_ofs EQU 4
TIM8_CCMR2_Output_OC3M_len EQU 3
TIM8_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM8_CCMR2_Output_OC3PE_ofs EQU 3
TIM8_CCMR2_Output_OC3PE_len EQU 1
TIM8_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM8_CCMR2_Output_OC3FE_ofs EQU 2
TIM8_CCMR2_Output_OC3FE_len EQU 1
TIM8_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM8_CCMR2_Output_CC3S_ofs EQU 0
TIM8_CCMR2_Output_CC3S_len EQU 2
TIM8_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM8_CCMR2_Output_OC3M_3_ofs EQU 16
TIM8_CCMR2_Output_OC3M_3_len EQU 1
TIM8_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM8_CCMR2_Output_OC4M_3_ofs EQU 24
TIM8_CCMR2_Output_OC4M_3_len EQU 1
; TIM8_CCMR2_Input fields:
TIM8_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM8_CCMR2_Input_IC4F_ofs EQU 12
TIM8_CCMR2_Input_IC4F_len EQU 4
TIM8_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM8_CCMR2_Input_IC4PSC_ofs EQU 10
TIM8_CCMR2_Input_IC4PSC_len EQU 2
TIM8_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Input_CC4S_ofs EQU 8
TIM8_CCMR2_Input_CC4S_len EQU 2
TIM8_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM8_CCMR2_Input_IC3F_ofs EQU 4
TIM8_CCMR2_Input_IC3F_len EQU 4
TIM8_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM8_CCMR2_Input_IC3PSC_ofs EQU 2
TIM8_CCMR2_Input_IC3PSC_len EQU 2
TIM8_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM8_CCMR2_Input_CC3S_ofs EQU 0
TIM8_CCMR2_Input_CC3S_len EQU 2
; TIM8_CCER fields:
TIM8_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM8_CCER_CC1E_ofs EQU 0
TIM8_CCER_CC1E_len EQU 1
TIM8_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1P_ofs EQU 1
TIM8_CCER_CC1P_len EQU 1
TIM8_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM8_CCER_CC1NE_ofs EQU 2
TIM8_CCER_CC1NE_len EQU 1
TIM8_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1NP_ofs EQU 3
TIM8_CCER_CC1NP_len EQU 1
TIM8_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM8_CCER_CC2E_ofs EQU 4
TIM8_CCER_CC2E_len EQU 1
TIM8_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2P_ofs EQU 5
TIM8_CCER_CC2P_len EQU 1
TIM8_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM8_CCER_CC2NE_ofs EQU 6
TIM8_CCER_CC2NE_len EQU 1
TIM8_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2NP_ofs EQU 7
TIM8_CCER_CC2NP_len EQU 1
TIM8_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM8_CCER_CC3E_ofs EQU 8
TIM8_CCER_CC3E_len EQU 1
TIM8_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3P_ofs EQU 9
TIM8_CCER_CC3P_len EQU 1
TIM8_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM8_CCER_CC3NE_ofs EQU 10
TIM8_CCER_CC3NE_len EQU 1
TIM8_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3NP_ofs EQU 11
TIM8_CCER_CC3NP_len EQU 1
TIM8_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM8_CCER_CC4E_ofs EQU 12
TIM8_CCER_CC4E_len EQU 1
TIM8_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC4P_ofs EQU 13
TIM8_CCER_CC4P_len EQU 1
TIM8_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM8_CCER_CC4NP_ofs EQU 15
TIM8_CCER_CC4NP_len EQU 1
TIM8_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM8_CCER_CC5E_ofs EQU 16
TIM8_CCER_CC5E_len EQU 1
TIM8_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM8_CCER_CC5P_ofs EQU 17
TIM8_CCER_CC5P_len EQU 1
TIM8_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM8_CCER_CC6E_ofs EQU 20
TIM8_CCER_CC6E_len EQU 1
TIM8_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM8_CCER_CC6P_ofs EQU 21
TIM8_CCER_CC6P_len EQU 1
; TIM8_CNT fields:
TIM8_CNT_CNT EQU 0x0000ffff ; counter value
TIM8_CNT_CNT_ofs EQU 0
TIM8_CNT_CNT_len EQU 16
TIM8_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM8_CNT_UIFCPY_ofs EQU 31
TIM8_CNT_UIFCPY_len EQU 1
; TIM8_PSC fields:
TIM8_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM8_PSC_PSC_ofs EQU 0
TIM8_PSC_PSC_len EQU 16
; TIM8_ARR fields:
TIM8_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM8_ARR_ARR_ofs EQU 0
TIM8_ARR_ARR_len EQU 16
; TIM8_RCR fields:
TIM8_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM8_RCR_REP_ofs EQU 0
TIM8_RCR_REP_len EQU 16
; TIM8_CCR1 fields:
TIM8_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM8_CCR1_CCR1_ofs EQU 0
TIM8_CCR1_CCR1_len EQU 16
; TIM8_CCR2 fields:
TIM8_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM8_CCR2_CCR2_ofs EQU 0
TIM8_CCR2_CCR2_len EQU 16
; TIM8_CCR3 fields:
TIM8_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR3_CCR3_ofs EQU 0
TIM8_CCR3_CCR3_len EQU 16
; TIM8_CCR4 fields:
TIM8_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR4_CCR4_ofs EQU 0
TIM8_CCR4_CCR4_len EQU 16
; TIM8_BDTR fields:
TIM8_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM8_BDTR_DTG_ofs EQU 0
TIM8_BDTR_DTG_len EQU 8
TIM8_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM8_BDTR_LOCK_ofs EQU 8
TIM8_BDTR_LOCK_len EQU 2
TIM8_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM8_BDTR_OSSI_ofs EQU 10
TIM8_BDTR_OSSI_len EQU 1
TIM8_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM8_BDTR_OSSR_ofs EQU 11
TIM8_BDTR_OSSR_len EQU 1
TIM8_BDTR_BKE EQU 0x00001000 ; Break enable
TIM8_BDTR_BKE_ofs EQU 12
TIM8_BDTR_BKE_len EQU 1
TIM8_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM8_BDTR_BKP_ofs EQU 13
TIM8_BDTR_BKP_len EQU 1
TIM8_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM8_BDTR_AOE_ofs EQU 14
TIM8_BDTR_AOE_len EQU 1
TIM8_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM8_BDTR_MOE_ofs EQU 15
TIM8_BDTR_MOE_len EQU 1
TIM8_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM8_BDTR_BKF_ofs EQU 16
TIM8_BDTR_BKF_len EQU 4
TIM8_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM8_BDTR_BK2F_ofs EQU 20
TIM8_BDTR_BK2F_len EQU 4
TIM8_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM8_BDTR_BK2E_ofs EQU 24
TIM8_BDTR_BK2E_len EQU 1
TIM8_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM8_BDTR_BK2P_ofs EQU 25
TIM8_BDTR_BK2P_len EQU 1
; TIM8_DCR fields:
TIM8_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM8_DCR_DBL_ofs EQU 8
TIM8_DCR_DBL_len EQU 5
TIM8_DCR_DBA EQU 0x0000001f ; DMA base address
TIM8_DCR_DBA_ofs EQU 0
TIM8_DCR_DBA_len EQU 5
; TIM8_DMAR fields:
TIM8_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM8_DMAR_DMAB_ofs EQU 0
TIM8_DMAR_DMAB_len EQU 16
; TIM8_CCMR3_Output fields:
TIM8_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM8_CCMR3_Output_OC5FE_ofs EQU 2
TIM8_CCMR3_Output_OC5FE_len EQU 1
TIM8_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM8_CCMR3_Output_OC5PE_ofs EQU 3
TIM8_CCMR3_Output_OC5PE_len EQU 1
TIM8_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM8_CCMR3_Output_OC5M_ofs EQU 4
TIM8_CCMR3_Output_OC5M_len EQU 3
TIM8_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM8_CCMR3_Output_OC5CE_ofs EQU 7
TIM8_CCMR3_Output_OC5CE_len EQU 1
TIM8_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM8_CCMR3_Output_OC6FE_ofs EQU 10
TIM8_CCMR3_Output_OC6FE_len EQU 1
TIM8_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM8_CCMR3_Output_OC6PE_ofs EQU 11
TIM8_CCMR3_Output_OC6PE_len EQU 1
TIM8_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM8_CCMR3_Output_OC6M_ofs EQU 12
TIM8_CCMR3_Output_OC6M_len EQU 3
TIM8_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM8_CCMR3_Output_OC6CE_ofs EQU 15
TIM8_CCMR3_Output_OC6CE_len EQU 1
TIM8_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM8_CCMR3_Output_OC5M_3_ofs EQU 16
TIM8_CCMR3_Output_OC5M_3_len EQU 1
TIM8_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM8_CCMR3_Output_OC6M_3_ofs EQU 24
TIM8_CCMR3_Output_OC6M_3_len EQU 1
; TIM8_CCR5 fields:
TIM8_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM8_CCR5_CCR5_ofs EQU 0
TIM8_CCR5_CCR5_len EQU 16
TIM8_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM8_CCR5_GC5C1_ofs EQU 29
TIM8_CCR5_GC5C1_len EQU 1
TIM8_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM8_CCR5_GC5C2_ofs EQU 30
TIM8_CCR5_GC5C2_len EQU 1
TIM8_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM8_CCR5_GC5C3_ofs EQU 31
TIM8_CCR5_GC5C3_len EQU 1
; TIM8_CCR6 fields:
TIM8_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM8_CCR6_CCR6_ofs EQU 0
TIM8_CCR6_CCR6_len EQU 16
; TIM8_OR fields:
TIM8_OR_TIM8_ETR_ADC2_RMP EQU 0x00000003 ; TIM8_ETR_ADC2 remapping capability
TIM8_OR_TIM8_ETR_ADC2_RMP_ofs EQU 0
TIM8_OR_TIM8_ETR_ADC2_RMP_len EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP EQU 0x0000000c ; TIM8_ETR_ADC3 remapping capability
TIM8_OR_TIM8_ETR_ADC3_RMP_ofs EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP_len EQU 2
; ---- ADC1 --------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC1 base address:
ADC1_BASE EQU 0x50000000
; ADC1 registers:
ADC1_ISR EQU (ADC1_BASE + 0x0) ; interrupt and status register
ADC1_IER EQU (ADC1_BASE + 0x4) ; interrupt enable register
ADC1_CR EQU (ADC1_BASE + 0x8) ; control register
ADC1_CFGR EQU (ADC1_BASE + 0xc) ; configuration register
ADC1_SMPR1 EQU (ADC1_BASE + 0x14) ; sample time register 1
ADC1_SMPR2 EQU (ADC1_BASE + 0x18) ; sample time register 2
ADC1_TR1 EQU (ADC1_BASE + 0x20) ; watchdog threshold register 1
ADC1_TR2 EQU (ADC1_BASE + 0x24) ; watchdog threshold register
ADC1_TR3 EQU (ADC1_BASE + 0x28) ; watchdog threshold register 3
ADC1_SQR1 EQU (ADC1_BASE + 0x30) ; regular sequence register 1
ADC1_SQR2 EQU (ADC1_BASE + 0x34) ; regular sequence register 2
ADC1_SQR3 EQU (ADC1_BASE + 0x38) ; regular sequence register 3
ADC1_SQR4 EQU (ADC1_BASE + 0x3c) ; regular sequence register 4
ADC1_DR EQU (ADC1_BASE + 0x40) ; regular Data Register
ADC1_JSQR EQU (ADC1_BASE + 0x4c) ; injected sequence register
ADC1_OFR1 EQU (ADC1_BASE + 0x60) ; offset register 1
ADC1_OFR2 EQU (ADC1_BASE + 0x64) ; offset register 2
ADC1_OFR3 EQU (ADC1_BASE + 0x68) ; offset register 3
ADC1_OFR4 EQU (ADC1_BASE + 0x6c) ; offset register 4
ADC1_JDR1 EQU (ADC1_BASE + 0x80) ; injected data register 1
ADC1_JDR2 EQU (ADC1_BASE + 0x84) ; injected data register 2
ADC1_JDR3 EQU (ADC1_BASE + 0x88) ; injected data register 3
ADC1_JDR4 EQU (ADC1_BASE + 0x8c) ; injected data register 4
ADC1_AWD2CR EQU (ADC1_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC1_AWD3CR EQU (ADC1_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC1_DIFSEL EQU (ADC1_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC1_CALFACT EQU (ADC1_BASE + 0xb4) ; Calibration Factors
; ADC1_ISR fields:
ADC1_ISR_JQOVF EQU 0x00000400 ; JQOVF
ADC1_ISR_JQOVF_ofs EQU 10
ADC1_ISR_JQOVF_len EQU 1
ADC1_ISR_AWD3 EQU 0x00000200 ; AWD3
ADC1_ISR_AWD3_ofs EQU 9
ADC1_ISR_AWD3_len EQU 1
ADC1_ISR_AWD2 EQU 0x00000100 ; AWD2
ADC1_ISR_AWD2_ofs EQU 8
ADC1_ISR_AWD2_len EQU 1
ADC1_ISR_AWD1 EQU 0x00000080 ; AWD1
ADC1_ISR_AWD1_ofs EQU 7
ADC1_ISR_AWD1_len EQU 1
ADC1_ISR_JEOS EQU 0x00000040 ; JEOS
ADC1_ISR_JEOS_ofs EQU 6
ADC1_ISR_JEOS_len EQU 1
ADC1_ISR_JEOC EQU 0x00000020 ; JEOC
ADC1_ISR_JEOC_ofs EQU 5
ADC1_ISR_JEOC_len EQU 1
ADC1_ISR_OVR EQU 0x00000010 ; OVR
ADC1_ISR_OVR_ofs EQU 4
ADC1_ISR_OVR_len EQU 1
ADC1_ISR_EOS EQU 0x00000008 ; EOS
ADC1_ISR_EOS_ofs EQU 3
ADC1_ISR_EOS_len EQU 1
ADC1_ISR_EOC EQU 0x00000004 ; EOC
ADC1_ISR_EOC_ofs EQU 2
ADC1_ISR_EOC_len EQU 1
ADC1_ISR_EOSMP EQU 0x00000002 ; EOSMP
ADC1_ISR_EOSMP_ofs EQU 1
ADC1_ISR_EOSMP_len EQU 1
ADC1_ISR_ADRDY EQU 0x00000001 ; ADRDY
ADC1_ISR_ADRDY_ofs EQU 0
ADC1_ISR_ADRDY_len EQU 1
; ADC1_IER fields:
ADC1_IER_JQOVFIE EQU 0x00000400 ; JQOVFIE
ADC1_IER_JQOVFIE_ofs EQU 10
ADC1_IER_JQOVFIE_len EQU 1
ADC1_IER_AWD3IE EQU 0x00000200 ; AWD3IE
ADC1_IER_AWD3IE_ofs EQU 9
ADC1_IER_AWD3IE_len EQU 1
ADC1_IER_AWD2IE EQU 0x00000100 ; AWD2IE
ADC1_IER_AWD2IE_ofs EQU 8
ADC1_IER_AWD2IE_len EQU 1
ADC1_IER_AWD1IE EQU 0x00000080 ; AWD1IE
ADC1_IER_AWD1IE_ofs EQU 7
ADC1_IER_AWD1IE_len EQU 1
ADC1_IER_JEOSIE EQU 0x00000040 ; JEOSIE
ADC1_IER_JEOSIE_ofs EQU 6
ADC1_IER_JEOSIE_len EQU 1
ADC1_IER_JEOCIE EQU 0x00000020 ; JEOCIE
ADC1_IER_JEOCIE_ofs EQU 5
ADC1_IER_JEOCIE_len EQU 1
ADC1_IER_OVRIE EQU 0x00000010 ; OVRIE
ADC1_IER_OVRIE_ofs EQU 4
ADC1_IER_OVRIE_len EQU 1
ADC1_IER_EOSIE EQU 0x00000008 ; EOSIE
ADC1_IER_EOSIE_ofs EQU 3
ADC1_IER_EOSIE_len EQU 1
ADC1_IER_EOCIE EQU 0x00000004 ; EOCIE
ADC1_IER_EOCIE_ofs EQU 2
ADC1_IER_EOCIE_len EQU 1
ADC1_IER_EOSMPIE EQU 0x00000002 ; EOSMPIE
ADC1_IER_EOSMPIE_ofs EQU 1
ADC1_IER_EOSMPIE_len EQU 1
ADC1_IER_ADRDYIE EQU 0x00000001 ; ADRDYIE
ADC1_IER_ADRDYIE_ofs EQU 0
ADC1_IER_ADRDYIE_len EQU 1
; ADC1_CR fields:
ADC1_CR_ADCAL EQU 0x80000000 ; ADCAL
ADC1_CR_ADCAL_ofs EQU 31
ADC1_CR_ADCAL_len EQU 1
ADC1_CR_ADCALDIF EQU 0x40000000 ; ADCALDIF
ADC1_CR_ADCALDIF_ofs EQU 30
ADC1_CR_ADCALDIF_len EQU 1
ADC1_CR_DEEPPWD EQU 0x20000000 ; DEEPPWD
ADC1_CR_DEEPPWD_ofs EQU 29
ADC1_CR_DEEPPWD_len EQU 1
ADC1_CR_ADVREGEN EQU 0x10000000 ; ADVREGEN
ADC1_CR_ADVREGEN_ofs EQU 28
ADC1_CR_ADVREGEN_len EQU 1
ADC1_CR_JADSTP EQU 0x00000020 ; JADSTP
ADC1_CR_JADSTP_ofs EQU 5
ADC1_CR_JADSTP_len EQU 1
ADC1_CR_ADSTP EQU 0x00000010 ; ADSTP
ADC1_CR_ADSTP_ofs EQU 4
ADC1_CR_ADSTP_len EQU 1
ADC1_CR_JADSTART EQU 0x00000008 ; JADSTART
ADC1_CR_JADSTART_ofs EQU 3
ADC1_CR_JADSTART_len EQU 1
ADC1_CR_ADSTART EQU 0x00000004 ; ADSTART
ADC1_CR_ADSTART_ofs EQU 2
ADC1_CR_ADSTART_len EQU 1
ADC1_CR_ADDIS EQU 0x00000002 ; ADDIS
ADC1_CR_ADDIS_ofs EQU 1
ADC1_CR_ADDIS_len EQU 1
ADC1_CR_ADEN EQU 0x00000001 ; ADEN
ADC1_CR_ADEN_ofs EQU 0
ADC1_CR_ADEN_len EQU 1
; ADC1_CFGR fields:
ADC1_CFGR_AWDCH1CH EQU 0x7c000000 ; AWDCH1CH
ADC1_CFGR_AWDCH1CH_ofs EQU 26
ADC1_CFGR_AWDCH1CH_len EQU 5
ADC1_CFGR_JAUTO EQU 0x02000000 ; JAUTO
ADC1_CFGR_JAUTO_ofs EQU 25
ADC1_CFGR_JAUTO_len EQU 1
ADC1_CFGR_JAWD1EN EQU 0x01000000 ; JAWD1EN
ADC1_CFGR_JAWD1EN_ofs EQU 24
ADC1_CFGR_JAWD1EN_len EQU 1
ADC1_CFGR_AWD1EN EQU 0x00800000 ; AWD1EN
ADC1_CFGR_AWD1EN_ofs EQU 23
ADC1_CFGR_AWD1EN_len EQU 1
ADC1_CFGR_AWD1SGL EQU 0x00400000 ; AWD1SGL
ADC1_CFGR_AWD1SGL_ofs EQU 22
ADC1_CFGR_AWD1SGL_len EQU 1
ADC1_CFGR_JQM EQU 0x00200000 ; JQM
ADC1_CFGR_JQM_ofs EQU 21
ADC1_CFGR_JQM_len EQU 1
ADC1_CFGR_JDISCEN EQU 0x00100000 ; JDISCEN
ADC1_CFGR_JDISCEN_ofs EQU 20
ADC1_CFGR_JDISCEN_len EQU 1
ADC1_CFGR_DISCNUM EQU 0x000e0000 ; DISCNUM
ADC1_CFGR_DISCNUM_ofs EQU 17
ADC1_CFGR_DISCNUM_len EQU 3
ADC1_CFGR_DISCEN EQU 0x00010000 ; DISCEN
ADC1_CFGR_DISCEN_ofs EQU 16
ADC1_CFGR_DISCEN_len EQU 1
ADC1_CFGR_AUTOFF EQU 0x00008000 ; AUTOFF
ADC1_CFGR_AUTOFF_ofs EQU 15
ADC1_CFGR_AUTOFF_len EQU 1
ADC1_CFGR_AUTDLY EQU 0x00004000 ; AUTDLY
ADC1_CFGR_AUTDLY_ofs EQU 14
ADC1_CFGR_AUTDLY_len EQU 1
ADC1_CFGR_CONT EQU 0x00002000 ; CONT
ADC1_CFGR_CONT_ofs EQU 13
ADC1_CFGR_CONT_len EQU 1
ADC1_CFGR_OVRMOD EQU 0x00001000 ; OVRMOD
ADC1_CFGR_OVRMOD_ofs EQU 12
ADC1_CFGR_OVRMOD_len EQU 1
ADC1_CFGR_EXTEN EQU 0x00000c00 ; EXTEN
ADC1_CFGR_EXTEN_ofs EQU 10
ADC1_CFGR_EXTEN_len EQU 2
ADC1_CFGR_EXTSEL EQU 0x000003c0 ; EXTSEL
ADC1_CFGR_EXTSEL_ofs EQU 6
ADC1_CFGR_EXTSEL_len EQU 4
ADC1_CFGR_ALIGN EQU 0x00000020 ; ALIGN
ADC1_CFGR_ALIGN_ofs EQU 5
ADC1_CFGR_ALIGN_len EQU 1
ADC1_CFGR_RES EQU 0x00000018 ; RES
ADC1_CFGR_RES_ofs EQU 3
ADC1_CFGR_RES_len EQU 2
ADC1_CFGR_DMACFG EQU 0x00000002 ; DMACFG
ADC1_CFGR_DMACFG_ofs EQU 1
ADC1_CFGR_DMACFG_len EQU 1
ADC1_CFGR_DMAEN EQU 0x00000001 ; DMAEN
ADC1_CFGR_DMAEN_ofs EQU 0
ADC1_CFGR_DMAEN_len EQU 1
; ADC1_SMPR1 fields:
ADC1_SMPR1_SMP9 EQU 0x38000000 ; SMP9
ADC1_SMPR1_SMP9_ofs EQU 27
ADC1_SMPR1_SMP9_len EQU 3
ADC1_SMPR1_SMP8 EQU 0x07000000 ; SMP8
ADC1_SMPR1_SMP8_ofs EQU 24
ADC1_SMPR1_SMP8_len EQU 3
ADC1_SMPR1_SMP7 EQU 0x00e00000 ; SMP7
ADC1_SMPR1_SMP7_ofs EQU 21
ADC1_SMPR1_SMP7_len EQU 3
ADC1_SMPR1_SMP6 EQU 0x001c0000 ; SMP6
ADC1_SMPR1_SMP6_ofs EQU 18
ADC1_SMPR1_SMP6_len EQU 3
ADC1_SMPR1_SMP5 EQU 0x00038000 ; SMP5
ADC1_SMPR1_SMP5_ofs EQU 15
ADC1_SMPR1_SMP5_len EQU 3
ADC1_SMPR1_SMP4 EQU 0x00007000 ; SMP4
ADC1_SMPR1_SMP4_ofs EQU 12
ADC1_SMPR1_SMP4_len EQU 3
ADC1_SMPR1_SMP3 EQU 0x00000e00 ; SMP3
ADC1_SMPR1_SMP3_ofs EQU 9
ADC1_SMPR1_SMP3_len EQU 3
ADC1_SMPR1_SMP2 EQU 0x000001c0 ; SMP2
ADC1_SMPR1_SMP2_ofs EQU 6
ADC1_SMPR1_SMP2_len EQU 3
ADC1_SMPR1_SMP1 EQU 0x00000038 ; SMP1
ADC1_SMPR1_SMP1_ofs EQU 3
ADC1_SMPR1_SMP1_len EQU 3
; ADC1_SMPR2 fields:
ADC1_SMPR2_SMP18 EQU 0x07000000 ; SMP18
ADC1_SMPR2_SMP18_ofs EQU 24
ADC1_SMPR2_SMP18_len EQU 3
ADC1_SMPR2_SMP17 EQU 0x00e00000 ; SMP17
ADC1_SMPR2_SMP17_ofs EQU 21
ADC1_SMPR2_SMP17_len EQU 3
ADC1_SMPR2_SMP16 EQU 0x001c0000 ; SMP16
ADC1_SMPR2_SMP16_ofs EQU 18
ADC1_SMPR2_SMP16_len EQU 3
ADC1_SMPR2_SMP15 EQU 0x00038000 ; SMP15
ADC1_SMPR2_SMP15_ofs EQU 15
ADC1_SMPR2_SMP15_len EQU 3
ADC1_SMPR2_SMP14 EQU 0x00007000 ; SMP14
ADC1_SMPR2_SMP14_ofs EQU 12
ADC1_SMPR2_SMP14_len EQU 3
ADC1_SMPR2_SMP13 EQU 0x00000e00 ; SMP13
ADC1_SMPR2_SMP13_ofs EQU 9
ADC1_SMPR2_SMP13_len EQU 3
ADC1_SMPR2_SMP12 EQU 0x000001c0 ; SMP12
ADC1_SMPR2_SMP12_ofs EQU 6
ADC1_SMPR2_SMP12_len EQU 3
ADC1_SMPR2_SMP11 EQU 0x00000038 ; SMP11
ADC1_SMPR2_SMP11_ofs EQU 3
ADC1_SMPR2_SMP11_len EQU 3
ADC1_SMPR2_SMP10 EQU 0x00000007 ; SMP10
ADC1_SMPR2_SMP10_ofs EQU 0
ADC1_SMPR2_SMP10_len EQU 3
; ADC1_TR1 fields:
ADC1_TR1_HT1 EQU 0x0fff0000 ; HT1
ADC1_TR1_HT1_ofs EQU 16
ADC1_TR1_HT1_len EQU 12
ADC1_TR1_LT1 EQU 0x00000fff ; LT1
ADC1_TR1_LT1_ofs EQU 0
ADC1_TR1_LT1_len EQU 12
; ADC1_TR2 fields:
ADC1_TR2_HT2 EQU 0x00ff0000 ; HT2
ADC1_TR2_HT2_ofs EQU 16
ADC1_TR2_HT2_len EQU 8
ADC1_TR2_LT2 EQU 0x000000ff ; LT2
ADC1_TR2_LT2_ofs EQU 0
ADC1_TR2_LT2_len EQU 8
; ADC1_TR3 fields:
ADC1_TR3_HT3 EQU 0x00ff0000 ; HT3
ADC1_TR3_HT3_ofs EQU 16
ADC1_TR3_HT3_len EQU 8
ADC1_TR3_LT3 EQU 0x000000ff ; LT3
ADC1_TR3_LT3_ofs EQU 0
ADC1_TR3_LT3_len EQU 8
; ADC1_SQR1 fields:
ADC1_SQR1_SQ4 EQU 0x1f000000 ; SQ4
ADC1_SQR1_SQ4_ofs EQU 24
ADC1_SQR1_SQ4_len EQU 5
ADC1_SQR1_SQ3 EQU 0x007c0000 ; SQ3
ADC1_SQR1_SQ3_ofs EQU 18
ADC1_SQR1_SQ3_len EQU 5
ADC1_SQR1_SQ2 EQU 0x0001f000 ; SQ2
ADC1_SQR1_SQ2_ofs EQU 12
ADC1_SQR1_SQ2_len EQU 5
ADC1_SQR1_SQ1 EQU 0x000007c0 ; SQ1
ADC1_SQR1_SQ1_ofs EQU 6
ADC1_SQR1_SQ1_len EQU 5
ADC1_SQR1_L3 EQU 0x0000000f ; L3
ADC1_SQR1_L3_ofs EQU 0
ADC1_SQR1_L3_len EQU 4
; ADC1_SQR2 fields:
ADC1_SQR2_SQ9 EQU 0x1f000000 ; SQ9
ADC1_SQR2_SQ9_ofs EQU 24
ADC1_SQR2_SQ9_len EQU 5
ADC1_SQR2_SQ8 EQU 0x007c0000 ; SQ8
ADC1_SQR2_SQ8_ofs EQU 18
ADC1_SQR2_SQ8_len EQU 5
ADC1_SQR2_SQ7 EQU 0x0001f000 ; SQ7
ADC1_SQR2_SQ7_ofs EQU 12
ADC1_SQR2_SQ7_len EQU 5
ADC1_SQR2_SQ6 EQU 0x000007c0 ; SQ6
ADC1_SQR2_SQ6_ofs EQU 6
ADC1_SQR2_SQ6_len EQU 5
ADC1_SQR2_SQ5 EQU 0x0000001f ; SQ5
ADC1_SQR2_SQ5_ofs EQU 0
ADC1_SQR2_SQ5_len EQU 5
; ADC1_SQR3 fields:
ADC1_SQR3_SQ14 EQU 0x1f000000 ; SQ14
ADC1_SQR3_SQ14_ofs EQU 24
ADC1_SQR3_SQ14_len EQU 5
ADC1_SQR3_SQ13 EQU 0x007c0000 ; SQ13
ADC1_SQR3_SQ13_ofs EQU 18
ADC1_SQR3_SQ13_len EQU 5
ADC1_SQR3_SQ12 EQU 0x0001f000 ; SQ12
ADC1_SQR3_SQ12_ofs EQU 12
ADC1_SQR3_SQ12_len EQU 5
ADC1_SQR3_SQ11 EQU 0x000007c0 ; SQ11
ADC1_SQR3_SQ11_ofs EQU 6
ADC1_SQR3_SQ11_len EQU 5
ADC1_SQR3_SQ10 EQU 0x0000001f ; SQ10
ADC1_SQR3_SQ10_ofs EQU 0
ADC1_SQR3_SQ10_len EQU 5
; ADC1_SQR4 fields:
ADC1_SQR4_SQ16 EQU 0x000007c0 ; SQ16
ADC1_SQR4_SQ16_ofs EQU 6
ADC1_SQR4_SQ16_len EQU 5
ADC1_SQR4_SQ15 EQU 0x0000001f ; SQ15
ADC1_SQR4_SQ15_ofs EQU 0
ADC1_SQR4_SQ15_len EQU 5
; ADC1_DR fields:
ADC1_DR_regularDATA EQU 0x0000ffff ; regularDATA
ADC1_DR_regularDATA_ofs EQU 0
ADC1_DR_regularDATA_len EQU 16
; ADC1_JSQR fields:
ADC1_JSQR_JSQ4 EQU 0x7c000000 ; JSQ4
ADC1_JSQR_JSQ4_ofs EQU 26
ADC1_JSQR_JSQ4_len EQU 5
ADC1_JSQR_JSQ3 EQU 0x01f00000 ; JSQ3
ADC1_JSQR_JSQ3_ofs EQU 20
ADC1_JSQR_JSQ3_len EQU 5
ADC1_JSQR_JSQ2 EQU 0x0007c000 ; JSQ2
ADC1_JSQR_JSQ2_ofs EQU 14
ADC1_JSQR_JSQ2_len EQU 5
ADC1_JSQR_JSQ1 EQU 0x00001f00 ; JSQ1
ADC1_JSQR_JSQ1_ofs EQU 8
ADC1_JSQR_JSQ1_len EQU 5
ADC1_JSQR_JEXTEN EQU 0x000000c0 ; JEXTEN
ADC1_JSQR_JEXTEN_ofs EQU 6
ADC1_JSQR_JEXTEN_len EQU 2
ADC1_JSQR_JEXTSEL EQU 0x0000003c ; JEXTSEL
ADC1_JSQR_JEXTSEL_ofs EQU 2
ADC1_JSQR_JEXTSEL_len EQU 4
ADC1_JSQR_JL EQU 0x00000003 ; JL
ADC1_JSQR_JL_ofs EQU 0
ADC1_JSQR_JL_len EQU 2
; ADC1_OFR1 fields:
ADC1_OFR1_OFFSET1_EN EQU 0x80000000 ; OFFSET1_EN
ADC1_OFR1_OFFSET1_EN_ofs EQU 31
ADC1_OFR1_OFFSET1_EN_len EQU 1
ADC1_OFR1_OFFSET1_CH EQU 0x7c000000 ; OFFSET1_CH
ADC1_OFR1_OFFSET1_CH_ofs EQU 26
ADC1_OFR1_OFFSET1_CH_len EQU 5
ADC1_OFR1_OFFSET1 EQU 0x00000fff ; OFFSET1
ADC1_OFR1_OFFSET1_ofs EQU 0
ADC1_OFR1_OFFSET1_len EQU 12
; ADC1_OFR2 fields:
ADC1_OFR2_OFFSET2_EN EQU 0x80000000 ; OFFSET2_EN
ADC1_OFR2_OFFSET2_EN_ofs EQU 31
ADC1_OFR2_OFFSET2_EN_len EQU 1
ADC1_OFR2_OFFSET2_CH EQU 0x7c000000 ; OFFSET2_CH
ADC1_OFR2_OFFSET2_CH_ofs EQU 26
ADC1_OFR2_OFFSET2_CH_len EQU 5
ADC1_OFR2_OFFSET2 EQU 0x00000fff ; OFFSET2
ADC1_OFR2_OFFSET2_ofs EQU 0
ADC1_OFR2_OFFSET2_len EQU 12
; ADC1_OFR3 fields:
ADC1_OFR3_OFFSET3_EN EQU 0x80000000 ; OFFSET3_EN
ADC1_OFR3_OFFSET3_EN_ofs EQU 31
ADC1_OFR3_OFFSET3_EN_len EQU 1
ADC1_OFR3_OFFSET3_CH EQU 0x7c000000 ; OFFSET3_CH
ADC1_OFR3_OFFSET3_CH_ofs EQU 26
ADC1_OFR3_OFFSET3_CH_len EQU 5
ADC1_OFR3_OFFSET3 EQU 0x00000fff ; OFFSET3
ADC1_OFR3_OFFSET3_ofs EQU 0
ADC1_OFR3_OFFSET3_len EQU 12
; ADC1_OFR4 fields:
ADC1_OFR4_OFFSET4_EN EQU 0x80000000 ; OFFSET4_EN
ADC1_OFR4_OFFSET4_EN_ofs EQU 31
ADC1_OFR4_OFFSET4_EN_len EQU 1
ADC1_OFR4_OFFSET4_CH EQU 0x7c000000 ; OFFSET4_CH
ADC1_OFR4_OFFSET4_CH_ofs EQU 26
ADC1_OFR4_OFFSET4_CH_len EQU 5
ADC1_OFR4_OFFSET4 EQU 0x00000fff ; OFFSET4
ADC1_OFR4_OFFSET4_ofs EQU 0
ADC1_OFR4_OFFSET4_len EQU 12
; ADC1_JDR1 fields:
ADC1_JDR1_JDATA1 EQU 0x0000ffff ; JDATA1
ADC1_JDR1_JDATA1_ofs EQU 0
ADC1_JDR1_JDATA1_len EQU 16
; ADC1_JDR2 fields:
ADC1_JDR2_JDATA2 EQU 0x0000ffff ; JDATA2
ADC1_JDR2_JDATA2_ofs EQU 0
ADC1_JDR2_JDATA2_len EQU 16
; ADC1_JDR3 fields:
ADC1_JDR3_JDATA3 EQU 0x0000ffff ; JDATA3
ADC1_JDR3_JDATA3_ofs EQU 0
ADC1_JDR3_JDATA3_len EQU 16
; ADC1_JDR4 fields:
ADC1_JDR4_JDATA4 EQU 0x0000ffff ; JDATA4
ADC1_JDR4_JDATA4_ofs EQU 0
ADC1_JDR4_JDATA4_len EQU 16
; ADC1_AWD2CR fields:
ADC1_AWD2CR_AWD2CH EQU 0x0007fffe ; AWD2CH
ADC1_AWD2CR_AWD2CH_ofs EQU 1
ADC1_AWD2CR_AWD2CH_len EQU 18
; ADC1_AWD3CR fields:
ADC1_AWD3CR_AWD3CH EQU 0x0007fffe ; AWD3CH
ADC1_AWD3CR_AWD3CH_ofs EQU 1
ADC1_AWD3CR_AWD3CH_len EQU 18
; ADC1_DIFSEL fields:
ADC1_DIFSEL_DIFSEL_1_15 EQU 0x0000fffe ; Differential mode for channels 15 to 1
ADC1_DIFSEL_DIFSEL_1_15_ofs EQU 1
ADC1_DIFSEL_DIFSEL_1_15_len EQU 15
ADC1_DIFSEL_DIFSEL_16_18 EQU 0x00070000 ; Differential mode for channels 18 to 16
ADC1_DIFSEL_DIFSEL_16_18_ofs EQU 16
ADC1_DIFSEL_DIFSEL_16_18_len EQU 3
; ADC1_CALFACT fields:
ADC1_CALFACT_CALFACT_D EQU 0x007f0000 ; CALFACT_D
ADC1_CALFACT_CALFACT_D_ofs EQU 16
ADC1_CALFACT_CALFACT_D_len EQU 7
ADC1_CALFACT_CALFACT_S EQU 0x0000007f ; CALFACT_S
ADC1_CALFACT_CALFACT_S_ofs EQU 0
ADC1_CALFACT_CALFACT_S_len EQU 7
; ---- ADC2 --------------------------------------------------
; Desc: None
; ADC2 base address:
ADC2_BASE EQU 0x50000100
; ADC2 registers:
ADC2_ISR EQU (ADC2_BASE + 0x0) ; interrupt and status register
ADC2_IER EQU (ADC2_BASE + 0x4) ; interrupt enable register
ADC2_CR EQU (ADC2_BASE + 0x8) ; control register
ADC2_CFGR EQU (ADC2_BASE + 0xc) ; configuration register
ADC2_SMPR1 EQU (ADC2_BASE + 0x14) ; sample time register 1
ADC2_SMPR2 EQU (ADC2_BASE + 0x18) ; sample time register 2
ADC2_TR1 EQU (ADC2_BASE + 0x20) ; watchdog threshold register 1
ADC2_TR2 EQU (ADC2_BASE + 0x24) ; watchdog threshold register
ADC2_TR3 EQU (ADC2_BASE + 0x28) ; watchdog threshold register 3
ADC2_SQR1 EQU (ADC2_BASE + 0x30) ; regular sequence register 1
ADC2_SQR2 EQU (ADC2_BASE + 0x34) ; regular sequence register 2
ADC2_SQR3 EQU (ADC2_BASE + 0x38) ; regular sequence register 3
ADC2_SQR4 EQU (ADC2_BASE + 0x3c) ; regular sequence register 4
ADC2_DR EQU (ADC2_BASE + 0x40) ; regular Data Register
ADC2_JSQR EQU (ADC2_BASE + 0x4c) ; injected sequence register
ADC2_OFR1 EQU (ADC2_BASE + 0x60) ; offset register 1
ADC2_OFR2 EQU (ADC2_BASE + 0x64) ; offset register 2
ADC2_OFR3 EQU (ADC2_BASE + 0x68) ; offset register 3
ADC2_OFR4 EQU (ADC2_BASE + 0x6c) ; offset register 4
ADC2_JDR1 EQU (ADC2_BASE + 0x80) ; injected data register 1
ADC2_JDR2 EQU (ADC2_BASE + 0x84) ; injected data register 2
ADC2_JDR3 EQU (ADC2_BASE + 0x88) ; injected data register 3
ADC2_JDR4 EQU (ADC2_BASE + 0x8c) ; injected data register 4
ADC2_AWD2CR EQU (ADC2_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC2_AWD3CR EQU (ADC2_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC2_DIFSEL EQU (ADC2_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC2_CALFACT EQU (ADC2_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC3 --------------------------------------------------
; Desc: None
; ADC3 base address:
ADC3_BASE EQU 0x50000400
; ADC3 registers:
ADC3_ISR EQU (ADC3_BASE + 0x0) ; interrupt and status register
ADC3_IER EQU (ADC3_BASE + 0x4) ; interrupt enable register
ADC3_CR EQU (ADC3_BASE + 0x8) ; control register
ADC3_CFGR EQU (ADC3_BASE + 0xc) ; configuration register
ADC3_SMPR1 EQU (ADC3_BASE + 0x14) ; sample time register 1
ADC3_SMPR2 EQU (ADC3_BASE + 0x18) ; sample time register 2
ADC3_TR1 EQU (ADC3_BASE + 0x20) ; watchdog threshold register 1
ADC3_TR2 EQU (ADC3_BASE + 0x24) ; watchdog threshold register
ADC3_TR3 EQU (ADC3_BASE + 0x28) ; watchdog threshold register 3
ADC3_SQR1 EQU (ADC3_BASE + 0x30) ; regular sequence register 1
ADC3_SQR2 EQU (ADC3_BASE + 0x34) ; regular sequence register 2
ADC3_SQR3 EQU (ADC3_BASE + 0x38) ; regular sequence register 3
ADC3_SQR4 EQU (ADC3_BASE + 0x3c) ; regular sequence register 4
ADC3_DR EQU (ADC3_BASE + 0x40) ; regular Data Register
ADC3_JSQR EQU (ADC3_BASE + 0x4c) ; injected sequence register
ADC3_OFR1 EQU (ADC3_BASE + 0x60) ; offset register 1
ADC3_OFR2 EQU (ADC3_BASE + 0x64) ; offset register 2
ADC3_OFR3 EQU (ADC3_BASE + 0x68) ; offset register 3
ADC3_OFR4 EQU (ADC3_BASE + 0x6c) ; offset register 4
ADC3_JDR1 EQU (ADC3_BASE + 0x80) ; injected data register 1
ADC3_JDR2 EQU (ADC3_BASE + 0x84) ; injected data register 2
ADC3_JDR3 EQU (ADC3_BASE + 0x88) ; injected data register 3
ADC3_JDR4 EQU (ADC3_BASE + 0x8c) ; injected data register 4
ADC3_AWD2CR EQU (ADC3_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC3_AWD3CR EQU (ADC3_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC3_DIFSEL EQU (ADC3_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC3_CALFACT EQU (ADC3_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC4 --------------------------------------------------
; Desc: None
; ADC4 base address:
ADC4_BASE EQU 0x50000500
; ADC4 registers:
ADC4_ISR EQU (ADC4_BASE + 0x0) ; interrupt and status register
ADC4_IER EQU (ADC4_BASE + 0x4) ; interrupt enable register
ADC4_CR EQU (ADC4_BASE + 0x8) ; control register
ADC4_CFGR EQU (ADC4_BASE + 0xc) ; configuration register
ADC4_SMPR1 EQU (ADC4_BASE + 0x14) ; sample time register 1
ADC4_SMPR2 EQU (ADC4_BASE + 0x18) ; sample time register 2
ADC4_TR1 EQU (ADC4_BASE + 0x20) ; watchdog threshold register 1
ADC4_TR2 EQU (ADC4_BASE + 0x24) ; watchdog threshold register
ADC4_TR3 EQU (ADC4_BASE + 0x28) ; watchdog threshold register 3
ADC4_SQR1 EQU (ADC4_BASE + 0x30) ; regular sequence register 1
ADC4_SQR2 EQU (ADC4_BASE + 0x34) ; regular sequence register 2
ADC4_SQR3 EQU (ADC4_BASE + 0x38) ; regular sequence register 3
ADC4_SQR4 EQU (ADC4_BASE + 0x3c) ; regular sequence register 4
ADC4_DR EQU (ADC4_BASE + 0x40) ; regular Data Register
ADC4_JSQR EQU (ADC4_BASE + 0x4c) ; injected sequence register
ADC4_OFR1 EQU (ADC4_BASE + 0x60) ; offset register 1
ADC4_OFR2 EQU (ADC4_BASE + 0x64) ; offset register 2
ADC4_OFR3 EQU (ADC4_BASE + 0x68) ; offset register 3
ADC4_OFR4 EQU (ADC4_BASE + 0x6c) ; offset register 4
ADC4_JDR1 EQU (ADC4_BASE + 0x80) ; injected data register 1
ADC4_JDR2 EQU (ADC4_BASE + 0x84) ; injected data register 2
ADC4_JDR3 EQU (ADC4_BASE + 0x88) ; injected data register 3
ADC4_JDR4 EQU (ADC4_BASE + 0x8c) ; injected data register 4
ADC4_AWD2CR EQU (ADC4_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC4_AWD3CR EQU (ADC4_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC4_DIFSEL EQU (ADC4_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC4_CALFACT EQU (ADC4_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC12 -------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC12 base address:
ADC12_BASE EQU 0x50000300
; ADC12 registers:
ADC12_CSR EQU (ADC12_BASE + 0x0) ; ADC Common status register
ADC12_CCR EQU (ADC12_BASE + 0x8) ; ADC common control register
ADC12_CDR EQU (ADC12_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; ADC12_CSR fields:
ADCC_CSR_ADDRDY_MST EQU 0x00000001 ; ADDRDY_MST
ADCC_CSR_ADDRDY_MST_ofs EQU 0
ADCC_CSR_ADDRDY_MST_len EQU 1
ADCC_CSR_EOSMP_MST EQU 0x00000002 ; EOSMP_MST
ADCC_CSR_EOSMP_MST_ofs EQU 1
ADCC_CSR_EOSMP_MST_len EQU 1
ADCC_CSR_EOC_MST EQU 0x00000004 ; EOC_MST
ADCC_CSR_EOC_MST_ofs EQU 2
ADCC_CSR_EOC_MST_len EQU 1
ADCC_CSR_EOS_MST EQU 0x00000008 ; EOS_MST
ADCC_CSR_EOS_MST_ofs EQU 3
ADCC_CSR_EOS_MST_len EQU 1
ADCC_CSR_OVR_MST EQU 0x00000010 ; OVR_MST
ADCC_CSR_OVR_MST_ofs EQU 4
ADCC_CSR_OVR_MST_len EQU 1
ADCC_CSR_JEOC_MST EQU 0x00000020 ; JEOC_MST
ADCC_CSR_JEOC_MST_ofs EQU 5
ADCC_CSR_JEOC_MST_len EQU 1
ADCC_CSR_JEOS_MST EQU 0x00000040 ; JEOS_MST
ADCC_CSR_JEOS_MST_ofs EQU 6
ADCC_CSR_JEOS_MST_len EQU 1
ADCC_CSR_AWD1_MST EQU 0x00000080 ; AWD1_MST
ADCC_CSR_AWD1_MST_ofs EQU 7
ADCC_CSR_AWD1_MST_len EQU 1
ADCC_CSR_AWD2_MST EQU 0x00000100 ; AWD2_MST
ADCC_CSR_AWD2_MST_ofs EQU 8
ADCC_CSR_AWD2_MST_len EQU 1
ADCC_CSR_AWD3_MST EQU 0x00000200 ; AWD3_MST
ADCC_CSR_AWD3_MST_ofs EQU 9
ADCC_CSR_AWD3_MST_len EQU 1
ADCC_CSR_JQOVF_MST EQU 0x00000400 ; JQOVF_MST
ADCC_CSR_JQOVF_MST_ofs EQU 10
ADCC_CSR_JQOVF_MST_len EQU 1
ADCC_CSR_ADRDY_SLV EQU 0x00010000 ; ADRDY_SLV
ADCC_CSR_ADRDY_SLV_ofs EQU 16
ADCC_CSR_ADRDY_SLV_len EQU 1
ADCC_CSR_EOSMP_SLV EQU 0x00020000 ; EOSMP_SLV
ADCC_CSR_EOSMP_SLV_ofs EQU 17
ADCC_CSR_EOSMP_SLV_len EQU 1
ADCC_CSR_EOC_SLV EQU 0x00040000 ; End of regular conversion of the slave ADC
ADCC_CSR_EOC_SLV_ofs EQU 18
ADCC_CSR_EOC_SLV_len EQU 1
ADCC_CSR_EOS_SLV EQU 0x00080000 ; End of regular sequence flag of the slave ADC
ADCC_CSR_EOS_SLV_ofs EQU 19
ADCC_CSR_EOS_SLV_len EQU 1
ADCC_CSR_OVR_SLV EQU 0x00100000 ; Overrun flag of the slave ADC
ADCC_CSR_OVR_SLV_ofs EQU 20
ADCC_CSR_OVR_SLV_len EQU 1
ADCC_CSR_JEOC_SLV EQU 0x00200000 ; End of injected conversion flag of the slave ADC
ADCC_CSR_JEOC_SLV_ofs EQU 21
ADCC_CSR_JEOC_SLV_len EQU 1
ADCC_CSR_JEOS_SLV EQU 0x00400000 ; End of injected sequence flag of the slave ADC
ADCC_CSR_JEOS_SLV_ofs EQU 22
ADCC_CSR_JEOS_SLV_len EQU 1
ADCC_CSR_AWD1_SLV EQU 0x00800000 ; Analog watchdog 1 flag of the slave ADC
ADCC_CSR_AWD1_SLV_ofs EQU 23
ADCC_CSR_AWD1_SLV_len EQU 1
ADCC_CSR_AWD2_SLV EQU 0x01000000 ; Analog watchdog 2 flag of the slave ADC
ADCC_CSR_AWD2_SLV_ofs EQU 24
ADCC_CSR_AWD2_SLV_len EQU 1
ADCC_CSR_AWD3_SLV EQU 0x02000000 ; Analog watchdog 3 flag of the slave ADC
ADCC_CSR_AWD3_SLV_ofs EQU 25
ADCC_CSR_AWD3_SLV_len EQU 1
ADCC_CSR_JQOVF_SLV EQU 0x04000000 ; Injected Context Queue Overflow flag of the slave ADC
ADCC_CSR_JQOVF_SLV_ofs EQU 26
ADCC_CSR_JQOVF_SLV_len EQU 1
; ADC12_CCR fields:
ADCC_CCR_MULT EQU 0x0000001f ; Multi ADC mode selection
ADCC_CCR_MULT_ofs EQU 0
ADCC_CCR_MULT_len EQU 5
ADCC_CCR_DELAY EQU 0x00000f00 ; Delay between 2 sampling phases
ADCC_CCR_DELAY_ofs EQU 8
ADCC_CCR_DELAY_len EQU 4
ADCC_CCR_DMACFG EQU 0x00002000 ; DMA configuration (for multi-ADC mode)
ADCC_CCR_DMACFG_ofs EQU 13
ADCC_CCR_DMACFG_len EQU 1
ADCC_CCR_MDMA EQU 0x0000c000 ; Direct memory access mode for multi ADC mode
ADCC_CCR_MDMA_ofs EQU 14
ADCC_CCR_MDMA_len EQU 2
ADCC_CCR_CKMODE EQU 0x00030000 ; ADC clock mode
ADCC_CCR_CKMODE_ofs EQU 16
ADCC_CCR_CKMODE_len EQU 2
ADCC_CCR_VREFEN EQU 0x00400000 ; VREFINT enable
ADCC_CCR_VREFEN_ofs EQU 22
ADCC_CCR_VREFEN_len EQU 1
ADCC_CCR_TSEN EQU 0x00800000 ; Temperature sensor enable
ADCC_CCR_TSEN_ofs EQU 23
ADCC_CCR_TSEN_len EQU 1
ADCC_CCR_VBATEN EQU 0x01000000 ; VBAT enable
ADCC_CCR_VBATEN_ofs EQU 24
ADCC_CCR_VBATEN_len EQU 1
; ADC12_CDR fields:
ADCC_CDR_RDATA_SLV EQU 0xffff0000 ; Regular data of the slave ADC
ADCC_CDR_RDATA_SLV_ofs EQU 16
ADCC_CDR_RDATA_SLV_len EQU 16
ADCC_CDR_RDATA_MST EQU 0x0000ffff ; Regular data of the master ADC
ADCC_CDR_RDATA_MST_ofs EQU 0
ADCC_CDR_RDATA_MST_len EQU 16
; ---- ADC34 -------------------------------------------------
; Desc: None
; ADC34 base address:
ADC34_BASE EQU 0x50000700
; ADC34 registers:
ADC34_CSR EQU (ADC34_BASE + 0x0) ; ADC Common status register
ADC34_CCR EQU (ADC34_BASE + 0x8) ; ADC common control register
ADC34_CDR EQU (ADC34_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; Fields the same as in the first instance.
; ---- SYSCFG ------------------------------------------------
; Desc: System configuration controller
; SYSCFG base address:
SYSCFG_BASE EQU 0x40010000
; SYSCFG registers:
SYSCFG_CFGR1 EQU (SYSCFG_BASE + 0x0) ; configuration register 1
SYSCFG_EXTICR1 EQU (SYSCFG_BASE + 0x8) ; external interrupt configuration register 1
SYSCFG_EXTICR2 EQU (SYSCFG_BASE + 0xc) ; external interrupt configuration register 2
SYSCFG_EXTICR3 EQU (SYSCFG_BASE + 0x10) ; external interrupt configuration register 3
SYSCFG_EXTICR4 EQU (SYSCFG_BASE + 0x14) ; external interrupt configuration register 4
SYSCFG_CFGR2 EQU (SYSCFG_BASE + 0x18) ; configuration register 2
SYSCFG_RCR EQU (SYSCFG_BASE + 0x4) ; CCM SRAM protection register
; SYSCFG_CFGR1 fields:
SYSCFG_CFGR1_MEM_MODE EQU 0x00000003 ; Memory mapping selection bits
SYSCFG_CFGR1_MEM_MODE_ofs EQU 0
SYSCFG_CFGR1_MEM_MODE_len EQU 2
SYSCFG_CFGR1_USB_IT_RMP EQU 0x00000020 ; USB interrupt remap
SYSCFG_CFGR1_USB_IT_RMP_ofs EQU 5
SYSCFG_CFGR1_USB_IT_RMP_len EQU 1
SYSCFG_CFGR1_TIM1_ITR_RMP EQU 0x00000040 ; Timer 1 ITR3 selection
SYSCFG_CFGR1_TIM1_ITR_RMP_ofs EQU 6
SYSCFG_CFGR1_TIM1_ITR_RMP_len EQU 1
SYSCFG_CFGR1_DAC_TRIG_RMP EQU 0x00000080 ; DAC trigger remap (when TSEL = 001)
SYSCFG_CFGR1_DAC_TRIG_RMP_ofs EQU 7
SYSCFG_CFGR1_DAC_TRIG_RMP_len EQU 1
SYSCFG_CFGR1_ADC24_DMA_RMP EQU 0x00000100 ; ADC24 DMA remapping bit
SYSCFG_CFGR1_ADC24_DMA_RMP_ofs EQU 8
SYSCFG_CFGR1_ADC24_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM16_DMA_RMP EQU 0x00000800 ; TIM16 DMA request remapping bit
SYSCFG_CFGR1_TIM16_DMA_RMP_ofs EQU 11
SYSCFG_CFGR1_TIM16_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM17_DMA_RMP EQU 0x00001000 ; TIM17 DMA request remapping bit
SYSCFG_CFGR1_TIM17_DMA_RMP_ofs EQU 12
SYSCFG_CFGR1_TIM17_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP EQU 0x00002000 ; TIM6 and DAC1 DMA request remapping bit
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_ofs EQU 13
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP EQU 0x00004000 ; TIM7 and DAC2 DMA request remapping bit
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_ofs EQU 14
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_len EQU 1
SYSCFG_CFGR1_I2C_PB6_FM EQU 0x00010000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB6_FM_ofs EQU 16
SYSCFG_CFGR1_I2C_PB6_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB7_FM EQU 0x00020000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB7_FM_ofs EQU 17
SYSCFG_CFGR1_I2C_PB7_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB8_FM EQU 0x00040000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB8_FM_ofs EQU 18
SYSCFG_CFGR1_I2C_PB8_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB9_FM EQU 0x00080000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB9_FM_ofs EQU 19
SYSCFG_CFGR1_I2C_PB9_FM_len EQU 1
SYSCFG_CFGR1_I2C1_FM EQU 0x00100000 ; I2C1 Fast Mode Plus
SYSCFG_CFGR1_I2C1_FM_ofs EQU 20
SYSCFG_CFGR1_I2C1_FM_len EQU 1
SYSCFG_CFGR1_I2C2_FM EQU 0x00200000 ; I2C2 Fast Mode Plus
SYSCFG_CFGR1_I2C2_FM_ofs EQU 21
SYSCFG_CFGR1_I2C2_FM_len EQU 1
SYSCFG_CFGR1_ENCODER_MODE EQU 0x00c00000 ; Encoder mode
SYSCFG_CFGR1_ENCODER_MODE_ofs EQU 22
SYSCFG_CFGR1_ENCODER_MODE_len EQU 2
SYSCFG_CFGR1_FPU_IT EQU 0xfc000000 ; Interrupt enable bits from FPU
SYSCFG_CFGR1_FPU_IT_ofs EQU 26
SYSCFG_CFGR1_FPU_IT_len EQU 6
; SYSCFG_EXTICR1 fields:
SYSCFG_EXTICR1_EXTI3 EQU 0x0000f000 ; EXTI 3 configuration bits
SYSCFG_EXTICR1_EXTI3_ofs EQU 12
SYSCFG_EXTICR1_EXTI3_len EQU 4
SYSCFG_EXTICR1_EXTI2 EQU 0x00000f00 ; EXTI 2 configuration bits
SYSCFG_EXTICR1_EXTI2_ofs EQU 8
SYSCFG_EXTICR1_EXTI2_len EQU 4
SYSCFG_EXTICR1_EXTI1 EQU 0x000000f0 ; EXTI 1 configuration bits
SYSCFG_EXTICR1_EXTI1_ofs EQU 4
SYSCFG_EXTICR1_EXTI1_len EQU 4
SYSCFG_EXTICR1_EXTI0 EQU 0x0000000f ; EXTI 0 configuration bits
SYSCFG_EXTICR1_EXTI0_ofs EQU 0
SYSCFG_EXTICR1_EXTI0_len EQU 4
; SYSCFG_EXTICR2 fields:
SYSCFG_EXTICR2_EXTI7 EQU 0x0000f000 ; EXTI 7 configuration bits
SYSCFG_EXTICR2_EXTI7_ofs EQU 12
SYSCFG_EXTICR2_EXTI7_len EQU 4
SYSCFG_EXTICR2_EXTI6 EQU 0x00000f00 ; EXTI 6 configuration bits
SYSCFG_EXTICR2_EXTI6_ofs EQU 8
SYSCFG_EXTICR2_EXTI6_len EQU 4
SYSCFG_EXTICR2_EXTI5 EQU 0x000000f0 ; EXTI 5 configuration bits
SYSCFG_EXTICR2_EXTI5_ofs EQU 4
SYSCFG_EXTICR2_EXTI5_len EQU 4
SYSCFG_EXTICR2_EXTI4 EQU 0x0000000f ; EXTI 4 configuration bits
SYSCFG_EXTICR2_EXTI4_ofs EQU 0
SYSCFG_EXTICR2_EXTI4_len EQU 4
; SYSCFG_EXTICR3 fields:
SYSCFG_EXTICR3_EXTI11 EQU 0x0000f000 ; EXTI 11 configuration bits
SYSCFG_EXTICR3_EXTI11_ofs EQU 12
SYSCFG_EXTICR3_EXTI11_len EQU 4
SYSCFG_EXTICR3_EXTI10 EQU 0x00000f00 ; EXTI 10 configuration bits
SYSCFG_EXTICR3_EXTI10_ofs EQU 8
SYSCFG_EXTICR3_EXTI10_len EQU 4
SYSCFG_EXTICR3_EXTI9 EQU 0x000000f0 ; EXTI 9 configuration bits
SYSCFG_EXTICR3_EXTI9_ofs EQU 4
SYSCFG_EXTICR3_EXTI9_len EQU 4
SYSCFG_EXTICR3_EXTI8 EQU 0x0000000f ; EXTI 8 configuration bits
SYSCFG_EXTICR3_EXTI8_ofs EQU 0
SYSCFG_EXTICR3_EXTI8_len EQU 4
; SYSCFG_EXTICR4 fields:
SYSCFG_EXTICR4_EXTI15 EQU 0x0000f000 ; EXTI 15 configuration bits
SYSCFG_EXTICR4_EXTI15_ofs EQU 12
SYSCFG_EXTICR4_EXTI15_len EQU 4
SYSCFG_EXTICR4_EXTI14 EQU 0x00000f00 ; EXTI 14 configuration bits
SYSCFG_EXTICR4_EXTI14_ofs EQU 8
SYSCFG_EXTICR4_EXTI14_len EQU 4
SYSCFG_EXTICR4_EXTI13 EQU 0x000000f0 ; EXTI 13 configuration bits
SYSCFG_EXTICR4_EXTI13_ofs EQU 4
SYSCFG_EXTICR4_EXTI13_len EQU 4
SYSCFG_EXTICR4_EXTI12 EQU 0x0000000f ; EXTI 12 configuration bits
SYSCFG_EXTICR4_EXTI12_ofs EQU 0
SYSCFG_EXTICR4_EXTI12_len EQU 4
; SYSCFG_CFGR2 fields:
SYSCFG_CFGR2_LOCUP_LOCK EQU 0x00000001 ; Cortex-M0 LOCKUP bit enable bit
SYSCFG_CFGR2_LOCUP_LOCK_ofs EQU 0
SYSCFG_CFGR2_LOCUP_LOCK_len EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK EQU 0x00000002 ; SRAM parity lock bit
SYSCFG_CFGR2_SRAM_PARITY_LOCK_ofs EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK_len EQU 1
SYSCFG_CFGR2_PVD_LOCK EQU 0x00000004 ; PVD lock enable bit
SYSCFG_CFGR2_PVD_LOCK_ofs EQU 2
SYSCFG_CFGR2_PVD_LOCK_len EQU 1
SYSCFG_CFGR2_BYP_ADD_PAR EQU 0x00000010 ; Bypass address bit 29 in parity calculation
SYSCFG_CFGR2_BYP_ADD_PAR_ofs EQU 4
SYSCFG_CFGR2_BYP_ADD_PAR_len EQU 1
SYSCFG_CFGR2_SRAM_PEF EQU 0x00000100 ; SRAM parity flag
SYSCFG_CFGR2_SRAM_PEF_ofs EQU 8
SYSCFG_CFGR2_SRAM_PEF_len EQU 1
; SYSCFG_RCR fields:
SYSCFG_RCR_PAGE0_WP EQU 0x00000001 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE0_WP_ofs EQU 0
SYSCFG_RCR_PAGE0_WP_len EQU 1
SYSCFG_RCR_PAGE1_WP EQU 0x00000002 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE1_WP_ofs EQU 1
SYSCFG_RCR_PAGE1_WP_len EQU 1
SYSCFG_RCR_PAGE2_WP EQU 0x00000004 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE2_WP_ofs EQU 2
SYSCFG_RCR_PAGE2_WP_len EQU 1
SYSCFG_RCR_PAGE3_WP EQU 0x00000008 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE3_WP_ofs EQU 3
SYSCFG_RCR_PAGE3_WP_len EQU 1
SYSCFG_RCR_PAGE4_WP EQU 0x00000010 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE4_WP_ofs EQU 4
SYSCFG_RCR_PAGE4_WP_len EQU 1
SYSCFG_RCR_PAGE5_WP EQU 0x00000020 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE5_WP_ofs EQU 5
SYSCFG_RCR_PAGE5_WP_len EQU 1
SYSCFG_RCR_PAGE6_WP EQU 0x00000040 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE6_WP_ofs EQU 6
SYSCFG_RCR_PAGE6_WP_len EQU 1
SYSCFG_RCR_PAGE7_WP EQU 0x00000080 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE7_WP_ofs EQU 7
SYSCFG_RCR_PAGE7_WP_len EQU 1
; ---- OPAMP -------------------------------------------------
; Desc: Operational amplifier
; OPAMP base address:
OPAMP_BASE EQU 0x40010038
; OPAMP registers:
OPAMP1_CR EQU (OPAMP_BASE + 0x0) ; OPAMP1 control register
OPAMP2_CR EQU (OPAMP_BASE + 0x4) ; OPAMP2 control register
OPAMP3_CR EQU (OPAMP_BASE + 0x8) ; OPAMP3 control register
OPAMP4_CR EQU (OPAMP_BASE + 0xc) ; OPAMP4 control register
; OPAMP_OPAMP1_CR fields:
OPAMPx_CR_EN EQU 0x00000001 ; OPAMPx enable
OPAMPx_CR_EN_ofs EQU 0
OPAMPx_CR_EN_len EQU 1
OPAMPx_CR_FORCE_VP EQU 0x00000002 ; FORCE_VP
OPAMPx_CR_FORCE_VP_ofs EQU 1
OPAMPx_CR_FORCE_VP_len EQU 1
OPAMPx_CR_VP_SEL EQU 0x0000000c ; OPAMPx Non inverting input selection
OPAMPx_CR_VP_SEL_ofs EQU 2
OPAMPx_CR_VP_SEL_len EQU 2
OPAMPx_CR_VM_SEL EQU 0x00000060 ; OPAMPx inverting input selection
OPAMPx_CR_VM_SEL_ofs EQU 5
OPAMPx_CR_VM_SEL_len EQU 2
OPAMPx_CR_TCM_EN EQU 0x00000080 ; Timer controlled Mux mode enable
OPAMPx_CR_TCM_EN_ofs EQU 7
OPAMPx_CR_TCM_EN_len EQU 1
OPAMPx_CR_VMS_SEL EQU 0x00000100 ; OPAMPx inverting input secondary selection
OPAMPx_CR_VMS_SEL_ofs EQU 8
OPAMPx_CR_VMS_SEL_len EQU 1
OPAMPx_CR_VPS_SEL EQU 0x00000600 ; OPAMPx Non inverting input secondary selection
OPAMPx_CR_VPS_SEL_ofs EQU 9
OPAMPx_CR_VPS_SEL_len EQU 2
OPAMPx_CR_CALON EQU 0x00000800 ; Calibration mode enable
OPAMPx_CR_CALON_ofs EQU 11
OPAMPx_CR_CALON_len EQU 1
OPAMPx_CR_CALSEL EQU 0x00003000 ; Calibration selection
OPAMPx_CR_CALSEL_ofs EQU 12
OPAMPx_CR_CALSEL_len EQU 2
OPAMPx_CR_PGA_GAIN EQU 0x0003c000 ; Gain in PGA mode
OPAMPx_CR_PGA_GAIN_ofs EQU 14
OPAMPx_CR_PGA_GAIN_len EQU 4
OPAMPx_CR_USER_TRIM EQU 0x00040000 ; User trimming enable
OPAMPx_CR_USER_TRIM_ofs EQU 18
OPAMPx_CR_USER_TRIM_len EQU 1
OPAMPx_CR_TRIMOFFSETP EQU 0x00f80000 ; Offset trimming value (PMOS)
OPAMPx_CR_TRIMOFFSETP_ofs EQU 19
OPAMPx_CR_TRIMOFFSETP_len EQU 5
OPAMPx_CR_TRIMOFFSETN EQU 0x1f000000 ; Offset trimming value (NMOS)
OPAMPx_CR_TRIMOFFSETN_ofs EQU 24
OPAMPx_CR_TRIMOFFSETN_len EQU 5
OPAMPx_CR_TSTREF EQU 0x20000000 ; TSTREF
OPAMPx_CR_TSTREF_ofs EQU 29
OPAMPx_CR_TSTREF_len EQU 1
OPAMPx_CR_OUTCAL EQU 0x40000000 ; OPAMPx ouput status flag
OPAMPx_CR_OUTCAL_ofs EQU 30
OPAMPx_CR_OUTCAL_len EQU 1
OPAMPx_CR_LOCK EQU 0x80000000 ; OPAMPx lock
OPAMPx_CR_LOCK_ofs EQU 31
OPAMPx_CR_LOCK_len EQU 1
END
|
SECTION code_clib
IF !__CPU_INTEL__ & !__CPU_RABBIT__ & !__CPU_GBZ80__
PUBLIC psg_envelope
PUBLIC _psg_envelope
;
; $Id: psg_envelope.asm $
;========================================================================================
; void psg_envelope(unsigned int waveform, int period, unsigned int channel) __smallc;
;========================================================================================
; foo entry, envelope is not avaliable on SN76489
;==============================================================
INCLUDE "sn76489.inc"
.psg_envelope
._psg_envelope
ld hl, 2
add hl, sp
ld c, (hl) ; C = Channel
ld a, $0F ; max attenuation,
ld b, a ; ..only the 4 lower bits are significant
ld a, c
rrc a
rrc a
rrc a
and a, $60 ; Puts the channel number in bits 5 and 6
or a, $90
or a, b ; Prepares the first byte of the command
IF HAVE16bitbus
ld bc,psgport
out (c),a
ELSE
out (psgport), a ; Sends it
IF PSGLatchPort
in a,(PSGLatchPort)
ENDIF
ENDIF
ret
ENDIF
|
; A175386: a(n) = denominator of sum((1/i)*C(2n-i-1,i-1),i=1..n).
; Submitted by Christian Krause
; 1,2,6,4,5,4,7,8,18,10,11,24,13,14,30,16,17,12,19,20,42,22,23,48,25,26,54,28,29,20,31,32,66,34,35,72,37,38,78,40,41,28,43,44,90,46,47,96,49,50,6,52,53,36,55,56,114,58,59,120,61,62,126,64,65,44,67,68,138,70,71
mul $0,2
add $0,1
seq $0,242926 ; a(n) = denominator of B(0,n), where B(n,n)=0, B(n-1,n)=1/n and otherwise B(m,n)=B(m-1,n+1)-B(m-1,n).
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r13
push %r14
push %rax
push %rbx
push %rdx
lea addresses_WC_ht+0x6307, %r13
nop
nop
nop
and %rbx, %rbx
mov (%r13), %r12
nop
inc %rax
lea addresses_A_ht+0xa04d, %rdx
nop
nop
xor %r10, %r10
movb $0x61, (%rdx)
nop
and $28224, %r13
lea addresses_D_ht+0x1cfcb, %r13
nop
nop
cmp %r14, %r14
and $0xffffffffffffffc0, %r13
vmovaps (%r13), %ymm3
vextracti128 $1, %ymm3, %xmm3
vpextrq $1, %xmm3, %r12
nop
nop
nop
inc %r13
pop %rdx
pop %rbx
pop %rax
pop %r14
pop %r13
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %rbp
push %rdi
push %rdx
push %rsi
// Faulty Load
lea addresses_D+0x1ac7, %rbp
nop
nop
nop
nop
nop
xor %rsi, %rsi
movb (%rbp), %dl
lea oracles, %rdi
and $0xff, %rdx
shlq $12, %rdx
mov (%rdi,%rdx,1), %rdx
pop %rsi
pop %rdx
pop %rdi
pop %rbp
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 1}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'same': False, 'congruent': 6, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 1}}
{'src': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_D_ht', 'AVXalign': True, 'size': 32}, 'OP': 'LOAD'}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x000000000000FFFF", "0x000000000000FFFF"],
"XMM1": ["0x000000000000FFFF", "0x000000000000FFFF"],
"XMM2": ["0x6162636465667778", "0x5152535455564748"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465667778
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455564748
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx]
pcmpeqw xmm0, [rdx + 8 * 2]
movapd xmm1, [rdx]
movapd xmm2, [rdx + 8 * 2]
pcmpeqw xmm1, xmm2
hlt
|
; 8259 Programmable Interrupt Controller related functions
; Remaps the 8259 Programmable Interrupt Controller.
; IN: Nothing
; OUT: Nothing
pic_init:
push ax
pushf
cli
; Get current mask
in al, 0x21
mov [.master_mask], al
; Restart
mov al, 0x11
out 0x20, al
xor al, al
out 0x80, al
; Set master PIC offset to 0x08
mov al, 0x08
out 0x21, al
xor al, al
out 0x80, al
; Set cascading
mov al, 0x04
out 0x21, al
xor al, al
out 0x80, al
; Done
mov al, 0x01
out 0x21, al
xor al, al
out 0x80, al
; Recover mask
mov al, [.master_mask]
; And enable IRQ 0 and IRQ 1
and al, -4
out 0x21, al
xor al, al
out 0x80, al
sti
popf
pop ax
ret
.master_mask: db 0x00 ; Temporary buffer
|
TITLE Calculating a Factorial (Fact.asm)
; This program uses recursion to calculate the
; factorial of an integer.
; Last update: 11/23/01
INCLUDE Irvine32.inc
.code
main PROC
push 12 ; calc 12!
call Factorial ; calculate factorial (eax)
ReturnMain:
call WriteDec ; display it
call Crlf
exit
main ENDP
Factorial PROC
push ebp
mov ebp,esp
mov eax,[ebp+8] ; get n
cmp eax,0 ; n < 0?
ja L1 ; yes: continue
mov eax,1 ; no: return 1
jmp L2
L1: dec eax
push eax ; Factorial(n-1)
call Factorial
; Instructions from this point on execute when each
; recursive call returns.
ReturnFact:
mov ebx,[ebp+8] ; get n
mul ebx ; ax = ax * bx
L2: pop ebp ; return EAX
ret 4 ; clean up stack
Factorial ENDP
END main |
[BITS 32]
GLOBAL api_openwin
[SECTION .text]
api_openwin: ; int api_openwin(char *buf, int xsiz, int ysiz, int col_inv, char *title);
PUSH EDI
PUSH ESI
PUSH EBX
MOV EDX, 5
MOV EBX, [ESP+16] ; buf
MOV ESI, [ESP+20] ; xsiz
MOV EDI, [ESP+24] ; ysiz
MOV EAX, [ESP+28] ; col_inv
MOV ECX, [ESP+32] ; title
INT 0x40
POP EBX
POP ESI
POP EDI
RET
|
; A199264: Period 18: repeat (9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8).
; 9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6
add $0,2
mov $1,2
mov $2,2
mov $4,2
add $4,$0
add $0,106
add $2,$0
mov $0,$2
mul $0,2
sub $4,2
lpb $0
mul $1,2
add $4,9
sub $0,$4
sub $0,1
sub $1,2
mov $3,1
trn $3,$0
mov $4,8
lpe
mul $1,$3
add $1,$0
sub $1,1
|
; *****************************************************
; *** SPECTRUM +3 ROM 0 DISASSEMBLY (48K BASIC ROM) ***
; *****************************************************
; The Spectrum ROMs are copyright Amstrad, who have kindly given permission
; to reverse engineer and publish Spectrum ROM disassemblies.
; =====
; NOTES
; =====
; ------------
; Release Date
; ------------
; 17th May 2010
; ------------------------
; Disassembly Contributors
; ------------------------
; Garry Lancaster
;
; The ROM disassembly was created with the aid of dZ80 V1.10, and incorporates work from
; "The Complete Spectrum ROM Disassembly" by Logan/O'Hara, and "The canonical list of +3
; oddities" by Ian Collier.
; -----------------
; Assembler Details
; -----------------
; This file can be assembled to produce a binary image of the ROM
; with Interlogic's Z80ASM assembler (available for Z88, QL, DOS and Linux).
; Note that the defs directive is used and this causes a block of $00 bytes to be created.
module rom3
;**************************************************
; include "sysvar48.def"
; System variable definitions for 48K Spectrum
defc KSTATE=$5c00
defc LAST_K=$5c08
defc REPDEL=$5c09
defc REPPER=$5c0a
defc DEFADD=$5c0b
defc K_DATA=$5c0d
defc TVDATA=$5c0e
defc STRMS=$5c10
defc CHARS=$5c36
defc RASP=$5c38
defc PIP=$5c39
defc ERR_NR=$5c3a
defc FLAGS=$5c3b
defc TV_FLAG=$5c3c
defc ERR_SP=$5c3d
defc LIST_SP=$5c3f
defc MODE=$5c41
defc NEWPPC=$5c42
defc NSPPC=$5c44
defc PPC=$5c45
defc SUBPPC=$5c47
defc BORDCR=$5c48
defc E_PPC=$5c49
defc VARS=$5c4b
defc DEST=$5c4d
defc CHANS=$5c4f
defc CURCHL=$5c51
defc PROG=$5c53
defc NXTLIN=$5c55
defc DATADD=$5c57
defc E_LINE=$5c59
defc K_CUR=$5c5b
defc CH_ADD=$5c5d
defc X_PTR=$5c5f
defc WORKSP=$5c61
defc STKBOT=$5c63
defc STKEND=$5c65
defc BREG=$5c67
defc MEM=$5c68
defc FLAGS2=$5c6a
defc DF_SZ=$5c6b
defc S_TOP=$5c6c
defc OLDPPC=$5c6e
defc OSPCC=$5c70
defc FLAGX=$5c71
defc STRLEN=$5c72
defc T_ADDR=$5c74
defc SEED=$5c76
defc FRAMES=$5c78
defc UDG=$5c7b
defc COORDS=$5c7d
defc P_POSN=$5c7f
defc PR_CC=$5c80
defc ECHO_E=$5c82
defc DF_CC=$5c84
defc DF_CCL=$5c86
defc S_POSN=$5c88
defc SPOSNL=$5c8a
defc SCR_CT=$5c8c
defc ATTR_P=$5c8d
defc MASK_P=$5c8e
defc ATTR_T=$5c8f
defc MASK_T=$5c90
defc P_FLAG=$5c91
defc MEMBOT=$5c92
defc NMIADD=$5cb0 ; only used in +3
defc RAMTOP=$5cb2
defc P_RAMT=$5cb4
;**************************************************
; include "sysvarp3.def"
; Additional system variables used in the +3
defc SWAP=$5b00
defc STOO=$5b10
defc YOUNGER=$5b21
defc REGNUOY=$5b2a
defc ONERR=$5b3a
defc OLDHL=$5b52
defc OLDBC=$5b54
defc OLDAF=$5b56
defc TARGET=$5b58
defc RETADDR=$5b5a
defc BANKM=$5b5c
defc RAMRST=$5b5d
defc RAMERR=$5b5e
defc BAUD=$5b5f
defc SERFL=$5b61
defc COL=$5b63
defc WIDTH=$5b64
defc TVPARS=$5b65
defc FLAGS3=$5b66
defc BANK678=$5b67
defc XLOC=$5b68
defc YLOC=$5b69
defc OLDSP=$5b6a
defc SYNRET=$5b6c
defc LASTV=$5b6e
defc RC_LINE=$5b73
defc RC_START=$5b75
defc RC_STEP=$5b77
defc LODDRV=$5b79
defc SAVDRV=$5b7a
defc DUMPLF=$5b7b
defc STRIP1=$5b7c
defc STRIP2=$5b84
defc TSTACK=$5bff
;**************************************************
; include "fpcalc.def"
; The floating-point calculator commands
defgroup
{
jump_true, exchange, delete, subtract, multiply, division,
to_power, or, no_and_no, no_l_eql, no_gr_eq, nos_neql, no_grtr,
no_less, nos_eql, addition, str_and_no, str_l_eql, str_gr_eq,
strs_neql, str_grtr, str_less, strs_eql, strs_add, val_str, usr_str,
read_in, negate, code, val, len, sin, cos, tan, asn, acs, atn,
ln, exp, int, sqr, sgn, abs, peek, in, usr_no, str_str, chr_str,
not, duplicate, n_mod_m, jump, stk_data, dec_jr_nz, less_0,
greater_0, end_calc, get_argt, truncate, fp_calc_2, e_to_fp,
re_stack
}
defc series_06=$86
defc series_08=$88
defc series_0c=$8c
defc stk_zero=$a0
defc stk_one=$a1
defc stk_half=$a2
defc stk_pi_2=$a3
defc stk_ten=$a4
defc st_mem_0=$c0
defc st_mem_1=$c1
defc st_mem_2=$c2
defc st_mem_3=$c3
defc st_mem_4=$c4
defc st_mem_5=$c5
defc get_mem_0=$e0
defc get_mem_1=$e1
defc get_mem_2=$e2
defc get_mem_3=$e3
defc get_mem_4=$e4
defc get_mem_5=$e5
;**************************************************
org $0000
; The "START"
.l0000 di ; disable interrupts
xor a ; A=00 for "start" ($ff for "NEW")
ld de,$ffff ; DE=top of possible RAM
jp l11cb ; jump forward
; The "Error" restart
.l0008 ld hl,(CH_ADD)
ld (X_PTR),hl ; copy interpreter address to error pointer
jr l0053 ; move on
; The "Print a character" restart
.l0010 jp l15f2 ; go to print it
and a ; ?
rst $38 ; unused
rst $38
rst $38
rst $38
; The "Collect character" restart
.l0018 ld hl,(CH_ADD)
ld a,(hl) ; fetch value at CH_ADD
.l001c call l007d ; is char printable?
ret nc ; if so, return
; The "Collect next character" restart
.l0020 call l0074 ; increment CH_ADD
jr l001c ; jump back to test
rst $38 ; unused
rst $38
rst $38
; The "Calculator" restart
.l0028 jp l335b ; enter the calculator
rst $38 ; unused
rst $38
rst $38
rst $38
rst $38
; The "Make BC spaces" restart
.l0030 push bc ; save space to create
ld hl,(WORKSP)
push hl ; and start of workspace
jp l169e ; move on
; The "Maskable interrupt" routine
.l0038 push af
push hl
ld hl,(FRAMES)
inc hl ; increment FRAMES counter
ld (FRAMES),hl
ld a,h
or l
jr nz,l0048
inc (iy+$40) ; increment high byte of FRAMES
.l0048 push bc
push de
call l386e ; scan the keyboard
pop de
pop bc
pop hl
pop af
ei
ret
; The "ERROR-2" routine
.l0053 pop hl
ld l,(hl) ; get error code
.l0055 ld (iy+$00),l ; save in ERR_NR
ld sp,(ERR_SP) ; reset SP
jp l16c5 ; exit via SET-STK
rst $38 ; unused
rst $38
rst $38
rst $38
rst $38
rst $38
rst $38
; The "Non-maskable interrupt" routine
.l0066 push af
push hl
ld hl,(NMIADD) ; get NMI routine address
ld a,h
or l
jr z,l0070 ; skip if zero (fixed from original 48K ROM)
jp (hl) ; execute routine
.l0070 pop hl
pop af
retn
; The "CH_ADD+1" subroutine
.l0074 ld hl,(CH_ADD)
.l0077 inc hl ; increment CH_ADD
.l0078 ld (CH_ADD),hl
ld a,(hl) ; get character
ret
; The "Skip-over" subroutine
.l007d cp $21
ret nc ; return with carry reset if printable
cp $0d
ret z ; return with carry reset if CR
cp $10
ret c ; return with carry SET if $00-$0f
cp $18
ccf
ret c ; return with carry SET if $18-$20
inc hl ; skip one for INK to OVER
cp $16
jr c,l0090
inc hl ; skip again if AT or TAB
.l0090 scf
ld (CH_ADD),hl ; update CH_ADD
ret ; return with carry SET
; The Token table
.l0095 defb '?'+$80
defm "RN"&('D'+$80)
defm "INKEY"&('$'+$80)
defm "P"&('I'+$80)
defm "F"&('N'+$80)
defm "POIN"&('T'+$80)
defm "SCREEN"&('$'+$80)
defm "ATT"&('R'+$80)
defm "A"&('T'+$80)
defm "TA"&('B'+$80)
defm "VAL"&('$'+$80)
defm "COD"&('E'+$80)
defm "VA"&('L'+$80)
defm "LE"&('N'+$80)
defm "SI"&('N'+$80)
defm "CO"&('S'+$80)
defm "TA"&('N'+$80)
defm "AS"&('N'+$80)
defm "AC"&('S'+$80)
defm "AT"&('N'+$80)
defm "L"&('N'+$80)
defm "EX"&('P'+$80)
defm "IN"&('T'+$80)
defm "SQ"&('R'+$80)
defm "SG"&('N'+$80)
defm "AB"&('S'+$80)
defm "PEE"&('K'+$80)
defm "I"&('N'+$80)
defm "US"&('R'+$80)
defm "STR"&('$'+$80)
defm "CHR"&('$'+$80)
defm "NO"&('T'+$80)
defm "BI"&('N'+$80)
defm "O"&('R'+$80)
defm "AN"&('D'+$80)
defm "<"&('='+$80)
defm ">"&('='+$80)
defm "<"&('>'+$80)
defm "LIN"&('E'+$80)
.l010f defm "THE"&('N'+$80)
defm "T"&('O'+$80)
defm "STE"&('P'+$80)
defm "DEF F"&('N'+$80)
defm "CA"&('T'+$80)
defm "FORMA"&('T'+$80)
defm "MOV"&('E'+$80)
defm "ERAS"&('E'+$80)
defm "OPEN "&('#'+$80)
defm "CLOSE "&('#'+$80)
defm "MERG"&('E'+$80)
defm "VERIF"&('Y'+$80)
defm "BEE"&('P'+$80)
defm "CIRCL"&('E'+$80)
defm "IN"&('K'+$80)
defm "PAPE"&('R'+$80)
defm "FLAS"&('H'+$80)
defm "BRIGH"&('T'+$80)
defm "INVERS"&('E'+$80)
defm "OVE"&('R'+$80)
defm "OU"&('T'+$80)
defm "LPRIN"&('T'+$80)
defm "LLIS"&('T'+$80)
defm "STO"&('P'+$80)
defm "REA"&('D'+$80)
defm "DAT"&('A'+$80)
defm "RESTOR"&('E'+$80)
defm "NE"&('W'+$80)
defm "BORDE"&('R'+$80)
defm "CONTINU"&('E'+$80)
defm "DI"&('M'+$80)
defm "RE"&('M'+$80)
defm "FO"&('R'+$80)
defm "GO T"&('O'+$80)
defm "GO SU"&('B'+$80)
defm "INPU"&('T'+$80)
defm "LOA"&('D'+$80)
defm "LIS"&('T'+$80)
defm "LE"&('T'+$80)
defm "PAUS"&('E'+$80)
defm "NEX"&('T'+$80)
defm "POK"&('E'+$80)
defm "PRIN"&('T'+$80)
defm "PLO"&('T'+$80)
defm "RU"&('N'+$80)
defm "SAV"&('E'+$80)
defm "RANDOMIZ"&('E'+$80)
defm "I"&('F'+$80)
defm "CL"&('S'+$80)
defm "DRA"&('W'+$80)
defm "CLEA"&('R'+$80)
defm "RETUR"&('N'+$80)
defm "COP"&('Y'+$80)
; The L-mode keytable with CAPS-SHIFT
.l0205 defm "BHY65TGV"
defm "NJU74RFC"
defm "MKI83EDX"
defm $0e&"LO92WSZ"
defm " "&$0d&"P01QA"
; The extended-mode keytable (unshifted letters)
.l022c defb $e3,$c4,$e0,$e4
defb $b4,$bc,$bd,$bb
defb $af,$b0,$b1,$c0
defb $a7,$a6,$be,$ad
defb $b2,$ba,$e5,$a5
defb $c2,$e1,$b3,$b9
defb $c1,$b8
; The extended mode keytable (shifted letters)
.l0246 defb $7e,$dc,$da,$5c
defb $b7,$7b,$7d,$d8
defb $bf,$ae,$aa,$ab
defb $dd,$de,$df,$7f
defb $b5,$d6,$7c,$d5
defb $5d,$db,$b6,$d9
defb $5b,$d7
; The control code keytable (CAPS-SHIFTed digits)
.l0260 defb $0c,$07,$06,$04
defb $05,$08,$0a,$0b
defb $09,$0f
; The symbol code keytable (letters with symbol shift)
.l026a defb $e2,$2a,$3f,$cd
defb $c8,$cc,$cb,$5e
defb $ac,$2d,$2b,$3d
defb $2e,$2c,$3b,$22
defb $c7,$3c,$c3,$3e
defb $c5,$2f,$c9,$60
defb $c6,$3a
; The extended mode keytable (SYM-SHIFTed digits)
.l0284 defb $d0,$ce,$a8,$ca
defb $d3,$d4,$d1,$d2
defb $a9,$cf
; The "keyboard scanning" subroutine
; On exit E contains keyvalue $00 to $27 (or $ff=no-key)
; D may contain a shift value
; Z is set unless more than two keys are pressed, or two keys are pressed
; and neither is a shift key
.l028e ld l,$2f ; initial key value ($2f first line...$28)
ld de,$ffff ; "no key"
ld bc,$fefe ; C=port, B=counter
.l0296 in a,(c) ; get port value
cpl
and $1f ; mask keyboard bits
jr z,l02ab ; forward if none pressed this line
ld h,a ; save keybits
ld a,l ; get initial key value
.l029f inc d
ret nz ; exit if 3 keys pressed
.l02a1 sub $08
srl h
jr nc,l02a1 ; subtract 8 from value until a keybit found
ld d,e ; D=earlier key value
ld e,a ; E=key value
jr nz,l029f ; back for more keys in this line
.l02ab dec l ; reduce initial key value for next line
rlc b
jr c,l0296 ; loop back for further key lines
ld a,d
inc a
ret z ; exit with E=keyval if only one key (or none)
cp $28
ret z ; exit if D=caps shift
cp $19
ret z ; or sym shift
ld a,e
ld e,d
ld d,a
cp $18 ; exit with Z set if 2nd key was sym shift
ret
; The "keyboard" subroutine
; This is called every maskable interrupt to scan the keyboard
; The keyboard state is held in two sets: KSTATE to KSTATE+3 and
; KSTATE+4 to KSTATE+7, to allow for detection of new key within
; repeat period of previous key
; KSTATE+0/4 = "main" keycode (free=$ff)
; KSTATE+1/5 = 5 call counter before becoming free
; KSTATE+2/6 = repeat delay period
; KSTATE+3/7 = decoded key value
.l02bf call l028e ; get DE=key values
ret nz ; exit if none/bad
ld hl,KSTATE ; first set of keystates
.l02c6 bit 7,(hl)
jr nz,l02d1 ; move on if free
inc hl
dec (hl) ; decrement 5-call counter
dec hl
jr nz,l02d1
ld (hl),$ff ; flag as free if 5 calls done
.l02d1 ld a,l
ld hl,KSTATE+$04
cp l
jr nz,l02c6 ; loop back to consider second set
call l031e ; make tests
ret nc ; exit if no key
ld hl,KSTATE
cp (hl)
jr z,l0310 ; move on if repeat in first set
ex de,hl
ld hl,KSTATE+$04
cp (hl)
jr z,l0310 ; move on if repeat in second set
bit 7,(hl)
jr nz,l02f1 ; use second set for new key if free
ex de,hl
bit 7,(hl)
ret z ; return if first set not free for new key
.l02f1 ld e,a ; E=keyvalue
ld (hl),a ; store in KSTATE+0/4
inc hl
ld (hl),$05 ; initialise 5-call counter in KSTATE+1/5
inc hl
ld a,(REPDEL)
ld (hl),a ; initialise KSTATE+2/6 to REPDEL
inc hl
ld c,(iy+$07) ; get MODE
ld d,(iy+$01) ; get FLAGS
push hl
call l0333 ; decode value
pop hl
ld (hl),a ; store in KSTATE+3/7
.l0308 ld (LAST_K),a ; store deocoded value in LAST_K
set 5,(iy+$01) ; signal a "new key" in FLAGS
ret
.l0310 inc hl
ld (hl),$05 ; reset 5-call counter
inc hl
dec (hl) ; decrement repeat delay period
ret nz ; exit if time not up yet
ld a,(REPPER)
ld (hl),a ; future repeat delay is REPPER
inc hl
ld a,(hl) ; get decoded value
jr l0308 ; jump to store it
; The "K-test" subroutine
; exit with Carry reset if no key, else A="main" code, B=shift byte
.l031e ld b,d ; B=shift byte
ld d,$00
ld a,e
cp $27
ret nc ; exit if key was "no key" or CAPS only
cp $18
jr nz,l032c ; move on unless second key was SYM shift
bit 7,b
ret nz ; exit if SYM only
.l032c ld hl,l0205
add hl,de
ld a,(hl) ; "main" code from L-mode keytable
scf
ret
; The "keyboard decoding" subroutine
; On entry, E="main" code, D=(FLAGS), C=(MODE) and B=shift byte
; On exit, A=decoded key code
.l0333 ld a,e
cp $3a
jr c,l0367 ; jump on for non-letters
dec c ; decrement mode value
jp m,l034f ; move forward if "K","L" or "C"
jr z,l0341 ; move forward if "E" mode
add a,$4f ; convert key to graphics character
ret
.l0341 ld hl,l022c-'A' ; get start of unshifted E-mode table
inc b
jr z,l034a
ld hl,l0246-'A' ; for a shift key, use shifted E-mode table
.l034a ld d,$00
add hl,de
ld a,(hl) ; get decoded key from offset into tables
ret
.l034f ld hl,l026a-'A' ; get start of symbol-shifted letter table
bit 0,b
jr z,l034a ; use if symbol shift pressed
bit 3,d
jr z,l0364 ; move forward for "K" mode
bit 3,(iy+$30)
ret nz ; exit with main code if caps lock set
inc b
ret nz ; or if caps shift pressed
add a,$20 ; else convert to lower-case
ret
.l0364 add a,$a5 ; convert main letter code to keyword token
ret
.l0367 cp '0'
ret c ; exit with ENTER, SPACE or EXTEND
dec c ; decrement mode value
jp m,l039d ; move on if "K", "L" or "C"
jr nz,l0389 ; move on if "G", else we are in "E" mode
ld hl,l0284-'0' ; get start of E-mode sym-shifted number table
bit 5,b
jr z,l034a ; use if symbol shift pressed
cp '8'
jr nc,l0382 ; move on if 8 or 9
sub $20 ; A=paper colour code $10-$17
inc b
ret z ; exit if caps shift not pressed
add a,$08 ; else use A=ink colour code $18-$1f
ret
.l0382 sub $36 ; convert '8' or '9' to BRIGHT codes $02,$03
inc b
ret z ; exit if caps shift not pressed
add a,$fe ; else use FLASH codes $00,$01
ret
.l0389 ld hl,l0260-'0' ; get start of caps-shifted number table
cp '9'
jr z,l034a ; use for GRAPHICS
cp '0'
jr z,l034a ; or DELETE
and $07
add a,$80 ; convert to unshifted block graphic $80-$87
inc b
ret z ; exit for no shift key
xor $0f ; else convert to shifted graphic $88-$8f
ret
.l039d inc b
ret z ; exit with digit if no shifts
bit 5,b
ld hl,l0260-'0' ; get start of caps-shifted number table
jr nz,l034a ; use if caps shift pressed
sub $10 ; else get symbol code $20 to $29
cp '"'
jr z,l03b2 ; move on if sym shift-2
cp ' '
ret nz ; exit if not sym shift-0
ld a,'_' ; use "_" for sym shift-0
ret
.l03b2 ld a,'@' ; use "@" for sym shift-2
ret
; The "Beeper" subroutine
; On entry, DE=freq*time, and HL=(Tstates in timing loop)/4
.l03b5 di ; disable interrupts for clean sound
ld a,l
srl l
srl l ; L=counter for every 16 Tstates
cpl
and $03
ld c,a
ld b,$00 ; BC=4-remainder
.l03c1 ld ix,l03d1
add ix,bc ; IX=entry point in timing loop
ld a,(BORDCR)
and $38
rrca
rrca
rrca
or $08 ; A=border colour, with MIC off
.l03d1 nop ; 3x4-Tstates for "remainder" part of loop
nop
nop
inc b ; the timing loop
inc c
.l03d6 dec c
jr nz,l03d6
ld c,$3f
dec b
jp nz,l03d6
xor $10 ; flip loudspeaker bit
out ($fe),a
ld b,h ; reset B counter
ld c,a ; save A
bit 4,a
jr nz,l03f2 ; jump if at half-cycle point
ld a,d
or e
jr z,l03f6 ; move on if finished
ld a,c
ld c,l ; reset C counter
dec de ; decrement pass counter
jp (ix) ; back to timing loop
.l03f2 ld c,l ; reset C counter
inc c ; compensate for shorter path
jp (ix) ; back to timing loop
.l03f6 ei ; re-enable interrupts
ret
; The "BEEP" command routine
.l03f8 rst $28 ; start FP calculator with stack: t,P
defb duplicate ; t,P,P
defb int ; t,P,i
defb st_mem_0 ; save i in mem0
defb subtract ; t,p
defb stk_data ; stack value K=0.0577622606
defb $ec,$6c,$98,$1f,$f5
defb multiply ; t,pK
defb stk_one ; t,pK,1
defb addition ; t,pK+1
defb end_calc
ld hl,MEMBOT
ld a,(hl) ; A=exponent of i (integer part of pitch)
and a
jr nz,l046c ; give error B if not integral (short) form
inc hl
ld c,(hl) ; C=sign byte
inc hl
ld b,(hl)
ld a,b ; A=B=low byte
rla
sbc a,a
cp c
jr nz,l046c ; give error B if not -128<=i<=127
inc hl
cp (hl)
jr nz,l046c ; ditto
ld a,b
add a,$3c
jp p,l0425
jp po,l046c ; error B if i in range -128 to -61
.l0425 ld b,$fa ; start 6 octaves below middle C
.l0427 inc b
sub $0c
jr nc,l0427 ; get to correct octave
add a,$0c
push bc ; save octave number
ld hl,l046e ; semitone table
call l3406 ; pass "Ath" value
call l33b4 ; to calculator stack (call it C)
rst $28 ; start FP calculator with: t,pK+1,C
defb multiply ; t,C(pK+1)
defb end_calc
pop af ; A=octave
add a,(hl)
ld (hl),a ; add into exponent of C(pK+1)
rst $28 ; start FP calculator with: t,f
defb st_mem_0 ; save f in mem0
defb delete ; t
defb duplicate ; t,t
defb end_calc
call l1e94
cp $0b
jr nc,l046c ; error if INT t > $0a
rst $28 ; start FP calculator with: t
defb get_mem_0 ; t,f
defb multiply ; f*t
defb get_mem_0 ; f*t,f
defb stk_data ; stack 3.5*10^6/8 (437,500)
defb $80,$43,$55,$9f,$80
defb exchange ; f*t,437500,f
defb division ; f*t,437500/f
defb stk_data ; stack 30.125
defb $35,$71
defb subtract ; f*t,437500/f-30.125
defb end_calc
call l1e99 ; get BC=timing loop value
push bc
call l1e99 ; get BC=f*t
pop hl ; HL=timing loop value
ld d,b ; DE=f*t
ld e,c
ld a,d
or e
ret z ; exit if no time
dec de
jp l03b5 ; exit through Beeper subroutine
.l046c rst $8
defb $0a ; error B - Integer out of range
; The semitone table
.l046e defb $89,$02,$d0,$12,$86 ; 261.63 C
defb $89,$0a,$97,$60,$75 ; 277.18 C#
defb $89,$12,$d5,$17,$1f ; 293.66 D
defb $89,$1b,$90,$41,$02 ; 311.13 D#
defb $89,$24,$d0,$53,$ca ; 329.63 E
defb $89,$2e,$9d,$36,$b1 ; 349.23 F
defb $89,$38,$ff,$49,$3e ; 369.99 F#
defb $89,$43,$ff,$6a,$73 ; 392.00 G
defb $89,$4f,$a7,$00,$54 ; 415.30 G#
defb $89,$5c,$00,$00,$00 ; 440.00 A
defb $89,$69,$14,$f6,$24 ; 466.16 A#
defb $89,$76,$f1,$10,$05 ; 493.88 B
; The following is the "Program Name" subroutine, leftover from
; the ZX81 ROM but not used (24 bytes long)
.l04aa call $24fb
ld a,($5c3b)
add a,a
jp m,$1c8a
pop hl
ret nc
push hl
call $2bf1
ld h,d
ld l,e
dec c
ret m
add hl,bc
set 7,(hl)
ret
.l04c2 ld hl,$053f
push hl
ld hl,$1f80
bit 7,a
jr z,l04d0 ; (3)
ld hl,$0c98
.l04d0 ex af,af'
inc de
dec ix
di
ld a,$02
ld b,a
.l04d8 djnz $04d8 ; (-2)
out ($fe),a
xor $0f
ld b,$a4
dec l
jr nz,l04d8 ; (-11)
dec b
.l04e4 dec h
.l04e5 jp p,$04d8
ld b,$2f
.l04ea djnz $04ea ; (-2)
out ($fe),a
ld a,$0d
ld b,$37
.l04f2 djnz $04f2 ; (-2)
out ($fe),a
ld bc,$3b0e
ex af,af'
ld l,a
jp $0507
.l04fe ld a,d
or e
jr z,l050e ; (12)
ld l,(ix+$00)
.l0505 ld a,h
xor l
.l0507 ld h,a
ld a,$01
scf
jp $0525
.l050e ld l,h
jr l0505 ; (-12)
.l0511 ld a,c
bit 7,b
.l0514 djnz $0514 ; (-2)
jr nc,l051c ; (4)
ld b,$42
.l051a djnz $051a ; (-2)
.l051c out ($fe),a
ld b,$3e
jr nz,l0511 ; (-17)
dec b
xor a
inc a
.l0525 rl l
jp nz,$0514
dec de
inc ix
ld b,$31
ld a,$7f
in a,($fe)
rra
ret nc
ld a,d
inc a
jp nz,$04fe
ld b,$3b
.l053c djnz $053c ; (-2)
ret
push af
ld a,(BORDCR)
and $38
rrca
rrca
rrca
out ($fe),a
ld a,$7f
in a,($fe)
rra
ei
jr c,l0554 ; (2)
rst $8
inc c
.l0554 pop af
ret
.l0556 inc d
ex af,af'
dec d
di
ld a,$0f
out ($fe),a
ld hl,$053f
push hl
in a,($fe)
rra
and $20
or $02
ld c,a
cp a
.l056b ret nz
.l056c call $05e7
jr nc,l056b ; (-6)
ld hl,$0415
.l0574 djnz $0574 ; (-2)
dec hl
ld a,h
or l
jr nz,l0574 ; (-7)
call $05e3
jr nc,l056b ; (-21)
.l0580 ld b,$9c
call $05e3
jr nc,l056b ; (-28)
ld a,$c6
cp b
jr nc,l056c ; (-32)
inc h
jr nz,l0580 ; (-15)
.l058f ld b,$c9
call $05e7
jr nc,l056b ; (-43)
ld a,b
cp $d4
jr nc,l058f ; (-12)
call $05e7
ret nc
ld a,c
xor $03
ld c,a
ld h,$00
ld b,$b0
jr l05c8 ; (31)
.l05a9 ex af,af'
jr nz,l05b3 ; (7)
jr nc,l05bd ; (15)
ld (ix+$00),l
jr l05c2 ; (15)
.l05b3 rl c
xor l
ret nz
ld a,c
rra
ld c,a
inc de
jr l05c4 ; (7)
.l05bd ld a,(ix+$00)
xor l
ret nz
.l05c2 inc ix
.l05c4 dec de
ex af,af'
ld b,$b2
.l05c8 ld l,$01
.l05ca call $05e3
ret nc
ld a,$cb
cp b
rl l
ld b,$b0
jp nc,$05ca
ld a,h
xor l
ld h,a
ld a,d
or e
jr nz,l05a9 ; (-54)
ld a,h
cp $01
ret
.l05e3 call $05e7
ret nc
.l05e7 ld a,$16
.l05e9 dec a
jr nz,l05e9 ; (-3)
and a
.l05ed inc b
ret z
ld a,$7f
in a,($fe)
rra
ret nc
xor c
and $20
jr z,l05ed ; (-13)
ld a,c
cpl
ld c,a
and $07
or $08
out ($fe),a
scf
ret
.l0605 pop af
ld a,(T_ADDR)
sub $e0
ld (T_ADDR),a
call $1c8c
call $2530
jr z,l0652 ; (60)
ld bc,$0011
ld a,(T_ADDR)
and a
jr z,l0621 ; (2)
ld c,$22
.l0621 rst $30
.l0622 push de
pop ix
ld b,$0b
ld a,$20
.l0629 ld (de),a
inc de
djnz $0629 ; (-4)
ld (ix+$01),$ff
call $2bf1
ld hl,$fff6
dec bc
add hl,bc
inc bc
jr nc,l064b ; (15)
ld a,(T_ADDR)
and a
defb $20
defb 2
rst $8
ld c,$78
or c
jr z,l0652 ; (10)
ld bc,$000a
.l064b push ix
pop hl
inc hl
ex de,hl
ldir
.l0652 rst $18
cp $e4
jr nz,l06a0 ; (73)
ld a,(T_ADDR)
cp $03
jp z,$1c8a
rst $20
call $28b2
set 7,c
defb $30
defb 11
ld hl,$0000
ld a,(T_ADDR)
dec a
jr z,l0685 ; (21)
rst $8
ld bc,$8ac2
inc e
call $2530
jr z,l0692 ; (24)
inc hl
ld a,(hl)
ld (ix+$0b),a
inc hl
ld a,(hl)
ld (ix+$0c),a
inc hl
.l0685 ld (ix+$0e),c
ld a,$01
bit 6,c
jr z,l068f ; (1)
inc a
.l068f ld (ix+$00),a
.l0692 ex de,hl
rst $20
cp $29
defb $20
defb -38
rst $20
call $1bee
ex de,hl
jp $075a
.l06a0 cp $aa
jr nz,l06c3 ; (31)
ld a,(T_ADDR)
cp $03
jp z,$1c8a
rst $20
call $1bee
ld (ix+$0b),$00
ld (ix+$0c),$1b
ld hl,$4000
ld (ix+$0d),l
ld (ix+$0e),h
jr l0710 ; (77)
.l06c3 cp $af
jr nz,l0716 ; (79)
ld a,(T_ADDR)
cp $03
jp z,$1c8a
rst $20
call $2048
jr nz,l06e1 ; (12)
ld a,(T_ADDR)
and a
jp z,$1c8a
call $1ce6
jr l06f0 ; (15)
.l06e1 call $1c82
rst $18
cp $2c
jr z,l06f5 ; (12)
ld a,(T_ADDR)
and a
jp z,$1c8a
.l06f0 call $1ce6
jr l06f9 ; (4)
.l06f5 rst $20
call $1c82
.l06f9 call $1bee
call $1e99
ld (ix+$0b),c
ld (ix+$0c),b
call $1e99
ld (ix+$0d),c
ld (ix+$0e),b
ld h,b
ld l,c
.l0710 ld (ix+$00),$03
jr l075a ; (68)
.l0716 cp $ca
jr z,l0723 ; (9)
call $1bee
ld (ix+$0e),$80
jr l073a ; (23)
.l0723 ld a,(T_ADDR)
and a
jp nz,$1c8a
rst $20
call $1c82
call $1bee
call $1e99
ld (ix+$0d),c
ld (ix+$0e),b
.l073a ld (ix+$00),$00
ld hl,(E_LINE)
ld de,(PROG)
scf
sbc hl,de
ld (ix+$0b),l
ld (ix+$0c),h
ld hl,(VARS)
sbc hl,de
ld (ix+$0f),l
ld (ix+$10),h
ex de,hl
.l075a ld a,(T_ADDR)
and a
jp z,$0970
push hl
ld bc,$0011
add ix,bc
.l0767 push ix
ld de,$0011
xor a
scf
call $0556
pop ix
jr nc,l0767 ; (-14)
ld a,$fe
call $1601
ld (iy+$52),$03
ld c,$80
ld a,(ix+$00)
cp (ix-$11)
jr nz,l078a ; (2)
ld c,$f6
.l078a cp $04
jr nc,l0767 ; (-39)
ld de,$09c0
push bc
call $0c0a
pop bc
push ix
pop de
ld hl,$fff0
add hl,de
ld b,$0a
ld a,(hl)
inc a
jr nz,l07a6 ; (3)
ld a,c
add a,b
ld c,a
.l07a6 inc de
ld a,(de)
cp (hl)
inc hl
jr nz,l07ad ; (1)
inc c
.l07ad rst $10
djnz $07a6 ; (-10)
bit 7,c
jr nz,l0767 ; (-77)
ld a,$0d
rst $10
pop hl
ld a,(ix+$00)
cp $03
jr z,l07cb ; (12)
ld a,(T_ADDR)
dec a
jp z,$0808
cp $02
jp z,$08b6
.l07cb push hl
ld l,(ix-$06)
ld h,(ix-$05)
ld e,(ix+$0b)
ld d,(ix+$0c)
ld a,h
or l
jr z,l07e9 ; (13)
sbc hl,de
jr c,l0806 ; (38)
jr z,l07e9 ; (7)
ld a,(ix+$00)
cp $03
jr nz,l0806 ; (29)
.l07e9 pop hl
ld a,h
or l
jr nz,l07f4 ; (6)
ld l,(ix+$0d)
ld h,(ix+$0e)
.l07f4 push hl
pop ix
ld a,(T_ADDR)
cp $02
scf
jr nz,l0800 ; (1)
and a
.l0800 ld a,$ff
.l0802 call $0556
ret c
.l0806 rst $8
ld a,(de)
.l0808 ld e,(ix+$0b)
ld d,(ix+$0c)
push hl
ld a,h
or l
jr nz,l0819 ; (6)
inc de
inc de
inc de
ex de,hl
jr l0825 ; (12)
.l0819 ld l,(ix-$06)
ld h,(ix-$05)
ex de,hl
scf
sbc hl,de
jr c,l082e ; (9)
.l0825 ld de,$0005
add hl,de
ld b,h
ld c,l
call $1f05
.l082e pop hl
ld a,(ix+$00)
and a
jr z,l0873 ; (62)
ld a,h
or l
jr z,l084c ; (19)
dec hl
ld b,(hl)
dec hl
ld c,(hl)
dec hl
inc bc
inc bc
inc bc
ld (X_PTR),ix
call $19e8
ld ix,(X_PTR)
.l084c ld hl,(E_LINE)
dec hl
ld c,(ix+$0b)
ld b,(ix+$0c)
push bc
inc bc
inc bc
inc bc
ld a,(ix-$03)
push af
call $1655
inc hl
pop af
ld (hl),a
pop de
inc hl
ld (hl),e
inc hl
ld (hl),d
inc hl
push hl
pop ix
scf
ld a,$ff
jp $0802
.l0873 ex de,hl
ld hl,(E_LINE)
dec hl
ld (X_PTR),ix
ld c,(ix+$0b)
ld b,(ix+$0c)
push bc
call $19e5
pop bc
push hl
push bc
call $1655
ld ix,(X_PTR)
inc hl
ld c,(ix+$0f)
ld b,(ix+$10)
add hl,bc
ld (VARS),hl
ld h,(ix+$0e)
ld a,h
and $c0
jr nz,l08ad ; (10)
ld l,(ix+$0d)
ld (NEWPPC),hl
ld (iy+$0a),$00
.l08ad pop de
pop ix
scf
ld a,$ff
jp $0802
.l08b6 ld c,(ix+$0b)
ld b,(ix+$0c)
push bc
inc bc
rst $30
ld (hl),$80
ex de,hl
pop de
push hl
push hl
pop ix
scf
ld a,$ff
call $0802
pop hl
ld de,(PROG)
.l08d2 ld a,(hl)
and $c0
jr nz,l08f0 ; (25)
.l08d7 ld a,(de)
inc de
cp (hl)
inc hl
jr nz,l08df ; (2)
ld a,(de)
cp (hl)
.l08df dec de
dec hl
jr nc,l08eb ; (8)
push hl
ex de,hl
call $19b8
pop hl
jr l08d7 ; (-20)
.l08eb call $092c
jr l08d2 ; (-30)
.l08f0 ld a,(hl)
ld c,a
cp $80
ret z
push hl
ld hl,(VARS)
.l08f9 ld a,(hl)
cp $80
jr z,l0923 ; (37)
cp c
jr z,l0909 ; (8)
.l0901 push bc
call $19b8
pop bc
ex de,hl
jr l08f9 ; (-16)
.l0909 and $e0
cp $a0
jr nz,l0921 ; (18)
pop de
push de
push hl
.l0912 inc hl
inc de
ld a,(de)
cp (hl)
jr nz,l091e ; (6)
rla
jr nc,l0912 ; (-9)
pop hl
jr l0921 ; (3)
.l091e pop hl
jr l0901 ; (-32)
.l0921 ld a,$ff
.l0923 pop de
ex de,hl
inc a
scf
call $092c
jr l08f0 ; (-60)
.l092c jr nz,l093e ; (16)
ex af,af'
ld (X_PTR),hl
ex de,hl
call $19b8
call $19e8
ex de,hl
ld hl,(X_PTR)
ex af,af'
.l093e ex af,af'
push de
call $19b8
ld (X_PTR),hl
ld hl,(PROG)
ex (sp),hl
push bc
ex af,af'
jr c,l0955 ; (7)
dec hl
call $1655
inc hl
jr l0958 ; (3)
.l0955 call $1655
.l0958 inc hl
pop bc
pop de
ld (PROG),de
ld de,(X_PTR)
push bc
push de
ex de,hl
ldir
pop hl
pop bc
push de
call $19e8
pop de
ret
.l0970 push hl
ld a,$fd
call $1601
xor a
ld de,$09a1
call $0c0a
set 5,(iy+$02)
call $15d4
push ix
ld de,$0011
xor a
call $04c2
pop ix
ld b,$32
.l0991 halt
djnz l0991
ld e,(ix+$0b)
ld d,(ix+$0c)
ld a,$ff
pop ix
jp l04c2
.l09a1 defb $80
defm "Press REC & PLAY, then any key"&$ae
defm $0d&"Program:"&$a0
defm $0d&"Number array:"&$a0
defm $0d&"Character array:"&$a0
defm $0d&"Bytes:"&$a0
.l09f4 defb $cd
inc bc
dec bc
cp $20
jp nc,$0ad9
cp $06
jr c,l0a69 ; (105)
cp $18
jr nc,l0a69 ; (101)
ld hl,$0a0b
ld e,a
ld d,$00
add hl,de
ld e,(hl)
add hl,de
push hl
jp $0b03
ld c,(hl)
ld d,a
djnz $0a3e ; (41)
ld d,h
ld d,e
ld d,d
scf
ld d,b
ld c,a
.l0a1b ld e,a
ld e,(hl)
ld e,l
ld e,h
ld e,e
ld e,d
ld d,h
ld d,e
inc c
ld a,$22
cp c
jr nz,l0a3a ; (17)
.l0a29 bit 1,(iy+$01)
jr nz,l0a38 ; (9)
inc b
ld c,$02
ld a,$18
cp b
.l0a35 jr nz,l0a3a ; (3)
dec b
.l0a38 ld c,$21
.l0a3a jp $0dd9
ld a,(P_FLAG)
push af
ld (iy+$57),$01
ld a,$20
.l0a47 call $0b65
pop af
ld (P_FLAG),a
ret
bit 1,(iy+$01)
jp nz,$0ecd
ld c,$21
call $0c55
dec b
jp $0dd9
call $0b03
ld a,c
dec a
dec a
and $10
jr l0ac3 ; (90)
.l0a69 ld a,$3f
defb $18
defb 108
ld de,$0a87
ld (TVDATA+1),a
jr l0a80 ; (11)
ld de,$0a6d
jr l0a7d ; (3)
ld de,$0a87
.l0a7d ld (TVDATA),a
.l0a80 ld hl,(CURCHL)
ld (hl),e
inc hl
ld (hl),d
ret
ld de,$09f4
call $0a80
ld hl,(TVDATA)
ld d,a
ld a,l
cp $16
jp c,$2211
jr nz,l0ac2 ; (41)
ld b,h
ld c,d
ld a,$1f
sub c
jr c,l0aac ; (12)
add a,$02
ld c,a
bit 1,(iy+$01)
jr nz,l0abf ; (22)
ld a,$16
sub b
.l0aac jp c,$1e9f
inc a
ld b,a
inc b
bit 0,(iy+$02)
jp nz,$0c55
cp (iy+$31)
jp c,$0c86
.l0abf jp $0dd9
.l0ac2 ld a,h
.l0ac3 call $0b03
add a,c
dec a
and $1f
ret z
ld d,a
set 0,(iy+$01)
.l0ad0 ld a,$20
call $0c3b
dec d
jr nz,l0ad0 ; (-8)
ret
.l0ad9 call $0b24
.l0adc bit 1,(iy+$01)
jr nz,l0afc ; (26)
bit 0,(iy+$02)
jr nz,l0af0 ; (8)
ld (S_POSN),bc
ld (DF_CC),hl
ret
.l0af0 ld (SPOSNL),bc
ld (ECHO_E),bc
ld (DF_CCL),hl
ret
.l0afc ld (iy+$45),c
ld (PR_CC),hl
ret
.l0b03 bit 1,(iy+$01)
jr nz,l0b1d ; (20)
ld bc,(S_POSN)
ld hl,(DF_CC)
bit 0,(iy+$02)
ret z
ld bc,(SPOSNL)
ld hl,(DF_CCL)
ret
.l0b1d ld c,(iy+$45)
ld hl,(PR_CC)
ret
.l0b24 cp $80
jr c,l0b65 ; (61)
cp $90
jr nc,l0b52 ; (38)
ld b,a
call $0b38
call $0b03
ld de,MEMBOT
jr l0b7f ; (71)
.l0b38 ld hl,MEMBOT
call $0b3e
.l0b3e rr b
sbc a,a
and $0f
ld c,a
rr b
sbc a,a
and $f0
or c
ld c,$04
.l0b4c ld (hl),a
inc hl
dec c
jr nz,l0b4c ; (-5)
ret
.l0b52 jp $3a7e
nop
.l0b56 add a,$15
push bc
ld bc,(UDG)
jr l0b6a ; (11)
.l0b5f call $0c10
jp $0b03
.l0b65 push bc
ld bc,(CHARS)
.l0b6a ex de,hl
ld hl,FLAGS
res 0,(hl)
cp $20
jr nz,l0b76 ; (2)
set 0,(hl)
.l0b76 ld h,$00
ld l,a
add hl,hl
add hl,hl
add hl,hl
add hl,bc
pop bc
ex de,hl
.l0b7f ld a,c
dec a
ld a,$21
jr nz,l0b93 ; (14)
dec b
ld c,a
bit 1,(iy+$01)
jr z,l0b93 ; (6)
push de
call $0ecd
pop de
ld a,c
.l0b93 cp c
push de
call z,$0c55
pop de
push bc
push hl
ld a,(P_FLAG)
ld b,$ff
rra
jr c,l0ba4 ; (1)
inc b
.l0ba4 rra
rra
sbc a,a
ld c,a
ld a,$08
and a
bit 1,(iy+$01)
jr z,l0bb6 ; (5)
set 1,(iy+$30)
scf
.l0bb6 ex de,hl
.l0bb7 ex af,af'
ld a,(de)
and b
xor (hl)
xor c
ld (de),a
ex af,af'
jr c,l0bd3 ; (19)
inc d
.l0bc1 inc hl
dec a
jr nz,l0bb7 ; (-14)
ex de,hl
dec h
bit 1,(iy+$01)
call z,$0bdb
pop hl
pop bc
dec c
inc hl
ret
.l0bd3 ex af,af'
ld a,$20
add a,e
ld e,a
ex af,af'
jr l0bc1 ; (-26)
.l0bdb ld a,h
rrca
rrca
rrca
and $03
or $58
ld h,a
ld de,(ATTR_T)
ld a,(hl)
xor e
and d
xor e
bit 6,(iy+$57)
jr z,l0bfa ; (8)
and $c7
bit 2,a
jr nz,l0bfa ; (2)
xor $38
.l0bfa bit 4,(iy+$57)
jr z,l0c08 ; (8)
and $f8
bit 5,a
jr nz,l0c08 ; (2)
xor $07
.l0c08 ld (hl),a
ret
.l0c0a push hl
ld h,$00
ex (sp),hl
jr l0c14 ; (4)
.l0c10 ld de,$0095
push af
.l0c14 call $0c41
.l0c17 jr c,l0c22 ; (9)
ld a,$20
bit 0,(iy+$01)
call z,$0c3b
.l0c22 ld a,(de)
and $7f
call $0c3b
ld a,(de)
inc de
add a,a
jr nc,l0c22 ; (-11)
pop de
cp $48
jr z,l0c35 ; (3)
cp $82
ret c
.l0c35 ld a,d
cp $03
ret c
ld a,$20
.l0c3b push de
exx
rst $10
exx
pop de
ret
.l0c41 push af
ex de,hl
inc a
.l0c44 bit 7,(hl)
inc hl
jr z,l0c44 ; (-5)
dec a
jr nz,l0c44 ; (-8)
ex de,hl
pop af
cp $20
ret c
ld a,(de)
sub $41
ret
.l0c55 bit 1,(iy+$01)
ret nz
ld de,$0dd9
push de
ld a,b
bit 0,(iy+$02)
jp nz,$0d02
cp (iy+$31)
jr c,l0c86 ; (27)
ret nz
bit 4,(iy+$02)
jr z,l0c88 ; (22)
ld e,(iy+$2d)
dec e
jr z,l0cd2 ; (90)
ld a,$00
call $1601
ld sp,(LIST_SP)
res 4,(iy+$02)
ret
.l0c86 rst $8
inc b
.l0c88 dec (iy+$52)
jr nz,l0cd2 ; (69)
ld a,$18
sub b
ld (SCR_CT),a
ld hl,(ATTR_T)
push hl
ld a,(P_FLAG)
push af
ld a,$fd
call $1601
xor a
ld de,$0cf8
call $0c0a
set 5,(iy+$02)
ld hl,FLAGS
set 3,(hl)
res 5,(hl)
exx
call $15d4
exx
cp $20
jr z,l0d00 ; (69)
cp $e2
jr z,l0d00 ; (65)
or $20
cp $6e
jr z,l0d00 ; (59)
ld a,$fe
call $1601
pop af
ld (P_FLAG),a
pop hl
ld (ATTR_T),hl
.l0cd2 call $0dfe
ld b,(iy+$31)
inc b
ld c,$21
push bc
call $0e9b
ld a,h
rrca
rrca
rrca
and $03
or $58
ld h,a
ld de,$5ae0
ld a,(de)
ld c,(hl)
ld b,$20
ex de,hl
.l0cf0 ld (de),a
ld (hl),c
inc de
inc hl
djnz $0cf0 ; (-6)
pop bc
ret
add a,b
ld (hl),e
ld h,e
ld (hl),d
ld l,a
ld l,h
ld l,h
cp a
.l0d00 rst $8
inc c
.l0d02 cp $02
jr c,l0c86 ; (-128)
add a,(iy+$31)
sub $19
ret nc
neg
push bc
ld b,a
ld hl,(ATTR_T)
push hl
ld hl,(P_FLAG)
push hl
call $0d4d
ld a,b
.l0d1c push af
ld hl,DF_SZ
ld b,(hl)
ld a,b
inc a
ld (hl),a
ld hl,S_POSN+1
cp (hl)
jr c,l0d2d ; (3)
inc (hl)
ld b,$18
.l0d2d call $0e00
pop af
dec a
jr nz,l0d1c ; (-24)
pop hl
ld (iy+$57),l
pop hl
ld (ATTR_T),hl
ld bc,(S_POSN)
res 0,(iy+$02)
call $0dd9
set 0,(iy+$02)
pop bc
ret
.l0d4d xor a
ld hl,(ATTR_P)
bit 0,(iy+$02)
jr z,l0d5b ; (4)
ld h,a
ld l,(iy+$0e)
.l0d5b ld (ATTR_T),hl
ld hl,P_FLAG
jr nz,l0d65 ; (2)
ld a,(hl)
rrca
.l0d65 xor (hl)
and $55
xor (hl)
ld (hl),a
ret
.l0d6b call $0daf
.l0d6e ld hl,TV_FLAG
res 5,(hl)
set 0,(hl)
call $0d4d
ld b,(iy+$31)
call $0e44
ld hl,$5ac0
ld a,(ATTR_P)
dec b
jr l0d8e ; (7)
.l0d87 ld c,$20
.l0d89 dec hl
ld (hl),a
dec c
jr nz,l0d89 ; (-5)
.l0d8e djnz $0d87 ; (-9)
ld (iy+$31),$02
.l0d94 ld a,$fd
call $1601
ld hl,(CURCHL)
ld de,$09f4
and a
.l0da0 ld (hl),e
inc hl
ld (hl),d
inc hl
ld de,$10a8
ccf
jr c,l0da0 ; (-10)
ld bc,$1721
jr l0dd9 ; (42)
.l0daf ld hl,$0000
ld (COORDS),hl
res 0,(iy+$30)
call $0d94
ld a,$fe
call $1601
call $0d4d
ld b,$18
call $0e44
ld hl,(CURCHL)
ld de,$09f4
ld (hl),e
inc hl
ld (hl),d
ld (iy+$52),$01
ld bc,$1821
.l0dd9 ld hl,$5b00
bit 1,(iy+$01)
jr nz,l0df4 ; (18)
ld a,b
bit 0,(iy+$02)
jr z,l0dee ; (5)
add a,(iy+$31)
sub $18
.l0dee push bc
ld b,a
call $0e9b
pop bc
.l0df4 ld a,$21
sub c
ld e,a
ld d,$00
add hl,de
jp $0adc
.l0dfe ld b,$17
.l0e00 call $0e9b
ld c,$08
.l0e05 push bc
push hl
ld a,b
and $07
ld a,b
jr nz,l0e19 ; (12)
.l0e0d ex de,hl
ld hl,$f8e0
add hl,de
ex de,hl
ld bc,$0020
dec a
ldir
.l0e19 ex de,hl
ld hl,$ffe0
add hl,de
ex de,hl
ld b,a
and $07
rrca
rrca
rrca
ld c,a
ld a,b
ld b,$00
ldir
ld b,$07
add hl,bc
and $f8
jr nz,l0e0d ; (-37)
pop hl
inc h
pop bc
dec c
jr nz,l0e05 ; (-51)
call $0e88
ld hl,$ffe0
add hl,de
ex de,hl
ldir
ld b,$01
.l0e44 push bc
call $0e9b
ld c,$08
.l0e4a push bc
push hl
ld a,b
.l0e4d and $07
rrca
rrca
rrca
ld c,a
ld a,b
ld b,$00
dec c
ld d,h
ld e,l
ld (hl),$00
inc de
ldir
ld de,$0701
add hl,de
dec a
and $f8
ld b,a
jr nz,l0e4d ; (-27)
pop hl
inc h
pop bc
dec c
jr nz,l0e4a ; (-36)
call $0e88
ld h,d
ld l,e
inc de
ld a,(ATTR_P)
bit 0,(iy+$02)
jr z,l0e80 ; (3)
ld a,(BORDCR)
.l0e80 ld (hl),a
dec bc
ldir
pop bc
ld c,$21
ret
.l0e88 ld a,h
rrca
rrca
rrca
dec a
or $50
ld h,a
ex de,hl
ld h,c
ld l,b
add hl,hl
add hl,hl
add hl,hl
add hl,hl
add hl,hl
ld b,h
ld c,l
ret
.l0e9b ld a,$18
sub b
ld d,a
rrca
rrca
rrca
and $e0
ld l,a
ld a,d
and $18
or $40
ld h,a
ret
di
ld b,$b0
ld hl,$4000
.l0eb2 push hl
push bc
call $0ef4
pop bc
pop hl
inc h
ld a,h
and $07
jr nz,l0ec9 ; (10)
ld a,l
add a,$20
ld l,a
ccf
sbc a,a
and $f8
add a,h
ld h,a
.l0ec9 djnz $0eb2 ; (-25)
jr l0eda ; (13)
.l0ecd di
ld hl,$5b00
ld b,$08
.l0ed3 push bc
call $0ef4
pop bc
djnz $0ed3 ; (-7)
.l0eda ld a,$04
out ($fb),a
ei
.l0edf ld hl,$5b00
ld (iy+$46),l
xor a
ld b,a
.l0ee7 ld (hl),a
inc hl
djnz $0ee7 ; (-4)
res 1,(iy+$30)
ld c,$21
jp $0dd9
.l0ef4 ld a,b
cp $03
sbc a,a
and $02
out ($fb),a
ld d,a
.l0efd call $1f54
jr c,l0f0c ; (10)
ld a,$04
.l0f04 out ($fb),a
ei
call $0edf
rst $8
inc c
.l0f0c in a,($fb)
add a,a
ret m
jr nc,l0efd ; (-21)
ld c,$20
.l0f14 ld e,(hl)
inc hl
ld b,$08
.l0f18 rl d
rl e
rr d
.l0f1e in a,($fb)
rra
jr nc,l0f1e ; (-5)
ld a,d
out ($fb),a
djnz $0f18 ; (-16)
dec c
jr nz,l0f14 ; (-23)
ret
.l0f2c ld hl,(ERR_SP)
push hl
.l0f30 ld hl,$107f
push hl
ld (ERR_SP),sp
call $15d4
push af
ld d,$00
ld e,(iy-$01)
ld hl,$00c8
call $03b5
pop af
ld hl,$0f38
push hl
cp $18
jr nc,l0f81 ; (49)
cp $07
jr c,l0f81 ; (45)
cp $10
jr c,l0f92 ; (58)
ld bc,$0002
ld d,a
cp $16
jr c,l0f6c ; (12)
inc bc
bit 7,(iy+$37)
jp z,$101e
call $15d4
ld e,a
.l0f6c call $15d4
push de
ld hl,(K_CUR)
res 0,(iy+$07)
call $1655
pop bc
inc hl
ld (hl),b
inc hl
ld (hl),c
jr l0f8b ; (10)
.l0f81 res 0,(iy+$07)
ld hl,(K_CUR)
call $1652
.l0f8b ld (de),a
inc de
ld (K_CUR),de
ret
.l0f92 ld e,a
ld d,$00
ld hl,$0f99
add hl,de
ld e,(hl)
add hl,de
push hl
ld hl,(K_CUR)
ret
add hl,bc
ld h,(hl)
ld l,d
ld d,b
or l
ld (hl),b
ld a,(hl)
rst $8
call nc,$492a
ld e,h
bit 5,(iy+$37)
jp nz,$1097
call $196e
call $1695
ld a,d
or e
jp z,$1097
push hl
inc hl
ld c,(hl)
inc hl
ld b,(hl)
ld hl,$000a
add hl,bc
ld b,h
ld c,l
call $1f05
call $1097
ld hl,(CURCHL)
ex (sp),hl
push hl
ld a,$ff
call $1601
pop hl
dec hl
dec (iy+$0f)
call $1855
inc (iy+$0f)
ld hl,(E_LINE)
inc hl
inc hl
inc hl
inc hl
ld (K_CUR),hl
pop hl
call $1615
ret
bit 5,(iy+$37)
jr nz,l1001 ; (8)
ld hl,E_PPC
call $190f
jr l106e ; (109)
.l1001 ld (iy+$00),$10
jr l1024 ; (29)
call $1031
jr l1011 ; (5)
ld a,(hl)
cp $0d
ret z
inc hl
.l1011 ld (K_CUR),hl
ret
call $1031
ld bc,$0001
jp $19e8
.l101e call $15d4
call $15d4
.l1024 pop hl
pop hl
.l1026 pop hl
ld (ERR_SP),hl
bit 7,(iy+$00)
ret nz
ld sp,hl
ret
.l1031 scf
call $1195
sbc hl,de
add hl,de
inc hl
pop bc
ret c
push bc
ld b,h
ld c,l
.l103e ld h,d
ld l,e
inc hl
ld a,(de)
and $f0
cp $10
jr nz,l1051 ; (9)
inc hl
ld a,(de)
sub $17
adc a,$00
jr nz,l1051 ; (1)
inc hl
.l1051 and a
sbc hl,bc
add hl,bc
ex de,hl
jr c,l103e ; (-26)
ret
bit 5,(iy+$37)
ret nz
ld hl,(E_PPC)
call $196e
ex de,hl
call $1695
ld hl,E_PPC+1
call $191c
.l106e call $1795
ld a,$00
jp $1601
bit 7,(iy+$37)
jr z,l1024 ; (-88)
jp $0f81
bit 4,(iy+$30)
jr z,l1026 ; (-95)
ld (iy+$00),$ff
ld d,$00
ld e,(iy-$02)
ld hl,$1a90
call $03b5
jp $0f30
.l1097 push hl
call $1190
dec hl
call $19e5
ld (K_CUR),hl
ld (iy+$07),$00
pop hl
ret
bit 3,(iy+$02)
call nz,$111d
and a
bit 5,(iy+$01)
ret z
ld a,(LAST_K)
res 5,(iy+$01)
push af
bit 5,(iy+$02)
call nz,$0d6e
pop af
cp $20
jr nc,l111b ; (82)
cp $10
jr nc,l10fa ; (45)
cp $06
jr nc,l10db ; (10)
ld b,a
and $01
ld c,a
ld a,b
rra
add a,$12
jr l1105 ; (42)
.l10db jr nz,l10e6 ; (9)
ld hl,FLAGS2
ld a,$08
xor (hl)
ld (hl),a
jr l10f4 ; (14)
.l10e6 cp $0e
ret c
sub $0d
ld hl,MODE
cp (hl)
ld (hl),a
jr nz,l10f4 ; (2)
ld (hl),$00
.l10f4 set 3,(iy+$02)
cp a
ret
.l10fa ld b,a
and $07
ld c,a
ld a,$10
bit 3,b
jr nz,l1105 ; (1)
inc a
.l1105 ld (iy-$2d),c
ld de,$110d
jr l1113 ; (6)
ld a,(K_DATA)
ld de,$10a8
.l1113 ld hl,(CHANS)
inc hl
inc hl
ld (hl),e
inc hl
ld (hl),d
.l111b scf
ret
.l111d call $0d4d
res 3,(iy+$02)
res 5,(iy+$02)
ld hl,(SPOSNL)
push hl
ld hl,(ERR_SP)
push hl
ld hl,$1167
push hl
ld (ERR_SP),sp
ld hl,(ECHO_E)
push hl
scf
call $1195
ex de,hl
call $187d
ex de,hl
call $18e1
ld hl,(SPOSNL)
ex (sp),hl
ex de,hl
call $0d4d
.l1150 ld a,(SPOSNL+1)
sub d
jr c,l117c ; (38)
jr nz,l115e ; (6)
ld a,e
sub (iy+$50)
jr nc,l117c ; (30)
.l115e ld a,$20
push de
call $09f4
pop de
jr l1150 ; (-23)
ld d,$00
ld e,(iy-$02)
ld hl,$1a90
call $03b5
ld (iy+$00),$ff
ld de,(SPOSNL)
jr l117e ; (2)
.l117c pop de
pop hl
.l117e pop hl
ld (ERR_SP),hl
pop bc
push de
call $0dd9
pop hl
ld (ECHO_E),hl
ld (iy+$26),$00
ret
.l1190 ld hl,(WORKSP)
dec hl
and a
.l1195 ld de,(E_LINE)
bit 5,(iy+$37)
ret z
ld de,(WORKSP)
ret c
ld hl,(STKBOT)
ret
.l11a7 ld a,(hl)
cp $0e
ld bc,$0006
call z,$19e8
ld a,(hl)
inc hl
cp $0d
jr nz,l11a7 ; (-15)
ret
di
ld a,$ff
ld de,(RAMTOP)
exx
ld bc,(P_RAMT)
ld de,(RASP)
ld hl,(UDG)
exx
.l11cb ld b,a
ld a,$07
out ($fe),a
ld a,$3f
ld i,a
nop
nop
nop
nop
nop
nop
ld h,d
ld l,e
.l11dc ld (hl),$02
dec hl
cp h
jr nz,l11dc ; (-6)
.l11e2 and a
sbc hl,de
add hl,de
inc hl
jr nc,l11ef ; (6)
dec (hl)
jr z,l11ef ; (3)
dec (hl)
jr z,l11e2 ; (-13)
.l11ef dec hl
exx
ld (P_RAMT),bc
ld (RASP),de
ld (UDG),hl
exx
inc b
jr z,l1219 ; (25)
ld (P_RAMT),hl
ld de,$3eaf
ld bc,$00a8
ex de,hl
lddr
ex de,hl
inc hl
ld (UDG),hl
dec hl
ld bc,$0040
ld (RASP),bc
.l1219 ld (RAMTOP),hl
ld hl,$3c00
ld (CHARS),hl
ld hl,(RAMTOP)
ld (hl),$3e
dec hl
ld sp,hl
dec hl
dec hl
ld (ERR_SP),hl
im 1
ld iy,ERR_NR
ei
ld hl,$5cb6
ld (CHANS),hl
ld de,$15af
ld bc,$0015
ex de,hl
ldir
ex de,hl
dec hl
ld (DATADD),hl
inc hl
ld (PROG),hl
ld (VARS),hl
ld (hl),$80
inc hl
ld (E_LINE),hl
ld (hl),$0d
inc hl
ld (hl),$80
inc hl
ld (WORKSP),hl
ld (STKBOT),hl
ld (STKEND),hl
ld a,$38
ld (ATTR_P),a
ld (ATTR_T),a
ld (BORDCR),a
ld hl,$0523
ld (REPDEL),hl
dec (iy-$3a)
dec (iy-$36)
ld hl,$15c6
ld de,STRMS
ld bc,$000e
ldir
set 1,(iy+$01)
call $0edf
ld (iy+$31),$02
call $0d6b
xor a
ld de,$1538
call $0c0a
set 5,(iy+$02)
jr l12a9 ; (7)
.l12a2 ld (iy+$31),$02
call $1795
.l12a9 call $16b0
.l12ac ld a,$00
call $1601
call $0f2c
call $1b17
bit 7,(iy+$00)
jr nz,l12cf ; (18)
bit 4,(iy+$30)
jr z,l1303 ; (64)
ld hl,(E_LINE)
call $11a7
ld (iy+$00),$ff
jr l12ac ; (-35)
.l12cf ld hl,(E_LINE)
ld (CH_ADD),hl
call $19fb
ld a,b
or c
jp nz,$155d
rst $18
cp $0d
jr z,l12a2 ; (-64)
bit 0,(iy+$30)
call nz,$0daf
call $0d6e
ld a,$19
sub (iy+$4f)
ld (SCR_CT),a
set 7,(iy+$01)
ld (iy+$00),$ff
ld (iy+$0a),$01
call $1b8a
.l1303 halt
res 5,(iy+$01)
bit 1,(iy+$30)
call nz,$0ecd
ld a,(ERR_NR)
inc a
.l1313 push af
ld hl,$0000
ld (iy+$37),h
ld (iy+$26),h
ld (DEFADD),hl
ld hl,$0001
ld (STRMS+$06),hl
call $16b0
res 5,(iy+$37)
call $0d6e
set 5,(iy+$02)
pop af
ld b,a
cp $0a
jr c,l133c ; (2)
add a,$07
.l133c call $15ef
ld a,$20
rst $10
ld a,b
ld de,$1391
call $0c0a
call $3a29
nop
call $0c0a
ld bc,(PPC)
call $1a1b
ld a,$3a
rst $10
ld c,(iy+$0d)
ld b,$00
call $1a1b
call $1097
ld a,(ERR_NR)
inc a
jr z,l1386 ; (27)
cp $09
jr z,l1373 ; (4)
cp $15
jr nz,l1376 ; (3)
.l1373 inc (iy+$0d)
.l1376 ld bc,$0003
ld de,OSPCC
ld hl,NSPPC
bit 7,(hl)
jr z,l1384 ; (1)
add hl,bc
.l1384 lddr
.l1386 ld (iy+$0a),$ff
res 3,(iy+$01)
jp $12ac
.l1391 defb $80
defm "O"&('K'+$80)
defm "NEXT without FO"&('R'+$80)
defm "Variable not foun"&('d'+$80)
defm "Subscript wron"&('g'+$80)
defm "Out of memor"&('y'+$80)
defm "Out of scree"&('n'+$80)
defm "Number too bi"&('g'+$80)
defm "RETURN without GOSU"&('B'+$80)
defm "End of fil"&('e'+$80)
defm "STOP statemen"&('t'+$80)
defm "Invalid argumen"&('t'+$80)
defm "Integer out of rang"&('e'+$80)
defm "Nonsense in BASI"&('C'+$80)
defm "BREAK - CONT repeat"&('s'+$80)
defm "Out of DAT"&('A'+$80)
defm "Invalid file nam"&('e'+$80)
defm "No room for lin"&('e'+$80)
defm "STOP in INPU"&('T'+$80)
defm "FOR without NEX"&('T'+$80)
defm "Invalid I/O devic"&('e'+$80)
defm "Invalid colou"&('r'+$80)
defm "BREAK into progra"&('m'+$80)
defm "RAMTOP no goo"&('d'+$80)
defm "Statement los"&('t'+$80)
defm "Invalid strea"&('m'+$80)
defm "FN without DE"&('F'+$80)
defm "Parameter erro"&('r'+$80)
defm "Tape loading erro"&('r'+$80)
defm ","&$a0
defm $7f&" 1982 Amstrad "&$a0
.l1555 ld a,$10
ld bc,$0000
jp $1313
.l155d ld (E_PPC),bc
ld hl,(CH_ADD)
ex de,hl
ld hl,$1555
push hl
.l1569 ld hl,(WORKSP)
scf
.l156d sbc hl,de
.l156f push hl
ld h,b
.l1571 ld l,c
call $196e
jr nz,l157d ; (6)
call $19b8
call $19e8
.l157d pop bc
ld a,c
dec a
or b
jr z,l15ab ; (40)
.l1583 push bc
inc bc
inc bc
.l1586 inc bc
inc bc
dec hl
ld de,(PROG)
push de
call $1655
pop hl
ld (PROG),hl
pop bc
push bc
.l1597 inc de
.l1598 ld hl,(WORKSP)
dec hl
dec hl
lddr
ld hl,(E_PPC)
ex de,hl
pop bc
ld (hl),b
dec hl
ld (hl),c
dec hl
ld (hl),e
dec hl
ld (hl),d
.l15ab pop af
jp $12a2
call p,$a809
djnz $15ff ; (75)
call p,$c409
dec d
ld d,e
add a,c
rrca
call nz,$5215
call p,$c409
dec d
ld d,b
add a,b
rst $8
ld (de),a
ld bc,$0600
nop
dec bc
nop
ld bc,$0100
nop
ld b,$00
djnz $15d4 ; (0)
.l15d4 bit 5,(iy+$02)
jr nz,l15de ; (4)
set 3,(iy+$02)
.l15de call $15e6
ret c
jr z,l15de ; (-6)
rst $8
rlca
.l15e6 exx
push hl
ld hl,(CURCHL)
inc hl
inc hl
jr l15f7 ; (8)
.l15ef ld e,$30
add a,e
.l15f2 exx
push hl
ld hl,(CURCHL)
.l15f7 ld e,(hl)
inc hl
ld d,(hl)
ex de,hl
call $162c
pop hl
.l15ff exx
ret
.l1601 add a,a
add a,$16
ld l,a
ld h,$5c
ld e,(hl)
inc hl
ld d,(hl)
ld a,d
or e
jr nz,l1610 ; (2)
.l160e rst $8
rla
.l1610 dec de
ld hl,(CHANS)
add hl,de
.l1615 ld (CURCHL),hl
res 4,(iy+$30)
inc hl
inc hl
inc hl
inc hl
ld c,(hl)
ld hl,$162d
call $16dc
ret nc
ld d,$00
ld e,(hl)
add hl,de
.l162c jp (hl)
ld c,e
ld b,$53
ld (de),a
ld d,b
dec de
nop
set 0,(iy+$02)
res 5,(iy+$01)
set 4,(iy+$30)
jr l1646 ; (4)
res 0,(iy+$02)
.l1646 res 1,(iy+$01)
jp $0d4d
set 1,(iy+$01)
ret
.l1652 ld bc,$0001
.l1655 push hl
call $1f05
pop hl
call $1664
ld hl,(STKEND)
ex de,hl
lddr
ret
.l1664 push af
push hl
ld hl,VARS
ld a,$0e
.l166b ld e,(hl)
inc hl
ld d,(hl)
ex (sp),hl
and a
sbc hl,de
add hl,de
ex (sp),hl
jr nc,l167f ; (9)
push de
ex de,hl
add hl,bc
ex de,hl
ld (hl),d
dec hl
ld (hl),e
inc hl
pop de
.l167f inc hl
dec a
jr nz,l166b ; (-24)
ex de,hl
pop de
pop af
and a
sbc hl,de
ld b,h
ld c,l
inc bc
add hl,de
ex de,hl
ret
nop
nop
.l1691 ex de,hl
ld de,$168f
.l1695 ld a,(hl)
and $c0
jr nz,l1691 ; (-9)
ld d,(hl)
inc hl
ld e,(hl)
ret
.l169e ld hl,(STKBOT)
dec hl
call $1655
inc hl
inc hl
pop bc
ld (WORKSP),bc
pop bc
ex de,hl
inc hl
ret
.l16b0 ld hl,(E_LINE)
ld (hl),$0d
ld (K_CUR),hl
inc hl
ld (hl),$80
inc hl
ld (WORKSP),hl
.l16bf ld hl,(WORKSP)
ld (STKBOT),hl
.l16c5 ld hl,(STKBOT)
ld (STKEND),hl
push hl
ld hl,MEMBOT
ld (MEM),hl
pop hl
ret
ld de,(E_LINE)
jp $19e5
.l16db inc hl
.l16dc ld a,(hl)
and a
ret z
cp c
inc hl
jr nz,l16db ; (-8)
scf
ret
call $171e
call $1701
ld bc,$0000
ld de,$a3e2
ex de,hl
add hl,de
jr c,l16fc ; (7)
ld bc,$15d4
add hl,bc
ld c,(hl)
inc hl
ld b,(hl)
.l16fc ex de,hl
ld (hl),c
inc hl
ld (hl),b
ret
.l1701 push hl
ld hl,(CHANS)
add hl,bc
inc hl
inc hl
inc hl
ld c,(hl)
ex de,hl
ld hl,$1716
call $16dc
ld c,(hl)
ld b,$00
add hl,bc
jp (hl)
ld c,e
dec b
ld d,e
inc bc
ld d,b
ld bc,$c9e1
.l171e call $1e94
cp $10
jr c,l1727 ; (2)
.l1725 rst $8
rla
.l1727 add a,$03
rlca
ld hl,STRMS
ld c,a
ld b,$00
add hl,bc
ld c,(hl)
inc hl
ld b,(hl)
dec hl
ret
rst $28
ld bc,$cd38
ld e,$17
ld a,b
or c
jr z,l1756 ; (22)
ex de,hl
ld hl,(CHANS)
add hl,bc
inc hl
inc hl
inc hl
ld a,(hl)
ex de,hl
cp $4b
jr z,l1756 ; (8)
cp $53
jr z,l1756 ; (4)
cp $50
jr nz,l1725 ; (-49)
.l1756 call $175d
ld (hl),e
inc hl
ld (hl),d
ret
.l175d push hl
call $2bf1
ld a,b
or c
defb $20
defb 2
.l1765 rst $8
ld c,$c5
ld a,(de)
and $df
ld c,a
ld hl,$177a
call $16dc
jr nc,l1765 ; (-15)
ld c,(hl)
ld b,$00
add hl,bc
pop bc
jp (hl)
ld c,e
ld b,$53
ex af,af'
ld d,b
ld a,(bc)
nop
ld e,$01
jr l178b ; (6)
ld e,$06
jr l178b ; (2)
ld e,$10
.l178b dec bc
ld a,b
or c
jr nz,l1765 ; (-43)
ld d,a
pop hl
ret
jr l1725 ; (-112)
.l1795 ld (LIST_SP),sp
ld (iy+$02),$10
call $0daf
set 0,(iy+$02)
ld b,(iy+$31)
call $0e44
res 0,(iy+$02)
set 0,(iy+$30)
ld hl,(E_PPC)
ld de,(S_TOP)
and a
sbc hl,de
add hl,de
jr c,l17e1 ; (34)
push de
call $196e
ld de,$02c0
ex de,hl
sbc hl,de
ex (sp),hl
call $196e
pop bc
.l17ce push bc
call $19b8
pop bc
add hl,bc
jr c,l17e4 ; (14)
ex de,hl
ld d,(hl)
inc hl
ld e,(hl)
dec hl
ld (S_TOP),de
jr l17ce ; (-19)
.l17e1 ld (S_TOP),hl
.l17e4 ld hl,(S_TOP)
call $196e
jr z,l17ed ; (1)
ex de,hl
.l17ed call $1833
res 4,(iy+$02)
ret
ld a,$03
jr l17fb ; (2)
ld a,$02
.l17fb ld (iy+$02),$00
call $2530
call nz,$1601
rst $18
call $2070
jr c,l181f ; (20)
rst $18
cp $3b
jr z,l1814 ; (4)
cp $2c
jr nz,l181a ; (6)
.l1814 rst $20
call $1c82
jr l1822 ; (8)
.l181a call $1ce6
jr l1822 ; (3)
.l181f call $1cde
.l1822 call $1bee
call $1e99
ld a,b
and $3f
ld h,a
ld l,c
ld (E_PPC),hl
call $196e
.l1833 ld e,$01
.l1835 call $1855
rst $10
bit 4,(iy+$02)
jr z,l1835 ; (-10)
ld a,(DF_SZ)
sub (iy+$4f)
jr nz,l1835 ; (-18)
xor e
ret z
push hl
push de
ld hl,S_TOP
call $190f
pop de
pop hl
jr l1835 ; (-32)
.l1855 ld bc,(E_PPC)
call $1980
ld d,$3e
jr z,l1865 ; (5)
ld de,$0000
rl e
.l1865 ld (iy+$2d),e
ld a,(hl)
cp $40
pop bc
ret nc
push bc
call $1a28
inc hl
inc hl
inc hl
res 0,(iy+$01)
ld a,d
and a
jr z,l1881 ; (5)
rst $10
.l187d set 0,(iy+$01)
.l1881 push de
ex de,hl
res 2,(iy+$30)
ld hl,FLAGS
res 2,(hl)
bit 5,(iy+$37)
jr z,l1894 ; (2)
set 2,(hl)
.l1894 ld hl,(X_PTR)
and a
sbc hl,de
jr nz,l18a1 ; (5)
ld a,$3f
call $18c1
.l18a1 call $18e1
ex de,hl
ld a,(hl)
call $18b6
inc hl
cp $0d
jr z,l18b4 ; (6)
ex de,hl
call $1937
jr l1894 ; (-32)
.l18b4 pop de
ret
.l18b6 cp $0e
ret nz
inc hl
inc hl
inc hl
inc hl
inc hl
inc hl
ld a,(hl)
ret
.l18c1 exx
ld hl,(ATTR_T)
push hl
res 7,h
set 7,l
ld (ATTR_T),hl
ld hl,P_FLAG
ld d,(hl)
push de
ld (hl),$00
call $09f4
pop hl
ld (iy+$57),h
pop hl
ld (ATTR_T),hl
exx
ret
.l18e1 ld hl,(K_CUR)
and a
sbc hl,de
ret nz
ld a,(MODE)
rlc a
jr z,l18f3 ; (4)
add a,$43
jr l1909 ; (22)
.l18f3 ld hl,FLAGS
res 3,(hl)
ld a,$4b
bit 2,(hl)
jr z,l1909 ; (11)
set 3,(hl)
inc a
bit 3,(iy+$30)
jr z,l1909 ; (2)
ld a,$43
.l1909 push de
call $18c1
pop de
ret
.l190f ld e,(hl)
inc hl
ld d,(hl)
push hl
ex de,hl
inc hl
call $196e
call $1695
pop hl
.l191c bit 5,(iy+$37)
ret nz
ld (hl),d
dec hl
ld (hl),e
ret
.l1925 ld a,e
and a
ret m
jr l1937 ; (13)
.l192a xor a
.l192b add hl,bc
inc a
jr c,l192b ; (-4)
sbc hl,bc
dec a
jr z,l1925 ; (-15)
jp $15ef
.l1937 call $2d1b
jr nc,l196c ; (48)
cp $21
jr c,l196c ; (44)
res 2,(iy+$01)
cp $cb
jr z,l196c ; (36)
cp $3a
jr nz,l195a ; (14)
bit 5,(iy+$37)
jr nz,l1968 ; (22)
bit 2,(iy+$30)
jr z,l196c ; (20)
jr l1968 ; (14)
.l195a cp $22
jr nz,l1968 ; (10)
push af
ld a,(FLAGS2)
xor $04
ld (FLAGS2),a
pop af
.l1968 set 2,(iy+$01)
.l196c rst $10
ret
.l196e push hl
ld hl,(PROG)
ld d,h
ld e,l
.l1974 pop bc
call $1980
ret nc
push bc
call $19b8
ex de,hl
jr l1974 ; (-12)
.l1980 ld a,(hl)
cp b
ret nz
inc hl
ld a,(hl)
dec hl
cp c
ret
inc hl
inc hl
inc hl
.l198b ld (CH_ADD),hl
ld c,$00
.l1990 dec d
ret z
rst $20
cp e
jr nz,l199a ; (4)
and a
ret
.l1998 inc hl
ld a,(hl)
.l199a call $18b6
ld (CH_ADD),hl
cp $22
jr nz,l19a5 ; (1)
dec c
.l19a5 cp $3a
jr z,l19ad ; (4)
cp $cb
jr nz,l19b1 ; (4)
.l19ad bit 0,c
jr z,l1990 ; (-33)
.l19b1 cp $0d
jr nz,l1998 ; (-29)
dec d
scf
ret
.l19b8 push hl
ld a,(hl)
cp $40
jr c,l19d5 ; (23)
bit 5,a
jr z,l19d6 ; (20)
add a,a
jp m,$19c7
ccf
.l19c7 ld bc,$0005
jr nc,l19ce ; (2)
ld c,$12
.l19ce rla
inc hl
ld a,(hl)
jr nc,l19ce ; (-5)
jr l19db ; (6)
.l19d5 inc hl
.l19d6 inc hl
ld c,(hl)
inc hl
ld b,(hl)
inc hl
.l19db add hl,bc
pop de
.l19dd and a
sbc hl,de
ld b,h
ld c,l
add hl,de
ex de,hl
ret
.l19e5 call $19dd
.l19e8 push bc
ld a,b
cpl
ld b,a
ld a,c
cpl
ld c,a
inc bc
call $1664
ex de,hl
pop hl
add hl,de
push de
ldir
pop hl
ret
.l19fb ld hl,(E_LINE)
dec hl
ld (CH_ADD),hl
rst $20
ld hl,MEMBOT
ld (STKEND),hl
call $2d3b
call $2da2
jr c,l1a15 ; (4)
ld hl,$d8f0
add hl,bc
.l1a15 jp c,$1c8a
jp $16c5
.l1a1b push de
push hl
xor a
bit 7,b
jr nz,l1a42 ; (32)
ld h,b
ld l,c
ld e,$ff
jr l1a30 ; (8)
.l1a28 push de
ld d,(hl)
inc hl
ld e,(hl)
push hl
ex de,hl
ld e,$20
.l1a30 ld bc,$fc18
call $192a
ld bc,$ff9c
call $192a
ld c,$f6
call $192a
ld a,l
.l1a42 call $15ef
pop hl
pop de
ret
or c
res 7,h
cp a
call nz,$b4af
sub e
sub c
sub d
sub l
sbc a,b
sbc a,b
sbc a,b
sbc a,b
sbc a,b
sbc a,b
sbc a,b
ld a,a
add a,c
ld l,$6c
ld l,(hl)
ld (hl),b
ld c,b
sub h
ld d,(hl)
ccf
ld b,c
dec hl
rla
rra
scf
ld (hl),a
ld b,h
rrca
ld e,c
dec hl
ld b,e
dec l
ld d,c
ld a,($426d)
dec c
ld c,c
ld e,h
ld b,h
dec d
ld e,l
ld bc,$023d
ld b,$00
ld h,a
ld e,$06
rlc l
ret p
inc e
ld b,$00
defb $ed
defb $1e ; Undocumented 8 T-State NOP
nop
xor $1c
nop
inc hl
rra
inc b
dec a
ld b,$cc
ld b,$05
inc bc
dec e
inc b
nop
xor e
dec e
dec b
call $051f
adc a,c
jr nz,l1aa8 ; (5)
ld (bc),a
inc l
dec b
or d
dec de
.l1aa8 nop
or a
ld de,$a103
ld e,$05
ld sp,hl
rla
ex af,af'
nop
add a,b
ld e,$03
ld c,a
ld e,$00
ld e,a
ld e,$03
xor h
ld e,$00
ld l,e
dec c
add hl,bc
nop
call c,$0622
nop
ld a,($051f)
defb $ed
defb $1d ; Undocumented 8 T-State NOP
dec b
daa
ld e,$03
ld b,d
ld e,$09
dec b
add a,d
inc hl
nop
xor h
ld c,$05
ret
rra
dec b
push af
rla
dec bc
dec bc
dec bc
dec bc
ex af,af'
nop
ret m
inc bc
add hl,bc
dec b
jr nz,l1b0e ; (35)
rlca
rlca
rlca
rlca
rlca
rlca
ex af,af'
nop
ld a,d
ld e,$06
nop
sub h
ld ($6005),hl
rra
ld b,$2c
ld a,(bc)
nop
ld (hl),$17
ld b,$00
push hl
ld d,$0a
nop
sub e
rla
ld a,(bc)
inc l
ld a,(bc)
nop
.l1b0e sub e
rla
ld a,(bc)
nop
sub e
rla
nop
sub e
rla
.l1b17 res 7,(iy+$01)
call $19fb
xor a
ld (SUBPPC),a
dec a
ld (ERR_NR),a
jr l1b29 ; (1)
.l1b28 rst $20
.l1b29 call $16bf
inc (iy+$0d)
jp m,$1c8a
rst $18
ld b,$00
cp $0d
jr z,l1bb3 ; (122)
cp $3a
jr z,l1b28 ; (-21)
ld hl,$1b76
push hl
ld c,a
rst $20
ld a,c
sub $ce
jp c,$1c8a
ld c,a
ld hl,$1a48
add hl,bc
ld c,(hl)
add hl,bc
jr l1b55 ; (3)
ld hl,(T_ADDR)
.l1b55 ld a,(hl)
inc hl
ld (T_ADDR),hl
ld bc,$1b52
push bc
ld c,a
cp $20
jr nc,l1b6f ; (12)
ld hl,$1c01
ld b,$00
add hl,bc
ld c,(hl)
add hl,bc
push hl
rst $18
dec b
ret
.l1b6f rst $18
cp c
jp nz,$1c8a
rst $20
ret
call $1f54
jr c,l1b7d ; (2)
rst $8
inc d
.l1b7d call $3a3b
nop
jr nz,l1bf4 ; (113)
ld hl,(NEWPPC)
bit 7,h
jr z,l1b9e ; (20)
.l1b8a ld hl,$fffe
ld (PPC),hl
ld hl,(WORKSP)
dec hl
ld de,(E_LINE)
dec de
ld a,(NSPPC)
jr l1bd1 ; (51)
.l1b9e call $196e
ld a,(NSPPC)
jr z,l1bbf ; (25)
and a
jr nz,l1bec ; (67)
ld b,a
ld a,(hl)
and $c0
ld a,b
jr z,l1bbf ; (15)
rst $8
rst $38
pop bc
.l1bb3 call $2530
ret z
ld hl,(NXTLIN)
ld a,$c0
and (hl)
ret nz
xor a
.l1bbf cp $01
adc a,$00
ld d,(hl)
inc hl
ld e,(hl)
ld (PPC),de
inc hl
ld e,(hl)
inc hl
ld d,(hl)
ex de,hl
add hl,de
inc hl
.l1bd1 ld (NXTLIN),hl
ex de,hl
ld (CH_ADD),hl
ld d,a
ld e,$00
ld (iy+$0a),$ff
dec d
ld (iy+$0d),d
jp z,$1b28
inc d
call $198b
.l1bea jr z,l1bf4 ; (8)
.l1bec rst $8
ld d,$cd
jr nc,l1c16 ; (37)
ret nz
pop bc
pop bc
.l1bf4 call $3a4b
jr z,l1bb3 ; (-70)
cp $3a
jp z,$1b28
jp $1c8a
rrca
dec e
ld c,e
add hl,bc
ld h,a
dec bc
ld a,e
adc a,(hl)
ld (hl),c
or h
add a,c
rst $8
call $1cde
cp a
pop bc
call z,$1bee
ex de,hl
.l1c16 ld hl,(T_ADDR)
ld c,(hl)
inc hl
ld b,(hl)
ex de,hl
push bc
ret
.l1c1f call $28b2
.l1c22 ld (iy+$37),$00
defb $30
defb 8
set 1,(iy+$37)
jr nz,l1c46 ; (24)
.l1c2e rst $8
ld bc,$96cc
add hl,hl
bit 6,(iy+$01)
jr nz,l1c46 ; (13)
xor a
call $2530
call nz,$2bf1
ld hl,FLAGX
or (hl)
ld (hl),a
ex de,hl
.l1c46 ld (STRLEN),bc
ld (DEST),hl
ret
pop bc
call $1c56
call $1bee
ret
.l1c56 ld a,(FLAGS)
.l1c59 push af
call $24fb
pop af
ld d,(iy+$01)
xor d
and $40
jr nz,l1c8a ; (36)
bit 7,d
jp nz,$2aff
ret
call $28b2
push af
ld a,c
or $9f
inc a
jr nz,l1c8a ; (20)
pop af
jr l1c22 ; (-87)
.l1c79 rst $20
.l1c7a call $1c82
cp $2c
jr nz,l1c8a ; (9)
rst $20
.l1c82 call $24fb
bit 6,(iy+$01)
ret nz
.l1c8a rst $8
dec bc
.l1c8c call $24fb
bit 6,(iy+$01)
ret z
jr l1c8a ; (-12)
bit 7,(iy+$01)
res 0,(iy+$02)
call nz,$0d4d
pop af
ld a,(T_ADDR)
sub $13
call $21fc
call $1bee
ld hl,(ATTR_T)
ld (ATTR_P),hl
ld hl,P_FLAG
ld a,(hl)
.l1cb7 rlca
xor (hl)
and $aa
xor (hl)
ld (hl),a
ret
call $2530
jr z,l1cd6 ; (19)
res 0,(iy+$02)
call $0d4d
ld hl,MASK_T
ld a,(hl)
or $f8
ld (hl),a
res 6,(iy+$57)
rst $18
.l1cd6 call $21e2
jr l1c7a ; (-97)
jp $0605
.l1cde cp $0d
jr z,l1ce6 ; (4)
cp $3a
jr nz,l1c82 ; (-100)
.l1ce6 call $2530
ret z
rst $28
.l1ceb and b
jr c,l1cb7 ; (-55)
rst $8
ex af,af'
pop bc
call $2530
jr z,l1d00 ; (10)
rst $28
ld (bc),a
defb $38
defb -21
call $34e9
jp c,$1bb3
.l1d00 jp $1b29
cp $cd
jr nz,l1d10 ; (9)
rst $20
call $1c82
call $1bee
defb $18
defb 6
.l1d10 call $1bee
rst $28
and c
defb $38
defb -17
ret nz
ld (bc),a
ld bc,$01e0
jr c,l1ceb ; (-51)
rst $38
ld hl,($6822)
ld e,h
dec hl
ld a,(hl)
set 7,(hl)
ld bc,$0006
add hl,bc
rlca
jr c,l1d34 ; (6)
ld c,$0d
call $1655
inc hl
.l1d34 push hl
rst $28
ld (bc),a
ld (bc),a
defb $38
defb -31
ex de,hl
ld c,$0a
ldir
ld hl,(PPC)
ex de,hl
ld (hl),e
inc hl
ld (hl),d
ld d,(iy+$0d)
inc d
inc hl
ld (hl),d
call $1dda
ret nc
ld b,(iy+$38)
ld hl,(PPC)
ld (NEWPPC),hl
ld a,(SUBPPC)
neg
ld d,a
ld hl,(CH_ADD)
ld e,$f3
.l1d64 push bc
ld bc,(NXTLIN)
call $1d86
ld (NXTLIN),bc
pop bc
jr c,l1d84 ; (17)
rst $20
or $20
cp b
jr z,l1d7c ; (3)
rst $20
jr l1d64 ; (-24)
.l1d7c rst $20
ld a,$01
sub d
ld (NSPPC),a
ret
.l1d84 rst $8
ld de,$fe7e
ld a,($1828)
.l1d8b inc hl
ld a,(hl)
and $c0
.l1d8f scf
ret nz
ld b,(hl)
.l1d92 inc hl
ld c,(hl)
ld (NEWPPC),bc
inc hl
ld c,(hl)
inc hl
ld b,(hl)
push hl
add hl,bc
ld b,h
ld c,l
pop hl
ld d,$00
push bc
call $198b
pop bc
ret nc
jr l1d8b ; (-32)
bit 1,(iy+$37)
jp nz,$1c2e
ld hl,(DEST)
bit 7,(hl)
jr z,l1dd8 ; (31)
inc hl
ld (MEM),hl
rst $28
ret po
jp po,$c00f
ld (bc),a
jr c,l1d92 ; (-51)
jp c,$d81d
ld hl,(MEM)
ld de,$000f
add hl,de
ld e,(hl)
inc hl
ld d,(hl)
inc hl
ld h,(hl)
ex de,hl
jp $1e73
.l1dd8 rst $8
nop
.l1dda rst $28
pop hl
ret po
jp po,$0036
ld (bc),a
ld bc,$3703
nop
inc b
jr c,l1d8f ; (-89)
ret
defb $38
defb 55
ret
.l1dec rst $20
call $1c1f
call $2530
jr z,l1e1e ; (41)
rst $18
ld (X_PTR),hl
ld hl,(DATADD)
ld a,(hl)
cp $2c
jr z,l1e0a ; (9)
ld e,$e4
call $1d86
jr nc,l1e0a ; (2)
rst $8
dec c
.l1e0a call $0077
call $1c56
rst $18
ld (DATADD),hl
ld hl,(X_PTR)
ld (iy+$26),$00
call $0078
.l1e1e rst $18
cp $2c
jr z,l1dec ; (-55)
call $1bee
ret
call $2530
jr nz,l1e37 ; (11)
.l1e2c call $24fb
cp $2c
call nz,$1bee
rst $20
jr l1e2c ; (-11)
.l1e37 ld a,$e4
.l1e39 ld b,a
cpdr
ld de,$0200
jp $198b
call $1e99
.l1e45 ld h,b
ld l,c
call $196e
dec hl
ld (DATADD),hl
ret
call $1e99
ld a,b
or c
jr nz,l1e5a ; (4)
ld bc,(FRAMES)
.l1e5a ld (SEED),bc
ret
ld hl,(OLDPPC)
ld d,(iy+$36)
jr l1e73 ; (12)
.l1e67 call $1e99
ld h,b
ld l,c
ld d,$00
ld a,h
cp $f0
jr nc,l1e9f ; (44)
.l1e73 ld (NEWPPC),hl
ld (iy+$0a),d
ret
call $1e85
out (c),a
ret
call $1e85
ld (bc),a
ret
.l1e85 call $2dd5
jr c,l1e9f ; (21)
jr z,l1e8e ; (2)
neg
.l1e8e push af
call $1e99
pop af
ret
.l1e94 call $2dd5
jr l1e9c ; (3)
.l1e99 call $2da2
.l1e9c jr c,l1e9f ; (1)
ret z
.l1e9f rst $8
ld a,(bc)
call $1e67
ld bc,$0000
call $1e45
jr l1eaf ; (3)
call $1e99
.l1eaf ld a,b
or c
jr nz,l1eb7 ; (4)
ld bc,(RAMTOP)
.l1eb7 push bc
ld de,(VARS)
ld hl,(E_LINE)
dec hl
call $19e5
call $0d6b
ld hl,(STKEND)
ld de,$0032
add hl,de
pop de
sbc hl,de
jr nc,l1eda ; (8)
ld hl,(P_RAMT)
and a
sbc hl,de
jr nc,l1edc ; (2)
.l1eda rst $8
dec d
.l1edc ex de,hl
ld (RAMTOP),hl
pop de
pop bc
ld (hl),$3e
dec hl
ld sp,hl
push bc
ld (ERR_SP),sp
ex de,hl
jp (hl)
pop de
ld h,(iy+$0d)
inc h
ex (sp),hl
inc sp
ld bc,(PPC)
push bc
push hl
ld (ERR_SP),sp
push de
call $1e67
ld bc,$0014
.l1f05 ld hl,(STKEND)
add hl,bc
jr c,l1f15 ; (10)
ex de,hl
ld hl,$0050
add hl,de
jr c,l1f15 ; (3)
sbc hl,sp
ret c
.l1f15 ld l,$03
jp $0055
ld bc,$0000
call $1f05
ld b,h
ld c,l
ret
pop bc
pop hl
pop de
ld a,d
cp $3e
jr z,l1f36 ; (11)
dec sp
ex (sp),hl
ex de,hl
ld (ERR_SP),sp
push bc
jp $1e73
.l1f36 push de
push hl
rst $8
ld b,$cd
sbc a,c
ld e,$76
dec bc
ld a,b
or c
jr z,l1f4f ; (12)
ld a,b
and c
inc a
jr nz,l1f49 ; (1)
inc bc
.l1f49 bit 5,(iy+$01)
defb $28
defb -18
.l1f4f res 5,(iy+$01)
ret
.l1f54 ld a,$7f
in a,($fe)
rra
ret c
ld a,$fe
in a,($fe)
rra
ret
call $2530
jr z,l1f6a ; (5)
ld a,$ce
jp $1e39
.l1f6a set 6,(iy+$01)
call $2c8d
jr nc,l1f89 ; (22)
rst $20
cp $24
jr nz,l1f7d ; (5)
res 6,(iy+$01)
rst $20
.l1f7d cp $28
jr nz,l1fbd ; (60)
rst $20
cp $29
jr z,l1fa6 ; (32)
.l1f86 call $2c8d
.l1f89 jp nc,$1c8a
ex de,hl
rst $20
cp $24
jr nz,l1f94 ; (2)
ex de,hl
rst $20
.l1f94 ex de,hl
ld bc,$0006
call $1655
inc hl
inc hl
ld (hl),$0e
cp $2c
jr nz,l1fa6 ; (3)
rst $20
jr l1f86 ; (-32)
.l1fa6 cp $29
jr nz,l1fbd ; (19)
rst $20
cp $3d
jr nz,l1fbd ; (14)
rst $20
ld a,(FLAGS)
push af
call $24fb
pop af
xor (iy+$01)
and $40
.l1fbd jp nz,$1c8a
call $1bee
.l1fc3 call $2530
pop hl
ret z
jp (hl)
ld a,$03
jr l1fcf ; (2)
ld a,$02
.l1fcf call $2530
call nz,$1601
call $0d4d
call $1fdf
call $1bee
ret
.l1fdf rst $18
call $2045
jr z,l1ff2 ; (13)
.l1fe5 call $204e
jr z,l1fe5 ; (-5)
call $1ffc
call $204e
jr z,l1fe5 ; (-13)
.l1ff2 cp $29
ret z
.l1ff5 call $1fc3
ld a,$0d
rst $10
ret
.l1ffc rst $18
cp $ac
jr nz,l200e ; (13)
call $1c79
call $1fc3
call $2307
ld a,$16
jr l201e ; (16)
.l200e cp $ad
jr nz,l2024 ; (18)
rst $20
call $1c82
call $1fc3
call $1e99
ld a,$17
.l201e rst $10
ld a,c
rst $10
ld a,b
rst $10
ret
.l2024 call $21f2
ret nc
call $2070
ret nc
call $24fb
call $1fc3
bit 6,(iy+$01)
call z,$2bf1
jp nz,$2de3
.l203c ld a,b
or c
dec bc
ret z
ld a,(de)
inc de
rst $10
jr l203c ; (-9)
.l2045 cp $29
ret z
.l2048 cp $0d
ret z
cp $3a
ret
.l204e rst $18
cp $3b
jr z,l2067 ; (20)
cp $2c
jr nz,l2061 ; (10)
call $2530
jr z,l2067 ; (11)
ld a,$06
rst $10
jr l2067 ; (6)
.l2061 cp $27
ret nz
call $1ff5
.l2067 rst $20
call $2045
jr nz,l206e ; (1)
pop bc
.l206e cp a
ret
.l2070 cp $23
scf
ret nz
rst $20
call $1c82
and a
call $1fc3
call $1e94
cp $10
jp nc,$160e
call $1601
and a
ret
call $2530
jr z,l2096 ; (8)
ld a,$01
call $1601
call $0d6e
.l2096 ld (iy+$02),$01
call $20c1
call $1bee
ld bc,(S_POSN)
ld a,(DF_SZ)
cp b
jr c,l20ad ; (3)
ld c,$21
ld b,a
.l20ad ld (S_POSN),bc
ld a,$19
sub b
ld (SCR_CT),a
res 0,(iy+$02)
call $0dd9
jp $0d6e
.l20c1 call $204e
jr z,l20c1 ; (-5)
cp $28
jr nz,l20d8 ; (14)
rst $20
call $1fdf
rst $18
cp $29
jp nz,$1c8a
rst $20
jp $21b2
.l20d8 cp $ca
jr nz,l20ed ; (17)
rst $20
call $1c1f
set 7,(iy+$37)
bit 6,(iy+$01)
jp nz,$1c8a
jr l20fa ; (13)
.l20ed call $2c8d
jp nc,$21af
call $1c1f
res 7,(iy+$37)
.l20fa call $2530
jp z,$21b2
call $16bf
ld hl,FLAGX
res 6,(hl)
set 5,(hl)
ld bc,$0001
bit 7,(hl)
jr nz,l211c ; (11)
ld a,(FLAGS)
and $40
jr nz,l211a ; (2)
ld c,$03
.l211a or (hl)
ld (hl),a
.l211c rst $30
ld (hl),$0d
ld a,c
rrca
rrca
jr nc,l2129 ; (5)
ld a,$22
ld (de),a
dec hl
ld (hl),a
.l2129 ld (K_CUR),hl
bit 7,(iy+$37)
jr nz,l215e ; (44)
ld hl,(CH_ADD)
push hl
ld hl,(ERR_SP)
push hl
ld hl,$213a
push hl
bit 4,(iy+$30)
jr z,l2148 ; (4)
ld (ERR_SP),sp
.l2148 ld hl,(WORKSP)
call $11a7
ld (iy+$00),$ff
call $0f2c
res 7,(iy+$01)
call $21b9
jr l2161 ; (3)
.l215e call $0f2c
.l2161 ld (iy+$22),$00
call $21d6
jr nz,l2174 ; (10)
call $111d
ld bc,(ECHO_E)
call $0dd9
.l2174 ld hl,FLAGX
res 5,(hl)
bit 7,(hl)
res 7,(hl)
jr nz,l219b ; (28)
pop hl
pop hl
ld (ERR_SP),hl
pop hl
ld (X_PTR),hl
set 7,(iy+$01)
call $21b9
ld hl,(X_PTR)
ld (iy+$26),$00
ld (CH_ADD),hl
jr l21b2 ; (23)
.l219b ld hl,(STKBOT)
ld de,(WORKSP)
scf
sbc hl,de
ld b,h
ld c,l
call $2ab2
call $2aff
jr l21b2 ; (3)
.l21af call $1ffc
.l21b2 call $204e
jp z,$20c1
ret
.l21b9 ld hl,(WORKSP)
ld (CH_ADD),hl
rst $18
cp $e2
jr z,l21d0 ; (12)
ld a,(FLAGX)
call $1c59
rst $18
cp $0d
ret z
rst $8
dec bc
.l21d0 call $2530
ret z
rst $8
djnz $2201 ; (42)
ld d,c
ld e,h
inc hl
inc hl
inc hl
inc hl
ld a,(hl)
cp $4b
ret
.l21e1 rst $20
.l21e2 call $21f2
ret c
rst $18
cp $2c
jr z,l21e1 ; (-10)
cp $3b
jr z,l21e1 ; (-14)
jp $1c8a
.l21f2 cp $d9
ret c
cp $df
ccf
ret c
push af
rst $20
pop af
.l21fc sub $c9
push af
call $1c82
pop af
and a
call $1fc3
push af
call $1e94
ld d,a
pop af
rst $10
ld a,d
rst $10
ret
.l2211 sub $11
adc a,$00
jr z,l2234 ; (29)
sub $02
adc a,$00
jr z,l2273 ; (86)
cp $01
ld a,d
ld b,$01
jr nz,l2228 ; (4)
rlca
rlca
ld b,$04
.l2228 ld c,a
ld a,d
cp $02
jr nc,l2244 ; (22)
ld a,c
ld hl,P_FLAG
jr l226c ; (56)
.l2234 ld a,d
ld b,$07
jr c,l223e ; (5)
rlca
rlca
rlca
ld b,$38
.l223e ld c,a
ld a,d
cp $0a
jr c,l2246 ; (2)
.l2244 rst $8
inc de
.l2246 ld hl,ATTR_T
cp $08
jr c,l2258 ; (11)
ld a,(hl)
jr z,l2257 ; (7)
or b
cpl
and $24
jr z,l2257 ; (1)
ld a,b
.l2257 ld c,a
.l2258 ld a,c
call $226c
ld a,$07
cp d
sbc a,a
call $226c
rlca
rlca
and $50
ld b,a
ld a,$08
cp d
sbc a,a
.l226c xor (hl)
and b
xor (hl)
ld (hl),a
inc hl
ld a,b
ret
.l2273 sbc a,a
ld a,d
rrca
ld b,$80
jr nz,l227d ; (3)
rrca
ld b,$40
.l227d ld c,a
ld a,d
cp $08
jr z,l2287 ; (4)
cp $02
jr nc,l2244 ; (-67)
.l2287 ld a,c
ld hl,ATTR_T
call $226c
ld a,c
rrca
rrca
rrca
jr l226c ; (-40)
call $1e94
cp $08
jr nc,l2244 ; (-87)
out ($fe),a
rlca
rlca
rlca
bit 5,a
jr nz,l22a6 ; (2)
xor $07
.l22a6 ld (BORDCR),a
ret
.l22aa ld a,$af
sub b
jp c,$24f9
ld b,a
and a
rra
scf
rra
and a
rra
xor b
and $f8
xor b
ld h,a
ld a,c
rlca
rlca
rlca
xor b
and $c7
xor b
rlca
rlca
ld l,a
ld a,c
and $07
ret
.l22cb call $2307
call $22aa
ld b,a
inc b
ld a,(hl)
.l22d4 rlca
djnz $22d4 ; (-3)
and $01
jp $2d28
.l22dc call $2307
call $22e5
jp $0d4d
.l22e5 ld (COORDS),bc
call $22aa
ld b,a
inc b
ld a,$fe
.l22f0 rrca
djnz $22f0 ; (-3)
ld b,a
ld a,(hl)
ld c,(iy+$57)
bit 0,c
jr nz,l22fd ; (1)
and b
.l22fd bit 2,c
jr nz,l2303 ; (2)
xor b
cpl
.l2303 ld (hl),a
jp $0bdb
.l2307 call $2314
ld b,a
push bc
call $2314
ld e,c
pop bc
ld d,c
.l2312 ld c,a
ret
.l2314 call $2dd5
jp c,$24f9
ld c,$01
ret z
ld c,$ff
ret
rst $18
cp $2c
jp nz,$1c8a
rst $20
call $1c82
call $1bee
rst $28
ld hl,($383d)
ld a,(hl)
cp $81
jr nc,l233b ; (5)
rst $28
ld (bc),a
jr c,l2352 ; (24)
and c
.l233b rst $28
and e
jr c,l2375 ; (54)
add a,e
rst $28
push bc
ld (bc),a
jr c,l2312 ; (-51)
ld a,l
inc h
push bc
rst $28
ld sp,$04e1
jr c,l23cc ; (126)
cp $80
jr nc,l235a ; (8)
.l2352 rst $28
ld (bc),a
ld (bc),a
defb $38
defb -63
jp $22dc
.l235a rst $28
jp nz,$c001
ld (bc),a
inc bc
ld bc,$0fe0
ret nz
.l2364 ld bc,$e031
ld bc,$e031
and b
pop bc
.l236c ld (bc),a
jr c,l236c ; (-3)
inc (hl)
ld h,d
call $1e94
ld l,a
.l2375 push hl
call $1e94
pop hl
ld h,a
ld (COORDS),hl
pop bc
jp $2420
.l2382 rst $18
cp $2c
jr z,l238d ; (6)
call $1bee
jp $2477
.l238d rst $20
call $1c82
call $1bee
rst $28
push bc
and d
inc b
rra
ld sp,$3030
nop
ld b,$02
jr c,l2364 ; (-61)
ld (hl),a
.l23a2 inc h
ret nz
ld (bc),a
pop bc
ld (bc),a
ld sp,$e12a
ld bc,$2ae1
rrca
ret po
dec b
ld hl,($01e0)
dec a
jr c,l2434 ; (126)
cp $81
jr nc,l23c1 ; (7)
rst $28
ld (bc),a
ld (bc),a
jr c,l2382 ; (-61)
ld (hl),a
inc h
.l23c1 call $247d
push bc
rst $28
ld (bc),a
pop hl
ld bc,$c105
ld (bc),a
.l23cc ld bc,$e131
inc b
jp nz,$0102
ld sp,$04e1
jp po,$e0e5
inc bc
and d
inc b
ld sp,$c51f
ld (bc),a
jr nz,l23a2 ; (-64)
ld (bc),a
jp nz,$c102
push hl
inc b
ret po
jp po,$0f04
pop hl
ld bc,$02c1
ret po
inc b
jp po,$04e5
inc bc
jp nz,$e12a
ld hl,($020f)
defb $38
defb 26
cp $81
pop bc
jp c,$2477
push bc
rst $28
ld bc,$3a38
ld a,l
ld e,h
call $2d28
rst $28
ret nz
rrca
ld bc,$3a38
ld a,(hl)
ld e,h
call $2d28
rst $28
push bc
rrca
ret po
push hl
defb $38
defb -63
.l2420 dec b
jr z,l245f ; (60)
jr l2439 ; (20)
.l2425 rst $28
pop hl
.l2427 ld sp,$04e3
jp po,$04e4
inc bc
pop bc
ld (bc),a
call po,$e204
ex (sp),hl
.l2434 inc b
rrca
jp nz,$3802
.l2439 push bc
rst $28
ret nz
ld (bc),a
pop hl
rrca
ld sp,$3a38
ld a,l
ld e,h
call $2d28
rst $28
inc bc
ret po
jp po,$c00f
ld bc,$38e0
ld a,(COORDS+1)
call $2d28
rst $28
inc bc
.l2458 jr c,l2427 ; (-51)
or a
inc h
pop bc
djnz $2425 ; (-58)
.l245f rst $28
ld (bc),a
ld (bc),a
ld bc,$3a38
ld a,l
ld e,h
call $2d28
rst $28
inc bc
ld bc,$3a38
ld a,(hl)
ld e,h
call $2d28
rst $28
inc bc
defb $38
defb -51
or a
inc h
jp $0d4d
.l247d rst $28
ld sp,$3428
ld ($0100),a
dec b
push hl
ld bc,$2a05
jr c,l2458 ; (-51)
push de
dec l
jr c,l2495 ; (6)
and $fc
add a,$04
jr nc,l2497 ; (2)
.l2495 ld a,$fc
.l2497 push af
call $2d28
rst $28
push hl
ld bc,$3105
rra
call nz,$3102
and d
inc b
rra
pop bc
ld bc,$02c0
ld sp,$3104
rrca
and c
inc bc
dec de
jp $3802
pop bc
ret
call $2307
ld a,c
cp b
jr nc,l24c4 ; (6)
ld l,c
push de
xor a
ld e,a
jr l24cb ; (7)
.l24c4 or c
ret z
ld l,b
ld b,c
push de
ld d,$00
.l24cb ld h,b
ld a,b
rra
.l24ce add a,l
jr c,l24d4 ; (3)
cp h
jr c,l24db ; (7)
.l24d4 sub h
ld c,a
exx
pop bc
push bc
jr l24df ; (4)
.l24db ld c,a
push de
exx
pop bc
.l24df ld hl,(COORDS)
ld a,b
add a,h
ld b,a
ld a,c
inc a
add a,l
jr c,l24f7 ; (13)
jr z,l24f9 ; (13)
.l24ec dec a
ld c,a
call $22e5
exx
ld a,c
djnz $24ce ; (-39)
pop de
ret
.l24f7 jr z,l24ec ; (-13)
.l24f9 rst $8
ld a,(bc)
.l24fb rst $18
ld b,$00
push bc
.l24ff ld c,a
ld hl,$2596
call $16dc
ld a,c
jp nc,$2684
ld b,$00
ld c,(hl)
add hl,bc
jp (hl)
.l250f call $0074
inc bc
cp $0d
jp z,$1c8a
cp $22
jr nz,l250f ; (-13)
call $0074
cp $22
ret
.l2522 rst $20
cp $28
jr nz,l252d ; (6)
call $1c79
rst $18
cp $29
.l252d jp nz,$1c8a
.l2530 bit 7,(iy+$01)
ret
.l2535 call $2307
ld hl,(CHARS)
ld de,$0100
add hl,de
ld a,c
rrca
rrca
rrca
and $e0
xor b
ld e,a
ld a,c
and $18
xor $40
ld d,a
ld b,$60
.l254f push bc
push de
push hl
ld a,(de)
xor (hl)
jr z,l255a ; (4)
inc a
jr nz,l2573 ; (26)
dec a
.l255a ld c,a
ld b,$07
.l255d inc d
inc hl
ld a,(de)
xor (hl)
xor c
jr nz,l2573 ; (15)
djnz $255d ; (-9)
pop bc
pop bc
pop bc
ld a,$80
sub b
ld bc,$0001
rst $30
ld (de),a
jr l257d ; (10)
.l2573 pop hl
ld de,$0008
add hl,de
pop de
pop bc
djnz $254f ; (-45)
ld c,b
.l257d jp $2ab2
.l2580 call $2307
ld a,c
rrca
rrca
rrca
ld c,a
and $e0
xor b
ld l,a
ld a,c
and $03
xor $58
ld h,a
ld a,(hl)
jp $2d28
ld ($281c),hl
ld c,a
ld l,$f2
dec hl
ld (de),a
xor b
ld d,(hl)
and l
ld d,a
and a
add a,h
and (hl)
adc a,a
call nz,$aae6
cp a
xor e
rst $0
xor c
adc a,$00
rst $20
jp $24ff
rst $18
inc hl
push hl
ld bc,$0000
call $250f
jr nz,l25d9 ; (27)
.l25be call $250f
jr z,l25be ; (-5)
call $2530
jr z,l25d9 ; (17)
rst $30
pop hl
push de
.l25cb ld a,(hl)
inc hl
ld (de),a
inc de
cp $22
jr nz,l25cb ; (-8)
ld a,(hl)
inc hl
cp $22
jr z,l25cb ; (-14)
.l25d9 dec bc
pop de
.l25db ld hl,FLAGS
res 6,(hl)
bit 7,(hl)
call nz,$2ab2
jp $2712
rst $20
call $24fb
cp $29
jp nz,$1c8a
rst $20
jp $2712
jp $27bd
call $2530
jr z,l2625 ; (40)
ld bc,(SEED)
call $2d2b
rst $28
and c
rrca
inc (hl)
scf
ld d,$04
inc (hl)
add a,b
ld b,c
nop
nop
add a,b
ld ($a102),a
inc bc
ld sp,$cd38
and d
dec l
ld (SEED),bc
ld a,(hl)
and a
jr z,l2625 ; (3)
sub $10
ld (hl),a
.l2625 jr l2630 ; (9)
call $2530
jr z,l2630 ; (4)
rst $28
and e
defb $38
defb 52
.l2630 rst $20
jp $26c3
ld bc,$105a
rst $20
cp $23
jp z,$270d
ld hl,FLAGS
res 6,(hl)
bit 7,(hl)
jr z,l2665 ; (31)
jp $3a5a
ld c,$00
jr nz,l2660 ; (19)
call $031e
jr nc,l2660 ; (14)
dec d
ld e,a
call $0333
.l2657 push af
ld bc,$0001
rst $30
pop af
ld (de),a
ld c,$01
.l2660 ld b,$00
call $2ab2
.l2665 jp $2712
call $2522
call nz,$2535
rst $20
jp $25db
call $2522
call nz,$2580
rst $20
jr l26c3 ; (72)
call $2522
call nz,$22cb
rst $20
jr l26c3 ; (63)
.l2684 call $2c88
jr nc,l26df ; (86)
cp $41
jr nc,l26c9 ; (60)
call $2530
jr nz,l26b5 ; (35)
call $2c9b
rst $18
ld bc,$0006
call $1655
inc hl
ld (hl),$0e
inc hl
ex de,hl
ld hl,(STKEND)
ld c,$05
and a
sbc hl,bc
ld (STKEND),hl
ldir
ex de,hl
dec hl
call $0077
jr l26c3 ; (14)
.l26b5 rst $18
.l26b6 inc hl
ld a,(hl)
cp $0e
jr nz,l26b6 ; (-6)
inc hl
call $33b4
ld (CH_ADD),hl
.l26c3 set 6,(iy+$01)
jr l26dd ; (20)
.l26c9 call $28b2
jp c,$1c2e
call z,$2996
ld a,(FLAGS)
cp $c0
jr c,l26dd ; (4)
inc hl
call $33b4
.l26dd jr l2712 ; (51)
.l26df ld bc,$09db
cp $2d
jr z,l270d ; (39)
ld bc,$1018
cp $ae
jr z,l270d ; (32)
sub $af
jp c,$1c8a
ld bc,$04f0
cp $14
jr z,l270d ; (20)
jp nc,$1c8a
ld b,$10
add a,$dc
ld c,a
cp $df
jr nc,l2707 ; (2)
res 6,c
.l2707 cp $ee
jr c,l270d ; (2)
res 7,c
.l270d push bc
rst $20
jp $24ff
.l2712 rst $18
.l2713 cp $28
jr nz,l2723 ; (12)
bit 6,(iy+$01)
jr nz,l2734 ; (23)
call $2a52
rst $20
jr l2713 ; (-16)
.l2723 ld b,$00
ld c,a
ld hl,$2795
call $16dc
jr nc,l2734 ; (6)
ld c,(hl)
ld hl,$26ed
add hl,bc
ld b,(hl)
.l2734 pop de
ld a,d
cp b
jr c,l2773 ; (58)
and a
jp z,$0018
push bc
ld hl,FLAGS
ld a,e
cp $ed
jr nz,l274c ; (6)
bit 6,(hl)
jr nz,l274c ; (2)
ld e,$99
.l274c push de
call $2530
jr z,l275b ; (9)
ld a,e
and $3f
ld b,a
rst $28
dec sp
defb $38
defb 24
add hl,bc
.l275b ld a,e
xor (iy+$01)
and $40
.l2761 jp nz,$1c8a
pop de
ld hl,FLAGS
set 6,(hl)
bit 7,e
jr nz,l2770 ; (2)
res 6,(hl)
.l2770 pop bc
jr l2734 ; (-63)
.l2773 push de
ld a,c
bit 6,(iy+$01)
jr nz,l2790 ; (21)
and $3f
add a,$08
ld c,a
cp $10
jr nz,l2788 ; (4)
set 6,c
jr l2790 ; (8)
.l2788 jr c,l2761 ; (-41)
cp $17
jr z,l2790 ; (2)
set 7,c
.l2790 push bc
rst $20
jp $24ff
dec hl
rst $8
dec l
jp $c42a
cpl
push bc
ld e,(hl)
add a,$3d
adc a,$3e
call z,$cd3c
rst $0
ret
ret z
jp z,$cbc9
push bc
rst $0
add a,$c8
nop
ld b,$08
ex af,af'
ld a,(bc)
ld (bc),a
inc bc
dec b
dec b
dec b
dec b
dec b
dec b
ld b,$cd
defb $30
defb 37
jr nz,l27f7 ; (53)
rst $20
call $2c8d
jp nc,$1c8a
rst $20
cp $24
push af
jr nz,l27d0 ; (1)
rst $20
.l27d0 cp $28
jr nz,l27e6 ; (18)
rst $20
cp $29
jr z,l27e9 ; (16)
.l27d9 call $24fb
rst $18
cp $2c
jr nz,l27e4 ; (3)
rst $20
jr l27d9 ; (-11)
.l27e4 cp $29
.l27e6 jp nz,$1c8a
.l27e9 rst $20
ld hl,FLAGS
res 6,(hl)
pop af
jr z,l27f4 ; (2)
set 6,(hl)
.l27f4 jp $2712
.l27f7 rst $20
and $df
.l27fa ld b,a
rst $20
sub $24
ld c,a
jr nz,l2802 ; (1)
rst $20
.l2802 rst $20
push hl
ld hl,(PROG)
dec hl
.l2808 ld de,$00ce
push bc
call $1d86
pop bc
defb $30
defb 2
rst $8
jr l27fa ; (-27)
call $28ab
and $df
cp b
jr nz,l2825 ; (8)
call $28ab
sub $24
cp c
jr z,l2831 ; (12)
.l2825 pop hl
dec hl
ld de,$0200
push bc
call $198b
pop bc
jr l2808 ; (-41)
.l2831 and a
call z,$28ab
pop de
pop de
ld (CH_ADD),de
call $28ab
push hl
cp $29
jr z,l2885 ; (66)
.l2843 inc hl
ld a,(hl)
cp $0e
ld d,$40
jr z,l2852 ; (7)
dec hl
call $28ab
inc hl
ld d,$00
.l2852 inc hl
push hl
push de
call $24fb
pop af
xor (iy+$01)
and $40
jr nz,l288b ; (43)
pop hl
ex de,hl
ld hl,(STKEND)
ld bc,$0005
sbc hl,bc
ld (STKEND),hl
ldir
ex de,hl
dec hl
call $28ab
cp $29
jr z,l2885 ; (13)
push hl
rst $18
cp $2c
jr nz,l288b ; (13)
rst $20
pop hl
call $28ab
jr l2843 ; (-66)
.l2885 push hl
rst $18
cp $29
jr z,l288d ; (2)
.l288b rst $8
add hl,de
.l288d pop de
ex de,hl
ld (CH_ADD),hl
ld hl,(DEFADD)
ex (sp),hl
ld (DEFADD),hl
push de
rst $20
rst $20
call $24fb
pop hl
ld (CH_ADD),hl
pop hl
ld (DEFADD),hl
rst $20
jp $2712
.l28ab inc hl
ld a,(hl)
cp $21
jr c,l28ab ; (-6)
ret
.l28b2 set 6,(iy+$01)
rst $18
call $2c8d
jp nc,$1c8a
push hl
and $1f
ld c,a
rst $20
push hl
cp $28
jr z,l28ef ; (40)
set 6,c
cp $24
jr z,l28de ; (17)
set 5,c
call $2c88
jr nc,l28e3 ; (15)
.l28d4 call $2c88
jr nc,l28ef ; (22)
res 6,c
rst $20
jr l28d4 ; (-10)
.l28de rst $20
res 6,(iy+$01)
.l28e3 ld a,(DEFADD+1)
and a
jr z,l28ef ; (6)
call $2530
jp nz,$2951
.l28ef ld b,c
call $2530
jr nz,l28fd ; (8)
ld a,c
and $e0
set 7,a
ld c,a
jr l2934 ; (55)
.l28fd ld hl,(VARS)
.l2900 ld a,(hl)
and $7f
jr z,l2932 ; (45)
cp c
jr nz,l292a ; (34)
rla
add a,a
jp p,$293f
jr c,l293f ; (48)
pop de
push de
push hl
.l2912 inc hl
.l2913 ld a,(de)
inc de
cp $20
jr z,l2913 ; (-6)
or $20
cp (hl)
jr z,l2912 ; (-12)
or $80
cp (hl)
jr nz,l2929 ; (6)
ld a,(de)
call $2c88
jr nc,l293e ; (21)
.l2929 pop hl
.l292a push bc
call $19b8
ex de,hl
pop bc
jr l2900 ; (-50)
.l2932 set 7,b
.l2934 pop de
rst $18
cp $28
jr z,l2943 ; (9)
set 5,b
jr l294b ; (13)
.l293e pop de
.l293f pop de
pop de
push hl
rst $18
.l2943 call $2c88
jr nc,l294b ; (3)
rst $20
jr l2943 ; (-8)
.l294b pop hl
rl b
bit 6,b
ret
.l2951 ld hl,(DEFADD)
ld a,(hl)
cp $29
jp z,$28ef
.l295a ld a,(hl)
or $60
ld b,a
inc hl
ld a,(hl)
cp $0e
jr z,l296b ; (7)
dec hl
call $28ab
inc hl
res 5,b
.l296b ld a,b
cp c
jr z,l2981 ; (18)
inc hl
inc hl
inc hl
inc hl
inc hl
call $28ab
cp $29
jp z,$28ef
call $28ab
jr l295a ; (-39)
.l2981 bit 5,c
jr nz,l2991 ; (12)
inc hl
ld de,(STKEND)
call $33c0
ex de,hl
ld (STKEND),hl
.l2991 pop de
pop de
xor a
inc a
ret
.l2996 xor a
ld b,a
bit 7,c
jr nz,l29e7 ; (75)
bit 7,(hl)
jr nz,l29ae ; (14)
inc a
.l29a1 inc hl
ld c,(hl)
inc hl
ld b,(hl)
inc hl
ex de,hl
call $2ab2
rst $18
jp $2a49
.l29ae inc hl
inc hl
inc hl
ld b,(hl)
bit 6,c
jr z,l29c0 ; (10)
dec b
jr z,l29a1 ; (-24)
ex de,hl
rst $18
cp $28
jr nz,l2a20 ; (97)
ex de,hl
.l29c0 ex de,hl
jr l29e7 ; (36)
.l29c3 push hl
rst $18
pop hl
cp $2c
jr z,l29ea ; (32)
bit 7,c
jr z,l2a20 ; (82)
bit 6,c
jr nz,l29d8 ; (6)
cp $29
jr nz,l2a12 ; (60)
rst $20
ret
.l29d8 cp $29
jr z,l2a48 ; (108)
cp $cc
jr nz,l2a12 ; (50)
.l29e0 rst $18
dec hl
ld (CH_ADD),hl
jr l2a45 ; (94)
.l29e7 ld hl,$0000
.l29ea push hl
rst $20
pop hl
ld a,c
cp $c0
jr nz,l29fb ; (9)
rst $18
cp $29
jr z,l2a48 ; (81)
cp $cc
jr z,l29e0 ; (-27)
.l29fb push bc
push hl
call $2aee
ex (sp),hl
ex de,hl
call $2acc
jr c,l2a20 ; (25)
dec bc
call $2af4
add hl,bc
pop de
pop bc
djnz $29c3 ; (-77)
bit 7,c
.l2a12 jr nz,l2a7a ; (102)
push hl
bit 6,c
jr nz,l2a2c ; (19)
ld b,d
ld c,e
rst $18
cp $29
jr z,l2a22 ; (2)
.l2a20 rst $8
ld (bc),a
.l2a22 rst $20
pop hl
ld de,$0005
call $2af4
add hl,bc
ret
.l2a2c call $2aee
ex (sp),hl
call $2af4
pop bc
add hl,bc
inc hl
ld b,d
ld c,e
ex de,hl
call $2ab1
rst $18
cp $29
jr z,l2a48 ; (7)
cp $2c
jr nz,l2a20 ; (-37)
.l2a45 call $2a52
.l2a48 rst $20
.l2a49 cp $28
jr z,l2a45 ; (-8)
res 6,(iy+$01)
ret
.l2a52 call $2530
call nz,$2bf1
rst $20
cp $29
jr z,l2aad ; (80)
push de
xor a
push af
push bc
ld de,$0001
rst $18
pop hl
cp $cc
jr z,l2a81 ; (23)
pop af
call $2acd
push af
ld d,b
ld e,c
push hl
rst $18
pop hl
cp $cc
jr z,l2a81 ; (9)
cp $29
.l2a7a jp nz,$1c8a
ld h,d
ld l,e
jr l2a94 ; (19)
.l2a81 push hl
rst $20
pop hl
cp $29
jr z,l2a94 ; (12)
pop af
call $2acd
push af
rst $18
ld h,b
ld l,c
cp $29
jr nz,l2a7a ; (-26)
.l2a94 pop af
ex (sp),hl
add hl,de
dec hl
ex (sp),hl
and a
sbc hl,de
ld bc,$0000
jr c,l2aa8 ; (7)
inc hl
and a
jp m,$2a20
ld b,h
ld c,l
.l2aa8 pop de
res 6,(iy+$01)
.l2aad call $2530
ret z
.l2ab1 xor a
.l2ab2 res 6,(iy+$01)
.l2ab6 push bc
call $33a9
pop bc
ld hl,(STKEND)
ld (hl),a
inc hl
ld (hl),e
inc hl
ld (hl),d
inc hl
ld (hl),c
inc hl
ld (hl),b
inc hl
ld (STKEND),hl
ret
.l2acc xor a
.l2acd push de
push hl
push af
call $1c82
pop af
call $2530
jr z,l2aeb ; (18)
push af
call $1e99
pop de
ld a,b
or c
scf
jr z,l2ae8 ; (5)
pop hl
push hl
and a
sbc hl,bc
.l2ae8 ld a,d
sbc a,$00
.l2aeb pop hl
pop de
ret
.l2aee ex de,hl
inc hl
ld e,(hl)
inc hl
ld d,(hl)
ret
.l2af4 call $2530
ret z
call $30a9
jp c,$1f15
ret
.l2aff ld hl,(DEST)
bit 1,(iy+$37)
jr z,l2b66 ; (94)
ld bc,$0005
.l2b0b inc bc
.l2b0c inc hl
ld a,(hl)
cp $20
jr z,l2b0c ; (-6)
jr nc,l2b1f ; (11)
cp $10
jr c,l2b29 ; (17)
cp $16
jr nc,l2b29 ; (13)
inc hl
jr l2b0c ; (-19)
.l2b1f call $2c88
jr c,l2b0b ; (-25)
cp $24
jp z,$2bc0
.l2b29 ld a,c
ld hl,(E_LINE)
dec hl
call $1655
inc hl
inc hl
ex de,hl
push de
ld hl,(DEST)
dec de
sub $06
ld b,a
jr z,l2b4f ; (17)
.l2b3e inc hl
.l2b3f ld a,(hl)
cp $21
jr c,l2b3e ; (-6)
or $20
inc de
ld (de),a
djnz $2b3e ; (-12)
or $80
ld (de),a
ld a,$c0
.l2b4f ld hl,(DEST)
xor (hl)
or $20
pop hl
call $2bea
.l2b59 push hl
rst $28
ld (bc),a
jr c,l2b3f ; (-31)
ld bc,$0005
and a
sbc hl,bc
jr l2ba6 ; (64)
.l2b66 bit 6,(iy+$01)
jr z,l2b72 ; (6)
ld de,$0006
add hl,de
jr l2b59 ; (-25)
.l2b72 ld hl,(DEST)
ld bc,(STRLEN)
bit 0,(iy+$37)
jr nz,l2baf ; (48)
ld a,b
or c
ret z
push hl
rst $30
push de
push bc
ld d,h
ld e,l
inc hl
ld (hl),$20
lddr
push hl
call $2bf1
pop hl
ex (sp),hl
and a
sbc hl,bc
add hl,bc
jr nc,l2b9b ; (2)
ld b,h
ld c,l
.l2b9b ex (sp),hl
ex de,hl
ld a,b
or c
jr z,l2ba3 ; (2)
ldir
.l2ba3 pop bc
pop de
pop hl
.l2ba6 ex de,hl
ld a,b
or c
ret z
push de
ldir
pop hl
ret
.l2baf dec hl
dec hl
dec hl
ld a,(hl)
push hl
push bc
call $2bc6
pop bc
pop hl
inc bc
inc bc
inc bc
jp $19e8
.l2bc0 ld a,$df
ld hl,(DEST)
and (hl)
.l2bc6 push af
call $2bf1
ex de,hl
add hl,bc
push bc
dec hl
ld (DEST),hl
inc bc
inc bc
inc bc
ld hl,(E_LINE)
dec hl
call $1655
ld hl,(DEST)
pop bc
push bc
inc bc
lddr
ex de,hl
inc hl
pop bc
ld (hl),b
dec hl
ld (hl),c
pop af
.l2bea dec hl
ld (hl),a
ld hl,(E_LINE)
dec hl
ret
.l2bf1 ld hl,(STKEND)
dec hl
ld b,(hl)
dec hl
ld c,(hl)
dec hl
ld d,(hl)
dec hl
ld e,(hl)
dec hl
ld a,(hl)
ld (STKEND),hl
ret
call $28b2
.l2c05 jp nz,$1c8a
call $2530
jr nz,l2c15 ; (8)
res 6,c
call $2996
call $1bee
.l2c15 jr c,l2c1f ; (8)
push bc
call $19b8
call $19e8
pop bc
.l2c1f set 7,c
ld b,$00
push bc
ld hl,$0001
bit 6,c
jr nz,l2c2d ; (2)
ld l,$05
.l2c2d ex de,hl
.l2c2e rst $20
ld h,$ff
call $2acc
jp c,$2a20
pop hl
push bc
inc h
push hl
ld h,b
ld l,c
call $2af4
ex de,hl
rst $18
cp $2c
jr z,l2c2e ; (-24)
cp $29
jr nz,l2c05 ; (-69)
rst $20
pop bc
ld a,c
ld l,b
ld h,$00
inc hl
inc hl
add hl,hl
add hl,de
jp c,$1f15
push de
push bc
push hl
ld b,h
ld c,l
ld hl,(E_LINE)
dec hl
call $1655
inc hl
ld (hl),a
pop bc
dec bc
dec bc
dec bc
inc hl
ld (hl),c
inc hl
ld (hl),b
pop bc
ld a,b
inc hl
ld (hl),a
ld h,d
ld l,e
dec de
ld (hl),$00
bit 6,c
jr z,l2c7c ; (2)
ld (hl),$20
.l2c7c pop bc
lddr
.l2c7f pop bc
ld (hl),b
dec hl
ld (hl),c
dec hl
dec a
jr nz,l2c7f ; (-8)
ret
.l2c88 call $2d1b
ccf
ret c
.l2c8d cp $41
ccf
ret nc
cp $5b
ret c
cp $61
ccf
ret nc
cp $7b
ret
.l2c9b cp $c4
jr nz,l2cb8 ; (25)
ld de,$0000
.l2ca2 rst $20
sub $31
adc a,$00
jr nz,l2cb3 ; (10)
ex de,hl
ccf
adc hl,hl
jp c,$31ad
ex de,hl
jr l2ca2 ; (-17)
.l2cb3 ld b,d
ld c,e
jp $2d2b
.l2cb8 cp $2e
.l2cba jr z,l2ccb ; (15)
call $2d3b
cp $2e
jr nz,l2ceb ; (40)
rst $20
call $2d1b
jr c,l2ceb ; (34)
defb $18
defb 10
.l2ccb rst $20
call $2d1b
.l2ccf jp c,$1c8a
rst $28
and b
defb $38
defb -17
and c
ret nz
ld (bc),a
jr c,l2cba ; (-33)
call $2d22
jr c,l2ceb ; (11)
rst $28
.l2ce1 ret po
and h
dec b
ret nz
inc b
rrca
defb $38
defb -25
defb $18
defb -17
.l2ceb cp $45
jr z,l2cf2 ; (3)
cp $65
ret nz
.l2cf2 ld b,$ff
rst $20
cp $2b
jr z,l2cfe ; (5)
cp $2d
jr nz,l2cff ; (2)
inc b
.l2cfe rst $20
.l2cff call $2d1b
jr c,l2ccf ; (-53)
push bc
call $2d3b
call $2dd5
pop bc
jp c,$31ad
and a
jp m,$31ad
inc b
jr z,l2d18 ; (2)
neg
.l2d18 jp $2d4f
.l2d1b cp $30
ret c
cp $3a
ccf
ret
.l2d22 call $2d1b
ret c
sub $30
.l2d28 ld c,a
ld b,$00
.l2d2b ld iy,ERR_NR
xor a
ld e,a
.l2d31 ld d,c
ld c,b
ld b,a
call $2ab6
rst $28
jr c,l2ce1 ; (-89)
ret
.l2d3b push af
rst $28
and b
jr c,l2d31 ; (-15)
.l2d40 call $2d22
ret c
rst $28
ld bc,$04a4
.l2d48 rrca
jr c,l2d18 ; (-51)
ld (hl),h
nop
jr l2d40 ; (-15)
.l2d4f rlca
rrca
.l2d51 jr nc,l2d55 ; (2)
cpl
inc a
.l2d55 push af
ld hl,MEMBOT
call $350b
rst $28
and h
jr c,l2d51 ; (-15)
.l2d60 srl a
.l2d62 jr nc,l2d71 ; (13)
push af
rst $28
pop bc
ret po
nop
inc b
inc b
.l2d6b inc sp
ld (bc),a
dec b
pop hl
jr c,l2d62 ; (-15)
.l2d71 jr z,l2d7b ; (8)
push af
rst $28
ld sp,$3804
pop af
jr l2d60 ; (-27)
.l2d7b rst $28
ld (bc),a
jr c,l2d48 ; (-55)
.l2d7f inc hl
ld c,(hl)
inc hl
ld a,(hl)
xor c
sub c
ld e,a
inc hl
ld a,(hl)
adc a,c
xor c
ld d,a
ret
ld c,$00
.l2d8e push hl
ld (hl),$00
inc hl
ld (hl),c
inc hl
ld a,e
xor c
.l2d96 sub c
ld (hl),a
inc hl
ld a,d
adc a,c
xor c
ld (hl),a
.l2d9d inc hl
ld (hl),$00
pop hl
ret
.l2da2 rst $28
.l2da3 defb $38
defb 126
and a
defb $28
defb 5
rst $28
and d
rrca
daa
jr c,l2d9d ; (-17)
ld (bc),a
jr c,l2d96 ; (-27)
push de
ex de,hl
ld b,(hl)
call $2d7f
xor a
sub b
bit 7,c
ld b,d
ld c,e
ld a,e
pop de
pop hl
ret
.l2dc1 ld d,a
rla
sbc a,a
ld e,a
ld c,a
xor a
ld b,a
.l2dc8 call $2ab6
rst $28
inc (hl)
rst $28
ld a,(de)
jr nz,l2d6b ; (-102)
add a,l
inc b
daa
jr c,l2da3 ; (-51)
and d
dec l
.l2dd8 ret c
push af
dec b
inc b
jr z,l2de1 ; (3)
pop af
scf
ret
.l2de1 pop af
ret
.l2de3 rst $28
ld sp,$0036
dec bc
ld sp,$0037
dec c
ld (bc),a
jr c,l2e2d ; (62)
jr nc,l2dc8 ; (-41)
ret
ld hl,($3e38)
dec l
rst $10
rst $28
and b
jp $c5c4
ld (bc),a
jr c,l2dd8 ; (-39)
push hl
exx
.l2e01 rst $28
ld sp,$c227
inc bc
jp po,$c201
ld (bc),a
jr c,l2e8a ; (126)
and a
jr nz,l2e56 ; (71)
call $2d7f
ld b,$10
ld a,d
and a
jr nz,l2e1e ; (6)
or e
jr z,l2e24 ; (9)
ld d,e
ld b,$08
.l2e1e push de
exx
pop de
exx
jr l2e7b ; (87)
.l2e24 rst $28
jp po,$7e38
sub $7e
call $2dc1
.l2e2d ld d,a
ld a,(MEMBOT+$1a)
sub d
ld (MEMBOT+$1a),a
ld a,d
call $2d4f
rst $28
ld sp,$c127
inc bc
pop hl
defb $38
defb -51
push de
dec l
push hl
ld (MEMBOT+$0f),a
dec a
rla
sbc a,a
inc a
ld hl,MEMBOT+$19
ld (hl),a
inc hl
add a,(hl)
ld (hl),a
pop hl
jp $2ecf
.l2e56 sub $80
cp $1c
jr c,l2e6f ; (19)
call $2dc1
sub $07
ld b,a
ld hl,MEMBOT+$1a
add a,(hl)
ld (hl),a
ld a,b
neg
call $2d4f
jr l2e01 ; (-110)
.l2e6f ex de,hl
call $2fba
exx
set 7,d
ld a,l
exx
sub $80
ld b,a
.l2e7b sla e
rl d
exx
rl e
rl d
exx
ld hl,MEMBOT+$18
ld c,$05
.l2e8a ld a,(hl)
adc a,a
daa
ld (hl),a
dec hl
dec c
jr nz,l2e8a ; (-8)
djnz $2e7b ; (-25)
xor a
ld hl,MEMBOT+$14
ld de,MEMBOT+$0f
ld b,$09
rld
ld c,$ff
.l2ea1 rld
jr nz,l2ea9 ; (4)
dec c
inc c
jr nz,l2eb3 ; (10)
.l2ea9 ld (de),a
inc de
inc (iy+$71)
inc (iy+$72)
ld c,$00
.l2eb3 bit 0,b
jr z,l2eb8 ; (1)
inc hl
.l2eb8 djnz $2ea1 ; (-25)
ld a,(MEMBOT+$19)
sub $09
jr c,l2ecb ; (10)
dec (iy+$71)
ld a,$04
cp (iy+$6f)
jr l2f0c ; (65)
.l2ecb rst $28
ld (bc),a
jp po,$eb38
call $2fba
exx
ld a,$80
sub l
ld l,$00
set 7,d
exx
call $2fdd
.l2edf ld a,(iy+$71)
cp $08
jr c,l2eec ; (6)
exx
rl d
exx
jr l2f0c ; (32)
.l2eec ld bc,$0200
.l2eef ld a,e
call $2f8b
ld e,a
ld a,d
call $2f8b
ld d,a
push bc
exx
pop bc
djnz $2eef ; (-15)
ld hl,MEMBOT+$0f
ld a,c
ld c,(iy+$71)
add hl,bc
ld (hl),a
inc (iy+$71)
jr l2edf ; (-45)
.l2f0c push af
.l2f0d ld hl,MEMBOT+$0f
ld c,(iy+$71)
ld b,$00
add hl,bc
ld b,c
pop af
.l2f18 dec hl
ld a,(hl)
adc a,$00
ld (hl),a
and a
jr z,l2f25 ; (5)
cp $0a
ccf
jr nc,l2f2d ; (8)
.l2f25 djnz $2f18 ; (-15)
ld (hl),$01
inc b
inc (iy+$72)
.l2f2d ld (iy+$71),b
rst $28
ld (bc),a
jr c,l2f0d ; (-39)
pop hl
exx
ld bc,(MEMBOT+$19)
ld hl,MEMBOT+$0f
ld a,b
cp $09
jr c,l2f46 ; (4)
cp $fc
jr c,l2f6c ; (38)
.l2f46 and a
call z,$15ef
.l2f4a xor a
sub b
jp m,$2f52
ld b,a
jr l2f5e ; (12)
.l2f52 ld a,c
and a
jr z,l2f59 ; (3)
ld a,(hl)
inc hl
dec c
.l2f59 call $15ef
djnz $2f52 ; (-12)
.l2f5e ld a,c
and a
ret z
inc b
ld a,$2e
.l2f64 rst $10
ld a,$30
djnz $2f64 ; (-5)
ld b,c
jr l2f52 ; (-26)
.l2f6c ld d,b
dec d
ld b,$01
call $2f4a
ld a,$45
rst $10
ld c,d
ld a,c
and a
jp p,$2f83
neg
ld c,a
ld a,$2d
jr l2f85 ; (2)
.l2f83 ld a,$2b
.l2f85 rst $10
ld b,$00
jp $1a1b
.l2f8b push de
ld l,a
ld h,$00
ld e,l
ld d,h
add hl,hl
add hl,hl
add hl,de
add hl,hl
ld e,c
add hl,de
ld c,h
ld a,l
pop de
ret
.l2f9b ld a,(hl)
ld (hl),$00
and a
ret z
inc hl
bit 7,(hl)
set 7,(hl)
dec hl
ret z
push bc
ld bc,$0005
add hl,bc
ld b,c
ld c,a
scf
.l2faf dec hl
ld a,(hl)
cpl
adc a,$00
ld (hl),a
djnz $2faf ; (-8)
ld a,c
pop bc
ret
.l2fba push hl
push af
ld c,(hl)
inc hl
ld b,(hl)
ld (hl),a
inc hl
ld a,c
ld c,(hl)
push bc
inc hl
ld c,(hl)
inc hl
ld b,(hl)
ex de,hl
ld d,a
ld e,(hl)
push de
inc hl
ld d,(hl)
inc hl
ld e,(hl)
push de
exx
pop de
pop hl
pop bc
exx
inc hl
ld d,(hl)
inc hl
ld e,(hl)
pop af
pop hl
ret
.l2fdd and a
ret z
cp $21
jr nc,l2ff9 ; (22)
push bc
ld b,a
.l2fe5 exx
sra l
rr d
rr e
exx
rr d
rr e
djnz $2fe5 ; (-14)
pop bc
ret nc
call $3004
ret nz
.l2ff9 exx
xor a
.l2ffb ld l,$00
ld d,a
ld e,l
exx
ld de,$0000
ret
.l3004 inc e
ret nz
inc d
ret nz
exx
inc e
jr nz,l300d ; (1)
inc d
.l300d exx
ret
.l300f ex de,hl
call $346e
ex de,hl
ld a,(de)
or (hl)
jr nz,l303e ; (38)
push de
inc hl
push hl
inc hl
ld e,(hl)
inc hl
ld d,(hl)
inc hl
inc hl
inc hl
ld a,(hl)
inc hl
ld c,(hl)
inc hl
ld b,(hl)
pop hl
ex de,hl
add hl,bc
ex de,hl
adc a,(hl)
rrca
adc a,$00
jr nz,l303c ; (11)
sbc a,a
ld (hl),a
inc hl
ld (hl),e
inc hl
ld (hl),d
dec hl
dec hl
dec hl
pop de
ret
.l303c dec hl
pop de
.l303e call $3293
exx
push hl
exx
push de
push hl
call $2f9b
ld b,a
ex de,hl
call $2f9b
ld c,a
cp b
jr nc,l3055 ; (3)
ld a,b
ld b,c
ex de,hl
.l3055 push af
sub b
call $2fba
call $2fdd
pop af
pop hl
ld (hl),a
push hl
ld l,b
ld h,c
add hl,de
exx
ex de,hl
adc hl,bc
ex de,hl
ld a,h
adc a,l
ld l,a
rra
xor l
exx
ex de,hl
pop hl
rra
jr nc,l307c ; (8)
ld a,$01
call $2fdd
inc (hl)
jr z,l309f ; (35)
.l307c exx
ld a,l
and $80
exx
inc hl
ld (hl),a
dec hl
jr z,l30a5 ; (31)
ld a,e
neg
ccf
ld e,a
ld a,d
cpl
adc a,$00
ld d,a
exx
ld a,e
cpl
adc a,$00
ld e,a
ld a,d
cpl
adc a,$00
jr nc,l30a3 ; (7)
rra
exx
inc (hl)
.l309f jp z,$31ad
exx
.l30a3 ld d,a
exx
.l30a5 xor a
jp $3155
.l30a9 push bc
ld b,$10
ld a,h
ld c,l
ld hl,$0000
.l30b1 add hl,hl
jr c,l30be ; (10)
rl c
rla
jr nc,l30bc ; (3)
add hl,de
jr c,l30be ; (2)
.l30bc djnz $30b1 ; (-13)
.l30be pop bc
ret
.l30c0 call $34e9
ret c
inc hl
xor (hl)
set 7,(hl)
dec hl
ret
ld a,(de)
or (hl)
jr nz,l30f0 ; (34)
push de
push hl
push de
call $2d7f
ex de,hl
ex (sp),hl
ld b,c
call $2d7f
ld a,b
xor c
ld c,a
pop hl
call $30a9
ex de,hl
pop hl
jr c,l30ef ; (10)
ld a,d
or e
jr nz,l30ea ; (1)
ld c,a
.l30ea call $2d8e
pop de
ret
.l30ef pop de
.l30f0 call $3293
xor a
call $30c0
ret c
exx
push hl
exx
push de
ex de,hl
call $30c0
ex de,hl
jr c,l315d ; (90)
push hl
call $2fba
ld a,b
and a
sbc hl,hl
exx
push hl
sbc hl,hl
exx
ld b,$21
jr l3125 ; (17)
.l3114 jr nc,l311b ; (5)
add hl,de
exx
adc hl,de
exx
.l311b exx
rr h
rr l
exx
rr h
rr l
.l3125 exx
rr b
rr c
exx
rr c
rra
djnz $3114 ; (-28)
ex de,hl
exx
ex de,hl
exx
pop bc
pop hl
ld a,b
add a,c
jr nz,l313b ; (1)
and a
.l313b dec a
ccf
.l313d rla
ccf
rra
jp p,$3146
jr nc,l31ad ; (104)
and a
.l3146 inc a
jr nz,l3151 ; (8)
jr c,l3151 ; (6)
exx
bit 7,d
exx
jr nz,l31ad ; (92)
.l3151 ld (hl),a
exx
ld a,b
exx
.l3155 jr nc,l316c ; (21)
ld a,(hl)
and a
.l3159 ld a,$80
jr z,l315e ; (1)
.l315d xor a
.l315e exx
and d
call $2ffb
rlca
ld (hl),a
jr c,l3195 ; (46)
inc hl
ld (hl),a
dec hl
jr l3195 ; (41)
.l316c ld b,$20
.l316e exx
bit 7,d
exx
jr nz,l3186 ; (18)
rlca
rl e
rl d
exx
rl e
rl d
exx
dec (hl)
jr z,l3159 ; (-41)
djnz $316e ; (-22)
jr l315d ; (-41)
.l3186 rla
jr nc,l3195 ; (12)
call $3004
jr nz,l3195 ; (7)
exx
ld d,$80
exx
inc (hl)
jr z,l31ad ; (24)
.l3195 push hl
inc hl
exx
push de
exx
pop bc
ld a,b
rla
rl (hl)
rra
ld (hl),a
inc hl
ld (hl),c
inc hl
ld (hl),d
inc hl
ld (hl),e
pop hl
pop de
exx
pop hl
exx
ret
.l31ad rst $8
dec b
call $3293
ex de,hl
xor a
call $30c0
jr c,l31ad ; (-12)
ex de,hl
call $30c0
ret c
exx
push hl
exx
push de
push hl
call $2fba
exx
push hl
ld h,b
ld l,c
exx
ld h,c
ld l,b
xor a
ld b,$df
jr l31e2 ; (16)
.l31d2 rla
rl c
exx
rl c
rl b
exx
add hl,hl
exx
adc hl,hl
exx
jr c,l31f2 ; (16)
.l31e2 sbc hl,de
exx
sbc hl,de
exx
jr nc,l31f9 ; (15)
add hl,de
exx
adc hl,de
exx
and a
jr l31fa ; (8)
.l31f2 and a
sbc hl,de
exx
sbc hl,de
exx
.l31f9 scf
.l31fa inc b
jp m,$31d2
push af
jr z,l31e2 ; (-31)
ld e,a
ld d,c
exx
ld e,c
ld d,b
pop af
rr b
pop af
rr b
exx
pop bc
pop hl
ld a,b
sub c
jp $313d
ld a,(hl)
and a
ret z
cp $81
jr nc,l3221 ; (6)
ld (hl),$00
ld a,$20
jr l3272 ; (81)
.l3221 cp $91
jr nz,l323f ; (26)
inc hl
inc hl
inc hl
ld a,$80
and (hl)
dec hl
or (hl)
dec hl
jr nz,l3233 ; (3)
ld a,$80
xor (hl)
.l3233 dec hl
jr nz,l326c ; (54)
ld (hl),a
inc hl
ld (hl),$ff
dec hl
ld a,$18
jr l3272 ; (51)
.l323f jr nc,l326d ; (44)
push de
cpl
add a,$91
inc hl
ld d,(hl)
inc hl
ld e,(hl)
dec hl
dec hl
ld c,$00
bit 7,d
jr z,l3252 ; (1)
dec c
.l3252 set 7,d
ld b,$08
sub b
add a,b
jr c,l325e ; (4)
ld e,d
ld d,$00
sub b
.l325e jr z,l3267 ; (7)
ld b,a
.l3261 srl d
rr e
djnz $3261 ; (-6)
.l3267 call $2d8e
pop de
ret
.l326c ld a,(hl)
.l326d sub $a0
ret p
neg
.l3272 push de
ex de,hl
dec hl
ld b,a
srl b
srl b
srl b
jr z,l3283 ; (5)
.l327e ld (hl),$00
dec hl
djnz $327e ; (-5)
.l3283 and $07
jr z,l3290 ; (9)
ld b,a
ld a,$ff
.l328a sla a
djnz $328a ; (-4)
and (hl)
ld (hl),a
.l3290 ex de,hl
.l3291 pop de
ret
.l3293 call $3296
.l3296 ex de,hl
.l3297 ld a,(hl)
and a
ret nz
push de
call $2d7f
xor a
inc hl
ld (hl),a
dec hl
ld (hl),a
ld b,$91
ld a,d
and a
jr nz,l32b1 ; (8)
or e
.l32aa ld b,d
jr z,l32bd ; (16)
ld d,e
ld e,b
ld b,$89
.l32b1 ex de,hl
.l32b2 dec b
add hl,hl
jr nc,l32b2 ; (-4)
rrc c
rr h
rr l
.l32bc ex de,hl
.l32bd dec hl
ld (hl),e
dec hl
ld (hl),d
dec hl
ld (hl),b
pop de
ret
nop
or b
nop
ld b,b
or b
nop
ld bc,$0030
pop af
ld c,c
rrca
jp c,$40a2
or b
nop
ld a,(bc)
adc a,a
ld (hl),$3c
inc (hl)
and c
inc sp
rrca
jr nc,l32aa ; (-54)
jr nc,l3291 ; (-81)
ld sp,$3851
dec de
dec (hl)
inc h
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
inc d
defb $30
defb 45
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
dec (hl)
dec sp
.l3302 dec (hl)
dec sp
dec (hl)
sbc a,h
dec (hl)
sbc a,$35
cp h
inc (hl)
ld b,l
ld (hl),$6e
inc (hl)
ld l,c
ld (hl),$de
dec (hl)
ld (hl),h
ld (hl),$b5
scf
xor d
scf
jp c,$3337
defb $38
defb 67
jr c,l3302 ; (-30)
scf
inc de
scf
call nz,$af36
ld (hl),$4a
jr c,l32bc ; (-110)
inc (hl)
ld l,d
inc (hl)
xor h
inc (hl)
and l
inc (hl)
or e
inc (hl)
rra
ld (hl),$c9
dec (hl)
.l3337 ld bc,$c035
inc sp
and b
ld (hl),$86
ld (hl),$c6
inc sp
ld a,d
ld (hl),$06
dec (hl)
ld sp,hl
inc (hl)
sbc a,e
ld (hl),$83
scf
inc d
ld ($33a2),a
ld c,a
dec l
sub a
ld ($3449),a
dec de
inc (hl)
dec l
inc (hl)
rrca
inc (hl)
.l335b call $35bf
.l335e ld a,b
ld (BREG),a
.l3362 exx
ex (sp),hl
exx
ld (STKEND),de
exx
ld a,(hl)
inc hl
.l336c push hl
and a
jp p,$3380
ld d,a
and $60
rrca
rrca
rrca
rrca
add a,$7c
ld l,a
ld a,d
and $1f
jr l338e ; (14)
.l3380 cp $18
jr nc,l338c ; (8)
exx
ld bc,$fffb
ld d,h
ld e,l
add hl,bc
exx
.l338c rlca
ld l,a
.l338e ld de,$32d7
ld h,$00
add hl,de
ld e,(hl)
inc hl
ld d,(hl)
ld hl,$3365
ex (sp),hl
push de
exx
ld bc,(STKEND+1)
ret
pop af
ld a,(BREG)
exx
jr l336c ; (-61)
.l33a9 push de
push hl
ld bc,$0005
call $1f05
pop hl
pop de
ret
.l33b4 ld de,(STKEND)
call $33c0
ld (STKEND),de
ret
.l33c0 call $33a9
ldir
ret
ld h,d
ld l,e
.l33c8 call $33a9
exx
push hl
exx
ex (sp),hl
push bc
ld a,(hl)
and $c0
rlca
rlca
ld c,a
inc c
ld a,(hl)
and $3f
jr nz,l33de ; (2)
inc hl
ld a,(hl)
.l33de add a,$50
ld (de),a
ld a,$05
sub c
inc hl
inc de
ld b,$00
ldir
pop bc
ex (sp),hl
exx
pop hl
exx
ld b,a
xor a
.l33f1 dec b
ret z
ld (de),a
inc de
jr l33f1 ; (-6)
.l33f7 and a
.l33f8 ret z
push af
push de
ld de,$0000
call $33c8
pop de
pop af
dec a
jr l33f8 ; (-14)
.l3406 ld c,a
rlca
rlca
add a,c
ld c,a
ld b,$00
add hl,bc
ret
push de
ld hl,(MEM)
call $3406
call $33c0
pop hl
ret
ld h,d
ld l,e
exx
push hl
ld hl,$32c5
exx
call $33f7
call $33c8
exx
pop hl
exx
ret
push hl
ex de,hl
ld hl,(MEM)
call $3406
ex de,hl
call $33c0
ex de,hl
pop hl
ret
.l343c ld b,$05
.l343e ld a,(de)
ld c,(hl)
ex de,hl
ld (de),a
ld (hl),c
inc hl
inc de
djnz $343e ; (-9)
ex de,hl
ret
ld b,a
call $335e
ld sp,$c00f
ld (bc),a
and b
jp nz,$e031
inc b
jp po,$03c1
defb $38
defb -51
add a,$33
call $3362
rrca
ld bc,$02c2
dec (hl)
xor $e1
inc bc
defb $38
defb -55
ld b,$ff
jr l3474 ; (6)
.l346e call $34e9
ret c
ld b,$00
.l3474 ld a,(hl)
and a
jr z,l3483 ; (11)
inc hl
ld a,b
and $80
or (hl)
rla
ccf
rra
ld (hl),a
dec hl
ret
.l3483 push de
push hl
call $2d7f
pop hl
ld a,b
or c
cpl
ld c,a
call $2d8e
pop de
ret
call $34e9
ret c
push de
ld de,$0001
inc hl
rl (hl)
dec hl
sbc a,a
ld c,a
call $2d8e
pop de
ret
call $1e99
in a,(c)
jr l34b0 ; (4)
call $1e99
ld a,(bc)
.l34b0 jp $2d28
call $1e99
ld hl,$2d2b
push hl
push bc
ret
call $2bf1
dec bc
ld a,b
or c
jr nz,l34e7 ; (35)
ld a,(de)
call $2c8d
jr c,l34d3 ; (9)
sub $90
jr c,l34e7 ; (25)
cp $15
jr nc,l34e7 ; (21)
inc a
.l34d3 dec a
add a,a
add a,a
add a,a
cp $a8
jr nc,l34e7 ; (12)
ld bc,(UDG)
add a,c
ld c,a
jr nc,l34e4 ; (1)
inc b
.l34e4 jp $2d2b
.l34e7 rst $8
add hl,bc
.l34e9 push hl
push bc
ld b,a
ld a,(hl)
inc hl
or (hl)
inc hl
or (hl)
inc hl
or (hl)
ld a,b
pop bc
pop hl
ret nz
scf
ret
.l34f9 call $34e9
ret c
ld a,$ff
jr l3507 ; (6)
.l3501 call $34e9
jr l350b ; (5)
xor a
.l3507 inc hl
xor (hl)
dec hl
rlca
.l350b push hl
ld a,$00
ld (hl),a
inc hl
ld (hl),a
inc hl
rla
ld (hl),a
rra
inc hl
ld (hl),a
inc hl
ld (hl),a
pop hl
ret
ex de,hl
call $34e9
ex de,hl
ret c
scf
jr l350b ; (-25)
ex de,hl
call $34e9
ex de,hl
ret nc
and a
jr l350b ; (-34)
ex de,hl
call $34e9
ex de,hl
ret nc
push de
dec de
xor a
ld (de),a
dec de
ld (de),a
pop de
ret
ld a,b
sub $08
bit 2,a
jr nz,l3543 ; (1)
dec a
.l3543 rrca
jr nc,l354e ; (8)
push af
push hl
call $343c
pop de
ex de,hl
pop af
.l354e bit 2,a
jr nz,l3559 ; (7)
rrca
push af
call $300f
defb $18
defb 51
.l3559 rrca
push af
call $2bf1
push de
push bc
call $2bf1
pop hl
.l3564 ld a,h
or l
ex (sp),hl
ld a,b
jr nz,l3575 ; (11)
or c
.l356b pop bc
jr z,l3572 ; (4)
pop af
ccf
jr l3588 ; (22)
.l3572 pop af
jr l3588 ; (19)
.l3575 or c
jr z,l3585 ; (13)
ld a,(de)
sub (hl)
jr c,l3585 ; (9)
jr nz,l356b ; (-19)
.l357e dec bc
inc de
inc hl
ex (sp),hl
dec hl
jr l3564 ; (-33)
.l3585 pop bc
pop af
and a
.l3588 push af
rst $28
and b
jr c,l357e ; (-15)
push af
call c,$3501
pop af
push af
call nc,$34f9
pop af
rrca
call nc,$3501
ret
call $2bf1
push de
push bc
call $2bf1
pop hl
push hl
push de
push bc
add hl,bc
ld b,h
ld c,l
rst $30
call $2ab2
pop bc
pop hl
ld a,b
or c
jr z,l35b7 ; (2)
ldir
.l35b7 pop bc
pop hl
ld a,b
or c
jr z,l35bf ; (2)
ldir
.l35bf ld hl,(STKEND)
ld de,$fffb
push hl
add hl,de
pop de
ret
call $2dd5
jr c,l35dc ; (14)
jr nz,l35dc ; (12)
push af
ld bc,$0001
rst $30
pop af
ld (de),a
call $2ab2
ex de,hl
ret
.l35dc rst $8
ld a,(bc)
ld hl,(CH_ADD)
push hl
ld a,b
add a,$e3
sbc a,a
push af
call $2bf1
push de
inc bc
rst $30
pop hl
ld (CH_ADD),de
push de
ldir
ex de,hl
dec hl
ld (hl),$0d
res 7,(iy+$01)
call $24fb
rst $18
cp $0d
jr nz,l360c ; (7)
pop hl
pop af
xor (iy+$01)
and $40
.l360c jp nz,$1c8a
ld (CH_ADD),hl
set 7,(iy+$01)
call $24fb
pop hl
ld (CH_ADD),hl
jr l35bf ; (-96)
ld bc,$0001
rst $30
ld (K_CUR),hl
push hl
ld hl,(CURCHL)
push hl
ld a,$ff
call $1601
call $2de3
pop hl
call $1615
pop de
ld hl,(K_CUR)
and a
sbc hl,de
ld b,h
ld c,l
call $2ab2
ex de,hl
ret
call $1e94
cp $10
jp nc,$1e9f
ld hl,(CURCHL)
push hl
call $1601
call $15e6
ld bc,$0000
jr nc,l365f ; (3)
inc c
rst $30
ld (de),a
.l365f call $2ab2
pop hl
call $1615
jp $35bf
call $2bf1
ld a,b
or c
jr z,l3671 ; (1)
ld a,(de)
.l3671 jp $2d28
.l3674 call $2bf1
jp $2d2b
exx
push hl
ld hl,BREG
dec (hl)
pop hl
jr nz,l3687 ; (4)
inc hl
exx
ret
.l3686 exx
.l3687 ld e,(hl)
ld a,e
rla
sbc a,a
ld d,a
add hl,de
.l368d exx
ret
inc de
inc de
ld a,(de)
dec de
dec de
and a
jr nz,l3686 ; (-17)
exx
inc hl
exx
ret
pop af
exx
ex (sp),hl
exx
ret
rst $28
ret nz
ld (bc),a
ld sp,$05e0
daa
ret po
ld bc,$04c0
inc bc
ret po
defb $38
defb -55
rst $28
ld sp,$0036
inc b
ld a,($c938)
ld sp,$c03a
inc bc
ret po
ld bc,$0030
inc bc
and c
inc bc
jr c,l368d ; (-55)
rst $28
dec a
inc (hl)
.l36c7 pop af
jr c,l3674 ; (-86)
dec sp
add hl,hl
inc b
ld sp,$c327
inc bc
ld sp,$a10f
inc bc
adc a,b
inc de
ld (hl),$58
ld h,l
ld h,(hl)
sbc a,l
.l36dc ld a,b
ld h,l
ld b,b
and d
ld h,b
ld ($e7c9),a
ld hl,$aff7
inc h
ex de,hl
cpl
.l36ea or b
or b
inc d
xor $7e
cp e
sub h
ld e,b
pop af
ld a,($f87e)
rst $8
ex (sp),hl
jr c,l36c7 ; (-51)
push de
dec l
jr nz,l3705 ; (7)
jr c,l3703 ; (3)
add a,(hl)
jr nc,l370c ; (9)
.l3703 rst $8
dec b
.l3705 jr c,l370e ; (7)
sub (hl)
jr nc,l370e ; (4)
neg
.l370c ld (hl),a
ret
.l370e rst $28
ld (bc),a
and b
jr c,l36dc ; (-55)
rst $28
dec a
ld sp,$0037
inc b
jr c,l36ea ; (-49)
add hl,bc
and b
ld (bc),a
jr c,l379e ; (126)
ld (hl),$80
call $2d28
rst $28
inc (hl)
jr c,l3729 ; (0)
.l3729 inc bc
ld bc,$3431
ret p
ld c,h
call z,$cdcc
inc bc
scf
nop
ex af,af'
ld bc,$03a1
ld bc,$3438
rst $28
ld bc,$f034
ld sp,$1772
ret m
inc b
ld bc,$03a2
and d
inc bc
ld sp,$3234
defb $20
defb 4
and d
inc bc
adc a,h
ld de,$14ac
add hl,bc
ld d,(hl)
jp c,$59a5
defb $30
defb -59
ld e,h
sub b
xor d
sbc a,(hl)
ld (hl),b
ld l,a
ld h,c
and c
set 3,d
sub (hl)
and h
ld sp,$b49f
rst $20
and b
cp $5c
call m,$1bea
ld b,e
.l3773 jp z,$ed36
and a
sbc a,h
ld a,(hl)
ld e,(hl)
ret p
ld l,(hl)
inc hl
add a,b
sub e
inc b
rrca
defb $38
defb -55
rst $28
dec a
inc (hl)
xor $22
ld sp,hl
add a,e
ld l,(hl)
inc b
ld sp,$0fa2
daa
inc bc
ld sp,$310f
rrca
ld sp,$a12a
inc bc
ld sp,$c037
nop
inc b
.l379e ld (bc),a
defb $38
defb -55
and c
inc bc
ld bc,$0036
ld (bc),a
dec de
jr c,l3773 ; (-55)
rst $28
.l37ab add hl,sp
ld hl,($03a1)
ret po
nop
ld b,$1b
inc sp
inc bc
rst $28
.l37b6 add hl,sp
.l37b7 ld sp,$0431
ld sp,$a10f
inc bc
add a,(hl)
inc d
and $5c
rra
dec bc
and e
adc a,a
jr c,l37b6 ; (-18)
jp (hl)
dec d
ld h,e
cp e
inc hl
xor $92
dec c
call $f1ed
inc hl
ld e,l
dec de
jp pe,$3804
ret
rst $28
ld sp,$011f
jr nz,l37e5 ; (5)
jr c,l37ab ; (-55)
call $3297
.l37e5 ld a,(hl)
cp $81
jr c,l37f8 ; (14)
rst $28
and c
dec de
ld bc,$3105
ld (hl),$a3
ld bc,$0600
dec de
inc sp
inc bc
.l37f8 rst $28
and b
ld bc,$3131
inc b
ld sp,$a10f
inc bc
.l3802 adc a,h
djnz $37b7 ; (-78)
inc de
ld c,$55
call po,$588d
add hl,sp
cp h
ld e,e
sbc a,b
sbc a,(iy+$00)
ld (hl),$75
and b
in a,($e8)
or h
ld h,e
ld b,d
call nz,$b5e6
add hl,bc
.l381e ld (hl),$be
jp (hl)
ld (hl),$73
dec de
ld e,l
call pe,$ded8
ld h,e
cp (hl)
ret p
ld h,c
and c
or e
inc c
inc b
rrca
defb $38
defb -55
rst $28
ld sp,$0431
.l3837 and c
inc bc
dec de
defb $28
defb -95
rrca
dec b
inc h
ld sp,$380f
ret
rst $28
ld ($03a3),hl
dec de
defb $38
defb -55
rst $28
ld sp,$0030
ld e,$a2
defb $38
defb -17
ld bc,$3031
nop
rlca
dec h
inc b
jr c,l381e ; (-61)
call nz,$0236
ld sp,$0030
add hl,bc
and b
ld bc,$0037
ld b,$a1
ld bc,$0205
and c
jr c,l3837 ; (-55)
; In the original 48K ROM, locations $386e to $3cff are "spare" and
; contain $ff
; This routine is a patch to the maskable interrupt routine.
; It scans the keyboard as normal, and then checks for disk motor timeout
.l386e push ix ; save IX (why?)
call l02bf ; scan keyboard as with 48K ROM
bit 4,(iy+$01)
jr z,l387c ; check bit 4 of FLAGS
call l387f ; check disk motor if true
.l387c pop ix
ret
; Subroutine to check disk motor timeout
.l387f ld bc,$7ffd
ld a,(BANKM)
or $07
out (c),a ; page in page 7
ld a,($e600)
or a
jr z,l38ac ; move on if motor already off
ld a,(FRAMES)
bit 0,a
jr nz,l38ac ; only decrement timeout every other time
ld a,($e600)
dec a ; decrement timeout
ld ($e600),a
jr nz,l38ac ; move on if not yet zero
ld bc,$1ffd
ld a,(BANK678)
and $f7
ld (BANK678),a
out (c),a ; switch motor off
.l38ac ld bc,$7ffd
ld a,(BANKM)
out (c),a ; page back page 0
ret
defs 331
; The printer input (l3a00) and output (l3a05) routines
; Channel information for "P" channel points here
.l3a00 ld hl,$3d03 ; input routine in ROM 1
jr l3a08
.l3a05 ld hl,$3d06 ; output routine in ROM 1
.l3a08 ex af,af'
ld bc,$1ffd
ld a,(BANK678)
push af
and $fb ; select ROM 1
di
ld (BANK678),a
out (c),a ; at this point, routine continues in ROM 1
jp $3d00
.l3a1b ex af,af'
pop af
ld bc,$1ffd
di
ld (BANK678),a
out (c),a
ei ; control returns to this ROM here
ex af,af'
ret
; Patch to print error message routine
.l3a29 bit 4,(iy+$01) ; check bit 4 of FLAGS
jr nz,l3a34 ; move on if in +3 BASIC
xor a
ld de,$1536 ; else exit to do standard "comma" message
ret
.l3a34 ld hl,$010f
.l3a37 ex (sp),hl
jp SWAP ; call routine in ROM 0
; note that all these routines seem to enter
; during the reset routine! Or am I missing
; something...
; Patch to "STMT-RET" routine
.l3a3b bit 4,(iy+$01) ; check bit 4 of FLAGS
jr nz,l3a46 ; move on if in +3 BASIC
bit 7,(iy+$0a) ; else exit with normal 48K ROM check done
ret
.l3a46 ld hl,$0112
jr l3a37 ; go to call routine in ROM 0
; Patch to "STMT-NEXT" routine
.l3a4b bit 4,(iy+$01) ; check bit 4 of FLAGS
jr nz,l3a55 ; move on if in +3 BASIC
rst $18
cp $0d ; else exit with normal 48K ROM check done
ret
.l3a55 ld hl,$0115
jr l3a37 ; go to call routine in ROM 0
; Patch to INKEY$ function routine
; Presumably, in earlier 128K spectrums this was used to read the
; external keypad, but it effectively does nothing different to the
; usual routine on the +3.
.l3a5a call l028e ; do normal call to get key-value in DE
ld c,$00
jr nz,l3a6e ; move on if too many keys pressed
call l031e ; test key value
jr nc,l3a6e ; move on if unsatisfactory
dec d ; D=$ff (L-mode)
ld e,a ; E=key value
call l0333 ; decode
jp l2657 ; jump back into INKEY$ routine with keycode
.l3a6e bit 4,(iy+$01) ; check bit 4 of FLAGS
jp z,l2660 ; jump back into INKEY$ if in 48K BASIC
di
ei
jr l3a79
.l3a79 ld c,$00
jp l2660 ; jump back into INKEY$ routine
; Patch to "print a character" routine
.l3a7e cp $a3
jr z,l3a8e ; move on for "SPECTRUM"
cp $a4
jr z,l3a8e ; move on for "PLAY"
.l3a86 sub $a5
jp nc,l0b5f ; else rejoin print character routine
jp l0b56 ; with normal test done
.l3a8e bit 4,(iy+$01) ; check bit 4 of FLAGS
jr z,l3a86 ; move back if in 48K mode
ld de,l3aa8
push de ; stack address to return to in this routine
sub $a3
ld de,l3ab1 ; address of "SPECTRUM"
jr z,l3aa2 ; move on if SPECTRUM
ld de,l3ab9 ; address of "PLAY"
.l3aa2 ld a,$04
push af ; stack $04 to get a trailing space
jp l0c17 ; output the token & return to next instruction
.l3aa8 scf
bit 1,(iy+$01)
ret nz ; exit if handling the printer
jp l0b03 ; else jump back into print routine
.l3ab1 defm "SPECTRU"&('M'+$80)
.l3ab9 defm "PLA"&('Y'+$80)
jp $3c01 ; what's this for???
defs 319
rst $38
rst $38
.l3c01 defm $13&$00&"19"&$13&$01&"87" ; testcard message
; why is it here???
defs 247
; -------------------------------
; THE 'ZX SPECTRUM CHARACTER SET'
; -------------------------------
.l3d00
; $20 - Character: ' ' CHR$(32)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
; $21 - Character: '!' CHR$(33)
defb $00 ; 00000000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
defb $10 ; 00010000
defb $00 ; 00000000
; $22 - Character: '"' CHR$(34)
defb $00 ; 00000000
defb $24 ; 00100100
defb $24 ; 00100100
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
; $23 - Character: '#' CHR$(35)
defb $00 ; 00000000
defb $24 ; 00100100
defb $7E ; 10000010
defb $24 ; 00100100
defb $24 ; 00100100
defb $7E ; 10000010
defb $24 ; 00100100
defb $00 ; 00000000
; $24 - Character: '$' CHR$(36)
defb $00 ; 00000000
defb $08 ; 00001000
defb $3E ; 01000010
defb $28 ; 00101000
defb $3E ; 01000010
defb $0A ; 00001010
defb $3E ; 01000010
defb $08 ; 00001000
; $25 - Character: '%' CHR$(37)
defb $00 ; 00000000
defb $62 ; 10100010
defb $64 ; 10100100
defb $08 ; 00001000
defb $10 ; 00010000
defb $26 ; 00101010
defb $46 ; 01001010
defb $00 ; 00000000
; $26 - Character: '&' CHR$(38)
defb $00 ; 00000000
defb $10 ; 00010000
defb $28 ; 00101000
defb $10 ; 00010000
defb $2A ; 00101010
defb $44 ; 01000100
defb $3A ; 01001010
defb $00 ; 00000000
; $27 - Character: ''' CHR$(39)
defb $00 ; 00000000
defb $08 ; 00001000
defb $10 ; 00010000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
; $28 - Character: '(' CHR$(40)
defb $00 ; 00000000
defb $04 ; 00000100
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $04 ; 00000100
defb $00 ; 00000000
; $29 - Character: ')' CHR$(41)
defb $00 ; 00000000
defb $20 ; 00100000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $20 ; 00100000
defb $00 ; 00000000
; $2A - Character: '*' CHR$(42)
defb $00 ; 00000000
defb $00 ; 00000000
defb $14 ; 00010100
defb $08 ; 00001000
defb $3E ; 01000010
defb $08 ; 00001000
defb $14 ; 00010100
defb $00 ; 00000000
; $2B - Character: '+' CHR$(43)
defb $00 ; 00000000
defb $00 ; 00000000
defb $08 ; 00001000
defb $08 ; 00001000
defb $3E ; 01000010
defb $08 ; 00001000
defb $08 ; 00001000
defb $00 ; 00000000
; $2C - Character: ',' CHR$(44)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $08 ; 00001000
defb $08 ; 00001000
defb $10 ; 00010000
; $2D - Character: '-' CHR$(45)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $3E ; 01000010
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
; $2E - Character: '.' CHR$(46)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $18 ; 00101000
defb $18 ; 00101000
defb $00 ; 00000000
; $2F - Character: '/' CHR$(47)
defb $00 ; 00000000
defb $00 ; 00000000
defb $02 ; 00000010
defb $04 ; 00000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $20 ; 00100000
defb $00 ; 00000000
; $30 - Character: '0' CHR$(48)
defb $00 ; 00000000
defb $3C ; 01000100
defb $46 ; 01001010
defb $4A ; 01001010
defb $52 ; 01010010
defb $62 ; 10100010
defb $3C ; 01000100
defb $00 ; 00000000
; $31 - Character: '1' CHR$(49)
defb $00 ; 00000000
defb $18 ; 00101000
defb $28 ; 00101000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $3E ; 01000010
defb $00 ; 00000000
; $32 - Character: '2' CHR$(50)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $02 ; 00000010
defb $3C ; 01000100
defb $40 ; 01000000
defb $7E ; 10000010
defb $00 ; 00000000
; $33 - Character: '3' CHR$(51)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $0C ; 00010100
defb $02 ; 00000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $34 - Character: '4' CHR$(52)
defb $00 ; 00000000
defb $08 ; 00001000
defb $18 ; 00101000
defb $28 ; 00101000
defb $48 ; 01001000
defb $7E ; 10000010
defb $08 ; 00001000
defb $00 ; 00000000
; $35 - Character: '5' CHR$(53)
defb $00 ; 00000000
defb $7E ; 10000010
defb $40 ; 01000000
defb $7C ; 10000100
defb $02 ; 00000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $36 - Character: '6' CHR$(54)
defb $00 ; 00000000
defb $3C ; 01000100
defb $40 ; 01000000
defb $7C ; 10000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $37 - Character: '7' CHR$(55)
defb $00 ; 00000000
defb $7E ; 10000010
defb $02 ; 00000010
defb $04 ; 00000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
; $38 - Character: '8' CHR$(56)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $3C ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $39 - Character: '9' CHR$(57)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $3E ; 01000010
defb $02 ; 00000010
defb $3C ; 01000100
defb $00 ; 00000000
; $3A - Character: ':' CHR$(58)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $10 ; 00010000
defb $00 ; 00000000
defb $00 ; 00000000
defb $10 ; 00010000
defb $00 ; 00000000
; $3B - Character: ';' CHR$(59)
defb $00 ; 00000000
defb $00 ; 00000000
defb $10 ; 00010000
defb $00 ; 00000000
defb $00 ; 00000000
defb $10 ; 00010000
defb $10 ; 00010000
defb $20 ; 00100000
; $3C - Character: '<' CHR$(60)
defb $00 ; 00000000
defb $00 ; 00000000
defb $04 ; 00000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $08 ; 00001000
defb $04 ; 00000100
defb $00 ; 00000000
; $3D - Character: '=' CHR$(61)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $3E ; 01000010
defb $00 ; 00000000
defb $3E ; 01000010
defb $00 ; 00000000
defb $00 ; 00000000
; $3E - Character: '>' CHR$(62)
defb $00 ; 00000000
defb $00 ; 00000000
defb $10 ; 00010000
defb $08 ; 00001000
defb $04 ; 00000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $00 ; 00000000
; $3F - Character: '?' CHR$(63)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $04 ; 00000100
defb $08 ; 00001000
defb $00 ; 00000000
defb $08 ; 00001000
defb $00 ; 00000000
; $40 - Character: '@' CHR$(64)
defb $00 ; 00000000
defb $3C ; 01000100
defb $4A ; 01001010
defb $56 ; 10101010
defb $5E ; 10100010
defb $40 ; 01000000
defb $3C ; 01000100
defb $00 ; 00000000
; $41 - Character: 'A' CHR$(65)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $7E ; 10000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $00 ; 00000000
; $42 - Character: 'B' CHR$(66)
defb $00 ; 00000000
defb $7C ; 10000100
defb $42 ; 01000010
defb $7C ; 10000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $7C ; 10000100
defb $00 ; 00000000
; $43 - Character: 'C' CHR$(67)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $40 ; 01000000
defb $40 ; 01000000
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $44 - Character: 'D' CHR$(68)
defb $00 ; 00000000
defb $78 ; 10001000
defb $44 ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $44 ; 01000100
defb $78 ; 10001000
defb $00 ; 00000000
; $45 - Character: 'E' CHR$(69)
defb $00 ; 00000000
defb $7E ; 10000010
defb $40 ; 01000000
defb $7C ; 10000100
defb $40 ; 01000000
defb $40 ; 01000000
defb $7E ; 10000010
defb $00 ; 00000000
; $46 - Character: 'F' CHR$(70)
defb $00 ; 00000000
defb $7E ; 10000010
defb $40 ; 01000000
defb $7C ; 10000100
defb $40 ; 01000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $00 ; 00000000
; $47 - Character: 'G' CHR$(71)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $40 ; 01000000
defb $4E ; 01010010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $48 - Character: 'H' CHR$(72)
defb $00 ; 00000000
defb $42 ; 01000010
defb $42 ; 01000010
defb $7E ; 10000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $00 ; 00000000
; $49 - Character: 'I' CHR$(73)
defb $00 ; 00000000
defb $3E ; 01000010
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $3E ; 01000010
defb $00 ; 00000000
; $4A - Character: 'J' CHR$(74)
defb $00 ; 00000000
defb $02 ; 00000010
defb $02 ; 00000010
defb $02 ; 00000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $4B - Character: 'K' CHR$(75)
defb $00 ; 00000000
defb $44 ; 01000100
defb $48 ; 01001000
defb $70 ; 10010000
defb $48 ; 01001000
defb $44 ; 01000100
defb $42 ; 01000010
defb $00 ; 00000000
; $4C - Character: 'L' CHR$(76)
defb $00 ; 00000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $7E ; 10000010
defb $00 ; 00000000
; $4D - Character: 'M' CHR$(77)
defb $00 ; 00000000
defb $42 ; 01000010
defb $66 ; 10101010
defb $5A ; 10101010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $00 ; 00000000
; $4E - Character: 'N' CHR$(78)
defb $00 ; 00000000
defb $42 ; 01000010
defb $62 ; 10100010
defb $52 ; 01010010
defb $4A ; 01001010
defb $46 ; 01001010
defb $42 ; 01000010
defb $00 ; 00000000
; $4F - Character: 'O' CHR$(79)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $50 - Character: 'P' CHR$(80)
defb $00 ; 00000000
defb $7C ; 10000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $7C ; 10000100
defb $40 ; 01000000
defb $40 ; 01000000
defb $00 ; 00000000
; $51 - Character: 'Q' CHR$(81)
defb $00 ; 00000000
defb $3C ; 01000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $52 ; 01010010
defb $4A ; 01001010
defb $3C ; 01000100
defb $00 ; 00000000
; $52 - Character: 'R' CHR$(82)
defb $00 ; 00000000
defb $7C ; 10000100
defb $42 ; 01000010
defb $42 ; 01000010
defb $7C ; 10000100
defb $44 ; 01000100
defb $42 ; 01000010
defb $00 ; 00000000
; $53 - Character: 'S' CHR$(83)
defb $00 ; 00000000
defb $3C ; 01000100
defb $40 ; 01000000
defb $3C ; 01000100
defb $02 ; 00000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $54 - Character: 'T' CHR$(84)
defb $00 ; 00000000
defb $FE ; 00000010
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
; $55 - Character: 'U' CHR$(85)
defb $00 ; 00000000
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $3C ; 01000100
defb $00 ; 00000000
; $56 - Character: 'V' CHR$(86)
defb $00 ; 00000000
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $24 ; 00100100
defb $18 ; 00101000
defb $00 ; 00000000
; $57 - Character: 'W' CHR$(87)
defb $00 ; 00000000
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $42 ; 01000010
defb $5A ; 10101010
defb $24 ; 00100100
defb $00 ; 00000000
; $58 - Character: 'X' CHR$(88)
defb $00 ; 00000000
defb $42 ; 01000010
defb $24 ; 00100100
defb $18 ; 00101000
defb $18 ; 00101000
defb $24 ; 00100100
defb $42 ; 01000010
defb $00 ; 00000000
; $59 - Character: 'Y' CHR$(89)
defb $00 ; 00000000
defb $82 ; 10000010
defb $44 ; 01000100
defb $28 ; 00101000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
; $5A - Character: 'Z' CHR$(90)
defb $00 ; 00000000
defb $7E ; 10000010
defb $04 ; 00000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $20 ; 00100000
defb $7E ; 10000010
defb $00 ; 00000000
; $5B - Character: '[' CHR$(91)
defb $00 ; 00000000
defb $0E ; 00010010
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $0E ; 00010010
defb $00 ; 00000000
; $5C - Character: '\' CHR$(92)
defb $00 ; 00000000
defb $00 ; 00000000
defb $40 ; 01000000
defb $20 ; 00100000
defb $10 ; 00010000
defb $08 ; 00001000
defb $04 ; 00000100
defb $00 ; 00000000
; $5D - Character: ']' CHR$(93)
defb $00 ; 00000000
defb $70 ; 10010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $70 ; 10010000
defb $00 ; 00000000
; $5E - Character: '^' CHR$(94)
defb $00 ; 00000000
defb $10 ; 00010000
defb $38 ; 01001000
defb $54 ; 01010100
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
; $5F - Character: '_' CHR$(95)
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $FF ; 00000001
; $60 - Character: '`' CHR$(96)
defb $00 ; 00000000
defb $1C ; 00100100
defb $22 ; 00100010
defb $78 ; 10001000
defb $20 ; 00100000
defb $20 ; 00100000
defb $7E ; 10000010
defb $00 ; 00000000
; $61 - Character: 'a' CHR$(97)
defb $00 ; 00000000
defb $00 ; 00000000
defb $38 ; 01001000
defb $04 ; 00000100
defb $3C ; 01000100
defb $44 ; 01000100
defb $3C ; 01000100
defb $00 ; 00000000
; $62 - Character: 'b' CHR$(98)
defb $00 ; 00000000
defb $20 ; 00100000
defb $20 ; 00100000
defb $3C ; 01000100
defb $22 ; 00100010
defb $22 ; 00100010
defb $3C ; 01000100
defb $00 ; 00000000
; $63 - Character: 'c' CHR$(99)
defb $00 ; 00000000
defb $00 ; 00000000
defb $1C ; 00100100
defb $20 ; 00100000
defb $20 ; 00100000
defb $20 ; 00100000
defb $1C ; 00100100
defb $00 ; 00000000
; $64 - Character: 'd' CHR$(100)
defb $00 ; 00000000
defb $04 ; 00000100
defb $04 ; 00000100
defb $3C ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $3C ; 01000100
defb $00 ; 00000000
; $65 - Character: 'e' CHR$(101)
defb $00 ; 00000000
defb $00 ; 00000000
defb $38 ; 01001000
defb $44 ; 01000100
defb $78 ; 10001000
defb $40 ; 01000000
defb $3C ; 01000100
defb $00 ; 00000000
; $66 - Character: 'f' CHR$(102)
defb $00 ; 00000000
defb $0C ; 00010100
defb $10 ; 00010000
defb $18 ; 00101000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $00 ; 00000000
; $67 - Character: 'g' CHR$(103)
defb $00 ; 00000000
defb $00 ; 00000000
defb $3C ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $3C ; 01000100
defb $04 ; 00000100
defb $38 ; 01001000
; $68 - Character: 'h' CHR$(104)
defb $00 ; 00000000
defb $40 ; 01000000
defb $40 ; 01000000
defb $78 ; 10001000
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $00 ; 00000000
; $69 - Character: 'i' CHR$(105)
defb $00 ; 00000000
defb $10 ; 00010000
defb $00 ; 00000000
defb $30 ; 01010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $38 ; 01001000
defb $00 ; 00000000
; $6A - Character: 'j' CHR$(106)
defb $00 ; 00000000
defb $04 ; 00000100
defb $00 ; 00000000
defb $04 ; 00000100
defb $04 ; 00000100
defb $04 ; 00000100
defb $24 ; 00100100
defb $18 ; 00101000
; $6B - Character: 'k' CHR$(107)
defb $00 ; 00000000
defb $20 ; 00100000
defb $28 ; 00101000
defb $30 ; 01010000
defb $30 ; 01010000
defb $28 ; 00101000
defb $24 ; 00100100
defb $00 ; 00000000
; $6C - Character: 'l' CHR$(108)
defb $00 ; 00000000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $0C ; 00010100
defb $00 ; 00000000
; $6D - Character: 'm' CHR$(109)
defb $00 ; 00000000
defb $00 ; 00000000
defb $68 ; 10101000
defb $54 ; 01010100
defb $54 ; 01010100
defb $54 ; 01010100
defb $54 ; 01010100
defb $00 ; 00000000
; $6E - Character: 'n' CHR$(110)
defb $00 ; 00000000
defb $00 ; 00000000
defb $78 ; 10001000
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $00 ; 00000000
; $6F - Character: 'o' CHR$(111)
defb $00 ; 00000000
defb $00 ; 00000000
defb $38 ; 01001000
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $38 ; 01001000
defb $00 ; 00000000
; $70 - Character: 'p' CHR$(112)
defb $00 ; 00000000
defb $00 ; 00000000
defb $78 ; 10001000
defb $44 ; 01000100
defb $44 ; 01000100
defb $78 ; 10001000
defb $40 ; 01000000
defb $40 ; 01000000
; $71 - Character: 'q' CHR$(113)
defb $00 ; 00000000
defb $00 ; 00000000
defb $3C ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $3C ; 01000100
defb $04 ; 00000100
defb $06 ; 00001010
; $72 - Character: 'r' CHR$(114)
defb $00 ; 00000000
defb $00 ; 00000000
defb $1C ; 00100100
defb $20 ; 00100000
defb $20 ; 00100000
defb $20 ; 00100000
defb $20 ; 00100000
defb $00 ; 00000000
; $73 - Character: 's' CHR$(115)
defb $00 ; 00000000
defb $00 ; 00000000
defb $38 ; 01001000
defb $40 ; 01000000
defb $38 ; 01001000
defb $04 ; 00000100
defb $78 ; 10001000
defb $00 ; 00000000
; $74 - Character: 't' CHR$(116)
defb $00 ; 00000000
defb $10 ; 00010000
defb $38 ; 01001000
defb $10 ; 00010000
defb $10 ; 00010000
defb $10 ; 00010000
defb $0C ; 00010100
defb $00 ; 00000000
; $75 - Character: 'u' CHR$(117)
defb $00 ; 00000000
defb $00 ; 00000000
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $38 ; 01001000
defb $00 ; 00000000
; $76 - Character: 'v' CHR$(118)
defb $00 ; 00000000
defb $00 ; 00000000
defb $44 ; 01000100
defb $44 ; 01000100
defb $28 ; 00101000
defb $28 ; 00101000
defb $10 ; 00010000
defb $00 ; 00000000
; $77 - Character: 'w' CHR$(119)
defb $00 ; 00000000
defb $00 ; 00000000
defb $44 ; 01000100
defb $54 ; 01010100
defb $54 ; 01010100
defb $54 ; 01010100
defb $28 ; 00101000
defb $00 ; 00000000
; $78 - Character: 'x' CHR$(120)
defb $00 ; 00000000
defb $00 ; 00000000
defb $44 ; 01000100
defb $28 ; 00101000
defb $10 ; 00010000
defb $28 ; 00101000
defb $44 ; 01000100
defb $00 ; 00000000
; $79 - Character: 'y' CHR$(121)
defb $00 ; 00000000
defb $00 ; 00000000
defb $44 ; 01000100
defb $44 ; 01000100
defb $44 ; 01000100
defb $3C ; 01000100
defb $04 ; 00000100
defb $38 ; 01001000
; $7A - Character: 'z' CHR$(122)
defb $00 ; 00000000
defb $00 ; 00000000
defb $7C ; 10000100
defb $08 ; 00001000
defb $10 ; 00010000
defb $20 ; 00100000
defb $7C ; 10000100
defb $00 ; 00000000
; $7B - Character: '{' CHR$(123)
defb $00 ; 00000000
defb $0E ; 00010010
defb $08 ; 00001000
defb $30 ; 01010000
defb $08 ; 00001000
defb $08 ; 00001000
defb $0E ; 00010010
defb $00 ; 00000000
; $7C - Character: '|' CHR$(124)
defb $00 ; 00000000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $08 ; 00001000
defb $00 ; 00000000
; $7D - Character: '}' CHR$(125)
defb $00 ; 00000000
defb $70 ; 10010000
defb $10 ; 00010000
defb $0C ; 00010100
defb $10 ; 00010000
defb $10 ; 00010000
defb $70 ; 10010000
defb $00 ; 00000000
; $7E - Character: '~' CHR$(126)
defb $00 ; 00000000
defb $14 ; 00010100
defb $28 ; 00101000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
defb $00 ; 00000000
; $7F - Character: '(c)' CHR$(127)
defb $3C ; 01000100
defb $42 ; 01000010
defb $99 ; 10101001
defb $A1 ; 10100001
defb $A1 ; 10100001
defb $99 ; 10101001
defb $42 ; 01000010
defb $3C ; 01000100
; ----------------------------------------------------------------------------------------------------
; =========================
; 48K BASIC ROM differences
; =========================
;
; The 48K BASIC ROM in the +3 differs from the original 48K ROM in the
; following respects:
;
; $0013 Filler byte changed from $ff to $a7 (reason unknown)
; $004b Maskable interrupt routine now calls new code at $386e
; $006d NMI routine bug fixed
; $09a2 Tape message changed to "Press REC & PLAY, then any key."
; $0b52 Token-checking code replaced with jump to new code at $3a7e
; $1349 Error-message code replaced with jump to new code at $3a29
; $1540 Copyright message changed to "(c) 1982 Amstrad"
; $1b7d STMT-R-1 code replaced with call to new code at $3a3b
; $1bf4 STMT-NEXT code replaced with call to new code at $3a4b
; $2646 Call to KEY-SCAN replaced with jump to new code at $3a5a
; $386e Patch to maskable interrupt routine, with disk motor timeout check
; $3a00 Printer i/o channel routines
;
; ; The following routines all seem to enter routines in ROM 0 within
; ; the reset code; presumably these are left over from 128K and can
; ; be removed?
;
; $3a29 Patch to error message routine
; $3a3b Patch to STMT-RET routine
; $3a4b Patch to STMT-NEXT routine
; $3a5a Patch to INKEY$ function (definitely redundant on +3)
; $3a7e Patch to print character routine, providing SPECTRUM & PLAY
; $3c01 Testcard message "1987"
;
; Remaining bytes between $386e and $3cff are set to zero; in the original
; 48K ROM, they were all set to $ff.
|
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <pwd.h>
#include <sys/types.h>
#include <unistd.h>
#include <vector>
#include <stdio.h>
#include <stdlib.h>
#include <errno.h>
#include <iostream>
#include <string>
#include "lib/sql_util.h"
#include "gtest/gtest.h"
class TestAlterTable : public ::testing::Test {
public:
TestAlterTable() {}
~TestAlterTable() {}
};
TEST_F(TestAlterTable, TestAlterTableAOColumnDefaultValue) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int, b text, c int)");
util.execute("insert into altable "
"select i, i::text, i from generate_series(1,10) i");
// test add new column into an ao table without default value setting
util.execute("alter table altable add column y int", false);
std::string errstr = "ERROR: ADD COLUMN with no default value in "
"append-only tables is not yet supported.";
EXPECT_STREQ(errstr.c_str(),
util.getPSQL()->getLastResult().substr(0, errstr.size()).c_str());
// test add new column into an ao table having default value setting
util.execute("alter table altable add column x int default 1");
util.query("select a,b,c,x from altable where a=1",
"1|1|1|1|\n");
// test alter column having default value setting
util.execute("alter table altable alter column c set default 10 - 1");
util.execute("insert into altable(a,b) values(11,'11')");
util.query("select a,b,c from altable where a=11",
"11|11|9|\n");
// test alter column dropping default value setting
util.execute("alter table altable alter column c drop default");
util.execute("insert into altable(a,b) values(12,'12')");
util.query("select a,b,c from altable where a=12",
"12|12||\n");
// cleanup
util.execute("drop table altable");
}
TEST_F(TestAlterTable, TestAlterTableAOColumnNOTNULL) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int, b text, c int)");
util.execute("insert into altable "
"select i, i::text, i from generate_series(1,10) i");
// test set not null
util.execute("alter table altable alter column c set not null");
util.execute("insert into altable(a,b) values(13,'13')", false);
std::string errstr = "ERROR: null value in column \"c\" violates "
"not-null constraint";
EXPECT_STREQ(errstr.c_str(),
util.getPSQL()->getLastResult().substr(0, errstr.size()).c_str());
// test drop not null
util.execute("alter table altable alter column c drop not null");
util.execute("insert into altable(a,b) values(13,'13')");
util.query("select a,b,c from altable where a=13",
"13|13||\n");
// cleanup
util.execute("drop table altable");
}
TEST_F(TestAlterTable, TestAlterTableAOColumnConstraint) {
hawq::test::SQLUtility util;
bool orcaon = false;
if (util.getGUCValue("optimizer") == "on") {
std::cout << "NOTE: TestAlterTable.TestAlterTableAOColumnConstraint "
"uses answer for optimizer on" << std::endl;
orcaon = true;
}
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int, b text, c int)");
util.execute("insert into altable "
"select i, i::text, i from generate_series(1,10) i");
// test , constaint is broken by existing rows
util.execute("alter table altable "
"add constraint c_check check (c<10)", false);
std::string errstr = "ERROR: check constraint \"c_check\" "
"is violated by some row";
EXPECT_STREQ(errstr.c_str(),
util.getPSQL()->getLastResult().substr(0, errstr.size()).c_str());
// test, new row breaks existing contraint
util.execute("alter table altable add constraint c_check check (c>0)");
util.execute("insert into altable(a,b,c) values(11,'11',-11)", false);
if (orcaon) {
errstr = "ERROR: One or more assertions failed";
}
else {
errstr = "ERROR: new row for relation \"altable\" "
"violates check constraint \"c_check\"";
}
EXPECT_STREQ(errstr.c_str(),
util.getPSQL()->getLastResult().substr(0, errstr.size()).c_str());
if (orcaon) {
std::string errdetail = "DETAIL: Check constraint c_check for table "
"altable was violated";
std::string::size_type find = util.getPSQL()->getLastResult().find(errdetail);
EXPECT_NE(find, std::string::npos);
}
// test, drop constraint
util.execute("alter table altable drop constraint c_check");
util.execute("insert into altable(a,b,c) values(11,'11',-11)");
util.query("select a,b,c from altable where a=11",
"11|11|-11|\n");
// cleanup
util.execute("drop table altable");
}
TEST_F(TestAlterTable, TestAlterTableAOColumnMisc) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int, b text, c int)");
util.execute("insert into altable "
"select i, i::text, i from generate_series(1,10) i");
util.execute("alter table altable alter column c set statistics 100");
util.execute("alter table altable alter column b set storage plain");
util.execute("insert into altable(a,b,c) values(11,'11',11)");
util.query("select a,b,c from altable where a=11",
"11|11|11|\n");
// drop column
util.execute("alter table altable drop column b");
util.query("select a,c from altable where a=1", "1|1|\n");
// change column type from int to bigint
util.execute("alter table altable alter column c type bigint");
// miscs ( should add more to verify the changes after successfully changed
// the target table
util.execute("alter table altable set without oids");
util.execute("alter table altable set (fillfactor=90)", false);
std::string errstr = "ERROR: altering reloptions for append only tables "
"is not permitted";
EXPECT_STREQ(errstr.c_str(),
util.getPSQL()->getLastResult().substr(0, errstr.size()).c_str());
// cleanup
util.execute("drop table altable");
}
TEST_F(TestAlterTable, TestAlterTableAODropColumn) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int, b text, c int)");
util.execute("insert into altable "
"select i, i::text, i from generate_series(1,10) i");
// test set not null
util.execute("alter table altable drop column b");
util.query("select a,c from altable where a=10","10|10|\n");
// cleanup
util.execute("drop table altable");
}
TEST_F(TestAlterTable, TestAlterTableOwner) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("drop user if exists altuser");
// test
util.execute("create user altuser");
util.execute("create table altable (a,b) as values(1,10),(2,20)");
util.execute("alter table altable owner to altuser");
util.execute("set role altuser");
util.execute("insert into altable(a,b) values(3,30)");
util.execute("reset role");
// cleanup
util.execute("drop table altable");
util.execute("drop user altuser");
}
TEST_F(TestAlterTable, TestAlterTableAddColumn) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists tmp");
// test
util.execute("create table tmp (initial int4)");
util.execute("ALTER TABLE tmp ADD COLUMN a int4 default 3");
util.execute("ALTER TABLE tmp ADD COLUMN b name default 'Alan Turing'");
util.execute("ALTER TABLE tmp ADD COLUMN c text default 'Pivotal'");
util.execute("ALTER TABLE tmp ADD COLUMN d float8 default 0");
util.execute("ALTER TABLE tmp ADD COLUMN e float4 default 0");
util.execute("ALTER TABLE tmp ADD COLUMN f int2 default 0");
util.execute("ALTER TABLE tmp ADD COLUMN g polygon default "
"'(1,1),(1,2),(2,2)'::polygon");
util.execute("ALTER TABLE tmp ADD COLUMN h abstime default null");
util.execute("ALTER TABLE tmp ADD COLUMN i char default 'P'");
util.execute("set datestyle=ISO,DMY;"
"ALTER TABLE tmp ADD COLUMN j abstime[] "
"default ARRAY['2/2/2013 4:05:06'::abstime, "
"'2/2/2013 5:05:06'::abstime]");
util.execute("ALTER TABLE tmp ADD COLUMN k int4 default 0");
util.execute("ALTER TABLE tmp ADD COLUMN l tid default '(0,1)'::tid");
util.execute("ALTER TABLE tmp ADD COLUMN m xid default '0'::xid");
util.execute("ALTER TABLE tmp ADD COLUMN n oidvector "
"default '0 0 0 0'::oidvector");
util.execute("ALTER TABLE tmp ADD COLUMN p smgr "
"default 'magnetic disk'::smgr");
util.execute("ALTER TABLE tmp ADD COLUMN q point default '(0,0)'::point");
util.execute("ALTER TABLE tmp ADD COLUMN r lseg default '(0,0),(1,1)'::lseg");
util.execute("ALTER TABLE tmp ADD COLUMN s path default '(1,1),(1,2),(2,2)'::path");
util.execute("ALTER TABLE tmp ADD COLUMN t box default box(circle '((0,0), 2.0)')");
util.execute("set datestyle=ISO,DMY;"
"ALTER TABLE tmp ADD COLUMN u tinterval "
"default tinterval('2/2/2013 4:05:06', '2/2/2013 5:05:06')");
util.execute("set datestyle=ISO,DMY;"
"ALTER TABLE tmp ADD COLUMN v timestamp "
"default '2/2/2013 4:05:06'::timestamp");
util.execute("ALTER TABLE tmp ADD COLUMN w interval default '3 4:05:06'::interval");
util.execute("ALTER TABLE tmp ADD COLUMN x float8[] default ARRAY[0, 0, 0]");
util.execute("ALTER TABLE tmp ADD COLUMN y float4[] default ARRAY[0, 0, 0]");
util.execute("ALTER TABLE tmp ADD COLUMN z int2[] default ARRAY[0, 0, 0]");
util.execSQLFile("catalog/sql/alter-table-addcol-insert-alltypes.sql",
"catalog/ans/alter-table-addcol-insert-alltypes.ans");
// cleanup
util.execute("drop table tmp");
}
TEST_F(TestAlterTable, TestAlterTableDistributed) {
hawq::test::SQLUtility util;
// prepare
util.execute("drop table if exists altable");
util.execute("create table altable (a int)");
util.execute("insert into altable select generate_series(1,1000);");
// set bucket_number and do distributed
util.execute("set default_hash_table_bucket_number=8;");
util.execute("alter table altable set with(reorganize=true) distributed by (a);");
// check access ok
util.execSQLFile("catalog/sql/alter-table-distributed.sql",
"catalog/ans/alter-table-distributed.ans");
// set another bucket_number and check again
util.execute("set default_hash_table_bucket_number=11;");
util.execute("alter table altable set with(reorganize=true) distributed by (a);");
// check access ok
util.execSQLFile("catalog/sql/alter-table-distributed.sql",
"catalog/ans/alter-table-distributed.ans");
// cleanup
util.execute("drop table altable");
}
|
; A185858: 1/128 the number of (n+2) X 3 binary arrays with no 3 X 3 subblock trace equal to any horizontal or vertical neighbor 3 X 3 subblock trace.
; Submitted by Jon Maiga
; 4,22,124,694,3892,21814,122284,685462,3842404,21538774,120736732,676795894,3793814164,21266419702,119210006284,668237802454,3745841266372,20997505287574,117702592547644,659787917778742,3698475004043764,20731991276183734,116214240141128812,651444882050168854,3651707689470834724,20469834696334858582,114744707990576946844,643207344229321514614,3605531748832478580052,20210993093393807951734,113293758113067539027404,635073970292814427675222,3559939704188865561947524,19955424549390792096867094
mov $2,11
lpb $0
sub $0,1
add $4,4
add $2,$4
mov $3,$4
mul $3,3
mov $4,$2
add $2,$3
mul $2,3
lpe
mov $0,$4
div $0,5
mul $0,6
add $0,4
|
.data
inputfile: .asciiz "./test.dat"
.text
j main
knapsack_dp_loop:
# save $ra and $sn
subi $sp, $sp, 16
sw $ra, 0($sp)
sw $s0, 4($sp)
sw $s1, 8($sp)
sw $s2, 12($sp)
# cache_ptr: $s0
# weight: $s1
# val: $s2
# allocate space for cache_ptr
subi $sp, $sp, 256
move $s0, $sp
# set cache_ptr to 0
# for (i = 0; i < 64; ++i)
# cache_ptr[i] = 0
# i: $t0
li $t0, 0
set_cache_ptr_zero_for:
# compare of for-loop
slti $t1, $t0, 64
beq $t1, $0, end_set_cache_ptr_zero_for
# loop: set to zero
sll $t1, $t0, 2
add $t1, $t1, $s0
sw $0, 0($t1)
addi $t0, $t0, 1
j set_cache_ptr_zero_for
end_set_cache_ptr_zero_for:
# i: $t0
# j: $t1
li $t0, 0
for_i:
# for_i: judge
slt $t2, $t0, $a0
beq $t2, $0, end_for_i
# for_i: loop
sll $t2, $t0, 3 # i * 8
add $t2, $t2, $a1
lw $s1, 0($t2) # get $s1: weight
lw $s2, 4($t2) # get $s2: val
# store the address of cache_ptr[j] in $t3
# and cache[j - weight] in $t4
sll $t3, $a2, 2 # knap_cap * 4
add $t3, $t3, $s0
sub $t4, $a2, $s1 # knap_cap - weight
sll $t4, $t4, 2
add $t4, $t4, $s0
# j = knapsack_capacity
move $t1, $a2
for_j:
# for_j: judge
slt $t2, $t1, $0
bne $t2, $0, end_for_j
# loop_j
# if (j >= weight)
slt $t2, $t1, $s1
bne $t2, $0, end_if_j_geq_weight
lw $t5, 0($t3) # cache_ptr[j]
lw $t6, 0($t4) # cache_ptr[j - weight]
add $t6, $t6, $s2 # cache_ptr[j - weight] + val
slt $t7, $t6, $t5
beq $t7, $0, put_tsix_to_j
j end_put_tsix_to_j
put_tsix_to_j:
sw $t6, 0($t3)
end_put_tsix_to_j:
end_if_j_geq_weight:
# for_j: --j
addi $t3, $t3, -4
addi $t4, $t4, -4
addi $t1, $t1, -1
j for_j
end_for_j:
# for_i: ++i
addi $t0, $t0, 1
j for_i
end_for_i:
# return value
sll $v0, $a2, 2
add $v0, $v0, $s0
lw $v0, 0($v0)
# destruct cache_ptr
addi $sp, $sp, 256
# restore $ra and $sn
lw $ra, 0($sp)
lw $s0, 4($sp)
lw $s1, 8($sp)
lw $s2, 12($sp)
addi $sp, $sp, 16
jr $ra
# ====================================================
main:
# infile: $s0
# in_buffer: $s1
# item_num: $s2
# alloc for in_buffer on stack
addi $sp, $sp, -2048
move $s1, $sp
#open file
la $a0, inputfile
li $a1, 0
li $a2, 0
li $v0, 13
syscall
move $s0, $v0
# read from file
move $a0, $s0
move $a1, $s1
li $a2, 2048
li $v0, 14
syscall
# close file
move $a0, $s0
li $v0, 16
syscall
# call knapsack_dp_loop
lw, $a2, 0($s1)
addi, $a1, $s1, 8
lw, $a0, 4($s1)
jal knapsack_dp_loop
move $s0, $v0
# print result
move $a0, $s0
li $v0, 1
syscall
# store the value into $v0
move $v0, $s0
# restore stack
addi $sp, $sp, 2048
|
; A049380: Expansion of (1-25*x)^(-2/5).
; Submitted by Jamie Morken(s3)
; 1,10,175,3500,74375,1636250,36815625,841500000,19459687500,454059375000,10670395312500,252209343750000,5989971914062500,142837791796875000,3417904303710937500,82029703289062500000,1973839735393066406250,47604370088891601562500,1150438943814880371093750,27852732323939208984375000,675428758855525817871093750,16403269857919912719726562500,398897698817597877502441406250,9712291797298035278320312500000,236737112559139609909057617187500,5776385546443006481781005859375000
mov $2,1
mov $3,$0
mul $3,5
add $3,1
mov $4,1
lpb $3
sub $3,4
mul $2,$3
mul $2,5
div $2,$4
sub $3,1
add $4,1
lpe
mov $0,$2
|
namespace factor {
namespace atomic {
FACTOR_FORCE_INLINE static bool load(volatile bool* ptr) {
atomic::fence();
return *ptr;
}
FACTOR_FORCE_INLINE static cell load(volatile cell* ptr) {
atomic::fence();
return *ptr;
}
FACTOR_FORCE_INLINE static fixnum load(volatile fixnum* ptr) {
atomic::fence();
return *ptr;
}
FACTOR_FORCE_INLINE static void store(volatile bool* ptr, bool val) {
*ptr = val;
atomic::fence();
}
FACTOR_FORCE_INLINE static void store(volatile cell* ptr, cell val) {
*ptr = val;
atomic::fence();
}
FACTOR_FORCE_INLINE static void store(volatile fixnum* ptr, fixnum val) {
*ptr = val;
atomic::fence();
}
}
}
|
;;
;; Copyright (c) 2012-2020, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the distribution.
;; * Neither the name of Intel Corporation nor the names of its contributors
;; may be used to endorse or promote products derived from this software
;; without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;
;;; routine to do a 256 bit CBC AES encrypt
;;; process 4 buffers at a time, single data structure as input
;;; Updates In and Out pointers at end
%include "include/os.asm"
%include "mb_mgr_datastruct.asm"
%include "include/clear_regs.asm"
%define MOVDQ movdqu ;; assume buffers not aligned
%macro pxor2 2
MOVDQ XTMP, %2
pxor %1, XTMP
%endm
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; struct AES_ARGS {
;; void* in[8];
;; void* out[8];
;; UINT128* keys[8];
;; UINT128 IV[8];
;; }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; void aes_cbc_enc_256_x4(AES_ARGS *args, UINT64 len);
;; arg 1: ARG : addr of AES_ARGS structure
;; arg 2: LEN : len (in units of bytes)
%ifdef LINUX
%define ARG rdi
%define LEN rsi
%define REG3 rcx
%define REG4 rdx
%else
%define ARG rcx
%define LEN rdx
%define REG3 rsi
%define REG4 rdi
%endif
%define IDX rax
%define IN0 r8
%define KEYS0 rbx
%define OUT0 r9
%define IN1 r10
%define KEYS1 REG3
%define OUT1 r11
%define IN2 r12
%define KEYS2 REG4
%define OUT2 r13
%define IN3 r14
%define KEYS3 rbp
%define OUT3 r15
%define XDATA0 xmm0
%define XDATA1 xmm1
%define XDATA2 xmm2
%define XDATA3 xmm3
%define XKEY0_3 xmm4
%define XKEY0_6 [KEYS0 + 16*6]
%define XTMP xmm5
%define XKEY0_9 xmm6
%define XKEY1_3 xmm7
%define XKEY1_6 xmm8
%define XKEY1_9 xmm9
%define XKEY2_3 xmm10
%define XKEY2_6 xmm11
%define XKEY2_9 xmm12
%define XKEY3_3 xmm13
%define XKEY3_6 xmm14
%define XKEY3_9 xmm15
%ifndef AES_CBC_ENC_X4
%define AES_CBC_ENC_X4 aes_cbc_enc_256_x4
%endif
section .text
MKGLOBAL(AES_CBC_ENC_X4,function,internal)
AES_CBC_ENC_X4:
push rbp
mov IDX, 16
mov IN0, [ARG + _aesarg_in + 8*0]
mov IN1, [ARG + _aesarg_in + 8*1]
mov IN2, [ARG + _aesarg_in + 8*2]
mov IN3, [ARG + _aesarg_in + 8*3]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOVDQ XDATA0, [IN0] ; load first block of plain text
MOVDQ XDATA1, [IN1] ; load first block of plain text
MOVDQ XDATA2, [IN2] ; load first block of plain text
MOVDQ XDATA3, [IN3] ; load first block of plain text
mov KEYS0, [ARG + _aesarg_keys + 8*0]
mov KEYS1, [ARG + _aesarg_keys + 8*1]
mov KEYS2, [ARG + _aesarg_keys + 8*2]
mov KEYS3, [ARG + _aesarg_keys + 8*3]
pxor XDATA0, [ARG + _aesarg_IV + 16*0] ; plaintext XOR IV
pxor XDATA1, [ARG + _aesarg_IV + 16*1] ; plaintext XOR IV
pxor XDATA2, [ARG + _aesarg_IV + 16*2] ; plaintext XOR IV
pxor XDATA3, [ARG + _aesarg_IV + 16*3] ; plaintext XOR IV
mov OUT0, [ARG + _aesarg_out + 8*0]
mov OUT1, [ARG + _aesarg_out + 8*1]
mov OUT2, [ARG + _aesarg_out + 8*2]
mov OUT3, [ARG + _aesarg_out + 8*3]
pxor XDATA0, [KEYS0 + 16*0] ; 0. ARK
pxor XDATA1, [KEYS1 + 16*0] ; 0. ARK
pxor XDATA2, [KEYS2 + 16*0] ; 0. ARK
pxor XDATA3, [KEYS3 + 16*0] ; 0. ARK
aesenc XDATA0, [KEYS0 + 16*1] ; 1. ENC
aesenc XDATA1, [KEYS1 + 16*1] ; 1. ENC
aesenc XDATA2, [KEYS2 + 16*1] ; 1. ENC
aesenc XDATA3, [KEYS3 + 16*1] ; 1. ENC
aesenc XDATA0, [KEYS0 + 16*2] ; 2. ENC
aesenc XDATA1, [KEYS1 + 16*2] ; 2. ENC
aesenc XDATA2, [KEYS2 + 16*2] ; 2. ENC
aesenc XDATA3, [KEYS3 + 16*2] ; 2. ENC
movdqa XKEY0_3, [KEYS0 + 16*3] ; load round 3 key
movdqa XKEY1_3, [KEYS1 + 16*3] ; load round 3 key
movdqa XKEY2_3, [KEYS2 + 16*3] ; load round 3 key
movdqa XKEY3_3, [KEYS3 + 16*3] ; load round 3 key
aesenc XDATA0, XKEY0_3 ; 3. ENC
aesenc XDATA1, XKEY1_3 ; 3. ENC
aesenc XDATA2, XKEY2_3 ; 3. ENC
aesenc XDATA3, XKEY3_3 ; 3. ENC
aesenc XDATA0, [KEYS0 + 16*4] ; 4. ENC
aesenc XDATA1, [KEYS1 + 16*4] ; 4. ENC
aesenc XDATA2, [KEYS2 + 16*4] ; 4. ENC
aesenc XDATA3, [KEYS3 + 16*4] ; 4. ENC
aesenc XDATA0, [KEYS0 + 16*5] ; 5. ENC
aesenc XDATA1, [KEYS1 + 16*5] ; 5. ENC
aesenc XDATA2, [KEYS2 + 16*5] ; 5. ENC
aesenc XDATA3, [KEYS3 + 16*5] ; 5. ENC
movdqa XKEY1_6, [KEYS1 + 16*6] ; load round 6 key
movdqa XKEY2_6, [KEYS2 + 16*6] ; load round 6 key
movdqa XKEY3_6, [KEYS3 + 16*6] ; load round 6 key
aesenc XDATA0, XKEY0_6 ; 6. ENC
aesenc XDATA1, XKEY1_6 ; 6. ENC
aesenc XDATA2, XKEY2_6 ; 6. ENC
aesenc XDATA3, XKEY3_6 ; 6. ENC
aesenc XDATA0, [KEYS0 + 16*7] ; 7. ENC
aesenc XDATA1, [KEYS1 + 16*7] ; 7. ENC
aesenc XDATA2, [KEYS2 + 16*7] ; 7. ENC
aesenc XDATA3, [KEYS3 + 16*7] ; 7. ENC
aesenc XDATA0, [KEYS0 + 16*8] ; 8. ENC
aesenc XDATA1, [KEYS1 + 16*8] ; 8. ENC
aesenc XDATA2, [KEYS2 + 16*8] ; 8. ENC
aesenc XDATA3, [KEYS3 + 16*8] ; 8. ENC
movdqa XKEY0_9, [KEYS0 + 16*9] ; load round 9 key
movdqa XKEY1_9, [KEYS1 + 16*9] ; load round 9 key
movdqa XKEY2_9, [KEYS2 + 16*9] ; load round 9 key
movdqa XKEY3_9, [KEYS3 + 16*9] ; load round 9 key
aesenc XDATA0, XKEY0_9 ; 9. ENC
aesenc XDATA1, XKEY1_9 ; 9. ENC
aesenc XDATA2, XKEY2_9 ; 9. ENC
aesenc XDATA3, XKEY3_9 ; 9. ENC
aesenc XDATA0, [KEYS0 + 16*10] ; 10. ENC
aesenc XDATA1, [KEYS1 + 16*10] ; 10. ENC
aesenc XDATA2, [KEYS2 + 16*10] ; 10. ENC
aesenc XDATA3, [KEYS3 + 16*10] ; 10. ENC
aesenc XDATA0, [KEYS0 + 16*11] ; 11. ENC
aesenc XDATA1, [KEYS1 + 16*11] ; 11. ENC
aesenc XDATA2, [KEYS2 + 16*11] ; 11. ENC
aesenc XDATA3, [KEYS3 + 16*11] ; 11. ENC
aesenc XDATA0, [KEYS0 + 16*12] ; 12. ENC
aesenc XDATA1, [KEYS1 + 16*12] ; 12. ENC
aesenc XDATA2, [KEYS2 + 16*12] ; 12. ENC
aesenc XDATA3, [KEYS3 + 16*12] ; 12. ENC
aesenc XDATA0, [KEYS0 + 16*13] ; 13. ENC
aesenc XDATA1, [KEYS1 + 16*13] ; 13. ENC
aesenc XDATA2, [KEYS2 + 16*13] ; 13. ENC
aesenc XDATA3, [KEYS3 + 16*13] ; 13. ENC
aesenclast XDATA0, [KEYS0 + 16*14] ; 14. ENC
aesenclast XDATA1, [KEYS1 + 16*14] ; 14. ENC
aesenclast XDATA2, [KEYS2 + 16*14] ; 14. ENC
aesenclast XDATA3, [KEYS3 + 16*14] ; 14. ENC
MOVDQ [OUT0], XDATA0 ; write back ciphertext
MOVDQ [OUT1], XDATA1 ; write back ciphertext
MOVDQ [OUT2], XDATA2 ; write back ciphertext
MOVDQ [OUT3], XDATA3 ; write back ciphertext
cmp LEN, IDX
je done
main_loop:
pxor2 XDATA0, [IN0 + IDX] ; plaintext XOR IV
pxor2 XDATA1, [IN1 + IDX] ; plaintext XOR IV
pxor2 XDATA2, [IN2 + IDX] ; plaintext XOR IV
pxor2 XDATA3, [IN3 + IDX] ; plaintext XOR IV
pxor XDATA0, [KEYS0 + 16*0] ; 0. ARK
pxor XDATA1, [KEYS1 + 16*0] ; 0. ARK
pxor XDATA2, [KEYS2 + 16*0] ; 0. ARK
pxor XDATA3, [KEYS3 + 16*0] ; 0. ARK
aesenc XDATA0, [KEYS0 + 16*1] ; 1. ENC
aesenc XDATA1, [KEYS1 + 16*1] ; 1. ENC
aesenc XDATA2, [KEYS2 + 16*1] ; 1. ENC
aesenc XDATA3, [KEYS3 + 16*1] ; 1. ENC
aesenc XDATA0, [KEYS0 + 16*2] ; 2. ENC
aesenc XDATA1, [KEYS1 + 16*2] ; 2. ENC
aesenc XDATA2, [KEYS2 + 16*2] ; 2. ENC
aesenc XDATA3, [KEYS3 + 16*2] ; 2. ENC
aesenc XDATA0, XKEY0_3 ; 3. ENC
aesenc XDATA1, XKEY1_3 ; 3. ENC
aesenc XDATA2, XKEY2_3 ; 3. ENC
aesenc XDATA3, XKEY3_3 ; 3. ENC
aesenc XDATA0, [KEYS0 + 16*4] ; 4. ENC
aesenc XDATA1, [KEYS1 + 16*4] ; 4. ENC
aesenc XDATA2, [KEYS2 + 16*4] ; 4. ENC
aesenc XDATA3, [KEYS3 + 16*4] ; 4. ENC
aesenc XDATA0, [KEYS0 + 16*5] ; 5. ENC
aesenc XDATA1, [KEYS1 + 16*5] ; 5. ENC
aesenc XDATA2, [KEYS2 + 16*5] ; 5. ENC
aesenc XDATA3, [KEYS3 + 16*5] ; 5. ENC
aesenc XDATA0, XKEY0_6 ; 6. ENC
aesenc XDATA1, XKEY1_6 ; 6. ENC
aesenc XDATA2, XKEY2_6 ; 6. ENC
aesenc XDATA3, XKEY3_6 ; 6. ENC
aesenc XDATA0, [KEYS0 + 16*7] ; 7. ENC
aesenc XDATA1, [KEYS1 + 16*7] ; 7. ENC
aesenc XDATA2, [KEYS2 + 16*7] ; 7. ENC
aesenc XDATA3, [KEYS3 + 16*7] ; 7. ENC
aesenc XDATA0, [KEYS0 + 16*8] ; 8. ENC
aesenc XDATA1, [KEYS1 + 16*8] ; 8. ENC
aesenc XDATA2, [KEYS2 + 16*8] ; 8. ENC
aesenc XDATA3, [KEYS3 + 16*8] ; 8. ENC
aesenc XDATA0, XKEY0_9 ; 9. ENC
aesenc XDATA1, XKEY1_9 ; 9. ENC
aesenc XDATA2, XKEY2_9 ; 9. ENC
aesenc XDATA3, XKEY3_9 ; 9. ENC
aesenc XDATA0, [KEYS0 + 16*10] ; 10. ENC
aesenc XDATA1, [KEYS1 + 16*10] ; 10. ENC
aesenc XDATA2, [KEYS2 + 16*10] ; 10. ENC
aesenc XDATA3, [KEYS3 + 16*10] ; 10. ENC
aesenc XDATA0, [KEYS0 + 16*11] ; 11. ENC
aesenc XDATA1, [KEYS1 + 16*11] ; 11. ENC
aesenc XDATA2, [KEYS2 + 16*11] ; 11. ENC
aesenc XDATA3, [KEYS3 + 16*11] ; 11. ENC
aesenc XDATA0, [KEYS0 + 16*12] ; 12. ENC
aesenc XDATA1, [KEYS1 + 16*12] ; 12. ENC
aesenc XDATA2, [KEYS2 + 16*12] ; 12. ENC
aesenc XDATA3, [KEYS3 + 16*12] ; 12. ENC
aesenc XDATA0, [KEYS0 + 16*13] ; 13. ENC
aesenc XDATA1, [KEYS1 + 16*13] ; 13. ENC
aesenc XDATA2, [KEYS2 + 16*13] ; 13. ENC
aesenc XDATA3, [KEYS3 + 16*13] ; 13. ENC
aesenclast XDATA0, [KEYS0 + 16*14] ; 14. ENC
aesenclast XDATA1, [KEYS1 + 16*14] ; 14. ENC
aesenclast XDATA2, [KEYS2 + 16*14] ; 14. ENC
aesenclast XDATA3, [KEYS3 + 16*14] ; 14. ENC
MOVDQ [OUT0 + IDX], XDATA0 ; write back ciphertext
MOVDQ [OUT1 + IDX], XDATA1 ; write back ciphertex
MOVDQ [OUT2 + IDX], XDATA2 ; write back ciphertex
MOVDQ [OUT3 + IDX], XDATA3 ; write back ciphertex
add IDX, 16
cmp LEN, IDX
jne main_loop
done:
;; update IV
movdqa [ARG + _aesarg_IV + 16*0], XDATA0
movdqa [ARG + _aesarg_IV + 16*1], XDATA1
movdqa [ARG + _aesarg_IV + 16*2], XDATA2
movdqa [ARG + _aesarg_IV + 16*3], XDATA3
;; update IN and OUT
add IN0, LEN
mov [ARG + _aesarg_in + 8*0], IN0
add IN1, LEN
mov [ARG + _aesarg_in + 8*1], IN1
add IN2, LEN
mov [ARG + _aesarg_in + 8*2], IN2
add IN3, LEN
mov [ARG + _aesarg_in + 8*3], IN3
add OUT0, LEN
mov [ARG + _aesarg_out + 8*0], OUT0
add OUT1, LEN
mov [ARG + _aesarg_out + 8*1], OUT1
add OUT2, LEN
mov [ARG + _aesarg_out + 8*2], OUT2
add OUT3, LEN
mov [ARG + _aesarg_out + 8*3], OUT3
pop rbp
%ifdef SAFE_DATA
clear_all_xmms_sse_asm
%endif ;; SAFE_DATA
ret
%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
|
; 2018 July feilipu
INCLUDE "config_private.inc"
SECTION code_clib
SECTION code_math
PUBLIC l_z80_zxn_mulu_32_32x32, l0_z80_zxn_mulu_32_32x32
l_z80_zxn_mulu_32_32x32:
; multiplication of two 32-bit numbers into a 32-bit product
;
; enter : dehl = 32-bit multiplicand
; dehl'= 32-bit multiplicand
;
; exit : dehl = 32-bit product
; carry reset
;
; uses : af, bc, de, hl, bc', de', hl'
push hl
exx
ld c,l
ld b,h
pop hl
push de
ex de,hl
exx
pop bc
l0_z80_zxn_mulu_32_32x32:
; multiplication of two 32-bit numbers into a 32-bit product
;
; enter : dede' = 32-bit multiplier = x
; bcbc' = 32-bit multiplicand = y
;
; exit : dehl = 32-bit product
; carry reset
;
; uses : af, bc, de, hl, bc', de', hl'
; save material for the byte p3 = x3*y0 + x2*y1 + x1*y2 + x0*y3 + p2 carry
push de ; x3 x2
exx
push bc ; y1 y0
push de ; x1 x0
exx
push bc ; y3 y2
; save material for the byte p2 = x2*y0 + x0*y2 + x1*y1 + p1 carry
; start of 32_32x32
ld h,e
ld l,c
push hl ; x2 y2
exx ; now we're working in the low order bytes
ld h,e
ld l,c
push hl ; x0 y0
; start of 32_16x16 p1 = x1*y0 + x0*y1 + p0 carry
; p0 = x0*y0
ld h,d
ld l,b
push hl ; x1 y1
ld h,d ; x1
ld d,b ; y1
ld l,c ; y0
ld b,e ; x0
; bc = x0 y0
; de = y1 x0
; hl = x1 y0
; stack = x1 y1
mul de ; y1*x0
ex de,hl
mul de ; x1*y0
xor a ; zero A
add hl,de ; sum cross products p2 p1
adc a,a ; capture carry p3
ld e,c ; x0
ld d,b ; y0
mul de ; y0*x0
ld b,a ; carry from cross products
ld c,h ; LSB of MSW from cross products
ld a,d
add a,l
ld h,a
ld l,e ; LSW in HL p1 p0
pop de
mul de ; x1*y1
ex de,hl
adc hl,bc ; HL = interim MSW p3 p2
; 32_16x16 = HLDE
push hl ; stack interim p3 p2
ex de,hl ; p1 p0 in HL
; continue doing the p2 byte
exx ; now we're working in the high order bytes
; DEHL' = end of 32_16x16
pop bc ; stack interim p3 p2
pop hl ; x0 y0
pop de ; x2 y2
ld a,h
ld h,d
ld d,a
mul de ; x0*y2
ex de,hl
mul de ; x2*y0
add hl,bc
add hl,de
ld b,h
ld c,l
; start doing the p3 byte
pop hl ; y3 y2
pop de ; x1 x0
ld a,h
ld h,d
ld d,a
mul de ; y3*x0
ex de,hl
mul de ; x1*y2
ld a,b ; work with existing p3 from B
add a,e ; add low bytes of products
add a,l
pop hl ; y1 y0
pop de ; x3 x2
ld b,h
ld h,d
ld d,b
mul de ; y1*x2
ex de,hl
mul de ; x3*y0
add a,l ; add low bytes of products
add a,e
ld b,a ; put final p3 back in B
push bc
exx ; now we're working in the low order bytes, again
pop de
xor a ; carry reset
ret ; exit : DEHL = 32-bit product
|
// Copyright (c) by respective owners including Yahoo!, Microsoft, and
// individual contributors. All rights reserved. Released under a BSD (revised)
// license as described in the file LICENSE.
#include "slates_label.h"
#include "cache.h"
#include "parser.h"
#include "vw_string_view.h"
#include "constant.h"
#include "vw_math.h"
#include <numeric>
namespace slates
{
void default_label(void* v);
#define READ_CACHED_VALUE(DEST, TYPE) \
next_read_size = sizeof(TYPE); \
if (cache.buf_read(read_ptr, next_read_size) < next_read_size) \
return 0; \
DEST = *(TYPE*)read_ptr; \
read_count += sizeof(TYPE);
#define WRITE_CACHED_VALUE(VALUE, TYPE) \
*(TYPE*)c = VALUE; \
c += sizeof(TYPE);
size_t read_cached_label(shared_data*, void* v, io_buf& cache)
{
// Since read_cached_features doesn't default the label we must do it here.
default_label(v);
slates::label* ld = static_cast<slates::label*>(v);
size_t read_count = 0;
char* read_ptr;
size_t next_read_size = 0;
READ_CACHED_VALUE(ld->type, slates::example_type);
READ_CACHED_VALUE(ld->weight, float);
READ_CACHED_VALUE(ld->labeled, bool);
READ_CACHED_VALUE(ld->cost, float);
READ_CACHED_VALUE(ld->slot_id, uint32_t);
uint32_t size_probs = 0;
READ_CACHED_VALUE(size_probs, uint32_t);
for (uint32_t i = 0; i < size_probs; i++)
{
ACTION_SCORE::action_score a_s;
READ_CACHED_VALUE(a_s, ACTION_SCORE::action_score);
ld->probabilities.push_back(a_s);
}
return read_count;
}
void cache_label(void* v, io_buf& cache)
{
char* c;
slates::label* ld = static_cast<slates::label*>(v);
size_t size = sizeof(ld->type)
+ sizeof(ld->weight)
+ sizeof(ld->labeled)
+ sizeof(ld->cost)
+ sizeof(ld->slot_id)
+ sizeof(uint32_t) // Size of probabilities
+ sizeof(ACTION_SCORE::action_score) * ld->probabilities.size();
cache.buf_write(c, size);
WRITE_CACHED_VALUE(ld->type, slates::example_type);
WRITE_CACHED_VALUE(ld->weight, float);
WRITE_CACHED_VALUE(ld->labeled, bool);
WRITE_CACHED_VALUE(ld->cost, float);
WRITE_CACHED_VALUE(VW::convert(ld->slot_id), uint32_t);
WRITE_CACHED_VALUE(VW::convert(ld->probabilities.size()), uint32_t);
for (const auto& score : ld->probabilities)
{
WRITE_CACHED_VALUE(score, ACTION_SCORE::action_score);
}
}
float weight(void* v)
{
return static_cast<polylabel*>(v)->slates.weight;
}
void default_label(void* v)
{
auto& label = static_cast<polylabel*>(v)->slates;
label.type = example_type::unset;
label.weight = 1.f;
label.labeled = false;
label.cost = 0.f;
label.slot_id = 0;
label.probabilities.clear();
}
bool test_label(void* v)
{
auto& ld = static_cast<polylabel*>(v)->slates;
return ld.labeled == false;
}
void delete_label(void* v)
{
auto& ld = static_cast<polylabel*>(v)->slates;
ld.probabilities.delete_v();
}
void copy_label(void* dst, void* src)
{
auto& ldDst = static_cast<polylabel*>(dst)->slates;
auto& ldSrc = static_cast<polylabel*>(src)->slates;
ldDst.type = ldSrc.type;
ldDst.weight = ldSrc.weight;
ldDst.labeled = ldSrc.labeled;
ldDst.cost = ldSrc.cost;
ldDst.slot_id = ldSrc.slot_id;
copy_array(ldDst.probabilities, ldSrc.probabilities);
}
// Slates labels come in three types, shared, action and slot with the following structure:
// slates shared [global_cost]
// slates action <slot_id>
// slates slot [chosen_action_id:probability[,action_id:probability...]]
//
// For a more complete description of the grammar, including examples see:
// https://github.com/VowpalWabbit/vowpal_wabbit/wiki/Slates
void parse_label(parser* p, shared_data*, void* v, v_array<VW::string_view>& words)
{
auto& ld = static_cast<polylabel*>(v)->slates;
ld.weight = 1;
if (words.size() == 0)
{
THROW("Slates labels may not be empty");
}
if (!(words[0] == SLATES_LABEL))
{
THROW("Slates labels require the first word to be slates");
}
if (words.size() == 1)
{
THROW("Slates labels require a type. It must be one of: [shared, action, slot]");
}
const auto& type = words[1];
if (type == SHARED_TYPE)
{
// There is a cost defined.
if (words.size() == 3)
{
ld.cost = float_of_string(words[2]);
ld.labeled = true;
}
else if (words.size() != 2)
{
THROW("Slates shared labels must be of the form: slates shared [global_cost]");
}
ld.type = example_type::shared;
}
else if (type == ACTION_TYPE)
{
if (words.size() != 3)
{
THROW("Slates action labels must be of the form: slates action <slot_id>");
}
ld.slot_id = int_of_string(words[2]);
ld.type = example_type::action;
}
else if (type == SLOT_TYPE)
{
if (words.size() == 3)
{
ld.labeled = true;
tokenize(',', words[2], p->parse_name);
auto split_colons = v_init<VW::string_view>();
for (auto& token : p->parse_name)
{
tokenize(':', token, split_colons);
if (split_colons.size() != 2)
{
THROW("Malformed action score token");
}
// Element 0 is the action, element 1 is the probability
ld.probabilities.push_back(
{static_cast<uint32_t>(int_of_string(split_colons[0])), float_of_string(split_colons[1])});
}
// If a full distribution has been given, check if it sums to 1, otherwise throw.
if (ld.probabilities.size() > 1)
{
float total_pred = std::accumulate(ld.probabilities.begin(), ld.probabilities.end(), 0.f,
[](float result_so_far, const ACTION_SCORE::action_score& action_pred) {
return result_so_far + action_pred.score;
});
if (!VW::math::are_same(total_pred, 1.f))
{
THROW(
"When providing all prediction probabilities they must add up to 1.0, instead summed to " << total_pred);
}
}
}
else if (words.size() > 3)
{
THROW(
"Slates shared labels must be of the form: slates slot "
"[chosen_action_id:probability[,action_id:probability...]]");
}
ld.type = example_type::slot;
}
else
{
THROW("Unknown slates label type: " << type);
}
}
// Export the definition of this label parser.
label_parser slates_label_parser = {default_label, parse_label, cache_label, read_cached_label, delete_label, weight,
copy_label, test_label, sizeof(slates::label)};
} // namespace CCB
|
; ------------------------------------------------------------------
; MichalOS File Manager
; ------------------------------------------------------------------
%INCLUDE "michalos.inc"
start:
mov [.load_segment], gs
call .draw_background
mov byte [32767], 0
call os_file_selector
jc near .exit
mov bx, ax
mov cx, .screenstring
mov ax, .root
call os_string_join
mov ax, bx
push ax
mov bx, cx
.commands:
mov ax, .command_list ; Draw list of disk operations
mov cx, .helpmsg
mov word [0089h], 37
call os_list_dialog
mov word [0089h], 76
jc near .clearstack ; User pressed Esc?
cmp ax, 1 ; Otherwise respond to choice
je near .launch_file
cmp ax, 2
je near .create_file
cmp ax, 3
je near .delete_file
cmp ax, 4
je near .rename_file
cmp ax, 5
je near .copy_file
.clearstack:
pop ax
jmp start
.launch_file:
mov al, 1
mov [32767], al
pop ax
ret
.create_file:
pop ax
call .draw_background
mov bx, .filename_msg ; Get a filename
mov ax, .filename_input
call os_input_dialog
mov cx, 0 ; Create an empty file
mov bx, 4096
mov ax, .filename_input
call os_write_file
jc near .writing_error
jmp start
.delete_file:
call .draw_background
mov ax, .delete_confirm_msg ; Confirm delete operation
mov bx, 0
mov cx, 0
mov dx, 1
call os_dialog_box
cmp ax, 0
je .ok_to_delete
pop ax
jmp start
.ok_to_delete:
pop ax
call os_remove_file
jc near .disk_error
jmp start
.rename_file:
call .draw_background
pop ax
mov si, ax ; And store it
mov di, .filename_tmp1
call os_string_copy
.retry_rename:
call .draw_background
mov bx, .filename_msg ; Get second filename
mov ax, .filename_input
call os_input_dialog
mov si, ax ; Store it for later
mov di, .filename_tmp2
call os_string_copy
mov ax, di ; Does the second filename already exist?
call os_file_exists
jnc .rename_fail ; Quit out if so
mov ax, .filename_tmp1
mov bx, .filename_tmp2
call os_rename_file
jc near .writing_error
jmp start
.rename_fail:
mov ax, .err_file_exists
mov bx, 0
mov cx, 0
mov dx, 0
call os_dialog_box
jmp start
.copy_file:
call .draw_background
pop ax
mov si, ax ; And store it
mov di, .filename_tmp1
call os_string_copy
call .draw_background
mov bx, .filename_msg ; Get second filename
mov ax, .filename_input
call os_input_dialog
call os_file_exists
jnc .file_exists
mov si, ax
mov di, .filename_tmp2
call os_string_copy
mov ax, .filename_tmp1
mov bx, .filename_tmp2
call os_get_file_size
cmp ebx, 28672
jl .no_copy_change
mov word [.load_segment], gs
mov word [.load_offset], 0000h
.no_copy_change:
push es
mov es, [.load_segment]
mov cx, [.load_offset]
call os_load_file
mov byte [0086h], 5
mov cx, bx
mov bx, [.load_offset]
mov ax, .filename_tmp2
call os_write_file
pop es
jc near .writing_error
mov word [.load_segment], cs
mov word [.load_offset], 1000h
jmp start
.no_copy_file_selected:
jmp start
.writing_error:
mov word [.load_segment], cs
mov word [.load_offset], 1000h
call .draw_background
clr bx
clr cx
clr dx
cmp byte [0086h], 0
je .failure0
cmp byte [0086h], 1
je .failure1
cmp byte [0086h], 2
je .failure2
cmp byte [0086h], 3
je .failure3
cmp byte [0086h], 4
je .failure4
mov ax, .error_msg
mov bx, .error_msg2
call os_dialog_box
jmp start
.failure0:
mov ax, .failure0msg
call os_dialog_box
jmp start
.failure1:
mov ax, .failure1msg
call os_dialog_box
jmp start
.failure2:
mov ax, .failure2msg
call os_dialog_box
jmp start
.failure3:
mov ax, .failure3msg
call os_dialog_box
jmp start
.failure4:
mov ax, .failure4msg
call os_dialog_box
jmp start
.exit:
call os_clear_screen
ret
.draw_background:
mov ax, .title_msg
mov bx, .footer_msg
mov cx, 256
call os_draw_background
ret
.disk_error:
mov ax, .dk_error
mov bx, 0
mov cx, 0
mov dx, 0
call os_dialog_box
jmp start
.file_exists:
mov ax, .err_file_exists
mov bx, 0
mov cx, 0
mov dx, 0
call os_dialog_box
jmp start
.command_list db 'Run application,Create file,Delete file,Rename,Copy file', 0
.root db 'A:/'
.helpmsg db 0
.title_msg db 'MichalOS File Manager', 0
.footer_msg db 0
.delete_confirm_msg db 'Are you sure?', 0
.filename_msg db 'Enter a new filename:', 0
.filename_input times 15 db 0
.filename_tmp1 times 15 db 0
.filename_tmp2 times 15 db 0
.error_msg db 'Error writing to the disk!', 0
.error_msg2 db '(Disk is read-only/file already exists)?', 0
.err_file_exists db 'File with this name already exists!', 0
.failure0msg db 'Filename is too long!', 0
.failure1msg db 'Filename is empty!', 0
.failure2msg db 'Filename has no extension!', 0
.failure3msg db 'Filename has no basename!', 0
.failure4msg db 'Extension is too short!', 0
.dk_error db 'Disk error!', 0
.load_segment dw 0
.load_offset dw 0
.screenstring times 24 db 0
blank:
; ------------------------------------------------------------------
|
SECTION TRICEROPOP
org 55000
; *** Song layout ***
LOOPSTART: DEFW PAT0
DEFW PAT0
DEFW PAT0
DEFW PAT0
DEFW PAT4
DEFW PAT3
DEFW PAT4
DEFW PAT3
DEFW PAT9
DEFW PAT9
DEFW PAT10
DEFW PAT10
DEFW PAT15
DEFW PAT15
DEFW PAT16
DEFW PAT16
DEFW PAT11
DEFW PAT12
DEFW PAT3
DEFW PAT4
DEFW PAT0
DEFW PAT0
DEFW PAT0
DEFW PAT0
DEFW PAT4
DEFW PAT3
DEFW PAT4
DEFW PAT3
DEFW PAT9
DEFW PAT10
DEFW PAT15
DEFW PAT27
DEFW PAT22
DEFW PAT23
DEFW PAT24
DEFW PAT25
DEFW PAT26
DEFW PAT26
DEFW PAT15
DEFW PAT15
DEFW PAT27
DEFW PAT27
DEFW PAT22
DEFW PAT23
DEFW PAT24
DEFW PAT25
DEFW $0000
DEFW LOOPSTART
; *** Patterns ***
PAT0:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$80,$76,$F1,$61,$90,$EC
DEFB $80,$EC,$01 ,$E1,$D8
DEFB $80,$76,$01 ,$90,$EC
DEFB $80,$EC,$01 ,$91,$D8
DEFB $04,$80,$8C,$F1,$A4,$91,$18
DEFB $81,$18,$01 ,$E2,$31
DEFB $80,$8C,$01 ,$91,$18
DEFB $81,$18,$01 ,$92,$31
DEFB $06,$80,$9D,$F1,$D8,$91,$3B
DEFB $81,$3B,$01 ,$E2,$76
DEFB $80,$9D,$01 ,$91,$3B
DEFB $81,$3B,$01 ,$92,$76
DEFB $04,$80,$69,$F1,$3B,$90,$D2
DEFB $80,$D2,$01 ,$E1,$A4
DEFB $80,$69,$01 ,$90,$D2
DEFB $80,$D2,$01 ,$91,$A4
DEFB $FF ; End of Pattern
PAT3:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$80,$EC,$F0,$ED,$B0,$76
DEFB $81,$61,$F1,$62,$01
DEFB $06,$81,$D8,$F1,$D9,$01
DEFB $80,$EC,$F0,$ED,$01
DEFB $03,$81,$61,$F1,$62,$01
DEFB $81,$D8,$F1,$D9,$01
DEFB $0E,$80,$EC,$F0,$ED,$01
DEFB $81,$61,$F1,$62,$01
DEFB $06,$81,$18,$F2,$31,$B1,$A4
DEFB $01 ,$01 ,$01
DEFB $06,$01 ,$81,$19,$81,$A4
DEFB $01 ,$01 ,$01
DEFB $03,$01 ,$F2,$31,$B1,$A4
DEFB $01 ,$01 ,$01
DEFB $0E,$E1,$18,$B1,$19,$E1,$A4
DEFB $01 ,$01 ,$01
DEFB $FF ; End of Pattern
PAT4:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$80,$EC,$E3,$B0,$80,$77
DEFB $81,$61,$E3,$49,$D1,$62
DEFB $06,$81,$D8,$82,$C3,$D1,$D9
DEFB $80,$EC,$81,$D8,$80,$77
DEFB $04,$81,$61,$E1,$A4,$D1,$62
DEFB $81,$D8,$E1,$D8,$D1,$D9
DEFB $0E,$80,$EC,$F2,$31,$80,$77
DEFB $81,$61,$00 ,$D1,$62
DEFB $06,$81,$18,$D2,$C3,$F1,$A4
DEFB $01 ,$D2,$31,$F0,$D2
DEFB $09,$01 ,$81,$D8,$81,$A4
DEFB $01 ,$81,$A4,$80,$D2
DEFB $04,$01 ,$E3,$B0,$F1,$A4
DEFB $01 ,$E3,$49,$F0,$D2
DEFB $0E,$E1,$18,$82,$C3,$E1,$A4
DEFB $01 ,$E2,$C3,$01
DEFB $FF ; End of Pattern
PAT9:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$01 ,$80,$EC
DEFB $06,$B0,$D3,$90,$D2,$F1,$A4
DEFB $01 ,$01 ,$F0,$D2
DEFB $04,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$01 ,$F0,$EC
DEFB $0E,$B0,$ED,$90,$EC,$00
DEFB $09,$00 ,$01 ,$01
DEFB $06,$B0,$EC,$90,$ED,$F1,$D8
DEFB $B0,$76,$01 ,$F0,$EC
DEFB $09,$01 ,$00 ,$00
DEFB $01 ,$01 ,$80,$EC
DEFB $04,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$00 ,$80,$EC
DEFB $0E,$B0,$D2,$90,$D3,$F1,$A4
DEFB $B0,$69,$01 ,$80,$D2
DEFB $FF ; End of Pattern
PAT10:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$ED,$90,$EC,$93,$B0
DEFB $B0,$76,$01 ,$00
DEFB $06,$B0,$D3,$90,$D2,$93,$49
DEFB $01 ,$01 ,$00
DEFB $04,$B0,$ED,$90,$EC,$94,$63
DEFB $B0,$76,$01 ,$E4,$63
DEFB $0E,$B0,$ED,$90,$EC,$93,$B0
DEFB $00 ,$01 ,$E3,$B0
DEFB $06,$B0,$EC,$90,$ED,$F1,$D8
DEFB $B0,$76,$01 ,$F0,$EC
DEFB $0E,$01 ,$00 ,$00
DEFB $01 ,$01 ,$80,$EC
DEFB $04,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$00 ,$80,$EC
DEFB $0E,$B0,$D3,$90,$D2,$F1,$A4
DEFB $B0,$69,$01 ,$80,$D2
DEFB $FF ; End of Pattern
PAT11:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$80,$ED,$F0,$EC,$93,$B0
DEFB $80,$76,$01 ,$93,$49
DEFB $06,$80,$D3,$F0,$D2,$92,$C3
DEFB $01 ,$01 ,$93,$49
DEFB $04,$80,$ED,$F0,$EC,$93,$B0
DEFB $80,$76,$01 ,$00
DEFB $0E,$80,$ED,$F0,$EC,$94,$63
DEFB $00 ,$01 ,$D4,$63
DEFB $06,$80,$ED,$F0,$EC,$F4,$63
DEFB $80,$76,$01 ,$00
DEFB $06,$01 ,$00 ,$F3,$B0
DEFB $01 ,$01 ,$D3,$9C
DEFB $04,$80,$ED,$F0,$EC,$E3,$87
DEFB $80,$76,$00 ,$B3,$73
DEFB $0E,$80,$D3,$F0,$D2,$93,$5E
DEFB $80,$69,$01 ,$83,$49
DEFB $FF ; End of Pattern
PAT12:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$80,$ED,$F0,$EC,$93,$49
DEFB $80,$76,$01 ,$D3,$49
DEFB $06,$80,$D3,$F0,$D2,$F3,$49
DEFB $01 ,$01 ,$00
DEFB $04,$80,$ED,$F0,$EC,$01
DEFB $80,$76,$01 ,$01
DEFB $0E,$80,$ED,$F0,$EC,$F1,$D8
DEFB $00 ,$01 ,$00
DEFB $06,$80,$ED,$F0,$EC,$D2,$C3
DEFB $80,$76,$F1,$D8,$E2,$31
DEFB $06,$01 ,$00 ,$F1,$D8
DEFB $01 ,$01 ,$00
DEFB $04,$80,$ED,$F0,$EC,$D1,$D8
DEFB $80,$76,$00 ,$81,$D8
DEFB $0E,$80,$D3,$F0,$D2,$D1,$A4
DEFB $80,$69,$01 ,$81,$A4
DEFB $FF ; End of Pattern
PAT15:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$EC,$F1,$D8,$93,$B0
DEFB $B0,$76,$80,$EC,$91,$D8
DEFB $0E,$B0,$D2,$F1,$A4,$93,$49
DEFB $01 ,$F0,$D3,$91,$A4
DEFB $04,$B0,$EC,$F1,$D8,$94,$E7
DEFB $B0,$76,$F0,$EC,$95,$86
DEFB $0E,$B0,$EC,$00 ,$93,$B0
DEFB $00 ,$01 ,$E1,$D8
DEFB $06,$B0,$EC,$F1,$D9,$81,$D8
DEFB $B0,$76,$F0,$EC,$01
DEFB $0F,$01 ,$00 ,$80,$EC
DEFB $01 ,$80,$ED,$01
DEFB $04,$B0,$EC,$F1,$D8,$D3,$B0
DEFB $B0,$76,$80,$EC,$91,$D8
DEFB $0E,$B0,$D2,$F1,$A4,$B3,$49
DEFB $B0,$69,$80,$D2,$B1,$A4
DEFB $FF ; End of Pattern
PAT16:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$EC,$F1,$D8,$B6,$92
DEFB $B0,$76,$80,$EC,$B5,$86
DEFB $0E,$B0,$D2,$F1,$A4,$B4,$63
DEFB $01 ,$F0,$D3,$93,$B0
DEFB $04,$B0,$EC,$F1,$D8,$00
DEFB $B0,$76,$F0,$EC,$85,$37
DEFB $0E,$B0,$EC,$00 ,$F4,$E7
DEFB $00 ,$01 ,$B4,$E7
DEFB $06,$B0,$EC,$F1,$D8,$94,$63
DEFB $B0,$76,$F0,$EC,$00
DEFB $09,$01 ,$00 ,$93,$B0
DEFB $01 ,$80,$EC,$91,$D8
DEFB $04,$B0,$D2,$F1,$A4,$E3,$49
DEFB $B0,$69,$80,$D2,$00
DEFB $0E,$B0,$EC,$F1,$D8,$E3,$B0
DEFB $B0,$76,$80,$EC,$00
DEFB $FF ; End of Pattern
PAT22:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$ED,$A3,$B0,$F1,$D8
DEFB $B0,$76,$A4,$63,$80,$EC
DEFB $0E,$B0,$D3,$A5,$86,$F1,$A4
DEFB $01 ,$00 ,$F0,$D2
DEFB $04,$B0,$ED,$D3,$B0,$F1,$D8
DEFB $B0,$76,$00 ,$F0,$EC
DEFB $0E,$B1,$19,$D4,$63,$F2,$31
DEFB $17,$B0,$8C,$D5,$86,$00
DEFB $06,$B0,$ED,$D7,$60,$F1,$D8
DEFB $B0,$76,$00 ,$F0,$EC
DEFB $0E,$B0,$D2,$E8,$C6,$F1,$A4
DEFB $06,$01 ,$E8,$47,$80,$D2
DEFB $04,$B1,$19,$E7,$60,$F2,$31
DEFB $B0,$8C,$E6,$92,$01
DEFB $0E,$B0,$ED,$F5,$86,$F1,$D8
DEFB $B0,$76,$F4,$63,$01
DEFB $FF ; End of Pattern
PAT23:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$D3,$E8,$47,$F1,$A4
DEFB $B0,$69,$01 ,$80,$D2
DEFB $0E,$B0,$BC,$01 ,$F1,$76
DEFB $06,$01 ,$01 ,$F0,$BB
DEFB $04,$B0,$D3,$E6,$92,$F1,$A4
DEFB $B0,$69,$01 ,$F0,$D2
DEFB $0E,$B0,$BC,$01 ,$F1,$76
DEFB $07,$B0,$5D,$01 ,$00
DEFB $06,$B0,$D3,$D4,$E7,$F1,$A4
DEFB $B0,$69,$01 ,$F0,$D2
DEFB $06,$B0,$BB,$01 ,$F1,$76
DEFB $01 ,$01 ,$80,$BB
DEFB $04,$B0,$D3,$B4,$63,$F1,$A4
DEFB $B0,$69,$01 ,$80,$D2
DEFB $05,$B0,$BC,$94,$23,$F1,$76
DEFB $06,$B0,$5D,$01 ,$80,$BB
DEFB $FF ; End of Pattern
PAT24:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$BC,$94,$63,$F1,$76
DEFB $B0,$5D,$A4,$63,$80,$BB
DEFB $06,$B0,$ED,$B4,$63,$F1,$D8
DEFB $01 ,$C4,$63,$F0,$EC
DEFB $04,$B1,$19,$D4,$63,$F2,$31
DEFB $B0,$8C,$E4,$63,$F1,$18
DEFB $0E,$B0,$ED,$F4,$63,$F1,$D8
DEFB $06,$01 ,$01 ,$00
DEFB $06,$B0,$BC,$E4,$E7,$F1,$76
DEFB $B0,$5D,$01 ,$F0,$BB
DEFB $06,$B0,$EC,$E4,$63,$F1,$D8
DEFB $01 ,$01 ,$80,$EC
DEFB $04,$B0,$ED,$E3,$B0,$F1,$D8
DEFB $01 ,$01 ,$80,$EC
DEFB $09,$B0,$BC,$E2,$ED,$F1,$76
DEFB $B0,$5D,$01 ,$80,$BB
DEFB $FF ; End of Pattern
PAT25:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$B1,$E2,$C3,$F1,$61
DEFB $01 ,$B2,$C3,$80,$B0
DEFB $06,$B0,$DF,$E2,$C3,$F1,$BD
DEFB $01 ,$B2,$C3,$F0,$DE
DEFB $04,$B1,$09,$F2,$C3,$F2,$11
DEFB $B0,$84,$01 ,$F1,$08
DEFB $0E,$B0,$DF,$B2,$C3,$F1,$BD
DEFB $04,$01 ,$92,$C3,$00
DEFB $06,$B0,$B1,$F2,$C3,$F1,$61
DEFB $01 ,$01 ,$F0,$B0
DEFB $06,$B0,$DE,$82,$C3,$F1,$BD
DEFB $01 ,$01 ,$80,$DE
DEFB $04,$B0,$DF,$F1,$61,$F1,$BD
DEFB $01 ,$01 ,$80,$DE
DEFB $0E,$B0,$B1,$F1,$62,$F1,$61
DEFB $09,$01 ,$01 ,$80,$B0
DEFB $FF ; End of Pattern
PAT26:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$ED,$93,$B0,$91,$D8
DEFB $B0,$76,$91,$D8,$00
DEFB $0E,$B0,$D3,$93,$49,$91,$A4
DEFB $01 ,$91,$A4,$00
DEFB $04,$B0,$ED,$93,$B0,$91,$D8
DEFB $B0,$76,$94,$63,$E0,$EC
DEFB $0E,$B0,$ED,$93,$B0,$90,$76
DEFB $00 ,$91,$D8,$01
DEFB $06,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$01 ,$F0,$EC
DEFB $0E,$01 ,$00 ,$00
DEFB $01 ,$01 ,$80,$EC
DEFB $04,$B0,$ED,$90,$EC,$F1,$D8
DEFB $B0,$76,$00 ,$80,$EC
DEFB $0E,$B0,$D3,$90,$D2,$F1,$A4
DEFB $B0,$69,$01 ,$80,$D2
DEFB $FF ; End of Pattern
PAT27:
DEFW 2896 ;; was 3692 ; Pattern tempo
; Drum,Chan.1 ,Chan.2 ,Chan.3
DEFB $06,$B0,$ED,$F1,$D8,$E3,$B0
DEFB $B0,$76,$80,$EC,$E3,$49
DEFB $0E,$B0,$D3,$F1,$A4,$85,$37
DEFB $01 ,$F0,$D2,$94,$E7
DEFB $04,$B0,$ED,$F1,$D8,$00
DEFB $B0,$76,$F0,$EC,$E4,$63
DEFB $0E,$B0,$ED,$00 ,$E3,$B0
DEFB $00 ,$01 ,$81,$D8
DEFB $06,$B0,$EC,$F1,$D9,$E4,$63
DEFB $B0,$76,$F0,$EC,$00
DEFB $06,$01 ,$00 ,$E3,$B0
DEFB $01 ,$80,$ED,$00
DEFB $04,$B0,$D2,$F1,$A4,$B3,$49
DEFB $B0,$69,$80,$D2,$91,$A4
DEFB $0E,$B0,$EC,$F1,$D8,$E3,$B0
DEFB $B0,$76,$80,$EC,$E1,$D8
DEFB $FF ; End of Pattern
|
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.7.0 #10231 (Linux)
;--------------------------------------------------------
.module stm8s_gpio
.optsdcc -mstm8
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _GPIO_DeInit
.globl _GPIO_Init
.globl _GPIO_Write
.globl _GPIO_WriteHigh
.globl _GPIO_WriteLow
.globl _GPIO_WriteReverse
.globl _GPIO_ReadOutputData
.globl _GPIO_ReadInputData
.globl _GPIO_ReadInputPin
.globl _GPIO_ExternalPullUpConfig
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
Sstm8s_gpio$GPIO_DeInit$0 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 53: void GPIO_DeInit(GPIO_TypeDef* GPIOx)
; genLabel
; -----------------------------------------
; function GPIO_DeInit
; -----------------------------------------
; Register assignment might be sub-optimal.
; Stack space usage: 0 bytes.
_GPIO_DeInit:
Sstm8s_gpio$GPIO_DeInit$1 ==.
Sstm8s_gpio$GPIO_DeInit$2 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 55: GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
; genAssign
ldw y, (0x03, sp)
; genPointerSet
clr (y)
Sstm8s_gpio$GPIO_DeInit$3 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 56: GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
; genPlus
ldw x, y
incw x
incw x
; genPointerSet
clr (x)
Sstm8s_gpio$GPIO_DeInit$4 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 57: GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
; genPlus
ldw x, y
addw x, #0x0003
; genPointerSet
clr (x)
Sstm8s_gpio$GPIO_DeInit$5 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 58: GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
; genPlus
ldw x, y
addw x, #0x0004
; genPointerSet
clr (x)
; genLabel
00101$:
Sstm8s_gpio$GPIO_DeInit$6 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 59: }
; genEndFunction
Sstm8s_gpio$GPIO_DeInit$7 ==.
XG$GPIO_DeInit$0$0 ==.
ret
Sstm8s_gpio$GPIO_DeInit$8 ==.
Sstm8s_gpio$GPIO_Init$9 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 71: void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
; genLabel
; -----------------------------------------
; function GPIO_Init
; -----------------------------------------
; Register assignment might be sub-optimal.
; Stack space usage: 5 bytes.
_GPIO_Init:
Sstm8s_gpio$GPIO_Init$10 ==.
sub sp, #5
Sstm8s_gpio$GPIO_Init$11 ==.
Sstm8s_gpio$GPIO_Init$12 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 81: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
; genAssign
ldw y, (0x08, sp)
; genPlus
ldw x, y
addw x, #0x0004
ldw (0x04, sp), x
; genPointerGet
ldw x, (0x04, sp)
ld a, (x)
; genCpl
push a
Sstm8s_gpio$GPIO_Init$13 ==.
ld a, (0x0b, sp)
cpl a
ld (0x04, sp), a
pop a
Sstm8s_gpio$GPIO_Init$14 ==.
; genAnd
and a, (0x03, sp)
; genPointerSet
ldw x, (0x04, sp)
ld (x), a
Sstm8s_gpio$GPIO_Init$15 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 98: GPIOx->DDR |= (uint8_t)GPIO_Pin;
; genPlus
ldw x, y
incw x
incw x
ldw (0x01, sp), x
Sstm8s_gpio$GPIO_Init$16 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 87: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
; genAnd
tnz (0x0b, sp)
jrmi 00131$
jp 00105$
00131$:
; skipping generated iCode
Sstm8s_gpio$GPIO_Init$17 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 91: GPIOx->ODR |= (uint8_t)GPIO_Pin;
; genPointerGet
ld a, (y)
Sstm8s_gpio$GPIO_Init$18 ==.
Sstm8s_gpio$GPIO_Init$19 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 89: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
; genAnd
push a
Sstm8s_gpio$GPIO_Init$20 ==.
ld a, (0x0c, sp)
bcp a, #0x10
pop a
Sstm8s_gpio$GPIO_Init$21 ==.
jrne 00132$
jp 00102$
00132$:
; skipping generated iCode
Sstm8s_gpio$GPIO_Init$22 ==.
Sstm8s_gpio$GPIO_Init$23 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 91: GPIOx->ODR |= (uint8_t)GPIO_Pin;
; genOr
or a, (0x0a, sp)
; genPointerSet
ld (y), a
Sstm8s_gpio$GPIO_Init$24 ==.
; genGoto
jp 00103$
; genLabel
00102$:
Sstm8s_gpio$GPIO_Init$25 ==.
Sstm8s_gpio$GPIO_Init$26 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 95: GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
; genAnd
and a, (0x03, sp)
; genPointerSet
ld (y), a
Sstm8s_gpio$GPIO_Init$27 ==.
; genLabel
00103$:
Sstm8s_gpio$GPIO_Init$28 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 98: GPIOx->DDR |= (uint8_t)GPIO_Pin;
; genPointerGet
ldw x, (0x01, sp)
ld a, (x)
; genOr
or a, (0x0a, sp)
; genPointerSet
ldw x, (0x01, sp)
ld (x), a
Sstm8s_gpio$GPIO_Init$29 ==.
; genGoto
jp 00106$
; genLabel
00105$:
Sstm8s_gpio$GPIO_Init$30 ==.
Sstm8s_gpio$GPIO_Init$31 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 103: GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
; genPointerGet
ldw x, (0x01, sp)
ld a, (x)
; genAnd
and a, (0x03, sp)
; genPointerSet
ldw x, (0x01, sp)
ld (x), a
Sstm8s_gpio$GPIO_Init$32 ==.
; genLabel
00106$:
Sstm8s_gpio$GPIO_Init$33 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 112: GPIOx->CR1 |= (uint8_t)GPIO_Pin;
; genPlus
ldw x, y
addw x, #0x0003
; genPointerGet
ld a, (x)
Sstm8s_gpio$GPIO_Init$34 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 110: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
; genAnd
push a
Sstm8s_gpio$GPIO_Init$35 ==.
ld a, (0x0c, sp)
bcp a, #0x40
pop a
Sstm8s_gpio$GPIO_Init$36 ==.
jrne 00133$
jp 00108$
00133$:
; skipping generated iCode
Sstm8s_gpio$GPIO_Init$37 ==.
Sstm8s_gpio$GPIO_Init$38 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 112: GPIOx->CR1 |= (uint8_t)GPIO_Pin;
; genOr
or a, (0x0a, sp)
; genPointerSet
ld (x), a
Sstm8s_gpio$GPIO_Init$39 ==.
; genGoto
jp 00109$
; genLabel
00108$:
Sstm8s_gpio$GPIO_Init$40 ==.
Sstm8s_gpio$GPIO_Init$41 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 116: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
; genAnd
and a, (0x03, sp)
; genPointerSet
ld (x), a
Sstm8s_gpio$GPIO_Init$42 ==.
; genLabel
00109$:
Sstm8s_gpio$GPIO_Init$43 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 81: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
; genPointerGet
ldw x, (0x04, sp)
ld a, (x)
Sstm8s_gpio$GPIO_Init$44 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 123: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
; genAnd
push a
Sstm8s_gpio$GPIO_Init$45 ==.
ld a, (0x0c, sp)
bcp a, #0x20
pop a
Sstm8s_gpio$GPIO_Init$46 ==.
jrne 00134$
jp 00111$
00134$:
; skipping generated iCode
Sstm8s_gpio$GPIO_Init$47 ==.
Sstm8s_gpio$GPIO_Init$48 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 125: GPIOx->CR2 |= (uint8_t)GPIO_Pin;
; genOr
or a, (0x0a, sp)
; genPointerSet
ldw x, (0x04, sp)
ld (x), a
Sstm8s_gpio$GPIO_Init$49 ==.
; genGoto
jp 00113$
; genLabel
00111$:
Sstm8s_gpio$GPIO_Init$50 ==.
Sstm8s_gpio$GPIO_Init$51 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 129: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
; genAnd
and a, (0x03, sp)
; genPointerSet
ldw x, (0x04, sp)
ld (x), a
Sstm8s_gpio$GPIO_Init$52 ==.
; genLabel
00113$:
Sstm8s_gpio$GPIO_Init$53 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 131: }
; genEndFunction
addw sp, #5
Sstm8s_gpio$GPIO_Init$54 ==.
Sstm8s_gpio$GPIO_Init$55 ==.
XG$GPIO_Init$0$0 ==.
ret
Sstm8s_gpio$GPIO_Init$56 ==.
Sstm8s_gpio$GPIO_Write$57 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 141: void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal)
; genLabel
; -----------------------------------------
; function GPIO_Write
; -----------------------------------------
; Register assignment is optimal.
; Stack space usage: 0 bytes.
_GPIO_Write:
Sstm8s_gpio$GPIO_Write$58 ==.
Sstm8s_gpio$GPIO_Write$59 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 143: GPIOx->ODR = PortVal;
; genAssign
ldw x, (0x03, sp)
; genPointerSet
ld a, (0x05, sp)
ld (x), a
; genLabel
00101$:
Sstm8s_gpio$GPIO_Write$60 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 144: }
; genEndFunction
Sstm8s_gpio$GPIO_Write$61 ==.
XG$GPIO_Write$0$0 ==.
ret
Sstm8s_gpio$GPIO_Write$62 ==.
Sstm8s_gpio$GPIO_WriteHigh$63 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 154: void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
; genLabel
; -----------------------------------------
; function GPIO_WriteHigh
; -----------------------------------------
; Register assignment is optimal.
; Stack space usage: 0 bytes.
_GPIO_WriteHigh:
Sstm8s_gpio$GPIO_WriteHigh$64 ==.
Sstm8s_gpio$GPIO_WriteHigh$65 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 156: GPIOx->ODR |= (uint8_t)PortPins;
; genAssign
ldw x, (0x03, sp)
; genPointerGet
ld a, (x)
; genOr
or a, (0x05, sp)
; genPointerSet
ld (x), a
; genLabel
00101$:
Sstm8s_gpio$GPIO_WriteHigh$66 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 157: }
; genEndFunction
Sstm8s_gpio$GPIO_WriteHigh$67 ==.
XG$GPIO_WriteHigh$0$0 ==.
ret
Sstm8s_gpio$GPIO_WriteHigh$68 ==.
Sstm8s_gpio$GPIO_WriteLow$69 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 167: void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
; genLabel
; -----------------------------------------
; function GPIO_WriteLow
; -----------------------------------------
; Register assignment is optimal.
; Stack space usage: 1 bytes.
_GPIO_WriteLow:
Sstm8s_gpio$GPIO_WriteLow$70 ==.
push a
Sstm8s_gpio$GPIO_WriteLow$71 ==.
Sstm8s_gpio$GPIO_WriteLow$72 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 169: GPIOx->ODR &= (uint8_t)(~PortPins);
; genAssign
ldw x, (0x04, sp)
; genPointerGet
ld a, (x)
ld (0x01, sp), a
; genCpl
ld a, (0x06, sp)
cpl a
; genAnd
and a, (0x01, sp)
; genPointerSet
ld (x), a
; genLabel
00101$:
Sstm8s_gpio$GPIO_WriteLow$73 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 170: }
; genEndFunction
pop a
Sstm8s_gpio$GPIO_WriteLow$74 ==.
Sstm8s_gpio$GPIO_WriteLow$75 ==.
XG$GPIO_WriteLow$0$0 ==.
ret
Sstm8s_gpio$GPIO_WriteLow$76 ==.
Sstm8s_gpio$GPIO_WriteReverse$77 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 180: void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)
; genLabel
; -----------------------------------------
; function GPIO_WriteReverse
; -----------------------------------------
; Register assignment is optimal.
; Stack space usage: 0 bytes.
_GPIO_WriteReverse:
Sstm8s_gpio$GPIO_WriteReverse$78 ==.
Sstm8s_gpio$GPIO_WriteReverse$79 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 182: GPIOx->ODR ^= (uint8_t)PortPins;
; genAssign
ldw x, (0x03, sp)
; genPointerGet
ld a, (x)
; genXor
xor a, (0x05, sp)
; genPointerSet
ld (x), a
; genLabel
00101$:
Sstm8s_gpio$GPIO_WriteReverse$80 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 183: }
; genEndFunction
Sstm8s_gpio$GPIO_WriteReverse$81 ==.
XG$GPIO_WriteReverse$0$0 ==.
ret
Sstm8s_gpio$GPIO_WriteReverse$82 ==.
Sstm8s_gpio$GPIO_ReadOutputData$83 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 191: uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
; genLabel
; -----------------------------------------
; function GPIO_ReadOutputData
; -----------------------------------------
; Register assignment is optimal.
; Stack space usage: 0 bytes.
_GPIO_ReadOutputData:
Sstm8s_gpio$GPIO_ReadOutputData$84 ==.
Sstm8s_gpio$GPIO_ReadOutputData$85 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 193: return ((uint8_t)GPIOx->ODR);
; genAssign
ldw x, (0x03, sp)
; genPointerGet
ld a, (x)
; genReturn
; genLabel
00101$:
Sstm8s_gpio$GPIO_ReadOutputData$86 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 194: }
; genEndFunction
Sstm8s_gpio$GPIO_ReadOutputData$87 ==.
XG$GPIO_ReadOutputData$0$0 ==.
ret
Sstm8s_gpio$GPIO_ReadOutputData$88 ==.
Sstm8s_gpio$GPIO_ReadInputData$89 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 202: uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
; genLabel
; -----------------------------------------
; function GPIO_ReadInputData
; -----------------------------------------
; Register assignment might be sub-optimal.
; Stack space usage: 0 bytes.
_GPIO_ReadInputData:
Sstm8s_gpio$GPIO_ReadInputData$90 ==.
Sstm8s_gpio$GPIO_ReadInputData$91 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 204: return ((uint8_t)GPIOx->IDR);
; genAssign
ldw x, (0x03, sp)
; genAssign
; genPointerGet
ld a, (0x1, x)
; genReturn
; genLabel
00101$:
Sstm8s_gpio$GPIO_ReadInputData$92 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 205: }
; genEndFunction
Sstm8s_gpio$GPIO_ReadInputData$93 ==.
XG$GPIO_ReadInputData$0$0 ==.
ret
Sstm8s_gpio$GPIO_ReadInputData$94 ==.
Sstm8s_gpio$GPIO_ReadInputPin$95 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 213: BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
; genLabel
; -----------------------------------------
; function GPIO_ReadInputPin
; -----------------------------------------
; Register assignment might be sub-optimal.
; Stack space usage: 0 bytes.
_GPIO_ReadInputPin:
Sstm8s_gpio$GPIO_ReadInputPin$96 ==.
Sstm8s_gpio$GPIO_ReadInputPin$97 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 215: return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
; genAssign
ldw x, (0x03, sp)
; genAssign
; genPointerGet
ld a, (0x1, x)
; genAnd
and a, (0x05, sp)
; genReturn
; genLabel
00101$:
Sstm8s_gpio$GPIO_ReadInputPin$98 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 216: }
; genEndFunction
Sstm8s_gpio$GPIO_ReadInputPin$99 ==.
XG$GPIO_ReadInputPin$0$0 ==.
ret
Sstm8s_gpio$GPIO_ReadInputPin$100 ==.
Sstm8s_gpio$GPIO_ExternalPullUpConfig$101 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 225: void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
; genLabel
; -----------------------------------------
; function GPIO_ExternalPullUpConfig
; -----------------------------------------
; Register assignment might be sub-optimal.
; Stack space usage: 1 bytes.
_GPIO_ExternalPullUpConfig:
Sstm8s_gpio$GPIO_ExternalPullUpConfig$102 ==.
push a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$103 ==.
Sstm8s_gpio$GPIO_ExternalPullUpConfig$104 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 233: GPIOx->CR1 |= (uint8_t)GPIO_Pin;
; genAssign
ldw x, (0x04, sp)
; genPlus
addw x, #0x0003
; genPointerGet
ld a, (x)
Sstm8s_gpio$GPIO_ExternalPullUpConfig$105 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 231: if (NewState != DISABLE) /* External Pull-Up Set*/
; genIfx
tnz (0x07, sp)
jrne 00110$
jp 00102$
00110$:
Sstm8s_gpio$GPIO_ExternalPullUpConfig$106 ==.
Sstm8s_gpio$GPIO_ExternalPullUpConfig$107 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 233: GPIOx->CR1 |= (uint8_t)GPIO_Pin;
; genOr
or a, (0x06, sp)
; genPointerSet
ld (x), a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$108 ==.
; genGoto
jp 00104$
; genLabel
00102$:
Sstm8s_gpio$GPIO_ExternalPullUpConfig$109 ==.
Sstm8s_gpio$GPIO_ExternalPullUpConfig$110 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 236: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
; genCpl
push a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$111 ==.
ld a, (0x07, sp)
cpl a
ld (0x02, sp), a
pop a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$112 ==.
; genAnd
and a, (0x01, sp)
; genPointerSet
ld (x), a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$113 ==.
; genLabel
00104$:
Sstm8s_gpio$GPIO_ExternalPullUpConfig$114 ==.
; ./STM8S_StdPeriph_Driver/src/stm8s_gpio.c: 238: }
; genEndFunction
pop a
Sstm8s_gpio$GPIO_ExternalPullUpConfig$115 ==.
Sstm8s_gpio$GPIO_ExternalPullUpConfig$116 ==.
XG$GPIO_ExternalPullUpConfig$0$0 ==.
ret
Sstm8s_gpio$GPIO_ExternalPullUpConfig$117 ==.
.area CODE
.area INITIALIZER
.area CABS (ABS)
.area .debug_line (NOLOAD)
.dw 0,Ldebug_line_end-Ldebug_line_start
Ldebug_line_start:
.dw 2
.dw 0,Ldebug_line_stmt-6-Ldebug_line_start
.db 1
.db 1
.db -5
.db 15
.db 10
.db 0
.db 1
.db 1
.db 1
.db 1
.db 0
.db 0
.db 0
.db 1
.ascii "/usr/bin/../share/sdcc/include/stm8"
.db 0
.ascii "/usr/share/sdcc/include/stm8"
.db 0
.ascii "/usr/bin/../share/sdcc/include"
.db 0
.ascii "/usr/share/sdcc/include"
.db 0
.db 0
.ascii "./STM8S_StdPeriph_Driver/src/stm8s_gpio.c"
.db 0
.uleb128 0
.uleb128 0
.uleb128 0
.db 0
Ldebug_line_stmt:
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_DeInit$0)
.db 3
.sleb128 52
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_DeInit$2-Sstm8s_gpio$GPIO_DeInit$0
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_DeInit$3-Sstm8s_gpio$GPIO_DeInit$2
.db 3
.sleb128 1
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_DeInit$4-Sstm8s_gpio$GPIO_DeInit$3
.db 3
.sleb128 1
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_DeInit$5-Sstm8s_gpio$GPIO_DeInit$4
.db 3
.sleb128 1
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_DeInit$6-Sstm8s_gpio$GPIO_DeInit$5
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_DeInit$7-Sstm8s_gpio$GPIO_DeInit$6
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_Init$9)
.db 3
.sleb128 70
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$12-Sstm8s_gpio$GPIO_Init$9
.db 3
.sleb128 10
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$15-Sstm8s_gpio$GPIO_Init$12
.db 3
.sleb128 17
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$16-Sstm8s_gpio$GPIO_Init$15
.db 3
.sleb128 -11
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$17-Sstm8s_gpio$GPIO_Init$16
.db 3
.sleb128 4
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$19-Sstm8s_gpio$GPIO_Init$17
.db 3
.sleb128 -2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$23-Sstm8s_gpio$GPIO_Init$19
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$26-Sstm8s_gpio$GPIO_Init$23
.db 3
.sleb128 4
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$28-Sstm8s_gpio$GPIO_Init$26
.db 3
.sleb128 3
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$31-Sstm8s_gpio$GPIO_Init$28
.db 3
.sleb128 5
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$33-Sstm8s_gpio$GPIO_Init$31
.db 3
.sleb128 9
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$34-Sstm8s_gpio$GPIO_Init$33
.db 3
.sleb128 -2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$38-Sstm8s_gpio$GPIO_Init$34
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$41-Sstm8s_gpio$GPIO_Init$38
.db 3
.sleb128 4
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$43-Sstm8s_gpio$GPIO_Init$41
.db 3
.sleb128 -35
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$44-Sstm8s_gpio$GPIO_Init$43
.db 3
.sleb128 42
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$48-Sstm8s_gpio$GPIO_Init$44
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$51-Sstm8s_gpio$GPIO_Init$48
.db 3
.sleb128 4
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Init$53-Sstm8s_gpio$GPIO_Init$51
.db 3
.sleb128 2
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_Init$55-Sstm8s_gpio$GPIO_Init$53
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_Write$57)
.db 3
.sleb128 140
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Write$59-Sstm8s_gpio$GPIO_Write$57
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_Write$60-Sstm8s_gpio$GPIO_Write$59
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_Write$61-Sstm8s_gpio$GPIO_Write$60
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_WriteHigh$63)
.db 3
.sleb128 153
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteHigh$65-Sstm8s_gpio$GPIO_WriteHigh$63
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteHigh$66-Sstm8s_gpio$GPIO_WriteHigh$65
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_WriteHigh$67-Sstm8s_gpio$GPIO_WriteHigh$66
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$69)
.db 3
.sleb128 166
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteLow$72-Sstm8s_gpio$GPIO_WriteLow$69
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteLow$73-Sstm8s_gpio$GPIO_WriteLow$72
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_WriteLow$75-Sstm8s_gpio$GPIO_WriteLow$73
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_WriteReverse$77)
.db 3
.sleb128 179
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteReverse$79-Sstm8s_gpio$GPIO_WriteReverse$77
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_WriteReverse$80-Sstm8s_gpio$GPIO_WriteReverse$79
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_WriteReverse$81-Sstm8s_gpio$GPIO_WriteReverse$80
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_ReadOutputData$83)
.db 3
.sleb128 190
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadOutputData$85-Sstm8s_gpio$GPIO_ReadOutputData$83
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadOutputData$86-Sstm8s_gpio$GPIO_ReadOutputData$85
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_ReadOutputData$87-Sstm8s_gpio$GPIO_ReadOutputData$86
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_ReadInputData$89)
.db 3
.sleb128 201
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadInputData$91-Sstm8s_gpio$GPIO_ReadInputData$89
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadInputData$92-Sstm8s_gpio$GPIO_ReadInputData$91
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_ReadInputData$93-Sstm8s_gpio$GPIO_ReadInputData$92
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_ReadInputPin$95)
.db 3
.sleb128 212
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadInputPin$97-Sstm8s_gpio$GPIO_ReadInputPin$95
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ReadInputPin$98-Sstm8s_gpio$GPIO_ReadInputPin$97
.db 3
.sleb128 1
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_ReadInputPin$99-Sstm8s_gpio$GPIO_ReadInputPin$98
.db 0
.uleb128 1
.db 1
.db 0
.uleb128 5
.db 2
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$101)
.db 3
.sleb128 224
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ExternalPullUpConfig$104-Sstm8s_gpio$GPIO_ExternalPullUpConfig$101
.db 3
.sleb128 8
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ExternalPullUpConfig$105-Sstm8s_gpio$GPIO_ExternalPullUpConfig$104
.db 3
.sleb128 -2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ExternalPullUpConfig$107-Sstm8s_gpio$GPIO_ExternalPullUpConfig$105
.db 3
.sleb128 2
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ExternalPullUpConfig$110-Sstm8s_gpio$GPIO_ExternalPullUpConfig$107
.db 3
.sleb128 3
.db 1
.db 9
.dw Sstm8s_gpio$GPIO_ExternalPullUpConfig$114-Sstm8s_gpio$GPIO_ExternalPullUpConfig$110
.db 3
.sleb128 2
.db 1
.db 9
.dw 1+Sstm8s_gpio$GPIO_ExternalPullUpConfig$116-Sstm8s_gpio$GPIO_ExternalPullUpConfig$114
.db 0
.uleb128 1
.db 1
Ldebug_line_end:
.area .debug_loc (NOLOAD)
Ldebug_loc_start:
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$115)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$117)
.dw 2
.db 120
.sleb128 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$112)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$115)
.dw 2
.db 120
.sleb128 2
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$111)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$112)
.dw 2
.db 120
.sleb128 3
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$103)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$111)
.dw 2
.db 120
.sleb128 2
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$102)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$103)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_ReadInputPin$96)
.dw 0,(Sstm8s_gpio$GPIO_ReadInputPin$100)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_ReadInputData$90)
.dw 0,(Sstm8s_gpio$GPIO_ReadInputData$94)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_ReadOutputData$84)
.dw 0,(Sstm8s_gpio$GPIO_ReadOutputData$88)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_WriteReverse$78)
.dw 0,(Sstm8s_gpio$GPIO_WriteReverse$82)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$74)
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$76)
.dw 2
.db 120
.sleb128 1
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$71)
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$74)
.dw 2
.db 120
.sleb128 2
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$70)
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$71)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_WriteHigh$64)
.dw 0,(Sstm8s_gpio$GPIO_WriteHigh$68)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_Write$58)
.dw 0,(Sstm8s_gpio$GPIO_Write$62)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_Init$54)
.dw 0,(Sstm8s_gpio$GPIO_Init$56)
.dw 2
.db 120
.sleb128 1
.dw 0,(Sstm8s_gpio$GPIO_Init$46)
.dw 0,(Sstm8s_gpio$GPIO_Init$54)
.dw 2
.db 120
.sleb128 6
.dw 0,(Sstm8s_gpio$GPIO_Init$45)
.dw 0,(Sstm8s_gpio$GPIO_Init$46)
.dw 2
.db 120
.sleb128 7
.dw 0,(Sstm8s_gpio$GPIO_Init$36)
.dw 0,(Sstm8s_gpio$GPIO_Init$45)
.dw 2
.db 120
.sleb128 6
.dw 0,(Sstm8s_gpio$GPIO_Init$35)
.dw 0,(Sstm8s_gpio$GPIO_Init$36)
.dw 2
.db 120
.sleb128 7
.dw 0,(Sstm8s_gpio$GPIO_Init$21)
.dw 0,(Sstm8s_gpio$GPIO_Init$35)
.dw 2
.db 120
.sleb128 6
.dw 0,(Sstm8s_gpio$GPIO_Init$20)
.dw 0,(Sstm8s_gpio$GPIO_Init$21)
.dw 2
.db 120
.sleb128 7
.dw 0,(Sstm8s_gpio$GPIO_Init$14)
.dw 0,(Sstm8s_gpio$GPIO_Init$20)
.dw 2
.db 120
.sleb128 6
.dw 0,(Sstm8s_gpio$GPIO_Init$13)
.dw 0,(Sstm8s_gpio$GPIO_Init$14)
.dw 2
.db 120
.sleb128 7
.dw 0,(Sstm8s_gpio$GPIO_Init$11)
.dw 0,(Sstm8s_gpio$GPIO_Init$13)
.dw 2
.db 120
.sleb128 6
.dw 0,(Sstm8s_gpio$GPIO_Init$10)
.dw 0,(Sstm8s_gpio$GPIO_Init$11)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.dw 0,(Sstm8s_gpio$GPIO_DeInit$1)
.dw 0,(Sstm8s_gpio$GPIO_DeInit$8)
.dw 2
.db 120
.sleb128 1
.dw 0,0
.dw 0,0
.area .debug_abbrev (NOLOAD)
Ldebug_abbrev:
.uleb128 6
.uleb128 15
.db 0
.uleb128 11
.uleb128 11
.uleb128 73
.uleb128 19
.uleb128 0
.uleb128 0
.uleb128 4
.uleb128 53
.db 0
.uleb128 73
.uleb128 19
.uleb128 0
.uleb128 0
.uleb128 7
.uleb128 5
.db 0
.uleb128 2
.uleb128 10
.uleb128 3
.uleb128 8
.uleb128 73
.uleb128 19
.uleb128 0
.uleb128 0
.uleb128 2
.uleb128 46
.db 1
.uleb128 1
.uleb128 19
.uleb128 3
.uleb128 8
.uleb128 17
.uleb128 1
.uleb128 18
.uleb128 1
.uleb128 63
.uleb128 12
.uleb128 64
.uleb128 6
.uleb128 0
.uleb128 0
.uleb128 11
.uleb128 46
.db 1
.uleb128 1
.uleb128 19
.uleb128 3
.uleb128 8
.uleb128 17
.uleb128 1
.uleb128 18
.uleb128 1
.uleb128 63
.uleb128 12
.uleb128 64
.uleb128 6
.uleb128 73
.uleb128 19
.uleb128 0
.uleb128 0
.uleb128 1
.uleb128 17
.db 1
.uleb128 3
.uleb128 8
.uleb128 16
.uleb128 6
.uleb128 19
.uleb128 11
.uleb128 37
.uleb128 8
.uleb128 0
.uleb128 0
.uleb128 5
.uleb128 13
.db 0
.uleb128 3
.uleb128 8
.uleb128 56
.uleb128 10
.uleb128 73
.uleb128 19
.uleb128 0
.uleb128 0
.uleb128 10
.uleb128 11
.db 0
.uleb128 17
.uleb128 1
.uleb128 18
.uleb128 1
.uleb128 0
.uleb128 0
.uleb128 12
.uleb128 46
.db 1
.uleb128 3
.uleb128 8
.uleb128 17
.uleb128 1
.uleb128 18
.uleb128 1
.uleb128 63
.uleb128 12
.uleb128 64
.uleb128 6
.uleb128 0
.uleb128 0
.uleb128 9
.uleb128 11
.db 1
.uleb128 1
.uleb128 19
.uleb128 17
.uleb128 1
.uleb128 18
.uleb128 1
.uleb128 0
.uleb128 0
.uleb128 3
.uleb128 19
.db 1
.uleb128 1
.uleb128 19
.uleb128 3
.uleb128 8
.uleb128 11
.uleb128 11
.uleb128 0
.uleb128 0
.uleb128 8
.uleb128 36
.db 0
.uleb128 3
.uleb128 8
.uleb128 11
.uleb128 11
.uleb128 62
.uleb128 11
.uleb128 0
.uleb128 0
.uleb128 0
.area .debug_info (NOLOAD)
.dw 0,Ldebug_info_end-Ldebug_info_start
Ldebug_info_start:
.dw 2
.dw 0,(Ldebug_abbrev)
.db 4
.uleb128 1
.ascii "./STM8S_StdPeriph_Driver/src/stm8s_gpio.c"
.db 0
.dw 0,(Ldebug_line_start+-4)
.db 1
.ascii "SDCC version 3.7.0 #10231"
.db 0
.uleb128 2
.dw 0,220
.ascii "GPIO_DeInit"
.db 0
.dw 0,(_GPIO_DeInit)
.dw 0,(XG$GPIO_DeInit$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+372)
.uleb128 3
.dw 0,199
.ascii "GPIO_struct"
.db 0
.db 5
.uleb128 4
.dw 0,220
.uleb128 5
.ascii "ODR"
.db 0
.db 2
.db 35
.uleb128 0
.dw 0,133
.uleb128 5
.ascii "IDR"
.db 0
.db 2
.db 35
.uleb128 1
.dw 0,133
.uleb128 5
.ascii "DDR"
.db 0
.db 2
.db 35
.uleb128 2
.dw 0,133
.uleb128 5
.ascii "CR1"
.db 0
.db 2
.db 35
.uleb128 3
.dw 0,133
.uleb128 5
.ascii "CR2"
.db 0
.db 2
.db 35
.uleb128 4
.dw 0,133
.uleb128 0
.uleb128 6
.db 2
.dw 0,115
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 0
.uleb128 8
.ascii "unsigned char"
.db 0
.db 1
.db 8
.uleb128 2
.dw 0,392
.ascii "GPIO_Init"
.db 0
.dw 0,(_GPIO_Init)
.dw 0,(XG$GPIO_Init$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+232)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "GPIO_Pin"
.db 0
.dw 0,392
.uleb128 7
.db 2
.db 145
.sleb128 5
.ascii "GPIO_Mode"
.db 0
.dw 0,392
.uleb128 9
.dw 0,346
.dw 0,(Sstm8s_gpio$GPIO_Init$18)
.dw 0,(Sstm8s_gpio$GPIO_Init$29)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$22)
.dw 0,(Sstm8s_gpio$GPIO_Init$24)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$25)
.dw 0,(Sstm8s_gpio$GPIO_Init$27)
.uleb128 0
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$30)
.dw 0,(Sstm8s_gpio$GPIO_Init$32)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$37)
.dw 0,(Sstm8s_gpio$GPIO_Init$39)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$40)
.dw 0,(Sstm8s_gpio$GPIO_Init$42)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$47)
.dw 0,(Sstm8s_gpio$GPIO_Init$49)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_Init$50)
.dw 0,(Sstm8s_gpio$GPIO_Init$52)
.uleb128 0
.uleb128 8
.ascii "unsigned char"
.db 0
.db 1
.db 8
.uleb128 2
.dw 0,469
.ascii "GPIO_Write"
.db 0
.dw 0,(_GPIO_Write)
.dw 0,(XG$GPIO_Write$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+212)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "PortVal"
.db 0
.dw 0,392
.uleb128 0
.uleb128 2
.dw 0,534
.ascii "GPIO_WriteHigh"
.db 0
.dw 0,(_GPIO_WriteHigh)
.dw 0,(XG$GPIO_WriteHigh$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+192)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "PortPins"
.db 0
.dw 0,392
.uleb128 0
.uleb128 2
.dw 0,598
.ascii "GPIO_WriteLow"
.db 0
.dw 0,(_GPIO_WriteLow)
.dw 0,(XG$GPIO_WriteLow$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+148)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "PortPins"
.db 0
.dw 0,392
.uleb128 0
.uleb128 2
.dw 0,666
.ascii "GPIO_WriteReverse"
.db 0
.dw 0,(_GPIO_WriteReverse)
.dw 0,(XG$GPIO_WriteReverse$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+128)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "PortPins"
.db 0
.dw 0,392
.uleb128 0
.uleb128 11
.dw 0,723
.ascii "GPIO_ReadOutputData"
.db 0
.dw 0,(_GPIO_ReadOutputData)
.dw 0,(XG$GPIO_ReadOutputData$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+108)
.dw 0,392
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 0
.uleb128 11
.dw 0,779
.ascii "GPIO_ReadInputData"
.db 0
.dw 0,(_GPIO_ReadInputData)
.dw 0,(XG$GPIO_ReadInputData$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+88)
.dw 0,392
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 0
.uleb128 11
.dw 0,851
.ascii "GPIO_ReadInputPin"
.db 0
.dw 0,(_GPIO_ReadInputPin)
.dw 0,(XG$GPIO_ReadInputPin$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start+68)
.dw 0,392
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "GPIO_Pin"
.db 0
.dw 0,392
.uleb128 0
.uleb128 12
.ascii "GPIO_ExternalPullUpConfig"
.db 0
.dw 0,(_GPIO_ExternalPullUpConfig)
.dw 0,(XG$GPIO_ExternalPullUpConfig$0$0+1)
.db 1
.dw 0,(Ldebug_loc_start)
.uleb128 7
.db 2
.db 145
.sleb128 2
.ascii "GPIOx"
.db 0
.dw 0,199
.uleb128 7
.db 2
.db 145
.sleb128 4
.ascii "GPIO_Pin"
.db 0
.dw 0,392
.uleb128 7
.db 2
.db 145
.sleb128 5
.ascii "NewState"
.db 0
.dw 0,392
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$106)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$108)
.uleb128 10
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$109)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$113)
.uleb128 0
.uleb128 0
.uleb128 0
.uleb128 0
Ldebug_info_end:
.area .debug_pubnames (NOLOAD)
.dw 0,Ldebug_pubnames_end-Ldebug_pubnames_start
Ldebug_pubnames_start:
.dw 2
.dw 0,(Ldebug_info_start-4)
.dw 0,4+Ldebug_info_end-Ldebug_info_start
.dw 0,85
.ascii "GPIO_DeInit"
.db 0
.dw 0,237
.ascii "GPIO_Init"
.db 0
.dw 0,409
.ascii "GPIO_Write"
.db 0
.dw 0,469
.ascii "GPIO_WriteHigh"
.db 0
.dw 0,534
.ascii "GPIO_WriteLow"
.db 0
.dw 0,598
.ascii "GPIO_WriteReverse"
.db 0
.dw 0,666
.ascii "GPIO_ReadOutputData"
.db 0
.dw 0,723
.ascii "GPIO_ReadInputData"
.db 0
.dw 0,779
.ascii "GPIO_ReadInputPin"
.db 0
.dw 0,851
.ascii "GPIO_ExternalPullUpConfig"
.db 0
.dw 0,0
Ldebug_pubnames_end:
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE0_end-Ldebug_CIE0_start
Ldebug_CIE0_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE0_end:
.dw 0,47
.dw 0,(Ldebug_CIE0_start-4)
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$102) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_ExternalPullUpConfig$117-Sstm8s_gpio$GPIO_ExternalPullUpConfig$102
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$102)
.db 14
.uleb128 2
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$103)
.db 14
.uleb128 3
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$111)
.db 14
.uleb128 4
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$112)
.db 14
.uleb128 3
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ExternalPullUpConfig$115)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE1_end-Ldebug_CIE1_start
Ldebug_CIE1_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE1_end:
.dw 0,19
.dw 0,(Ldebug_CIE1_start-4)
.dw 0,(Sstm8s_gpio$GPIO_ReadInputPin$96) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_ReadInputPin$100-Sstm8s_gpio$GPIO_ReadInputPin$96
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ReadInputPin$96)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE2_end-Ldebug_CIE2_start
Ldebug_CIE2_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE2_end:
.dw 0,19
.dw 0,(Ldebug_CIE2_start-4)
.dw 0,(Sstm8s_gpio$GPIO_ReadInputData$90) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_ReadInputData$94-Sstm8s_gpio$GPIO_ReadInputData$90
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ReadInputData$90)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE3_end-Ldebug_CIE3_start
Ldebug_CIE3_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE3_end:
.dw 0,19
.dw 0,(Ldebug_CIE3_start-4)
.dw 0,(Sstm8s_gpio$GPIO_ReadOutputData$84) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_ReadOutputData$88-Sstm8s_gpio$GPIO_ReadOutputData$84
.db 1
.dw 0,(Sstm8s_gpio$GPIO_ReadOutputData$84)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE4_end-Ldebug_CIE4_start
Ldebug_CIE4_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE4_end:
.dw 0,19
.dw 0,(Ldebug_CIE4_start-4)
.dw 0,(Sstm8s_gpio$GPIO_WriteReverse$78) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_WriteReverse$82-Sstm8s_gpio$GPIO_WriteReverse$78
.db 1
.dw 0,(Sstm8s_gpio$GPIO_WriteReverse$78)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE5_end-Ldebug_CIE5_start
Ldebug_CIE5_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE5_end:
.dw 0,33
.dw 0,(Ldebug_CIE5_start-4)
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$70) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_WriteLow$76-Sstm8s_gpio$GPIO_WriteLow$70
.db 1
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$70)
.db 14
.uleb128 2
.db 1
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$71)
.db 14
.uleb128 3
.db 1
.dw 0,(Sstm8s_gpio$GPIO_WriteLow$74)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE6_end-Ldebug_CIE6_start
Ldebug_CIE6_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE6_end:
.dw 0,19
.dw 0,(Ldebug_CIE6_start-4)
.dw 0,(Sstm8s_gpio$GPIO_WriteHigh$64) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_WriteHigh$68-Sstm8s_gpio$GPIO_WriteHigh$64
.db 1
.dw 0,(Sstm8s_gpio$GPIO_WriteHigh$64)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE7_end-Ldebug_CIE7_start
Ldebug_CIE7_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE7_end:
.dw 0,19
.dw 0,(Ldebug_CIE7_start-4)
.dw 0,(Sstm8s_gpio$GPIO_Write$58) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_Write$62-Sstm8s_gpio$GPIO_Write$58
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Write$58)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE8_end-Ldebug_CIE8_start
Ldebug_CIE8_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE8_end:
.dw 0,89
.dw 0,(Ldebug_CIE8_start-4)
.dw 0,(Sstm8s_gpio$GPIO_Init$10) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_Init$56-Sstm8s_gpio$GPIO_Init$10
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$10)
.db 14
.uleb128 2
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$11)
.db 14
.uleb128 7
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$13)
.db 14
.uleb128 8
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$14)
.db 14
.uleb128 7
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$20)
.db 14
.uleb128 8
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$21)
.db 14
.uleb128 7
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$35)
.db 14
.uleb128 8
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$36)
.db 14
.uleb128 7
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$45)
.db 14
.uleb128 8
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$46)
.db 14
.uleb128 7
.db 1
.dw 0,(Sstm8s_gpio$GPIO_Init$54)
.db 14
.uleb128 2
.area .debug_frame (NOLOAD)
.dw 0
.dw Ldebug_CIE9_end-Ldebug_CIE9_start
Ldebug_CIE9_start:
.dw 0xffff
.dw 0xffff
.db 1
.db 0
.uleb128 1
.sleb128 -1
.db 9
.db 12
.uleb128 8
.uleb128 2
.db 137
.uleb128 1
Ldebug_CIE9_end:
.dw 0,19
.dw 0,(Ldebug_CIE9_start-4)
.dw 0,(Sstm8s_gpio$GPIO_DeInit$1) ;initial loc
.dw 0,Sstm8s_gpio$GPIO_DeInit$8-Sstm8s_gpio$GPIO_DeInit$1
.db 1
.dw 0,(Sstm8s_gpio$GPIO_DeInit$1)
.db 14
.uleb128 2
|
; utilises iprint and iprintLF in functions.asm
%include 'src/include/functions.asm'
SECTION .text
global _start
_start:
mov ecx, 0
nextNumber:
inc ecx
mov eax, ecx
call iprintLF
cmp ecx, 10
jne nextNumber
call quit |
; A309337: a(n) = n^3 if n odd, 3*n^3/4 if n even.
; 0,1,6,27,48,125,162,343,384,729,750,1331,1296,2197,2058,3375,3072,4913,4374,6859,6000,9261,7986,12167,10368,15625,13182,19683,16464,24389,20250,29791,24576,35937,29478,42875,34992,50653,41154,59319,48000,68921,55566,79507,63888,91125
pow $0,3
mov $1,$0
dif $1,2
add $1,$0
div $1,2
|
stx {m1}+3 |
; A091577: Poincaré series [or Poincare series] of the preprojective algebra of a Dynkin diagram of type E_6.
; 6,10,14,18,20,20,20,18,14,10,6,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
sub $0,2
mov $2,9
trn $2,$0
mov $3,$0
add $3,15
sub $3,$2
mul $2,$3
mov $0,$2
mov $2,7
lpb $0
div $0,$2
mov $2,1
lpe
mul $0,2
|
; A087290: Number of pairs of polynomials (f,g) in GF(3)[x] satisfying deg(f) <= n, deg(g) <= n and gcd(f,g) = 1.
; 8,56,488,4376,39368,354296,3188648,28697816,258280328,2324522936,20920706408,188286357656,1694577218888,15251194969976,137260754729768,1235346792567896,11118121133111048,100063090197999416,900567811781994728,8105110306037952536
mov $1,9
pow $1,$0
div $1,8
mul $1,48
add $1,8
mov $0,$1
|
#include <kernel/syscall.h>
; defined in idt.c
extern isr_handler
extern irq_handler
extern int_handler
isr_common_stub:
pusha ; pushes e[ds]i, e[bs]p, e[abcd]x
push ds
push es
push fs
push gs
mov ax, 0x10 ; load the kernel data segment descriptor
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov eax, esp
push eax
mov eax, isr_handler
call eax
mov esp, eax
pop gs
pop fs
pop es
pop ds
popa ; pops e[ds]i, e[bs]p, e[abcd]x
add esp, 8 ; cleans up the pushed error code and pushed ISR number
iret ; pops cs, eip, eflags, ss and esp
irq_common_stub:
pusha
push ds
push es
push fs
push gs
mov ax, 0x10 ; load the kernel data segment
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov eax, esp
push eax
mov eax, irq_handler
call eax ; a special call, preserves the 'eip' register
mov esp, eax
pop gs ; restore the data segments
pop fs
pop es
pop ds
popa
add esp, 8
iret
int_common_stub:
pusha
push ds
push es
push fs
push gs
mov ax, 0x10 ; load the kernel data segment
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov eax, esp
push eax
mov eax, int_handler
call eax ; a special call, preserves the 'eip' register
mov esp, eax
pop gs ; restore the data segments
pop fs
pop es
pop ds
popa
add esp, 8
iret
; DRY
; argument #1: the ISR number
%macro isr_noerr 1
global isr%1
isr%1:
push dword 0xbadc0de ; dummy error code
push dword %1
jmp isr_common_stub
%endmacro
; argument #1: the ISR number
%macro isr_err 1
global isr%1
isr%1:
push dword %1
jmp isr_common_stub
%endmacro
; argument #1: the IRQ number
; argument #2: the IDT gate it is mapped to
%macro irq 2
global irq%1
irq%1:
push dword 0xbadc0de ; dummy error code
push dword %2 ; num
jmp irq_common_stub
%endmacro
; software interrupts
; argument #1: the INT number
%macro swint 1
global int%1
int%1:
push dword 0x0badc0de ; dummy error code
push dword %1 ; num
jmp int_common_stub
%endmacro
isr_noerr 0
isr_noerr 1
isr_noerr 2
isr_noerr 3
isr_noerr 4
isr_noerr 5
isr_noerr 6
isr_noerr 7
isr_err 8
isr_noerr 9
isr_err 10
isr_err 11
isr_err 12
isr_err 13
isr_err 14
isr_noerr 15
isr_noerr 16
isr_noerr 17
isr_noerr 18
isr_noerr 19
isr_noerr 20
isr_noerr 21
isr_noerr 22
isr_noerr 23
isr_noerr 24
isr_noerr 25
isr_noerr 26
isr_noerr 27
isr_noerr 28
isr_noerr 29
isr_noerr 30
isr_noerr 31
irq 0, 32
irq 1, 33
irq 2, 34
irq 3, 35
irq 4, 36
irq 5, 37
irq 6, 38
irq 7, 39
irq 8, 40
irq 9, 41
irq 10, 42
irq 11, 43
irq 12, 44
irq 13, 45
irq 14, 46
irq 15, 47
; hm, defines?
swint 127 ; process scheduler
swint SYSCALL_RPLY_MSG_VECTOR ; syscall for replying to messages
swint SYSCALL_SEND_MSG_VECTOR ; syscall for sending messages
swint SYSCALL_RECV_MSG_VECTOR ; syscall for receiving messages
; vi: ft=nasm:ts=2:sw=2 expandtab
|
; A103424: E.g.f.: 1 + sinh(2*x).
; 1,2,0,8,0,32,0,128,0,512,0,2048,0,8192,0,32768,0,131072,0,524288,0,2097152,0,8388608,0,33554432,0,134217728,0,536870912,0,2147483648,0,8589934592,0,34359738368,0,137438953472,0,549755813888,0,2199023255552,0,8796093022208,0,35184372088832,0,140737488355328,0,562949953421312,0,2251799813685248,0,9007199254740992,0
mov $1,$0
mod $1,2
mul $1,2
pow $1,$0
|
#include <iostream>
using namespace std;
int main()
{
string line;
int vowels, consonants, digits, spaces;
vowels = consonants = digits = spaces = 0;
cout << "Enter a line of string: ";
getline(cin, line);
for(int i = 0; i < line.length(); ++i)
{
if(line[i]=='a' || line[i]=='e' || line[i]=='i' ||
line[i]=='o' || line[i]=='u' || line[i]=='A' ||
line[i]=='E' || line[i]=='I' || line[i]=='O' ||
line[i]=='U')
{
++vowels;
}
else if((line[i]>='a'&& line[i]<='z') || (line[i]>='A'&& line[i]<='Z'))
{
++consonants;
}
else if(line[i]>='0' && line[i]<='9')
{
++digits;
}
else if (line[i]==' ')
{
++spaces;
}
}
cout << "Vowels: " << vowels << endl;
cout << "Consonants: " << consonants << endl;
cout << "Digits: " << digits << endl;
cout << "White spaces: " << spaces << endl;
return 0;
} |
# /* **************************************************************************
# * *
# * (C) Copyright Paul Mensonides 2002.
# * Distributed under the Boost Software License, Version 1.0. (See
# * accompanying file LICENSE_1_0.txt or copy at
# * http://www.boost.org/LICENSE_1_0.txt)
# * *
# ************************************************************************** */
#
# /* See http://www.boost.org for most recent version. */
#
# ifndef BOOST_PREPROCESSOR_SELECTION_HPP
# define BOOST_PREPROCESSOR_SELECTION_HPP
#
# include <boost/preprocessor/selection/max.hpp>
# include <boost/preprocessor/selection/min.hpp>
#
# endif
|
; A134202: Number of rigid Hv-groups of order n.
; 1,5,13,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14
add $0,1
bin $0,2
mul $0,2
add $0,3
mul $0,2
lpb $0,1
mov $0,19
lpe
mov $1,$0
sub $1,5
|
.8086
.model small
.data
array db 01h, 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, 0ah
count db 0ah
avg dw ?
.code
start:
mov ax, @data
mov ds, ax
mov ax, 00h
lea si, array
mov cl, count
back: mov dl, [si]
mov dh, 00h
add ax, dx
inc si
dec cl
jnz back
div count
mov avg, ax
mov ah, 4ch
int 3h
end start
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.