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/*---------------- Search Box */
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{
display:block;
position:absolute;
left:10px;
width:20px;
height:19px;
background:url('search_l.png') no-repeat;
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display:block;
position:absolute;
width:20px;
height:19px;
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left:4px;
}
.right #MSearchSelect {
right:5px;
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display:block;
position:absolute;
height:19px;
background:url('search_m.png') repeat-x;
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position: absolute;
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/search/variables_10.html | HTML | apache-2.0 | 1,018 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/search/variables_10.js | JavaScript | apache-2.0 | 111 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/search/variables_11.html | HTML | apache-2.0 | 1,018 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/search/variables_12.html | HTML | apache-2.0 | 1,018 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/search/variables_15.html | HTML | apache-2.0 | 1,018 |
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Macros</h2></td></tr>
<tr class="memitem:ac4c70ccf71cc9a2b8bd39c85675760ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#ac4c70ccf71cc9a2b8bd39c85675760ae">USR_MODE</a>   0x10</td></tr>
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<tr class="memitem:ad53b2deac028f5b71d1cdddda17c4ea0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#ad53b2deac028f5b71d1cdddda17c4ea0">FIQ_MODE</a>   0x11</td></tr>
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<tr class="memitem:a312ff1d5550cc17c9907a153b04e0efa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#a312ff1d5550cc17c9907a153b04e0efa">SVC_MODE</a>   0x13</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:a773f98dc213f4c8c5953d3b8a6db6acc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#a773f98dc213f4c8c5953d3b8a6db6acc">Vectors</a> (void)</td></tr>
<tr class="memdesc:a773f98dc213f4c8c5953d3b8a6db6acc"><td class="mdescLeft"> </td><td class="mdescRight">Exception and Interrupt Handler Jumptable. <a href="#a773f98dc213f4c8c5953d3b8a6db6acc">More...</a><br/></td></tr>
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<tr class="memitem:ae7ee340978f5c25f52f0cad1457c6616"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#ae7ee340978f5c25f52f0cad1457c6616">Reset_Handler</a> (void)</td></tr>
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<tr class="memitem:a4e0c522c1bb26af24accaf20e6b87d12"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="startup__ARMCA9_8c.html#a4e0c522c1bb26af24accaf20e6b87d12">Default_Handler</a> (void)</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ABT_MODE   0x17</td>
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<td class="memname">#define FIQ_MODE   0x11</td>
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<td class="memname">#define SVC_MODE   0x13</td>
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<td class="memname">#define SYS_MODE   0x1F</td>
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<td class="memname">#define UND_MODE   0x1B</td>
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<td class="memname">#define USR_MODE   0x10</td>
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<td class="memname">void Default_Handler </td>
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<div class="title">Startup File startup_<device>.c </div> </div>
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<div class="contents">
<div class="textblock"><p>The <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> contains:</p>
<ul>
<li>Exception vectors of the Cortex-A Processor with weak functions that implement default routines.</li>
<li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li>
<li>The setup values for the various stack pointers, i.e. per exceptional mode and main stack.</li>
</ul>
<p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p>
<h1><a class="anchor" id="startup_c_sec"></a>
startup_Device.c Template File</h1>
<p>An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p>
<pre class="fragment">/******************************************************************************
* @file startup_<Device>.c
* @brief CMSIS Cortex-A Device Startup
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
/*----------------------------------------------------------------------------
Definitions
*----------------------------------------------------------------------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Vectors (void) __attribute__ ((section("RESET")));
void Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
__ASM void Vectors(void) {
IMPORT Undef_Handler
IMPORT SVC_Handler
IMPORT PAbt_Handler
IMPORT DAbt_Handler
IMPORT IRQ_Handler
IMPORT FIQ_Handler
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
}
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__ASM void Reset_Handler(void) {
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exceptional mode
IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
IMPORT |Image$$SVC_STACK$$ZI$$Limit|
IMPORT |Image$$ABT_STACK$$ZI$$Limit|
IMPORT |Image$$UND_STACK$$ZI$$Limit|
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
CPS #0x11
LDR SP, =|Image$$FIQ_STACK$$ZI$$Limit|
CPS #0x12
LDR SP, =|Image$$IRQ_STACK$$ZI$$Limit|
CPS #0x13
LDR SP, =|Image$$SVC_STACK$$ZI$$Limit|
CPS #0x17
LDR SP, =|Image$$ABT_STACK$$ZI$$Limit|
CPS #0x1B
LDR SP, =|Image$$UND_STACK$$ZI$$Limit|
CPS #0x1F
LDR SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
// Call SystemInit
IMPORT SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __main
IMPORT __main
BL __main
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
while(1);
}
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">GICDistributor_Type Struct Reference<div class="ingroups"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div> </div>
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<p>Structure type to access the Generic Interrupt Controller Distributor (GICD)
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a6ca67d9838ab3425864207c3a0399bd7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a></td></tr>
<tr class="memdesc:a6ca67d9838ab3425864207c3a0399bd7"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Distributor Control Register. <a href="#a6ca67d9838ab3425864207c3a0399bd7">More...</a><br/></td></tr>
<tr class="separator:a6ca67d9838ab3425864207c3a0399bd7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a405823d97dc90dd9d397a3980e2cd207"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">TYPER</a></td></tr>
<tr class="memdesc:a405823d97dc90dd9d397a3980e2cd207"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register. <a href="#a405823d97dc90dd9d397a3980e2cd207">More...</a><br/></td></tr>
<tr class="separator:a405823d97dc90dd9d397a3980e2cd207"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">IIDR</a></td></tr>
<tr class="memdesc:acebf65dae4cb82cd3c7deeefca9c9722"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/ ) Distributor Implementer Identification Register. <a href="#acebf65dae4cb82cd3c7deeefca9c9722">More...</a><br/></td></tr>
<tr class="separator:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae24f260e27065660a2059803293084f2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">STATUSR</a></td></tr>
<tr class="memdesc:ae24f260e27065660a2059803293084f2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Error Reporting Status Register, optional. <a href="#ae24f260e27065660a2059803293084f2">More...</a><br/></td></tr>
<tr class="separator:ae24f260e27065660a2059803293084f2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afbdd372578e2cd6f998320282cc8ed25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">SETSPI_NSR</a></td></tr>
<tr class="memdesc:afbdd372578e2cd6f998320282cc8ed25"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 ( /W) Set SPI Register. <a href="#afbdd372578e2cd6f998320282cc8ed25">More...</a><br/></td></tr>
<tr class="separator:afbdd372578e2cd6f998320282cc8ed25"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">CLRSPI_NSR</a></td></tr>
<tr class="memdesc:a2f584d3fbeaa355faf234f2ee57d1168"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 ( /W) Clear SPI Register. <a href="#a2f584d3fbeaa355faf234f2ee57d1168">More...</a><br/></td></tr>
<tr class="separator:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c">SETSPI_SR</a></td></tr>
<tr class="memdesc:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 ( /W) Set SPI, Secure Register. <a href="#ad55a8644bc95caf8bf53e1407ec9ed0c">More...</a><br/></td></tr>
<tr class="separator:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab487e4a8684b8a77357c6c20cf71dead"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead">CLRSPI_SR</a></td></tr>
<tr class="memdesc:ab487e4a8684b8a77357c6c20cf71dead"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x058 ( /W) Clear SPI, Secure Register. <a href="#ab487e4a8684b8a77357c6c20cf71dead">More...</a><br/></td></tr>
<tr class="separator:ab487e4a8684b8a77357c6c20cf71dead"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6a9effdd633c6e75651d9f53caace306"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">IGROUPR</a> [32]</td></tr>
<tr class="memdesc:a6a9effdd633c6e75651d9f53caace306"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Group Registers. <a href="#a6a9effdd633c6e75651d9f53caace306">More...</a><br/></td></tr>
<tr class="separator:a6a9effdd633c6e75651d9f53caace306"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1da3a2066b64644a0bb8a3066075ba87"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">ISENABLER</a> [32]</td></tr>
<tr class="memdesc:a1da3a2066b64644a0bb8a3066075ba87"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set-Enable Registers. <a href="#a1da3a2066b64644a0bb8a3066075ba87">More...</a><br/></td></tr>
<tr class="separator:a1da3a2066b64644a0bb8a3066075ba87"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a390fa9f2f460951b2c6094932d890807"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">ICENABLER</a> [32]</td></tr>
<tr class="memdesc:a390fa9f2f460951b2c6094932d890807"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear-Enable Registers. <a href="#a390fa9f2f460951b2c6094932d890807">More...</a><br/></td></tr>
<tr class="separator:a390fa9f2f460951b2c6094932d890807"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> [32]</td></tr>
<tr class="memdesc:a1c15cd75ce30d8946792e2a1a19556a5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Set-Pending Registers. <a href="#a1c15cd75ce30d8946792e2a1a19556a5">More...</a><br/></td></tr>
<tr class="separator:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0155cb4637845258e4ee76cd93cca2a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">ICPENDR</a> [32]</td></tr>
<tr class="memdesc:a0155cb4637845258e4ee76cd93cca2a6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x280 (R/W) Interrupt Clear-Pending Registers. <a href="#a0155cb4637845258e4ee76cd93cca2a6">More...</a><br/></td></tr>
<tr class="separator:a0155cb4637845258e4ee76cd93cca2a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> [32]</td></tr>
<tr class="memdesc:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Set-Active Registers. <a href="#a5eb8e1ef5a88293e2759c41f6057ccc4">More...</a><br/></td></tr>
<tr class="separator:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">ICACTIVER</a> [32]</td></tr>
<tr class="memdesc:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x380 (R/W) Interrupt Clear-Active Registers. <a href="#ac0fd4c1ad19b5a332e403bb9966ba967">More...</a><br/></td></tr>
<tr class="separator:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a08fa902293567e85dc6398dab58afaa9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">IPRIORITYR</a> [255]</td></tr>
<tr class="memdesc:a08fa902293567e85dc6398dab58afaa9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x400 (R/W) Interrupt Priority Registers. <a href="#a08fa902293567e85dc6398dab58afaa9">More...</a><br/></td></tr>
<tr class="separator:a08fa902293567e85dc6398dab58afaa9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6f1b07d48d3a9199f2effec8492f721c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> [255]</td></tr>
<tr class="memdesc:a6f1b07d48d3a9199f2effec8492f721c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x800 (R/W) Interrupt Targets Registers. <a href="#a6f1b07d48d3a9199f2effec8492f721c">More...</a><br/></td></tr>
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<tr class="memdesc:ae9eeb19ca95d0b95828f1f98700b5689"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xD00 (R/W) Interrupt Group Modifier Registers. <a href="#ae9eeb19ca95d0b95828f1f98700b5689">More...</a><br/></td></tr>
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<tr class="memdesc:a644abefb7064e434db20cc6dab5fe5f1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE00 (R/W) Non-secure Access Control Registers. <a href="#a644abefb7064e434db20cc6dab5fe5f1">More...</a><br/></td></tr>
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<tr class="memdesc:a6ac65c4a5394926cc9518753a00d4da1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF00 ( /W) Software Generated Interrupt Register. <a href="#a6ac65c4a5394926cc9518753a00d4da1">More...</a><br/></td></tr>
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<tr class="memdesc:a644a70cf4c12093c0277ce01f194b69b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF10 (R/W) SGI Clear-Pending Registers. <a href="#a644a70cf4c12093c0277ce01f194b69b">More...</a><br/></td></tr>
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<tr class="memdesc:ae40b4a50d9766c2bbf57441f68094f41"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF20 (R/W) SGI Set-Pending Registers. <a href="#ae40b4a50d9766c2bbf57441f68094f41">More...</a><br/></td></tr>
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<tr class="memdesc:a73e0c679e5f45710deea474ab0d39cdb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x6100(R/W) Interrupt Routing Registers. <a href="#a73e0c679e5f45710deea474ab0d39cdb">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::CLRSPI_NSR</td>
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<p>Clear Non-secure SPI Pending Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to clear pending state from. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::CLRSPI_SR</td>
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<p>Clear Secure SPI Pending Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to clear pending state from. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint8_t GICDistributor_Type::CPENDSGIR[16]</td>
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<p>SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p>
<ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p>
<ul>
<li>0 - no effect</li>
<li>1 - removes the pending state </li>
</ul>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::CTLR</td>
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<p>Distributor Control Register</p>
<p>When access is Secure, in a system that supports two Security states:</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
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<td align="left">[30:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7] </td><td align="left">EINWF </td><td align="left">Enable 1 of N Wakeup Functionality, if available. </td></tr>
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<td align="left">[6] </td><td align="left">DS </td><td align="left">Disable Security. </td></tr>
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<td align="left">[5] </td><td align="left">ARE_NS </td><td align="left">Affinity Routing Enable, Non-secure state. </td></tr>
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<td align="left">[4] </td><td align="left">ARE_S </td><td align="left">Affinity Routing Enable, Secure state. </td></tr>
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<td align="left">[3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[2] </td><td align="left">EnableGrp1S </td><td align="left">Enable Secure Group 1 interrupts. </td></tr>
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<td align="left">[1] </td><td align="left">EnableGrp1NS </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
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<td align="left">[0] </td><td align="left">EnableGrp0 </td><td align="left">Enable Group 0 interrupts. </td></tr>
</table>
<p>When access is Non-secure, in a system that supports two Security states:</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
<tr>
<td align="left">[30:5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[4] </td><td align="left">ARE_NS </td><td align="left">Affinity Routing Enable, Non-secure state. </td></tr>
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<td align="left">[3:2] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[1] </td><td align="left">EnableGrp1A </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
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<td align="left">[0] </td><td align="left">EnableGrp1 </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
</table>
<p>When in a system that supports only a single Security state:</p>
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<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
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<td align="left">[30:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7] </td><td align="left">EINWF </td><td align="left">Enable 1 of N Wakeup Functionality, if available. </td></tr>
<tr>
<td align="left">[6] </td><td align="left">DS </td><td align="left">Disable Security. </td></tr>
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<td align="left">[5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[4] </td><td align="left">ARE </td><td align="left">Affinity Routing Enable. </td></tr>
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<td align="left">[3:2] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[1] </td><td align="left">EnableGrp1 </td><td align="left">Enable Group 1 interrupts. </td></tr>
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<td align="left">[0] </td><td align="left">EnableGrp0 </td><td align="left">Enable Group 0 interrupts. </td></tr>
</table>
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<p>Interrupt Clear-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
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<p>Interrupt Clear-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
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<p>Interrupt Configuration Registers</p>
<p>Each interrupt can be configured by two corresponding bits:</p>
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<td align="left">[2*INTID%16+1] </td><td align="left">Edge </td><td align="left">Interrupt is: 0 - level sensitive, 1 - edge triggered </td></tr>
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<td align="left">[2*INTID%16] </td><td align="left">Model </td><td align="left">0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported </td></tr>
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<p>Interrupt Clear-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
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<p>Interrupt Group Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<p>And the value denotes:</p>
<ul>
<li>0 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 0<br/>
When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Secure.</li>
<li>1 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 1.<br/>
When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Non-secure Group 1. </li>
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<p>Interrupt Group Modifier Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32 </li>
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<p>Distributor Implementer Identification Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:24] </td><td align="left">ProductID </td><td align="left">An IMPLEMENTATION DEFINED product identifier </td></tr>
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<td align="left">[23:20] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[19:16] </td><td align="left">Variant </td><td align="left">An IMPLEMENTATION DEFINED variant number. </td></tr>
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<td align="left">[15:12] </td><td align="left">Revision </td><td align="left">An IMPLEMENTATION DEFINED revision number. </td></tr>
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<td align="left">[11:0] </td><td align="left">Implementer </td><td align="left">Contains the JEP106 code of the company implemented the GICD. </td></tr>
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<p>Interrupt Priority Registers</p>
<p>A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.</p>
<dl class="section note"><dt>Note</dt><dd>A register field corresponding to an unimplemented interrupt is RAZ/WI. </dd></dl>
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<p>Interrupt Routing Registers</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[63:40] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[39:32] </td><td align="left">Aff3 </td><td align="left">Affinity level 3, the least significant affinity level field. </td></tr>
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<td align="left">[31] </td><td align="left">IRM </td><td align="left">Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. </td></tr>
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<td align="left">[30:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:16] </td><td align="left">Aff2 </td><td align="left">Affinity level 2, an intermediate affinity level field. </td></tr>
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<td align="left">[15:8] </td><td align="left">Aff1 </td><td align="left">Affinity level 1, an intermediate affinity level field. </td></tr>
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<td align="left">[7:0] </td><td align="left">Aff0 </td><td align="left">Affinity level 0, the most significant affinity level field. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::ISACTIVER[32]</td>
</tr>
</table>
</div><div class="memdoc">
<p>Interrupt Set-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
</div>
</div>
<a class="anchor" id="a1da3a2066b64644a0bb8a3066075ba87"></a>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::ISENABLER[32]</td>
</tr>
</table>
</div><div class="memdoc">
<p>Interrupt Set-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
</div>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::ISPENDR[32]</td>
</tr>
</table>
</div><div class="memdoc">
<p>Interrupt Set-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>
</div>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint8_t GICDistributor_Type::ITARGETSR[1020]</td>
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</table>
</div><div class="memdoc">
<p>Interrupt Processor Targets Registers</p>
<p>Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.</p>
<table class="doxtable">
<tr>
<th align="left">CPU target field value </th><th align="left">Interrupt targets </th></tr>
<tr>
<td align="left">0bxxxxxxx1 </td><td align="left">CPU interface 0 </td></tr>
<tr>
<td align="left">0bxxxxxx1x </td><td align="left">CPU interface 1 </td></tr>
<tr>
<td align="left">0bxxxxx1xx </td><td align="left">CPU interface 2 </td></tr>
<tr>
<td align="left">0bxxxx1xxx </td><td align="left">CPU interface 3 </td></tr>
<tr>
<td align="left">0bxxx1xxxx </td><td align="left">CPU interface 4 </td></tr>
<tr>
<td align="left">0bxx1xxxxx </td><td align="left">CPU interface 5 </td></tr>
<tr>
<td align="left">0bx1xxxxxx </td><td align="left">CPU interface 6 </td></tr>
<tr>
<td align="left">0b1xxxxxxx </td><td align="left">CPU interface 7 </td></tr>
</table>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::NSACR[64]</td>
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</table>
</div><div class="memdoc">
<p>Non-secure Access Control Registers</p>
<p>Each two bits corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/16</li>
<li>Bit number is given by 2*INTID%16</li>
</ul>
<p>The possible values of each 2-bit field are:</p>
<ul>
<li>00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.</li>
<li>01 - Non-secure accesses are only permitted to requesting fields.</li>
<li>10 - As 01, additionally accesses to clearing field are permitted.</li>
<li>11 - As 10, additionally accesses to target and routing fields are permitted. </li>
</ul>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::SETSPI_NSR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Set Non-secure SPI Pending Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to set pending state for. </td></tr>
</table>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::SETSPI_SR</td>
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</table>
</div><div class="memdoc">
<p>Set Secure SPI Pending Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to set pending state for. </td></tr>
</table>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICDistributor_Type::SGIR</td>
</tr>
</table>
</div><div class="memdoc">
<p>Software Generated Interrupt Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:26] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[25:24] </td><td align="left">TargetFilterList </td><td align="left">Determines how the Distributor processes the requested SGI. </td></tr>
<tr>
<td align="left">[23:16] </td><td align="left">CPUTargetList </td><td align="left">When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. </td></tr>
<tr>
<td align="left">[15] </td><td align="left">NSATT </td><td align="left">Specifies the required group of the SGI. </td></tr>
<tr>
<td align="left">[14:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3:0] </td><td align="left">INTID </td><td align="left">The INTID of the SGI to forward to the specified CPU interfaces. </td></tr>
</table>
<p>Refer to <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> for details on TargetFilterList field. </p>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint8_t GICDistributor_Type::SPENDSGIR[16]</td>
</tr>
</table>
</div><div class="memdoc">
<p>SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p>
<ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p>
<ul>
<li>0 - no effect</li>
<li>1 - adds the pending state </li>
</ul>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::STATUSR</td>
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<p>Error Reporting Status Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3] </td><td align="left">WROD </td><td align="left">Write to an RO location. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">RWOD </td><td align="left">Read of a WO location. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">WRD </td><td align="left">Write to a reserved location. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">RRD </td><td align="left">Read of a reserved location. </td></tr>
</table>
</div>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICDistributor_Type::TYPER</td>
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</table>
</div><div class="memdoc">
<p>Interrupt Controller Type Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[15:11] </td><td align="left">LSPI </td><td align="left">Maximum number of lockable shared interrupts. </td></tr>
<tr>
<td align="left">[10] </td><td align="left">SecurityExtn </td><td align="left">Security Extensions: 0 - not implemented. 1 - implemented. </td></tr>
<tr>
<td align="left">[9:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[7:5] </td><td align="left">CPUNumber </td><td align="left">Number of implemented CPU interfaces [=CPUNumber+1] </td></tr>
<tr>
<td align="left">[4:0] </td><td align="left">ITLinesNumber </td><td align="left">Maximum number of interrups supported [=32*(ITLinesNumber+1)]. </td></tr>
</table>
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<div class="title">GICInterface_Type Struct Reference<div class="ingroups"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div> </div>
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<p>Structure type to access the Generic Interrupt Controller Interface (GICC)
</p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a5969edab40aa24e4d96e072af187a3a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a></td></tr>
<tr class="memdesc:a5969edab40aa24e4d96e072af187a3a9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) CPU Interface Control Register. <a href="#a5969edab40aa24e4d96e072af187a3a9">More...</a><br/></td></tr>
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<tr class="memdesc:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Priority Mask Register. <a href="#a0edadabc6e3ce1f36d820f0b52bc143b">More...</a><br/></td></tr>
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<tr class="memitem:a949317484547dc1db89c9f7ab40d1829"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">BPR</a></td></tr>
<tr class="memdesc:a949317484547dc1db89c9f7ab40d1829"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Binary Point Register. <a href="#a949317484547dc1db89c9f7ab40d1829">More...</a><br/></td></tr>
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<tr class="memitem:aa48569605fc0c163e1db35321b4c76ea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">IAR</a></td></tr>
<tr class="memdesc:aa48569605fc0c163e1db35321b4c76ea"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/ ) Interrupt Acknowledge Register. <a href="#aa48569605fc0c163e1db35321b4c76ea">More...</a><br/></td></tr>
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<tr class="memitem:a4b9baa43aae026438bad64e63df17cdb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">EOIR</a></td></tr>
<tr class="memdesc:a4b9baa43aae026438bad64e63df17cdb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 ( /W) End Of Interrupt Register. <a href="#a4b9baa43aae026438bad64e63df17cdb">More...</a><br/></td></tr>
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<tr class="memitem:a37762d42768ecb3d1302f34abc7f2821"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">RPR</a></td></tr>
<tr class="memdesc:a37762d42768ecb3d1302f34abc7f2821"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/ ) Running Priority Register. <a href="#a37762d42768ecb3d1302f34abc7f2821">More...</a><br/></td></tr>
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<tr class="memitem:af793cd280a74bf73cca8c4fedfc329d6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">HPPIR</a></td></tr>
<tr class="memdesc:af793cd280a74bf73cca8c4fedfc329d6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. <a href="#af793cd280a74bf73cca8c4fedfc329d6">More...</a><br/></td></tr>
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<tr class="memitem:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">ABPR</a></td></tr>
<tr class="memdesc:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/W) Aliased Binary Point Register. <a href="#a6d3ca9eaae5e0ac38f20846a1e67180d">More...</a><br/></td></tr>
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<tr class="memitem:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">AIAR</a></td></tr>
<tr class="memdesc:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register. <a href="#a849e9ead6e9ced78dc6f0ba9256dd5a6">More...</a><br/></td></tr>
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<tr class="memitem:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">AEOIR</a></td></tr>
<tr class="memdesc:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 ( /W) Aliased End Of Interrupt Register. <a href="#a89d5a920c2b91b4b7bd0312ba4c38a89">More...</a><br/></td></tr>
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<tr class="memitem:a12f25dec95ab3dd13a477573fab4b9c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">AHPPIR</a></td></tr>
<tr class="memdesc:a12f25dec95ab3dd13a477573fab4b9c8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register. <a href="#a12f25dec95ab3dd13a477573fab4b9c8">More...</a><br/></td></tr>
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<tr class="memitem:abd978b408fb69b7887be2c422f48ce7e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">STATUSR</a></td></tr>
<tr class="memdesc:abd978b408fb69b7887be2c422f48ce7e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) Error Reporting Status Register, optional. <a href="#abd978b408fb69b7887be2c422f48ce7e">More...</a><br/></td></tr>
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<tr class="memitem:aebae4bdcd3930372d639b85c5c9301e8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">APR</a> [4]</td></tr>
<tr class="memdesc:aebae4bdcd3930372d639b85c5c9301e8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D0 (R/W) Active Priority Register. <a href="#aebae4bdcd3930372d639b85c5c9301e8">More...</a><br/></td></tr>
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<tr class="memitem:ade3473ace2a8bf7c79a0251457be20f4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">NSAPR</a> [4]</td></tr>
<tr class="memdesc:ade3473ace2a8bf7c79a0251457be20f4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E0 (R/W) Non-secure Active Priority Register. <a href="#ade3473ace2a8bf7c79a0251457be20f4">More...</a><br/></td></tr>
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<tr class="memitem:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">IIDR</a></td></tr>
<tr class="memdesc:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0FC (R/ ) CPU Interface Identification Register. <a href="#aee78d0b6f64a7b47fbd730aabfcc86cf">More...</a><br/></td></tr>
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<tr class="memitem:a554bd1f88421df3189c664b9fd9c02aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">DIR</a></td></tr>
<tr class="memdesc:a554bd1f88421df3189c664b9fd9c02aa"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1000( /W) Deactivate Interrupt Register. <a href="#a554bd1f88421df3189c664b9fd9c02aa">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::ABPR</td>
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<p>CPU Interface Aliased Binary Point Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register. ">GICInterface_Type::BPR</a> </dd></dl>
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<td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::AEOIR</td>
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<p>CPU Interface Aliased End Of Interrupt Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb" title="Offset: 0x010 ( /W) End Of Interrupt Register. ">GICInterface_Type::EOIR</a> </dd></dl>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AHPPIR</td>
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<p>CPU Interface Aliased Highest Priority Pending Interrupt Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. ">GICInterface_Type::HPPIR</a> </dd></dl>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AIAR</td>
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<p>CPU Interface Aliased Interrupt Acknowledge Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register. ">GICInterface_Type::IAR</a> </dd></dl>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::APR[4]</td>
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<p>CPU Interface Active Priorities Registers </p>
<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::BPR</td>
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<p>CPU Interface Binary Point Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[2:0] </td><td align="left">Binary_Point </td><td align="left">Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. </td></tr>
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<p>The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please refer to the section Interrupt prioritization in the <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a> for details. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::CTLR</td>
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<p>CPU Interface Control Register</p>
<p>Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. In a GICv2 implementation, this includes control of the end of interrupt (EOI) behavior.</p>
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<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[0] </td><td align="left">Enable </td><td align="left">Interrupt signaling: 0 - Disable. 1 - Enable. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::DIR</td>
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<p>CPU Interface Deactivate Interrupt Register</p>
<table class="doxtable">
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the interrupt to be disabled. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::EOIR</td>
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<p>CPU Interface End Of Interrupt Register</p>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the finished interrupt. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::HPPIR</td>
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<p>CPU Interface Highest Priority Pending Interrupt Register</p>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the signaled interrupt. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::IAR</td>
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<p>CPU Interface Interrupt Acknowledge Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the signaled interrupt. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::IIDR</td>
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<p>CPU Interface Identification Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:20] </td><td align="left">ProductID </td><td align="left">An IMPLEMENTATION DEFINED product identifier </td></tr>
<tr>
<td align="left">[19:16] </td><td align="left">Arch_version </td><td align="left">The version of the GIC architecture that is implemented. </td></tr>
<tr>
<td align="left">[15:12] </td><td align="left">Revision </td><td align="left">An IMPLEMENTATION DEFINED revision number for the CPU interface. </td></tr>
<tr>
<td align="left">[11:0] </td><td align="left">Implementer </td><td align="left">Contains the JEP106 code of the company that implemented the CPU interface. </td></tr>
</table>
</div>
</div>
<a class="anchor" id="ade3473ace2a8bf7c79a0251457be20f4"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::NSAPR[4]</td>
</tr>
</table>
</div><div class="memdoc">
<p>CPU Interface Non-secure Active Priorities Registers </p>
<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8" title="Offset: 0x0D0 (R/W) Active Priority Register. ">GICInterface_Type::APR</a>[4] </dd></dl>
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<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::PMR</td>
</tr>
</table>
</div><div class="memdoc">
<p>CPU Interface Priority Mask Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The priority mask level for the CPU interface. </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI. </dd></dl>
</div>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::RPR</td>
</tr>
</table>
</div><div class="memdoc">
<p>CPU Interface Running Priority Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The current running priority on the CPU interface. </td></tr>
</table>
</div>
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<div class="memitem">
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::STATUSR</td>
</tr>
</table>
</div><div class="memdoc">
<p>CPU Interface Status Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[4] </td><td align="left">ASV </td><td align="left">Attempted security violation. </td></tr>
<tr>
<td align="left">[3] </td><td align="left">WROD </td><td align="left">Write to an RO location. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">RWOD </td><td align="left">Read of a WO location. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">WRD </td><td align="left">Write to a reserved location. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">RRD </td><td align="left">Read of a reserved location. </td></tr>
</table>
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<div class="title">L2C_310_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group__L2__cache__functions.html">L2C-310 Cache Controller Functions</a></div></div> </div>
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<p>Union type to access the L2C_310 Cache Controller.
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<table class="memberdecls">
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Data Fields</h2></td></tr>
<tr class="memitem:a87833c2acdf685d6ad6d0811f45677d7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a87833c2acdf685d6ad6d0811f45677d7">CACHE_ID</a></td></tr>
<tr class="memdesc:a87833c2acdf685d6ad6d0811f45677d7"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0000 (R/ ) Cache ID Register. <a href="#a87833c2acdf685d6ad6d0811f45677d7">More...</a><br/></td></tr>
<tr class="separator:a87833c2acdf685d6ad6d0811f45677d7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af19e1fd8a729834557884232c9e50bd2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#af19e1fd8a729834557884232c9e50bd2">CACHE_TYPE</a></td></tr>
<tr class="memdesc:af19e1fd8a729834557884232c9e50bd2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0004 (R/ ) Cache Type Register. <a href="#af19e1fd8a729834557884232c9e50bd2">More...</a><br/></td></tr>
<tr class="separator:af19e1fd8a729834557884232c9e50bd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memdesc:a491a4ed1ecdcdf784b180fa13ef46f2f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0100 (R/W) Control Register. <a href="#a491a4ed1ecdcdf784b180fa13ef46f2f">More...</a><br/></td></tr>
<tr class="separator:a491a4ed1ecdcdf784b180fa13ef46f2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memdesc:a4f7bc7277a5baa1d804913e41b8200be"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0104 (R/W) Auxiliary Control. <a href="#a4f7bc7277a5baa1d804913e41b8200be">More...</a><br/></td></tr>
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<tr class="memdesc:a2bc6f09ea83f8d3c966558598a098995"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0200 (R/W) Event Counter Control. <a href="#a2bc6f09ea83f8d3c966558598a098995">More...</a><br/></td></tr>
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<tr class="memdesc:a4465c7dd7b45f8f35acde8c6e28cbd17"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0204 (R/W) Event Counter 1 Configuration. <a href="#a4465c7dd7b45f8f35acde8c6e28cbd17">More...</a><br/></td></tr>
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<tr class="memdesc:a1c78032b2b237ee968d6758bddc915ba"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0208 (R/W) Event Counter 1 Configuration. <a href="#a1c78032b2b237ee968d6758bddc915ba">More...</a><br/></td></tr>
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<tr class="memdesc:a7c8ff2c17c6f3eb0d951e4cd193fd8e4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0214 (R/W) Interrupt Mask. <a href="#a7c8ff2c17c6f3eb0d951e4cd193fd8e4">More...</a><br/></td></tr>
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<tr class="memitem:a207e1eb35e13440241db1109790d9740"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a207e1eb35e13440241db1109790d9740">MASKED_INT_STATUS</a></td></tr>
<tr class="memdesc:a207e1eb35e13440241db1109790d9740"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0218 (R/ ) Masked Interrupt Status. <a href="#a207e1eb35e13440241db1109790d9740">More...</a><br/></td></tr>
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<tr class="memitem:a404f8453b6df3aaf5f3db4ff9b658637"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637">RAW_INT_STATUS</a></td></tr>
<tr class="memdesc:a404f8453b6df3aaf5f3db4ff9b658637"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x021c (R/ ) Raw Interrupt Status. <a href="#a404f8453b6df3aaf5f3db4ff9b658637">More...</a><br/></td></tr>
<tr class="separator:a404f8453b6df3aaf5f3db4ff9b658637"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t L2C_310_TypeDef::RAW_INT_STATUS</td>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY</td>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/structL2C__310__TypeDef.html | HTML | apache-2.0 | 51,177 |
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<div class="title">Timer_Type Struct Reference<div class="ingroups"><a class="el" href="group__PTM__timer__functions.html">Private Timer Functions</a></div></div> </div>
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<p>Structure type to access the Private Timer.
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a073457d2d18c2eff93fd12aec81ef20b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a073457d2d18c2eff93fd12aec81ef20b">LOAD</a></td></tr>
<tr class="memdesc:a073457d2d18c2eff93fd12aec81ef20b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Private Timer Load Register. <a href="#a073457d2d18c2eff93fd12aec81ef20b">More...</a><br/></td></tr>
<tr class="separator:a073457d2d18c2eff93fd12aec81ef20b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac933977724591e6ca87d91848fc7a6b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ac933977724591e6ca87d91848fc7a6b6">COUNTER</a></td></tr>
<tr class="memdesc:ac933977724591e6ca87d91848fc7a6b6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Private Timer Counter Register. <a href="#ac933977724591e6ca87d91848fc7a6b6">More...</a><br/></td></tr>
<tr class="separator:ac933977724591e6ca87d91848fc7a6b6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a91845c88231f4f337be2810d73bc79e4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4">CONTROL</a></td></tr>
<tr class="memdesc:a91845c88231f4f337be2810d73bc79e4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Private Timer Control Register. <a href="#a91845c88231f4f337be2810d73bc79e4">More...</a><br/></td></tr>
<tr class="separator:a91845c88231f4f337be2810d73bc79e4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ace17db6ca92940b030ad2ccbc674877e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ace17db6ca92940b030ad2ccbc674877e">ISR</a></td></tr>
<tr class="memdesc:ace17db6ca92940b030ad2ccbc674877e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Private Timer Interrupt Status Register. <a href="#ace17db6ca92940b030ad2ccbc674877e">More...</a><br/></td></tr>
<tr class="separator:ace17db6ca92940b030ad2ccbc674877e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6855bbb5d49f336c9f995dcce492455a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a6855bbb5d49f336c9f995dcce492455a">WLOAD</a></td></tr>
<tr class="memdesc:a6855bbb5d49f336c9f995dcce492455a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) Watchdog Load Register. <a href="#a6855bbb5d49f336c9f995dcce492455a">More...</a><br/></td></tr>
<tr class="separator:a6855bbb5d49f336c9f995dcce492455a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7a763d92fbcb506a28a22de548934abc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a7a763d92fbcb506a28a22de548934abc">WCOUNTER</a></td></tr>
<tr class="memdesc:a7a763d92fbcb506a28a22de548934abc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) Watchdog Counter Register. <a href="#a7a763d92fbcb506a28a22de548934abc">More...</a><br/></td></tr>
<tr class="separator:a7a763d92fbcb506a28a22de548934abc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac04581b452702517bfbfa61f9af4c6dd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#ac04581b452702517bfbfa61f9af4c6dd">WCONTROL</a></td></tr>
<tr class="memdesc:ac04581b452702517bfbfa61f9af4c6dd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Watchdog Control Register. <a href="#ac04581b452702517bfbfa61f9af4c6dd">More...</a><br/></td></tr>
<tr class="separator:ac04581b452702517bfbfa61f9af4c6dd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6239a36319b919b809e00dd26db105fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a6239a36319b919b809e00dd26db105fc">WISR</a></td></tr>
<tr class="memdesc:a6239a36319b919b809e00dd26db105fc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) Watchdog Interrupt Status Register. <a href="#a6239a36319b919b809e00dd26db105fc">More...</a><br/></td></tr>
<tr class="separator:a6239a36319b919b809e00dd26db105fc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a775e70c9dbf2b562f9884a9e0dded741"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a775e70c9dbf2b562f9884a9e0dded741">WRESET</a></td></tr>
<tr class="memdesc:a775e70c9dbf2b562f9884a9e0dded741"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Watchdog Reset Status Register. <a href="#a775e70c9dbf2b562f9884a9e0dded741">More...</a><br/></td></tr>
<tr class="separator:a775e70c9dbf2b562f9884a9e0dded741"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9d577164e0a55ecd6c630a9720f153c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html#a9d577164e0a55ecd6c630a9720f153c3">WDISABLE</a></td></tr>
<tr class="memdesc:a9d577164e0a55ecd6c630a9720f153c3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 ( /W) Watchdog Disable Register. <a href="#a9d577164e0a55ecd6c630a9720f153c3">More...</a><br/></td></tr>
<tr class="separator:a9d577164e0a55ecd6c630a9720f153c3"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::CONTROL</td>
</tr>
</table>
</div><div class="memdoc">
<p>Private Timer Control Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[15:8] </td><td align="left">Prescaler </td><td align="left">The prescaler modifies the clock period for the decrementing event for the Counter Register. </td></tr>
<tr>
<td align="left">[7:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">IRQ Enable </td><td align="left">If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">Auto Reload </td><td align="left">If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">Time Enabled </td><td align="left">If set, Timer is enabled and the counter decrements normally. </td></tr>
</table>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::COUNTER</td>
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<p>Private Timer Counter Register The Timer Counter Register is a decrementing counter.</p>
<p>The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.</p>
<p>When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.</p>
<p>When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.</p>
<p>Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t Timer_Type::ISR</td>
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<p>Private Timer Interrupt Status Register</p>
<p>The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::LOAD</td>
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<p>Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WCONTROL</td>
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<p>Watchdog Control Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[15:8] </td><td align="left">Prescaler </td><td align="left">The prescaler modifies the clock period for the decrementing event for the Counter Register. </td></tr>
<tr>
<td align="left">[7:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3] </td><td align="left">Watchdog Mode </td><td align="left">0 - Timer mode (default), 1 - Watchdog mode </td></tr>
<tr>
<td align="left">[2] </td><td align="left">IT Enable </td><td align="left">Interrupt enable for timer mode. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">Auto Reload </td><td align="left">0 - Single shot mode, 1 - Continuous timer mode </td></tr>
<tr>
<td align="left">[0] </td><td align="left">Watchdog Enable </td><td align="left">0 - Watchdog counter disabled, 1 - Watchdog timer enabled </td></tr>
</table>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WCOUNTER</td>
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<p>Watchdog Counter Register</p>
<p>The Watchdog Counter Register is a down counter.</p>
<p>The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:</p>
<ul>
<li>Timer mode: The watchdog interrupt status event flag is set and the interrupt is set as pending in the Interrupt Distributor.</li>
<li>Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted. </li>
</ul>
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<p>Watchdog Disable Register</p>
<p>Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WISR</td>
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<p>Watchdog Interrupt Status Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">Event Flag </td><td align="left">The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. </td></tr>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WLOAD</td>
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<p>Watchdog Load Register</p>
<p>The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register. </p>
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<td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t Timer_Type::WRESET</td>
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<p>Watchdog Reset Status Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">Reset Flag </td><td align="left">The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) </td></tr>
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<title>System Configuration Files system_<device>.c and system_<device>.h</title>
<title>CMSIS-Core (Cortex-A): System Configuration Files system_<device>.c and system_<device>.h</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
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 <span id="projectnumber">Version 1.1.4</span>
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<div class="title">System Configuration Files system_<device>.c and system_<device>.h </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> provides as a minimum the functions described under <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a>. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.</p>
<p>For devices with external memory BUS the system_<device>.c also configures the BUS system.</p>
<p>The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.</p>
<h1><a class="anchor" id="system_Device_sec"></a>
system_Device.c Template File</h1>
<p>The <a class="el" href="system_c_pg.html#system_Device_sec">system_Device.c Template File</a> for the Cortex-M3 is shown below.</p>
<pre class="fragment">/******************************************************************************
* @file system_<Device>.c
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V1.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
#include "irq_ctrl.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define XTAL (12000000U) /* Oscillator frequency */
#define SYSTEM_CLOCK (5 * XTAL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System Initialization
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
/* ToDo: add code to initialize the system
Do not use global variables because this function is called before
reaching pre-main. RW section may be overwritten afterwards. */
SystemCoreClock = SYSTEM_CLOCK;
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
// Enable GIC
L2C_Enable();
#endif
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}
</pre><h1><a class="anchor" id="system_Device_h_sec"></a>
system_Device.h Template File</h1>
<p>The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> is shown below.</p>
<pre class="fragment">/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-A Device Peripheral Access Layer
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_<Device>_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */
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<div class="title">CMSIS-Core Device Templates </div> </div>
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<div class="textblock"><p>Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors. Refer to the list of <a class="el" href="index.html#tested_tools_sec">Tested and Verified Toolchains</a> for compliance.</p>
<p>These CMSIS-Core device template files include the following:</p>
<ul>
<li>Register names of the Core Peripherals and names of the Core Exception Vectors.</li>
<li>Functions to access core peripherals, cache, MMU and special CPU instructions</li>
<li>Generic startup code and system configuration code.</li>
</ul>
<p>The detailed file structure of the CMSIS-Core device templates is shown in the following picture.</p>
<h1><a class="anchor" id="CMSIS_Processor_files"></a>
CMSIS-Core Processor Files</h1>
<p>The CMSIS-Core processor files provided by Arm are in the directory .\CMSIS\Core_A\Include. These header files define all processor specific attributes do not need any modifications. The <b>core_<cpu>.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:</p>
<table class="doxtable">
<tr>
<th align="left">Header File </th><th align="left">Processor </th></tr>
<tr>
<td align="left"><a class="el" href="core__ca_8h.html" title="CMSIS Cortex-A Core Peripheral Access Layer Header File. ">core_ca.h</a> </td><td align="left">generics for all supportet Cortex-A processors </td></tr>
</table>
<h1><a class="anchor" id="device_examples"></a>
Device Examples</h1>
<p>The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\Device\ARM and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:</p>
<table class="doxtable">
<tr>
<th align="left">Family </th><th align="left">Device </th><th align="left">Description </th></tr>
<tr>
<td align="left">ARM Cortex-A5 </td><td align="left">ARMCA5 </td><td align="left">Cortex-A5 based device </td></tr>
<tr>
<td align="left">ARM Cortex-A7 </td><td align="left">ARMCA7 </td><td align="left">Cortex-A7 based device </td></tr>
<tr>
<td align="left">ARM Cortex-A9 </td><td align="left">ARMCA9 </td><td align="left">Cortex-A9 based device </td></tr>
</table>
<h1><a class="anchor" id="template_files_sec"></a>
Template Files</h1>
<p>To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add to these template files the following information:</p>
<ul>
<li><b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.</li>
<li><b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.</li>
<li><b>Interrupt vectors</b> in the startup file that are device specific.</li>
</ul>
<table class="cmtable">
<tr>
<th>Template File </th><th>Description </th></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Source\ARM\startup_Device.c </td><td>Startup file template for Arm C/C++ Compiler. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Source\ARM\Device.sct </td><td>Linker scatter file template for Arm C/C++ Compiler. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Source\system_Device.c </td><td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system). </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Source\mmu_Device.c </td><td>Sample mmu_Device.c file with memory map description for Memory Management Unit (MMU) configuration. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Include\Device.h </td><td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Include\system_Device.h </td><td>Generic system device configuration include file. </td></tr>
<tr>
<td>.\Device\_Template_Vendor\Vendor\Device_A\Include\mem_Device.h </td><td>Generic memory base address and size definitions used in scatter file. Settable via Configuration Wizard. </td></tr>
</table>
<p><b>Adapt Template Files to a Device</b></p>
<p>The following steps describe how to adopt the template files to a specific device or device family. Copy the complete all files in the template directory and replace:</p>
<ul>
<li>directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.</li>
<li>directory name 'Device' with the specific device name e.g.: LPC17xx.</li>
<li>in the file names 'Device' with the specific device name e.g.: LPC17xx.</li>
</ul>
<p>Each template file contains comments that start with <b>ToDo:</b> that describe a required modification. The template files contain place holders:</p>
<table class="cmtable">
<tr>
<th>Placeholder </th><th>Replaced with </th></tr>
<tr>
<td><Device> </td><td>the specific device name or device family name; i.e. LPC17xx. </td></tr>
<tr>
<td><DeviceInterrupt> </td><td>a specific interrupt name of the device; i.e. TIM1 for Timer 1. </td></tr>
<tr>
<td><DeviceAbbreviation> </td><td>short name or abbreviation of the device family; i.e. LPC. </td></tr>
<tr>
<td>Cortex-M# </td><td>the specific Cortex-M processor name; i.e. Cortex-M3. </td></tr>
</table>
<p>The device configuration of the template files is described in detail on the following pages:</p>
<ul>
<li><a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a></li>
<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a></li>
<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a></li>
<li><a class="el" href="mem_h_pg.html">Memory Configuration Files mem_<device>.h</a></li>
<li><a class="el" href="mmu_c_pg.html">Memory Management Unit Files mmu_<device>.c</a> </li>
</ul>
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<div class="title">ACTLR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></div></div> </div>
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<p>Bit field declaration for ACTLR layout.
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Data Fields</h2></td></tr>
<tr class="memitem:ac953059faa3a1139f8787d87f58a875d"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a50827448ef15f15f922e10a1c609f5d3"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">FW</a>:1</td></tr>
<tr class="memdesc:a50827448ef15f15f922e10a1c609f5d3"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast <a href="#a50827448ef15f15f922e10a1c609f5d3">More...</a><br/></td></tr>
<tr class="separator:a50827448ef15f15f922e10a1c609f5d3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:a4756b5b7479e4e5f5c27c841f99b50e8"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6 Enables coherent requests to the processor <a href="#a4756b5b7479e4e5f5c27c841f99b50e8">More...</a><br/></td></tr>
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<tr class="memitem:a1019cd812c2931a4e7eb82996127bebd"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">EXCL</a>:1</td></tr>
<tr class="memdesc:a1019cd812c2931a4e7eb82996127bebd"><td class="mdescLeft"> </td><td class="mdescRight">bit: 7 Exclusive L1/L2 cache control <a href="#a1019cd812c2931a4e7eb82996127bebd">More...</a><br/></td></tr>
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<tr class="memitem:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">DODMBS</a>:1</td></tr>
<tr class="memdesc:aaffa24a5ff6bf987d4ad0d73cafd014b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior <a href="#aaffa24a5ff6bf987d4ad0d73cafd014b">More...</a><br/></td></tr>
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<tr class="memitem:a9689f28161ce8516e8a74f1fb7cf1007"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#ad8faaa57629f258c6eba678ba8efc9da">DWBST</a>:1</td></tr>
<tr class="memdesc:a9689f28161ce8516e8a74f1fb7cf1007"><td class="mdescLeft"> </td><td class="mdescRight">bit: 11 AXI data write bursts to Normal memory <a href="#a9689f28161ce8516e8a74f1fb7cf1007">More...</a><br/></td></tr>
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<tr class="memitem:a1873f12ba4059c242c4d73c3c669532e"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3">RADIS</a>:1</td></tr>
<tr class="memdesc:a1873f12ba4059c242c4d73c3c669532e"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 L1 Data Cache read-allocate mode disable <a href="#a1873f12ba4059c242c4d73c3c669532e">More...</a><br/></td></tr>
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<tr class="memitem:a473b5ba32637965efc11c81809e2b3e2"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c">L1PCTL</a>:2</td></tr>
<tr class="memdesc:a473b5ba32637965efc11c81809e2b3e2"><td class="mdescLeft"> </td><td class="mdescRight">bit:13..14 L1 Data prefetch control <a href="#a473b5ba32637965efc11c81809e2b3e2">More...</a><br/></td></tr>
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<tr class="memdesc:ab446bfb09f286a0fabd62c9204bda75e"><td class="mdescLeft"> </td><td class="mdescRight">bit:16..15 Branch prediction policy <a href="#ab446bfb09f286a0fabd62c9204bda75e">More...</a><br/></td></tr>
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<tr class="memitem:a364f4cc4a6eef60fb3476fd8fe6ff748"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3">RSDIS</a>:1</td></tr>
<tr class="memdesc:a364f4cc4a6eef60fb3476fd8fe6ff748"><td class="mdescLeft"> </td><td class="mdescRight">bit: 17 Disable return stack operation <a href="#a364f4cc4a6eef60fb3476fd8fe6ff748">More...</a><br/></td></tr>
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<tr class="memitem:ab74d59bda944b237ad561ab6b8d9e452"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#ad1a121373ae8df19f6d11bde3b3ba9c9">BTDIS</a>:1</td></tr>
<tr class="memdesc:ab74d59bda944b237ad561ab6b8d9e452"><td class="mdescLeft"> </td><td class="mdescRight">bit: 18 Disable indirect Branch Target Address Cache (BTAC) <a href="#ab74d59bda944b237ad561ab6b8d9e452">More...</a><br/></td></tr>
<tr class="separator:ab74d59bda944b237ad561ab6b8d9e452"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa4ff9dd0a9fba2327631b183b09203cb"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a19e5f8f1a2ad8634619399b4eb50a449">DBDI</a>:1</td></tr>
<tr class="memdesc:aa4ff9dd0a9fba2327631b183b09203cb"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Disable branch dual issue <a href="#aa4ff9dd0a9fba2327631b183b09203cb">More...</a><br/></td></tr>
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<tr class="memitem:ac953059faa3a1139f8787d87f58a875d"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#ac953059faa3a1139f8787d87f58a875d">b</a></td></tr>
<tr class="memdesc:ac953059faa3a1139f8787d87f58a875d"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access on Cortex-A5. <a href="#ac953059faa3a1139f8787d87f58a875d">More...</a><br/></td></tr>
<tr class="separator:ac953059faa3a1139f8787d87f58a875d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:ae2aae6b9f3b12894f4a615c095a6a889"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:ae2aae6b9f3b12894f4a615c095a6a889"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6 Enables coherent requests to the processor <a href="#ae2aae6b9f3b12894f4a615c095a6a889">More...</a><br/></td></tr>
<tr class="separator:ae2aae6b9f3b12894f4a615c095a6a889"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a523e7c03812bc6962252e3a22022aa4c"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8">DODMBS</a>:1</td></tr>
<tr class="memdesc:a523e7c03812bc6962252e3a22022aa4c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10 Disable optimized data memory barrier behavior <a href="#a523e7c03812bc6962252e3a22022aa4c">More...</a><br/></td></tr>
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<tr class="memitem:add3dfd4a681eb6b3f88229f0bce6042f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a947f73d64ebde186b9416fd6dc66bc26">L2RADIS</a>:1</td></tr>
<tr class="memdesc:add3dfd4a681eb6b3f88229f0bce6042f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 11 L2 Data Cache read-allocate mode disable <a href="#add3dfd4a681eb6b3f88229f0bce6042f">More...</a><br/></td></tr>
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<tr class="memitem:a0cb4299988efa4fc3364898111f834ff"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a3800bdd7abfab1a51dcfa7069e245d65">L1RADIS</a>:1</td></tr>
<tr class="memdesc:a0cb4299988efa4fc3364898111f834ff"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 L1 Data Cache read-allocate mode disable <a href="#a0cb4299988efa4fc3364898111f834ff">More...</a><br/></td></tr>
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<tr class="memitem:aec089f449dbf249eb34dba39c7198805"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c">L1PCTL</a>:2</td></tr>
<tr class="memdesc:aec089f449dbf249eb34dba39c7198805"><td class="mdescLeft"> </td><td class="mdescRight">bit:13..14 L1 Data prefetch control <a href="#aec089f449dbf249eb34dba39c7198805">More...</a><br/></td></tr>
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<tr class="memitem:a9254469bb22c156ff411e35ef0751121"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a4fe04e95b26e089642bee6952f223f82">DDVM</a>:1</td></tr>
<tr class="memdesc:a9254469bb22c156ff411e35ef0751121"><td class="mdescLeft"> </td><td class="mdescRight">bit: 15 Disable Distributed Virtual Memory (DVM) transactions <a href="#a9254469bb22c156ff411e35ef0751121">More...</a><br/></td></tr>
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<tr class="memitem:ad3be842fda0aa2525ce4e9a151396403"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#ab938c32e10162d06ba6b02400e955e01">DDI</a>:1</td></tr>
<tr class="memdesc:ad3be842fda0aa2525ce4e9a151396403"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Disable dual issue <a href="#ad3be842fda0aa2525ce4e9a151396403">More...</a><br/></td></tr>
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<tr class="memitem:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a94d750b9b337ce140b04d6e30e7a2ca2">b</a></td></tr>
<tr class="memdesc:a94d750b9b337ce140b04d6e30e7a2ca2"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access on Cortex-A7. <a href="#a94d750b9b337ce140b04d6e30e7a2ca2">More...</a><br/></td></tr>
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<tr class="memitem:a5044f19ce5ae1f73dda07f7187e70923"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a5a318416ffc6404c2ba937554c5b869a"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781">FW</a>:1</td></tr>
<tr class="memdesc:a5a318416ffc6404c2ba937554c5b869a"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Cache and TLB maintenance broadcast <a href="#a5a318416ffc6404c2ba937554c5b869a">More...</a><br/></td></tr>
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<tr class="memitem:a697e277c2fd70cfbf4454224371f0a1f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#aacb87aa6bf093e1ee956342e0cb5903e">L1PE</a>:1</td></tr>
<tr class="memdesc:a697e277c2fd70cfbf4454224371f0a1f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 Dside prefetch <a href="#a697e277c2fd70cfbf4454224371f0a1f">More...</a><br/></td></tr>
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<tr class="memitem:acadb7b00e0fa53eb081040f50a97b6be"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a67e005f7741b6d46cf95d9c477efef36">WFLZM</a>:1</td></tr>
<tr class="memdesc:acadb7b00e0fa53eb081040f50a97b6be"><td class="mdescLeft"> </td><td class="mdescRight">bit: 3 Cache and TLB maintenance broadcast <a href="#acadb7b00e0fa53eb081040f50a97b6be">More...</a><br/></td></tr>
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<tr class="memitem:a6972b588e58acb9aada88fd820eb883d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149">SMP</a>:1</td></tr>
<tr class="memdesc:a6972b588e58acb9aada88fd820eb883d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6 Enables coherent requests to the processor <a href="#a6972b588e58acb9aada88fd820eb883d">More...</a><br/></td></tr>
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<tr class="memitem:a2391993a4a3b7e476627de84650571a1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91">EXCL</a>:1</td></tr>
<tr class="memdesc:a2391993a4a3b7e476627de84650571a1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 7 Exclusive L1/L2 cache control <a href="#a2391993a4a3b7e476627de84650571a1">More...</a><br/></td></tr>
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<tr class="memitem:ada7513bf16860a33ac99cce7f4eb2394"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a3f235030777fe4e20477063df416b515">AOW</a>:1</td></tr>
<tr class="memdesc:ada7513bf16860a33ac99cce7f4eb2394"><td class="mdescLeft"> </td><td class="mdescRight">bit: 8 Enable allocation in one cache way only <a href="#ada7513bf16860a33ac99cce7f4eb2394">More...</a><br/></td></tr>
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<tr class="memitem:aba098bbde24ff39c967d472b7c0c9f8a"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c">PARITY</a>:1</td></tr>
<tr class="memdesc:aba098bbde24ff39c967d472b7c0c9f8a"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Support for parity checking, if implemented <a href="#aba098bbde24ff39c967d472b7c0c9f8a">More...</a><br/></td></tr>
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<tr class="memitem:a5044f19ce5ae1f73dda07f7187e70923"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#a5044f19ce5ae1f73dda07f7187e70923">b</a></td></tr>
<tr class="memdesc:a5044f19ce5ae1f73dda07f7187e70923"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access on Cortex-A9. <a href="#a5044f19ce5ae1f73dda07f7187e70923">More...</a><br/></td></tr>
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<tr class="memitem:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html#ac65c09d839f8a78340c3b81d3bc90e4d">w</a></td></tr>
<tr class="memdesc:ac65c09d839f8a78340c3b81d3bc90e4d"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#ac65c09d839f8a78340c3b81d3bc90e4d">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a3f235030777fe4e20477063df416b515"></a>
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<td class="memname">struct { ... } ACTLR_Type::b</td>
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<td class="memname">struct { ... } ACTLR_Type::b</td>
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<td class="memname">uint32_t ACTLR_Type::BP</td>
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<td class="memname">uint32_t ACTLR_Type::BTDIS</td>
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<td class="memname">uint32_t ACTLR_Type::DBDI</td>
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<td class="memname">uint32_t ACTLR_Type::DDI</td>
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<td class="memname">uint32_t ACTLR_Type::DDVM</td>
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<td class="memname">uint32_t ACTLR_Type::DODMBS</td>
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<td class="memname">uint32_t ACTLR_Type::L1RADIS</td>
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<a class="anchor" id="a947f73d64ebde186b9416fd6dc66bc26"></a>
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<td class="memname">uint32_t ACTLR_Type::PARITY</td>
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<a class="anchor" id="a91288f7320d267d76b4aad4adcf8cda3"></a>
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<td class="memname">uint32_t ACTLR_Type::RSDIS</td>
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<td class="memname">uint32_t ACTLR_Type::SMP</td>
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var unionACTLR__Type =
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<div class="title">CNTP_CTL_Type Union Reference<div class="ingroups"><a class="el" href="group__PL1__timer__functions.html">Generic Physical Timer Functions</a></div></div> </div>
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<p>Physical Timer Control register.
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:acfac7f6bcdcf74d339bea24b437d977e"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a0badd73f8e87ac4ac7257976b84d0442"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#a3b7426f99d1ecdacd172999b4d04b210">ENABLE</a>:1</td></tr>
<tr class="memdesc:a0badd73f8e87ac4ac7257976b84d0442"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Enables the timer. <a href="#a0badd73f8e87ac4ac7257976b84d0442">More...</a><br/></td></tr>
<tr class="separator:a0badd73f8e87ac4ac7257976b84d0442"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a23c21a438494d4d2635703f1ffee0d3a"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#a07e23afbd292bcb84f15ea27ae2c157d">IMASK</a>:1</td></tr>
<tr class="memdesc:a23c21a438494d4d2635703f1ffee0d3a"><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Timer output signal mask bit. <a href="#a23c21a438494d4d2635703f1ffee0d3a">More...</a><br/></td></tr>
<tr class="separator:a23c21a438494d4d2635703f1ffee0d3a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7af26670bee00da951fd89b7a2792383"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#acb2f8900c7f6960443df47c1f2f2add3">ISTATUS</a>:1</td></tr>
<tr class="memdesc:a7af26670bee00da951fd89b7a2792383"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 The status of the timer. <a href="#a7af26670bee00da951fd89b7a2792383">More...</a><br/></td></tr>
<tr class="separator:a7af26670bee00da951fd89b7a2792383"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a52b68874ef44894f239e8c207a6aac78"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#a033fc913891068a89b1609af783db8a8">_reserved0</a>:29</td></tr>
<tr class="memdesc:a52b68874ef44894f239e8c207a6aac78"><td class="mdescLeft"> </td><td class="mdescRight">bit: 3..31 Reserved <a href="#a52b68874ef44894f239e8c207a6aac78">More...</a><br/></td></tr>
<tr class="separator:a52b68874ef44894f239e8c207a6aac78"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acfac7f6bcdcf74d339bea24b437d977e"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCNTP__CTL__Type.html#acfac7f6bcdcf74d339bea24b437d977e">b</a></td></tr>
<tr class="memdesc:acfac7f6bcdcf74d339bea24b437d977e"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#acfac7f6bcdcf74d339bea24b437d977e">More...</a><br/></td></tr>
<tr class="separator:acfac7f6bcdcf74d339bea24b437d977e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0e2d443e0447f9b286433220cd288dbf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCNTP__CTL__Type.html#a0e2d443e0447f9b286433220cd288dbf">w</a></td></tr>
<tr class="memdesc:a0e2d443e0447f9b286433220cd288dbf"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a0e2d443e0447f9b286433220cd288dbf">More...</a><br/></td></tr>
<tr class="separator:a0e2d443e0447f9b286433220cd288dbf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afdd6b14cdb03e4e694ec7db8163916b0"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:aa895e922fb1999148f0122f76c21e62c"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#a3b7426f99d1ecdacd172999b4d04b210">ENABLE</a>:1</td></tr>
<tr class="memdesc:aa895e922fb1999148f0122f76c21e62c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Enables the timer. <a href="#aa895e922fb1999148f0122f76c21e62c">More...</a><br/></td></tr>
<tr class="separator:aa895e922fb1999148f0122f76c21e62c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9e4350069ebf7bbe0a33728bd958bd8f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#a07e23afbd292bcb84f15ea27ae2c157d">IMASK</a>:1</td></tr>
<tr class="memdesc:a9e4350069ebf7bbe0a33728bd958bd8f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Timer output signal mask bit. <a href="#a9e4350069ebf7bbe0a33728bd958bd8f">More...</a><br/></td></tr>
<tr class="separator:a9e4350069ebf7bbe0a33728bd958bd8f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af340ef21505fcd55f4f14b5c3ac8423a"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCNTP__CTL__Type.html#acb2f8900c7f6960443df47c1f2f2add3">ISTATUS</a>:1</td></tr>
<tr class="memdesc:af340ef21505fcd55f4f14b5c3ac8423a"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 The status of the timer. <a href="#af340ef21505fcd55f4f14b5c3ac8423a">More...</a><br/></td></tr>
<tr class="separator:af340ef21505fcd55f4f14b5c3ac8423a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afdd6b14cdb03e4e694ec7db8163916b0"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCNTP__CTL__Type.html#afdd6b14cdb03e4e694ec7db8163916b0">b</a></td></tr>
<tr class="memdesc:afdd6b14cdb03e4e694ec7db8163916b0"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#afdd6b14cdb03e4e694ec7db8163916b0">More...</a><br/></td></tr>
<tr class="separator:afdd6b14cdb03e4e694ec7db8163916b0"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">uint32_t CNTP_CTL_Type::_reserved0</td>
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<p>Enables the timer.</p>
<p>Permitted values are:</p>
<ul>
<li>0 - Timer disabled.</li>
<li>1 - Timer enabled. </li>
</ul>
</div>
</div>
<a class="anchor" id="a07e23afbd292bcb84f15ea27ae2c157d"></a>
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<p>Timer output signal mask bit.</p>
<p>Permitted values are:</p>
<ul>
<li>0 - Timer output signal is not masked.</li>
<li>1 - Timer output signal is masked. </li>
</ul>
</div>
</div>
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<p>The status of the timer.</p>
<p>This bit indicates whether the timer condition is asserted:</p>
<ul>
<li>0 - Timer condition is not asserted.</li>
<li>1 - Timer condition is asserted. </li>
</ul>
</div>
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<div class="title">CPACR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__CPACR.html">Coprocessor Access Control Register (CPACR)</a></div></div> </div>
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<p>Bit field declaration for CPACR layout.
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<table class="memberdecls">
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Data Fields</h2></td></tr>
<tr class="memitem:a7aa1870fa74e00241618df136e04141f"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a5578ea4f0b27e49e856bea8db59c7f0d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195">CP0</a>:2</td></tr>
<tr class="memdesc:a5578ea4f0b27e49e856bea8db59c7f0d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0..1 Access rights for coprocessor 0 <a href="#a5578ea4f0b27e49e856bea8db59c7f0d">More...</a><br/></td></tr>
<tr class="separator:a5578ea4f0b27e49e856bea8db59c7f0d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1c1fdfc94d0d92c726883b3b529f6ad3"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624">CP1</a>:2</td></tr>
<tr class="memdesc:a1c1fdfc94d0d92c726883b3b529f6ad3"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2..3 Access rights for coprocessor 1 <a href="#a1c1fdfc94d0d92c726883b3b529f6ad3">More...</a><br/></td></tr>
<tr class="separator:a1c1fdfc94d0d92c726883b3b529f6ad3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adf02a8910e6395146f3e9803d49993b1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586">CP2</a>:2</td></tr>
<tr class="memdesc:adf02a8910e6395146f3e9803d49993b1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 4..5 Access rights for coprocessor 2 <a href="#adf02a8910e6395146f3e9803d49993b1">More...</a><br/></td></tr>
<tr class="separator:adf02a8910e6395146f3e9803d49993b1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac0ca0d2b6df3a87f30b98d1e4f6b73d1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79">CP3</a>:2</td></tr>
<tr class="memdesc:ac0ca0d2b6df3a87f30b98d1e4f6b73d1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6..7 Access rights for coprocessor 3 <a href="#ac0ca0d2b6df3a87f30b98d1e4f6b73d1">More...</a><br/></td></tr>
<tr class="separator:ac0ca0d2b6df3a87f30b98d1e4f6b73d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa65229667a948b837290d3023cb8e084"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb">CP4</a>:2</td></tr>
<tr class="memdesc:aa65229667a948b837290d3023cb8e084"><td class="mdescLeft"> </td><td class="mdescRight">bit: 8..9 Access rights for coprocessor 4 <a href="#aa65229667a948b837290d3023cb8e084">More...</a><br/></td></tr>
<tr class="separator:aa65229667a948b837290d3023cb8e084"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abc5a47af2f15ccb6b7f7a964a46f4808"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573">CP5</a>:2</td></tr>
<tr class="memdesc:abc5a47af2f15ccb6b7f7a964a46f4808"><td class="mdescLeft"> </td><td class="mdescRight">bit:10..11 Access rights for coprocessor 5 <a href="#abc5a47af2f15ccb6b7f7a964a46f4808">More...</a><br/></td></tr>
<tr class="separator:abc5a47af2f15ccb6b7f7a964a46f4808"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adb18e72f112f8e7a6e0a777e126df8bd"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#ad898cab7c89a07b80068d141ced869e3">CP6</a>:2</td></tr>
<tr class="memdesc:adb18e72f112f8e7a6e0a777e126df8bd"><td class="mdescLeft"> </td><td class="mdescRight">bit:12..13 Access rights for coprocessor 6 <a href="#adb18e72f112f8e7a6e0a777e126df8bd">More...</a><br/></td></tr>
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<tr class="memitem:a02d0a1971a70c204c54abab767d9f55b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d">CP7</a>:2</td></tr>
<tr class="memdesc:a02d0a1971a70c204c54abab767d9f55b"><td class="mdescLeft"> </td><td class="mdescRight">bit:14..15 Access rights for coprocessor 7 <a href="#a02d0a1971a70c204c54abab767d9f55b">More...</a><br/></td></tr>
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<tr class="memitem:a3fc38938b62f002b86f3cadba516e333"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f">CP8</a>:2</td></tr>
<tr class="memdesc:a3fc38938b62f002b86f3cadba516e333"><td class="mdescLeft"> </td><td class="mdescRight">bit:16..17 Access rights for coprocessor 8 <a href="#a3fc38938b62f002b86f3cadba516e333">More...</a><br/></td></tr>
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<tr class="memitem:ade62734cb13acdad25b6993d5e91805c"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5">CP9</a>:2</td></tr>
<tr class="memdesc:ade62734cb13acdad25b6993d5e91805c"><td class="mdescLeft"> </td><td class="mdescRight">bit:18..19 Access rights for coprocessor 9 <a href="#ade62734cb13acdad25b6993d5e91805c">More...</a><br/></td></tr>
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<tr class="memitem:a4fd8feccdc5334f09266e98ca4989541"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a0275dc6b0eb9f906ebc5c6431b03dc4e">CP10</a>:2</td></tr>
<tr class="memdesc:a4fd8feccdc5334f09266e98ca4989541"><td class="mdescLeft"> </td><td class="mdescRight">bit:20..21 Access rights for coprocessor 10 <a href="#a4fd8feccdc5334f09266e98ca4989541">More...</a><br/></td></tr>
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<tr class="memitem:a04fb9952fc07fac0adc063f469128230"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#ac54b8897f9358f37e0046b010c334e87">CP11</a>:2</td></tr>
<tr class="memdesc:a04fb9952fc07fac0adc063f469128230"><td class="mdescLeft"> </td><td class="mdescRight">bit:22..23 Access rights for coprocessor 11 <a href="#a04fb9952fc07fac0adc063f469128230">More...</a><br/></td></tr>
<tr class="separator:a04fb9952fc07fac0adc063f469128230"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a74f616eb10bf7bb39e4c32c4beb5a88f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce">CP12</a>:2</td></tr>
<tr class="memdesc:a74f616eb10bf7bb39e4c32c4beb5a88f"><td class="mdescLeft"> </td><td class="mdescRight">bit:24..25 Access rights for coprocessor 11 <a href="#a74f616eb10bf7bb39e4c32c4beb5a88f">More...</a><br/></td></tr>
<tr class="separator:a74f616eb10bf7bb39e4c32c4beb5a88f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9ead3c9653e3699f35208e9c8cc351a7"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90">CP13</a>:2</td></tr>
<tr class="memdesc:a9ead3c9653e3699f35208e9c8cc351a7"><td class="mdescLeft"> </td><td class="mdescRight">bit:26..27 Access rights for coprocessor 11 <a href="#a9ead3c9653e3699f35208e9c8cc351a7">More...</a><br/></td></tr>
<tr class="separator:a9ead3c9653e3699f35208e9c8cc351a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acf4ebdfe6b108c6d4087a5f90537252b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#ac6f2f67dd0250b9dc9a8271a05655bbe">TRCDIS</a>:1</td></tr>
<tr class="memdesc:acf4ebdfe6b108c6d4087a5f90537252b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Disable CP14 access to trace registers <a href="#acf4ebdfe6b108c6d4087a5f90537252b">More...</a><br/></td></tr>
<tr class="separator:acf4ebdfe6b108c6d4087a5f90537252b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a109bb595d6853cdf2540f39a8e4db467"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a6206695a548b18ce0e2ea5276d1eef1d">D32DIS</a>:1</td></tr>
<tr class="memdesc:a109bb595d6853cdf2540f39a8e4db467"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Disable use of registers D16-D31 of the VFP register file <a href="#a109bb595d6853cdf2540f39a8e4db467">More...</a><br/></td></tr>
<tr class="separator:a109bb595d6853cdf2540f39a8e4db467"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0a35b5e99b32966d73db7dc2b62d6095"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986">ASEDIS</a>:1</td></tr>
<tr class="memdesc:a0a35b5e99b32966d73db7dc2b62d6095"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Disable Advanced SIMD Functionality <a href="#a0a35b5e99b32966d73db7dc2b62d6095">More...</a><br/></td></tr>
<tr class="separator:a0a35b5e99b32966d73db7dc2b62d6095"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7aa1870fa74e00241618df136e04141f"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPACR__Type.html#a7aa1870fa74e00241618df136e04141f">b</a></td></tr>
<tr class="memdesc:a7aa1870fa74e00241618df136e04141f"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a7aa1870fa74e00241618df136e04141f">More...</a><br/></td></tr>
<tr class="separator:a7aa1870fa74e00241618df136e04141f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae2d9d724aff1f8f0060738f5d4527c33"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPACR__Type.html#ae2d9d724aff1f8f0060738f5d4527c33">w</a></td></tr>
<tr class="memdesc:ae2d9d724aff1f8f0060738f5d4527c33"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#ae2d9d724aff1f8f0060738f5d4527c33">More...</a><br/></td></tr>
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</table>
<h2 class="groupheader">Field Documentation</h2>
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<div class="title">CPSR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></div></div> </div>
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<p>Bit field declaration for CPSR layout.
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a2e735da6b6156874d12aaceb2017da06"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a509029513d2d0671c81cb9f4fda7fd47"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a2bc38ab81bc2e2fd111526a58f94511f">M</a>:5</td></tr>
<tr class="memdesc:a509029513d2d0671c81cb9f4fda7fd47"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 4 Mode field <a href="#a509029513d2d0671c81cb9f4fda7fd47">More...</a><br/></td></tr>
<tr class="separator:a509029513d2d0671c81cb9f4fda7fd47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaf8a6e9e2103ce35f4d534dca6ebc63e"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#ac5ec7329b5be4722abc3cef6ef2e9c1b">T</a>:1</td></tr>
<tr class="memdesc:aaf8a6e9e2103ce35f4d534dca6ebc63e"><td class="mdescLeft"> </td><td class="mdescRight">bit: 5 Thumb execution state bit <a href="#aaf8a6e9e2103ce35f4d534dca6ebc63e">More...</a><br/></td></tr>
<tr class="separator:aaf8a6e9e2103ce35f4d534dca6ebc63e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7d329d88dc139fc7abcef306e527c7cc"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a20bbf5d5ba32cae380b7f181cf306f9e">F</a>:1</td></tr>
<tr class="memdesc:a7d329d88dc139fc7abcef306e527c7cc"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6 FIQ mask bit <a href="#a7d329d88dc139fc7abcef306e527c7cc">More...</a><br/></td></tr>
<tr class="separator:a7d329d88dc139fc7abcef306e527c7cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a886fc4b6fa4d00d467fde41743eff95c"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a0d277e8b4d2147137407f526aa9e3214">I</a>:1</td></tr>
<tr class="memdesc:a886fc4b6fa4d00d467fde41743eff95c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 7 IRQ mask bit <a href="#a886fc4b6fa4d00d467fde41743eff95c">More...</a><br/></td></tr>
<tr class="separator:a886fc4b6fa4d00d467fde41743eff95c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0b1db505547e12f34498aad5ab40a278"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a8dc2435a7c376c9b8dfdd9748c091458">A</a>:1</td></tr>
<tr class="memdesc:a0b1db505547e12f34498aad5ab40a278"><td class="mdescLeft"> </td><td class="mdescRight">bit: 8 Asynchronous abort mask bit <a href="#a0b1db505547e12f34498aad5ab40a278">More...</a><br/></td></tr>
<tr class="separator:a0b1db505547e12f34498aad5ab40a278"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a07fd82ad0fdfe3a961c0ce6bc34b90c5"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a96bd175ed9927279dba40e76259dcfa7">E</a>:1</td></tr>
<tr class="memdesc:a07fd82ad0fdfe3a961c0ce6bc34b90c5"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Endianness execution state bit <a href="#a07fd82ad0fdfe3a961c0ce6bc34b90c5">More...</a><br/></td></tr>
<tr class="separator:a07fd82ad0fdfe3a961c0ce6bc34b90c5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a134b43540e84011412191db0ed62be78"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a8bdd87822e3c00b3742c94a42b0654b9">IT1</a>:6</td></tr>
<tr class="memdesc:a134b43540e84011412191db0ed62be78"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10..15 If-Then execution state bits 2-7 <a href="#a134b43540e84011412191db0ed62be78">More...</a><br/></td></tr>
<tr class="separator:a134b43540e84011412191db0ed62be78"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae7de2455aa2f72b90e4e5e7f50ccbfe9"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#acc18314a4088adfb93a9662c76073704">GE</a>:4</td></tr>
<tr class="memdesc:ae7de2455aa2f72b90e4e5e7f50ccbfe9"><td class="mdescLeft"> </td><td class="mdescRight">bit: 16..19 Greater than or Equal flags <a href="#ae7de2455aa2f72b90e4e5e7f50ccbfe9">More...</a><br/></td></tr>
<tr class="separator:ae7de2455aa2f72b90e4e5e7f50ccbfe9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab4427dfe1b30a992b3283e9999a0bd3b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a5d4e06d8dba8f512c54b16bfa7150d9d">J</a>:1</td></tr>
<tr class="memdesc:ab4427dfe1b30a992b3283e9999a0bd3b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 24 Jazelle bit <a href="#ab4427dfe1b30a992b3283e9999a0bd3b">More...</a><br/></td></tr>
<tr class="separator:ab4427dfe1b30a992b3283e9999a0bd3b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a783b22f93f2b14fa161702ae0572cea4"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a5299532c92c92babc22517a433686b95">IT0</a>:2</td></tr>
<tr class="memdesc:a783b22f93f2b14fa161702ae0572cea4"><td class="mdescLeft"> </td><td class="mdescRight">bit: 25..26 If-Then execution state bits 0-1 <a href="#a783b22f93f2b14fa161702ae0572cea4">More...</a><br/></td></tr>
<tr class="separator:a783b22f93f2b14fa161702ae0572cea4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adf97a71bbd0e1b110cd4bf29e64bc4ab"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a0bdcd0ceaa1ecb8f55ea15075974eb5a">Q</a>:1</td></tr>
<tr class="memdesc:adf97a71bbd0e1b110cd4bf29e64bc4ab"><td class="mdescLeft"> </td><td class="mdescRight">bit: 27 Saturation condition flag <a href="#adf97a71bbd0e1b110cd4bf29e64bc4ab">More...</a><br/></td></tr>
<tr class="separator:adf97a71bbd0e1b110cd4bf29e64bc4ab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a41fb45a17a81876943f1995133172e7d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#aba74c9da04be21f1266d3816af79f8c3">V</a>:1</td></tr>
<tr class="memdesc:a41fb45a17a81876943f1995133172e7d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Overflow condition code flag <a href="#a41fb45a17a81876943f1995133172e7d">More...</a><br/></td></tr>
<tr class="separator:a41fb45a17a81876943f1995133172e7d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2f63d6065415d533468b9d53b41cd18f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#aa967d0e42ed00bd886b2c6df6f49a7e2">C</a>:1</td></tr>
<tr class="memdesc:a2f63d6065415d533468b9d53b41cd18f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Carry condition code flag <a href="#a2f63d6065415d533468b9d53b41cd18f">More...</a><br/></td></tr>
<tr class="separator:a2f63d6065415d533468b9d53b41cd18f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac872cff099487b4ae8244ae860d0e251"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a790f1950658257a87ac58d132eca9849">Z</a>:1</td></tr>
<tr class="memdesc:ac872cff099487b4ae8244ae860d0e251"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Zero condition code flag <a href="#ac872cff099487b4ae8244ae860d0e251">More...</a><br/></td></tr>
<tr class="separator:ac872cff099487b4ae8244ae860d0e251"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6bbd85cb1c0830b4c1d3bb7d65c68e01"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCPSR__Type.html#a26907b41c086a9f9e7b8c7051481c643">N</a>:1</td></tr>
<tr class="memdesc:a6bbd85cb1c0830b4c1d3bb7d65c68e01"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Negative condition code flag <a href="#a6bbd85cb1c0830b4c1d3bb7d65c68e01">More...</a><br/></td></tr>
<tr class="separator:a6bbd85cb1c0830b4c1d3bb7d65c68e01"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2e735da6b6156874d12aaceb2017da06"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPSR__Type.html#a2e735da6b6156874d12aaceb2017da06">b</a></td></tr>
<tr class="memdesc:a2e735da6b6156874d12aaceb2017da06"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a2e735da6b6156874d12aaceb2017da06">More...</a><br/></td></tr>
<tr class="separator:a2e735da6b6156874d12aaceb2017da06"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afd5ed10bab25f324a6fbb3e124d16fc9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPSR__Type.html#afd5ed10bab25f324a6fbb3e124d16fc9">w</a></td></tr>
<tr class="memdesc:afd5ed10bab25f324a6fbb3e124d16fc9"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#afd5ed10bab25f324a6fbb3e124d16fc9">More...</a><br/></td></tr>
<tr class="separator:afd5ed10bab25f324a6fbb3e124d16fc9"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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<div class="title">DFSR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__DFSR.html">Data Fault Status Register (DFSR)</a></div></div> </div>
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<p>Bit field declaration for DFSR layout.
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a54c2eb668436a0f15d781265ceaa8c58"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:acdca7fbb1d1ada6afc315479e5a87f75"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#af29edf59ecfd29848b69e2bbfb7f3082">FS0</a>:4</td></tr>
<tr class="memdesc:acdca7fbb1d1ada6afc315479e5a87f75"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 3 Fault Status bits bit 0-3 <a href="#acdca7fbb1d1ada6afc315479e5a87f75">More...</a><br/></td></tr>
<tr class="separator:acdca7fbb1d1ada6afc315479e5a87f75"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0fe0bb74414f5c770932127140f04423"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a38982c7088a4069f8a4b347f5eb400e9">Domain</a>:4</td></tr>
<tr class="memdesc:a0fe0bb74414f5c770932127140f04423"><td class="mdescLeft"> </td><td class="mdescRight">bit: 4.. 7 Fault on which domain <a href="#a0fe0bb74414f5c770932127140f04423">More...</a><br/></td></tr>
<tr class="separator:a0fe0bb74414f5c770932127140f04423"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a68ab5dfdd0d9c208a7f487b1c1ba86ac"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#add7c7800b87cabdb4a9ecdf41e4469a7">LPAE</a>:1</td></tr>
<tr class="memdesc:a68ab5dfdd0d9c208a7f487b1c1ba86ac"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Large Physical Address Extension <a href="#a68ab5dfdd0d9c208a7f487b1c1ba86ac">More...</a><br/></td></tr>
<tr class="separator:a68ab5dfdd0d9c208a7f487b1c1ba86ac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a40f79f0cae52396cb658f442d8b72fcf"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a869658f432d5e213b8cd55e8e58d1f56">FS1</a>:1</td></tr>
<tr class="memdesc:a40f79f0cae52396cb658f442d8b72fcf"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10 Fault Status bits bit 4 <a href="#a40f79f0cae52396cb658f442d8b72fcf">More...</a><br/></td></tr>
<tr class="separator:a40f79f0cae52396cb658f442d8b72fcf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab71a926ecceb53514d9c4ea53e478a3b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a0512860c27723cd35f0abdaa68be9935">WnR</a>:1</td></tr>
<tr class="memdesc:ab71a926ecceb53514d9c4ea53e478a3b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 11 Write not Read bit <a href="#ab71a926ecceb53514d9c4ea53e478a3b">More...</a><br/></td></tr>
<tr class="separator:ab71a926ecceb53514d9c4ea53e478a3b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7e2d32981d01b0ea2316582273490c0d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#aede34079d030df1977646c155a90f445">ExT</a>:1</td></tr>
<tr class="memdesc:a7e2d32981d01b0ea2316582273490c0d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 External abort type <a href="#a7e2d32981d01b0ea2316582273490c0d">More...</a><br/></td></tr>
<tr class="separator:a7e2d32981d01b0ea2316582273490c0d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1a89a92e585211c2934dbd4976d2bf33"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a38562a26cc210ea4c39c6b951c4a5b62">CM</a>:1</td></tr>
<tr class="memdesc:a1a89a92e585211c2934dbd4976d2bf33"><td class="mdescLeft"> </td><td class="mdescRight">bit: 13 Cache maintenance fault <a href="#a1a89a92e585211c2934dbd4976d2bf33">More...</a><br/></td></tr>
<tr class="separator:a1a89a92e585211c2934dbd4976d2bf33"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a54c2eb668436a0f15d781265ceaa8c58"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDFSR__Type.html#a54c2eb668436a0f15d781265ceaa8c58">s</a></td></tr>
<tr class="memdesc:a54c2eb668436a0f15d781265ceaa8c58"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access in short format. <a href="#a54c2eb668436a0f15d781265ceaa8c58">More...</a><br/></td></tr>
<tr class="separator:a54c2eb668436a0f15d781265ceaa8c58"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a583e3138696be655c46f297e083ece52"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a6d2960e8890b3fb481f57bc0ee4871a9"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a4cb3ba7b8c8075bfbff792b7e5b88103">STATUS</a>:5</td></tr>
<tr class="memdesc:a6d2960e8890b3fb481f57bc0ee4871a9"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 5 Fault Status bits <a href="#a6d2960e8890b3fb481f57bc0ee4871a9">More...</a><br/></td></tr>
<tr class="separator:a6d2960e8890b3fb481f57bc0ee4871a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af2bc70888f77e671927a0c4a3be641ad"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#add7c7800b87cabdb4a9ecdf41e4469a7">LPAE</a>:1</td></tr>
<tr class="memdesc:af2bc70888f77e671927a0c4a3be641ad"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Large Physical Address Extension <a href="#af2bc70888f77e671927a0c4a3be641ad">More...</a><br/></td></tr>
<tr class="separator:af2bc70888f77e671927a0c4a3be641ad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae0e7c10ef644ec3de8339375024c1e56"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a0512860c27723cd35f0abdaa68be9935">WnR</a>:1</td></tr>
<tr class="memdesc:ae0e7c10ef644ec3de8339375024c1e56"><td class="mdescLeft"> </td><td class="mdescRight">bit: 11 Write not Read bit <a href="#ae0e7c10ef644ec3de8339375024c1e56">More...</a><br/></td></tr>
<tr class="separator:ae0e7c10ef644ec3de8339375024c1e56"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3cde449f610e5e1822372b3b7a6aade8"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#aede34079d030df1977646c155a90f445">ExT</a>:1</td></tr>
<tr class="memdesc:a3cde449f610e5e1822372b3b7a6aade8"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 External abort type <a href="#a3cde449f610e5e1822372b3b7a6aade8">More...</a><br/></td></tr>
<tr class="separator:a3cde449f610e5e1822372b3b7a6aade8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9f2e41ff2e5a4dd860b4607b026f0613"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionDFSR__Type.html#a38562a26cc210ea4c39c6b951c4a5b62">CM</a>:1</td></tr>
<tr class="memdesc:a9f2e41ff2e5a4dd860b4607b026f0613"><td class="mdescLeft"> </td><td class="mdescRight">bit: 13 Cache maintenance fault <a href="#a9f2e41ff2e5a4dd860b4607b026f0613">More...</a><br/></td></tr>
<tr class="separator:a9f2e41ff2e5a4dd860b4607b026f0613"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a583e3138696be655c46f297e083ece52"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDFSR__Type.html#a583e3138696be655c46f297e083ece52">l</a></td></tr>
<tr class="memdesc:a583e3138696be655c46f297e083ece52"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access in long format. <a href="#a583e3138696be655c46f297e083ece52">More...</a><br/></td></tr>
<tr class="separator:a583e3138696be655c46f297e083ece52"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad827a36e38ce2dee796835122ae95dd2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDFSR__Type.html#ad827a36e38ce2dee796835122ae95dd2">w</a></td></tr>
<tr class="memdesc:ad827a36e38ce2dee796835122ae95dd2"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#ad827a36e38ce2dee796835122ae95dd2">More...</a><br/></td></tr>
<tr class="separator:ad827a36e38ce2dee796835122ae95dd2"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">uint32_t DFSR_Type::CM</td>
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</div>
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<a class="anchor" id="a38982c7088a4069f8a4b347f5eb400e9"></a>
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<td class="memname">uint32_t DFSR_Type::Domain</td>
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<td class="memname">uint32_t DFSR_Type::ExT</td>
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<td class="memname">uint32_t DFSR_Type::FS0</td>
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<div class="title">IFSR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__IFSR.html">Instruction Fault Status Register (IFSR)</a></div></div> </div>
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<p>Bit field declaration for IFSR layout.
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a4ece60d66e87e10e78aab83ac05e957c"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:abbd6200d33704e915dbe34741e69429d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#a9f9ae1ffa89d33e90159eec5c4b7cd6a">FS0</a>:4</td></tr>
<tr class="memdesc:abbd6200d33704e915dbe34741e69429d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 3 Fault Status bits bit 0-3 <a href="#abbd6200d33704e915dbe34741e69429d">More...</a><br/></td></tr>
<tr class="separator:abbd6200d33704e915dbe34741e69429d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5ac817497bfc9e4d6a2c68c2bf1ae10b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#a40c5236caf0549cc1cc78945b0b0f131">LPAE</a>:1</td></tr>
<tr class="memdesc:a5ac817497bfc9e4d6a2c68c2bf1ae10b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Large Physical Address Extension <a href="#a5ac817497bfc9e4d6a2c68c2bf1ae10b">More...</a><br/></td></tr>
<tr class="separator:a5ac817497bfc9e4d6a2c68c2bf1ae10b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a62b36f8cda762e0ec19114c4811b9e13"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#adb493acf17881eaf09a2e8629ee2243e">FS1</a>:1</td></tr>
<tr class="memdesc:a62b36f8cda762e0ec19114c4811b9e13"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10 Fault Status bits bit 4 <a href="#a62b36f8cda762e0ec19114c4811b9e13">More...</a><br/></td></tr>
<tr class="separator:a62b36f8cda762e0ec19114c4811b9e13"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a67c88d6c3940c97a376618254404bd74"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#aee6fed7525c5125e637acc8e957c8d0f">ExT</a>:1</td></tr>
<tr class="memdesc:a67c88d6c3940c97a376618254404bd74"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 External abort type <a href="#a67c88d6c3940c97a376618254404bd74">More...</a><br/></td></tr>
<tr class="separator:a67c88d6c3940c97a376618254404bd74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4ece60d66e87e10e78aab83ac05e957c"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIFSR__Type.html#a4ece60d66e87e10e78aab83ac05e957c">s</a></td></tr>
<tr class="memdesc:a4ece60d66e87e10e78aab83ac05e957c"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access in short format. <a href="#a4ece60d66e87e10e78aab83ac05e957c">More...</a><br/></td></tr>
<tr class="separator:a4ece60d66e87e10e78aab83ac05e957c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f4e4fe46a9cb9b6c8a6355f9b0938e3"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:ab7437299b4401d9f78110fa106c3f2d8"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#a543066fc60d5b63478cc85ba082524d4">STATUS</a>:6</td></tr>
<tr class="memdesc:ab7437299b4401d9f78110fa106c3f2d8"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 5 Fault Status bits <a href="#ab7437299b4401d9f78110fa106c3f2d8">More...</a><br/></td></tr>
<tr class="separator:ab7437299b4401d9f78110fa106c3f2d8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac31abeae370c3d6818c7983509c78b4b"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#a40c5236caf0549cc1cc78945b0b0f131">LPAE</a>:1</td></tr>
<tr class="memdesc:ac31abeae370c3d6818c7983509c78b4b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9 Large Physical Address Extension <a href="#ac31abeae370c3d6818c7983509c78b4b">More...</a><br/></td></tr>
<tr class="separator:ac31abeae370c3d6818c7983509c78b4b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6b02f9f87b2af44ce432793fa33894fb"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIFSR__Type.html#aee6fed7525c5125e637acc8e957c8d0f">ExT</a>:1</td></tr>
<tr class="memdesc:a6b02f9f87b2af44ce432793fa33894fb"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 External abort type <a href="#a6b02f9f87b2af44ce432793fa33894fb">More...</a><br/></td></tr>
<tr class="separator:a6b02f9f87b2af44ce432793fa33894fb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8f4e4fe46a9cb9b6c8a6355f9b0938e3"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIFSR__Type.html#a8f4e4fe46a9cb9b6c8a6355f9b0938e3">l</a></td></tr>
<tr class="memdesc:a8f4e4fe46a9cb9b6c8a6355f9b0938e3"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access in long format. <a href="#a8f4e4fe46a9cb9b6c8a6355f9b0938e3">More...</a><br/></td></tr>
<tr class="separator:a8f4e4fe46a9cb9b6c8a6355f9b0938e3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae31262477d14b86f30c3bef90a3fc371"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIFSR__Type.html#ae31262477d14b86f30c3bef90a3fc371">w</a></td></tr>
<tr class="memdesc:ae31262477d14b86f30c3bef90a3fc371"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#ae31262477d14b86f30c3bef90a3fc371">More...</a><br/></td></tr>
<tr class="separator:ae31262477d14b86f30c3bef90a3fc371"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Bit field declaration for ISR layout.
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<tr class="memitem:ad01f116d61c2ae79c2469a38a0b2f497"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a92fcac62e6b254f6c692d9133884247d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionISR__Type.html#ae691a856f7de0f301c60521a7a779dc2">F</a>:1</td></tr>
<tr class="memdesc:a92fcac62e6b254f6c692d9133884247d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 6 FIQ pending bit <a href="#a92fcac62e6b254f6c692d9133884247d">More...</a><br/></td></tr>
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<tr class="memdesc:a172cf5c0223af615f6e87c5fd9904490"><td class="mdescLeft"> </td><td class="mdescRight">bit: 7 IRQ pending bit <a href="#a172cf5c0223af615f6e87c5fd9904490">More...</a><br/></td></tr>
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<tr class="memdesc:a61b81eaf375fbf6ad936475c4797bb14"><td class="mdescLeft"> </td><td class="mdescRight">bit: 8 External abort pending bit <a href="#a61b81eaf375fbf6ad936475c4797bb14">More...</a><br/></td></tr>
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<tr class="memitem:ad01f116d61c2ae79c2469a38a0b2f497"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionISR__Type.html#ad01f116d61c2ae79c2469a38a0b2f497">b</a></td></tr>
<tr class="memdesc:ad01f116d61c2ae79c2469a38a0b2f497"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#ad01f116d61c2ae79c2469a38a0b2f497">More...</a><br/></td></tr>
<tr class="separator:ad01f116d61c2ae79c2469a38a0b2f497"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4fca9c1057aa8a6006f1fb631a28ee30"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionISR__Type.html#a4fca9c1057aa8a6006f1fb631a28ee30">w</a></td></tr>
<tr class="memdesc:a4fca9c1057aa8a6006f1fb631a28ee30"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a4fca9c1057aa8a6006f1fb631a28ee30">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Bit field declaration for SCTLR layout.
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<tr class="memitem:a21ec59a37644281456a5f607450951d8"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:aee870fcf59accda9d93005b885db4e68"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a8cbfde3ba235ebd48e82cb314c9b9cc4">M</a>:1</td></tr>
<tr class="memdesc:aee870fcf59accda9d93005b885db4e68"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 MMU enable <a href="#aee870fcf59accda9d93005b885db4e68">More...</a><br/></td></tr>
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<tr class="memdesc:a9492fdd4500a9a7e596c0bf159017a38"><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Alignment check enable <a href="#a9492fdd4500a9a7e596c0bf159017a38">More...</a><br/></td></tr>
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<tr class="memdesc:aad882f21882a931a26abae1731600052"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 Cache enable <a href="#aad882f21882a931a26abae1731600052">More...</a><br/></td></tr>
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<tr class="memitem:ac59e580e268394e9e90a095c16563a9e"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a98b55213f3bf0a8bd4f1db90512238de">CP15BEN</a>:1</td></tr>
<tr class="memdesc:ac59e580e268394e9e90a095c16563a9e"><td class="mdescLeft"> </td><td class="mdescRight">bit: 5 CP15 barrier enable <a href="#ac59e580e268394e9e90a095c16563a9e">More...</a><br/></td></tr>
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<tr class="memdesc:a90c07e688b7dd59e8573d9713a28e918"><td class="mdescLeft"> </td><td class="mdescRight">bit: 7 Endianness model <a href="#a90c07e688b7dd59e8573d9713a28e918">More...</a><br/></td></tr>
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<tr class="memdesc:a8ee8275c8955af4214a3cd30964d9d4c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 10 SWP and SWPB enable <a href="#a8ee8275c8955af4214a3cd30964d9d4c">More...</a><br/></td></tr>
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<tr class="memdesc:a09f1b3d0c58bd829eede242dc4aa7742"><td class="mdescLeft"> </td><td class="mdescRight">bit: 11 Branch prediction enable <a href="#a09f1b3d0c58bd829eede242dc4aa7742">More...</a><br/></td></tr>
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<tr class="memdesc:a3a66d2af2ed13e551f9cf5251296da27"><td class="mdescLeft"> </td><td class="mdescRight">bit: 12 Instruction cache enable <a href="#a3a66d2af2ed13e551f9cf5251296da27">More...</a><br/></td></tr>
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<tr class="memitem:ac3255ae7d32a953d8b590e8b04c88439"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a9a3885d0e2ba2433d128f62ec2552a00">V</a>:1</td></tr>
<tr class="memdesc:ac3255ae7d32a953d8b590e8b04c88439"><td class="mdescLeft"> </td><td class="mdescRight">bit: 13 Vectors bit <a href="#ac3255ae7d32a953d8b590e8b04c88439">More...</a><br/></td></tr>
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<tr class="memitem:a20926a14c1963b5faa47f39743b4be86"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055">RR</a>:1</td></tr>
<tr class="memdesc:a20926a14c1963b5faa47f39743b4be86"><td class="mdescLeft"> </td><td class="mdescRight">bit: 14 Round Robin select <a href="#a20926a14c1963b5faa47f39743b4be86">More...</a><br/></td></tr>
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<tr class="memitem:a502e8aceb66e14fe2a77a08da124f450"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#aba2a8aac3478cdc34428af7b9726d97f">HA</a>:1</td></tr>
<tr class="memdesc:a502e8aceb66e14fe2a77a08da124f450"><td class="mdescLeft"> </td><td class="mdescRight">bit: 17 Hardware Access flag enable <a href="#a502e8aceb66e14fe2a77a08da124f450">More...</a><br/></td></tr>
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<tr class="memitem:aefd070d6ee9f3513bcce13f5be0599a4"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a551d0505856acaef4dd1ecca54cb540d">WXN</a>:1</td></tr>
<tr class="memdesc:aefd070d6ee9f3513bcce13f5be0599a4"><td class="mdescLeft"> </td><td class="mdescRight">bit: 19 Write permission implies XN <a href="#aefd070d6ee9f3513bcce13f5be0599a4">More...</a><br/></td></tr>
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<tr class="memitem:a4998de3b09d2c15b8facd4f0f3274616"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a32873e90e6814c3a2fc1b1c79c0bc8c8">UWXN</a>:1</td></tr>
<tr class="memdesc:a4998de3b09d2c15b8facd4f0f3274616"><td class="mdescLeft"> </td><td class="mdescRight">bit: 20 Unprivileged write permission implies PL1 XN <a href="#a4998de3b09d2c15b8facd4f0f3274616">More...</a><br/></td></tr>
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<tr class="memitem:a5baee3d49f17ae03176bec8340bd4d59"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc">FI</a>:1</td></tr>
<tr class="memdesc:a5baee3d49f17ae03176bec8340bd4d59"><td class="mdescLeft"> </td><td class="mdescRight">bit: 21 Fast interrupts configuration enable <a href="#a5baee3d49f17ae03176bec8340bd4d59">More...</a><br/></td></tr>
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<tr class="memitem:a1cd17f69c735dd44c7f07738a4da7b47"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a1ca6569db52bca6250afbbd565d05449">U</a>:1</td></tr>
<tr class="memdesc:a1cd17f69c735dd44c7f07738a4da7b47"><td class="mdescLeft"> </td><td class="mdescRight">bit: 22 Alignment model <a href="#a1cd17f69c735dd44c7f07738a4da7b47">More...</a><br/></td></tr>
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<tr class="memdesc:a6f7a63c4c3902ef2f9efa30788b3df7c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 24 Interrupt Vectors Enable <a href="#a6f7a63c4c3902ef2f9efa30788b3df7c">More...</a><br/></td></tr>
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<tr class="memdesc:ab23af569bdda48e5e10e649c33e7a18b"><td class="mdescLeft"> </td><td class="mdescRight">bit: 25 Exception Endianness <a href="#ab23af569bdda48e5e10e649c33e7a18b">More...</a><br/></td></tr>
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<tr class="memitem:a1f782067130fabb7871ab5e81846024d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a60d589567422115a14d6d0fde342dfce">NMFI</a>:1</td></tr>
<tr class="memdesc:a1f782067130fabb7871ab5e81846024d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 27 Non-maskable FIQ (NMFI) support <a href="#a1f782067130fabb7871ab5e81846024d">More...</a><br/></td></tr>
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<tr class="memitem:a09f921ddcda22ce695c9f9074370c70c"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#abc3055203ce7f9d117ceb10f146722f3">TRE</a>:1</td></tr>
<tr class="memdesc:a09f921ddcda22ce695c9f9074370c70c"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 TEX remap enable. <a href="#a09f921ddcda22ce695c9f9074370c70c">More...</a><br/></td></tr>
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<tr class="memitem:a375f85e72f3f61f58dbe4763d58c77e7"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#ae5a729bf64a6de4cbfa42c1a7d254535">AFE</a>:1</td></tr>
<tr class="memdesc:a375f85e72f3f61f58dbe4763d58c77e7"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Access flag enable <a href="#a375f85e72f3f61f58dbe4763d58c77e7">More...</a><br/></td></tr>
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<tr class="memitem:ac58fc5f8b7d0bf6311410c23cb5fb28d"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionSCTLR__Type.html#a25d4c4cf4df168a30cc4600a130580ab">TE</a>:1</td></tr>
<tr class="memdesc:ac58fc5f8b7d0bf6311410c23cb5fb28d"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Thumb Exception enable <a href="#ac58fc5f8b7d0bf6311410c23cb5fb28d">More...</a><br/></td></tr>
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<tr class="memitem:a21ec59a37644281456a5f607450951d8"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#a21ec59a37644281456a5f607450951d8">b</a></td></tr>
<tr class="memdesc:a21ec59a37644281456a5f607450951d8"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a21ec59a37644281456a5f607450951d8">More...</a><br/></td></tr>
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<tr class="memitem:a4cb084e09742794f1d040c4e44ee4e0f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#a4cb084e09742794f1d040c4e44ee4e0f">w</a></td></tr>
<tr class="memdesc:a4cb084e09742794f1d040c4e44ee4e0f"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a4cb084e09742794f1d040c4e44ee4e0f">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/unionSCTLR__Type.html | HTML | apache-2.0 | 26,089 |
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="title">Using CMSIS with generic Arm Processors </div> </div>
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<div class="textblock"><p>Arm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors. These files can be used when standard Arm processors should be used in a project. The table below lists the folder and device names of the Arm processors.</p>
<table class="cmtable">
<tr>
<th>Folder </th><th>Processor </th><th>Description </th></tr>
<tr>
<td>".\Device\ARM\ARMCA5" </td><td>Cortex-A5 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-A5 processor. The device name is ARMCA5 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCA5.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCA7" </td><td>Cortex-A7 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-A7 processor. The device name is ARMCA7 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCA7.h>. </td></tr>
<tr>
<td>".\Device\ARM\ARMCA9" </td><td>Cortex-A9 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-A9 processor. The device name is ARMCA9 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <<a class="el" href="ARMCA9_8h.html">ARMCA9.h</a>>. </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><em>device</em>.h</b> file of a project. This allows you to generate generic software components that adjust to the device settings. </dd></dl>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/using_ARM_pg.html | HTML | apache-2.0 | 8,159 |
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<div id="projectname">CMSIS-Core (Cortex-A)
 <span id="projectnumber">Version 1.1.4</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="textblock"><p>A typical example for using the CMSIS layer is provided below. The example is based on an unspecific Cortex-A9 Device.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include <<a class="code" href="ARMCA9_8h.html">ARMCA9.h</a>></span> <span class="comment">// File name depends on device used</span></div>
<div class="line"> </div>
<div class="line"><span class="keyword">static</span> <span class="keyword">const</span> uint32_t TICK_RATE_HZ = 1000U;</div>
<div class="line"> </div>
<div class="line">uint32_t <span class="keyword">volatile</span> msTicks; <span class="comment">// Counter for millisecond Interval</span></div>
<div class="line"> </div>
<div class="line"><span class="keyword">static</span> <span class="keywordtype">void</span> SysTick_Handler( <span class="keywordtype">void</span> )</div>
<div class="line">{</div>
<div class="line"> msTicks++; <span class="comment">// Increment Counter</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="comment">// We use the Private Tiemer (PTIM) of the Cortex-A9 FVP Model here.</span></div>
<div class="line"><span class="comment">// In general the available Timers are highly vendor specific for Cortex-A processors.</span></div>
<div class="line"><span class="keywordtype">void</span> private_timer_init(<span class="keywordtype">void</span>) {</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__PTM__timer__functions.html#ga30516fed24977be8eecf3efd8b6a2fea">PTIM_SetLoadValue</a> ((<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>/TICK_RATE_HZ) - 1U);</div>
<div class="line"> <a class="code" href="group__PTM__timer__functions.html#gaabc1dba029389fe0e2a6297952df7972">PTIM_SetControl</a> (<a class="code" href="group__PTM__timer__functions.html#ga34f0ceea142a4be1479cb552bf8bc4d1">PTIM_GetControl</a>() | 7U);</div>
<div class="line"></div>
<div class="line"> <span class="comment">/* Install SysTick_Handler as the interrupt function for PTIM */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3">IRQ_SetHandler</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a>, SysTick_Handler);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Determine number of implemented priority bits */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> ((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a>, <a class="code" href="group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa">IRQ_PRIORITY_Msk</a>);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Set lowest priority -1 */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2">IRQ_SetPriority</a> ((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)<a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a>, <a class="code" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a>((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)PrivTimer_IRQn)-1);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Enable IRQ */</span></div>
<div class="line"> <a class="code" href="group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7">IRQ_Enable</a> ((<a class="code" href="irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2">IRQn_ID_t</a>)PrivTimer_IRQn);</div>
<div class="line">}</div>
<div class="line"></div>
<div class="line"><span class="comment">/* Delay execution for given amount of ticks */</span></div>
<div class="line"><span class="keywordtype">void</span> Delay(uint32_t ticks) {</div>
<div class="line"> uint32_t tgtTicks = msTicks + ticks; <span class="comment">// target tick count to delay execution to</span></div>
<div class="line"> <span class="keywordflow">while</span> (msTicks == tgtTicks) {</div>
<div class="line"> <a class="code" href="group__CMSIS__Core__InstructionInterface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d">__WFE</a> (); <span class="comment">// Power-Down until next Event/Interrupt</span></div>
<div class="line"> }</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"><span class="comment">/* main function */</span></div>
<div class="line"><span class="keywordtype">int</span> main(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line"> <span class="comment">/* Initialize device HAL here */</span></div>
<div class="line"> private_timer_init();</div>
<div class="line"> </div>
<div class="line"> <span class="keyword">static</span> uint8_t ledState = 0;</div>
<div class="line"> </div>
<div class="line"> <span class="comment">/* Infinite loop */</span></div>
<div class="line"> <span class="keywordflow">while</span> (1)</div>
<div class="line"> {</div>
<div class="line"> <span class="comment">/* Add application code here */</span></div>
<div class="line"> ledState = !ledState;</div>
<div class="line"> Delay(500);</div>
<div class="line"> }</div>
<div class="line">}</div>
</div><!-- fragment --><p>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><em>device</em>.h</b> file of a project. This allows you to generate generic software components that use the device selected in a project.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include "RTE_Components.h"</span> <span class="comment">// include information about project configuration</span></div>
<div class="line"><span class="preprocessor">#include CMSIS_device_header // include <device>.h file</span></div>
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 <span id="projectnumber">Version 1.1.4</span>
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<div class="header">
<div class="headertitle">
<div class="title">Using CMSIS in Embedded Applications </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>To use the CMSIS-Core-A the following files are added to the embedded application:</p>
<ul>
<li><a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> with reset handler and exception vectors.</li>
<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> with general device configuration (i.e. for clock and bus setup).</li>
<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a> gives access to processor core and all peripherals.</li>
<li><a class="el" href="mem_h_pg.html">Memory Configuration Files mem_<device>.h</a> contains basic memory configurations.</li>
<li><a class="el" href="mmu_c_pg.html">Memory Management Unit Files mmu_<device>.c</a> contains the memory management unit setup.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>The files <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a>, <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a>, <a class="el" href="mem_h_pg.html">Memory Configuration Files mem_<device>.h</a>, and <a class="el" href="mmu_c_pg.html">Memory Management Unit Files mmu_<device>.c</a> may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.</dd></dl>
<p>The <a class="el" href="startup__ARMCA9_8c.html#ae7ee340978f5c25f52f0cad1457c6616">Reset_Handler</a> defined in <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> is executed after reset. The default initialization sequence is</p>
<ul>
<li>set the vector base address register (<a class="el" href="group__CMSIS__VBAR.html#ga582f9a60f7b090ae5a4e8f60ef3b79f8">__set_VBAR</a>),</li>
<li>set stacks for each exception mode (<a class="el" href="cmsis__armcc_8h.html#a306b0a932918f2243a40d4e855503be2">__set_mode</a>, <a class="el" href="group__CMSIS__SP.html#ga6af63cb939bd108aef1c0f12622350cb">__set_SP</a>),</li>
<li>call <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>.</li>
</ul>
<p>After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the <b>main</b> function in the user code. In addition the <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> contains a weak default handler implementation for every exception. It may also contain stack and heap configurations for the user application.</p>
<p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface and floating point unit. The variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> indicates the CPU clock speed. <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a> describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration.</p>
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is the central include file that the application programmer is using in the C/C++ source code. It provides the following features:</p>
<ul>
<li><a class="el" href="group__peripheral__gr.html">Peripheral Access</a> provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.</li>
<li><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a> can be accessed with standardized symbols and functions for the General Interrupt Controller (GIC) are provided.</li>
<li><a class="el" href="group__CMSIS__Core__InstructionInterface.html">Intrinsic Functions</a> allow to access special instructions, for example for activating sleep mode or the NOP instruction.</li>
<li><a class="el" href="group__PL1__timer__functions.html">Generic</a> and <a class="el" href="group__PTM__timer__functions.html">Private</a> Timer functions to configure and start a periodic timer interrupt.</li>
<li><a class="el" href="group__L1__cache__functions.html">Level 1</a> and <a class="el" href="group__L2__cache__functions.html">Level 2</a> Cache controller functions to enable, disable, clean and invalidate caches.</li>
</ul>
<p>CMSIS-Pack provides the <b>#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to this <b><em>device</em>.h</b> file.</p>
<div class="image">
<img src="CMSIS_CORE_A_Files_user.png" alt="CMSIS_CORE_A_Files_user.png"/>
<div class="caption">
CMSIS-Core-A User Files</div></div>
<p> The CMSIS-Core-A user files are device specific. In addition, the <a class="el" href="startup_c_pg.html">Startup File startup_<device>.c</a> is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.</p>
<dl class="section note"><dt>Note</dt><dd>The silicon vendors create these device-specific CMSIS-Core-A files based on <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> provide by Arm.</dd></dl>
<p>Thereafter, the functions described under <a href="Modules.html"><b>Reference</b> </a> can be used in the application.</p>
<p><b>Examples</b> </p>
<ul>
<li><a class="el" href="using_CMSIS.html">Basic CMSIS Example</a> is a simple example that shows the usage of the CMSIS layer.</li>
<li><a class="el" href="using_ARM_pg.html">Using CMSIS with generic Arm Processors</a> explains how to use CMSIS-Core-M for Arm processors. </li>
</ul>
</div></div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
<li class="footer">Generated on Wed Jul 10 2019 15:20:27 for CMSIS-Core (Cortex-A) Version 1.1.4 by Arm Ltd. All rights reserved.
<!--
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/using_pg.html | HTML | apache-2.0 | 12,428 |
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[
[ "Basic CMSIS Example", "using_CMSIS.html", null ],
[ "Using CMSIS with generic Arm Processors", "using_ARM_pg.html", null ]
]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core_A/html/using_pg.js | JavaScript | apache-2.0 | 153 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/DAP/html/cmsis.css | CSS | apache-2.0 | 20,795 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/DAP/html/dap_revisionHistory.html | HTML | apache-2.0 | 6,756 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/DAP/html/dir_7a3f7b856c1d77e4a9a9049e84d3db8d.html | HTML | apache-2.0 | 5,948 |
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<p>Commands between Debug Unit and host computer.
<a href="#details">More...</a></p>
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Content</h2></td></tr>
<tr class="memitem:group__DAP__genCommands__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__genCommands__gr.html">General Commands</a></td></tr>
<tr class="memdesc:group__DAP__genCommands__gr"><td class="mdescLeft"> </td><td class="mdescRight">Information and Control commands for the CMSIS-DAP Debug Unit. <br/></td></tr>
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<tr class="memitem:group__DAP__swj__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__swj__gr.html">Common SWD/JTAG Commands</a></td></tr>
<tr class="memdesc:group__DAP__swj__gr"><td class="mdescLeft"> </td><td class="mdescRight">Set SWD/JTAG clock and control/monitor SWD/JTAG I/O pins. <br/></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memdesc:group__DAP__swo__gr"><td class="mdescLeft"> </td><td class="mdescRight">Configure the parameters for SWO mode. <br/></td></tr>
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<tr class="memdesc:group__DAP__jtag__gr"><td class="mdescLeft"> </td><td class="mdescRight">Detect and configure the JTAG device chain. <br/></td></tr>
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<tr class="memdesc:group__DAP__transfer__gr"><td class="mdescLeft"> </td><td class="mdescRight">Read and Writes to CoreSight registers. <br/></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__DAP__Response__Status"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Response__Status.html">Response Status</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Commands between Debug Unit and host computer. </p>
<p>This section explains each command that is exchanged between the Debug Unit and the host computer. Every Command starts with a Command-ID and optional data. Depending on the Command, the CMSIS-DAP firmware replies with a Response that repeats the Command-ID and delivers additional data.</p>
<p>Command and Response data have a package size limitation that is defined with <a class="el" href="group__DAP__Config__Debug__gr.html#gaa28bb1da2661291634c4a8fb3e227404">DAP_PACKET_SIZE</a>. This configuration setting can be obtained with the command <a class="el" href="group__DAP__Info.html">DAP_Info</a> and is used to optimize the performance for Full-Speed or High-Speed USB. The debugger must ensure that each data package fits within the limitations of the configured <a class="el" href="group__DAP__Config__Debug__gr.html#gaa28bb1da2661291634c4a8fb3e227404">DAP_PACKET_SIZE</a>.</p>
<dl class="section note"><dt>Note</dt><dd>Commands that are not implemented reply with 0xFF instead of repeating the command byte.</dd></dl>
<h2>Conventions and Command Structure </h2>
<p>The following conventions describe the command semantic used in the following documentation:</p>
<table class="doxtable">
<tr>
<th>Symbol </th><th>Description </th></tr>
<tr>
<td>> </td><td>Prefix indicating the direction: Command from host to Debug Unit. </td></tr>
<tr>
<td>< </td><td>Prefix indicating the direction: Response from Debug Unit to host. </td></tr>
<tr>
<td>BYTE </td><td>8-bit value. </td></tr>
<tr>
<td>SHORT </td><td>16-bit value (low byte first). </td></tr>
<tr>
<td>WORD </td><td>32-bit value (low byte first). </td></tr>
<tr>
<td>LWORD </td><td>64-bit value (low byte first). </td></tr>
<tr>
<td>FLOAT </td><td>32-bit single precision floating point value (LSB first). </td></tr>
<tr>
<td>0x01 </td><td>Fixed HEX value in C notation. Used for example to identify a command. </td></tr>
<tr>
<td>Reserved </td><td>The field above is reserved for future extension. </td></tr>
<tr>
<td>**** </td><td>The field above has exactly one occurrence. </td></tr>
<tr>
<td>++++ </td><td>The field above has a variable length. </td></tr>
<tr>
<td>////// </td><td>The field above is repeated and may appear 0..n times. </td></tr>
</table>
<p>The commands are described in a structure consisting of three lines.</p>
<ul>
<li>The first line indicates the field type.</li>
<li>The second line indicates the communication direction and the command structure.</li>
<li>The third line indicates the occurrence of the field.</li>
</ul>
<p><b>Examples:</b> </p>
<div class="fragment"><div class="line">| BYTE | SHORT *| WORD ***|</div>
<div class="line">> 0x99 | RecLen | Data |</div>
<div class="line">|******|********|+++++++++| </div>
</div><!-- fragment --><p>The Command with the Command-ID <em>0x99</em> is sent from the host computer to the Debug Unit. The value of <em>RecLen</em> indicates the number of WORDS that follow with <em>Data</em>. <em>Data</em> is repeated several times depending on the value of <em>RecLen</em>.</p>
<p>Depending on the Command the Debug Unit may send a <b>Response</b>. </p>
<div class="fragment"><div class="line">| BYTE ***| WORD***********|</div>
<div class="line">< 0 | Register Value |</div>
<div class="line">|*Reserved|****************|</div>
</div><!-- fragment --> </div><!-- contents -->
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 <span id="projectnumber">Version 2.0.0</span>
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<p>The CMSIS-DAP Firmware is programmed into Flash ROM of a Debug Unit.
<a href="#details">More...</a></p>
<p>The CMSIS-DAP Firmware is programmed into Flash ROM of a Debug Unit. </p>
<p>Once the CMSIS-DAP Firmware is configured it needs to be programmed into the Flash ROM of the new Debug Unit. MDK provides already Flash algorithms for many Cortex-M based microcontrollers and therefore you may use the Flash programming facilities that are provide in uVision.</p>
<p>Once Flash programming is configured you may use the uVision menu item <b>Flash - Download</b>.</p>
<div class="image">
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Download CMSIS-DAP Firmware to new Debug Unit using MDK</div></div>
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 <span id="projectnumber">Version 2.0.0</span>
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<p>DAP_config.h configures I/O ports and Debug Unit hardware parameters.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
Content</h2></td></tr>
<tr class="memitem:group__DAP__Config__Debug__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Config__Debug__gr.html">CMSIS-DAP Debug Unit Information</a></td></tr>
<tr class="memdesc:group__DAP__Config__Debug__gr"><td class="mdescLeft"> </td><td class="mdescRight">Provides definitions about the hardware and configuration of the Debug Unit. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__DAP__Config__PortIO__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Config__PortIO__gr.html">CMSIS-DAP Hardware I/O Pin Access</a></td></tr>
<tr class="memdesc:group__DAP__Config__PortIO__gr"><td class="mdescLeft"> </td><td class="mdescRight">Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode and Serial Wire Debug (SWD) mode. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__DAP__Config__LEDs__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Config__LEDs__gr.html">CMSIS-DAP Hardware Status LEDs</a></td></tr>
<tr class="memdesc:group__DAP__Config__LEDs__gr"><td class="mdescLeft"> </td><td class="mdescRight">CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__DAP__Config__Timestamp__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Config__Timestamp__gr.html">CMSIS-DAP Timestamp</a></td></tr>
<tr class="memdesc:group__DAP__Config__Timestamp__gr"><td class="mdescLeft"> </td><td class="mdescRight">Access function for Test Domain Timer. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:group__DAP__Config__Initialization__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__DAP__Config__Initialization__gr.html">CMSIS-DAP Initialization</a></td></tr>
<tr class="memdesc:group__DAP__Config__Initialization__gr"><td class="mdescLeft"> </td><td class="mdescRight">CMSIS-DAP Hardware I/O and LED Pins are initialized with the function <a class="el" href="group__DAP__Config__Initialization__gr.html#ga6d4656af10c47ec0d6c0389be2dbb4bb">DAP_SETUP</a>. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>DAP_config.h configures I/O ports and Debug Unit hardware parameters. </p>
<p>The CMSIS-DAP Firmware configuration file <b>DAP_config.h</b> provides the interface functions and configuration parameters for the hardware of the CMSIS-DAP Debug Unit. </p>
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<div class="title">Debug Unit Processor<div class="ingroups"><a class="el" href="group__DAP__Config__gr.html">Firmware Configuration</a></div></div> </div>
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<p>CMSIS-DAP Firmware runs on Debug Units with a Cortex-M microcontroller.
<a href="#details">More...</a></p>
<p>CMSIS-DAP Firmware runs on Debug Units with a Cortex-M microcontroller. </p>
<p>The CMSIS-DAP Firmware is designed to execute on a Debug Unit that is using a Cortex-M0, Cortex-M0+, Cortex-M3, or Cortex-M4 processor-based microcontroller.</p>
<p>The following steps describe how to change the microcontroller in the CMSIS-DAP Firmware project:</p>
<ol type="1">
<li>Open in the uVision IDE the project file <b>.\Firmware\MyDebugUnit\CMSIS_DAP.uvproj</b>.</li>
<li>Open the <b>Project - Options - Device</b> dialog and select the microcontroller of the new Debug Unit.</li>
<li>In the <b>Project Window</b> replace the files that belong to the group <b>Startup Code</b> with the relevant files for the new device.</li>
<li>Optionally you may modify the project file <b>Target</b> name and the file <b>Abstract.txt</b> to reflect the new Debug Unit.</li>
</ol>
<div class="image">
<img src="MDK_Device.png" alt="MDK_Device.png"/>
<div class="caption">
Select the microcontroller</div></div>
<p> In MDK Version 5 changing the microcontroller should bring in already the relevant software components for the new target. However, depending on the availability you may need to replace some components with custom implementations.</p>
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<img src="RTE.png" alt="RTE.png"/>
<div class="caption">
Replace missing software components</div></div>
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 <span id="projectnumber">Version 2.0.0</span>
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<div class="title">Configure USB Peripheral<div class="ingroups"><a class="el" href="group__DAP__Config__gr.html">Firmware Configuration</a></div></div> </div>
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<p>CMSIS-DAP Firmware communicates via an USB interface to host computer.
<a href="#details">More...</a></p>
<p>CMSIS-DAP Firmware communicates via an USB interface to host computer. </p>
<p>The USB communication is implemented via MDK middleware components that access the USB peripheral of the microcontroller.</p>
<p>The CMSIS-DAP Firmware is able to communicate with the host computer using one of the following USB classes:</p>
<ul>
<li><a class="el" href="group__DAP__ConfigUSB__gr.html">Communication via USB HID</a> (Human Interface Device) does not require any USB driver installation.</li>
<li><a class="el" href="group__DAP__ConfigUSB__gr.html">Communication via WinUSB</a> provides higher speed communication but may require an *.inf file for USB installation.</li>
</ul>
<p>For the USB interface it is important to provide correct configuration information for the USB Peripheral as described in this section.</p>
<p>The following steps describe how to change and configure the USB peripheral in the CMSIS-DAP Firmware project:</p>
<ol type="1">
<li>In the <b>Project Window</b>, the group <b>USB</b> contains USB interface with the relevant configuration files.</li>
<li>Open the file <b>usb_config_0.c</b> in the editor and select <b>Configuration Wizard</b> as edit mode; then change the following settings:<ul>
<li><b>USB Device 0 - High-speed</b>: enable this option only for a high-speed USB peripheral; disable for full-speed USB.</li>
<li>Update <b>Device Settings - Vendor ID</b> which is provided by the <a href="http://www.usb.org/developers/vendor/" target="_blank">USB Implementers Forum</a>.</li>
<li>Update <b>Device Settings - Product ID</b> to provide a unique identification for the Debug Unit.</li>
<li>Update <b>Device Settings - Device Release Number</b> to indicate the revision of the adaptation.</li>
<li>Update <b>String Settings - Manufacturer String</b> to reflect the vendor of the Debug Unit. This setting should match the <b>Vendor ID</b>.</li>
<li>Update <b>String Settings - Product String</b> to indicate the Debug Unit. Note that "CMSIS-DAP" must be part of that string to allow identification by debuggers (or part of interface string for USB composite device).</li>
<li>Optionally each Debug Unit may provide a unique <b>Serial Number String</b>. If the <b>String Settings - Serial Number String</b> is not provided, only one Debug Unit can be connected at the same time to a host computer since it is impossible to identify multiple Debug Units.</li>
</ul>
</li>
</ol>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>The USB Device setting high-speed / full-speed USB must be reflected in the <b>DAP_config.h</b> file as described under <a class="el" href="group__DAP__Config__gr.html">Firmware Configuration</a>.</li>
<li>The <b>String Settings - Product String</b> must contain "CMSIS-DAP" somewhere in the string. This is used by the debuggers to identify a CMSIS-DAP compliant Debug Unit that is connected to a host computer.</li>
</ul>
</dd></dl>
<p><br/>
</p>
<div class="image">
<img src="MDK_USB.png" alt="MDK_USB.png"/>
<div class="caption">
Adapt the USB Peripheral to the microcontroller</div></div>
<h3><a class="anchor" id="USBHID"></a>Communication via USB HID</h3><div class="textblock">CMSIS-DAP with V1 configuration uses USB HID and is therefore compatible with previous versions of CMSIS-DAP.There is no modification at the debugger required as all the additions are fully upward compatible. To configure CMSIS-DAP for V1 interface, add to the compiler options the #define DAP_FW_V1 as shown below:<br/>
</p>
<div class="image">
<img src="MDK_DAP_FW_V1.png" alt="MDK_DAP_FW_V1.png"/>
<div class="caption">
Compiler CMSIS-DAP Firmware for USB HID interface</div></div>
<p> The CMSIS-DAP Firmware can be also part of a USB composite device. If this case, the <b>HID Interface String</b> must contain the sub-string <b>CMSIS-DAP</b>. The <b>HID Interface String</b> is configured in the file USBD_Config_HID_0.h under the category <b>Human Interface Device Class Settings</b>.<br/>
</p>
<div class="image">
<img src="MDK_USB_HID.png" alt="MDK_USB_HID.png"/>
<div class="caption">
Adapt CMSIS-DAP to the USB HID class</div></div>
</div>
<h3><a class="anchor" id="WinUSB"></a>Communication via WinUSB</h3><div class="textblock">CMSIS-DAP with default V2 configuration uses WinUSB and is therefore faster.Optionally support for streaming SWO trace is provided via an additional USB endpoint.The WinUSB configuration requires custom class support with the interface setting – Class Code: 0xFF (Vendor specific), Subclass: 0x00, Protocol code: 0x00. Depending on the configuration it uses the following USB endpoints which should be configured in the interface descriptor in this order:</p>
<ul>
<li>Endpoint 1: Bulk Out – used for commands received from host PC.</li>
<li>Endpoint 2: Bulk In – used for responses send to host PC.</li>
<li>Endpoint 3: Bulk In (optional) – used for streaming SWO trace (if enabled with <a class="el" href="group__DAP__Config__Debug__gr.html#gafd6f450a10f4e03757388e00ea56906f">SWO_STREAM</a>).</li>
</ul>
To identify a CMSIS-DAP V2 configuration by debuggers the following WinUSB GUID must be used: </p>
<div class="fragment"><div class="line">{CDB3B5AD-293B-4663-AA36-1AAE46463776}</div>
</div><!-- fragment --><p> The picture below shows the configuration of the USB custom class.<div class="image">
<img src="MDK_USB_Custom.png" alt="MDK_USB_Custom.png"/>
<div class="caption">
Adapt CMSIS-DAP to the WinUSB class</div></div>
<p> <b>USB Driver and *.inf file</b> <br/>
<br/>
Windows 8 and Windows 10 does not require a WinUSB driver provided that the USB firmware stack supports Microsoft descriptors. CMSIS-DAP v2 device should be configured as WCID (Windows Compatible ID) device which provides extra information to a Windows system to facilitate automated driver installation. <br/>
<br/>
For Windows 7, the CMSIS-DAP v2 device will install automatically if PC is connected to the Internet and Device Installation Settings of PC are set to automatically download and install drivers for devices. Automatically installed device will be seen in Device Manager under Universal Serial Bus devices as WinUsb Device <br/>
<br/>
If no Internet connection is available or you want device to show with different name under Device Manager you should provide an .inf file and sign it to generate .cat files. More information is available from Microsoft under the topic <a href="https://technet.microsoft.com/en-us/library/dd919238(v=ws.10).aspx" target="_blank">Steps for Signing a Device Driver Package</a>. <br/>
<br/>
The following CMSIS_DAP_v2.inf file should be provided for an Windows 7 host PC.<pre class="fragment">[Version]
Signature = "$Windows NT$"
Class = USBDevice
ClassGUID = {88BAE032-5A81-49f0-BC3D-A4FF138216D6}
Provider = %ManufacturerName%
DriverVer = 04/13/2016, 1.0.0.0
CatalogFile.nt = CMSIS_DAP_v2_x86.cat
CatalogFile.ntx86 = CMSIS_DAP_v2_x86.cat
CatalogFile.ntamd64 = CMSIS_DAP_v2_amd64.cat
; ========== Manufacturer/Models sections ===========
[Manufacturer]
%ManufacturerName% = Devices, NTx86, NTamd64
[Devices.NTx86]
%DeviceName% = USB_Install, USB\VID_c251&PID_f000
[Devices.NTamd64]
%DeviceName% = USB_Install, USB\VID_c251&PID_f000
; ========== Class definition ===========
[ClassInstall32]
AddReg = ClassInstall_AddReg
[ClassInstall_AddReg]
HKR,,,,%ClassName%
HKR,,NoInstallClass,,1
HKR,,IconPath,0x10000,"%%SystemRoot%%\System32\setupapi.dll,-20"
HKR,,LowerLogoVersion,,5.2
; =================== Installation ===================
[USB_Install]
Include = winusb.inf
Needs = WINUSB.NT
[USB_Install.Services]
Include = winusb.inf
Needs = WINUSB.NT.Services
[USB_Install.HW]
AddReg = Dev_AddReg
[Dev_AddReg]
HKR,,DeviceInterfaceGUIDs,0x10000,"{CDB3B5AD-293B-4663-AA36-1AAE46463776}"
; =================== Strings ===================
[Strings]
ClassName = "Universal Serial Bus devices"
ManufacturerName = "KEIL - Tools By ARM"
DeviceName = "CMSIS-DAP v2"
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var group__DAP__ConfigUSB__gr =
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[ "Communication via WinUSB", "group__DAP__ConfigUSB__gr.html#WinUSB", null ]
]; | YifuLiu/AliOS-Things | components/cmsis/docs/DAP/html/group__DAP__ConfigUSB__gr.js | JavaScript | apache-2.0 | 202 |