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<p>Instance structure for floating-point FIR decimator.
</p>
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Data Fields</h2></td></tr>
<tr class="memitem:a76a8b2161731638eb3d67f277919f95d"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__f32.html#a76a8b2161731638eb3d67f277919f95d">M</a></td></tr>
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<tr class="memitem:a2aa2986129db8affef03ede88dd45a03"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__f32.html#a2aa2986129db8affef03ede88dd45a03">numTaps</a></td></tr>
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<tr class="memitem:a1aef1d796b60749d87ff36e282284628"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__f32.html#a1aef1d796b60749d87ff36e282284628">pCoeffs</a></td></tr>
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<tr class="memitem:a5bddf29aaaf2011d2e3bcec59a83f633"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__f32.html#a5bddf29aaaf2011d2e3bcec59a83f633">pState</a></td></tr>
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<p>decimation factor. </p>
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<td class="memname">uint16_t arm_fir_decimate_instance_f32::numTaps</td>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_decimate_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_decimate_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q15 FIR decimator.
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<tr class="memitem:ac1e9844488ec717da334fbd4c4f41990"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__q15.html#ac1e9844488ec717da334fbd4c4f41990">numTaps</a></td></tr>
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<tr class="memitem:a44ba13cf8aa4425c34adc82dc468ad54"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__q15.html#a44ba13cf8aa4425c34adc82dc468ad54">pCoeffs</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>decimation factor. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_decimate_instance_q15::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_decimate_instance_q15::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q31 FIR decimator.
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Data Fields</h2></td></tr>
<tr class="memitem:ad3d6936c36303b30dd38f1eddf248ae5"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__q31.html#ad3d6936c36303b30dd38f1eddf248ae5">M</a></td></tr>
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<tr class="memitem:a37915d42b0dc5e3057ebe83110798482"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__q31.html#a37915d42b0dc5e3057ebe83110798482">numTaps</a></td></tr>
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<tr class="memitem:a530ab6a5d1a39367b281206cd7201dae"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__decimate__instance__q31.html#a530ab6a5d1a39367b281206cd7201dae">pCoeffs</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>decimation factor. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_decimate_instance_q31::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_decimate_instance_q31::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the floating-point FIR filter.
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<tr class="memitem:a20cf98c92b5323799b7881c9ff4d2f7c"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__f32.html#a20cf98c92b5323799b7881c9ff4d2f7c">numTaps</a></td></tr>
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<tr class="memitem:a7afcf4022e8560db9b8fd28b0d090a15"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__f32.html#a7afcf4022e8560db9b8fd28b0d090a15">pState</a></td></tr>
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<tr class="memitem:aa590e6c845fcb19e027d77307c8ef016"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__f32.html#aa590e6c845fcb19e027d77307c8ef016">pCoeffs</a></td></tr>
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<div class="textblock"><dl><dt><b>Examples: </b></dt><dd><a class="el" href="arm_fir_example_f32_8c-example.html#_a12">arm_fir_example_f32.c</a>, and <a class="el" href="arm_signal_converge_example_f32_8c-example.html#_a3">arm_signal_converge_example_f32.c</a>.</dd>
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<p>number of filter coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q15 FIR filter.
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<tr class="memitem:a0e46f93cf51bfb18b1be808be9c5bfc9"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__q15.html#a0e46f93cf51bfb18b1be808be9c5bfc9">numTaps</a></td></tr>
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<p>number of filter coefficients in the filter. </p>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q31 FIR filter.
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<tr class="memitem:a918fadd775b7a0482b21bf34dae2f094"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__q31.html#a918fadd775b7a0482b21bf34dae2f094">numTaps</a></td></tr>
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<p>number of filter coefficients in the filter. </p>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q7 FIR filter.
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<tr class="memitem:a9b50840e2c5ef5b17e1a584fb4cf0d06"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__q7.html#a9b50840e2c5ef5b17e1a584fb4cf0d06">numTaps</a></td></tr>
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<tr class="memitem:a6947bd695db2d5f8e198e68ca0c72026"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__instance__q7.html#a6947bd695db2d5f8e198e68ca0c72026">pCoeffs</a></td></tr>
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<p>number of filter coefficients in the filter. </p>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the floating-point FIR interpolator.
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<tr class="memitem:ae6f94dcc0ccd8aa4bc699b20985d9df5"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__f32.html#ae6f94dcc0ccd8aa4bc699b20985d9df5">L</a></td></tr>
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<tr class="memitem:a389e669e13ec56292a70db8e92194b12"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__f32.html#a389e669e13ec56292a70db8e92194b12">phaseLength</a></td></tr>
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<tr class="memitem:a9e1258a3dbe84fde28d5ee67311337f4"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__f32.html#a9e1258a3dbe84fde28d5ee67311337f4">pCoeffs</a></td></tr>
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<p>upsample factor. </p>
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<p>points to the coefficient array. The array is of length L*phaseLength. </p>
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<p>length of each polyphase filter component. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_interpolate_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length phaseLength+numTaps-1. </p>
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<p>Instance structure for the Q15 FIR interpolator.
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<tr class="memitem:a239cee528ee8f79188fc34a94c86673b"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__q15.html#a239cee528ee8f79188fc34a94c86673b">pCoeffs</a></td></tr>
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<p>upsample factor. </p>
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<p>points to the coefficient array. The array is of length L*phaseLength. </p>
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<p>length of each polyphase filter component. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_interpolate_instance_q15::pState</td>
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<p>points to the state variable array. The array is of length blockSize+phaseLength-1. </p>
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<p>Instance structure for the Q31 FIR interpolator.
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<tr class="memitem:a5cdf0a631cb74e0e9588c388abe5235c"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__q31.html#a5cdf0a631cb74e0e9588c388abe5235c">L</a></td></tr>
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<tr class="memitem:a5d243796584afc7cd6c557f00b7acca5"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__q31.html#a5d243796584afc7cd6c557f00b7acca5">phaseLength</a></td></tr>
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<tr class="memitem:a89c871637896a08168e87ec13691f020"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__interpolate__instance__q31.html#a89c871637896a08168e87ec13691f020">pCoeffs</a></td></tr>
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<p>upsample factor. </p>
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<p>points to the coefficient array. The array is of length L*phaseLength. </p>
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<p>length of each polyphase filter component. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_interpolate_instance_q31::pState</td>
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<p>points to the state variable array. The array is of length blockSize+phaseLength-1. </p>
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<p>Instance structure for the floating-point FIR lattice filter.
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<tr class="memitem:ad369bd9997a250f195254df37408a38f"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__lattice__instance__f32.html#ad369bd9997a250f195254df37408a38f">numStages</a></td></tr>
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<p>number of filter stages. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_lattice_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numStages. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_lattice_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length numStages. </p>
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<p>Instance structure for the Q15 FIR lattice filter.
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<p>number of filter stages. </p>
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<p>points to the coefficient array. The array is of length numStages. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_lattice_instance_q15::pState</td>
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<p>points to the state variable array. The array is of length numStages. </p>
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<p>Instance structure for the Q31 FIR lattice filter.
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<tr class="memitem:a9f3773bbb76bc5a8a5ee9d37786bf478"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__lattice__instance__q31.html#a9f3773bbb76bc5a8a5ee9d37786bf478">numStages</a></td></tr>
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<tr class="memitem:ac9e648f1e5bc7d5ee6d5f7d8d22b1e74"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__lattice__instance__q31.html#ac9e648f1e5bc7d5ee6d5f7d8d22b1e74">pCoeffs</a></td></tr>
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<p>number of filter stages. </p>
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<p>points to the coefficient array. The array is of length numStages. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_lattice_instance_q31::pState</td>
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<p>points to the state variable array. The array is of length numStages. </p>
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<p>Instance structure for the floating-point sparse FIR filter.
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Data Fields</h2></td></tr>
<tr class="memitem:a5e19e7f234ac30a3db843352bf2a8515"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#a5e19e7f234ac30a3db843352bf2a8515">numTaps</a></td></tr>
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<tr class="memitem:a57585aeca9dc8686e08df2865375a86d"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#a57585aeca9dc8686e08df2865375a86d">stateIndex</a></td></tr>
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<tr class="memitem:a794af0916666d11cc564d6df08553555"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#a794af0916666d11cc564d6df08553555">pState</a></td></tr>
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<tr class="memitem:a4bc78b1761b6349e6842241e813d6446"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#a4bc78b1761b6349e6842241e813d6446">pCoeffs</a></td></tr>
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<tr class="memitem:af8b8c775f4084c36774f06c082b4c078"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#af8b8c775f4084c36774f06c082b4c078">maxDelay</a></td></tr>
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<tr class="memitem:aaa54ae67e5d10c6dd0d697945c638d31"><td class="memItemLeft" align="right" valign="top">int32_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__f32.html#aaa54ae67e5d10c6dd0d697945c638d31">pTapDelay</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>maximum offset specified by the pTapDelay array. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_sparse_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_fir_sparse_instance_f32::pState</td>
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<p>points to the state buffer array. The array is of length maxDelay+blockSize-1. </p>
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<p>points to the array of delay values. The array is of length numTaps. </p>
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<p>state buffer index. Points to the oldest sample in the state buffer. </p>
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<p>Instance structure for the Q15 sparse FIR filter.
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Data Fields</h2></td></tr>
<tr class="memitem:a0f66b126dd8b85f7467cfb01b7bc4d77"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q15.html#a0f66b126dd8b85f7467cfb01b7bc4d77">numTaps</a></td></tr>
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<tr class="memitem:a98b92b0f5208110129b9a67b1db90408"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q15.html#a98b92b0f5208110129b9a67b1db90408">pState</a></td></tr>
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<tr class="memitem:a4180a6d16a979b59b707a3e7b8cc274b"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q15.html#a4180a6d16a979b59b707a3e7b8cc274b">pCoeffs</a></td></tr>
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<tr class="memitem:ad14cc1070eecf7e1926d8f67a8273182"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q15.html#ad14cc1070eecf7e1926d8f67a8273182">maxDelay</a></td></tr>
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<tr class="memitem:aeab2855176c6efdb231a73a3672837d5"><td class="memItemLeft" align="right" valign="top">int32_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q15.html#aeab2855176c6efdb231a73a3672837d5">pTapDelay</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>maximum offset specified by the pTapDelay array. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_sparse_instance_q15::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_fir_sparse_instance_q15::pState</td>
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<p>points to the state buffer array. The array is of length maxDelay+blockSize-1. </p>
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<td class="memname">int32_t* arm_fir_sparse_instance_q15::pTapDelay</td>
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<p>points to the array of delay values. The array is of length numTaps. </p>
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<p>state buffer index. Points to the oldest sample in the state buffer. </p>
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<p>Instance structure for the Q31 sparse FIR filter.
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<tr class="memitem:a07b6c01e58ec6dde384719130d36b0dc"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q31.html#a07b6c01e58ec6dde384719130d36b0dc">numTaps</a></td></tr>
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<tr class="memitem:a830be89daa5a393b225048889aa045d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q31.html#a830be89daa5a393b225048889aa045d1">pState</a></td></tr>
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<tr class="memitem:af714d56f8fec4f93ad557abce6994d45"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q31.html#af714d56f8fec4f93ad557abce6994d45">pCoeffs</a></td></tr>
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<p>maximum offset specified by the pTapDelay array. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_sparse_instance_q31::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_fir_sparse_instance_q31::pState</td>
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<p>points to the state buffer array. The array is of length maxDelay+blockSize-1. </p>
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<p>points to the array of delay values. The array is of length numTaps. </p>
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<p>state buffer index. Points to the oldest sample in the state buffer. </p>
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<p>Instance structure for the Q7 sparse FIR filter.
</p>
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Data Fields</h2></td></tr>
<tr class="memitem:a54cdd27ca1c672b126c38763ce678b1c"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#a54cdd27ca1c672b126c38763ce678b1c">numTaps</a></td></tr>
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<tr class="memitem:a2d2e65473fe3a3f2b953b4e0b60824df"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#a2d2e65473fe3a3f2b953b4e0b60824df">stateIndex</a></td></tr>
<tr class="separator:a2d2e65473fe3a3f2b953b4e0b60824df"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a18072cf3ef3666d588f0d49512f2b28f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#a18072cf3ef3666d588f0d49512f2b28f">pState</a></td></tr>
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<tr class="memitem:a7f0989ef34fdb5d08ce5a5abf917218f"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#a7f0989ef34fdb5d08ce5a5abf917218f">pCoeffs</a></td></tr>
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<tr class="memitem:af74dacc1d34c078283e50f2530eb91df"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#af74dacc1d34c078283e50f2530eb91df">maxDelay</a></td></tr>
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<tr class="memitem:ac625393c84bc0342ffdf26fc4eba1ac1"><td class="memItemLeft" align="right" valign="top">int32_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__fir__sparse__instance__q7.html#ac625393c84bc0342ffdf26fc4eba1ac1">pTapDelay</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>maximum offset specified by the pTapDelay array. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a>* arm_fir_sparse_instance_q7::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a>* arm_fir_sparse_instance_q7::pState</td>
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<p>points to the state buffer array. The array is of length maxDelay+blockSize-1. </p>
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<td class="memname">int32_t* arm_fir_sparse_instance_q7::pTapDelay</td>
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<p>points to the array of delay values. The array is of length numTaps. </p>
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<p>state buffer index. Points to the oldest sample in the state buffer. </p>
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<p>Instance structure for the floating-point IIR lattice filter.
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<p>number of stages in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_iir_lattice_instance_f32::pkCoeffs</td>
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<p>points to the reflection coefficient array. The array is of length numStages. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_iir_lattice_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length numStages+blockSize. </p>
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<p>points to the ladder coefficient array. The array is of length numStages+1. </p>
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<p>Instance structure for the Q15 IIR lattice filter.
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<tr class="memitem:a96fbed313bef01070409fa182d26ba3f"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__iir__lattice__instance__q15.html#a96fbed313bef01070409fa182d26ba3f">numStages</a></td></tr>
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<p>number of stages in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_iir_lattice_instance_q15::pkCoeffs</td>
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<p>points to the reflection coefficient array. The array is of length numStages. </p>
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<p>points to the state variable array. The array is of length numStages+blockSize. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_iir_lattice_instance_q15::pvCoeffs</td>
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<p>points to the ladder coefficient array. The array is of length numStages+1. </p>
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<p>Instance structure for the Q31 IIR lattice filter.
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">uint16_t arm_iir_lattice_instance_q31::numStages</td>
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<p>number of stages in the filter. </p>
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<p>points to the reflection coefficient array. The array is of length numStages. </p>
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<p>points to the state variable array. The array is of length numStages+blockSize. </p>
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<p>points to the ladder coefficient array. The array is of length numStages+1. </p>
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<p>Instance structure for the floating-point Linear Interpolate function.
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<tr class="memitem:a95f02a926b16d35359aca5b31e813b11"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__linear__interp__instance__f32.html#a95f02a926b16d35359aca5b31e813b11">nValues</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl><dt><b>Examples: </b></dt><dd><a class="el" href="arm_linear_interp_example_f32_8c-example.html#_a10">arm_linear_interp_example_f32.c</a>.</dd>
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<p>nValues </p>
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<p>pointer to the table of Y values </p>
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<p>x1 </p>
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<p>xSpacing </p>
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<p>Instance structure for the floating-point LMS filter.
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<tr class="memitem:af73880d9009982f5d14529869494ec3d"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__f32.html#af73880d9009982f5d14529869494ec3d">numTaps</a></td></tr>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_lms_instance_f32::mu</td>
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<p>step size that controls filter coefficient updates. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_lms_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q15 LMS filter.
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Data Fields</h2></td></tr>
<tr class="memitem:a0078e894f805af1b360369e619fb57b3"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__q15.html#a0078e894f805af1b360369e619fb57b3">numTaps</a></td></tr>
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<tr class="memitem:acca5fbaef4a52ae411de24c9a0b929cf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__q15.html#acca5fbaef4a52ae411de24c9a0b929cf">postShift</a></td></tr>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_lms_instance_q15::mu</td>
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<p>step size that controls filter coefficient updates. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_lms_instance_q15::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<p>bit shift applied to coefficients. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_lms_instance_q15::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the Q31 LMS filter.
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Data Fields</h2></td></tr>
<tr class="memitem:ac0d84f7d054555931ef8a62511fbcb8a"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__q31.html#ac0d84f7d054555931ef8a62511fbcb8a">numTaps</a></td></tr>
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<tr class="memitem:acb6ca9996b3c5f740d5d6c8e9f4f1d46"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__q31.html#acb6ca9996b3c5f740d5d6c8e9f4f1d46">mu</a></td></tr>
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<tr class="memitem:a4705a8f0011bb9166e09bf5bd51e595e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__instance__q31.html#a4705a8f0011bb9166e09bf5bd51e595e">postShift</a></td></tr>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> arm_lms_instance_q31::mu</td>
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<p>step size that controls filter coefficient updates. </p>
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<p>number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_lms_instance_q31::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname">uint32_t arm_lms_instance_q31::postShift</td>
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<p>bit shift applied to coefficients. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_lms_instance_q31::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<p>Instance structure for the floating-point normalized LMS filter.
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Data Fields</h2></td></tr>
<tr class="memitem:ac95f8ca3d816524c2070643852fac5e8"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__f32.html#ac95f8ca3d816524c2070643852fac5e8">numTaps</a></td></tr>
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<tr class="memitem:a84401d3cfc6c40f69c08223cf341b886"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__f32.html#a84401d3cfc6c40f69c08223cf341b886">mu</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl><dt><b>Examples: </b></dt><dd><a class="el" href="arm_signal_converge_example_f32_8c-example.html#_a8">arm_signal_converge_example_f32.c</a>.</dd>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_lms_norm_instance_f32::energy</td>
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<p>saves previous frame energy. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_lms_norm_instance_f32::mu</td>
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<p>step size that control filter coefficient updates. </p>
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<td class="memname">uint16_t arm_lms_norm_instance_f32::numTaps</td>
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<p>number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_lms_norm_instance_f32::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_lms_norm_instance_f32::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_lms_norm_instance_f32::x0</td>
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<p>saves previous input sample. </p>
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<p>Instance structure for the Q15 normalized LMS filter.
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Data Fields</h2></td></tr>
<tr class="memitem:a9ee7a45f4f315d7996a969e25fdc7146"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#a9ee7a45f4f315d7996a969e25fdc7146">numTaps</a></td></tr>
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<tr class="memitem:aa4de490b3bdbd03561b76ee07901c8e3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#aa4de490b3bdbd03561b76ee07901c8e3">pState</a></td></tr>
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<tr class="memitem:a7ce00f21d11cfda6d963240641deea8c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#a7ce00f21d11cfda6d963240641deea8c">mu</a></td></tr>
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<tr class="memitem:aa0d435fbcf7dedb7179d4467e9b79e9f"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#aa0d435fbcf7dedb7179d4467e9b79e9f">postShift</a></td></tr>
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<tr class="memitem:a07d272351a3291ed09e3f42447609df0"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#a07d272351a3291ed09e3f42447609df0">recipTable</a></td></tr>
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<tr class="memitem:a1c81ded399919d8181026bc1c8602e7b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q15.html#a1c81ded399919d8181026bc1c8602e7b">energy</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_lms_norm_instance_q15::energy</td>
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<p>saves previous frame energy. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_lms_norm_instance_q15::mu</td>
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<p>step size that controls filter coefficient updates. </p>
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<p>Number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_lms_norm_instance_q15::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname">uint8_t arm_lms_norm_instance_q15::postShift</td>
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<p>bit shift applied to coefficients. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_lms_norm_instance_q15::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_lms_norm_instance_q15::recipTable</td>
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<p>Points to the reciprocal initial value table. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_lms_norm_instance_q15::x0</td>
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<p>saves previous input sample. </p>
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<p>Instance structure for the Q31 normalized LMS filter.
</p>
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Data Fields</h2></td></tr>
<tr class="memitem:a28e4c085af69c9c3e2e95dacf8004c3e"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#a28e4c085af69c9c3e2e95dacf8004c3e">numTaps</a></td></tr>
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<tr class="memitem:a57a64c1ff102d033c1bd05043f1d9955"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#a57a64c1ff102d033c1bd05043f1d9955">pCoeffs</a></td></tr>
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<tr class="memitem:ad3dd2a2406e02fdaa7782ba6c3940a64"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#ad3dd2a2406e02fdaa7782ba6c3940a64">mu</a></td></tr>
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<tr class="memitem:a28d7b9e437817f83397e081967e90f3c"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#a28d7b9e437817f83397e081967e90f3c">postShift</a></td></tr>
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<tr class="memitem:adb1c356b4f9d6d1a9838577bc990e8eb"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#adb1c356b4f9d6d1a9838577bc990e8eb">recipTable</a></td></tr>
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<tr class="memitem:a3c0ae42869afec8555dc8e3a7ef9b386"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#a3c0ae42869afec8555dc8e3a7ef9b386">energy</a></td></tr>
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<tr class="memitem:a47c4466d644e0d8ba407995adfa9b917"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__lms__norm__instance__q31.html#a47c4466d644e0d8ba407995adfa9b917">x0</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> arm_lms_norm_instance_q31::energy</td>
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<p>saves previous frame energy. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> arm_lms_norm_instance_q31::mu</td>
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<p>step size that controls filter coefficient updates. </p>
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<td class="memname">uint16_t arm_lms_norm_instance_q31::numTaps</td>
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<p>number of coefficients in the filter. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_lms_norm_instance_q31::pCoeffs</td>
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<p>points to the coefficient array. The array is of length numTaps. </p>
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<td class="memname">uint8_t arm_lms_norm_instance_q31::postShift</td>
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<p>bit shift applied to coefficients. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_lms_norm_instance_q31::pState</td>
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<p>points to the state variable array. The array is of length numTaps+blockSize-1. </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_lms_norm_instance_q31::recipTable</td>
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<p>points to the reciprocal initial value table. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> arm_lms_norm_instance_q31::x0</td>
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<p>saves previous input sample. </p>
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<p>Instance structure for the floating-point matrix structure.
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Data Fields</h2></td></tr>
<tr class="memitem:a23f4e34d70a82c9cad7612add5640b7b"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__matrix__instance__f32.html#a23f4e34d70a82c9cad7612add5640b7b">numRows</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><dl><dt><b>Examples: </b></dt><dd><a class="el" href="arm_class_marks_example_f32_8c-example.html#_a13">arm_class_marks_example_f32.c</a>, and <a class="el" href="arm_matrix_example_f32_8c-example.html#_a9">arm_matrix_example_f32.c</a>.</dd>
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<p>number of columns of the matrix. </p>
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<p>number of rows of the matrix. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_matrix_instance_f32::pData</td>
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<p>points to the data of the matrix. </p>
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<p>Instance structure for the floating-point matrix structure.
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<p>number of columns of the matrix. </p>
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<p>number of rows of the matrix. </p>
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<p>points to the data of the matrix. </p>
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<p>Instance structure for the Q15 matrix structure.
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<p>number of columns of the matrix. </p>
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<p>number of rows of the matrix. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_matrix_instance_q15::pData</td>
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<p>points to the data of the matrix. </p>
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<p>Instance structure for the Q31 matrix structure.
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Data Fields</h2></td></tr>
<tr class="memitem:a63bacac158a821c8cfc06088d251598c"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__matrix__instance__q31.html#a63bacac158a821c8cfc06088d251598c">numRows</a></td></tr>
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<p>number of columns of the matrix. </p>
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<p>number of rows of the matrix. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_matrix_instance_q31::pData</td>
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<p>points to the data of the matrix. </p>
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<p>Instance structure for the floating-point PID Control.
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<tr class="memitem:ad7b0bed64915d0a25a3409fa2dc45556"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__f32.html#ad7b0bed64915d0a25a3409fa2dc45556">A0</a></td></tr>
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<tr class="memitem:afd394e1e52fb1d526aa472c83b8f2464"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__f32.html#afd394e1e52fb1d526aa472c83b8f2464">state</a> [3]</td></tr>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_pid_instance_f32::A0</td>
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<p>The derived gain, A0 = Kp + Ki + Kd . </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_pid_instance_f32::A1</td>
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<p>The derived gain, A1 = -Kp - 2Kd. </p>
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<p>The derived gain, A2 = Kd . </p>
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<p>The derivative gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_pid_instance_f32::Ki</td>
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<p>The integral gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_pid_instance_f32::Kp</td>
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<p>The proportional gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> arm_pid_instance_f32::state[3]</td>
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<p>The state array of length 3. </p>
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<p>Instance structure for the Q15 PID Control.
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Data Fields</h2></td></tr>
<tr class="memitem:ad77f3a2823c7f96de42c92a3fbf3246b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__q15.html#ad77f3a2823c7f96de42c92a3fbf3246b">A0</a></td></tr>
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<tr class="memitem:a4a3f0a878b5b6b055e3478a2f244cd30"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__q15.html#a4a3f0a878b5b6b055e3478a2f244cd30">state</a> [3]</td></tr>
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<tr class="memitem:ad228aae24a1b6d855c93a8b9bbc1c4f1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__q15.html#ad228aae24a1b6d855c93a8b9bbc1c4f1">Kp</a></td></tr>
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<tr class="memitem:af5d4b53091f19eff7536636b7cc43111"><td class="memItemLeft" align="right" valign="top"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__pid__instance__q15.html#af5d4b53091f19eff7536636b7cc43111">Kd</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_pid_instance_q15::A0</td>
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<p>The derived gain, A0 = Kp + Ki + Kd . </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_pid_instance_q15::Kd</td>
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<p>The derivative gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_pid_instance_q15::Ki</td>
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<p>The integral gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_pid_instance_q15::Kp</td>
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<p>The proportional gain. </p>
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<td class="memname"><a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> arm_pid_instance_q15::state[3]</td>
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<p>The state array of length 3. </p>
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<p>Instance structure for the Q31 PID Control.
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<p>The derived gain, A0 = Kp + Ki + Kd . </p>
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<p>The derived gain, A1 = -Kp - 2Kd. </p>
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<p>The derived gain, A2 = Kd . </p>
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<p>The derivative gain. </p>
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<p>The integral gain. </p>
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<p>The proportional gain. </p>
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<p>The state array of length 3. </p>
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<p>Instance structure for the floating-point RFFT/RIFFT function.
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<tr class="memitem:a37419ababdfb3151b1891ae6bcd21012"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structarm__cfft__instance__f32.html">arm_cfft_instance_f32</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__fast__instance__f32.html#a37419ababdfb3151b1891ae6bcd21012">Sint</a></td></tr>
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<tr class="memitem:aef06ab665041ec36f5b25d464f0cab14"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__fast__instance__f32.html#aef06ab665041ec36f5b25d464f0cab14">fftLenRFFT</a></td></tr>
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<tr class="memitem:ad1a1bd8b12b49eae674115308d324622"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__fast__instance__f32.html#ad1a1bd8b12b49eae674115308d324622">pTwiddleRFFT</a></td></tr>
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<p>length of the real sequence </p>
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_rfft_fast_instance_f32::pTwiddleRFFT</td>
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<p>Twiddle factors real stage </p>
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<p>Internal CFFT structure. </p>
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<p>Instance structure for the floating-point RFFT/RIFFT function.
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Data Fields</h2></td></tr>
<tr class="memitem:a4219d4669699e4efdcb150ed7a0d9a57"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#a4219d4669699e4efdcb150ed7a0d9a57">fftLenReal</a></td></tr>
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<tr class="memitem:a075076e07ebb8521d8e3b49a31db6c57"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#a075076e07ebb8521d8e3b49a31db6c57">fftLenBy2</a></td></tr>
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<tr class="memitem:a5ee6d10a934ab4b666e0bb286c3d633f"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#a5ee6d10a934ab4b666e0bb286c3d633f">ifftFlagR</a></td></tr>
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<tr class="memitem:ac342f3248157cbbd2f04a3c8ec9fc9eb"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#ac342f3248157cbbd2f04a3c8ec9fc9eb">bitReverseFlagR</a></td></tr>
<tr class="separator:ac342f3248157cbbd2f04a3c8ec9fc9eb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aede85350fb5ae6baa1b3e8bfa15b18d6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#aede85350fb5ae6baa1b3e8bfa15b18d6">twidCoefRModifier</a></td></tr>
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<tr class="memitem:aac5a79a077f3ecbca6e85ba582b33691"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#aac5a79a077f3ecbca6e85ba582b33691">pTwiddleAReal</a></td></tr>
<tr class="separator:aac5a79a077f3ecbca6e85ba582b33691"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8c5c8de5d526d3bb9527954ec5c585c9"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#a8c5c8de5d526d3bb9527954ec5c585c9">pTwiddleBReal</a></td></tr>
<tr class="separator:a8c5c8de5d526d3bb9527954ec5c585c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9f47ba9f50c81e4445ae3827b981bc05"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structarm__cfft__radix4__instance__f32.html">arm_cfft_radix4_instance_f32</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__f32.html#a9f47ba9f50c81e4445ae3827b981bc05">pCfft</a></td></tr>
<tr class="separator:a9f47ba9f50c81e4445ae3827b981bc05"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="ac342f3248157cbbd2f04a3c8ec9fc9eb"></a>
<div class="memitem">
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<td class="memname">uint8_t arm_rfft_instance_f32::bitReverseFlagR</td>
</tr>
</table>
</div><div class="memdoc">
<p>flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. </p>
</div>
</div>
<a class="anchor" id="a075076e07ebb8521d8e3b49a31db6c57"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">uint16_t arm_rfft_instance_f32::fftLenBy2</td>
</tr>
</table>
</div><div class="memdoc">
<p>length of the complex FFT. </p>
</div>
</div>
<a class="anchor" id="a4219d4669699e4efdcb150ed7a0d9a57"></a>
<div class="memitem">
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<tr>
<td class="memname">uint32_t arm_rfft_instance_f32::fftLenReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>length of the real FFT. </p>
</div>
</div>
<a class="anchor" id="a5ee6d10a934ab4b666e0bb286c3d633f"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">uint8_t arm_rfft_instance_f32::ifftFlagR</td>
</tr>
</table>
</div><div class="memdoc">
<p>flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. </p>
</div>
</div>
<a class="anchor" id="a9f47ba9f50c81e4445ae3827b981bc05"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname"><a class="el" href="structarm__cfft__radix4__instance__f32.html">arm_cfft_radix4_instance_f32</a>* arm_rfft_instance_f32::pCfft</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the complex FFT instance. </p>
</div>
</div>
<a class="anchor" id="aac5a79a077f3ecbca6e85ba582b33691"></a>
<div class="memitem">
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_rfft_instance_f32::pTwiddleAReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the real twiddle factor table. </p>
</div>
</div>
<a class="anchor" id="a8c5c8de5d526d3bb9527954ec5c585c9"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">const <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a>* arm_rfft_instance_f32::pTwiddleBReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the imag twiddle factor table. </p>
</div>
</div>
<a class="anchor" id="aede85350fb5ae6baa1b3e8bfa15b18d6"></a>
<div class="memitem">
<div class="memproto">
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<tr>
<td class="memname">uint32_t arm_rfft_instance_f32::twidCoefRModifier</td>
</tr>
</table>
</div><div class="memdoc">
<p>twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. </p>
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<div class="title">arm_rfft_instance_q15 Struct Reference</div> </div>
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<div class="contents">
<p>Instance structure for the Q15 RFFT/RIFFT function.
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:aac5cf9e825917cbb14f439e56bb86ab3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#aac5cf9e825917cbb14f439e56bb86ab3">fftLenReal</a></td></tr>
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<tr class="memitem:a8051ffe268c147e431e1bea7bb4c4258"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#a8051ffe268c147e431e1bea7bb4c4258">ifftFlagR</a></td></tr>
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<tr class="memitem:a4c65cd40e0098ec2f5c0dc31488b9bc6"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#a4c65cd40e0098ec2f5c0dc31488b9bc6">bitReverseFlagR</a></td></tr>
<tr class="separator:a4c65cd40e0098ec2f5c0dc31488b9bc6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afd444d05858c5f419980e94e8240d5c3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#afd444d05858c5f419980e94e8240d5c3">twidCoefRModifier</a></td></tr>
<tr class="separator:afd444d05858c5f419980e94e8240d5c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aab9899263ada770283136d01985a524f"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#aab9899263ada770283136d01985a524f">pTwiddleAReal</a></td></tr>
<tr class="separator:aab9899263ada770283136d01985a524f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5b288a44a0ce0154b1fed9386627c4b5"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#a5b288a44a0ce0154b1fed9386627c4b5">pTwiddleBReal</a></td></tr>
<tr class="separator:a5b288a44a0ce0154b1fed9386627c4b5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4329c15b056444746d37ff082a24d31a"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="structarm__cfft__instance__q15.html">arm_cfft_instance_q15</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q15.html#a4329c15b056444746d37ff082a24d31a">pCfft</a></td></tr>
<tr class="separator:a4329c15b056444746d37ff082a24d31a"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">uint8_t arm_rfft_instance_q15::bitReverseFlagR</td>
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</table>
</div><div class="memdoc">
<p>flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. </p>
</div>
</div>
<a class="anchor" id="aac5cf9e825917cbb14f439e56bb86ab3"></a>
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<td class="memname">uint32_t arm_rfft_instance_q15::fftLenReal</td>
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</div><div class="memdoc">
<p>length of the real FFT. </p>
</div>
</div>
<a class="anchor" id="a8051ffe268c147e431e1bea7bb4c4258"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">uint8_t arm_rfft_instance_q15::ifftFlagR</td>
</tr>
</table>
</div><div class="memdoc">
<p>flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. </p>
</div>
</div>
<a class="anchor" id="a4329c15b056444746d37ff082a24d31a"></a>
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<table class="memname">
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<td class="memname">const <a class="el" href="structarm__cfft__instance__q15.html">arm_cfft_instance_q15</a>* arm_rfft_instance_q15::pCfft</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the complex FFT instance. </p>
</div>
</div>
<a class="anchor" id="aab9899263ada770283136d01985a524f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_rfft_instance_q15::pTwiddleAReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the real twiddle factor table. </p>
</div>
</div>
<a class="anchor" id="a5b288a44a0ce0154b1fed9386627c4b5"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">const <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a>* arm_rfft_instance_q15::pTwiddleBReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the imag twiddle factor table. </p>
</div>
</div>
<a class="anchor" id="afd444d05858c5f419980e94e8240d5c3"></a>
<div class="memitem">
<div class="memproto">
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<tr>
<td class="memname">uint32_t arm_rfft_instance_q15::twidCoefRModifier</td>
</tr>
</table>
</div><div class="memdoc">
<p>twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. </p>
</div>
</div>
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<p>Instance structure for the Q31 RFFT/RIFFT function.
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:af777b0cadd5abaf064323692c2e6693b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#af777b0cadd5abaf064323692c2e6693b">fftLenReal</a></td></tr>
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<tr class="memitem:af5c2615e6cde15524df38fa57ea32d94"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#af5c2615e6cde15524df38fa57ea32d94">ifftFlagR</a></td></tr>
<tr class="separator:af5c2615e6cde15524df38fa57ea32d94"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3cb90cdc928a88b0203917dcb3dc1b71"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#a3cb90cdc928a88b0203917dcb3dc1b71">bitReverseFlagR</a></td></tr>
<tr class="separator:a3cb90cdc928a88b0203917dcb3dc1b71"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6fc90252b579f7c29e01bd279334fc43"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#a6fc90252b579f7c29e01bd279334fc43">twidCoefRModifier</a></td></tr>
<tr class="separator:a6fc90252b579f7c29e01bd279334fc43"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a04eb56288cddc9a366d3af02c3f86792"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#a04eb56288cddc9a366d3af02c3f86792">pTwiddleAReal</a></td></tr>
<tr class="separator:a04eb56288cddc9a366d3af02c3f86792"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7d57376f7be4945011d3a4d5b1f646b8"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#a7d57376f7be4945011d3a4d5b1f646b8">pTwiddleBReal</a></td></tr>
<tr class="separator:a7d57376f7be4945011d3a4d5b1f646b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8fe10d425b59e096c23aa4bb5caa1974"><td class="memItemLeft" align="right" valign="top">const <a class="el" href="structarm__cfft__instance__q31.html">arm_cfft_instance_q31</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="structarm__rfft__instance__q31.html#a8fe10d425b59e096c23aa4bb5caa1974">pCfft</a></td></tr>
<tr class="separator:a8fe10d425b59e096c23aa4bb5caa1974"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a3cb90cdc928a88b0203917dcb3dc1b71"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">uint8_t arm_rfft_instance_q31::bitReverseFlagR</td>
</tr>
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<p>flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. </p>
</div>
</div>
<a class="anchor" id="af777b0cadd5abaf064323692c2e6693b"></a>
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<td class="memname">uint32_t arm_rfft_instance_q31::fftLenReal</td>
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<p>length of the real FFT. </p>
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<td class="memname">uint8_t arm_rfft_instance_q31::ifftFlagR</td>
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<p>flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. </p>
</div>
</div>
<a class="anchor" id="a8fe10d425b59e096c23aa4bb5caa1974"></a>
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<td class="memname">const <a class="el" href="structarm__cfft__instance__q31.html">arm_cfft_instance_q31</a>* arm_rfft_instance_q31::pCfft</td>
</tr>
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<p>points to the complex FFT instance. </p>
</div>
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<a class="anchor" id="a04eb56288cddc9a366d3af02c3f86792"></a>
<div class="memitem">
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<td class="memname">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_rfft_instance_q31::pTwiddleAReal</td>
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<p>points to the real twiddle factor table. </p>
</div>
</div>
<a class="anchor" id="a7d57376f7be4945011d3a4d5b1f646b8"></a>
<div class="memitem">
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<td class="memname">const <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a>* arm_rfft_instance_q31::pTwiddleBReal</td>
</tr>
</table>
</div><div class="memdoc">
<p>points to the imag twiddle factor table. </p>
</div>
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<td class="memname">uint32_t arm_rfft_instance_q31::twidCoefRModifier</td>
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<p>twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. </p>
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Functions</h2></td></tr>
<tr class="memitem:ga4256d5b23ffcb27759a05f8e6b854f13"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga4256d5b23ffcb27759a05f8e6b854f13">ARM_CAN_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga4256d5b23ffcb27759a05f8e6b854f13"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__can__interface__gr.html#ga4256d5b23ffcb27759a05f8e6b854f13">More...</a><br/></td></tr>
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<tr class="memitem:ga35f21cabe1637b1be964024a8f77721c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__can__interface__gr.html#structARM__CAN__CAPABILITIES">ARM_CAN_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga35f21cabe1637b1be964024a8f77721c">ARM_CAN_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga35f21cabe1637b1be964024a8f77721c"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__can__interface__gr.html#ga35f21cabe1637b1be964024a8f77721c">More...</a><br/></td></tr>
<tr class="separator:ga35f21cabe1637b1be964024a8f77721c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa72ceb25ba67e279d7432404632deb44"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#gaa72ceb25ba67e279d7432404632deb44">ARM_CAN_Initialize</a> (<a class="el" href="group__can__interface__gr.html#gaac07b9fdf614bf439414f5417aaa376e">ARM_CAN_SignalUnitEvent_t</a> cb_unit_event, <a class="el" href="group__can__interface__gr.html#ga7ceceac3e9aa0981c5cacfab88efb4eb">ARM_CAN_SignalObjectEvent_t</a> cb_object_event)</td></tr>
<tr class="memdesc:gaa72ceb25ba67e279d7432404632deb44"><td class="mdescLeft"> </td><td class="mdescRight">Initialize CAN interface and register signal (callback) functions. <a href="group__can__interface__gr.html#gaa72ceb25ba67e279d7432404632deb44">More...</a><br/></td></tr>
<tr class="separator:gaa72ceb25ba67e279d7432404632deb44"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1e3e364b64f2ab277399e3279cce5ef8"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga1e3e364b64f2ab277399e3279cce5ef8">ARM_CAN_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:ga1e3e364b64f2ab277399e3279cce5ef8"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize CAN interface. <a href="group__can__interface__gr.html#ga1e3e364b64f2ab277399e3279cce5ef8">More...</a><br/></td></tr>
<tr class="separator:ga1e3e364b64f2ab277399e3279cce5ef8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6f634f126ac97daef2f3115aa7bfed7c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga6f634f126ac97daef2f3115aa7bfed7c">ARM_CAN_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga6f634f126ac97daef2f3115aa7bfed7c"><td class="mdescLeft"> </td><td class="mdescRight">Control CAN interface power. <a href="group__can__interface__gr.html#ga6f634f126ac97daef2f3115aa7bfed7c">More...</a><br/></td></tr>
<tr class="separator:ga6f634f126ac97daef2f3115aa7bfed7c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1fe6cc207415de604975ae251e269361"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga1fe6cc207415de604975ae251e269361">ARM_CAN_GetClock</a> (void)</td></tr>
<tr class="memdesc:ga1fe6cc207415de604975ae251e269361"><td class="mdescLeft"> </td><td class="mdescRight">Retrieve CAN base clock frequency. <a href="group__can__interface__gr.html#ga1fe6cc207415de604975ae251e269361">More...</a><br/></td></tr>
<tr class="separator:ga1fe6cc207415de604975ae251e269361"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga88bb27a8525503a250cca7a2c4a5d07a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga88bb27a8525503a250cca7a2c4a5d07a">ARM_CAN_SetBitrate</a> (<a class="el" href="group__can__timeseg__ctrls.html#ga11c12020b81a63a73a8b53e96a7e3dea">ARM_CAN_BITRATE_SELECT</a> select, uint32_t bitrate, uint32_t bit_segments)</td></tr>
<tr class="memdesc:ga88bb27a8525503a250cca7a2c4a5d07a"><td class="mdescLeft"> </td><td class="mdescRight">Set bitrate for CAN interface. <a href="group__can__interface__gr.html#ga88bb27a8525503a250cca7a2c4a5d07a">More...</a><br/></td></tr>
<tr class="separator:ga88bb27a8525503a250cca7a2c4a5d07a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga28226a6e223f9b95b4dafb7c2f48a855"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga28226a6e223f9b95b4dafb7c2f48a855">ARM_CAN_SetMode</a> (<a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcd">ARM_CAN_MODE</a> mode)</td></tr>
<tr class="memdesc:ga28226a6e223f9b95b4dafb7c2f48a855"><td class="mdescLeft"> </td><td class="mdescRight">Set operating mode for CAN interface. <a href="group__can__interface__gr.html#ga28226a6e223f9b95b4dafb7c2f48a855">More...</a><br/></td></tr>
<tr class="separator:ga28226a6e223f9b95b4dafb7c2f48a855"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga45ab314f5121cf5a1b32d9adc600e0f7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__can__interface__gr.html#structARM__CAN__OBJ__CAPABILITIES">ARM_CAN_OBJ_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga45ab314f5121cf5a1b32d9adc600e0f7">ARM_CAN_ObjectGetCapabilities</a> (uint32_t obj_idx)</td></tr>
<tr class="memdesc:ga45ab314f5121cf5a1b32d9adc600e0f7"><td class="mdescLeft"> </td><td class="mdescRight">Retrieve capabilities of an object. <a href="group__can__interface__gr.html#ga45ab314f5121cf5a1b32d9adc600e0f7">More...</a><br/></td></tr>
<tr class="separator:ga45ab314f5121cf5a1b32d9adc600e0f7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4f9bc7088704483388e14872c9d5385d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga4f9bc7088704483388e14872c9d5385d">ARM_CAN_ObjectSetFilter</a> (uint32_t obj_idx, <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75">ARM_CAN_FILTER_OPERATION</a> operation, uint32_t id, uint32_t arg)</td></tr>
<tr class="memdesc:ga4f9bc7088704483388e14872c9d5385d"><td class="mdescLeft"> </td><td class="mdescRight">Add or remove filter for message reception. <a href="group__can__interface__gr.html#ga4f9bc7088704483388e14872c9d5385d">More...</a><br/></td></tr>
<tr class="separator:ga4f9bc7088704483388e14872c9d5385d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga00ec0715f6755a49dae5b60dca182630"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga00ec0715f6755a49dae5b60dca182630">ARM_CAN_ObjectConfigure</a> (uint32_t obj_idx, <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0">ARM_CAN_OBJ_CONFIG</a> obj_cfg)</td></tr>
<tr class="memdesc:ga00ec0715f6755a49dae5b60dca182630"><td class="mdescLeft"> </td><td class="mdescRight">Configure object. <a href="group__can__interface__gr.html#ga00ec0715f6755a49dae5b60dca182630">More...</a><br/></td></tr>
<tr class="separator:ga00ec0715f6755a49dae5b60dca182630"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0dcffd362b4093043442a030eaebbcfe"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga0dcffd362b4093043442a030eaebbcfe">ARM_CAN_MessageSend</a> (uint32_t obj_idx, <a class="el" href="group__can__interface__gr.html#structARM__CAN__MSG__INFO">ARM_CAN_MSG_INFO</a> *msg_info, const uint8_t *data, uint8_t size)</td></tr>
<tr class="memdesc:ga0dcffd362b4093043442a030eaebbcfe"><td class="mdescLeft"> </td><td class="mdescRight">Send message on CAN bus. <a href="group__can__interface__gr.html#ga0dcffd362b4093043442a030eaebbcfe">More...</a><br/></td></tr>
<tr class="separator:ga0dcffd362b4093043442a030eaebbcfe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafc37084df5eab32f593c2744d35cf647"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#gafc37084df5eab32f593c2744d35cf647">ARM_CAN_MessageRead</a> (uint32_t obj_idx, <a class="el" href="group__can__interface__gr.html#structARM__CAN__MSG__INFO">ARM_CAN_MSG_INFO</a> *msg_info, uint8_t *data, uint8_t size)</td></tr>
<tr class="memdesc:gafc37084df5eab32f593c2744d35cf647"><td class="mdescLeft"> </td><td class="mdescRight">Read message received on CAN bus. <a href="group__can__interface__gr.html#gafc37084df5eab32f593c2744d35cf647">More...</a><br/></td></tr>
<tr class="separator:gafc37084df5eab32f593c2744d35cf647"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8d9f0c5f03a8a81ab062b5aa57e5dea4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga8d9f0c5f03a8a81ab062b5aa57e5dea4">ARM_CAN_Control</a> (uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:ga8d9f0c5f03a8a81ab062b5aa57e5dea4"><td class="mdescLeft"> </td><td class="mdescRight">Control CAN interface. <a href="group__can__interface__gr.html#ga8d9f0c5f03a8a81ab062b5aa57e5dea4">More...</a><br/></td></tr>
<tr class="separator:ga8d9f0c5f03a8a81ab062b5aa57e5dea4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga676d6b567fc4ab3d44f5d7a50ec9419c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__can__interface__gr.html#structARM__CAN__STATUS">ARM_CAN_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga676d6b567fc4ab3d44f5d7a50ec9419c">ARM_CAN_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga676d6b567fc4ab3d44f5d7a50ec9419c"><td class="mdescLeft"> </td><td class="mdescRight">Get CAN status. <a href="group__can__interface__gr.html#ga676d6b567fc4ab3d44f5d7a50ec9419c">More...</a><br/></td></tr>
<tr class="separator:ga676d6b567fc4ab3d44f5d7a50ec9419c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga38795d1ed135ce3bd87f31ef1596bccf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga38795d1ed135ce3bd87f31ef1596bccf">ARM_CAN_SignalUnitEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:ga38795d1ed135ce3bd87f31ef1596bccf"><td class="mdescLeft"> </td><td class="mdescRight">Signal CAN unit event. <a href="group__can__interface__gr.html#ga38795d1ed135ce3bd87f31ef1596bccf">More...</a><br/></td></tr>
<tr class="separator:ga38795d1ed135ce3bd87f31ef1596bccf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabfcaeac9e2ca25936ba5a29f2d594e7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#gabfcaeac9e2ca25936ba5a29f2d594e7e">ARM_CAN_SignalObjectEvent</a> (uint32_t obj_idx, uint32_t event)</td></tr>
<tr class="memdesc:gabfcaeac9e2ca25936ba5a29f2d594e7e"><td class="mdescLeft"> </td><td class="mdescRight">Signal CAN object event. <a href="group__can__interface__gr.html#gabfcaeac9e2ca25936ba5a29f2d594e7e">More...</a><br/></td></tr>
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<div class="title">Driver_CAN.h File Reference</div> </div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__CAN__OBJ__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#structARM__CAN__OBJ__CAPABILITIES">ARM_CAN_OBJ_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__CAN__OBJ__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">CAN Object Capabilities. <a href="group__can__interface__gr.html#structARM__CAN__OBJ__CAPABILITIES">More...</a><br/></td></tr>
<tr class="separator:structARM__CAN__OBJ__CAPABILITIES"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:structARM__CAN__MSG__INFO"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#structARM__CAN__MSG__INFO">ARM_CAN_MSG_INFO</a></td></tr>
<tr class="memdesc:structARM__CAN__MSG__INFO"><td class="mdescLeft"> </td><td class="mdescRight">CAN Message Information. <a href="group__can__interface__gr.html#structARM__CAN__MSG__INFO">More...</a><br/></td></tr>
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<tr class="memitem:structARM__CAN__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#structARM__CAN__STATUS">ARM_CAN_STATUS</a></td></tr>
<tr class="memdesc:structARM__CAN__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">CAN Status. <a href="group__can__interface__gr.html#structARM__CAN__STATUS">More...</a><br/></td></tr>
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<tr class="memitem:structARM__CAN__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#structARM__CAN__CAPABILITIES">ARM_CAN_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__CAN__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">CAN Device Driver Capabilities. <a href="group__can__interface__gr.html#structARM__CAN__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__CAN"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#structARM__DRIVER__CAN">ARM_DRIVER_CAN</a></td></tr>
<tr class="memdesc:structARM__DRIVER__CAN"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the CAN Driver. <a href="group__can__interface__gr.html#structARM__DRIVER__CAN">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a88cba309175477a369375827c6e67d16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a88cba309175477a369375827c6e67d16">ARM_CAN_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(1,2) /* API version */</td></tr>
<tr class="separator:a88cba309175477a369375827c6e67d16"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a71e16a70efe5e4b21e5622d2b0cb7889"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a71e16a70efe5e4b21e5622d2b0cb7889">ARM_CAN_BIT_PROP_SEG_Pos</a>   0UL</td></tr>
<tr class="memdesc:a71e16a70efe5e4b21e5622d2b0cb7889"><td class="mdescLeft"> </td><td class="mdescRight">bits 7..0 <a href="#a71e16a70efe5e4b21e5622d2b0cb7889">More...</a><br/></td></tr>
<tr class="separator:a71e16a70efe5e4b21e5622d2b0cb7889"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a018bef85dc771e75a5d0f017393af01a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a018bef85dc771e75a5d0f017393af01a">ARM_CAN_BIT_PROP_SEG_Msk</a>   (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)</td></tr>
<tr class="separator:a018bef85dc771e75a5d0f017393af01a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga01183319a5a899eafea9ffe7af73d5ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__timeseg__ctrls.html#ga01183319a5a899eafea9ffe7af73d5ea">ARM_CAN_BIT_PROP_SEG</a>(x)   (((x) << <a class="el" href="Driver__CAN_8h.html#a71e16a70efe5e4b21e5622d2b0cb7889">ARM_CAN_BIT_PROP_SEG_Pos</a>) & <a class="el" href="Driver__CAN_8h.html#a018bef85dc771e75a5d0f017393af01a">ARM_CAN_BIT_PROP_SEG_Msk</a>)</td></tr>
<tr class="separator:ga01183319a5a899eafea9ffe7af73d5ea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a23658b0cb98b00c900857aef64926922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a23658b0cb98b00c900857aef64926922">ARM_CAN_BIT_PHASE_SEG1_Pos</a>   8UL</td></tr>
<tr class="memdesc:a23658b0cb98b00c900857aef64926922"><td class="mdescLeft"> </td><td class="mdescRight">bits 15..8 <a href="#a23658b0cb98b00c900857aef64926922">More...</a><br/></td></tr>
<tr class="separator:a23658b0cb98b00c900857aef64926922"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4a661aa69c2825d9118a97695ba39546"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a4a661aa69c2825d9118a97695ba39546">ARM_CAN_BIT_PHASE_SEG1_Msk</a>   (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)</td></tr>
<tr class="separator:a4a661aa69c2825d9118a97695ba39546"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga03f1921ee97a7ebf5d767b6cacf40792"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__timeseg__ctrls.html#ga03f1921ee97a7ebf5d767b6cacf40792">ARM_CAN_BIT_PHASE_SEG1</a>(x)   (((x) << <a class="el" href="Driver__CAN_8h.html#a23658b0cb98b00c900857aef64926922">ARM_CAN_BIT_PHASE_SEG1_Pos</a>) & <a class="el" href="Driver__CAN_8h.html#a4a661aa69c2825d9118a97695ba39546">ARM_CAN_BIT_PHASE_SEG1_Msk</a>)</td></tr>
<tr class="separator:ga03f1921ee97a7ebf5d767b6cacf40792"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acd52b5921a5ab0ad0b251957a93a5993"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#acd52b5921a5ab0ad0b251957a93a5993">ARM_CAN_BIT_PHASE_SEG2_Pos</a>   16UL</td></tr>
<tr class="memdesc:acd52b5921a5ab0ad0b251957a93a5993"><td class="mdescLeft"> </td><td class="mdescRight">bits 23..16 <a href="#acd52b5921a5ab0ad0b251957a93a5993">More...</a><br/></td></tr>
<tr class="separator:acd52b5921a5ab0ad0b251957a93a5993"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae4df531026a911d53df401a4b9eec89c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#ae4df531026a911d53df401a4b9eec89c">ARM_CAN_BIT_PHASE_SEG2_Msk</a>   (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)</td></tr>
<tr class="separator:ae4df531026a911d53df401a4b9eec89c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga76de056d56803cb7a0d01978ee981e80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__timeseg__ctrls.html#ga76de056d56803cb7a0d01978ee981e80">ARM_CAN_BIT_PHASE_SEG2</a>(x)   (((x) << <a class="el" href="Driver__CAN_8h.html#acd52b5921a5ab0ad0b251957a93a5993">ARM_CAN_BIT_PHASE_SEG2_Pos</a>) & <a class="el" href="Driver__CAN_8h.html#ae4df531026a911d53df401a4b9eec89c">ARM_CAN_BIT_PHASE_SEG2_Msk</a>)</td></tr>
<tr class="separator:ga76de056d56803cb7a0d01978ee981e80"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac233859cfb244895fa47c02d8df02ee8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#ac233859cfb244895fa47c02d8df02ee8">ARM_CAN_BIT_SJW_Pos</a>   24UL</td></tr>
<tr class="memdesc:ac233859cfb244895fa47c02d8df02ee8"><td class="mdescLeft"> </td><td class="mdescRight">bits 28..24 <a href="#ac233859cfb244895fa47c02d8df02ee8">More...</a><br/></td></tr>
<tr class="separator:ac233859cfb244895fa47c02d8df02ee8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac3af13704609a6b14655f00b3d7ac419"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#ac3af13704609a6b14655f00b3d7ac419">ARM_CAN_BIT_SJW_Msk</a>   (0x1FUL << ARM_CAN_BIT_SJW_Pos)</td></tr>
<tr class="separator:ac3af13704609a6b14655f00b3d7ac419"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab32e97fa4edf497c111dd3f0d8779269"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__timeseg__ctrls.html#gab32e97fa4edf497c111dd3f0d8779269">ARM_CAN_BIT_SJW</a>(x)   (((x) << <a class="el" href="Driver__CAN_8h.html#ac233859cfb244895fa47c02d8df02ee8">ARM_CAN_BIT_SJW_Pos</a>) & <a class="el" href="Driver__CAN_8h.html#ac3af13704609a6b14655f00b3d7ac419">ARM_CAN_BIT_SJW_Msk</a>)</td></tr>
<tr class="separator:gab32e97fa4edf497c111dd3f0d8779269"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aba948867397ee2081d82f5c6db5edd4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#aba948867397ee2081d82f5c6db5edd4b">ARM_CAN_CONTROL_Pos</a>   0UL</td></tr>
<tr class="separator:aba948867397ee2081d82f5c6db5edd4b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0b9ca7f824e6931dd0945673c4d29d14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a0b9ca7f824e6931dd0945673c4d29d14">ARM_CAN_CONTROL_Msk</a>   (0xFFUL << ARM_CAN_CONTROL_Pos)</td></tr>
<tr class="separator:a0b9ca7f824e6931dd0945673c4d29d14"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga978ab3e8860f644dea780e87b3478ff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__mode__ctrls.html#ga978ab3e8860f644dea780e87b3478ff4">ARM_CAN_SET_FD_MODE</a>   (1UL << ARM_CAN_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga978ab3e8860f644dea780e87b3478ff4"><td class="mdescLeft"> </td><td class="mdescRight">Set FD operation mode; arg: 0 = disable, 1 = enable. <a href="group__can__mode__ctrls.html#ga978ab3e8860f644dea780e87b3478ff4">More...</a><br/></td></tr>
<tr class="separator:ga978ab3e8860f644dea780e87b3478ff4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae051a548bf785104a934908360529438"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__mode__ctrls.html#gae051a548bf785104a934908360529438">ARM_CAN_ABORT_MESSAGE_SEND</a>   (2UL << ARM_CAN_CONTROL_Pos)</td></tr>
<tr class="memdesc:gae051a548bf785104a934908360529438"><td class="mdescLeft"> </td><td class="mdescRight">Abort sending of CAN message; arg = object. <a href="group__can__mode__ctrls.html#gae051a548bf785104a934908360529438">More...</a><br/></td></tr>
<tr class="separator:gae051a548bf785104a934908360529438"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0453b8900ca3a0d5210ffd6a918a78e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__mode__ctrls.html#ga0453b8900ca3a0d5210ffd6a918a78e6">ARM_CAN_CONTROL_RETRANSMISSION</a>   (3UL << ARM_CAN_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga0453b8900ca3a0d5210ffd6a918a78e6"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state) <a href="group__can__mode__ctrls.html#ga0453b8900ca3a0d5210ffd6a918a78e6">More...</a><br/></td></tr>
<tr class="separator:ga0453b8900ca3a0d5210ffd6a918a78e6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga398dd25256e644cd8d6506495a06bde8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__mode__ctrls.html#ga398dd25256e644cd8d6506495a06bde8">ARM_CAN_SET_TRANSCEIVER_DELAY</a>   (4UL << ARM_CAN_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga398dd25256e644cd8d6506495a06bde8"><td class="mdescLeft"> </td><td class="mdescRight">Set transceiver delay; arg = delay in time quanta. <a href="group__can__mode__ctrls.html#ga398dd25256e644cd8d6506495a06bde8">More...</a><br/></td></tr>
<tr class="separator:ga398dd25256e644cd8d6506495a06bde8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a874d634951197372eaa0c54b0b5c726f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a874d634951197372eaa0c54b0b5c726f">ARM_CAN_ID_IDE_Pos</a>   31UL</td></tr>
<tr class="separator:a874d634951197372eaa0c54b0b5c726f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abd2dde58dd280c29aaba971dcc11ce66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#abd2dde58dd280c29aaba971dcc11ce66">ARM_CAN_ID_IDE_Msk</a>   (1UL << ARM_CAN_ID_IDE_Pos)</td></tr>
<tr class="separator:abd2dde58dd280c29aaba971dcc11ce66"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga561635b816ddaf5fb87377155fc692c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__identifer__ctrls.html#ga561635b816ddaf5fb87377155fc692c7">ARM_CAN_STANDARD_ID</a>(id)   (id & 0x000007FFUL)</td></tr>
<tr class="memdesc:ga561635b816ddaf5fb87377155fc692c7"><td class="mdescLeft"> </td><td class="mdescRight">CAN identifier in standard format (11-bits) <a href="group__can__identifer__ctrls.html#ga561635b816ddaf5fb87377155fc692c7">More...</a><br/></td></tr>
<tr class="separator:ga561635b816ddaf5fb87377155fc692c7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae7d4efb6fb49e1ec47c2b12e22f37cae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__identifer__ctrls.html#gae7d4efb6fb49e1ec47c2b12e22f37cae">ARM_CAN_EXTENDED_ID</a>(id)   ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)</td></tr>
<tr class="memdesc:gae7d4efb6fb49e1ec47c2b12e22f37cae"><td class="mdescLeft"> </td><td class="mdescRight">CAN identifier in extended format (29-bits) <a href="group__can__identifer__ctrls.html#gae7d4efb6fb49e1ec47c2b12e22f37cae">More...</a><br/></td></tr>
<tr class="separator:gae7d4efb6fb49e1ec47c2b12e22f37cae"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a09e23c4f9b9b8c68bd8687b43757110d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a09e23c4f9b9b8c68bd8687b43757110d">ARM_CAN_INVALID_BITRATE_SELECT</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td></tr>
<tr class="memdesc:a09e23c4f9b9b8c68bd8687b43757110d"><td class="mdescLeft"> </td><td class="mdescRight">Bitrate selection not supported. <a href="#a09e23c4f9b9b8c68bd8687b43757110d">More...</a><br/></td></tr>
<tr class="separator:a09e23c4f9b9b8c68bd8687b43757110d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a90b9d9323a6049fb4fcd1efe7c892294"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a90b9d9323a6049fb4fcd1efe7c892294">ARM_CAN_INVALID_BITRATE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 2)</td></tr>
<tr class="memdesc:a90b9d9323a6049fb4fcd1efe7c892294"><td class="mdescLeft"> </td><td class="mdescRight">Requested bitrate not supported. <a href="#a90b9d9323a6049fb4fcd1efe7c892294">More...</a><br/></td></tr>
<tr class="separator:a90b9d9323a6049fb4fcd1efe7c892294"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2911dd8c4017147690f274fc4ef88f44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a2911dd8c4017147690f274fc4ef88f44">ARM_CAN_INVALID_BIT_PROP_SEG</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 3)</td></tr>
<tr class="memdesc:a2911dd8c4017147690f274fc4ef88f44"><td class="mdescLeft"> </td><td class="mdescRight">Propagation segment value not supported. <a href="#a2911dd8c4017147690f274fc4ef88f44">More...</a><br/></td></tr>
<tr class="separator:a2911dd8c4017147690f274fc4ef88f44"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aabdfe8d6ad5be07ad471dc00193afb48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#aabdfe8d6ad5be07ad471dc00193afb48">ARM_CAN_INVALID_BIT_PHASE_SEG1</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 4)</td></tr>
<tr class="memdesc:aabdfe8d6ad5be07ad471dc00193afb48"><td class="mdescLeft"> </td><td class="mdescRight">Phase segment 1 value not supported. <a href="#aabdfe8d6ad5be07ad471dc00193afb48">More...</a><br/></td></tr>
<tr class="separator:aabdfe8d6ad5be07ad471dc00193afb48"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a71cfbc4a4f8a37aafaeb6cf826d32c27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#a71cfbc4a4f8a37aafaeb6cf826d32c27">ARM_CAN_INVALID_BIT_PHASE_SEG2</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 5)</td></tr>
<tr class="memdesc:a71cfbc4a4f8a37aafaeb6cf826d32c27"><td class="mdescLeft"> </td><td class="mdescRight">Phase segment 2 value not supported. <a href="#a71cfbc4a4f8a37aafaeb6cf826d32c27">More...</a><br/></td></tr>
<tr class="separator:a71cfbc4a4f8a37aafaeb6cf826d32c27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad1c5957b266c8dcaf687288a2465d1b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#ad1c5957b266c8dcaf687288a2465d1b9">ARM_CAN_INVALID_BIT_SJW</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 6)</td></tr>
<tr class="memdesc:ad1c5957b266c8dcaf687288a2465d1b9"><td class="mdescLeft"> </td><td class="mdescRight">SJW value not supported. <a href="#ad1c5957b266c8dcaf687288a2465d1b9">More...</a><br/></td></tr>
<tr class="separator:ad1c5957b266c8dcaf687288a2465d1b9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aab7a77388b250367f7e38844485bc513"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__CAN_8h.html#aab7a77388b250367f7e38844485bc513">ARM_CAN_NO_MESSAGE_AVAILABLE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 7)</td></tr>
<tr class="memdesc:aab7a77388b250367f7e38844485bc513"><td class="mdescLeft"> </td><td class="mdescRight">Message is not available. <a href="#aab7a77388b250367f7e38844485bc513">More...</a><br/></td></tr>
<tr class="separator:aab7a77388b250367f7e38844485bc513"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga911a65cc31304d57d283a21476d9ade7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga911a65cc31304d57d283a21476d9ade7">ARM_CAN_UNIT_STATE_INACTIVE</a>   (0U)</td></tr>
<tr class="memdesc:ga911a65cc31304d57d283a21476d9ade7"><td class="mdescLeft"> </td><td class="mdescRight">Unit state: Not active on bus (initialization) <a href="group__can__status__code__ctrls.html#ga911a65cc31304d57d283a21476d9ade7">More...</a><br/></td></tr>
<tr class="separator:ga911a65cc31304d57d283a21476d9ade7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5f72c295ee2b829a8ae33b96466cc0e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga5f72c295ee2b829a8ae33b96466cc0e8">ARM_CAN_UNIT_STATE_ACTIVE</a>   (1U)</td></tr>
<tr class="memdesc:ga5f72c295ee2b829a8ae33b96466cc0e8"><td class="mdescLeft"> </td><td class="mdescRight">Unit state: Active on bus (can generate active error frame) <a href="group__can__status__code__ctrls.html#ga5f72c295ee2b829a8ae33b96466cc0e8">More...</a><br/></td></tr>
<tr class="separator:ga5f72c295ee2b829a8ae33b96466cc0e8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gace2db0f930f935054c21242f735e1922"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#gace2db0f930f935054c21242f735e1922">ARM_CAN_UNIT_STATE_PASSIVE</a>   (2U)</td></tr>
<tr class="memdesc:gace2db0f930f935054c21242f735e1922"><td class="mdescLeft"> </td><td class="mdescRight">Unit state: Error passive (can not generate active error frame) <a href="group__can__status__code__ctrls.html#gace2db0f930f935054c21242f735e1922">More...</a><br/></td></tr>
<tr class="separator:gace2db0f930f935054c21242f735e1922"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadd78b515410235cd77d0a10213ff4192"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#gadd78b515410235cd77d0a10213ff4192">ARM_CAN_UNIT_STATE_BUS_OFF</a>   (3U)</td></tr>
<tr class="memdesc:gadd78b515410235cd77d0a10213ff4192"><td class="mdescLeft"> </td><td class="mdescRight">Unit state: Bus-off (can recover to active state) <a href="group__can__status__code__ctrls.html#gadd78b515410235cd77d0a10213ff4192">More...</a><br/></td></tr>
<tr class="separator:gadd78b515410235cd77d0a10213ff4192"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5332a311f44caec256d59087c705e1e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga5332a311f44caec256d59087c705e1e9">ARM_CAN_LEC_NO_ERROR</a>   (0U)</td></tr>
<tr class="memdesc:ga5332a311f44caec256d59087c705e1e9"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: No error. <a href="group__can__status__code__ctrls.html#ga5332a311f44caec256d59087c705e1e9">More...</a><br/></td></tr>
<tr class="separator:ga5332a311f44caec256d59087c705e1e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0571c3c3e341ac0579aa713fdfdae77e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga0571c3c3e341ac0579aa713fdfdae77e">ARM_CAN_LEC_BIT_ERROR</a>   (1U)</td></tr>
<tr class="memdesc:ga0571c3c3e341ac0579aa713fdfdae77e"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: Bit error. <a href="group__can__status__code__ctrls.html#ga0571c3c3e341ac0579aa713fdfdae77e">More...</a><br/></td></tr>
<tr class="separator:ga0571c3c3e341ac0579aa713fdfdae77e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga33cbda311f4c2f2464e4070dee78b2f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga33cbda311f4c2f2464e4070dee78b2f2">ARM_CAN_LEC_STUFF_ERROR</a>   (2U)</td></tr>
<tr class="memdesc:ga33cbda311f4c2f2464e4070dee78b2f2"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: Bit stuffing error. <a href="group__can__status__code__ctrls.html#ga33cbda311f4c2f2464e4070dee78b2f2">More...</a><br/></td></tr>
<tr class="separator:ga33cbda311f4c2f2464e4070dee78b2f2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1380f80b709ca921634aecdaf34a24e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga1380f80b709ca921634aecdaf34a24e5">ARM_CAN_LEC_CRC_ERROR</a>   (3U)</td></tr>
<tr class="memdesc:ga1380f80b709ca921634aecdaf34a24e5"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: CRC error. <a href="group__can__status__code__ctrls.html#ga1380f80b709ca921634aecdaf34a24e5">More...</a><br/></td></tr>
<tr class="separator:ga1380f80b709ca921634aecdaf34a24e5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f753ba50045b28653fb3215ec2e4b8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#ga9f753ba50045b28653fb3215ec2e4b8a">ARM_CAN_LEC_FORM_ERROR</a>   (4U)</td></tr>
<tr class="memdesc:ga9f753ba50045b28653fb3215ec2e4b8a"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: Illegal fixed-form bit. <a href="group__can__status__code__ctrls.html#ga9f753ba50045b28653fb3215ec2e4b8a">More...</a><br/></td></tr>
<tr class="separator:ga9f753ba50045b28653fb3215ec2e4b8a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaae6e827242137bc4d8976cd4ba73015f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__status__code__ctrls.html#gaae6e827242137bc4d8976cd4ba73015f">ARM_CAN_LEC_ACK_ERROR</a>   (5U)</td></tr>
<tr class="memdesc:gaae6e827242137bc4d8976cd4ba73015f"><td class="mdescLeft"> </td><td class="mdescRight">Last error code: Acknowledgment error. <a href="group__can__status__code__ctrls.html#gaae6e827242137bc4d8976cd4ba73015f">More...</a><br/></td></tr>
<tr class="separator:gaae6e827242137bc4d8976cd4ba73015f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa2347c172c8a8f42ac66cb42cd7a08db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__unit__events.html#gaa2347c172c8a8f42ac66cb42cd7a08db">ARM_CAN_EVENT_UNIT_INACTIVE</a>   (0U)</td></tr>
<tr class="memdesc:gaa2347c172c8a8f42ac66cb42cd7a08db"><td class="mdescLeft"> </td><td class="mdescRight">Unit entered Inactive state. <a href="group__CAN__unit__events.html#gaa2347c172c8a8f42ac66cb42cd7a08db">More...</a><br/></td></tr>
<tr class="separator:gaa2347c172c8a8f42ac66cb42cd7a08db"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0e65231ccb20684d7c8eac80385f8c18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__unit__events.html#ga0e65231ccb20684d7c8eac80385f8c18">ARM_CAN_EVENT_UNIT_ACTIVE</a>   (1U)</td></tr>
<tr class="memdesc:ga0e65231ccb20684d7c8eac80385f8c18"><td class="mdescLeft"> </td><td class="mdescRight">Unit entered Error Active state. <a href="group__CAN__unit__events.html#ga0e65231ccb20684d7c8eac80385f8c18">More...</a><br/></td></tr>
<tr class="separator:ga0e65231ccb20684d7c8eac80385f8c18"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3690f864edd2e124f4f9875fdde9a2eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__unit__events.html#ga3690f864edd2e124f4f9875fdde9a2eb">ARM_CAN_EVENT_UNIT_WARNING</a>   (2U)</td></tr>
<tr class="memdesc:ga3690f864edd2e124f4f9875fdde9a2eb"><td class="mdescLeft"> </td><td class="mdescRight">Unit entered Error Warning state (one or both error counters >= 96) <a href="group__CAN__unit__events.html#ga3690f864edd2e124f4f9875fdde9a2eb">More...</a><br/></td></tr>
<tr class="separator:ga3690f864edd2e124f4f9875fdde9a2eb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9c529d6697fe21e69639224322f8c4b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__unit__events.html#ga9c529d6697fe21e69639224322f8c4b4">ARM_CAN_EVENT_UNIT_PASSIVE</a>   (3U)</td></tr>
<tr class="memdesc:ga9c529d6697fe21e69639224322f8c4b4"><td class="mdescLeft"> </td><td class="mdescRight">Unit entered Error Passive state. <a href="group__CAN__unit__events.html#ga9c529d6697fe21e69639224322f8c4b4">More...</a><br/></td></tr>
<tr class="separator:ga9c529d6697fe21e69639224322f8c4b4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa4f992a97b4ca0f079aec2990a69bed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__unit__events.html#gafa4f992a97b4ca0f079aec2990a69bed">ARM_CAN_EVENT_UNIT_BUS_OFF</a>   (4U)</td></tr>
<tr class="memdesc:gafa4f992a97b4ca0f079aec2990a69bed"><td class="mdescLeft"> </td><td class="mdescRight">Unit entered Bus-off state. <a href="group__CAN__unit__events.html#gafa4f992a97b4ca0f079aec2990a69bed">More...</a><br/></td></tr>
<tr class="separator:gafa4f992a97b4ca0f079aec2990a69bed"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga486f0f35ebc7e3b5931ee68b56703503"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__events.html#ga486f0f35ebc7e3b5931ee68b56703503">ARM_CAN_EVENT_SEND_COMPLETE</a>   (1UL << 0)</td></tr>
<tr class="memdesc:ga486f0f35ebc7e3b5931ee68b56703503"><td class="mdescLeft"> </td><td class="mdescRight">Send complete. <a href="group__CAN__events.html#ga486f0f35ebc7e3b5931ee68b56703503">More...</a><br/></td></tr>
<tr class="separator:ga486f0f35ebc7e3b5931ee68b56703503"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c1082561eeae3b2b8132e81fc241e47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__events.html#ga2c1082561eeae3b2b8132e81fc241e47">ARM_CAN_EVENT_RECEIVE</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga2c1082561eeae3b2b8132e81fc241e47"><td class="mdescLeft"> </td><td class="mdescRight">Message received. <a href="group__CAN__events.html#ga2c1082561eeae3b2b8132e81fc241e47">More...</a><br/></td></tr>
<tr class="separator:ga2c1082561eeae3b2b8132e81fc241e47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6c2d29b5c49d5cd18e97f5931157a94c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CAN__events.html#ga6c2d29b5c49d5cd18e97f5931157a94c">ARM_CAN_EVENT_RECEIVE_OVERRUN</a>   (1UL << 2)</td></tr>
<tr class="memdesc:ga6c2d29b5c49d5cd18e97f5931157a94c"><td class="mdescLeft"> </td><td class="mdescRight">Received message overrun. <a href="group__CAN__events.html#ga6c2d29b5c49d5cd18e97f5931157a94c">More...</a><br/></td></tr>
<tr class="separator:ga6c2d29b5c49d5cd18e97f5931157a94c"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gaac07b9fdf614bf439414f5417aaa376e"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#gaac07b9fdf614bf439414f5417aaa376e">ARM_CAN_SignalUnitEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:gaac07b9fdf614bf439414f5417aaa376e"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__can__interface__gr.html#ga38795d1ed135ce3bd87f31ef1596bccf">ARM_CAN_SignalUnitEvent</a> : Signal CAN Unit Event. <a href="group__can__interface__gr.html#gaac07b9fdf614bf439414f5417aaa376e">More...</a><br/></td></tr>
<tr class="separator:gaac07b9fdf614bf439414f5417aaa376e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7ceceac3e9aa0981c5cacfab88efb4eb"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__interface__gr.html#ga7ceceac3e9aa0981c5cacfab88efb4eb">ARM_CAN_SignalObjectEvent_t</a> )(uint32_t obj_idx, uint32_t event)</td></tr>
<tr class="memdesc:ga7ceceac3e9aa0981c5cacfab88efb4eb"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__can__interface__gr.html#gabfcaeac9e2ca25936ba5a29f2d594e7e">ARM_CAN_SignalObjectEvent</a> : Signal CAN Object Event. <a href="group__can__interface__gr.html#ga7ceceac3e9aa0981c5cacfab88efb4eb">More...</a><br/></td></tr>
<tr class="separator:ga7ceceac3e9aa0981c5cacfab88efb4eb"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga11c12020b81a63a73a8b53e96a7e3dea"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__timeseg__ctrls.html#ga11c12020b81a63a73a8b53e96a7e3dea">ARM_CAN_BITRATE_SELECT</a> { <br/>
  <a class="el" href="group__can__timeseg__ctrls.html#ga11c12020b81a63a73a8b53e96a7e3deaa3b6d191c99f1eba4f01bcc5fbfaf67f3">ARM_CAN_BITRATE_NOMINAL</a>,
<br/>
  <a class="el" href="group__can__timeseg__ctrls.html#ga11c12020b81a63a73a8b53e96a7e3deaaa6c9996de0cdf42da5c02086cd8f16dc">ARM_CAN_BITRATE_FD_DATA</a>
<br/>
}</td></tr>
<tr class="memdesc:ga11c12020b81a63a73a8b53e96a7e3dea"><td class="mdescLeft"> </td><td class="mdescRight">Set the bit rate. <a href="group__can__timeseg__ctrls.html#ga11c12020b81a63a73a8b53e96a7e3dea">More...</a><br/></td></tr>
<tr class="separator:ga11c12020b81a63a73a8b53e96a7e3dea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabbca99c46d478bcf822eee71cdf75dcd"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcd">ARM_CAN_MODE</a> { <br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcda9967a5ebaa045afe54d75e5629676ddc">ARM_CAN_MODE_INITIALIZATION</a>,
<br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcdaa3190344bdf3452462e5c0518ac3cdc4">ARM_CAN_MODE_NORMAL</a>,
<br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcda22a9bb26e68c2a04f641d466040d755d">ARM_CAN_MODE_RESTRICTED</a>,
<br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcda904f68f08c84c4b85c763f5d98c574ab">ARM_CAN_MODE_MONITOR</a>,
<br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcda8579315576baa43860a398a30fd527d8">ARM_CAN_MODE_LOOPBACK_INTERNAL</a>,
<br/>
  <a class="el" href="group__can__bus__mode__ctrls.html#gabbca99c46d478bcf822eee71cdf75dcda5ee1ba60abcf39d575e7cb309e641b9b">ARM_CAN_MODE_LOOPBACK_EXTERNAL</a>
<br/>
}</td></tr>
<tr class="separator:gabbca99c46d478bcf822eee71cdf75dcd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacb04d0f8b3969ee69362ff2b62941d75"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75">ARM_CAN_FILTER_OPERATION</a> { <br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75aa734058b50573de3b0cc49311997806b">ARM_CAN_FILTER_ID_EXACT_ADD</a>,
<br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75a6fdaecf3fa244ef1e4d1069d9c6c95f8">ARM_CAN_FILTER_ID_EXACT_REMOVE</a>,
<br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75a22123bef8e773844fce604c553bf2ed5">ARM_CAN_FILTER_ID_RANGE_ADD</a>,
<br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75a17fea7d388dc702bb3318ecae911f50d">ARM_CAN_FILTER_ID_RANGE_REMOVE</a>,
<br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75ac4ad302fa9b762c1d14964141e234ba9">ARM_CAN_FILTER_ID_MASKABLE_ADD</a>,
<br/>
  <a class="el" href="group__can__filter__operation__ctrls.html#gacb04d0f8b3969ee69362ff2b62941d75ad9573d5d0e112aece7abc0bc24aa92fb">ARM_CAN_FILTER_ID_MASKABLE_REMOVE</a>
<br/>
}</td></tr>
<tr class="separator:gacb04d0f8b3969ee69362ff2b62941d75"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa9488554de0575bc821c9f65213c4cd0"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0">ARM_CAN_OBJ_CONFIG</a> { <br/>
  <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0aebbd0da59658805af30203be66d80249">ARM_CAN_OBJ_INACTIVE</a>,
<br/>
  <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0a3e20952f92855298cd0a39a7f47b3f3c">ARM_CAN_OBJ_TX</a>,
<br/>
  <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0a14780ac7274831ee94f427cbbf67c003">ARM_CAN_OBJ_RX</a>,
<br/>
  <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0ac5d28d180ea9e4328974ffcb8b928a0c">ARM_CAN_OBJ_RX_RTR_TX_DATA</a>,
<br/>
  <a class="el" href="group__can__obj__config__ctrls.html#gaa9488554de0575bc821c9f65213c4cd0a396d7a6cd2353e1a2936405ace6417f5">ARM_CAN_OBJ_TX_RTR_RX_DATA</a>
<br/>
}</td></tr>
<tr class="separator:gaa9488554de0575bc821c9f65213c4cd0"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a88cba309175477a369375827c6e67d16"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(1,2) /* API version */</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a71e16a70efe5e4b21e5622d2b0cb7889"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PROP_SEG_Pos   0UL</td>
</tr>
</table>
</div><div class="memdoc">
<p>bits 7..0 </p>
</div>
</div>
<a class="anchor" id="a018bef85dc771e75a5d0f017393af01a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PROP_SEG_Msk   (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a23658b0cb98b00c900857aef64926922"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PHASE_SEG1_Pos   8UL</td>
</tr>
</table>
</div><div class="memdoc">
<p>bits 15..8 </p>
</div>
</div>
<a class="anchor" id="a4a661aa69c2825d9118a97695ba39546"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PHASE_SEG1_Msk   (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="acd52b5921a5ab0ad0b251957a93a5993"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PHASE_SEG2_Pos   16UL</td>
</tr>
</table>
</div><div class="memdoc">
<p>bits 23..16 </p>
</div>
</div>
<a class="anchor" id="ae4df531026a911d53df401a4b9eec89c"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_PHASE_SEG2_Msk   (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ac233859cfb244895fa47c02d8df02ee8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_SJW_Pos   24UL</td>
</tr>
</table>
</div><div class="memdoc">
<p>bits 28..24 </p>
</div>
</div>
<a class="anchor" id="ac3af13704609a6b14655f00b3d7ac419"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_BIT_SJW_Msk   (0x1FUL << ARM_CAN_BIT_SJW_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aba948867397ee2081d82f5c6db5edd4b"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_CONTROL_Pos   0UL</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a0b9ca7f824e6931dd0945673c4d29d14"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_CONTROL_Msk   (0xFFUL << ARM_CAN_CONTROL_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a874d634951197372eaa0c54b0b5c726f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_ID_IDE_Pos   31UL</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="abd2dde58dd280c29aaba971dcc11ce66"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_ID_IDE_Msk   (1UL << ARM_CAN_ID_IDE_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a09e23c4f9b9b8c68bd8687b43757110d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BITRATE_SELECT   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Bitrate selection not supported. </p>
</div>
</div>
<a class="anchor" id="a90b9d9323a6049fb4fcd1efe7c892294"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BITRATE   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 2)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Requested bitrate not supported. </p>
</div>
</div>
<a class="anchor" id="a2911dd8c4017147690f274fc4ef88f44"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BIT_PROP_SEG   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 3)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Propagation segment value not supported. </p>
</div>
</div>
<a class="anchor" id="aabdfe8d6ad5be07ad471dc00193afb48"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BIT_PHASE_SEG1   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 4)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Phase segment 1 value not supported. </p>
</div>
</div>
<a class="anchor" id="a71cfbc4a4f8a37aafaeb6cf826d32c27"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BIT_PHASE_SEG2   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 5)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Phase segment 2 value not supported. </p>
</div>
</div>
<a class="anchor" id="ad1c5957b266c8dcaf687288a2465d1b9"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_INVALID_BIT_SJW   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 6)</td>
</tr>
</table>
</div><div class="memdoc">
<p>SJW value not supported. </p>
</div>
</div>
<a class="anchor" id="aab7a77388b250367f7e38844485bc513"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_CAN_NO_MESSAGE_AVAILABLE   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 7)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Message is not available. </p>
</div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__DRIVER__VERSION"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a></td></tr>
<tr class="memdesc:structARM__DRIVER__VERSION"><td class="mdescLeft"> </td><td class="mdescRight">Driver Version. <a href="group__common__drv__gr.html#structARM__DRIVER__VERSION">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a43c7ca1eb0786d818624246c09932a74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(major, minor)   (((major) << 8) | (minor))</td></tr>
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<tr class="memitem:ga85752c5de59e8adeb001e35ff5be6be7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga85752c5de59e8adeb001e35ff5be6be7">ARM_DRIVER_OK</a>   0</td></tr>
<tr class="memdesc:ga85752c5de59e8adeb001e35ff5be6be7"><td class="mdescLeft"> </td><td class="mdescRight">Operation succeeded. <a href="group__execution__status.html#ga85752c5de59e8adeb001e35ff5be6be7">More...</a><br/></td></tr>
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<tr class="memitem:ga2f627075447749bb368d3b768be107cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga2f627075447749bb368d3b768be107cb">ARM_DRIVER_ERROR</a>   -1</td></tr>
<tr class="memdesc:ga2f627075447749bb368d3b768be107cb"><td class="mdescLeft"> </td><td class="mdescRight">Unspecified error. <a href="group__execution__status.html#ga2f627075447749bb368d3b768be107cb">More...</a><br/></td></tr>
<tr class="separator:ga2f627075447749bb368d3b768be107cb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga13c1123319c7b9a4735d63447f35116b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga13c1123319c7b9a4735d63447f35116b">ARM_DRIVER_ERROR_BUSY</a>   -2</td></tr>
<tr class="memdesc:ga13c1123319c7b9a4735d63447f35116b"><td class="mdescLeft"> </td><td class="mdescRight">Driver is busy. <a href="group__execution__status.html#ga13c1123319c7b9a4735d63447f35116b">More...</a><br/></td></tr>
<tr class="separator:ga13c1123319c7b9a4735d63447f35116b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0bac892205bb2d586b822e8b178ab310"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga0bac892205bb2d586b822e8b178ab310">ARM_DRIVER_ERROR_TIMEOUT</a>   -3</td></tr>
<tr class="memdesc:ga0bac892205bb2d586b822e8b178ab310"><td class="mdescLeft"> </td><td class="mdescRight">Timeout occurred. <a href="group__execution__status.html#ga0bac892205bb2d586b822e8b178ab310">More...</a><br/></td></tr>
<tr class="separator:ga0bac892205bb2d586b822e8b178ab310"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2efa59e480d82697795439220e6884e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga2efa59e480d82697795439220e6884e4">ARM_DRIVER_ERROR_UNSUPPORTED</a>   -4</td></tr>
<tr class="memdesc:ga2efa59e480d82697795439220e6884e4"><td class="mdescLeft"> </td><td class="mdescRight">Operation not supported. <a href="group__execution__status.html#ga2efa59e480d82697795439220e6884e4">More...</a><br/></td></tr>
<tr class="separator:ga2efa59e480d82697795439220e6884e4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac781d4b70ce17c4c2efe2db045be751c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#gac781d4b70ce17c4c2efe2db045be751c">ARM_DRIVER_ERROR_PARAMETER</a>   -5</td></tr>
<tr class="memdesc:gac781d4b70ce17c4c2efe2db045be751c"><td class="mdescLeft"> </td><td class="mdescRight">Parameter error. <a href="group__execution__status.html#gac781d4b70ce17c4c2efe2db045be751c">More...</a><br/></td></tr>
<tr class="separator:gac781d4b70ce17c4c2efe2db045be751c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a2b5d68f6649598d099b88c0eaee3e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a>   -6</td></tr>
<tr class="memdesc:ga5a2b5d68f6649598d099b88c0eaee3e5"><td class="mdescLeft"> </td><td class="mdescRight">Start of driver specific errors. <a href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">More...</a><br/></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga47d6d7c31f88f3b8ae4aaf9d8444afa5"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> { <br/>
  <a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5ab6f5becc85ebd51c3dd2524a95d2ca35">ARM_POWER_OFF</a>,
<br/>
  <a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5a9ef9e57cbcc948d0e22314e73dc8c434">ARM_POWER_LOW</a>,
<br/>
  <a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5abed52b77a9ce4775570e44a842b1295e">ARM_POWER_FULL</a>
<br/>
}</td></tr>
<tr class="memdesc:ga47d6d7c31f88f3b8ae4aaf9d8444afa5"><td class="mdescLeft"> </td><td class="mdescRight">General power states. <a href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<div class="title">Driver_ETH.h File Reference</div> </div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__ETH__LINK__INFO"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__gr.html#structARM__ETH__LINK__INFO">ARM_ETH_LINK_INFO</a></td></tr>
<tr class="memdesc:structARM__ETH__LINK__INFO"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet link information. <a href="group__eth__interface__gr.html#structARM__ETH__LINK__INFO">More...</a><br/></td></tr>
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<tr class="memitem:structARM__ETH__MAC__ADDR"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__gr.html#structARM__ETH__MAC__ADDR">ARM_ETH_MAC_ADDR</a></td></tr>
<tr class="memdesc:structARM__ETH__MAC__ADDR"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet MAC Address. <a href="group__eth__interface__gr.html#structARM__ETH__MAC__ADDR">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga468c848ddf75d7925130171af1ec2ac7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__types1.html#ga468c848ddf75d7925130171af1ec2ac7">ARM_ETH_INTERFACE_MII</a>   (0)</td></tr>
<tr class="memdesc:ga468c848ddf75d7925130171af1ec2ac7"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet Media Interface type. <a href="group__eth__interface__types1.html#ga468c848ddf75d7925130171af1ec2ac7">More...</a><br/></td></tr>
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<tr class="memitem:gac0361b34fbec9c19840ad0349e4c388b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__types1.html#gac0361b34fbec9c19840ad0349e4c388b">ARM_ETH_INTERFACE_RMII</a>   (1)</td></tr>
<tr class="memdesc:gac0361b34fbec9c19840ad0349e4c388b"><td class="mdescLeft"> </td><td class="mdescRight">Reduced Media Independent Interface (RMII) <a href="group__eth__interface__types1.html#gac0361b34fbec9c19840ad0349e4c388b">More...</a><br/></td></tr>
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<tr class="memitem:ga24047d142be48bbc241e8d6eacb5cf7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__types1.html#ga24047d142be48bbc241e8d6eacb5cf7a">ARM_ETH_INTERFACE_SMII</a>   (2)</td></tr>
<tr class="memdesc:ga24047d142be48bbc241e8d6eacb5cf7a"><td class="mdescLeft"> </td><td class="mdescRight">Serial Media Independent Interface (SMII) <a href="group__eth__interface__types1.html#ga24047d142be48bbc241e8d6eacb5cf7a">More...</a><br/></td></tr>
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<tr class="memitem:a1f834c4c785d7f69b1eaca011ee298ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH_8h.html#a1f834c4c785d7f69b1eaca011ee298ec">ARM_ETH_SPEED_10M</a>   (0)</td></tr>
<tr class="memdesc:a1f834c4c785d7f69b1eaca011ee298ec"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet link speed. <a href="#a1f834c4c785d7f69b1eaca011ee298ec">More...</a><br/></td></tr>
<tr class="separator:a1f834c4c785d7f69b1eaca011ee298ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3bddfc4cf5645f8568d9cb6621fd606a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH_8h.html#a3bddfc4cf5645f8568d9cb6621fd606a">ARM_ETH_SPEED_100M</a>   (1)</td></tr>
<tr class="memdesc:a3bddfc4cf5645f8568d9cb6621fd606a"><td class="mdescLeft"> </td><td class="mdescRight">100 Mbps link speed <a href="#a3bddfc4cf5645f8568d9cb6621fd606a">More...</a><br/></td></tr>
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<tr class="memitem:a218f470079b7c04de6776d467a53772a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH_8h.html#a218f470079b7c04de6776d467a53772a">ARM_ETH_SPEED_1G</a>   (2)</td></tr>
<tr class="memdesc:a218f470079b7c04de6776d467a53772a"><td class="mdescLeft"> </td><td class="mdescRight">1 Gpbs link speed <a href="#a218f470079b7c04de6776d467a53772a">More...</a><br/></td></tr>
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<tr class="memitem:acb15afc2bfe61c56049b7279d6eae8fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH_8h.html#acb15afc2bfe61c56049b7279d6eae8fe">ARM_ETH_DUPLEX_HALF</a>   (0)</td></tr>
<tr class="memdesc:acb15afc2bfe61c56049b7279d6eae8fe"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet duplex mode. <a href="#acb15afc2bfe61c56049b7279d6eae8fe">More...</a><br/></td></tr>
<tr class="separator:acb15afc2bfe61c56049b7279d6eae8fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7848c83cd1fd6b2645c17919c2990354"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH_8h.html#a7848c83cd1fd6b2645c17919c2990354">ARM_ETH_DUPLEX_FULL</a>   (1)</td></tr>
<tr class="memdesc:a7848c83cd1fd6b2645c17919c2990354"><td class="mdescLeft"> </td><td class="mdescRight">Full duplex link. <a href="#a7848c83cd1fd6b2645c17919c2990354">More...</a><br/></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:gacf7db5320eb841b462a4af3c56cc9291"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__interface__gr.html#gacf7db5320eb841b462a4af3c56cc9291">ARM_ETH_LINK_STATE</a> { <br/>
  <a class="el" href="group__eth__interface__gr.html#gacf7db5320eb841b462a4af3c56cc9291a5f635c9352db6cb6fa9ad95660850487">ARM_ETH_LINK_DOWN</a>,
<br/>
  <a class="el" href="group__eth__interface__gr.html#gacf7db5320eb841b462a4af3c56cc9291ab5e5b02c3c8a5a0fefcf69f3be7e31c1">ARM_ETH_LINK_UP</a>
<br/>
}</td></tr>
<tr class="memdesc:gacf7db5320eb841b462a4af3c56cc9291"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet link state. <a href="group__eth__interface__gr.html#gacf7db5320eb841b462a4af3c56cc9291">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_ETH_SPEED_10M   (0)</td>
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<p>Ethernet link speed. </p>
<p>10 Mbps link speed </p>
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<td class="memname">#define ARM_ETH_SPEED_100M   (1)</td>
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<p>100 Mbps link speed </p>
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<a class="anchor" id="a218f470079b7c04de6776d467a53772a"></a>
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<td class="memname">#define ARM_ETH_SPEED_1G   (2)</td>
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<p>1 Gpbs link speed </p>
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<td class="memname">#define ARM_ETH_DUPLEX_HALF   (0)</td>
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<p>Ethernet duplex mode. </p>
<p>Half duplex link </p>
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<p>Full duplex link. </p>
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Functions</h2></td></tr>
<tr class="memitem:ga86b15062c297384ad5842dd57b9d6b1d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga86b15062c297384ad5842dd57b9d6b1d">ARM_ETH_MAC_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga86b15062c297384ad5842dd57b9d6b1d"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__eth__mac__interface__gr.html#ga86b15062c297384ad5842dd57b9d6b1d">More...</a><br/></td></tr>
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<tr class="memitem:ga2b13b230502736d8c7679b359dff20d0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__CAPABILITIES">ARM_ETH_MAC_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga2b13b230502736d8c7679b359dff20d0">ARM_ETH_MAC_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga2b13b230502736d8c7679b359dff20d0"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__eth__mac__interface__gr.html#ga2b13b230502736d8c7679b359dff20d0">More...</a><br/></td></tr>
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<tr class="memitem:gacf42d11b171cd032f0ec1de6db2b6832"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gacf42d11b171cd032f0ec1de6db2b6832">ARM_ETH_MAC_Initialize</a> (<a class="el" href="group__eth__mac__interface__gr.html#gadfc95cb09c541a29a72da86963668726">ARM_ETH_MAC_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:gacf42d11b171cd032f0ec1de6db2b6832"><td class="mdescLeft"> </td><td class="mdescRight">Initialize Ethernet MAC Device. <a href="group__eth__mac__interface__gr.html#gacf42d11b171cd032f0ec1de6db2b6832">More...</a><br/></td></tr>
<tr class="separator:gacf42d11b171cd032f0ec1de6db2b6832"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacb2c2ae06f32328775bffbdeaaabfb5d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gacb2c2ae06f32328775bffbdeaaabfb5d">ARM_ETH_MAC_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gacb2c2ae06f32328775bffbdeaaabfb5d"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize Ethernet MAC Device. <a href="group__eth__mac__interface__gr.html#gacb2c2ae06f32328775bffbdeaaabfb5d">More...</a><br/></td></tr>
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<tr class="memitem:ga346fef040a0e9bac5762a04a306b1be7"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga346fef040a0e9bac5762a04a306b1be7">ARM_ETH_MAC_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga346fef040a0e9bac5762a04a306b1be7"><td class="mdescLeft"> </td><td class="mdescRight">Control Ethernet MAC Device Power. <a href="group__eth__mac__interface__gr.html#ga346fef040a0e9bac5762a04a306b1be7">More...</a><br/></td></tr>
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<tr class="memitem:ga66308c1e791952047e974bd653037fae"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga66308c1e791952047e974bd653037fae">ARM_ETH_MAC_GetMacAddress</a> (<a class="el" href="group__eth__interface__gr.html#structARM__ETH__MAC__ADDR">ARM_ETH_MAC_ADDR</a> *ptr_addr)</td></tr>
<tr class="memdesc:ga66308c1e791952047e974bd653037fae"><td class="mdescLeft"> </td><td class="mdescRight">Get Ethernet MAC Address. <a href="group__eth__mac__interface__gr.html#ga66308c1e791952047e974bd653037fae">More...</a><br/></td></tr>
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<tr class="memitem:ga7cc3d17c7312c5032202dfd9a915f24a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga7cc3d17c7312c5032202dfd9a915f24a">ARM_ETH_MAC_SetMacAddress</a> (const <a class="el" href="group__eth__interface__gr.html#structARM__ETH__MAC__ADDR">ARM_ETH_MAC_ADDR</a> *ptr_addr)</td></tr>
<tr class="memdesc:ga7cc3d17c7312c5032202dfd9a915f24a"><td class="mdescLeft"> </td><td class="mdescRight">Set Ethernet MAC Address. <a href="group__eth__mac__interface__gr.html#ga7cc3d17c7312c5032202dfd9a915f24a">More...</a><br/></td></tr>
<tr class="separator:ga7cc3d17c7312c5032202dfd9a915f24a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga150fe30290275a4b32756f94208124e8"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga150fe30290275a4b32756f94208124e8">ARM_ETH_MAC_SetAddressFilter</a> (const <a class="el" href="group__eth__interface__gr.html#structARM__ETH__MAC__ADDR">ARM_ETH_MAC_ADDR</a> *ptr_addr, uint32_t num_addr)</td></tr>
<tr class="memdesc:ga150fe30290275a4b32756f94208124e8"><td class="mdescLeft"> </td><td class="mdescRight">Configure Address Filter. <a href="group__eth__mac__interface__gr.html#ga150fe30290275a4b32756f94208124e8">More...</a><br/></td></tr>
<tr class="separator:ga150fe30290275a4b32756f94208124e8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5bf58defdb239ed7dc948f1da147a1c3"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga5bf58defdb239ed7dc948f1da147a1c3">ARM_ETH_MAC_SendFrame</a> (const uint8_t *frame, uint32_t len, uint32_t flags)</td></tr>
<tr class="memdesc:ga5bf58defdb239ed7dc948f1da147a1c3"><td class="mdescLeft"> </td><td class="mdescRight">Send Ethernet frame. <a href="group__eth__mac__interface__gr.html#ga5bf58defdb239ed7dc948f1da147a1c3">More...</a><br/></td></tr>
<tr class="separator:ga5bf58defdb239ed7dc948f1da147a1c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4b79f57d8624bb4410ee12c73a483993"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga4b79f57d8624bb4410ee12c73a483993">ARM_ETH_MAC_ReadFrame</a> (uint8_t *frame, uint32_t len)</td></tr>
<tr class="memdesc:ga4b79f57d8624bb4410ee12c73a483993"><td class="mdescLeft"> </td><td class="mdescRight">Read data of received Ethernet frame. <a href="group__eth__mac__interface__gr.html#ga4b79f57d8624bb4410ee12c73a483993">More...</a><br/></td></tr>
<tr class="separator:ga4b79f57d8624bb4410ee12c73a483993"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5ee86d6b0efab5329b9bc191c23a466d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga5ee86d6b0efab5329b9bc191c23a466d">ARM_ETH_MAC_GetRxFrameSize</a> (void)</td></tr>
<tr class="memdesc:ga5ee86d6b0efab5329b9bc191c23a466d"><td class="mdescLeft"> </td><td class="mdescRight">Get size of received Ethernet frame. <a href="group__eth__mac__interface__gr.html#ga5ee86d6b0efab5329b9bc191c23a466d">More...</a><br/></td></tr>
<tr class="separator:ga5ee86d6b0efab5329b9bc191c23a466d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa7c6865fb09754be869778142466c5e4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gaa7c6865fb09754be869778142466c5e4">ARM_ETH_MAC_GetRxFrameTime</a> (<a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__TIME">ARM_ETH_MAC_TIME</a> *time)</td></tr>
<tr class="memdesc:gaa7c6865fb09754be869778142466c5e4"><td class="mdescLeft"> </td><td class="mdescRight">Get time of received Ethernet frame. <a href="group__eth__mac__interface__gr.html#gaa7c6865fb09754be869778142466c5e4">More...</a><br/></td></tr>
<tr class="separator:gaa7c6865fb09754be869778142466c5e4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga115b5c7e149aec2b181de760f5d83f60"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga115b5c7e149aec2b181de760f5d83f60">ARM_ETH_MAC_GetTxFrameTime</a> (<a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__TIME">ARM_ETH_MAC_TIME</a> *time)</td></tr>
<tr class="memdesc:ga115b5c7e149aec2b181de760f5d83f60"><td class="mdescLeft"> </td><td class="mdescRight">Get time of transmitted Ethernet frame. <a href="group__eth__mac__interface__gr.html#ga115b5c7e149aec2b181de760f5d83f60">More...</a><br/></td></tr>
<tr class="separator:ga115b5c7e149aec2b181de760f5d83f60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac3e90c66058d20077f04ac8e8b8d0536"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gac3e90c66058d20077f04ac8e8b8d0536">ARM_ETH_MAC_Control</a> (uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:gac3e90c66058d20077f04ac8e8b8d0536"><td class="mdescLeft"> </td><td class="mdescRight">Control Ethernet Interface. <a href="group__eth__mac__interface__gr.html#gac3e90c66058d20077f04ac8e8b8d0536">More...</a><br/></td></tr>
<tr class="separator:gac3e90c66058d20077f04ac8e8b8d0536"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga85d9dc865af3702b71a514b18a588643"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga85d9dc865af3702b71a514b18a588643">ARM_ETH_MAC_ControlTimer</a> (uint32_t control, <a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__TIME">ARM_ETH_MAC_TIME</a> *time)</td></tr>
<tr class="memdesc:ga85d9dc865af3702b71a514b18a588643"><td class="mdescLeft"> </td><td class="mdescRight">Control Precision Timer. <a href="group__eth__mac__interface__gr.html#ga85d9dc865af3702b71a514b18a588643">More...</a><br/></td></tr>
<tr class="separator:ga85d9dc865af3702b71a514b18a588643"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaded29ad58366e9222487db9944373c29"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gaded29ad58366e9222487db9944373c29">ARM_ETH_MAC_PHY_Read</a> (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)</td></tr>
<tr class="memdesc:gaded29ad58366e9222487db9944373c29"><td class="mdescLeft"> </td><td class="mdescRight">Read Ethernet PHY Register through Management Interface. <a href="group__eth__mac__interface__gr.html#gaded29ad58366e9222487db9944373c29">More...</a><br/></td></tr>
<tr class="separator:gaded29ad58366e9222487db9944373c29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga79dd38672749aeebd28f39d9b4f813ce"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#ga79dd38672749aeebd28f39d9b4f813ce">ARM_ETH_MAC_PHY_Write</a> (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)</td></tr>
<tr class="memdesc:ga79dd38672749aeebd28f39d9b4f813ce"><td class="mdescLeft"> </td><td class="mdescRight">Write Ethernet PHY Register through Management Interface. <a href="group__eth__mac__interface__gr.html#ga79dd38672749aeebd28f39d9b4f813ce">More...</a><br/></td></tr>
<tr class="separator:ga79dd38672749aeebd28f39d9b4f813ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0697be4c4229601f3bfc17e2978ada6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gae0697be4c4229601f3bfc17e2978ada6">ARM_ETH_MAC_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:gae0697be4c4229601f3bfc17e2978ada6"><td class="mdescLeft"> </td><td class="mdescRight">Callback function that signals a Ethernet Event. <a href="group__eth__mac__interface__gr.html#gae0697be4c4229601f3bfc17e2978ada6">More...</a><br/></td></tr>
<tr class="separator:gae0697be4c4229601f3bfc17e2978ada6"><td class="memSeparator" colspan="2"> </td></tr>
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<div class="title">Driver_ETH_MAC.h File Reference</div> </div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__ETH__MAC__TIME"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__TIME">ARM_ETH_MAC_TIME</a></td></tr>
<tr class="memdesc:structARM__ETH__MAC__TIME"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet MAC Time. <a href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__TIME">More...</a><br/></td></tr>
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<tr class="memitem:structARM__ETH__MAC__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__CAPABILITIES">ARM_ETH_MAC_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__ETH__MAC__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">Ethernet MAC Capabilities. <a href="group__eth__mac__interface__gr.html#structARM__ETH__MAC__CAPABILITIES">More...</a><br/></td></tr>
<tr class="separator:structARM__ETH__MAC__CAPABILITIES"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:structARM__DRIVER__ETH__MAC"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#structARM__DRIVER__ETH__MAC">ARM_DRIVER_ETH_MAC</a></td></tr>
<tr class="memdesc:structARM__DRIVER__ETH__MAC"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the Ethernet MAC Driver. <a href="group__eth__mac__interface__gr.html#structARM__DRIVER__ETH__MAC">More...</a><br/></td></tr>
<tr class="separator:structARM__DRIVER__ETH__MAC"><td class="memSeparator" colspan="2"> </td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a89ade7fd7f91b1b6e21883a8f823a8cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#a89ade7fd7f91b1b6e21883a8f823a8cc">ARM_ETH_MAC_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,1) /* API version */</td></tr>
<tr class="separator:a89ade7fd7f91b1b6e21883a8f823a8cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ade64adbfd1c8076b7acf0b3994fb4df2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#ade64adbfd1c8076b7acf0b3994fb4df2">_ARM_Driver_ETH_MAC_</a>(n)   Driver_ETH_MAC##n</td></tr>
<tr class="separator:ade64adbfd1c8076b7acf0b3994fb4df2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abc6ea74fb57580e41b7321fb255da6d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#abc6ea74fb57580e41b7321fb255da6d0">ARM_Driver_ETH_MAC_</a>(n)   <a class="el" href="Driver__ETH__MAC_8h.html#ade64adbfd1c8076b7acf0b3994fb4df2">_ARM_Driver_ETH_MAC_</a>(n)</td></tr>
<tr class="separator:abc6ea74fb57580e41b7321fb255da6d0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7819c7a1aa7bbc13dc42d0fd7e75a23c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#ga7819c7a1aa7bbc13dc42d0fd7e75a23c">ARM_ETH_MAC_CONFIGURE</a>   (0x01)</td></tr>
<tr class="memdesc:ga7819c7a1aa7bbc13dc42d0fd7e75a23c"><td class="mdescLeft"> </td><td class="mdescRight">Configure MAC; arg = configuration. <a href="group__eth__mac__ctrls.html#ga7819c7a1aa7bbc13dc42d0fd7e75a23c">More...</a><br/></td></tr>
<tr class="separator:ga7819c7a1aa7bbc13dc42d0fd7e75a23c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3a98c8a7ee5ed4b1ffd250eecaeefe5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#ga3a98c8a7ee5ed4b1ffd250eecaeefe5c">ARM_ETH_MAC_CONTROL_TX</a>   (0x02)</td></tr>
<tr class="memdesc:ga3a98c8a7ee5ed4b1ffd250eecaeefe5c"><td class="mdescLeft"> </td><td class="mdescRight">Transmitter; arg: 0=disabled (default), 1=enabled. <a href="group__eth__mac__ctrls.html#ga3a98c8a7ee5ed4b1ffd250eecaeefe5c">More...</a><br/></td></tr>
<tr class="separator:ga3a98c8a7ee5ed4b1ffd250eecaeefe5c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0964364b81b38b6e1fbf7196f3be869"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#gae0964364b81b38b6e1fbf7196f3be869">ARM_ETH_MAC_CONTROL_RX</a>   (0x03)</td></tr>
<tr class="memdesc:gae0964364b81b38b6e1fbf7196f3be869"><td class="mdescLeft"> </td><td class="mdescRight">Receiver; arg: 0=disabled (default), 1=enabled. <a href="group__eth__mac__ctrls.html#gae0964364b81b38b6e1fbf7196f3be869">More...</a><br/></td></tr>
<tr class="separator:gae0964364b81b38b6e1fbf7196f3be869"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga530812ef349a2e297f23de72e660fe27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#ga530812ef349a2e297f23de72e660fe27">ARM_ETH_MAC_FLUSH</a>   (0x04)</td></tr>
<tr class="memdesc:ga530812ef349a2e297f23de72e660fe27"><td class="mdescLeft"> </td><td class="mdescRight">Flush buffer; arg = ARM_ETH_MAC_FLUSH_... <a href="group__eth__mac__ctrls.html#ga530812ef349a2e297f23de72e660fe27">More...</a><br/></td></tr>
<tr class="separator:ga530812ef349a2e297f23de72e660fe27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4afe66589216f566f529af52f9075fdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#ga4afe66589216f566f529af52f9075fdf">ARM_ETH_MAC_SLEEP</a>   (0x05)</td></tr>
<tr class="memdesc:ga4afe66589216f566f529af52f9075fdf"><td class="mdescLeft"> </td><td class="mdescRight">Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit. <a href="group__eth__mac__ctrls.html#ga4afe66589216f566f529af52f9075fdf">More...</a><br/></td></tr>
<tr class="separator:ga4afe66589216f566f529af52f9075fdf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab332b58ba320e73864830dc42ad74181"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__ctrls.html#gab332b58ba320e73864830dc42ad74181">ARM_ETH_MAC_VLAN_FILTER</a>   (0x06)</td></tr>
<tr class="memdesc:gab332b58ba320e73864830dc42ad74181"><td class="mdescLeft"> </td><td class="mdescRight">VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) <a href="group__eth__mac__ctrls.html#gab332b58ba320e73864830dc42ad74181">More...</a><br/></td></tr>
<tr class="separator:gab332b58ba320e73864830dc42ad74181"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad7fd5c5f4d4f39a56466c2d34cb699ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#ad7fd5c5f4d4f39a56466c2d34cb699ef">ARM_ETH_MAC_SPEED_Pos</a>   0</td></tr>
<tr class="separator:ad7fd5c5f4d4f39a56466c2d34cb699ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7f3cf200085c3387a5572102af2ee2da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#a7f3cf200085c3387a5572102af2ee2da">ARM_ETH_MAC_SPEED_Msk</a>   (3UL << ARM_ETH_MAC_SPEED_Pos)</td></tr>
<tr class="separator:a7f3cf200085c3387a5572102af2ee2da"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8c5b40d018ecfad05fe2546ba717c1d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga8c5b40d018ecfad05fe2546ba717c1d4">ARM_ETH_MAC_SPEED_10M</a>   (<a class="el" href="Driver__ETH_8h.html#a1f834c4c785d7f69b1eaca011ee298ec">ARM_ETH_SPEED_10M</a> << <a class="el" href="Driver__ETH__MAC_8h.html#ad7fd5c5f4d4f39a56466c2d34cb699ef">ARM_ETH_MAC_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:ga8c5b40d018ecfad05fe2546ba717c1d4"><td class="mdescLeft"> </td><td class="mdescRight">10 Mbps link speed <a href="group__eth__mac__configuration__ctrls.html#ga8c5b40d018ecfad05fe2546ba717c1d4">More...</a><br/></td></tr>
<tr class="separator:ga8c5b40d018ecfad05fe2546ba717c1d4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga29160c83a7b0952c64053d86789c6490"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga29160c83a7b0952c64053d86789c6490">ARM_ETH_MAC_SPEED_100M</a>   (<a class="el" href="Driver__ETH_8h.html#a3bddfc4cf5645f8568d9cb6621fd606a">ARM_ETH_SPEED_100M</a> << <a class="el" href="Driver__ETH__MAC_8h.html#ad7fd5c5f4d4f39a56466c2d34cb699ef">ARM_ETH_MAC_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:ga29160c83a7b0952c64053d86789c6490"><td class="mdescLeft"> </td><td class="mdescRight">100 Mbps link speed <a href="group__eth__mac__configuration__ctrls.html#ga29160c83a7b0952c64053d86789c6490">More...</a><br/></td></tr>
<tr class="separator:ga29160c83a7b0952c64053d86789c6490"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8acefed744d8397a1777b9fd0e6230d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga8acefed744d8397a1777b9fd0e6230d2">ARM_ETH_MAC_SPEED_1G</a>   (<a class="el" href="Driver__ETH_8h.html#a218f470079b7c04de6776d467a53772a">ARM_ETH_SPEED_1G</a> << <a class="el" href="Driver__ETH__MAC_8h.html#ad7fd5c5f4d4f39a56466c2d34cb699ef">ARM_ETH_MAC_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:ga8acefed744d8397a1777b9fd0e6230d2"><td class="mdescLeft"> </td><td class="mdescRight">1 Gpbs link speed <a href="group__eth__mac__configuration__ctrls.html#ga8acefed744d8397a1777b9fd0e6230d2">More...</a><br/></td></tr>
<tr class="separator:ga8acefed744d8397a1777b9fd0e6230d2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a245688f6265e8d017435dc6d2c233b87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#a245688f6265e8d017435dc6d2c233b87">ARM_ETH_MAC_DUPLEX_Pos</a>   2</td></tr>
<tr class="separator:a245688f6265e8d017435dc6d2c233b87"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9249afa842bb7e1088a7729542f91e22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__MAC_8h.html#a9249afa842bb7e1088a7729542f91e22">ARM_ETH_MAC_DUPLEX_Msk</a>   (1UL << ARM_ETH_MAC_DUPLEX_Pos)</td></tr>
<tr class="separator:a9249afa842bb7e1088a7729542f91e22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadb0fe2c5a1e21b0656d39c788ae22f36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#gadb0fe2c5a1e21b0656d39c788ae22f36">ARM_ETH_MAC_DUPLEX_HALF</a>   (<a class="el" href="Driver__ETH_8h.html#acb15afc2bfe61c56049b7279d6eae8fe">ARM_ETH_DUPLEX_HALF</a> << <a class="el" href="Driver__ETH__MAC_8h.html#a245688f6265e8d017435dc6d2c233b87">ARM_ETH_MAC_DUPLEX_Pos</a>)</td></tr>
<tr class="memdesc:gadb0fe2c5a1e21b0656d39c788ae22f36"><td class="mdescLeft"> </td><td class="mdescRight">Half duplex link. <a href="group__eth__mac__configuration__ctrls.html#gadb0fe2c5a1e21b0656d39c788ae22f36">More...</a><br/></td></tr>
<tr class="separator:gadb0fe2c5a1e21b0656d39c788ae22f36"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad5a7d4b5b8a31825eff1504e3828d8f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#gad5a7d4b5b8a31825eff1504e3828d8f6">ARM_ETH_MAC_DUPLEX_FULL</a>   (<a class="el" href="Driver__ETH_8h.html#a7848c83cd1fd6b2645c17919c2990354">ARM_ETH_DUPLEX_FULL</a> << <a class="el" href="Driver__ETH__MAC_8h.html#a245688f6265e8d017435dc6d2c233b87">ARM_ETH_MAC_DUPLEX_Pos</a>)</td></tr>
<tr class="memdesc:gad5a7d4b5b8a31825eff1504e3828d8f6"><td class="mdescLeft"> </td><td class="mdescRight">Full duplex link. <a href="group__eth__mac__configuration__ctrls.html#gad5a7d4b5b8a31825eff1504e3828d8f6">More...</a><br/></td></tr>
<tr class="separator:gad5a7d4b5b8a31825eff1504e3828d8f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab32765f35c35b672ee476278fe24a24e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#gab32765f35c35b672ee476278fe24a24e">ARM_ETH_MAC_LOOPBACK</a>   (1UL << 4)</td></tr>
<tr class="memdesc:gab32765f35c35b672ee476278fe24a24e"><td class="mdescLeft"> </td><td class="mdescRight">Loop-back test mode. <a href="group__eth__mac__configuration__ctrls.html#gab32765f35c35b672ee476278fe24a24e">More...</a><br/></td></tr>
<tr class="separator:gab32765f35c35b672ee476278fe24a24e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga281dfed993b5666ed999709b9f28578f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga281dfed993b5666ed999709b9f28578f">ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX</a>   (1UL << 5)</td></tr>
<tr class="memdesc:ga281dfed993b5666ed999709b9f28578f"><td class="mdescLeft"> </td><td class="mdescRight">Receiver Checksum offload. <a href="group__eth__mac__configuration__ctrls.html#ga281dfed993b5666ed999709b9f28578f">More...</a><br/></td></tr>
<tr class="separator:ga281dfed993b5666ed999709b9f28578f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7272d2c55aeeeadbb95c591cbf6c1a2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga7272d2c55aeeeadbb95c591cbf6c1a2e">ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ga7272d2c55aeeeadbb95c591cbf6c1a2e"><td class="mdescLeft"> </td><td class="mdescRight">Transmitter Checksum offload. <a href="group__eth__mac__configuration__ctrls.html#ga7272d2c55aeeeadbb95c591cbf6c1a2e">More...</a><br/></td></tr>
<tr class="separator:ga7272d2c55aeeeadbb95c591cbf6c1a2e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga43792feab641c3c87eafb943351ab0f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga43792feab641c3c87eafb943351ab0f4">ARM_ETH_MAC_ADDRESS_BROADCAST</a>   (1UL << 7)</td></tr>
<tr class="memdesc:ga43792feab641c3c87eafb943351ab0f4"><td class="mdescLeft"> </td><td class="mdescRight">Accept frames with Broadcast address. <a href="group__eth__mac__configuration__ctrls.html#ga43792feab641c3c87eafb943351ab0f4">More...</a><br/></td></tr>
<tr class="separator:ga43792feab641c3c87eafb943351ab0f4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1d3ff8c63362b385548fe91730f20588"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#ga1d3ff8c63362b385548fe91730f20588">ARM_ETH_MAC_ADDRESS_MULTICAST</a>   (1UL << 8)</td></tr>
<tr class="memdesc:ga1d3ff8c63362b385548fe91730f20588"><td class="mdescLeft"> </td><td class="mdescRight">Accept frames with any Multicast address. <a href="group__eth__mac__configuration__ctrls.html#ga1d3ff8c63362b385548fe91730f20588">More...</a><br/></td></tr>
<tr class="separator:ga1d3ff8c63362b385548fe91730f20588"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab29ab9e295807f4c59ddd1c4642086d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__configuration__ctrls.html#gab29ab9e295807f4c59ddd1c4642086d1">ARM_ETH_MAC_ADDRESS_ALL</a>   (1UL << 9)</td></tr>
<tr class="memdesc:gab29ab9e295807f4c59ddd1c4642086d1"><td class="mdescLeft"> </td><td class="mdescRight">Accept frames with any address (Promiscuous Mode) <a href="group__eth__mac__configuration__ctrls.html#gab29ab9e295807f4c59ddd1c4642086d1">More...</a><br/></td></tr>
<tr class="separator:gab29ab9e295807f4c59ddd1c4642086d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac18950811038319960756f063e1ef6d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__flush__flag__ctrls.html#gac18950811038319960756f063e1ef6d4">ARM_ETH_MAC_FLUSH_RX</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gac18950811038319960756f063e1ef6d4"><td class="mdescLeft"> </td><td class="mdescRight">Flush Receive buffer. <a href="group__eth__mac__flush__flag__ctrls.html#gac18950811038319960756f063e1ef6d4">More...</a><br/></td></tr>
<tr class="separator:gac18950811038319960756f063e1ef6d4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2d10ff33f4f4927820c6a17a2262b120"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__flush__flag__ctrls.html#ga2d10ff33f4f4927820c6a17a2262b120">ARM_ETH_MAC_FLUSH_TX</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga2d10ff33f4f4927820c6a17a2262b120"><td class="mdescLeft"> </td><td class="mdescRight">Flush Transmit buffer. <a href="group__eth__mac__flush__flag__ctrls.html#ga2d10ff33f4f4927820c6a17a2262b120">More...</a><br/></td></tr>
<tr class="separator:ga2d10ff33f4f4927820c6a17a2262b120"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2511c9e4c22a2b351ce2e454be1c9427"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__vlan__filter__ctrls.html#ga2511c9e4c22a2b351ce2e454be1c9427">ARM_ETH_MAC_VLAN_FILTER_ID_ONLY</a>   (1UL << 16)</td></tr>
<tr class="memdesc:ga2511c9e4c22a2b351ce2e454be1c9427"><td class="mdescLeft"> </td><td class="mdescRight">Compare only the VLAN Identifier (12-bit) <a href="group__eth__mac__vlan__filter__ctrls.html#ga2511c9e4c22a2b351ce2e454be1c9427">More...</a><br/></td></tr>
<tr class="separator:ga2511c9e4c22a2b351ce2e454be1c9427"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab7bd6dea5bb57240291db71e95c99d9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__frame__transmit__ctrls.html#gab7bd6dea5bb57240291db71e95c99d9c">ARM_ETH_MAC_TX_FRAME_FRAGMENT</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gab7bd6dea5bb57240291db71e95c99d9c"><td class="mdescLeft"> </td><td class="mdescRight">Indicate frame fragment. <a href="group__eth__mac__frame__transmit__ctrls.html#gab7bd6dea5bb57240291db71e95c99d9c">More...</a><br/></td></tr>
<tr class="separator:gab7bd6dea5bb57240291db71e95c99d9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga91a923680ea0dad758b8950a3fbd237e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__frame__transmit__ctrls.html#ga91a923680ea0dad758b8950a3fbd237e">ARM_ETH_MAC_TX_FRAME_EVENT</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga91a923680ea0dad758b8950a3fbd237e"><td class="mdescLeft"> </td><td class="mdescRight">Generate event when frame is transmitted. <a href="group__eth__mac__frame__transmit__ctrls.html#ga91a923680ea0dad758b8950a3fbd237e">More...</a><br/></td></tr>
<tr class="separator:ga91a923680ea0dad758b8950a3fbd237e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gade137f65dd345ae40e93c77d495f9b54"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__frame__transmit__ctrls.html#gade137f65dd345ae40e93c77d495f9b54">ARM_ETH_MAC_TX_FRAME_TIMESTAMP</a>   (1UL << 2)</td></tr>
<tr class="memdesc:gade137f65dd345ae40e93c77d495f9b54"><td class="mdescLeft"> </td><td class="mdescRight">Capture frame time stamp. <a href="group__eth__mac__frame__transmit__ctrls.html#gade137f65dd345ae40e93c77d495f9b54">More...</a><br/></td></tr>
<tr class="separator:gade137f65dd345ae40e93c77d495f9b54"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad9a439b9727c032a7d851df2a7a622c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#gad9a439b9727c032a7d851df2a7a622c2">ARM_ETH_MAC_TIMER_GET_TIME</a>   (0x01)</td></tr>
<tr class="memdesc:gad9a439b9727c032a7d851df2a7a622c2"><td class="mdescLeft"> </td><td class="mdescRight">Get current time. <a href="group__eth__mac__time__control.html#gad9a439b9727c032a7d851df2a7a622c2">More...</a><br/></td></tr>
<tr class="separator:gad9a439b9727c032a7d851df2a7a622c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5e867a003c06046d7944bcb5723e6049"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#ga5e867a003c06046d7944bcb5723e6049">ARM_ETH_MAC_TIMER_SET_TIME</a>   (0x02)</td></tr>
<tr class="memdesc:ga5e867a003c06046d7944bcb5723e6049"><td class="mdescLeft"> </td><td class="mdescRight">Set new time. <a href="group__eth__mac__time__control.html#ga5e867a003c06046d7944bcb5723e6049">More...</a><br/></td></tr>
<tr class="separator:ga5e867a003c06046d7944bcb5723e6049"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3c57b3150717fb1a8cbbbac6a9b7ff69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#ga3c57b3150717fb1a8cbbbac6a9b7ff69">ARM_ETH_MAC_TIMER_INC_TIME</a>   (0x03)</td></tr>
<tr class="memdesc:ga3c57b3150717fb1a8cbbbac6a9b7ff69"><td class="mdescLeft"> </td><td class="mdescRight">Increment current time. <a href="group__eth__mac__time__control.html#ga3c57b3150717fb1a8cbbbac6a9b7ff69">More...</a><br/></td></tr>
<tr class="separator:ga3c57b3150717fb1a8cbbbac6a9b7ff69"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaca9f1c4259d0342e9717a362de1ccf41"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#gaca9f1c4259d0342e9717a362de1ccf41">ARM_ETH_MAC_TIMER_DEC_TIME</a>   (0x04)</td></tr>
<tr class="memdesc:gaca9f1c4259d0342e9717a362de1ccf41"><td class="mdescLeft"> </td><td class="mdescRight">Decrement current time. <a href="group__eth__mac__time__control.html#gaca9f1c4259d0342e9717a362de1ccf41">More...</a><br/></td></tr>
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<tr class="memitem:ga04c2469ba027b020bc6b5baf3b51cf74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#ga04c2469ba027b020bc6b5baf3b51cf74">ARM_ETH_MAC_TIMER_SET_ALARM</a>   (0x05)</td></tr>
<tr class="memdesc:ga04c2469ba027b020bc6b5baf3b51cf74"><td class="mdescLeft"> </td><td class="mdescRight">Set alarm time. <a href="group__eth__mac__time__control.html#ga04c2469ba027b020bc6b5baf3b51cf74">More...</a><br/></td></tr>
<tr class="separator:ga04c2469ba027b020bc6b5baf3b51cf74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga85cb862eba0934e958a8552022588db7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__time__control.html#ga85cb862eba0934e958a8552022588db7">ARM_ETH_MAC_TIMER_ADJUST_CLOCK</a>   (0x06)</td></tr>
<tr class="memdesc:ga85cb862eba0934e958a8552022588db7"><td class="mdescLeft"> </td><td class="mdescRight">Adjust clock frequency; time->ns: correction factor * 2^31. <a href="group__eth__mac__time__control.html#ga85cb862eba0934e958a8552022588db7">More...</a><br/></td></tr>
<tr class="separator:ga85cb862eba0934e958a8552022588db7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga76943471a4a3e9e8c1ff9fe83e43bd47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ETH__MAC__events.html#ga76943471a4a3e9e8c1ff9fe83e43bd47">ARM_ETH_MAC_EVENT_RX_FRAME</a>   (1UL << 0)</td></tr>
<tr class="memdesc:ga76943471a4a3e9e8c1ff9fe83e43bd47"><td class="mdescLeft"> </td><td class="mdescRight">Frame Received. <a href="group__ETH__MAC__events.html#ga76943471a4a3e9e8c1ff9fe83e43bd47">More...</a><br/></td></tr>
<tr class="separator:ga76943471a4a3e9e8c1ff9fe83e43bd47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0c0328ff7cf886d5fdb53bb84ec03c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ETH__MAC__events.html#ga0c0328ff7cf886d5fdb53bb84ec03c1b">ARM_ETH_MAC_EVENT_TX_FRAME</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga0c0328ff7cf886d5fdb53bb84ec03c1b"><td class="mdescLeft"> </td><td class="mdescRight">Frame Transmitted. <a href="group__ETH__MAC__events.html#ga0c0328ff7cf886d5fdb53bb84ec03c1b">More...</a><br/></td></tr>
<tr class="separator:ga0c0328ff7cf886d5fdb53bb84ec03c1b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1f3bdb219afa8f2a121b58cc84f5761c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ETH__MAC__events.html#ga1f3bdb219afa8f2a121b58cc84f5761c">ARM_ETH_MAC_EVENT_WAKEUP</a>   (1UL << 2)</td></tr>
<tr class="memdesc:ga1f3bdb219afa8f2a121b58cc84f5761c"><td class="mdescLeft"> </td><td class="mdescRight">Wake-up (on Magic Packet) <a href="group__ETH__MAC__events.html#ga1f3bdb219afa8f2a121b58cc84f5761c">More...</a><br/></td></tr>
<tr class="separator:ga1f3bdb219afa8f2a121b58cc84f5761c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4afc71ecac964f195e27be4acdbe7c61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ETH__MAC__events.html#ga4afc71ecac964f195e27be4acdbe7c61">ARM_ETH_MAC_EVENT_TIMER_ALARM</a>   (1UL << 3)</td></tr>
<tr class="memdesc:ga4afc71ecac964f195e27be4acdbe7c61"><td class="mdescLeft"> </td><td class="mdescRight">Timer Alarm. <a href="group__ETH__MAC__events.html#ga4afc71ecac964f195e27be4acdbe7c61">More...</a><br/></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:gadfc95cb09c541a29a72da86963668726"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__mac__interface__gr.html#gadfc95cb09c541a29a72da86963668726">ARM_ETH_MAC_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:gadfc95cb09c541a29a72da86963668726"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__eth__mac__interface__gr.html#gae0697be4c4229601f3bfc17e2978ada6">ARM_ETH_MAC_SignalEvent</a> : Signal Ethernet Event. <a href="group__eth__mac__interface__gr.html#gadfc95cb09c541a29a72da86963668726">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a89ade7fd7f91b1b6e21883a8f823a8cc"></a>
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<td class="memname">#define ARM_ETH_MAC_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,1) /* API version */</td>
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<td class="memname">#define _ARM_Driver_ETH_MAC_</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">n</td><td>)</td>
<td>   Driver_ETH_MAC##n</td>
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<td class="memname">#define ARM_Driver_ETH_MAC_</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">n</td><td>)</td>
<td>   <a class="el" href="Driver__ETH__MAC_8h.html#ade64adbfd1c8076b7acf0b3994fb4df2">_ARM_Driver_ETH_MAC_</a>(n)</td>
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<td class="memname">#define ARM_ETH_MAC_SPEED_Pos   0</td>
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<td class="memname">#define ARM_ETH_MAC_SPEED_Msk   (3UL << ARM_ETH_MAC_SPEED_Pos)</td>
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<td class="memname">#define ARM_ETH_MAC_DUPLEX_Pos   2</td>
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<td class="memname">#define ARM_ETH_MAC_DUPLEX_Msk   (1UL << ARM_ETH_MAC_DUPLEX_Pos)</td>
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Functions</h2></td></tr>
<tr class="memitem:ga6850d33d699d9deee4e983a2c99e9734"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga6850d33d699d9deee4e983a2c99e9734">ARM_ETH_PHY_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga6850d33d699d9deee4e983a2c99e9734"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__eth__phy__interface__gr.html#ga6850d33d699d9deee4e983a2c99e9734">More...</a><br/></td></tr>
<tr class="separator:ga6850d33d699d9deee4e983a2c99e9734"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacf2332a7fa2d84694b8e5f0838135589"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#gacf2332a7fa2d84694b8e5f0838135589">ARM_ETH_PHY_Initialize</a> (<a class="el" href="group__eth__phy__interface__gr.html#ga987d5dd36f179192721c03df37d93e87">ARM_ETH_PHY_Read_t</a> fn_read, <a class="el" href="group__eth__phy__interface__gr.html#gaf690fde16281b25f2ffa07f9c4e8e240">ARM_ETH_PHY_Write_t</a> fn_write)</td></tr>
<tr class="memdesc:gacf2332a7fa2d84694b8e5f0838135589"><td class="mdescLeft"> </td><td class="mdescRight">Initialize Ethernet PHY Device. <a href="group__eth__phy__interface__gr.html#gacf2332a7fa2d84694b8e5f0838135589">More...</a><br/></td></tr>
<tr class="separator:gacf2332a7fa2d84694b8e5f0838135589"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga26ea7e1e9825b959284241ebff6eea3f"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga26ea7e1e9825b959284241ebff6eea3f">ARM_ETH_PHY_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:ga26ea7e1e9825b959284241ebff6eea3f"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize Ethernet PHY Device. <a href="group__eth__phy__interface__gr.html#ga26ea7e1e9825b959284241ebff6eea3f">More...</a><br/></td></tr>
<tr class="separator:ga26ea7e1e9825b959284241ebff6eea3f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba0f92561754dad8f8f03feb1cf2855e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#gaba0f92561754dad8f8f03feb1cf2855e">ARM_ETH_PHY_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:gaba0f92561754dad8f8f03feb1cf2855e"><td class="mdescLeft"> </td><td class="mdescRight">Control Ethernet PHY Device Power. <a href="group__eth__phy__interface__gr.html#gaba0f92561754dad8f8f03feb1cf2855e">More...</a><br/></td></tr>
<tr class="separator:gaba0f92561754dad8f8f03feb1cf2855e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaedd8b5650a1259d572a1f303d3e2c01c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#gaedd8b5650a1259d572a1f303d3e2c01c">ARM_ETH_PHY_SetInterface</a> (uint32_t interface)</td></tr>
<tr class="memdesc:gaedd8b5650a1259d572a1f303d3e2c01c"><td class="mdescLeft"> </td><td class="mdescRight">Set Ethernet Media Interface. <a href="group__eth__phy__interface__gr.html#gaedd8b5650a1259d572a1f303d3e2c01c">More...</a><br/></td></tr>
<tr class="separator:gaedd8b5650a1259d572a1f303d3e2c01c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9aa688c951f01ed9ca7c88cf51be8a09"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga9aa688c951f01ed9ca7c88cf51be8a09">ARM_ETH_PHY_SetMode</a> (uint32_t mode)</td></tr>
<tr class="memdesc:ga9aa688c951f01ed9ca7c88cf51be8a09"><td class="mdescLeft"> </td><td class="mdescRight">Set Ethernet PHY Device Operation mode. <a href="group__eth__phy__interface__gr.html#ga9aa688c951f01ed9ca7c88cf51be8a09">More...</a><br/></td></tr>
<tr class="separator:ga9aa688c951f01ed9ca7c88cf51be8a09"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4085cd24ebe33b78d51a3c003da4a5ba"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__eth__interface__gr.html#gacf7db5320eb841b462a4af3c56cc9291">ARM_ETH_LINK_STATE</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga4085cd24ebe33b78d51a3c003da4a5ba">ARM_ETH_PHY_GetLinkState</a> (void)</td></tr>
<tr class="memdesc:ga4085cd24ebe33b78d51a3c003da4a5ba"><td class="mdescLeft"> </td><td class="mdescRight">Get Ethernet PHY Device Link state. <a href="group__eth__phy__interface__gr.html#ga4085cd24ebe33b78d51a3c003da4a5ba">More...</a><br/></td></tr>
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<tr class="memitem:ga8c79dcd7a12656403f3befab3c8605a2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__eth__interface__gr.html#structARM__ETH__LINK__INFO">ARM_ETH_LINK_INFO</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga8c79dcd7a12656403f3befab3c8605a2">ARM_ETH_PHY_GetLinkInfo</a> (void)</td></tr>
<tr class="memdesc:ga8c79dcd7a12656403f3befab3c8605a2"><td class="mdescLeft"> </td><td class="mdescRight">Get Ethernet PHY Device Link information. <a href="group__eth__phy__interface__gr.html#ga8c79dcd7a12656403f3befab3c8605a2">More...</a><br/></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__DRIVER__ETH__PHY"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#structARM__DRIVER__ETH__PHY">ARM_DRIVER_ETH_PHY</a></td></tr>
<tr class="memdesc:structARM__DRIVER__ETH__PHY"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the Ethernet PHY Driver. <a href="group__eth__phy__interface__gr.html#structARM__DRIVER__ETH__PHY">More...</a><br/></td></tr>
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<tr class="memitem:abb996b4afe22e0600aff5623076d0505"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#abb996b4afe22e0600aff5623076d0505">ARM_ETH_PHY_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,1) /* API version */</td></tr>
<tr class="separator:abb996b4afe22e0600aff5623076d0505"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a261d0c3527c5880cbce44c92c5779a95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#a261d0c3527c5880cbce44c92c5779a95">_ARM_Driver_ETH_PHY_</a>(n)   Driver_ETH_PHY##n</td></tr>
<tr class="separator:a261d0c3527c5880cbce44c92c5779a95"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4d6d9b4a50776a881488782b9576af59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#a4d6d9b4a50776a881488782b9576af59">ARM_Driver_ETH_PHY_</a>(n)   <a class="el" href="Driver__ETH__PHY_8h.html#a261d0c3527c5880cbce44c92c5779a95">_ARM_Driver_ETH_PHY_</a>(n)</td></tr>
<tr class="separator:a4d6d9b4a50776a881488782b9576af59"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a13700fab82aa60a3357614faa0619e97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#a13700fab82aa60a3357614faa0619e97">ARM_ETH_PHY_SPEED_Pos</a>   0</td></tr>
<tr class="separator:a13700fab82aa60a3357614faa0619e97"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8802cb0c4caed22c70d92f656e0811f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#a8802cb0c4caed22c70d92f656e0811f5">ARM_ETH_PHY_SPEED_Msk</a>   (3UL << ARM_ETH_PHY_SPEED_Pos)</td></tr>
<tr class="separator:a8802cb0c4caed22c70d92f656e0811f5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc7acc4ebe828c3d0825400e14ad20f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#gabc7acc4ebe828c3d0825400e14ad20f0">ARM_ETH_PHY_SPEED_10M</a>   (<a class="el" href="Driver__ETH_8h.html#a1f834c4c785d7f69b1eaca011ee298ec">ARM_ETH_SPEED_10M</a> << <a class="el" href="Driver__ETH__PHY_8h.html#a13700fab82aa60a3357614faa0619e97">ARM_ETH_PHY_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:gabc7acc4ebe828c3d0825400e14ad20f0"><td class="mdescLeft"> </td><td class="mdescRight">10 Mbps link speed <a href="group__eth__phy__mode__ctrls.html#gabc7acc4ebe828c3d0825400e14ad20f0">More...</a><br/></td></tr>
<tr class="separator:gabc7acc4ebe828c3d0825400e14ad20f0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad1e8b2c8c210fa36949db9a34a993657"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#gad1e8b2c8c210fa36949db9a34a993657">ARM_ETH_PHY_SPEED_100M</a>   (<a class="el" href="Driver__ETH_8h.html#a3bddfc4cf5645f8568d9cb6621fd606a">ARM_ETH_SPEED_100M</a> << <a class="el" href="Driver__ETH__PHY_8h.html#a13700fab82aa60a3357614faa0619e97">ARM_ETH_PHY_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:gad1e8b2c8c210fa36949db9a34a993657"><td class="mdescLeft"> </td><td class="mdescRight">100 Mbps link speed <a href="group__eth__phy__mode__ctrls.html#gad1e8b2c8c210fa36949db9a34a993657">More...</a><br/></td></tr>
<tr class="separator:gad1e8b2c8c210fa36949db9a34a993657"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga046605398ceae99a176e6f82432ae710"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#ga046605398ceae99a176e6f82432ae710">ARM_ETH_PHY_SPEED_1G</a>   (<a class="el" href="Driver__ETH_8h.html#a218f470079b7c04de6776d467a53772a">ARM_ETH_SPEED_1G</a> << <a class="el" href="Driver__ETH__PHY_8h.html#a13700fab82aa60a3357614faa0619e97">ARM_ETH_PHY_SPEED_Pos</a>)</td></tr>
<tr class="memdesc:ga046605398ceae99a176e6f82432ae710"><td class="mdescLeft"> </td><td class="mdescRight">1 Gpbs link speed <a href="group__eth__phy__mode__ctrls.html#ga046605398ceae99a176e6f82432ae710">More...</a><br/></td></tr>
<tr class="separator:ga046605398ceae99a176e6f82432ae710"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aebafadc356d8e58407db156a5dac743f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#aebafadc356d8e58407db156a5dac743f">ARM_ETH_PHY_DUPLEX_Pos</a>   2</td></tr>
<tr class="separator:aebafadc356d8e58407db156a5dac743f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a832fd4424dc9aaafac8034457396c259"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__ETH__PHY_8h.html#a832fd4424dc9aaafac8034457396c259">ARM_ETH_PHY_DUPLEX_Msk</a>   (1UL << ARM_ETH_PHY_DUPLEX_Pos)</td></tr>
<tr class="separator:a832fd4424dc9aaafac8034457396c259"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gace797b3cd143be22f47c3ef61b20e14d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#gace797b3cd143be22f47c3ef61b20e14d">ARM_ETH_PHY_DUPLEX_HALF</a>   (<a class="el" href="Driver__ETH_8h.html#acb15afc2bfe61c56049b7279d6eae8fe">ARM_ETH_DUPLEX_HALF</a> << <a class="el" href="Driver__ETH__PHY_8h.html#aebafadc356d8e58407db156a5dac743f">ARM_ETH_PHY_DUPLEX_Pos</a>)</td></tr>
<tr class="memdesc:gace797b3cd143be22f47c3ef61b20e14d"><td class="mdescLeft"> </td><td class="mdescRight">Half duplex link. <a href="group__eth__phy__mode__ctrls.html#gace797b3cd143be22f47c3ef61b20e14d">More...</a><br/></td></tr>
<tr class="separator:gace797b3cd143be22f47c3ef61b20e14d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5d06a94867c89cd311b6e279669321e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#ga5d06a94867c89cd311b6e279669321e3">ARM_ETH_PHY_DUPLEX_FULL</a>   (<a class="el" href="Driver__ETH_8h.html#a7848c83cd1fd6b2645c17919c2990354">ARM_ETH_DUPLEX_FULL</a> << <a class="el" href="Driver__ETH__PHY_8h.html#aebafadc356d8e58407db156a5dac743f">ARM_ETH_PHY_DUPLEX_Pos</a>)</td></tr>
<tr class="memdesc:ga5d06a94867c89cd311b6e279669321e3"><td class="mdescLeft"> </td><td class="mdescRight">Full duplex link. <a href="group__eth__phy__mode__ctrls.html#ga5d06a94867c89cd311b6e279669321e3">More...</a><br/></td></tr>
<tr class="separator:ga5d06a94867c89cd311b6e279669321e3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6a8c54f8fed3e5f68bd04eb715d10ab9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#ga6a8c54f8fed3e5f68bd04eb715d10ab9">ARM_ETH_PHY_AUTO_NEGOTIATE</a>   (1UL << 3)</td></tr>
<tr class="memdesc:ga6a8c54f8fed3e5f68bd04eb715d10ab9"><td class="mdescLeft"> </td><td class="mdescRight">Auto Negotiation mode. <a href="group__eth__phy__mode__ctrls.html#ga6a8c54f8fed3e5f68bd04eb715d10ab9">More...</a><br/></td></tr>
<tr class="separator:ga6a8c54f8fed3e5f68bd04eb715d10ab9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5f7e46cda8ab3c774fe7ce0a8a1ba3ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#ga5f7e46cda8ab3c774fe7ce0a8a1ba3ec">ARM_ETH_PHY_LOOPBACK</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga5f7e46cda8ab3c774fe7ce0a8a1ba3ec"><td class="mdescLeft"> </td><td class="mdescRight">Loop-back test mode. <a href="group__eth__phy__mode__ctrls.html#ga5f7e46cda8ab3c774fe7ce0a8a1ba3ec">More...</a><br/></td></tr>
<tr class="separator:ga5f7e46cda8ab3c774fe7ce0a8a1ba3ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8d68719e07c7af449b57c5df802376c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__mode__ctrls.html#ga8d68719e07c7af449b57c5df802376c8">ARM_ETH_PHY_ISOLATE</a>   (1UL << 5)</td></tr>
<tr class="memdesc:ga8d68719e07c7af449b57c5df802376c8"><td class="mdescLeft"> </td><td class="mdescRight">Isolate PHY from MII/RMII interface. <a href="group__eth__phy__mode__ctrls.html#ga8d68719e07c7af449b57c5df802376c8">More...</a><br/></td></tr>
<tr class="separator:ga8d68719e07c7af449b57c5df802376c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga987d5dd36f179192721c03df37d93e87"><td class="memItemLeft" align="right" valign="top">typedef int32_t(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#ga987d5dd36f179192721c03df37d93e87">ARM_ETH_PHY_Read_t</a> )(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)</td></tr>
<tr class="memdesc:ga987d5dd36f179192721c03df37d93e87"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__eth__mac__interface__gr.html#gaded29ad58366e9222487db9944373c29">ARM_ETH_MAC_PHY_Read</a> : Read Ethernet PHY Register. <a href="group__eth__phy__interface__gr.html#ga987d5dd36f179192721c03df37d93e87">More...</a><br/></td></tr>
<tr class="separator:ga987d5dd36f179192721c03df37d93e87"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf690fde16281b25f2ffa07f9c4e8e240"><td class="memItemLeft" align="right" valign="top">typedef int32_t(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__eth__phy__interface__gr.html#gaf690fde16281b25f2ffa07f9c4e8e240">ARM_ETH_PHY_Write_t</a> )(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)</td></tr>
<tr class="memdesc:gaf690fde16281b25f2ffa07f9c4e8e240"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__eth__mac__interface__gr.html#ga79dd38672749aeebd28f39d9b4f813ce">ARM_ETH_MAC_PHY_Write</a> : Write Ethernet PHY Register. <a href="group__eth__phy__interface__gr.html#gaf690fde16281b25f2ffa07f9c4e8e240">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_ETH_PHY_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,1) /* API version */</td>
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<td class="memname">#define _ARM_Driver_ETH_PHY_</td>
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<td>   Driver_ETH_PHY##n</td>
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<td class="memname">#define ARM_Driver_ETH_PHY_</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">n</td><td>)</td>
<td>   <a class="el" href="Driver__ETH__PHY_8h.html#a261d0c3527c5880cbce44c92c5779a95">_ARM_Driver_ETH_PHY_</a>(n)</td>
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<td class="memname">#define ARM_ETH_PHY_SPEED_Pos   0</td>
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<td class="memname">#define ARM_ETH_PHY_SPEED_Msk   (3UL << ARM_ETH_PHY_SPEED_Pos)</td>
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<td class="memname">#define ARM_ETH_PHY_DUPLEX_Pos   2</td>
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Functions</h2></td></tr>
<tr class="memitem:ga1cfe24b2ffa571ee50ae544bd922b604"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga1cfe24b2ffa571ee50ae544bd922b604">ARM_Flash_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga1cfe24b2ffa571ee50ae544bd922b604"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__flash__interface__gr.html#ga1cfe24b2ffa571ee50ae544bd922b604">More...</a><br/></td></tr>
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<tr class="memitem:ga27c23c998032cd47cb47293c0185ee5d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__flash__interface__gr.html#structARM__FLASH__CAPABILITIES">ARM_FLASH_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga27c23c998032cd47cb47293c0185ee5d">ARM_Flash_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga27c23c998032cd47cb47293c0185ee5d"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__flash__interface__gr.html#ga27c23c998032cd47cb47293c0185ee5d">More...</a><br/></td></tr>
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<tr class="memitem:gaa5b4bbe529d620d4ad4825588a4c4cf0"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#gaa5b4bbe529d620d4ad4825588a4c4cf0">ARM_Flash_Initialize</a> (<a class="el" href="group__flash__interface__gr.html#gabeb4ad43b1e6fa4ed956cd5c9371d327">ARM_Flash_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:gaa5b4bbe529d620d4ad4825588a4c4cf0"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the Flash Interface. <a href="group__flash__interface__gr.html#gaa5b4bbe529d620d4ad4825588a4c4cf0">More...</a><br/></td></tr>
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<tr class="memitem:gae23af293e9f8a67cdb19c7d0d562d415"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#gae23af293e9f8a67cdb19c7d0d562d415">ARM_Flash_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gae23af293e9f8a67cdb19c7d0d562d415"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize the Flash Interface. <a href="group__flash__interface__gr.html#gae23af293e9f8a67cdb19c7d0d562d415">More...</a><br/></td></tr>
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<tr class="memitem:gaa8baa4618ea33568f8b3752afb2ab5a2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#gaa8baa4618ea33568f8b3752afb2ab5a2">ARM_Flash_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:gaa8baa4618ea33568f8b3752afb2ab5a2"><td class="mdescLeft"> </td><td class="mdescRight">Control the Flash interface power. <a href="group__flash__interface__gr.html#gaa8baa4618ea33568f8b3752afb2ab5a2">More...</a><br/></td></tr>
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<tr class="memitem:ga223138342383219896ed7e255faeb99a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga223138342383219896ed7e255faeb99a">ARM_Flash_ReadData</a> (uint32_t addr, void *data, uint32_t cnt)</td></tr>
<tr class="memdesc:ga223138342383219896ed7e255faeb99a"><td class="mdescLeft"> </td><td class="mdescRight">Read data from Flash. <a href="group__flash__interface__gr.html#ga223138342383219896ed7e255faeb99a">More...</a><br/></td></tr>
<tr class="separator:ga223138342383219896ed7e255faeb99a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga947f24ea4042093fdb5605a68ae74f9d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga947f24ea4042093fdb5605a68ae74f9d">ARM_Flash_ProgramData</a> (uint32_t addr, const void *data, uint32_t cnt)</td></tr>
<tr class="memdesc:ga947f24ea4042093fdb5605a68ae74f9d"><td class="mdescLeft"> </td><td class="mdescRight">Program data to Flash. <a href="group__flash__interface__gr.html#ga947f24ea4042093fdb5605a68ae74f9d">More...</a><br/></td></tr>
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<tr class="memitem:ga0b2b4fe5a7be579cf3644995a765ea20"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga0b2b4fe5a7be579cf3644995a765ea20">ARM_Flash_EraseSector</a> (uint32_t addr)</td></tr>
<tr class="memdesc:ga0b2b4fe5a7be579cf3644995a765ea20"><td class="mdescLeft"> </td><td class="mdescRight">Erase Flash Sector. <a href="group__flash__interface__gr.html#ga0b2b4fe5a7be579cf3644995a765ea20">More...</a><br/></td></tr>
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<tr class="memitem:ga6cbaebe069d31d56c70b1f8f847e2d55"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga6cbaebe069d31d56c70b1f8f847e2d55">ARM_Flash_EraseChip</a> (void)</td></tr>
<tr class="memdesc:ga6cbaebe069d31d56c70b1f8f847e2d55"><td class="mdescLeft"> </td><td class="mdescRight">Erase complete Flash. Optional function for faster full chip erase. <a href="group__flash__interface__gr.html#ga6cbaebe069d31d56c70b1f8f847e2d55">More...</a><br/></td></tr>
<tr class="separator:ga6cbaebe069d31d56c70b1f8f847e2d55"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga06885c0d4587d5a23f97614a8b849ef1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__flash__interface__gr.html#structARM__FLASH__STATUS">ARM_FLASH_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga06885c0d4587d5a23f97614a8b849ef1">ARM_Flash_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga06885c0d4587d5a23f97614a8b849ef1"><td class="mdescLeft"> </td><td class="mdescRight">Get Flash status. <a href="group__flash__interface__gr.html#ga06885c0d4587d5a23f97614a8b849ef1">More...</a><br/></td></tr>
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<tr class="memitem:gac047b7509356e888502e0424a9d189ae"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__flash__interface__gr.html#structARM__FLASH__INFO">ARM_FLASH_INFO</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#gac047b7509356e888502e0424a9d189ae">ARM_Flash_GetInfo</a> (void)</td></tr>
<tr class="memdesc:gac047b7509356e888502e0424a9d189ae"><td class="mdescLeft"> </td><td class="mdescRight">Get Flash information. <a href="group__flash__interface__gr.html#gac047b7509356e888502e0424a9d189ae">More...</a><br/></td></tr>
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<tr class="memitem:ga97b75555b5433b268add81f2e60f095a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#ga97b75555b5433b268add81f2e60f095a">ARM_Flash_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:ga97b75555b5433b268add81f2e60f095a"><td class="mdescLeft"> </td><td class="mdescRight">Signal Flash event. <a href="group__flash__interface__gr.html#ga97b75555b5433b268add81f2e60f095a">More...</a><br/></td></tr>
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<tr class="memitem:structARM__FLASH__SECTOR"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#structARM__FLASH__SECTOR">ARM_FLASH_SECTOR</a></td></tr>
<tr class="memdesc:structARM__FLASH__SECTOR"><td class="mdescLeft"> </td><td class="mdescRight">Flash Sector information. <a href="group__flash__interface__gr.html#structARM__FLASH__SECTOR">More...</a><br/></td></tr>
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<tr class="memitem:structARM__FLASH__INFO"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#structARM__FLASH__INFO">ARM_FLASH_INFO</a></td></tr>
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<tr class="memitem:structARM__DRIVER__FLASH"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#structARM__DRIVER__FLASH">ARM_DRIVER_FLASH</a></td></tr>
<tr class="memdesc:structARM__DRIVER__FLASH"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the Flash Driver. <a href="group__flash__interface__gr.html#structARM__DRIVER__FLASH">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a16e58dce04f3f65d5183c973c9189fa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__Flash_8h.html#a16e58dce04f3f65d5183c973c9189fa4">ARM_FLASH_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td></tr>
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<tr class="memitem:a0955bb54d18c78992e20395e32c537e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__Flash_8h.html#a0955bb54d18c78992e20395e32c537e6">_ARM_Driver_Flash_</a>(n)   Driver_Flash##n</td></tr>
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<tr class="memitem:afda179843b93526222e15d61f226ac8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__Flash_8h.html#afda179843b93526222e15d61f226ac8f">ARM_Driver_Flash_</a>(n)   <a class="el" href="Driver__Flash_8h.html#a0955bb54d18c78992e20395e32c537e6">_ARM_Driver_Flash_</a>(n)</td></tr>
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<tr class="memitem:aaeb2830d80f8aca0eaf72e3718537a60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__Flash_8h.html#aaeb2830d80f8aca0eaf72e3718537a60">ARM_FLASH_SECTOR_INFO</a>(addr, size)   { (addr), (addr)+(size)-1 }</td></tr>
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<tr class="memitem:gaf7a9c4ad125ee90df35907d861151e23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Flash__events.html#gaf7a9c4ad125ee90df35907d861151e23">ARM_FLASH_EVENT_READY</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gaf7a9c4ad125ee90df35907d861151e23"><td class="mdescLeft"> </td><td class="mdescRight">Flash Ready. <a href="group__Flash__events.html#gaf7a9c4ad125ee90df35907d861151e23">More...</a><br/></td></tr>
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<tr class="memitem:ga0dfea52761c0eed83e5d73e7a7f69962"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Flash__events.html#ga0dfea52761c0eed83e5d73e7a7f69962">ARM_FLASH_EVENT_ERROR</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga0dfea52761c0eed83e5d73e7a7f69962"><td class="mdescLeft"> </td><td class="mdescRight">Read/Program/Erase Error. <a href="group__Flash__events.html#ga0dfea52761c0eed83e5d73e7a7f69962">More...</a><br/></td></tr>
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<tr class="memitem:gabeb4ad43b1e6fa4ed956cd5c9371d327"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__flash__interface__gr.html#gabeb4ad43b1e6fa4ed956cd5c9371d327">ARM_Flash_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:gabeb4ad43b1e6fa4ed956cd5c9371d327"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__flash__interface__gr.html#ga97b75555b5433b268add81f2e60f095a">ARM_Flash_SignalEvent</a> : Signal Flash Event. <a href="group__flash__interface__gr.html#gabeb4ad43b1e6fa4ed956cd5c9371d327">More...</a><br/></td></tr>
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<td class="memname">#define ARM_FLASH_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td>
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<td class="memname">#define _ARM_Driver_Flash_</td>
<td>(</td>
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<td class="paramname">n</td><td>)</td>
<td>   Driver_Flash##n</td>
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<td class="memname">#define ARM_Driver_Flash_</td>
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<td class="paramname">n</td><td>)</td>
<td>   <a class="el" href="Driver__Flash_8h.html#a0955bb54d18c78992e20395e32c537e6">_ARM_Driver_Flash_</a>(n)</td>
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<td class="memname">#define ARM_FLASH_SECTOR_INFO</td>
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<td class="paramname">addr, </td>
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<td class="paramtype"> </td>
<td class="paramname">size </td>
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<td>)</td>
<td></td><td>   { (addr), (addr)+(size)-1 }</td>
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Functions</h2></td></tr>
<tr class="memitem:ga956bd87590c7fb6e23609a0abfb5412c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga956bd87590c7fb6e23609a0abfb5412c">ARM_I2C_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga956bd87590c7fb6e23609a0abfb5412c"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__i2c__interface__gr.html#ga956bd87590c7fb6e23609a0abfb5412c">More...</a><br/></td></tr>
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<tr class="memitem:gad20e6731f627aa7b9d6e99a50806122e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__i2c__interface__gr.html#structARM__I2C__CAPABILITIES">ARM_I2C_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gad20e6731f627aa7b9d6e99a50806122e">ARM_I2C_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:gad20e6731f627aa7b9d6e99a50806122e"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__i2c__interface__gr.html#gad20e6731f627aa7b9d6e99a50806122e">More...</a><br/></td></tr>
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<tr class="memitem:ga79d2f7d01b3a681d1cf0d70ac6692696"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga79d2f7d01b3a681d1cf0d70ac6692696">ARM_I2C_Initialize</a> (<a class="el" href="group__i2c__interface__gr.html#ga24277c48248a09b0dd7f12bbe22ce13c">ARM_I2C_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga79d2f7d01b3a681d1cf0d70ac6692696"><td class="mdescLeft"> </td><td class="mdescRight">Initialize I2C Interface. <a href="group__i2c__interface__gr.html#ga79d2f7d01b3a681d1cf0d70ac6692696">More...</a><br/></td></tr>
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<tr class="memitem:ga30d8bf600b6b3182a1f867407b3d6e75"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga30d8bf600b6b3182a1f867407b3d6e75">ARM_I2C_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:ga30d8bf600b6b3182a1f867407b3d6e75"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize I2C Interface. <a href="group__i2c__interface__gr.html#ga30d8bf600b6b3182a1f867407b3d6e75">More...</a><br/></td></tr>
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<tr class="memitem:ga734a69200e063fdbfb5110062afe9329"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga734a69200e063fdbfb5110062afe9329">ARM_I2C_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga734a69200e063fdbfb5110062afe9329"><td class="mdescLeft"> </td><td class="mdescRight">Control I2C Interface Power. <a href="group__i2c__interface__gr.html#ga734a69200e063fdbfb5110062afe9329">More...</a><br/></td></tr>
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<tr class="memitem:ga8bf4214580149d5a5d2360f71f0feb94"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga8bf4214580149d5a5d2360f71f0feb94">ARM_I2C_MasterTransmit</a> (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)</td></tr>
<tr class="memdesc:ga8bf4214580149d5a5d2360f71f0feb94"><td class="mdescLeft"> </td><td class="mdescRight">Start transmitting data as I2C Master. <a href="group__i2c__interface__gr.html#ga8bf4214580149d5a5d2360f71f0feb94">More...</a><br/></td></tr>
<tr class="separator:ga8bf4214580149d5a5d2360f71f0feb94"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa22504bcf88a85584dfe6e0dd270ad5"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gafa22504bcf88a85584dfe6e0dd270ad5">ARM_I2C_MasterReceive</a> (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)</td></tr>
<tr class="memdesc:gafa22504bcf88a85584dfe6e0dd270ad5"><td class="mdescLeft"> </td><td class="mdescRight">Start receiving data as I2C Master. <a href="group__i2c__interface__gr.html#gafa22504bcf88a85584dfe6e0dd270ad5">More...</a><br/></td></tr>
<tr class="separator:gafa22504bcf88a85584dfe6e0dd270ad5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafe164f30eba78f066272373b98a62cd4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gafe164f30eba78f066272373b98a62cd4">ARM_I2C_SlaveTransmit</a> (const uint8_t *data, uint32_t num)</td></tr>
<tr class="memdesc:gafe164f30eba78f066272373b98a62cd4"><td class="mdescLeft"> </td><td class="mdescRight">Start transmitting data as I2C Slave. <a href="group__i2c__interface__gr.html#gafe164f30eba78f066272373b98a62cd4">More...</a><br/></td></tr>
<tr class="separator:gafe164f30eba78f066272373b98a62cd4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae3c9abccd1d377385d3d4cfe29035164"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gae3c9abccd1d377385d3d4cfe29035164">ARM_I2C_SlaveReceive</a> (uint8_t *data, uint32_t num)</td></tr>
<tr class="memdesc:gae3c9abccd1d377385d3d4cfe29035164"><td class="mdescLeft"> </td><td class="mdescRight">Start receiving data as I2C Slave. <a href="group__i2c__interface__gr.html#gae3c9abccd1d377385d3d4cfe29035164">More...</a><br/></td></tr>
<tr class="separator:gae3c9abccd1d377385d3d4cfe29035164"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga19db20ad8d7fde84d07f6db4d75f4b7c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga19db20ad8d7fde84d07f6db4d75f4b7c">ARM_I2C_GetDataCount</a> (void)</td></tr>
<tr class="memdesc:ga19db20ad8d7fde84d07f6db4d75f4b7c"><td class="mdescLeft"> </td><td class="mdescRight">Get transferred data count. <a href="group__i2c__interface__gr.html#ga19db20ad8d7fde84d07f6db4d75f4b7c">More...</a><br/></td></tr>
<tr class="separator:ga19db20ad8d7fde84d07f6db4d75f4b7c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga828f5fa289d065675ef78a9a73d129dc"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga828f5fa289d065675ef78a9a73d129dc">ARM_I2C_Control</a> (uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:ga828f5fa289d065675ef78a9a73d129dc"><td class="mdescLeft"> </td><td class="mdescRight">Control I2C Interface. <a href="group__i2c__interface__gr.html#ga828f5fa289d065675ef78a9a73d129dc">More...</a><br/></td></tr>
<tr class="separator:ga828f5fa289d065675ef78a9a73d129dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba4e0f3eb4018e7dafd51b675c465f3e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__i2c__interface__gr.html#structARM__I2C__STATUS">ARM_I2C_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gaba4e0f3eb4018e7dafd51b675c465f3e">ARM_I2C_GetStatus</a> (void)</td></tr>
<tr class="memdesc:gaba4e0f3eb4018e7dafd51b675c465f3e"><td class="mdescLeft"> </td><td class="mdescRight">Get I2C status. <a href="group__i2c__interface__gr.html#gaba4e0f3eb4018e7dafd51b675c465f3e">More...</a><br/></td></tr>
<tr class="separator:gaba4e0f3eb4018e7dafd51b675c465f3e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad4f93d2895794b416dc8d8e9de91c05e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#gad4f93d2895794b416dc8d8e9de91c05e">ARM_I2C_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:gad4f93d2895794b416dc8d8e9de91c05e"><td class="mdescLeft"> </td><td class="mdescRight">Signal I2C Events. <a href="group__i2c__interface__gr.html#gad4f93d2895794b416dc8d8e9de91c05e">More...</a><br/></td></tr>
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<div class="title">Driver_I2C.h File Reference</div> </div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__I2C__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#structARM__I2C__STATUS">ARM_I2C_STATUS</a></td></tr>
<tr class="memdesc:structARM__I2C__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">I2C Status. <a href="group__i2c__interface__gr.html#structARM__I2C__STATUS">More...</a><br/></td></tr>
<tr class="separator:structARM__I2C__STATUS"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:structARM__I2C__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#structARM__I2C__CAPABILITIES">ARM_I2C_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__I2C__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">I2C Driver Capabilities. <a href="group__i2c__interface__gr.html#structARM__I2C__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__I2C"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#structARM__DRIVER__I2C">ARM_DRIVER_I2C</a></td></tr>
<tr class="memdesc:structARM__DRIVER__I2C"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the I2C Driver. <a href="group__i2c__interface__gr.html#structARM__DRIVER__I2C">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a1d02c71e603ea569af1755251b1d179f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__I2C_8h.html#a1d02c71e603ea569af1755251b1d179f">ARM_I2C_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td></tr>
<tr class="separator:a1d02c71e603ea569af1755251b1d179f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga69d130b9f8aa34d6df5334ab67c74307"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__control__codes.html#ga69d130b9f8aa34d6df5334ab67c74307">ARM_I2C_OWN_ADDRESS</a>   (0x01)</td></tr>
<tr class="memdesc:ga69d130b9f8aa34d6df5334ab67c74307"><td class="mdescLeft"> </td><td class="mdescRight">Set Own Slave Address; arg = address. <a href="group__i2c__control__codes.html#ga69d130b9f8aa34d6df5334ab67c74307">More...</a><br/></td></tr>
<tr class="separator:ga69d130b9f8aa34d6df5334ab67c74307"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga35733133237d65146abd9449f5353a7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__control__codes.html#ga35733133237d65146abd9449f5353a7f">ARM_I2C_BUS_SPEED</a>   (0x02)</td></tr>
<tr class="memdesc:ga35733133237d65146abd9449f5353a7f"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed; arg = speed. <a href="group__i2c__control__codes.html#ga35733133237d65146abd9449f5353a7f">More...</a><br/></td></tr>
<tr class="separator:ga35733133237d65146abd9449f5353a7f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadacf04578770faca4b3eaae34b2c5f03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__control__codes.html#gadacf04578770faca4b3eaae34b2c5f03">ARM_I2C_BUS_CLEAR</a>   (0x03)</td></tr>
<tr class="memdesc:gadacf04578770faca4b3eaae34b2c5f03"><td class="mdescLeft"> </td><td class="mdescRight">Execute Bus clear: send nine clock pulses. <a href="group__i2c__control__codes.html#gadacf04578770faca4b3eaae34b2c5f03">More...</a><br/></td></tr>
<tr class="separator:gadacf04578770faca4b3eaae34b2c5f03"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga661e91aaa642d10ba80e3cc72f263040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__control__codes.html#ga661e91aaa642d10ba80e3cc72f263040">ARM_I2C_ABORT_TRANSFER</a>   (0x04)</td></tr>
<tr class="memdesc:ga661e91aaa642d10ba80e3cc72f263040"><td class="mdescLeft"> </td><td class="mdescRight">Abort Master/Slave Transmit/Receive. <a href="group__i2c__control__codes.html#ga661e91aaa642d10ba80e3cc72f263040">More...</a><br/></td></tr>
<tr class="separator:ga661e91aaa642d10ba80e3cc72f263040"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0aaa6398280fdd7ad651d7d6d44c863f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__bus__speed__ctrls.html#ga0aaa6398280fdd7ad651d7d6d44c863f">ARM_I2C_BUS_SPEED_STANDARD</a>   (0x01)</td></tr>
<tr class="memdesc:ga0aaa6398280fdd7ad651d7d6d44c863f"><td class="mdescLeft"> </td><td class="mdescRight">Standard Speed (100kHz) <a href="group__i2c__bus__speed__ctrls.html#ga0aaa6398280fdd7ad651d7d6d44c863f">More...</a><br/></td></tr>
<tr class="separator:ga0aaa6398280fdd7ad651d7d6d44c863f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga39f49ef4cd1100a8d9dc9003329e5ecd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__bus__speed__ctrls.html#ga39f49ef4cd1100a8d9dc9003329e5ecd">ARM_I2C_BUS_SPEED_FAST</a>   (0x02)</td></tr>
<tr class="memdesc:ga39f49ef4cd1100a8d9dc9003329e5ecd"><td class="mdescLeft"> </td><td class="mdescRight">Fast Speed (400kHz) <a href="group__i2c__bus__speed__ctrls.html#ga39f49ef4cd1100a8d9dc9003329e5ecd">More...</a><br/></td></tr>
<tr class="separator:ga39f49ef4cd1100a8d9dc9003329e5ecd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2615262062e0327ab478ec85675ca649"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__bus__speed__ctrls.html#ga2615262062e0327ab478ec85675ca649">ARM_I2C_BUS_SPEED_FAST_PLUS</a>   (0x03)</td></tr>
<tr class="memdesc:ga2615262062e0327ab478ec85675ca649"><td class="mdescLeft"> </td><td class="mdescRight">Fast+ Speed ( 1MHz) <a href="group__i2c__bus__speed__ctrls.html#ga2615262062e0327ab478ec85675ca649">More...</a><br/></td></tr>
<tr class="separator:ga2615262062e0327ab478ec85675ca649"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga10aae5a8c7fcc90e514c5fb7393056ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__bus__speed__ctrls.html#ga10aae5a8c7fcc90e514c5fb7393056ec">ARM_I2C_BUS_SPEED_HIGH</a>   (0x04)</td></tr>
<tr class="memdesc:ga10aae5a8c7fcc90e514c5fb7393056ec"><td class="mdescLeft"> </td><td class="mdescRight">High Speed (3.4MHz) <a href="group__i2c__bus__speed__ctrls.html#ga10aae5a8c7fcc90e514c5fb7393056ec">More...</a><br/></td></tr>
<tr class="separator:ga10aae5a8c7fcc90e514c5fb7393056ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga16be1861b90774bf062feab2dbb829a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__address__flags.html#ga16be1861b90774bf062feab2dbb829a4">ARM_I2C_ADDRESS_10BIT</a>   (0x0400)</td></tr>
<tr class="memdesc:ga16be1861b90774bf062feab2dbb829a4"><td class="mdescLeft"> </td><td class="mdescRight">10-bit address flag <a href="group__i2c__address__flags.html#ga16be1861b90774bf062feab2dbb829a4">More...</a><br/></td></tr>
<tr class="separator:ga16be1861b90774bf062feab2dbb829a4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga337f4f1aa082e9b593b2dcd43c50134e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__address__flags.html#ga337f4f1aa082e9b593b2dcd43c50134e">ARM_I2C_ADDRESS_GC</a>   (0x8000)</td></tr>
<tr class="memdesc:ga337f4f1aa082e9b593b2dcd43c50134e"><td class="mdescLeft"> </td><td class="mdescRight">General Call flag. <a href="group__i2c__address__flags.html#ga337f4f1aa082e9b593b2dcd43c50134e">More...</a><br/></td></tr>
<tr class="separator:ga337f4f1aa082e9b593b2dcd43c50134e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5992dc0f6e839c4d066cfa83d535f30d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#ga5992dc0f6e839c4d066cfa83d535f30d">ARM_I2C_EVENT_TRANSFER_DONE</a>   (1UL << 0)</td></tr>
<tr class="memdesc:ga5992dc0f6e839c4d066cfa83d535f30d"><td class="mdescLeft"> </td><td class="mdescRight">Master/Slave Transmit/Receive finished. <a href="group__I2C__events.html#ga5992dc0f6e839c4d066cfa83d535f30d">More...</a><br/></td></tr>
<tr class="separator:ga5992dc0f6e839c4d066cfa83d535f30d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafac3989c7b57727e1bed4ee9f2496ac9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#gafac3989c7b57727e1bed4ee9f2496ac9">ARM_I2C_EVENT_TRANSFER_INCOMPLETE</a>   (1UL << 1)</td></tr>
<tr class="memdesc:gafac3989c7b57727e1bed4ee9f2496ac9"><td class="mdescLeft"> </td><td class="mdescRight">Master/Slave Transmit/Receive incomplete transfer. <a href="group__I2C__events.html#gafac3989c7b57727e1bed4ee9f2496ac9">More...</a><br/></td></tr>
<tr class="separator:gafac3989c7b57727e1bed4ee9f2496ac9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacfbbec9af083d35e8ea87ad16e9c6ec2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#gacfbbec9af083d35e8ea87ad16e9c6ec2">ARM_I2C_EVENT_SLAVE_TRANSMIT</a>   (1UL << 2)</td></tr>
<tr class="memdesc:gacfbbec9af083d35e8ea87ad16e9c6ec2"><td class="mdescLeft"> </td><td class="mdescRight">Addressed as Slave Transmitter but transmit operation is not set. <a href="group__I2C__events.html#gacfbbec9af083d35e8ea87ad16e9c6ec2">More...</a><br/></td></tr>
<tr class="separator:gacfbbec9af083d35e8ea87ad16e9c6ec2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd875b57ce39dadd849c53b885ad6661"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#gabd875b57ce39dadd849c53b885ad6661">ARM_I2C_EVENT_SLAVE_RECEIVE</a>   (1UL << 3)</td></tr>
<tr class="memdesc:gabd875b57ce39dadd849c53b885ad6661"><td class="mdescLeft"> </td><td class="mdescRight">Addressed as Slave Receiver but receive operation is not set. <a href="group__I2C__events.html#gabd875b57ce39dadd849c53b885ad6661">More...</a><br/></td></tr>
<tr class="separator:gabd875b57ce39dadd849c53b885ad6661"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga98b815769634d9578526b43589caa017"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#ga98b815769634d9578526b43589caa017">ARM_I2C_EVENT_ADDRESS_NACK</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga98b815769634d9578526b43589caa017"><td class="mdescLeft"> </td><td class="mdescRight">Address not acknowledged from Slave. <a href="group__I2C__events.html#ga98b815769634d9578526b43589caa017">More...</a><br/></td></tr>
<tr class="separator:ga98b815769634d9578526b43589caa017"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3ab54410b6410ed3a58762ff0c0d68b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#ga3ab54410b6410ed3a58762ff0c0d68b9">ARM_I2C_EVENT_GENERAL_CALL</a>   (1UL << 5)</td></tr>
<tr class="memdesc:ga3ab54410b6410ed3a58762ff0c0d68b9"><td class="mdescLeft"> </td><td class="mdescRight">Slave addressed with general call address. <a href="group__I2C__events.html#ga3ab54410b6410ed3a58762ff0c0d68b9">More...</a><br/></td></tr>
<tr class="separator:ga3ab54410b6410ed3a58762ff0c0d68b9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac9000f44a578e2117d64dbc2093cec6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#gac9000f44a578e2117d64dbc2093cec6d">ARM_I2C_EVENT_ARBITRATION_LOST</a>   (1UL << 6)</td></tr>
<tr class="memdesc:gac9000f44a578e2117d64dbc2093cec6d"><td class="mdescLeft"> </td><td class="mdescRight">Master lost arbitration. <a href="group__I2C__events.html#gac9000f44a578e2117d64dbc2093cec6d">More...</a><br/></td></tr>
<tr class="separator:gac9000f44a578e2117d64dbc2093cec6d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeef542840355131c18b53fd9ed1904a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#gaeef542840355131c18b53fd9ed1904a8">ARM_I2C_EVENT_BUS_ERROR</a>   (1UL << 7)</td></tr>
<tr class="memdesc:gaeef542840355131c18b53fd9ed1904a8"><td class="mdescLeft"> </td><td class="mdescRight">Bus error detected (START/STOP at illegal position) <a href="group__I2C__events.html#gaeef542840355131c18b53fd9ed1904a8">More...</a><br/></td></tr>
<tr class="separator:gaeef542840355131c18b53fd9ed1904a8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga81ca21fad73dac1ffaff58921f848ea9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__I2C__events.html#ga81ca21fad73dac1ffaff58921f848ea9">ARM_I2C_EVENT_BUS_CLEAR</a>   (1UL << 8)</td></tr>
<tr class="memdesc:ga81ca21fad73dac1ffaff58921f848ea9"><td class="mdescLeft"> </td><td class="mdescRight">Bus clear finished. <a href="group__I2C__events.html#ga81ca21fad73dac1ffaff58921f848ea9">More...</a><br/></td></tr>
<tr class="separator:ga81ca21fad73dac1ffaff58921f848ea9"><td class="memSeparator" colspan="2"> </td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:ga24277c48248a09b0dd7f12bbe22ce13c"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2c__interface__gr.html#ga24277c48248a09b0dd7f12bbe22ce13c">ARM_I2C_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:ga24277c48248a09b0dd7f12bbe22ce13c"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__i2c__interface__gr.html#gad4f93d2895794b416dc8d8e9de91c05e">ARM_I2C_SignalEvent</a> : Signal I2C Event. <a href="group__i2c__interface__gr.html#ga24277c48248a09b0dd7f12bbe22ce13c">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_I2C_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td>
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Functions</h2></td></tr>
<tr class="memitem:ga3418183015dbf3025b94eebaedb00ab1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga3418183015dbf3025b94eebaedb00ab1">ARM_MCI_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga3418183015dbf3025b94eebaedb00ab1"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__mci__interface__gr.html#ga3418183015dbf3025b94eebaedb00ab1">More...</a><br/></td></tr>
<tr class="separator:ga3418183015dbf3025b94eebaedb00ab1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7e5a78b6e6409189833a0b72a0a3c48a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__CAPABILITIES">ARM_MCI_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga7e5a78b6e6409189833a0b72a0a3c48a">ARM_MCI_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga7e5a78b6e6409189833a0b72a0a3c48a"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__mci__interface__gr.html#ga7e5a78b6e6409189833a0b72a0a3c48a">More...</a><br/></td></tr>
<tr class="separator:ga7e5a78b6e6409189833a0b72a0a3c48a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6f34d4ab362e596ddaf23aac093268cf"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga6f34d4ab362e596ddaf23aac093268cf">ARM_MCI_Initialize</a> (<a class="el" href="group__mci__interface__gr.html#ga0d14651f6788c1ffd81544602565faf1">ARM_MCI_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga6f34d4ab362e596ddaf23aac093268cf"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the Memory Card Interface. <a href="group__mci__interface__gr.html#ga6f34d4ab362e596ddaf23aac093268cf">More...</a><br/></td></tr>
<tr class="separator:ga6f34d4ab362e596ddaf23aac093268cf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaef8183e77797e74997551d03646d42c2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#gaef8183e77797e74997551d03646d42c2">ARM_MCI_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gaef8183e77797e74997551d03646d42c2"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize Memory Card Interface. <a href="group__mci__interface__gr.html#gaef8183e77797e74997551d03646d42c2">More...</a><br/></td></tr>
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<tr class="memitem:ga19752749d04ed22dc91c4294645e0244"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga19752749d04ed22dc91c4294645e0244">ARM_MCI_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga19752749d04ed22dc91c4294645e0244"><td class="mdescLeft"> </td><td class="mdescRight">Control Memory Card Interface Power. <a href="group__mci__interface__gr.html#ga19752749d04ed22dc91c4294645e0244">More...</a><br/></td></tr>
<tr class="separator:ga19752749d04ed22dc91c4294645e0244"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab161f80e0eda2815f3e0ebbba1314ff0"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#gab161f80e0eda2815f3e0ebbba1314ff0">ARM_MCI_CardPower</a> (uint32_t voltage)</td></tr>
<tr class="memdesc:gab161f80e0eda2815f3e0ebbba1314ff0"><td class="mdescLeft"> </td><td class="mdescRight">Set Memory Card Power supply voltage. <a href="group__mci__interface__gr.html#gab161f80e0eda2815f3e0ebbba1314ff0">More...</a><br/></td></tr>
<tr class="separator:gab161f80e0eda2815f3e0ebbba1314ff0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga012fca8f1ce5366fce14b708c771c635"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga012fca8f1ce5366fce14b708c771c635">ARM_MCI_ReadCD</a> (void)</td></tr>
<tr class="memdesc:ga012fca8f1ce5366fce14b708c771c635"><td class="mdescLeft"> </td><td class="mdescRight">Read Card Detect (CD) state. <a href="group__mci__interface__gr.html#ga012fca8f1ce5366fce14b708c771c635">More...</a><br/></td></tr>
<tr class="separator:ga012fca8f1ce5366fce14b708c771c635"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3d70286918405ac81fa795c7d09dc6fd"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga3d70286918405ac81fa795c7d09dc6fd">ARM_MCI_ReadWP</a> (void)</td></tr>
<tr class="memdesc:ga3d70286918405ac81fa795c7d09dc6fd"><td class="mdescLeft"> </td><td class="mdescRight">Read Write Protect (WP) state. <a href="group__mci__interface__gr.html#ga3d70286918405ac81fa795c7d09dc6fd">More...</a><br/></td></tr>
<tr class="separator:ga3d70286918405ac81fa795c7d09dc6fd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a431da89feabc2b4bc0c27943dff6f2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga5a431da89feabc2b4bc0c27943dff6f2">ARM_MCI_SendCommand</a> (uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)</td></tr>
<tr class="memdesc:ga5a431da89feabc2b4bc0c27943dff6f2"><td class="mdescLeft"> </td><td class="mdescRight">Send Command to card and get the response. <a href="group__mci__interface__gr.html#ga5a431da89feabc2b4bc0c27943dff6f2">More...</a><br/></td></tr>
<tr class="separator:ga5a431da89feabc2b4bc0c27943dff6f2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaec681bcd8e6811c5743e33ee0f35ed1"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#gaaec681bcd8e6811c5743e33ee0f35ed1">ARM_MCI_SetupTransfer</a> (uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode)</td></tr>
<tr class="memdesc:gaaec681bcd8e6811c5743e33ee0f35ed1"><td class="mdescLeft"> </td><td class="mdescRight">Setup read or write transfer operation. <a href="group__mci__interface__gr.html#gaaec681bcd8e6811c5743e33ee0f35ed1">More...</a><br/></td></tr>
<tr class="separator:gaaec681bcd8e6811c5743e33ee0f35ed1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3dfcf7b7186b711f9b63a096be816fe5"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga3dfcf7b7186b711f9b63a096be816fe5">ARM_MCI_AbortTransfer</a> (void)</td></tr>
<tr class="memdesc:ga3dfcf7b7186b711f9b63a096be816fe5"><td class="mdescLeft"> </td><td class="mdescRight">Abort current read/write data transfer. <a href="group__mci__interface__gr.html#ga3dfcf7b7186b711f9b63a096be816fe5">More...</a><br/></td></tr>
<tr class="separator:ga3dfcf7b7186b711f9b63a096be816fe5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaec0506a2aa4ae75cf6bc02528f36fe30"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#gaec0506a2aa4ae75cf6bc02528f36fe30">ARM_MCI_Control</a> (uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:gaec0506a2aa4ae75cf6bc02528f36fe30"><td class="mdescLeft"> </td><td class="mdescRight">Control MCI Interface. <a href="group__mci__interface__gr.html#gaec0506a2aa4ae75cf6bc02528f36fe30">More...</a><br/></td></tr>
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<tr class="memitem:ga8d61aa42ce78d1864fa928c1f273cbd9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__STATUS">ARM_MCI_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga8d61aa42ce78d1864fa928c1f273cbd9">ARM_MCI_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga8d61aa42ce78d1864fa928c1f273cbd9"><td class="mdescLeft"> </td><td class="mdescRight">Get MCI status. <a href="group__mci__interface__gr.html#ga8d61aa42ce78d1864fa928c1f273cbd9">More...</a><br/></td></tr>
<tr class="separator:ga8d61aa42ce78d1864fa928c1f273cbd9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaac2dbd1c1a98436938c5d0d6248cb700"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#gaac2dbd1c1a98436938c5d0d6248cb700">ARM_MCI_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:gaac2dbd1c1a98436938c5d0d6248cb700"><td class="mdescLeft"> </td><td class="mdescRight">Callback function that signals a MCI Card Event. <a href="group__mci__interface__gr.html#gaac2dbd1c1a98436938c5d0d6248cb700">More...</a><br/></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__MCI__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__STATUS">ARM_MCI_STATUS</a></td></tr>
<tr class="memdesc:structARM__MCI__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">MCI Status. <a href="group__mci__interface__gr.html#structARM__MCI__STATUS">More...</a><br/></td></tr>
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<tr class="memitem:structARM__MCI__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__MCI__CAPABILITIES">ARM_MCI_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__MCI__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">MCI Driver Capabilities. <a href="group__mci__interface__gr.html#structARM__MCI__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__MCI"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#structARM__DRIVER__MCI">ARM_DRIVER_MCI</a></td></tr>
<tr class="memdesc:structARM__DRIVER__MCI"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the MCI Driver. <a href="group__mci__interface__gr.html#structARM__DRIVER__MCI">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ac1863acc4889811dc5f45ec0e059d892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#ac1863acc4889811dc5f45ec0e059d892">ARM_MCI_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td></tr>
<tr class="separator:ac1863acc4889811dc5f45ec0e059d892"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a125bb871e85f4646ff0fa8be1ab7c8c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a125bb871e85f4646ff0fa8be1ab7c8c9">ARM_MCI_RESPONSE_Pos</a>   0</td></tr>
<tr class="separator:a125bb871e85f4646ff0fa8be1ab7c8c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af12ae94785114eb31b1e077d52eda3fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#af12ae94785114eb31b1e077d52eda3fd">ARM_MCI_RESPONSE_Msk</a>   (3UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="separator:af12ae94785114eb31b1e077d52eda3fd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga70934cef80884e8c75fb4eebf8452118"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga70934cef80884e8c75fb4eebf8452118">ARM_MCI_RESPONSE_NONE</a>   (0UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:ga70934cef80884e8c75fb4eebf8452118"><td class="mdescLeft"> </td><td class="mdescRight">No response expected (default) <a href="group__mci__send__command__flags__ctrls.html#ga70934cef80884e8c75fb4eebf8452118">More...</a><br/></td></tr>
<tr class="separator:ga70934cef80884e8c75fb4eebf8452118"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gaa5ddf1cf772b234e3c247039effd0e7b">ARM_MCI_RESPONSE_SHORT</a>   (1UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="mdescLeft"> </td><td class="mdescRight">Short response (48-bit) <a href="group__mci__send__command__flags__ctrls.html#gaa5ddf1cf772b234e3c247039effd0e7b">More...</a><br/></td></tr>
<tr class="separator:gaa5ddf1cf772b234e3c247039effd0e7b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gaa1d541b0edf32ec05e68d623c727ef9c">ARM_MCI_RESPONSE_SHORT_BUSY</a>   (2UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="mdescLeft"> </td><td class="mdescRight">Short response with busy signal (48-bit) <a href="group__mci__send__command__flags__ctrls.html#gaa1d541b0edf32ec05e68d623c727ef9c">More...</a><br/></td></tr>
<tr class="separator:gaa1d541b0edf32ec05e68d623c727ef9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac49c7b39a7c51bd2193e048835bec2fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gac49c7b39a7c51bd2193e048835bec2fb">ARM_MCI_RESPONSE_LONG</a>   (3UL << ARM_MCI_RESPONSE_Pos)</td></tr>
<tr class="memdesc:gac49c7b39a7c51bd2193e048835bec2fb"><td class="mdescLeft"> </td><td class="mdescRight">Long response (136-bit) <a href="group__mci__send__command__flags__ctrls.html#gac49c7b39a7c51bd2193e048835bec2fb">More...</a><br/></td></tr>
<tr class="separator:gac49c7b39a7c51bd2193e048835bec2fb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga497abf878c6e12f54cc7ddb92da76c4a">ARM_MCI_RESPONSE_INDEX</a>   (1UL << 2)</td></tr>
<tr class="memdesc:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="mdescLeft"> </td><td class="mdescRight">Check command index in response. <a href="group__mci__send__command__flags__ctrls.html#ga497abf878c6e12f54cc7ddb92da76c4a">More...</a><br/></td></tr>
<tr class="separator:ga497abf878c6e12f54cc7ddb92da76c4a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de">ARM_MCI_RESPONSE_CRC</a>   (1UL << 3)</td></tr>
<tr class="memdesc:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="mdescLeft"> </td><td class="mdescRight">Check CRC in response. <a href="group__mci__send__command__flags__ctrls.html#ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de">More...</a><br/></td></tr>
<tr class="separator:ga6ab3f4c1a2bf0fdb81fbcf7a5698f2de"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga68e879799bb27a1b13baf57ed19d719d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga68e879799bb27a1b13baf57ed19d719d">ARM_MCI_WAIT_BUSY</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga68e879799bb27a1b13baf57ed19d719d"><td class="mdescLeft"> </td><td class="mdescRight">Wait until busy before sending the command. <a href="group__mci__send__command__flags__ctrls.html#ga68e879799bb27a1b13baf57ed19d719d">More...</a><br/></td></tr>
<tr class="separator:ga68e879799bb27a1b13baf57ed19d719d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8aa566f69aa74ed416213df6ca3267bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga8aa566f69aa74ed416213df6ca3267bd">ARM_MCI_TRANSFER_DATA</a>   (1UL << 5)</td></tr>
<tr class="memdesc:ga8aa566f69aa74ed416213df6ca3267bd"><td class="mdescLeft"> </td><td class="mdescRight">Activate Data transfer. <a href="group__mci__send__command__flags__ctrls.html#ga8aa566f69aa74ed416213df6ca3267bd">More...</a><br/></td></tr>
<tr class="separator:ga8aa566f69aa74ed416213df6ca3267bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga81606bd94ce782e2c3764b913f929f60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga81606bd94ce782e2c3764b913f929f60">ARM_MCI_CARD_INITIALIZE</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ga81606bd94ce782e2c3764b913f929f60"><td class="mdescLeft"> </td><td class="mdescRight">Execute Memory Card initialization sequence. <a href="group__mci__send__command__flags__ctrls.html#ga81606bd94ce782e2c3764b913f929f60">More...</a><br/></td></tr>
<tr class="separator:ga81606bd94ce782e2c3764b913f929f60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab2bfeedf1dc2df1872ebbcc559a7385a">ARM_MCI_INTERRUPT_COMMAND</a>   (1UL << 7)</td></tr>
<tr class="memdesc:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="mdescLeft"> </td><td class="mdescRight">Send Interrupt command (CMD40 - MMC only) <a href="group__mci__send__command__flags__ctrls.html#gab2bfeedf1dc2df1872ebbcc559a7385a">More...</a><br/></td></tr>
<tr class="separator:gab2bfeedf1dc2df1872ebbcc559a7385a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc31b6b26988998c84c92a9a698fd5dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gabc31b6b26988998c84c92a9a698fd5dc">ARM_MCI_INTERRUPT_RESPONSE</a>   (1UL << 8)</td></tr>
<tr class="memdesc:gabc31b6b26988998c84c92a9a698fd5dc"><td class="mdescLeft"> </td><td class="mdescRight">Send Interrupt response (CMD40 - MMC only) <a href="group__mci__send__command__flags__ctrls.html#gabc31b6b26988998c84c92a9a698fd5dc">More...</a><br/></td></tr>
<tr class="separator:gabc31b6b26988998c84c92a9a698fd5dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae04254f51dfd9838583206cae0a5f8f7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gae04254f51dfd9838583206cae0a5f8f7">ARM_MCI_BOOT_OPERATION</a>   (1UL << 9)</td></tr>
<tr class="memdesc:gae04254f51dfd9838583206cae0a5f8f7"><td class="mdescLeft"> </td><td class="mdescRight">Execute Boot operation (MMC only) <a href="group__mci__send__command__flags__ctrls.html#gae04254f51dfd9838583206cae0a5f8f7">More...</a><br/></td></tr>
<tr class="separator:gae04254f51dfd9838583206cae0a5f8f7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga30bd304652d4f870ee7ce61c266a9348"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga30bd304652d4f870ee7ce61c266a9348">ARM_MCI_BOOT_ALTERNATIVE</a>   (1UL << 10)</td></tr>
<tr class="memdesc:ga30bd304652d4f870ee7ce61c266a9348"><td class="mdescLeft"> </td><td class="mdescRight">Execute Alternative Boot operation (MMC only) <a href="group__mci__send__command__flags__ctrls.html#ga30bd304652d4f870ee7ce61c266a9348">More...</a><br/></td></tr>
<tr class="separator:ga30bd304652d4f870ee7ce61c266a9348"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8c55bc0a310630d49810802ccd1bb10d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#ga8c55bc0a310630d49810802ccd1bb10d">ARM_MCI_BOOT_ACK</a>   (1UL << 11)</td></tr>
<tr class="memdesc:ga8c55bc0a310630d49810802ccd1bb10d"><td class="mdescLeft"> </td><td class="mdescRight">Expect Boot Acknowledge (MMC only) <a href="group__mci__send__command__flags__ctrls.html#ga8c55bc0a310630d49810802ccd1bb10d">More...</a><br/></td></tr>
<tr class="separator:ga8c55bc0a310630d49810802ccd1bb10d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab9df5169b37621764f8bb0f93db5281a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab9df5169b37621764f8bb0f93db5281a">ARM_MCI_CCSD</a>   (1UL << 12)</td></tr>
<tr class="memdesc:gab9df5169b37621764f8bb0f93db5281a"><td class="mdescLeft"> </td><td class="mdescRight">Send Command Completion Signal Disable (CCSD) for CE-ATA device. <a href="group__mci__send__command__flags__ctrls.html#gab9df5169b37621764f8bb0f93db5281a">More...</a><br/></td></tr>
<tr class="separator:gab9df5169b37621764f8bb0f93db5281a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab82c472e4ca3fca12ae3291e25997f00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__send__command__flags__ctrls.html#gab82c472e4ca3fca12ae3291e25997f00">ARM_MCI_CCS</a>   (1UL << 13)</td></tr>
<tr class="memdesc:gab82c472e4ca3fca12ae3291e25997f00"><td class="mdescLeft"> </td><td class="mdescRight">Expect Command Completion Signal (CCS) for CE-ATA device. <a href="group__mci__send__command__flags__ctrls.html#gab82c472e4ca3fca12ae3291e25997f00">More...</a><br/></td></tr>
<tr class="separator:gab82c472e4ca3fca12ae3291e25997f00"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa6f3be235a9dce5c66be8fe64f399846"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gaa6f3be235a9dce5c66be8fe64f399846">ARM_MCI_TRANSFER_READ</a>   (0UL << 0)</td></tr>
<tr class="memdesc:gaa6f3be235a9dce5c66be8fe64f399846"><td class="mdescLeft"> </td><td class="mdescRight">Data Read Transfer (from MCI) <a href="group__mci__transfer__ctrls.html#gaa6f3be235a9dce5c66be8fe64f399846">More...</a><br/></td></tr>
<tr class="separator:gaa6f3be235a9dce5c66be8fe64f399846"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaddc60aab15f75993a99f98f71ddbd50c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gaddc60aab15f75993a99f98f71ddbd50c">ARM_MCI_TRANSFER_WRITE</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gaddc60aab15f75993a99f98f71ddbd50c"><td class="mdescLeft"> </td><td class="mdescRight">Data Write Transfer (to MCI) <a href="group__mci__transfer__ctrls.html#gaddc60aab15f75993a99f98f71ddbd50c">More...</a><br/></td></tr>
<tr class="separator:gaddc60aab15f75993a99f98f71ddbd50c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#ga4ced782e7c0c70d5f0edbddd1e48323b">ARM_MCI_TRANSFER_BLOCK</a>   (0UL << 1)</td></tr>
<tr class="memdesc:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="mdescLeft"> </td><td class="mdescRight">Block Data transfer (default) <a href="group__mci__transfer__ctrls.html#ga4ced782e7c0c70d5f0edbddd1e48323b">More...</a><br/></td></tr>
<tr class="separator:ga4ced782e7c0c70d5f0edbddd1e48323b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac7db0cffd571e60758627d889ba7a432"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__transfer__ctrls.html#gac7db0cffd571e60758627d889ba7a432">ARM_MCI_TRANSFER_STREAM</a>   (1UL << 1)</td></tr>
<tr class="memdesc:gac7db0cffd571e60758627d889ba7a432"><td class="mdescLeft"> </td><td class="mdescRight">Stream Data transfer (MMC only) <a href="group__mci__transfer__ctrls.html#gac7db0cffd571e60758627d889ba7a432">More...</a><br/></td></tr>
<tr class="separator:gac7db0cffd571e60758627d889ba7a432"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga7f982d2e5aec768307d35a83c65fb3ef">ARM_MCI_BUS_SPEED</a>   (0x01)</td></tr>
<tr class="memdesc:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s. <a href="group__mci__mode__ctrls.html#ga7f982d2e5aec768307d35a83c65fb3ef">More...</a><br/></td></tr>
<tr class="separator:ga7f982d2e5aec768307d35a83c65fb3ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gaf7ede525eabc618fbbb9f7a294c8ed96">ARM_MCI_BUS_SPEED_MODE</a>   (0x02)</td></tr>
<tr class="memdesc:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed Mode as specified with arg. <a href="group__mci__mode__ctrls.html#gaf7ede525eabc618fbbb9f7a294c8ed96">More...</a><br/></td></tr>
<tr class="separator:gaf7ede525eabc618fbbb9f7a294c8ed96"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8b7571e37520c07d8ef4f697f3886715"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga8b7571e37520c07d8ef4f697f3886715">ARM_MCI_BUS_CMD_MODE</a>   (0x03)</td></tr>
<tr class="memdesc:ga8b7571e37520c07d8ef4f697f3886715"><td class="mdescLeft"> </td><td class="mdescRight">Set CMD Line Mode as specified with arg. <a href="group__mci__mode__ctrls.html#ga8b7571e37520c07d8ef4f697f3886715">More...</a><br/></td></tr>
<tr class="separator:ga8b7571e37520c07d8ef4f697f3886715"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga876d964d0eeacdb16e93f7558a544587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga876d964d0eeacdb16e93f7558a544587">ARM_MCI_BUS_DATA_WIDTH</a>   (0x04)</td></tr>
<tr class="memdesc:ga876d964d0eeacdb16e93f7558a544587"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Data Width as specified with arg. <a href="group__mci__mode__ctrls.html#ga876d964d0eeacdb16e93f7558a544587">More...</a><br/></td></tr>
<tr class="separator:ga876d964d0eeacdb16e93f7558a544587"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga78068f519139f2ae7b09e0608070aaf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga78068f519139f2ae7b09e0608070aaf6">ARM_MCI_DRIVER_STRENGTH</a>   (0x05)</td></tr>
<tr class="memdesc:ga78068f519139f2ae7b09e0608070aaf6"><td class="mdescLeft"> </td><td class="mdescRight">Set SD UHS-I Driver Strength as specified with arg. <a href="group__mci__mode__ctrls.html#ga78068f519139f2ae7b09e0608070aaf6">More...</a><br/></td></tr>
<tr class="separator:ga78068f519139f2ae7b09e0608070aaf6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga21e403e8c3fa8cc75431a513813f0a16"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga21e403e8c3fa8cc75431a513813f0a16">ARM_MCI_CONTROL_RESET</a>   (0x06)</td></tr>
<tr class="memdesc:ga21e403e8c3fa8cc75431a513813f0a16"><td class="mdescLeft"> </td><td class="mdescRight">Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active. <a href="group__mci__mode__ctrls.html#ga21e403e8c3fa8cc75431a513813f0a16">More...</a><br/></td></tr>
<tr class="separator:ga21e403e8c3fa8cc75431a513813f0a16"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga889473fbfbdcb89aab4d53cc8a13f615">ARM_MCI_CONTROL_CLOCK_IDLE</a>   (0x07)</td></tr>
<tr class="memdesc:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="mdescLeft"> </td><td class="mdescRight">Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#ga889473fbfbdcb89aab4d53cc8a13f615">More...</a><br/></td></tr>
<tr class="separator:ga889473fbfbdcb89aab4d53cc8a13f615"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga98853f60bdc085aeeccd66f7bdf22d3d">ARM_MCI_UHS_TUNING_OPERATION</a>   (0x08)</td></tr>
<tr class="memdesc:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="mdescLeft"> </td><td class="mdescRight">Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute. <a href="group__mci__mode__ctrls.html#ga98853f60bdc085aeeccd66f7bdf22d3d">More...</a><br/></td></tr>
<tr class="separator:ga98853f60bdc085aeeccd66f7bdf22d3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd3af448e26da5657c1c5a03330476b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gabd3af448e26da5657c1c5a03330476b7">ARM_MCI_UHS_TUNING_RESULT</a>   (0x09)</td></tr>
<tr class="memdesc:gabd3af448e26da5657c1c5a03330476b7"><td class="mdescLeft"> </td><td class="mdescRight">Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error. <a href="group__mci__mode__ctrls.html#gabd3af448e26da5657c1c5a03330476b7">More...</a><br/></td></tr>
<tr class="separator:gabd3af448e26da5657c1c5a03330476b7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga09a58821e42595f0c2e55f8cc2d32ceb">ARM_MCI_DATA_TIMEOUT</a>   (0x0A)</td></tr>
<tr class="memdesc:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="mdescLeft"> </td><td class="mdescRight">Set Data timeout; arg = timeout in bus cycles. <a href="group__mci__mode__ctrls.html#ga09a58821e42595f0c2e55f8cc2d32ceb">More...</a><br/></td></tr>
<tr class="separator:ga09a58821e42595f0c2e55f8cc2d32ceb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gae97b1a819a5d326b1f1009b0d6d48b5a">ARM_MCI_CSS_TIMEOUT</a>   (0x0B)</td></tr>
<tr class="memdesc:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="mdescLeft"> </td><td class="mdescRight">Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles. <a href="group__mci__mode__ctrls.html#gae97b1a819a5d326b1f1009b0d6d48b5a">More...</a><br/></td></tr>
<tr class="separator:gae97b1a819a5d326b1f1009b0d6d48b5a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga19fd7d3b74ac48ca74a2e138b3ee9963">ARM_MCI_MONITOR_SDIO_INTERRUPT</a>   (0x0C)</td></tr>
<tr class="memdesc:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="mdescLeft"> </td><td class="mdescRight">Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#ga19fd7d3b74ac48ca74a2e138b3ee9963">More...</a><br/></td></tr>
<tr class="separator:ga19fd7d3b74ac48ca74a2e138b3ee9963"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gaaa10c5aa7a8108aa59c3734b3eec2e3a">ARM_MCI_CONTROL_READ_WAIT</a>   (0x0D)</td></tr>
<tr class="memdesc:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="mdescLeft"> </td><td class="mdescRight">Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled. <a href="group__mci__mode__ctrls.html#gaaa10c5aa7a8108aa59c3734b3eec2e3a">More...</a><br/></td></tr>
<tr class="separator:gaaa10c5aa7a8108aa59c3734b3eec2e3a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#ga04cf174b0ef13240f26225bf8e45a4a0">ARM_MCI_SUSPEND_TRANSFER</a>   (0x0E)</td></tr>
<tr class="memdesc:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="mdescLeft"> </td><td class="mdescRight">Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer. <a href="group__mci__mode__ctrls.html#ga04cf174b0ef13240f26225bf8e45a4a0">More...</a><br/></td></tr>
<tr class="separator:ga04cf174b0ef13240f26225bf8e45a4a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac4907319499072fddf61f2f83b0dd966"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__mode__ctrls.html#gac4907319499072fddf61f2f83b0dd966">ARM_MCI_RESUME_TRANSFER</a>   (0x0F)</td></tr>
<tr class="memdesc:gac4907319499072fddf61f2f83b0dd966"><td class="mdescLeft"> </td><td class="mdescRight">Resume Data transfer (SD I/O) <a href="group__mci__mode__ctrls.html#gac4907319499072fddf61f2f83b0dd966">More...</a><br/></td></tr>
<tr class="separator:gac4907319499072fddf61f2f83b0dd966"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga601fa8b27ab2e5f6d90c93d54c8f412d">ARM_MCI_BUS_DEFAULT_SPEED</a>   (0x00)</td></tr>
<tr class="memdesc:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="mdescLeft"> </td><td class="mdescRight">SD/MMC: Default Speed mode up to 25/26MHz. <a href="group__mci__bus__speed__ctrls.html#ga601fa8b27ab2e5f6d90c93d54c8f412d">More...</a><br/></td></tr>
<tr class="separator:ga601fa8b27ab2e5f6d90c93d54c8f412d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaabda746ac7d6b4497358ff655a8ea6be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gaabda746ac7d6b4497358ff655a8ea6be">ARM_MCI_BUS_HIGH_SPEED</a>   (0x01)</td></tr>
<tr class="memdesc:gaabda746ac7d6b4497358ff655a8ea6be"><td class="mdescLeft"> </td><td class="mdescRight">SD/MMC: High Speed mode up to 50/52MHz. <a href="group__mci__bus__speed__ctrls.html#gaabda746ac7d6b4497358ff655a8ea6be">More...</a><br/></td></tr>
<tr class="separator:gaabda746ac7d6b4497358ff655a8ea6be"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga0473c44a7b65044b3c6a8e7012009a4a">ARM_MCI_BUS_UHS_SDR12</a>   (0x02)</td></tr>
<tr class="memdesc:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga0473c44a7b65044b3c6a8e7012009a4a">More...</a><br/></td></tr>
<tr class="separator:ga0473c44a7b65044b3c6a8e7012009a4a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae32422631052307b3c4d269b25415907"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gae32422631052307b3c4d269b25415907">ARM_MCI_BUS_UHS_SDR25</a>   (0x03)</td></tr>
<tr class="memdesc:gae32422631052307b3c4d269b25415907"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#gae32422631052307b3c4d269b25415907">More...</a><br/></td></tr>
<tr class="separator:gae32422631052307b3c4d269b25415907"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f326c02391d965918ae619b912b81e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga9f326c02391d965918ae619b912b81e7">ARM_MCI_BUS_UHS_SDR50</a>   (0x04)</td></tr>
<tr class="memdesc:ga9f326c02391d965918ae619b912b81e7"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga9f326c02391d965918ae619b912b81e7">More...</a><br/></td></tr>
<tr class="separator:ga9f326c02391d965918ae619b912b81e7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#gad2bab563e7bbb4bcf6bdabe6a13dadf4">ARM_MCI_BUS_UHS_SDR104</a>   (0x05)</td></tr>
<tr class="memdesc:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="mdescLeft"> </td><td class="mdescRight">SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#gad2bab563e7bbb4bcf6bdabe6a13dadf4">More...</a><br/></td></tr>
<tr class="separator:gad2bab563e7bbb4bcf6bdabe6a13dadf4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04da920a5cac99eab9784527057f1b9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__speed__ctrls.html#ga04da920a5cac99eab9784527057f1b9c">ARM_MCI_BUS_UHS_DDR50</a>   (0x06)</td></tr>
<tr class="memdesc:ga04da920a5cac99eab9784527057f1b9c"><td class="mdescLeft"> </td><td class="mdescRight">SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling. <a href="group__mci__bus__speed__ctrls.html#ga04da920a5cac99eab9784527057f1b9c">More...</a><br/></td></tr>
<tr class="separator:ga04da920a5cac99eab9784527057f1b9c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaed404312d9bc073e3489779a911c7dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__cmd__line__ctrls.html#gaaed404312d9bc073e3489779a911c7dc">ARM_MCI_BUS_CMD_PUSH_PULL</a>   (0x00)</td></tr>
<tr class="memdesc:gaaed404312d9bc073e3489779a911c7dc"><td class="mdescLeft"> </td><td class="mdescRight">Push-Pull CMD line (default) <a href="group__mci__cmd__line__ctrls.html#gaaed404312d9bc073e3489779a911c7dc">More...</a><br/></td></tr>
<tr class="separator:gaaed404312d9bc073e3489779a911c7dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaadf8667985731964d57d1ed672e90fd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__cmd__line__ctrls.html#gaadf8667985731964d57d1ed672e90fd3">ARM_MCI_BUS_CMD_OPEN_DRAIN</a>   (0x01)</td></tr>
<tr class="memdesc:gaadf8667985731964d57d1ed672e90fd3"><td class="mdescLeft"> </td><td class="mdescRight">Open Drain CMD line (MMC only) <a href="group__mci__cmd__line__ctrls.html#gaadf8667985731964d57d1ed672e90fd3">More...</a><br/></td></tr>
<tr class="separator:gaadf8667985731964d57d1ed672e90fd3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa09a00d810a4dfd1d1824311ee290585"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaa09a00d810a4dfd1d1824311ee290585">ARM_MCI_BUS_DATA_WIDTH_1</a>   (0x00)</td></tr>
<tr class="memdesc:gaa09a00d810a4dfd1d1824311ee290585"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 1 bit (default) <a href="group__mci__bus__data__width__ctrls.html#gaa09a00d810a4dfd1d1824311ee290585">More...</a><br/></td></tr>
<tr class="separator:gaa09a00d810a4dfd1d1824311ee290585"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaa28150d8c3789e8cf1bcda318f74a28c">ARM_MCI_BUS_DATA_WIDTH_4</a>   (0x01)</td></tr>
<tr class="memdesc:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 4 bits. <a href="group__mci__bus__data__width__ctrls.html#gaa28150d8c3789e8cf1bcda318f74a28c">More...</a><br/></td></tr>
<tr class="separator:gaa28150d8c3789e8cf1bcda318f74a28c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#ga3bb99a2d98ba9fb8c5bc97fa2b8ef469">ARM_MCI_BUS_DATA_WIDTH_8</a>   (0x02)</td></tr>
<tr class="memdesc:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 8 bits. <a href="group__mci__bus__data__width__ctrls.html#ga3bb99a2d98ba9fb8c5bc97fa2b8ef469">More...</a><br/></td></tr>
<tr class="separator:ga3bb99a2d98ba9fb8c5bc97fa2b8ef469"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#gaccb174bd131f8fd8cd9a56439a8ebb60">ARM_MCI_BUS_DATA_WIDTH_4_DDR</a>   (0x03)</td></tr>
<tr class="memdesc:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only. <a href="group__mci__bus__data__width__ctrls.html#gaccb174bd131f8fd8cd9a56439a8ebb60">More...</a><br/></td></tr>
<tr class="separator:gaccb174bd131f8fd8cd9a56439a8ebb60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7b31f81ae703229095fe9efcfbe80b47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__bus__data__width__ctrls.html#ga7b31f81ae703229095fe9efcfbe80b47">ARM_MCI_BUS_DATA_WIDTH_8_DDR</a>   (0x04)</td></tr>
<tr class="memdesc:ga7b31f81ae703229095fe9efcfbe80b47"><td class="mdescLeft"> </td><td class="mdescRight">Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only. <a href="group__mci__bus__data__width__ctrls.html#ga7b31f81ae703229095fe9efcfbe80b47">More...</a><br/></td></tr>
<tr class="separator:ga7b31f81ae703229095fe9efcfbe80b47"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga64eb1c4847711a262f084c361b60a912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga64eb1c4847711a262f084c361b60a912">ARM_MCI_DRIVER_TYPE_A</a>   (0x01)</td></tr>
<tr class="memdesc:ga64eb1c4847711a262f084c361b60a912"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type A. <a href="group__mci__driver__strength__ctrls.html#ga64eb1c4847711a262f084c361b60a912">More...</a><br/></td></tr>
<tr class="separator:ga64eb1c4847711a262f084c361b60a912"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga078d3c3bc7c9335b92e6445a0abafc46">ARM_MCI_DRIVER_TYPE_B</a>   (0x00)</td></tr>
<tr class="memdesc:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type B (default) <a href="group__mci__driver__strength__ctrls.html#ga078d3c3bc7c9335b92e6445a0abafc46">More...</a><br/></td></tr>
<tr class="separator:ga078d3c3bc7c9335b92e6445a0abafc46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3da11696d1fcd3930eb7e70fe097d747"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga3da11696d1fcd3930eb7e70fe097d747">ARM_MCI_DRIVER_TYPE_C</a>   (0x02)</td></tr>
<tr class="memdesc:ga3da11696d1fcd3930eb7e70fe097d747"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type C. <a href="group__mci__driver__strength__ctrls.html#ga3da11696d1fcd3930eb7e70fe097d747">More...</a><br/></td></tr>
<tr class="separator:ga3da11696d1fcd3930eb7e70fe097d747"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__driver__strength__ctrls.html#ga8185f82b1d8857a3f0eb461d664f2b3d">ARM_MCI_DRIVER_TYPE_D</a>   (0x03)</td></tr>
<tr class="memdesc:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="mdescLeft"> </td><td class="mdescRight">SD UHS-I Driver Type D. <a href="group__mci__driver__strength__ctrls.html#ga8185f82b1d8857a3f0eb461d664f2b3d">More...</a><br/></td></tr>
<tr class="separator:ga8185f82b1d8857a3f0eb461d664f2b3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8de1e84f879b741ed1e13a0aac93a246"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a8de1e84f879b741ed1e13a0aac93a246">ARM_MCI_POWER_VDD_Pos</a>   0</td></tr>
<tr class="separator:a8de1e84f879b741ed1e13a0aac93a246"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a58913d82ea4abd60dee50cec024de4a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#a58913d82ea4abd60dee50cec024de4a0">ARM_MCI_POWER_VDD_Msk</a>   (0x0FUL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="separator:a58913d82ea4abd60dee50cec024de4a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga288fbd80b384739a80e8f3ec31205cf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga288fbd80b384739a80e8f3ec31205cf5">ARM_MCI_POWER_VDD_OFF</a>   (0x01UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga288fbd80b384739a80e8f3ec31205cf5"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) turned off. <a href="group__mci__card__power__ctrls.html#ga288fbd80b384739a80e8f3ec31205cf5">More...</a><br/></td></tr>
<tr class="separator:ga288fbd80b384739a80e8f3ec31205cf5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga565ecd36c8d0379fb4172da577cc540d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga565ecd36c8d0379fb4172da577cc540d">ARM_MCI_POWER_VDD_3V3</a>   (0x02UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga565ecd36c8d0379fb4172da577cc540d"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) = 3.3V. <a href="group__mci__card__power__ctrls.html#ga565ecd36c8d0379fb4172da577cc540d">More...</a><br/></td></tr>
<tr class="separator:ga565ecd36c8d0379fb4172da577cc540d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga2ce8e379c3691da3b51c9c97d61770ef">ARM_MCI_POWER_VDD_1V8</a>   (0x03UL << ARM_MCI_POWER_VDD_Pos)</td></tr>
<tr class="memdesc:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="mdescLeft"> </td><td class="mdescRight">VDD (VCC) = 1.8V. <a href="group__mci__card__power__ctrls.html#ga2ce8e379c3691da3b51c9c97d61770ef">More...</a><br/></td></tr>
<tr class="separator:ga2ce8e379c3691da3b51c9c97d61770ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae2de0ecc2d5d73b134c18b80bedb23a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#ae2de0ecc2d5d73b134c18b80bedb23a7">ARM_MCI_POWER_VCCQ_Pos</a>   4</td></tr>
<tr class="separator:ae2de0ecc2d5d73b134c18b80bedb23a7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aef11db3d5da54f0e0cf2e346f08622e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__MCI_8h.html#aef11db3d5da54f0e0cf2e346f08622e2">ARM_MCI_POWER_VCCQ_Msk</a>   (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="separator:aef11db3d5da54f0e0cf2e346f08622e2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6929c98a6bc8d898939a95111509220b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga6929c98a6bc8d898939a95111509220b">ARM_MCI_POWER_VCCQ_OFF</a>   (0x01UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga6929c98a6bc8d898939a95111509220b"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ turned off <a href="group__mci__card__power__ctrls.html#ga6929c98a6bc8d898939a95111509220b">More...</a><br/></td></tr>
<tr class="separator:ga6929c98a6bc8d898939a95111509220b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga91a7201173cc092eaf7f0bcee028871e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga91a7201173cc092eaf7f0bcee028871e">ARM_MCI_POWER_VCCQ_3V3</a>   (0x02UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga91a7201173cc092eaf7f0bcee028871e"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 3.3V <a href="group__mci__card__power__ctrls.html#ga91a7201173cc092eaf7f0bcee028871e">More...</a><br/></td></tr>
<tr class="separator:ga91a7201173cc092eaf7f0bcee028871e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#gaaf389e0a139d5808dff8ebb6897d4c7b">ARM_MCI_POWER_VCCQ_1V8</a>   (0x03UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 1.8V <a href="group__mci__card__power__ctrls.html#gaaf389e0a139d5808dff8ebb6897d4c7b">More...</a><br/></td></tr>
<tr class="separator:gaaf389e0a139d5808dff8ebb6897d4c7b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__card__power__ctrls.html#ga5304b3b6cadc5113f841c3d526ab5db6">ARM_MCI_POWER_VCCQ_1V2</a>   (0x04UL << ARM_MCI_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="mdescLeft"> </td><td class="mdescRight">eMMC VCCQ = 1.2V <a href="group__mci__card__power__ctrls.html#ga5304b3b6cadc5113f841c3d526ab5db6">More...</a><br/></td></tr>
<tr class="separator:ga5304b3b6cadc5113f841c3d526ab5db6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae2cf8ef238c092e94e96a01602f3a23c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gae2cf8ef238c092e94e96a01602f3a23c">ARM_MCI_EVENT_CARD_INSERTED</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gae2cf8ef238c092e94e96a01602f3a23c"><td class="mdescLeft"> </td><td class="mdescRight">Memory Card inserted. <a href="group__mci__event__gr.html#gae2cf8ef238c092e94e96a01602f3a23c">More...</a><br/></td></tr>
<tr class="separator:gae2cf8ef238c092e94e96a01602f3a23c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga92ba748f9324ec13898f10456f17c8cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga92ba748f9324ec13898f10456f17c8cc">ARM_MCI_EVENT_CARD_REMOVED</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga92ba748f9324ec13898f10456f17c8cc"><td class="mdescLeft"> </td><td class="mdescRight">Memory Card removed. <a href="group__mci__event__gr.html#ga92ba748f9324ec13898f10456f17c8cc">More...</a><br/></td></tr>
<tr class="separator:ga92ba748f9324ec13898f10456f17c8cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae69356c75d55103d93ef91ac1bc02b49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gae69356c75d55103d93ef91ac1bc02b49">ARM_MCI_EVENT_COMMAND_COMPLETE</a>   (1UL << 2)</td></tr>
<tr class="memdesc:gae69356c75d55103d93ef91ac1bc02b49"><td class="mdescLeft"> </td><td class="mdescRight">Command completed. <a href="group__mci__event__gr.html#gae69356c75d55103d93ef91ac1bc02b49">More...</a><br/></td></tr>
<tr class="separator:gae69356c75d55103d93ef91ac1bc02b49"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab79b3ab4dcd03c38df1e173fa903d822"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gab79b3ab4dcd03c38df1e173fa903d822">ARM_MCI_EVENT_COMMAND_TIMEOUT</a>   (1UL << 3)</td></tr>
<tr class="memdesc:gab79b3ab4dcd03c38df1e173fa903d822"><td class="mdescLeft"> </td><td class="mdescRight">Command timeout. <a href="group__mci__event__gr.html#gab79b3ab4dcd03c38df1e173fa903d822">More...</a><br/></td></tr>
<tr class="separator:gab79b3ab4dcd03c38df1e173fa903d822"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga373aeb3eca0e4c6d159312488a130442"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga373aeb3eca0e4c6d159312488a130442">ARM_MCI_EVENT_COMMAND_ERROR</a>   (1UL << 4)</td></tr>
<tr class="memdesc:ga373aeb3eca0e4c6d159312488a130442"><td class="mdescLeft"> </td><td class="mdescRight">Command response error (CRC error or invalid response) <a href="group__mci__event__gr.html#ga373aeb3eca0e4c6d159312488a130442">More...</a><br/></td></tr>
<tr class="separator:ga373aeb3eca0e4c6d159312488a130442"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc3c468dedaed890683360f2c5c65bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gabc3c468dedaed890683360f2c5c65bea">ARM_MCI_EVENT_TRANSFER_COMPLETE</a>   (1UL << 5)</td></tr>
<tr class="memdesc:gabc3c468dedaed890683360f2c5c65bea"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer completed. <a href="group__mci__event__gr.html#gabc3c468dedaed890683360f2c5c65bea">More...</a><br/></td></tr>
<tr class="separator:gabc3c468dedaed890683360f2c5c65bea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga614e7c7226adbaa8ec4165bf8b87ef27">ARM_MCI_EVENT_TRANSFER_TIMEOUT</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer timeout. <a href="group__mci__event__gr.html#ga614e7c7226adbaa8ec4165bf8b87ef27">More...</a><br/></td></tr>
<tr class="separator:ga614e7c7226adbaa8ec4165bf8b87ef27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5d2cee5ba6d0e40ad505983155706c29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga5d2cee5ba6d0e40ad505983155706c29">ARM_MCI_EVENT_TRANSFER_ERROR</a>   (1UL << 7)</td></tr>
<tr class="memdesc:ga5d2cee5ba6d0e40ad505983155706c29"><td class="mdescLeft"> </td><td class="mdescRight">Data transfer CRC failed. <a href="group__mci__event__gr.html#ga5d2cee5ba6d0e40ad505983155706c29">More...</a><br/></td></tr>
<tr class="separator:ga5d2cee5ba6d0e40ad505983155706c29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga75a050fdfe04e6816e96c938d6a6c197"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga75a050fdfe04e6816e96c938d6a6c197">ARM_MCI_EVENT_SDIO_INTERRUPT</a>   (1UL << 8)</td></tr>
<tr class="memdesc:ga75a050fdfe04e6816e96c938d6a6c197"><td class="mdescLeft"> </td><td class="mdescRight">SD I/O Interrupt. <a href="group__mci__event__gr.html#ga75a050fdfe04e6816e96c938d6a6c197">More...</a><br/></td></tr>
<tr class="separator:ga75a050fdfe04e6816e96c938d6a6c197"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#ga8161f3960ddf2a3cdc3c4c83148c6099">ARM_MCI_EVENT_CCS</a>   (1UL << 9)</td></tr>
<tr class="memdesc:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="mdescLeft"> </td><td class="mdescRight">Command Completion Signal (CCS) <a href="group__mci__event__gr.html#ga8161f3960ddf2a3cdc3c4c83148c6099">More...</a><br/></td></tr>
<tr class="separator:ga8161f3960ddf2a3cdc3c4c83148c6099"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa8cbcd597a05c64901eeb777cc0b74f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__event__gr.html#gafa8cbcd597a05c64901eeb777cc0b74f">ARM_MCI_EVENT_CCS_TIMEOUT</a>   (1UL << 10)</td></tr>
<tr class="memdesc:gafa8cbcd597a05c64901eeb777cc0b74f"><td class="mdescLeft"> </td><td class="mdescRight">Command Completion Signal (CCS) Timeout. <a href="group__mci__event__gr.html#gafa8cbcd597a05c64901eeb777cc0b74f">More...</a><br/></td></tr>
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<tr class="memitem:ga0d14651f6788c1ffd81544602565faf1"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mci__interface__gr.html#ga0d14651f6788c1ffd81544602565faf1">ARM_MCI_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:ga0d14651f6788c1ffd81544602565faf1"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__mci__interface__gr.html#gaac2dbd1c1a98436938c5d0d6248cb700">ARM_MCI_SignalEvent</a> : Signal MCI Card Event. <a href="group__mci__interface__gr.html#ga0d14651f6788c1ffd81544602565faf1">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_MCI_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td>
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<td class="memname">#define ARM_MCI_RESPONSE_Pos   0</td>
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<td class="memname">#define ARM_MCI_RESPONSE_Msk   (3UL << ARM_MCI_RESPONSE_Pos)</td>
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<td class="memname">#define ARM_MCI_POWER_VDD_Pos   0</td>
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<td class="memname">#define ARM_MCI_POWER_VDD_Msk   (0x0FUL << ARM_MCI_POWER_VDD_Pos)</td>
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<td class="memname">#define ARM_MCI_POWER_VCCQ_Pos   4</td>
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<td class="memname">#define ARM_MCI_POWER_VCCQ_Msk   (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)</td>
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Functions</h2></td></tr>
<tr class="memitem:ga01255fd4f15e7fa4751c7ea59648ef5a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga01255fd4f15e7fa4751c7ea59648ef5a">ARM_NAND_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga01255fd4f15e7fa4751c7ea59648ef5a"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__nand__interface__gr.html#ga01255fd4f15e7fa4751c7ea59648ef5a">More...</a><br/></td></tr>
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<tr class="memitem:ga9f2609975c2008d21b9ae28f15daf147"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">ARM_NAND_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9f2609975c2008d21b9ae28f15daf147">ARM_NAND_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga9f2609975c2008d21b9ae28f15daf147"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__nand__interface__gr.html#ga9f2609975c2008d21b9ae28f15daf147">More...</a><br/></td></tr>
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<tr class="memitem:ga74ad34718a595e7a4375b90f33e72750"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga74ad34718a595e7a4375b90f33e72750">ARM_NAND_Initialize</a> (<a class="el" href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">ARM_NAND_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga74ad34718a595e7a4375b90f33e72750"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the NAND Interface. <a href="group__nand__interface__gr.html#ga74ad34718a595e7a4375b90f33e72750">More...</a><br/></td></tr>
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<tr class="memitem:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gaa788b638ab696b166fee2f4a4bc8d97a">ARM_NAND_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize the NAND Interface. <a href="group__nand__interface__gr.html#gaa788b638ab696b166fee2f4a4bc8d97a">More...</a><br/></td></tr>
<tr class="separator:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9c9975637980b5d42db7baba0191fda1"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9c9975637980b5d42db7baba0191fda1">ARM_NAND_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga9c9975637980b5d42db7baba0191fda1"><td class="mdescLeft"> </td><td class="mdescRight">Control the NAND interface power. <a href="group__nand__interface__gr.html#ga9c9975637980b5d42db7baba0191fda1">More...</a><br/></td></tr>
<tr class="separator:ga9c9975637980b5d42db7baba0191fda1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga11adcbaaace09746581a36befbd563c9"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga11adcbaaace09746581a36befbd563c9">ARM_NAND_DevicePower</a> (uint32_t voltage)</td></tr>
<tr class="memdesc:ga11adcbaaace09746581a36befbd563c9"><td class="mdescLeft"> </td><td class="mdescRight">Set device power supply voltage. <a href="group__nand__interface__gr.html#ga11adcbaaace09746581a36befbd563c9">More...</a><br/></td></tr>
<tr class="separator:ga11adcbaaace09746581a36befbd563c9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1987e65a4e756d748db86332c9fb1cec"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1987e65a4e756d748db86332c9fb1cec">ARM_NAND_WriteProtect</a> (uint32_t dev_num, bool enable)</td></tr>
<tr class="memdesc:ga1987e65a4e756d748db86332c9fb1cec"><td class="mdescLeft"> </td><td class="mdescRight">Control WPn (Write Protect). <a href="group__nand__interface__gr.html#ga1987e65a4e756d748db86332c9fb1cec">More...</a><br/></td></tr>
<tr class="separator:ga1987e65a4e756d748db86332c9fb1cec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1c0cba87cb7b706ad5986dc67c831ad1">ARM_NAND_ChipEnable</a> (uint32_t dev_num, bool enable)</td></tr>
<tr class="memdesc:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="mdescLeft"> </td><td class="mdescRight">Control CEn (Chip Enable). <a href="group__nand__interface__gr.html#ga1c0cba87cb7b706ad5986dc67c831ad1">More...</a><br/></td></tr>
<tr class="separator:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga43011066306bd716b580e6aa9a80cf65"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga43011066306bd716b580e6aa9a80cf65">ARM_NAND_GetDeviceBusy</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga43011066306bd716b580e6aa9a80cf65"><td class="mdescLeft"> </td><td class="mdescRight">Get Device Busy pin state. <a href="group__nand__interface__gr.html#ga43011066306bd716b580e6aa9a80cf65">More...</a><br/></td></tr>
<tr class="separator:ga43011066306bd716b580e6aa9a80cf65"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9f70b89ba478eadfe7f5dee7453a4fb7">ARM_NAND_SendCommand</a> (uint32_t dev_num, uint8_t cmd)</td></tr>
<tr class="memdesc:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="mdescLeft"> </td><td class="mdescRight">Send command to NAND device. <a href="group__nand__interface__gr.html#ga9f70b89ba478eadfe7f5dee7453a4fb7">More...</a><br/></td></tr>
<tr class="separator:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga00e195031e03d364db7595858a7e76f3"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga00e195031e03d364db7595858a7e76f3">ARM_NAND_SendAddress</a> (uint32_t dev_num, uint8_t addr)</td></tr>
<tr class="memdesc:ga00e195031e03d364db7595858a7e76f3"><td class="mdescLeft"> </td><td class="mdescRight">Send address to NAND device. <a href="group__nand__interface__gr.html#ga00e195031e03d364db7595858a7e76f3">More...</a><br/></td></tr>
<tr class="separator:ga00e195031e03d364db7595858a7e76f3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae1899a20ef107400c8bf84fad477a8ce"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gae1899a20ef107400c8bf84fad477a8ce">ARM_NAND_ReadData</a> (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)</td></tr>
<tr class="memdesc:gae1899a20ef107400c8bf84fad477a8ce"><td class="mdescLeft"> </td><td class="mdescRight">Read data from NAND device. <a href="group__nand__interface__gr.html#gae1899a20ef107400c8bf84fad477a8ce">More...</a><br/></td></tr>
<tr class="separator:gae1899a20ef107400c8bf84fad477a8ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1fa497dd51a86fc308e946b4419fd006"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1fa497dd51a86fc308e946b4419fd006">ARM_NAND_WriteData</a> (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)</td></tr>
<tr class="memdesc:ga1fa497dd51a86fc308e946b4419fd006"><td class="mdescLeft"> </td><td class="mdescRight">Write data to NAND device. <a href="group__nand__interface__gr.html#ga1fa497dd51a86fc308e946b4419fd006">More...</a><br/></td></tr>
<tr class="separator:ga1fa497dd51a86fc308e946b4419fd006"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a0108dba757a4610475151144b52825"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga8a0108dba757a4610475151144b52825">ARM_NAND_ExecuteSequence</a> (uint32_t dev_num, uint32_t code, uint32_t cmd, uint32_t addr_col, uint32_t addr_row, void *data, uint32_t data_cnt, uint8_t *status, uint32_t *count)</td></tr>
<tr class="memdesc:ga8a0108dba757a4610475151144b52825"><td class="mdescLeft"> </td><td class="mdescRight">Execute sequence of operations. <a href="group__nand__interface__gr.html#ga8a0108dba757a4610475151144b52825">More...</a><br/></td></tr>
<tr class="separator:ga8a0108dba757a4610475151144b52825"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga00832861f018db0d8368900b099ecd30"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga00832861f018db0d8368900b099ecd30">ARM_NAND_AbortSequence</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga00832861f018db0d8368900b099ecd30"><td class="mdescLeft"> </td><td class="mdescRight">Abort sequence execution. <a href="group__nand__interface__gr.html#ga00832861f018db0d8368900b099ecd30">More...</a><br/></td></tr>
<tr class="separator:ga00832861f018db0d8368900b099ecd30"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga83061d6d53ffb148853efbc87a864607"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> (uint32_t dev_num, uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:ga83061d6d53ffb148853efbc87a864607"><td class="mdescLeft"> </td><td class="mdescRight">Control NAND Interface. <a href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">More...</a><br/></td></tr>
<tr class="separator:ga83061d6d53ffb148853efbc87a864607"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4578642f37a556b58b0bba0ad5d42641"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__STATUS">ARM_NAND_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga4578642f37a556b58b0bba0ad5d42641">ARM_NAND_GetStatus</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga4578642f37a556b58b0bba0ad5d42641"><td class="mdescLeft"> </td><td class="mdescRight">Get NAND status. <a href="group__nand__interface__gr.html#ga4578642f37a556b58b0bba0ad5d42641">More...</a><br/></td></tr>
<tr class="separator:ga4578642f37a556b58b0bba0ad5d42641"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac21425454d586ef48fdfc35e7bd78947"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gac21425454d586ef48fdfc35e7bd78947">ARM_NAND_InquireECC</a> (int32_t index, <a class="el" href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">ARM_NAND_ECC_INFO</a> *info)</td></tr>
<tr class="memdesc:gac21425454d586ef48fdfc35e7bd78947"><td class="mdescLeft"> </td><td class="mdescRight">Inquire about available ECC. <a href="group__nand__interface__gr.html#gac21425454d586ef48fdfc35e7bd78947">More...</a><br/></td></tr>
<tr class="separator:gac21425454d586ef48fdfc35e7bd78947"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf4ce80b0fd6717de7ddfb1cfaf7dd754"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">ARM_NAND_SignalEvent</a> (uint32_t dev_num, uint32_t event)</td></tr>
<tr class="memdesc:gaf4ce80b0fd6717de7ddfb1cfaf7dd754"><td class="mdescLeft"> </td><td class="mdescRight">Signal NAND event. <a href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">More...</a><br/></td></tr>
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<a href="#nested-classes">Data Structures</a> |
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<div class="title">Driver_NAND.h File Reference</div> </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:structARM__NAND__ECC__INFO"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">ARM_NAND_ECC_INFO</a></td></tr>
<tr class="memdesc:structARM__NAND__ECC__INFO"><td class="mdescLeft"> </td><td class="mdescRight">NAND ECC (Error Correction Code) Information. <a href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">More...</a><br/></td></tr>
<tr class="separator:structARM__NAND__ECC__INFO"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:structARM__NAND__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__STATUS">ARM_NAND_STATUS</a></td></tr>
<tr class="memdesc:structARM__NAND__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">NAND Status. <a href="group__nand__interface__gr.html#structARM__NAND__STATUS">More...</a><br/></td></tr>
<tr class="separator:structARM__NAND__STATUS"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:structARM__NAND__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">ARM_NAND_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__NAND__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">NAND Driver Capabilities. <a href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__NAND"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__DRIVER__NAND">ARM_DRIVER_NAND</a></td></tr>
<tr class="memdesc:structARM__DRIVER__NAND"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the NAND Driver. <a href="group__nand__interface__gr.html#structARM__DRIVER__NAND">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a121ff96c31275cef4bb7e86007665e1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a121ff96c31275cef4bb7e86007665e1c">ARM_NAND_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td></tr>
<tr class="separator:a121ff96c31275cef4bb7e86007665e1c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a848a27ec9ebf0a13a82a1d9760f39d90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a848a27ec9ebf0a13a82a1d9760f39d90">ARM_NAND_POWER_VCC_Pos</a>   0</td></tr>
<tr class="separator:a848a27ec9ebf0a13a82a1d9760f39d90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad898ef5cd4ffe3b6b09d69e224aa0912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad898ef5cd4ffe3b6b09d69e224aa0912">ARM_NAND_POWER_VCC_Msk</a>   (0x07UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
<tr class="separator:ad898ef5cd4ffe3b6b09d69e224aa0912"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a323c320a6195b78c2c79f5c6e85f02e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a323c320a6195b78c2c79f5c6e85f02e1">ARM_NAND_POWER_VCC_OFF</a>   (0x01UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
<tr class="memdesc:a323c320a6195b78c2c79f5c6e85f02e1"><td class="mdescLeft"> </td><td class="mdescRight">VCC Power off. <a href="#a323c320a6195b78c2c79f5c6e85f02e1">More...</a><br/></td></tr>
<tr class="separator:a323c320a6195b78c2c79f5c6e85f02e1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad15355d67bc239ff49cceac69c2024b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad15355d67bc239ff49cceac69c2024b3">ARM_NAND_POWER_VCC_3V3</a>   (0x02UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
<tr class="memdesc:ad15355d67bc239ff49cceac69c2024b3"><td class="mdescLeft"> </td><td class="mdescRight">VCC = 3.3V. <a href="#ad15355d67bc239ff49cceac69c2024b3">More...</a><br/></td></tr>
<tr class="separator:ad15355d67bc239ff49cceac69c2024b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa7b9d5a71125b745caba5c1d7aff6385"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa7b9d5a71125b745caba5c1d7aff6385">ARM_NAND_POWER_VCC_1V8</a>   (0x03UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
<tr class="memdesc:aa7b9d5a71125b745caba5c1d7aff6385"><td class="mdescLeft"> </td><td class="mdescRight">VCC = 1.8V. <a href="#aa7b9d5a71125b745caba5c1d7aff6385">More...</a><br/></td></tr>
<tr class="separator:aa7b9d5a71125b745caba5c1d7aff6385"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac38023b94cd8a68295d48a1019a386e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac38023b94cd8a68295d48a1019a386e0">ARM_NAND_POWER_VCCQ_Pos</a>   3</td></tr>
<tr class="separator:ac38023b94cd8a68295d48a1019a386e0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7a453227301d7c08d09b22dc8afafbe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a7a453227301d7c08d09b22dc8afafbe7">ARM_NAND_POWER_VCCQ_Msk</a>   (0x07UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
<tr class="separator:a7a453227301d7c08d09b22dc8afafbe7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aca7679e8269ee986559f4218816937c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aca7679e8269ee986559f4218816937c3">ARM_NAND_POWER_VCCQ_OFF</a>   (0x01UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:aca7679e8269ee986559f4218816937c3"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ I/O Power off. <a href="#aca7679e8269ee986559f4218816937c3">More...</a><br/></td></tr>
<tr class="separator:aca7679e8269ee986559f4218816937c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6d5a8a33a0fdaaff2e57e1ac53c984c2">ARM_NAND_POWER_VCCQ_3V3</a>   (0x02UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ = 3.3V. <a href="#a6d5a8a33a0fdaaff2e57e1ac53c984c2">More...</a><br/></td></tr>
<tr class="separator:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a653d9b4d7bee173beb49d8fec0469476"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a653d9b4d7bee173beb49d8fec0469476">ARM_NAND_POWER_VCCQ_1V8</a>   (0x03UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
<tr class="memdesc:a653d9b4d7bee173beb49d8fec0469476"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ = 1.8V. <a href="#a653d9b4d7bee173beb49d8fec0469476">More...</a><br/></td></tr>
<tr class="separator:a653d9b4d7bee173beb49d8fec0469476"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae2d278901881ffc73d3e0b48717b22f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae2d278901881ffc73d3e0b48717b22f0">ARM_NAND_POWER_VPP_OFF</a>   (1UL << 6)</td></tr>
<tr class="memdesc:ae2d278901881ffc73d3e0b48717b22f0"><td class="mdescLeft"> </td><td class="mdescRight">VPP off. <a href="#ae2d278901881ffc73d3e0b48717b22f0">More...</a><br/></td></tr>
<tr class="separator:ae2d278901881ffc73d3e0b48717b22f0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aeb0d50e30bbcd8ab59c3b78db634aad5">ARM_NAND_POWER_VPP_ON</a>   (1Ul << 7)</td></tr>
<tr class="memdesc:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="mdescLeft"> </td><td class="mdescRight">VPP on. <a href="#aeb0d50e30bbcd8ab59c3b78db634aad5">More...</a><br/></td></tr>
<tr class="separator:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a>   (0x01)</td></tr>
<tr class="memdesc:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Mode as specified with arg. <a href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">More...</a><br/></td></tr>
<tr class="separator:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2d3356f5b47871c465ae7136a2c533f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga2d3356f5b47871c465ae7136a2c533f4">ARM_NAND_BUS_DATA_WIDTH</a>   (0x02)</td></tr>
<tr class="memdesc:ga2d3356f5b47871c465ae7136a2c533f4"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Data Width as specified with arg. <a href="group__nand__control__codes.html#ga2d3356f5b47871c465ae7136a2c533f4">More...</a><br/></td></tr>
<tr class="separator:ga2d3356f5b47871c465ae7136a2c533f4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5d1d46198404fe115b013bdae7af2a2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga5d1d46198404fe115b013bdae7af2a2f">ARM_NAND_DRIVER_STRENGTH</a>   (0x03)</td></tr>
<tr class="memdesc:ga5d1d46198404fe115b013bdae7af2a2f"><td class="mdescLeft"> </td><td class="mdescRight">Set Driver Strength as specified with arg. <a href="group__nand__control__codes.html#ga5d1d46198404fe115b013bdae7af2a2f">More...</a><br/></td></tr>
<tr class="separator:ga5d1d46198404fe115b013bdae7af2a2f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1bffc9f341e704ee0e845d86a2989921"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga1bffc9f341e704ee0e845d86a2989921">ARM_NAND_DEVICE_READY_EVENT</a>   (0x04)</td></tr>
<tr class="memdesc:ga1bffc9f341e704ee0e845d86a2989921"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">ARM_NAND_EVENT_DEVICE_READY</a>; arg: 0=disabled (default), 1=enabled. <a href="group__nand__control__codes.html#ga1bffc9f341e704ee0e845d86a2989921">More...</a><br/></td></tr>
<tr class="separator:ga1bffc9f341e704ee0e845d86a2989921"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaab6dea1b565aeb53e360876a4e50783c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#gaab6dea1b565aeb53e360876a4e50783c">ARM_NAND_DRIVER_READY_EVENT</a>   (0x05)</td></tr>
<tr class="memdesc:gaab6dea1b565aeb53e360876a4e50783c"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">ARM_NAND_EVENT_DRIVER_READY</a>; arg: 0=disabled (default), 1=enabled. <a href="group__nand__control__codes.html#gaab6dea1b565aeb53e360876a4e50783c">More...</a><br/></td></tr>
<tr class="separator:gaab6dea1b565aeb53e360876a4e50783c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a372fc9b9cc1315046ceaffd6fd99e12c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>   4</td></tr>
<tr class="separator:a372fc9b9cc1315046ceaffd6fd99e12c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aea213eb1ba9c67beb6216a630d81b91f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aea213eb1ba9c67beb6216a630d81b91f">ARM_NAND_BUS_INTERFACE_Msk</a>   (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
<tr class="separator:aea213eb1ba9c67beb6216a630d81b91f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">ARM_NAND_BUS_SDR</a>   (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
<tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default) <a href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">More...</a><br/></td></tr>
<tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>   (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
<tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate) <a href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">More...</a><br/></td></tr>
<tr class="separator:ga82b8261b3d0d85881535adada318a7df"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga13c102201d6021db184a2f068656c518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">ARM_NAND_BUS_DDR2</a>   (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
<tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate) <a href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">More...</a><br/></td></tr>
<tr class="separator:ga13c102201d6021db184a2f068656c518"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acc98e42d23656734c7f9a8a5421842d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>   0</td></tr>
<tr class="separator:acc98e42d23656734c7f9a8a5421842d6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a57f6c319265b00878661656103abe660"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a57f6c319265b00878661656103abe660">ARM_NAND_BUS_TIMING_MODE_Msk</a>   (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="separator:a57f6c319265b00878661656103abe660"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga971e574ac412bbba445055e9afc384ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">ARM_NAND_BUS_TIMING_MODE_0</a>   (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 0 (default) <a href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">More...</a><br/></td></tr>
<tr class="separator:ga971e574ac412bbba445055e9afc384ba"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga475a339e929eca46e11bc8a7b330aa45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">ARM_NAND_BUS_TIMING_MODE_1</a>   (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 1. <a href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">More...</a><br/></td></tr>
<tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>   (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 2. <a href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">More...</a><br/></td></tr>
<tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>   (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 3. <a href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">More...</a><br/></td></tr>
<tr class="separator:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga709d51a5215cd23ce2d85aec57141456"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">ARM_NAND_BUS_TIMING_MODE_4</a>   (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 4 (SDR EDO capable) <a href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">More...</a><br/></td></tr>
<tr class="separator:ga709d51a5215cd23ce2d85aec57141456"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>   (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 5 (SDR EDO capable) <a href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">More...</a><br/></td></tr>
<tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>   (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only) <a href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">More...</a><br/></td></tr>
<tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>   (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
<tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only) <a href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">More...</a><br/></td></tr>
<tr class="separator:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a57b282c0818c87b79ea4f11d03cc4f3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>   8</td></tr>
<tr class="separator:a57b282c0818c87b79ea4f11d03cc4f3c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad30dfdbdc50a7ff72a5bb173c5f549dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad30dfdbdc50a7ff72a5bb173c5f549dc">ARM_NAND_BUS_DDR2_DO_WCYC_Msk</a>   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="separator:ad30dfdbdc50a7ff72a5bb173c5f549dc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">ARM_NAND_BUS_DDR2_DO_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default) <a href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">More...</a><br/></td></tr>
<tr class="separator:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">ARM_NAND_BUS_DDR2_DO_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1. <a href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">More...</a><br/></td></tr>
<tr class="separator:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">ARM_NAND_BUS_DDR2_DO_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2. <a href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">More...</a><br/></td></tr>
<tr class="separator:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">ARM_NAND_BUS_DDR2_DO_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
<tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4. <a href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">More...</a><br/></td></tr>
<tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa80b898cdf665aa14ff0e181e4ff31f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>   12</td></tr>
<tr class="separator:aa80b898cdf665aa14ff0e181e4ff31f1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad9ab38101de68a1bc186f5687f63f7c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad9ab38101de68a1bc186f5687f63f7c3">ARM_NAND_BUS_DDR2_DI_WCYC_Msk</a>   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="separator:ad9ab38101de68a1bc186f5687f63f7c3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">ARM_NAND_BUS_DDR2_DI_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default) <a href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">More...</a><br/></td></tr>
<tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1. <a href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">More...</a><br/></td></tr>
<tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2. <a href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">More...</a><br/></td></tr>
<tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
<tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4. <a href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">More...</a><br/></td></tr>
<tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>   (1UL << 16)</td></tr>
<tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable external VREFQ as reference. <a href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">More...</a><br/></td></tr>
<tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>   (1UL << 17)</td></tr>
<tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal. <a href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">More...</a><br/></td></tr>
<tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>   (1UL << 18)</td></tr>
<tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal. <a href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">More...</a><br/></td></tr>
<tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga578051cc193ae0b7125aec8007071d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__data__bus__width__codes.html#ga578051cc193ae0b7125aec8007071d21">ARM_NAND_BUS_DATA_WIDTH_8</a>   (0x00)</td></tr>
<tr class="memdesc:ga578051cc193ae0b7125aec8007071d21"><td class="mdescLeft"> </td><td class="mdescRight">Bus Data Width: 8 bit (default) <a href="group__nand__data__bus__width__codes.html#ga578051cc193ae0b7125aec8007071d21">More...</a><br/></td></tr>
<tr class="separator:ga578051cc193ae0b7125aec8007071d21"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__data__bus__width__codes.html#ga49e0e3a946a4d9f26dbd5b32ccc3b2f3">ARM_NAND_BUS_DATA_WIDTH_16</a>   (0x01)</td></tr>
<tr class="memdesc:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="mdescLeft"> </td><td class="mdescRight">Bus Data Width: 16 bit. <a href="group__nand__data__bus__width__codes.html#ga49e0e3a946a4d9f26dbd5b32ccc3b2f3">More...</a><br/></td></tr>
<tr class="separator:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga942e20df12022f3bbd0e9a558ec1c7a0">ARM_NAND_DRIVER_STRENGTH_18</a>   (0x00)</td></tr>
<tr class="memdesc:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 2.0x = 18 Ohms. <a href="group__nand__driver__strength__codes.html#ga942e20df12022f3bbd0e9a558ec1c7a0">More...</a><br/></td></tr>
<tr class="separator:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga17188e039f5f87c581033327399a057d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga17188e039f5f87c581033327399a057d">ARM_NAND_DRIVER_STRENGTH_25</a>   (0x01)</td></tr>
<tr class="memdesc:ga17188e039f5f87c581033327399a057d"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 1.4x = 25 Ohms. <a href="group__nand__driver__strength__codes.html#ga17188e039f5f87c581033327399a057d">More...</a><br/></td></tr>
<tr class="separator:ga17188e039f5f87c581033327399a057d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga33562a66a5bf328eea82b2f1893a7874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga33562a66a5bf328eea82b2f1893a7874">ARM_NAND_DRIVER_STRENGTH_35</a>   (0x02)</td></tr>
<tr class="memdesc:ga33562a66a5bf328eea82b2f1893a7874"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 1.0x = 35 Ohms (default) <a href="group__nand__driver__strength__codes.html#ga33562a66a5bf328eea82b2f1893a7874">More...</a><br/></td></tr>
<tr class="separator:ga33562a66a5bf328eea82b2f1893a7874"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa502e2c995447037d266f939faa43223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#gaa502e2c995447037d266f939faa43223">ARM_NAND_DRIVER_STRENGTH_50</a>   (0x03)</td></tr>
<tr class="memdesc:gaa502e2c995447037d266f939faa43223"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 0.7x = 50 Ohms. <a href="group__nand__driver__strength__codes.html#gaa502e2c995447037d266f939faa43223">More...</a><br/></td></tr>
<tr class="separator:gaa502e2c995447037d266f939faa43223"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7944be4f63c439d5d64053ad9476407b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a7944be4f63c439d5d64053ad9476407b">ARM_NAND_ECC_INDEX_Pos</a>   0</td></tr>
<tr class="separator:a7944be4f63c439d5d64053ad9476407b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a656537439264ab495c86e4c36051a3c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a656537439264ab495c86e4c36051a3c1">ARM_NAND_ECC_INDEX_Msk</a>   (0xFFUL << ARM_NAND_ECC_INDEX_Pos)</td></tr>
<tr class="separator:a656537439264ab495c86e4c36051a3c1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac2eb4475f12a443209165d29fe200030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#gac2eb4475f12a443209165d29fe200030">ARM_NAND_ECC</a>(n)   ((n) & <a class="el" href="Driver__NAND_8h.html#a656537439264ab495c86e4c36051a3c1">ARM_NAND_ECC_INDEX_Msk</a>)</td></tr>
<tr class="memdesc:gac2eb4475f12a443209165d29fe200030"><td class="mdescLeft"> </td><td class="mdescRight">Select ECC. <a href="group__nand__driver__ecc__codes.html#gac2eb4475f12a443209165d29fe200030">More...</a><br/></td></tr>
<tr class="separator:gac2eb4475f12a443209165d29fe200030"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga15c79a12200c16f953936635f930df1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#ga15c79a12200c16f953936635f930df1d">ARM_NAND_ECC0</a>   (1UL << 8)</td></tr>
<tr class="memdesc:ga15c79a12200c16f953936635f930df1d"><td class="mdescLeft"> </td><td class="mdescRight">Use ECC0 of selected ECC. <a href="group__nand__driver__ecc__codes.html#ga15c79a12200c16f953936635f930df1d">More...</a><br/></td></tr>
<tr class="separator:ga15c79a12200c16f953936635f930df1d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaee653288a88318ee33d1db81baa69bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#gaee653288a88318ee33d1db81baa69bbc">ARM_NAND_ECC1</a>   (1UL << 9)</td></tr>
<tr class="memdesc:gaee653288a88318ee33d1db81baa69bbc"><td class="mdescLeft"> </td><td class="mdescRight">Use ECC1 of selected ECC. <a href="group__nand__driver__ecc__codes.html#gaee653288a88318ee33d1db81baa69bbc">More...</a><br/></td></tr>
<tr class="separator:gaee653288a88318ee33d1db81baa69bbc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf40631ba62411e0ac06c3a945d608581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__flag__codes.html#gaf40631ba62411e0ac06c3a945d608581">ARM_NAND_DRIVER_DONE_EVENT</a>   (1UL << 16)</td></tr>
<tr class="memdesc:gaf40631ba62411e0ac06c3a945d608581"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">ARM_NAND_EVENT_DRIVER_DONE</a>. <a href="group__nand__driver__flag__codes.html#gaf40631ba62411e0ac06c3a945d608581">More...</a><br/></td></tr>
<tr class="separator:gaf40631ba62411e0ac06c3a945d608581"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaef90c96cd4f2309044d7d438c6b0930a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gaef90c96cd4f2309044d7d438c6b0930a">ARM_NAND_CODE_SEND_CMD1</a>   (1UL << 17)</td></tr>
<tr class="memdesc:gaef90c96cd4f2309044d7d438c6b0930a"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 1. <a href="group__nand__driver__seq__exec__codes.html#gaef90c96cd4f2309044d7d438c6b0930a">More...</a><br/></td></tr>
<tr class="separator:gaef90c96cd4f2309044d7d438c6b0930a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga891bcba60ebb1195ec80c00c9bec748a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga891bcba60ebb1195ec80c00c9bec748a">ARM_NAND_CODE_SEND_ADDR_COL1</a>   (1UL << 18)</td></tr>
<tr class="memdesc:ga891bcba60ebb1195ec80c00c9bec748a"><td class="mdescLeft"> </td><td class="mdescRight">Send Column Address 1. <a href="group__nand__driver__seq__exec__codes.html#ga891bcba60ebb1195ec80c00c9bec748a">More...</a><br/></td></tr>
<tr class="separator:ga891bcba60ebb1195ec80c00c9bec748a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga62a3f6ddcfb9ee317655bbec9e09bc10">ARM_NAND_CODE_SEND_ADDR_COL2</a>   (1UL << 19)</td></tr>
<tr class="memdesc:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="mdescLeft"> </td><td class="mdescRight">Send Column Address 2. <a href="group__nand__driver__seq__exec__codes.html#ga62a3f6ddcfb9ee317655bbec9e09bc10">More...</a><br/></td></tr>
<tr class="separator:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadc001e69d1e81dc28a542237c6fe11ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gadc001e69d1e81dc28a542237c6fe11ff">ARM_NAND_CODE_SEND_ADDR_ROW1</a>   (1UL << 20)</td></tr>
<tr class="memdesc:gadc001e69d1e81dc28a542237c6fe11ff"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 1. <a href="group__nand__driver__seq__exec__codes.html#gadc001e69d1e81dc28a542237c6fe11ff">More...</a><br/></td></tr>
<tr class="separator:gadc001e69d1e81dc28a542237c6fe11ff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga5e55628cb59f5d7d35c529f04ebfcd10">ARM_NAND_CODE_SEND_ADDR_ROW2</a>   (1UL << 21)</td></tr>
<tr class="memdesc:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 2. <a href="group__nand__driver__seq__exec__codes.html#ga5e55628cb59f5d7d35c529f04ebfcd10">More...</a><br/></td></tr>
<tr class="separator:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gaeb5d1be9c13b7ad2ad246d5db10cd419">ARM_NAND_CODE_SEND_ADDR_ROW3</a>   (1UL << 22)</td></tr>
<tr class="memdesc:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 3. <a href="group__nand__driver__seq__exec__codes.html#gaeb5d1be9c13b7ad2ad246d5db10cd419">More...</a><br/></td></tr>
<tr class="separator:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga959522c98183036da32984dd5e07979b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga959522c98183036da32984dd5e07979b">ARM_NAND_CODE_INC_ADDR_ROW</a>   (1UL << 23)</td></tr>
<tr class="memdesc:ga959522c98183036da32984dd5e07979b"><td class="mdescLeft"> </td><td class="mdescRight">Auto-increment Row Address. <a href="group__nand__driver__seq__exec__codes.html#ga959522c98183036da32984dd5e07979b">More...</a><br/></td></tr>
<tr class="separator:ga959522c98183036da32984dd5e07979b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga1b40fc5fbf22dc4fa8130f5836e30d12">ARM_NAND_CODE_WRITE_DATA</a>   (1UL << 24)</td></tr>
<tr class="memdesc:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="mdescLeft"> </td><td class="mdescRight">Write Data. <a href="group__nand__driver__seq__exec__codes.html#ga1b40fc5fbf22dc4fa8130f5836e30d12">More...</a><br/></td></tr>
<tr class="separator:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gacffafbbbca74f7ffa4cd3bb6b067c4ef">ARM_NAND_CODE_SEND_CMD2</a>   (1UL << 25)</td></tr>
<tr class="memdesc:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 2. <a href="group__nand__driver__seq__exec__codes.html#gacffafbbbca74f7ffa4cd3bb6b067c4ef">More...</a><br/></td></tr>
<tr class="separator:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0f4a8b1e97656e09f1c383852f290a37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga0f4a8b1e97656e09f1c383852f290a37">ARM_NAND_CODE_WAIT_BUSY</a>   (1UL << 26)</td></tr>
<tr class="memdesc:ga0f4a8b1e97656e09f1c383852f290a37"><td class="mdescLeft"> </td><td class="mdescRight">Wait while R/Bn busy. <a href="group__nand__driver__seq__exec__codes.html#ga0f4a8b1e97656e09f1c383852f290a37">More...</a><br/></td></tr>
<tr class="separator:ga0f4a8b1e97656e09f1c383852f290a37"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab524d840ab57c720ce8560144651dc9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gab524d840ab57c720ce8560144651dc9d">ARM_NAND_CODE_READ_DATA</a>   (1UL << 27)</td></tr>
<tr class="memdesc:gab524d840ab57c720ce8560144651dc9d"><td class="mdescLeft"> </td><td class="mdescRight">Read Data. <a href="group__nand__driver__seq__exec__codes.html#gab524d840ab57c720ce8560144651dc9d">More...</a><br/></td></tr>
<tr class="separator:gab524d840ab57c720ce8560144651dc9d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga20f96743ab77bda14ba391dc0c3cdba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga20f96743ab77bda14ba391dc0c3cdba5">ARM_NAND_CODE_SEND_CMD3</a>   (1UL << 28)</td></tr>
<tr class="memdesc:ga20f96743ab77bda14ba391dc0c3cdba5"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 3. <a href="group__nand__driver__seq__exec__codes.html#ga20f96743ab77bda14ba391dc0c3cdba5">More...</a><br/></td></tr>
<tr class="separator:ga20f96743ab77bda14ba391dc0c3cdba5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2250f6a532d2c0834bfdc618761ddc86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga2250f6a532d2c0834bfdc618761ddc86">ARM_NAND_CODE_READ_STATUS</a>   (1UL << 29)</td></tr>
<tr class="memdesc:ga2250f6a532d2c0834bfdc618761ddc86"><td class="mdescLeft"> </td><td class="mdescRight">Read Status byte and check FAIL bit (bit 0) <a href="group__nand__driver__seq__exec__codes.html#ga2250f6a532d2c0834bfdc618761ddc86">More...</a><br/></td></tr>
<tr class="separator:ga2250f6a532d2c0834bfdc618761ddc86"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae34722cf52938f50bf117780a742b6f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae34722cf52938f50bf117780a742b6f1">ARM_NAND_CODE_CMD1_Pos</a>   0</td></tr>
<tr class="separator:ae34722cf52938f50bf117780a742b6f1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac65db62329bb943592afdb523e4aadca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac65db62329bb943592afdb523e4aadca">ARM_NAND_CODE_CMD1_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD1_Pos)</td></tr>
<tr class="separator:ac65db62329bb943592afdb523e4aadca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aeebe274650e7d0c02b478318759972e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aeebe274650e7d0c02b478318759972e5">ARM_NAND_CODE_CMD2_Pos</a>   8</td></tr>
<tr class="separator:aeebe274650e7d0c02b478318759972e5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0f963016c81be2ddf7a09d983de226a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a0f963016c81be2ddf7a09d983de226a9">ARM_NAND_CODE_CMD2_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD2_Pos)</td></tr>
<tr class="separator:a0f963016c81be2ddf7a09d983de226a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa0b87b819cf3c94f32e3ef18dcfd1c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa0b87b819cf3c94f32e3ef18dcfd1c6c">ARM_NAND_CODE_CMD3_Pos</a>   16</td></tr>
<tr class="separator:aa0b87b819cf3c94f32e3ef18dcfd1c6c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a16d474e55d0f6ea6efc3cc5436493b22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a16d474e55d0f6ea6efc3cc5436493b22">ARM_NAND_CODE_CMD3_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD3_Pos)</td></tr>
<tr class="separator:a16d474e55d0f6ea6efc3cc5436493b22"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab8b06772e2b6c5930319b17bbb806133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ab8b06772e2b6c5930319b17bbb806133">ARM_NAND_CODE_ADDR_COL1_Pos</a>   0</td></tr>
<tr class="separator:ab8b06772e2b6c5930319b17bbb806133"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0951de69f3836c1ab229ec60b3996fcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a0951de69f3836c1ab229ec60b3996fcc">ARM_NAND_CODE_ADDR_COL1_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)</td></tr>
<tr class="separator:a0951de69f3836c1ab229ec60b3996fcc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1c4b9e7f44f77ebf665af8860a3c7528"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a1c4b9e7f44f77ebf665af8860a3c7528">ARM_NAND_CODE_ADDR_COL2_Pos</a>   8</td></tr>
<tr class="separator:a1c4b9e7f44f77ebf665af8860a3c7528"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6126261e7c53713cee04aeae839d330e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6126261e7c53713cee04aeae839d330e">ARM_NAND_CODE_ADDR_COL2_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)</td></tr>
<tr class="separator:a6126261e7c53713cee04aeae839d330e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8b75efa00810fcf23fb0f12e7f62d338"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a8b75efa00810fcf23fb0f12e7f62d338">ARM_NAND_CODE_ADDR_ROW1_Pos</a>   0</td></tr>
<tr class="separator:a8b75efa00810fcf23fb0f12e7f62d338"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac24600be47e725ab1ad4193fd84daf80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac24600be47e725ab1ad4193fd84daf80">ARM_NAND_CODE_ADDR_ROW1_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)</td></tr>
<tr class="separator:ac24600be47e725ab1ad4193fd84daf80"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a326e135c57b38c78ae88cea121722a30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a326e135c57b38c78ae88cea121722a30">ARM_NAND_CODE_ADDR_ROW2_Pos</a>   8</td></tr>
<tr class="separator:a326e135c57b38c78ae88cea121722a30"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae17a3f9b9fd70a88f9f9f38dd2c17951"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae17a3f9b9fd70a88f9f9f38dd2c17951">ARM_NAND_CODE_ADDR_ROW2_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)</td></tr>
<tr class="separator:ae17a3f9b9fd70a88f9f9f38dd2c17951"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6873f7aedfe81efa8ca21dc85cbb384c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6873f7aedfe81efa8ca21dc85cbb384c">ARM_NAND_CODE_ADDR_ROW3_Pos</a>   16</td></tr>
<tr class="separator:a6873f7aedfe81efa8ca21dc85cbb384c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acf1ecacc2b225877c9cfe4f15dafc03c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#acf1ecacc2b225877c9cfe4f15dafc03c">ARM_NAND_CODE_ADDR_ROW3_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)</td></tr>
<tr class="separator:acf1ecacc2b225877c9cfe4f15dafc03c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafebec6ac091750a47b1d59bc843c15b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__execution__status.html#gafebec6ac091750a47b1d59bc843c15b0">ARM_NAND_ERROR_ECC</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td></tr>
<tr class="memdesc:gafebec6ac091750a47b1d59bc843c15b0"><td class="mdescLeft"> </td><td class="mdescRight">ECC generation/correction failed. <a href="group__nand__execution__status.html#gafebec6ac091750a47b1d59bc843c15b0">More...</a><br/></td></tr>
<tr class="separator:gafebec6ac091750a47b1d59bc843c15b0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0be7e1b41188def905de0a1568d442d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">ARM_NAND_EVENT_DEVICE_READY</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gae0be7e1b41188def905de0a1568d442d"><td class="mdescLeft"> </td><td class="mdescRight">Device Ready: R/Bn rising edge. <a href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">More...</a><br/></td></tr>
<tr class="separator:gae0be7e1b41188def905de0a1568d442d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">ARM_NAND_EVENT_DRIVER_READY</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="mdescLeft"> </td><td class="mdescRight">Driver Ready. <a href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">More...</a><br/></td></tr>
<tr class="separator:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac774a334871789d24107b843d1ebd00c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">ARM_NAND_EVENT_DRIVER_DONE</a>   (1UL << 2)</td></tr>
<tr class="memdesc:gac774a334871789d24107b843d1ebd00c"><td class="mdescLeft"> </td><td class="mdescRight">Driver operation done. <a href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">More...</a><br/></td></tr>
<tr class="separator:gac774a334871789d24107b843d1ebd00c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7bee0c32528ab991c0c064f895f80664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#ga7bee0c32528ab991c0c064f895f80664">ARM_NAND_EVENT_ECC_ERROR</a>   (1UL << 3)</td></tr>
<tr class="memdesc:ga7bee0c32528ab991c0c064f895f80664"><td class="mdescLeft"> </td><td class="mdescRight">ECC could not correct data. <a href="group__NAND__events.html#ga7bee0c32528ab991c0c064f895f80664">More...</a><br/></td></tr>
<tr class="separator:ga7bee0c32528ab991c0c064f895f80664"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">ARM_NAND_SignalEvent_t</a> )(uint32_t dev_num, uint32_t event)</td></tr>
<tr class="memdesc:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">ARM_NAND_SignalEvent</a> : Signal NAND Event. <a href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">More...</a><br/></td></tr>
<tr class="separator:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a121ff96c31275cef4bb7e86007665e1c"></a>
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<td class="memname">#define ARM_NAND_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,3) /* API version */</td>
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<a class="anchor" id="a848a27ec9ebf0a13a82a1d9760f39d90"></a>
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<td class="memname">#define ARM_NAND_POWER_VCC_Pos   0</td>
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<td class="memname">#define ARM_NAND_POWER_VCC_Msk   (0x07UL << ARM_NAND_POWER_VCC_Pos)</td>
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<a class="anchor" id="a323c320a6195b78c2c79f5c6e85f02e1"></a>
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<td class="memname">#define ARM_NAND_POWER_VCC_OFF   (0x01UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC Power off. </p>
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<td class="memname">#define ARM_NAND_POWER_VCC_3V3   (0x02UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC = 3.3V. </p>
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<td class="memname">#define ARM_NAND_POWER_VCC_1V8   (0x03UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC = 1.8V. </p>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_Pos   3</td>
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<a class="anchor" id="a7a453227301d7c08d09b22dc8afafbe7"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_Msk   (0x07UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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</table>
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</div>
<a class="anchor" id="aca7679e8269ee986559f4218816937c3"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_OFF   (0x01UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ I/O Power off. </p>
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</div>
<a class="anchor" id="a6d5a8a33a0fdaaff2e57e1ac53c984c2"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_3V3   (0x02UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ = 3.3V. </p>
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</div>
<a class="anchor" id="a653d9b4d7bee173beb49d8fec0469476"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_1V8   (0x03UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ = 1.8V. </p>
</div>
</div>
<a class="anchor" id="ae2d278901881ffc73d3e0b48717b22f0"></a>
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<td class="memname">#define ARM_NAND_POWER_VPP_OFF   (1UL << 6)</td>
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</table>
</div><div class="memdoc">
<p>VPP off. </p>
</div>
</div>
<a class="anchor" id="aeb0d50e30bbcd8ab59c3b78db634aad5"></a>
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<td class="memname">#define ARM_NAND_POWER_VPP_ON   (1Ul << 7)</td>
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<p>VPP on. </p>
</div>
</div>
<a class="anchor" id="a372fc9b9cc1315046ceaffd6fd99e12c"></a>
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<td class="memname">#define ARM_NAND_BUS_INTERFACE_Pos   4</td>
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</div>
</div>
<a class="anchor" id="aea213eb1ba9c67beb6216a630d81b91f"></a>
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<td class="memname">#define ARM_NAND_BUS_INTERFACE_Msk   (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)</td>
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</div>
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<a class="anchor" id="acc98e42d23656734c7f9a8a5421842d6"></a>
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<td class="memname">#define ARM_NAND_BUS_TIMING_MODE_Pos   0</td>
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</div>
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<a class="anchor" id="a57f6c319265b00878661656103abe660"></a>
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<td class="memname">#define ARM_NAND_BUS_TIMING_MODE_Msk   (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)</td>
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</div>
<a class="anchor" id="a57b282c0818c87b79ea4f11d03cc4f3c"></a>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos   8</td>
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<a class="anchor" id="ad30dfdbdc50a7ff72a5bb173c5f549dc"></a>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
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</div>
<a class="anchor" id="aa80b898cdf665aa14ff0e181e4ff31f1"></a>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos   12</td>
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</div>
</div>
<a class="anchor" id="ad9ab38101de68a1bc186f5687f63f7c3"></a>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
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</div>
<a class="anchor" id="a7944be4f63c439d5d64053ad9476407b"></a>
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<td class="memname">#define ARM_NAND_ECC_INDEX_Pos   0</td>
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<a class="anchor" id="a656537439264ab495c86e4c36051a3c1"></a>
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<td class="memname">#define ARM_NAND_ECC_INDEX_Msk   (0xFFUL << ARM_NAND_ECC_INDEX_Pos)</td>
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</div>
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<a class="anchor" id="ae34722cf52938f50bf117780a742b6f1"></a>
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<td class="memname">#define ARM_NAND_CODE_CMD1_Pos   0</td>
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</div>
</div>
<a class="anchor" id="ac65db62329bb943592afdb523e4aadca"></a>
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<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_CMD1_Msk   (0xFFUL << ARM_NAND_CODE_CMD1_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aeebe274650e7d0c02b478318759972e5"></a>
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<td class="memname">#define ARM_NAND_CODE_CMD2_Pos   8</td>
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<a class="anchor" id="a0f963016c81be2ddf7a09d983de226a9"></a>
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<td class="memname">#define ARM_NAND_CODE_CMD2_Msk   (0xFFUL << ARM_NAND_CODE_CMD2_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aa0b87b819cf3c94f32e3ef18dcfd1c6c"></a>
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<td class="memname">#define ARM_NAND_CODE_CMD3_Pos   16</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a16d474e55d0f6ea6efc3cc5436493b22"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_CMD3_Msk   (0xFFUL << ARM_NAND_CODE_CMD3_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ab8b06772e2b6c5930319b17bbb806133"></a>
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL1_Pos   0</td>
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</div><div class="memdoc">
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<a class="anchor" id="a0951de69f3836c1ab229ec60b3996fcc"></a>
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<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL1_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)</td>
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</div><div class="memdoc">
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</div>
<a class="anchor" id="a1c4b9e7f44f77ebf665af8860a3c7528"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL2_Pos   8</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a6126261e7c53713cee04aeae839d330e"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL2_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a8b75efa00810fcf23fb0f12e7f62d338"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW1_Pos   0</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ac24600be47e725ab1ad4193fd84daf80"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW1_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)</td>
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</table>
</div><div class="memdoc">
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</div>
<a class="anchor" id="a326e135c57b38c78ae88cea121722a30"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW2_Pos   8</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ae17a3f9b9fd70a88f9f9f38dd2c17951"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW2_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a6873f7aedfe81efa8ca21dc85cbb384c"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW3_Pos   16</td>
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</div><div class="memdoc">
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<div class="memitem">
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW3_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)</td>
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Functions</h2></td></tr>
<tr class="memitem:ga786b1970a788a4dfc6156b42364e52f8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga786b1970a788a4dfc6156b42364e52f8">ARM_SAI_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga786b1970a788a4dfc6156b42364e52f8"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__sai__interface__gr.html#ga786b1970a788a4dfc6156b42364e52f8">More...</a><br/></td></tr>
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<tr class="memitem:gac6c636757944eaf25aebf312a67665aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sai__interface__gr.html#structARM__SAI__CAPABILITIES">ARM_SAI_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gac6c636757944eaf25aebf312a67665aa">ARM_SAI_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:gac6c636757944eaf25aebf312a67665aa"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__sai__interface__gr.html#gac6c636757944eaf25aebf312a67665aa">More...</a><br/></td></tr>
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<tr class="memitem:ga89622a02ca1e7affb1a01eefacb6f54c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga89622a02ca1e7affb1a01eefacb6f54c">ARM_SAI_Initialize</a> (<a class="el" href="group__sai__interface__gr.html#gad8ca8e2459e540928f6315b3df6da0ee">ARM_SAI_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga89622a02ca1e7affb1a01eefacb6f54c"><td class="mdescLeft"> </td><td class="mdescRight">Initialize SAI Interface. <a href="group__sai__interface__gr.html#ga89622a02ca1e7affb1a01eefacb6f54c">More...</a><br/></td></tr>
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<tr class="memitem:gabdefafaba6f072cfd7ed6f8f132422b6"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gabdefafaba6f072cfd7ed6f8f132422b6">ARM_SAI_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gabdefafaba6f072cfd7ed6f8f132422b6"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize SAI Interface. <a href="group__sai__interface__gr.html#gabdefafaba6f072cfd7ed6f8f132422b6">More...</a><br/></td></tr>
<tr class="separator:gabdefafaba6f072cfd7ed6f8f132422b6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacdec50a3dd5902de601caa7397c1dabc"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gacdec50a3dd5902de601caa7397c1dabc">ARM_SAI_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:gacdec50a3dd5902de601caa7397c1dabc"><td class="mdescLeft"> </td><td class="mdescRight">Control SAI Interface Power. <a href="group__sai__interface__gr.html#gacdec50a3dd5902de601caa7397c1dabc">More...</a><br/></td></tr>
<tr class="separator:gacdec50a3dd5902de601caa7397c1dabc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8bb6866c535adeb930bc4a847d476fcd"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga8bb6866c535adeb930bc4a847d476fcd">ARM_SAI_Send</a> (const void *data, uint32_t num)</td></tr>
<tr class="memdesc:ga8bb6866c535adeb930bc4a847d476fcd"><td class="mdescLeft"> </td><td class="mdescRight">Start sending data to SAI transmitter. <a href="group__sai__interface__gr.html#ga8bb6866c535adeb930bc4a847d476fcd">More...</a><br/></td></tr>
<tr class="separator:ga8bb6866c535adeb930bc4a847d476fcd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2d55f506cef9d2849cbe418146086d98"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga2d55f506cef9d2849cbe418146086d98">ARM_SAI_Receive</a> (void *data, uint32_t num)</td></tr>
<tr class="memdesc:ga2d55f506cef9d2849cbe418146086d98"><td class="mdescLeft"> </td><td class="mdescRight">Start receiving data from SAI receiver. <a href="group__sai__interface__gr.html#ga2d55f506cef9d2849cbe418146086d98">More...</a><br/></td></tr>
<tr class="separator:ga2d55f506cef9d2849cbe418146086d98"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa9805f9d32aee205f787e625a58e8898"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gaa9805f9d32aee205f787e625a58e8898">ARM_SAI_GetTxCount</a> (void)</td></tr>
<tr class="memdesc:gaa9805f9d32aee205f787e625a58e8898"><td class="mdescLeft"> </td><td class="mdescRight">Get transmitted data count. <a href="group__sai__interface__gr.html#gaa9805f9d32aee205f787e625a58e8898">More...</a><br/></td></tr>
<tr class="separator:gaa9805f9d32aee205f787e625a58e8898"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c571fcc8b9632c25a64043bc2b2baec"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga2c571fcc8b9632c25a64043bc2b2baec">ARM_SAI_GetRxCount</a> (void)</td></tr>
<tr class="memdesc:ga2c571fcc8b9632c25a64043bc2b2baec"><td class="mdescLeft"> </td><td class="mdescRight">Get received data count. <a href="group__sai__interface__gr.html#ga2c571fcc8b9632c25a64043bc2b2baec">More...</a><br/></td></tr>
<tr class="separator:ga2c571fcc8b9632c25a64043bc2b2baec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga405a0769c33da6801055db0fb9b6c869"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga405a0769c33da6801055db0fb9b6c869">ARM_SAI_Control</a> (uint32_t control, uint32_t arg1, uint32_t arg2)</td></tr>
<tr class="memdesc:ga405a0769c33da6801055db0fb9b6c869"><td class="mdescLeft"> </td><td class="mdescRight">Control SAI Interface. <a href="group__sai__interface__gr.html#ga405a0769c33da6801055db0fb9b6c869">More...</a><br/></td></tr>
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<tr class="memitem:ga6a202b57697f0f7a9742e76b33d5eeec"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__sai__interface__gr.html#structARM__SAI__STATUS">ARM_SAI_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#ga6a202b57697f0f7a9742e76b33d5eeec">ARM_SAI_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga6a202b57697f0f7a9742e76b33d5eeec"><td class="mdescLeft"> </td><td class="mdescRight">Get SAI status. <a href="group__sai__interface__gr.html#ga6a202b57697f0f7a9742e76b33d5eeec">More...</a><br/></td></tr>
<tr class="separator:ga6a202b57697f0f7a9742e76b33d5eeec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaedf3347cb25d6bf2faad1bbb35ad79f4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gaedf3347cb25d6bf2faad1bbb35ad79f4">ARM_SAI_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:gaedf3347cb25d6bf2faad1bbb35ad79f4"><td class="mdescLeft"> </td><td class="mdescRight">Signal SAI Events. <a href="group__sai__interface__gr.html#gaedf3347cb25d6bf2faad1bbb35ad79f4">More...</a><br/></td></tr>
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<div class="title">Driver_SAI.h File Reference</div> </div>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__SAI__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#structARM__SAI__STATUS">ARM_SAI_STATUS</a></td></tr>
<tr class="memdesc:structARM__SAI__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">SAI Status. <a href="group__sai__interface__gr.html#structARM__SAI__STATUS">More...</a><br/></td></tr>
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<tr class="memitem:structARM__SAI__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#structARM__SAI__CAPABILITIES">ARM_SAI_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__SAI__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">SAI Driver Capabilities. <a href="group__sai__interface__gr.html#structARM__SAI__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__SAI"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#structARM__DRIVER__SAI">ARM_DRIVER_SAI</a></td></tr>
<tr class="memdesc:structARM__DRIVER__SAI"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the SAI Driver. <a href="group__sai__interface__gr.html#structARM__DRIVER__SAI">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:a228007626e6f533b7a86a85e73e74d1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a228007626e6f533b7a86a85e73e74d1e">ARM_SAI_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(1,1) /* API version */</td></tr>
<tr class="separator:a228007626e6f533b7a86a85e73e74d1e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abe35f330af97ad488b28f580f7105b27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#abe35f330af97ad488b28f580f7105b27">ARM_SAI_CONTROL_Msk</a>   (0xFFU)</td></tr>
<tr class="separator:abe35f330af97ad488b28f580f7105b27"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga14ac7775060e731b26bc5b3acd2f317a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#ga14ac7775060e731b26bc5b3acd2f317a">ARM_SAI_CONFIGURE_TX</a>   (0x01U)</td></tr>
<tr class="memdesc:ga14ac7775060e731b26bc5b3acd2f317a"><td class="mdescLeft"> </td><td class="mdescRight">Configure Transmitter; arg1 and arg2 provide additional configuration. <a href="group__sai__controls.html#ga14ac7775060e731b26bc5b3acd2f317a">More...</a><br/></td></tr>
<tr class="separator:ga14ac7775060e731b26bc5b3acd2f317a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba3e824e022fe2a5736de5dcbbd3d291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#gaba3e824e022fe2a5736de5dcbbd3d291">ARM_SAI_CONFIGURE_RX</a>   (0x02U)</td></tr>
<tr class="memdesc:gaba3e824e022fe2a5736de5dcbbd3d291"><td class="mdescLeft"> </td><td class="mdescRight">Configure Receiver; arg1 and arg2 provide additional configuration. <a href="group__sai__controls.html#gaba3e824e022fe2a5736de5dcbbd3d291">More...</a><br/></td></tr>
<tr class="separator:gaba3e824e022fe2a5736de5dcbbd3d291"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga74d7850973c095bb8dbffa880b4af1bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#ga74d7850973c095bb8dbffa880b4af1bc">ARM_SAI_CONTROL_TX</a>   (0x03U)</td></tr>
<tr class="memdesc:ga74d7850973c095bb8dbffa880b4af1bc"><td class="mdescLeft"> </td><td class="mdescRight">Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute. <a href="group__sai__controls.html#ga74d7850973c095bb8dbffa880b4af1bc">More...</a><br/></td></tr>
<tr class="separator:ga74d7850973c095bb8dbffa880b4af1bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa40390b6dd0df3b140fdc45bb7b1439d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#gaa40390b6dd0df3b140fdc45bb7b1439d">ARM_SAI_CONTROL_RX</a>   (0x04U)</td></tr>
<tr class="memdesc:gaa40390b6dd0df3b140fdc45bb7b1439d"><td class="mdescLeft"> </td><td class="mdescRight">Control Receiver; arg1.0: 0=disable (default), 1=enable. <a href="group__sai__controls.html#gaa40390b6dd0df3b140fdc45bb7b1439d">More...</a><br/></td></tr>
<tr class="separator:gaa40390b6dd0df3b140fdc45bb7b1439d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8675b9776189caf4df7d558b3e18fcba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#ga8675b9776189caf4df7d558b3e18fcba">ARM_SAI_MASK_SLOTS_TX</a>   (0x05U)</td></tr>
<tr class="memdesc:ga8675b9776189caf4df7d558b3e18fcba"><td class="mdescLeft"> </td><td class="mdescRight">Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default. <a href="group__sai__controls.html#ga8675b9776189caf4df7d558b3e18fcba">More...</a><br/></td></tr>
<tr class="separator:ga8675b9776189caf4df7d558b3e18fcba"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga84302d372185665852c9ed941c6545e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#ga84302d372185665852c9ed941c6545e0">ARM_SAI_MASK_SLOTS_RX</a>   (0x06U)</td></tr>
<tr class="memdesc:ga84302d372185665852c9ed941c6545e0"><td class="mdescLeft"> </td><td class="mdescRight">Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default. <a href="group__sai__controls.html#ga84302d372185665852c9ed941c6545e0">More...</a><br/></td></tr>
<tr class="separator:ga84302d372185665852c9ed941c6545e0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab3ec8ef9e5e5a190bd2131ac8c99a240"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#gab3ec8ef9e5e5a190bd2131ac8c99a240">ARM_SAI_ABORT_SEND</a>   (0x07U)</td></tr>
<tr class="memdesc:gab3ec8ef9e5e5a190bd2131ac8c99a240"><td class="mdescLeft"> </td><td class="mdescRight">Abort <a class="el" href="group__sai__interface__gr.html#ga8bb6866c535adeb930bc4a847d476fcd">ARM_SAI_Send</a>. <a href="group__sai__controls.html#gab3ec8ef9e5e5a190bd2131ac8c99a240">More...</a><br/></td></tr>
<tr class="separator:gab3ec8ef9e5e5a190bd2131ac8c99a240"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2b8d3d85c1e60f137f8c433f319244cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__controls.html#ga2b8d3d85c1e60f137f8c433f319244cb">ARM_SAI_ABORT_RECEIVE</a>   (0x08U)</td></tr>
<tr class="memdesc:ga2b8d3d85c1e60f137f8c433f319244cb"><td class="mdescLeft"> </td><td class="mdescRight">Abort <a class="el" href="group__sai__interface__gr.html#ga2d55f506cef9d2849cbe418146086d98">ARM_SAI_Receive</a>. <a href="group__sai__controls.html#ga2b8d3d85c1e60f137f8c433f319244cb">More...</a><br/></td></tr>
<tr class="separator:ga2b8d3d85c1e60f137f8c433f319244cb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8779654f638207bcee1b86a508b3a486"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a8779654f638207bcee1b86a508b3a486">ARM_SAI_MODE_Pos</a>   8</td></tr>
<tr class="separator:a8779654f638207bcee1b86a508b3a486"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae949aad131ef68cde3190e3ab772f5bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#ae949aad131ef68cde3190e3ab772f5bc">ARM_SAI_MODE_Msk</a>   (1U << ARM_SAI_MODE_Pos)</td></tr>
<tr class="separator:ae949aad131ef68cde3190e3ab772f5bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5bedff714ea0f90139665b72d44daddc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mode__control.html#ga5bedff714ea0f90139665b72d44daddc">ARM_SAI_MODE_MASTER</a>   (1U << ARM_SAI_MODE_Pos)</td></tr>
<tr class="memdesc:ga5bedff714ea0f90139665b72d44daddc"><td class="mdescLeft"> </td><td class="mdescRight">Master Mode. <a href="group__sai__mode__control.html#ga5bedff714ea0f90139665b72d44daddc">More...</a><br/></td></tr>
<tr class="separator:ga5bedff714ea0f90139665b72d44daddc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5956c12a24a506754ecc7999f0660bb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mode__control.html#ga5956c12a24a506754ecc7999f0660bb5">ARM_SAI_MODE_SLAVE</a>   (0U << ARM_SAI_MODE_Pos)</td></tr>
<tr class="memdesc:ga5956c12a24a506754ecc7999f0660bb5"><td class="mdescLeft"> </td><td class="mdescRight">Slave Mode (default) <a href="group__sai__mode__control.html#ga5956c12a24a506754ecc7999f0660bb5">More...</a><br/></td></tr>
<tr class="separator:ga5956c12a24a506754ecc7999f0660bb5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a07e9aff784158ff76feab30b9c1b39ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a07e9aff784158ff76feab30b9c1b39ec">ARM_SAI_SYNCHRONIZATION_Pos</a>   9</td></tr>
<tr class="separator:a07e9aff784158ff76feab30b9c1b39ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a42244bcaa347e43405cc356c00458c2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a42244bcaa347e43405cc356c00458c2e">ARM_SAI_SYNCHRONIZATION_Msk</a>   (1U << ARM_SAI_SYNCHRONIZATION_Pos)</td></tr>
<tr class="separator:a42244bcaa347e43405cc356c00458c2e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad123537cb6ab9eefd6feab193ed74655"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__sync__control.html#gad123537cb6ab9eefd6feab193ed74655">ARM_SAI_ASYNCHRONOUS</a>   (0U << ARM_SAI_SYNCHRONIZATION_Pos)</td></tr>
<tr class="memdesc:gad123537cb6ab9eefd6feab193ed74655"><td class="mdescLeft"> </td><td class="mdescRight">Asynchronous (default) <a href="group__sai__sync__control.html#gad123537cb6ab9eefd6feab193ed74655">More...</a><br/></td></tr>
<tr class="separator:gad123537cb6ab9eefd6feab193ed74655"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad2ad5406c30c353e80f54b40b3de5db8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__sync__control.html#gad2ad5406c30c353e80f54b40b3de5db8">ARM_SAI_SYNCHRONOUS</a>   (1U << ARM_SAI_SYNCHRONIZATION_Pos)</td></tr>
<tr class="memdesc:gad2ad5406c30c353e80f54b40b3de5db8"><td class="mdescLeft"> </td><td class="mdescRight">Synchronous. <a href="group__sai__sync__control.html#gad2ad5406c30c353e80f54b40b3de5db8">More...</a><br/></td></tr>
<tr class="separator:gad2ad5406c30c353e80f54b40b3de5db8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9d46c20d74fc28cd23c61efec5d7e264"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a9d46c20d74fc28cd23c61efec5d7e264">ARM_SAI_PROTOCOL_Pos</a>   10</td></tr>
<tr class="separator:a9d46c20d74fc28cd23c61efec5d7e264"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aff67558883dcbaaed0feb28ddb5104a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#aff67558883dcbaaed0feb28ddb5104a9">ARM_SAI_PROTOCOL_Msk</a>   (7U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="separator:aff67558883dcbaaed0feb28ddb5104a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacef87941052c21ebacd3dde6ce9d6925"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#gacef87941052c21ebacd3dde6ce9d6925">ARM_SAI_PROTOCOL_USER</a>   (0U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:gacef87941052c21ebacd3dde6ce9d6925"><td class="mdescLeft"> </td><td class="mdescRight">User defined (default) <a href="group__sai__protocol__control.html#gacef87941052c21ebacd3dde6ce9d6925">More...</a><br/></td></tr>
<tr class="separator:gacef87941052c21ebacd3dde6ce9d6925"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaaf423bbe59920b3c7813e22ce083ddc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#gaaaf423bbe59920b3c7813e22ce083ddc">ARM_SAI_PROTOCOL_I2S</a>   (1U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:gaaaf423bbe59920b3c7813e22ce083ddc"><td class="mdescLeft"> </td><td class="mdescRight">I2S. <a href="group__sai__protocol__control.html#gaaaf423bbe59920b3c7813e22ce083ddc">More...</a><br/></td></tr>
<tr class="separator:gaaaf423bbe59920b3c7813e22ce083ddc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad931f9e8aedff4e6040d726d707862f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#gad931f9e8aedff4e6040d726d707862f0">ARM_SAI_PROTOCOL_MSB_JUSTIFIED</a>   (2U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:gad931f9e8aedff4e6040d726d707862f0"><td class="mdescLeft"> </td><td class="mdescRight">MSB (left) justified. <a href="group__sai__protocol__control.html#gad931f9e8aedff4e6040d726d707862f0">More...</a><br/></td></tr>
<tr class="separator:gad931f9e8aedff4e6040d726d707862f0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab88b6f9b61a20927ac8f8d39e46c6349"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#gab88b6f9b61a20927ac8f8d39e46c6349">ARM_SAI_PROTOCOL_LSB_JUSTIFIED</a>   (3U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:gab88b6f9b61a20927ac8f8d39e46c6349"><td class="mdescLeft"> </td><td class="mdescRight">LSB (right) justified. <a href="group__sai__protocol__control.html#gab88b6f9b61a20927ac8f8d39e46c6349">More...</a><br/></td></tr>
<tr class="separator:gab88b6f9b61a20927ac8f8d39e46c6349"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3762437e0b1402b5d4fd293ae745f103"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#ga3762437e0b1402b5d4fd293ae745f103">ARM_SAI_PROTOCOL_PCM_SHORT</a>   (4U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:ga3762437e0b1402b5d4fd293ae745f103"><td class="mdescLeft"> </td><td class="mdescRight">PCM with short frame. <a href="group__sai__protocol__control.html#ga3762437e0b1402b5d4fd293ae745f103">More...</a><br/></td></tr>
<tr class="separator:ga3762437e0b1402b5d4fd293ae745f103"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad43530c5b6ae1e89db587b20d71440b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#gad43530c5b6ae1e89db587b20d71440b4">ARM_SAI_PROTOCOL_PCM_LONG</a>   (5U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:gad43530c5b6ae1e89db587b20d71440b4"><td class="mdescLeft"> </td><td class="mdescRight">PCM with long frame. <a href="group__sai__protocol__control.html#gad43530c5b6ae1e89db587b20d71440b4">More...</a><br/></td></tr>
<tr class="separator:gad43530c5b6ae1e89db587b20d71440b4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8b1669910f4db4bb3584543e7eb04d7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__protocol__control.html#ga8b1669910f4db4bb3584543e7eb04d7a">ARM_SAI_PROTOCOL_AC97</a>   (6U << ARM_SAI_PROTOCOL_Pos)</td></tr>
<tr class="memdesc:ga8b1669910f4db4bb3584543e7eb04d7a"><td class="mdescLeft"> </td><td class="mdescRight">AC'97. <a href="group__sai__protocol__control.html#ga8b1669910f4db4bb3584543e7eb04d7a">More...</a><br/></td></tr>
<tr class="separator:ga8b1669910f4db4bb3584543e7eb04d7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a78090bb0f32ce2b2d1214164d875f1f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a78090bb0f32ce2b2d1214164d875f1f5">ARM_SAI_DATA_SIZE_Pos</a>   13</td></tr>
<tr class="separator:a78090bb0f32ce2b2d1214164d875f1f5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1e2b0edcbfbdcb5c452d18830af7c010"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a1e2b0edcbfbdcb5c452d18830af7c010">ARM_SAI_DATA_SIZE_Msk</a>   (0x1FU << ARM_SAI_DATA_SIZE_Pos)</td></tr>
<tr class="separator:a1e2b0edcbfbdcb5c452d18830af7c010"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1a7529e4b46d69dbd57ccef84552a3f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__data__bits__control.html#ga1a7529e4b46d69dbd57ccef84552a3f4">ARM_SAI_DATA_SIZE</a>(n)   ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos)</td></tr>
<tr class="memdesc:ga1a7529e4b46d69dbd57ccef84552a3f4"><td class="mdescLeft"> </td><td class="mdescRight">Data size in bits (8..32) <a href="group__sai__data__bits__control.html#ga1a7529e4b46d69dbd57ccef84552a3f4">More...</a><br/></td></tr>
<tr class="separator:ga1a7529e4b46d69dbd57ccef84552a3f4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a662f3dbd09ce9c8c4df8490ba6fd430d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a662f3dbd09ce9c8c4df8490ba6fd430d">ARM_SAI_BIT_ORDER_Pos</a>   18</td></tr>
<tr class="separator:a662f3dbd09ce9c8c4df8490ba6fd430d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a91d4cec3990025090d2fb31437bc57d2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a91d4cec3990025090d2fb31437bc57d2">ARM_SAI_BIT_ORDER_Msk</a>   (1U << ARM_SAI_BIT_ORDER_Pos)</td></tr>
<tr class="separator:a91d4cec3990025090d2fb31437bc57d2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf74bfe9c3005bf3b80d69f112ea9e62b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__bit__order__control.html#gaf74bfe9c3005bf3b80d69f112ea9e62b">ARM_SAI_MSB_FIRST</a>   (0U << ARM_SAI_BIT_ORDER_Pos)</td></tr>
<tr class="memdesc:gaf74bfe9c3005bf3b80d69f112ea9e62b"><td class="mdescLeft"> </td><td class="mdescRight">Data is transferred with MSB first (default) <a href="group__sai__bit__order__control.html#gaf74bfe9c3005bf3b80d69f112ea9e62b">More...</a><br/></td></tr>
<tr class="separator:gaf74bfe9c3005bf3b80d69f112ea9e62b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga19b51b75537b030b975efcf68f3db78b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__bit__order__control.html#ga19b51b75537b030b975efcf68f3db78b">ARM_SAI_LSB_FIRST</a>   (1U << ARM_SAI_BIT_ORDER_Pos)</td></tr>
<tr class="memdesc:ga19b51b75537b030b975efcf68f3db78b"><td class="mdescLeft"> </td><td class="mdescRight">Data is transferred with LSB first; User Protocol only (ignored otherwise) <a href="group__sai__bit__order__control.html#ga19b51b75537b030b975efcf68f3db78b">More...</a><br/></td></tr>
<tr class="separator:ga19b51b75537b030b975efcf68f3db78b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0adcd27875d92add813b9664e9cb0b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mono__control.html#ga0adcd27875d92add813b9664e9cb0b4b">ARM_SAI_MONO_MODE</a>   (1U << 19)</td></tr>
<tr class="memdesc:ga0adcd27875d92add813b9664e9cb0b4b"><td class="mdescLeft"> </td><td class="mdescRight">Mono Mode (only for I2S, MSB/LSB justified) <a href="group__sai__mono__control.html#ga0adcd27875d92add813b9664e9cb0b4b">More...</a><br/></td></tr>
<tr class="separator:ga0adcd27875d92add813b9664e9cb0b4b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a81a330ce8d7c6fe4ebae73b55af6adb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a81a330ce8d7c6fe4ebae73b55af6adb9">ARM_SAI_COMPANDING_Pos</a>   20</td></tr>
<tr class="separator:a81a330ce8d7c6fe4ebae73b55af6adb9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a14371d4016e5863aa2033f47c213e271"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a14371d4016e5863aa2033f47c213e271">ARM_SAI_COMPANDING_Msk</a>   (3U << ARM_SAI_COMPANDING_Pos)</td></tr>
<tr class="separator:a14371d4016e5863aa2033f47c213e271"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga185919d553cf9204e514136eb375ef08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__companding__control.html#ga185919d553cf9204e514136eb375ef08">ARM_SAI_COMPANDING_NONE</a>   (0U << ARM_SAI_COMPANDING_Pos)</td></tr>
<tr class="memdesc:ga185919d553cf9204e514136eb375ef08"><td class="mdescLeft"> </td><td class="mdescRight">No companding (default) <a href="group__sai__companding__control.html#ga185919d553cf9204e514136eb375ef08">More...</a><br/></td></tr>
<tr class="separator:ga185919d553cf9204e514136eb375ef08"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacfd6c74148c0ae90aa6eaaf8e69da3a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__companding__control.html#gacfd6c74148c0ae90aa6eaaf8e69da3a9">ARM_SAI_COMPANDING_A_LAW</a>   (2U << ARM_SAI_COMPANDING_Pos)</td></tr>
<tr class="memdesc:gacfd6c74148c0ae90aa6eaaf8e69da3a9"><td class="mdescLeft"> </td><td class="mdescRight">A-Law companding. <a href="group__sai__companding__control.html#gacfd6c74148c0ae90aa6eaaf8e69da3a9">More...</a><br/></td></tr>
<tr class="separator:gacfd6c74148c0ae90aa6eaaf8e69da3a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7b571406bcce383140198e53312faee5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__companding__control.html#ga7b571406bcce383140198e53312faee5">ARM_SAI_COMPANDING_U_LAW</a>   (3U << ARM_SAI_COMPANDING_Pos)</td></tr>
<tr class="memdesc:ga7b571406bcce383140198e53312faee5"><td class="mdescLeft"> </td><td class="mdescRight">u-Law companding <a href="group__sai__companding__control.html#ga7b571406bcce383140198e53312faee5">More...</a><br/></td></tr>
<tr class="separator:ga7b571406bcce383140198e53312faee5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7652e9ea76805425bd1380d386fa956d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a7652e9ea76805425bd1380d386fa956d">ARM_SAI_CLOCK_POLARITY_Pos</a>   23</td></tr>
<tr class="separator:a7652e9ea76805425bd1380d386fa956d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a593bd6efd49b976a12243c2b429bd94f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a593bd6efd49b976a12243c2b429bd94f">ARM_SAI_CLOCK_POLARITY_Msk</a>   (1U << ARM_SAI_CLOCK_POLARITY_Pos)</td></tr>
<tr class="separator:a593bd6efd49b976a12243c2b429bd94f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4311b6b6fd937d6ac37aa2d031a5d5ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__clock__pol__control.html#ga4311b6b6fd937d6ac37aa2d031a5d5ee">ARM_SAI_CLOCK_POLARITY_0</a>   (0U << ARM_SAI_CLOCK_POLARITY_Pos)</td></tr>
<tr class="memdesc:ga4311b6b6fd937d6ac37aa2d031a5d5ee"><td class="mdescLeft"> </td><td class="mdescRight">Drive on falling edge, Capture on rising edge (default) <a href="group__sai__clock__pol__control.html#ga4311b6b6fd937d6ac37aa2d031a5d5ee">More...</a><br/></td></tr>
<tr class="separator:ga4311b6b6fd937d6ac37aa2d031a5d5ee"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae4c9b9abd3b7390810a5494363875a53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__clock__pol__control.html#gae4c9b9abd3b7390810a5494363875a53">ARM_SAI_CLOCK_POLARITY_1</a>   (1U << ARM_SAI_CLOCK_POLARITY_Pos)</td></tr>
<tr class="memdesc:gae4c9b9abd3b7390810a5494363875a53"><td class="mdescLeft"> </td><td class="mdescRight">Drive on rising edge, Capture on falling edge. <a href="group__sai__clock__pol__control.html#gae4c9b9abd3b7390810a5494363875a53">More...</a><br/></td></tr>
<tr class="separator:gae4c9b9abd3b7390810a5494363875a53"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a62e1f07e62ec45d44a4b35a975323233"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a62e1f07e62ec45d44a4b35a975323233">ARM_SAI_MCLK_PIN_Pos</a>   24</td></tr>
<tr class="separator:a62e1f07e62ec45d44a4b35a975323233"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1fcfc4708ec7324563be3d0d840a72bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a1fcfc4708ec7324563be3d0d840a72bf">ARM_SAI_MCLK_PIN_Msk</a>   (3U << ARM_SAI_MCLK_PIN_Pos)</td></tr>
<tr class="separator:a1fcfc4708ec7324563be3d0d840a72bf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7654bffb42e96d48df57c598323337d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mclk__pin__control.html#ga7654bffb42e96d48df57c598323337d6">ARM_SAI_MCLK_PIN_INACTIVE</a>   (0U << ARM_SAI_MCLK_PIN_Pos)</td></tr>
<tr class="memdesc:ga7654bffb42e96d48df57c598323337d6"><td class="mdescLeft"> </td><td class="mdescRight">MCLK not used (default) <a href="group__sai__mclk__pin__control.html#ga7654bffb42e96d48df57c598323337d6">More...</a><br/></td></tr>
<tr class="separator:ga7654bffb42e96d48df57c598323337d6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga24d99edf05699eff32da02742fb04ced"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mclk__pin__control.html#ga24d99edf05699eff32da02742fb04ced">ARM_SAI_MCLK_PIN_OUTPUT</a>   (1U << ARM_SAI_MCLK_PIN_Pos)</td></tr>
<tr class="memdesc:ga24d99edf05699eff32da02742fb04ced"><td class="mdescLeft"> </td><td class="mdescRight">MCLK is output (Master only) <a href="group__sai__mclk__pin__control.html#ga24d99edf05699eff32da02742fb04ced">More...</a><br/></td></tr>
<tr class="separator:ga24d99edf05699eff32da02742fb04ced"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2cd610be9ba9532b2926376deaacf5ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mclk__pin__control.html#ga2cd610be9ba9532b2926376deaacf5ad">ARM_SAI_MCLK_PIN_INPUT</a>   (2U << ARM_SAI_MCLK_PIN_Pos)</td></tr>
<tr class="memdesc:ga2cd610be9ba9532b2926376deaacf5ad"><td class="mdescLeft"> </td><td class="mdescRight">MCLK is input (Master only) <a href="group__sai__mclk__pin__control.html#ga2cd610be9ba9532b2926376deaacf5ad">More...</a><br/></td></tr>
<tr class="separator:ga2cd610be9ba9532b2926376deaacf5ad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a330fef2eea5b47e38951600c36ee2a1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a330fef2eea5b47e38951600c36ee2a1b">ARM_SAI_FRAME_LENGTH_Pos</a>   0</td></tr>
<tr class="separator:a330fef2eea5b47e38951600c36ee2a1b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a23789f916975a203d0f17831452540cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a23789f916975a203d0f17831452540cd">ARM_SAI_FRAME_LENGTH_Msk</a>   (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos)</td></tr>
<tr class="separator:a23789f916975a203d0f17831452540cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4c557aa02c83b8595be23a6c58d284e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__frame__control.html#ga4c557aa02c83b8595be23a6c58d284e9">ARM_SAI_FRAME_LENGTH</a>(n)   ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos)</td></tr>
<tr class="memdesc:ga4c557aa02c83b8595be23a6c58d284e9"><td class="mdescLeft"> </td><td class="mdescRight">Frame length in bits (8..1024); default depends on protocol and data. <a href="group__sai__frame__control.html#ga4c557aa02c83b8595be23a6c58d284e9">More...</a><br/></td></tr>
<tr class="separator:ga4c557aa02c83b8595be23a6c58d284e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1012f372276699c44b38b5e093802864"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a1012f372276699c44b38b5e093802864">ARM_SAI_FRAME_SYNC_WIDTH_Pos</a>   10</td></tr>
<tr class="separator:a1012f372276699c44b38b5e093802864"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a319e93ff4c5ac4f067c47118a3334776"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a319e93ff4c5ac4f067c47118a3334776">ARM_SAI_FRAME_SYNC_WIDTH_Msk</a>   (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos)</td></tr>
<tr class="separator:a319e93ff4c5ac4f067c47118a3334776"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae165fd96e6a5b06b362954fadeabcb7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__frame__control.html#gae165fd96e6a5b06b362954fadeabcb7a">ARM_SAI_FRAME_SYNC_WIDTH</a>(n)   ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos)</td></tr>
<tr class="memdesc:gae165fd96e6a5b06b362954fadeabcb7a"><td class="mdescLeft"> </td><td class="mdescRight">Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) <a href="group__sai__frame__control.html#gae165fd96e6a5b06b362954fadeabcb7a">More...</a><br/></td></tr>
<tr class="separator:gae165fd96e6a5b06b362954fadeabcb7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abc50a101bbf53b0fb438ad6682b2745d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#abc50a101bbf53b0fb438ad6682b2745d">ARM_SAI_FRAME_SYNC_POLARITY_Pos</a>   18</td></tr>
<tr class="separator:abc50a101bbf53b0fb438ad6682b2745d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a887b40a5223f2febd4a8b6cc7b7386f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a887b40a5223f2febd4a8b6cc7b7386f1">ARM_SAI_FRAME_SYNC_POLARITY_Msk</a>   (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)</td></tr>
<tr class="separator:a887b40a5223f2febd4a8b6cc7b7386f1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7be0326e15d61d6c67febb22f5b14d58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__frame__control.html#ga7be0326e15d61d6c67febb22f5b14d58">ARM_SAI_FRAME_SYNC_POLARITY_HIGH</a>   (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)</td></tr>
<tr class="memdesc:ga7be0326e15d61d6c67febb22f5b14d58"><td class="mdescLeft"> </td><td class="mdescRight">Frame Sync is active high (default); User Protocol only (ignored otherwise) <a href="group__sai__frame__control.html#ga7be0326e15d61d6c67febb22f5b14d58">More...</a><br/></td></tr>
<tr class="separator:ga7be0326e15d61d6c67febb22f5b14d58"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf3d6bdbc05379ac30905cecf1b2d917e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__frame__control.html#gaf3d6bdbc05379ac30905cecf1b2d917e">ARM_SAI_FRAME_SYNC_POLARITY_LOW</a>   (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)</td></tr>
<tr class="memdesc:gaf3d6bdbc05379ac30905cecf1b2d917e"><td class="mdescLeft"> </td><td class="mdescRight">Frame Sync is active low; User Protocol only (ignored otherwise) <a href="group__sai__frame__control.html#gaf3d6bdbc05379ac30905cecf1b2d917e">More...</a><br/></td></tr>
<tr class="separator:gaf3d6bdbc05379ac30905cecf1b2d917e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabec3992447436a2a8ed99108908ae208"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__frame__control.html#gabec3992447436a2a8ed99108908ae208">ARM_SAI_FRAME_SYNC_EARLY</a>   (1U << 19)</td></tr>
<tr class="memdesc:gabec3992447436a2a8ed99108908ae208"><td class="mdescLeft"> </td><td class="mdescRight">Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) <a href="group__sai__frame__control.html#gabec3992447436a2a8ed99108908ae208">More...</a><br/></td></tr>
<tr class="separator:gabec3992447436a2a8ed99108908ae208"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac2b8807f6651d6f72e0ec35ccfaea467"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#ac2b8807f6651d6f72e0ec35ccfaea467">ARM_SAI_SLOT_COUNT_Pos</a>   20</td></tr>
<tr class="separator:ac2b8807f6651d6f72e0ec35ccfaea467"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4c650eb9f59911ea332bbc090e0176ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a4c650eb9f59911ea332bbc090e0176ec">ARM_SAI_SLOT_COUNT_Msk</a>   (0x1FU << ARM_SAI_SLOT_COUNT_Pos)</td></tr>
<tr class="separator:a4c650eb9f59911ea332bbc090e0176ec"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8f2cf3a212ca7fe389e00b082efb5d0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__slot__control.html#ga8f2cf3a212ca7fe389e00b082efb5d0b">ARM_SAI_SLOT_COUNT</a>(n)   ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos)</td></tr>
<tr class="memdesc:ga8f2cf3a212ca7fe389e00b082efb5d0b"><td class="mdescLeft"> </td><td class="mdescRight">Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) <a href="group__sai__slot__control.html#ga8f2cf3a212ca7fe389e00b082efb5d0b">More...</a><br/></td></tr>
<tr class="separator:ga8f2cf3a212ca7fe389e00b082efb5d0b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6c17885d8e10e8befe7d04bca108ffda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a6c17885d8e10e8befe7d04bca108ffda">ARM_SAI_SLOT_SIZE_Pos</a>   25</td></tr>
<tr class="separator:a6c17885d8e10e8befe7d04bca108ffda"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a91b6372d62b46f5608f3de2c66186137"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a91b6372d62b46f5608f3de2c66186137">ARM_SAI_SLOT_SIZE_Msk</a>   (3U << ARM_SAI_SLOT_SIZE_Pos)</td></tr>
<tr class="separator:a91b6372d62b46f5608f3de2c66186137"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad77c6c0de2a4e7223a0c42e1594f0a2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__slot__control.html#gad77c6c0de2a4e7223a0c42e1594f0a2c">ARM_SAI_SLOT_SIZE_DEFAULT</a>   (0U << ARM_SAI_SLOT_SIZE_Pos)</td></tr>
<tr class="memdesc:gad77c6c0de2a4e7223a0c42e1594f0a2c"><td class="mdescLeft"> </td><td class="mdescRight">Slot size is equal to data size (default) <a href="group__sai__slot__control.html#gad77c6c0de2a4e7223a0c42e1594f0a2c">More...</a><br/></td></tr>
<tr class="separator:gad77c6c0de2a4e7223a0c42e1594f0a2c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2bb9cf53b07cac81fb0fe71de6c97c83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__slot__control.html#ga2bb9cf53b07cac81fb0fe71de6c97c83">ARM_SAI_SLOT_SIZE_16</a>   (1U << ARM_SAI_SLOT_SIZE_Pos)</td></tr>
<tr class="memdesc:ga2bb9cf53b07cac81fb0fe71de6c97c83"><td class="mdescLeft"> </td><td class="mdescRight">Slot size = 16 bits; User Protocol only (ignored otherwise) <a href="group__sai__slot__control.html#ga2bb9cf53b07cac81fb0fe71de6c97c83">More...</a><br/></td></tr>
<tr class="separator:ga2bb9cf53b07cac81fb0fe71de6c97c83"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaa5c4cc18a0f5668bc9f117874cd83dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__slot__control.html#gaaa5c4cc18a0f5668bc9f117874cd83dd">ARM_SAI_SLOT_SIZE_32</a>   (3U << ARM_SAI_SLOT_SIZE_Pos)</td></tr>
<tr class="memdesc:gaaa5c4cc18a0f5668bc9f117874cd83dd"><td class="mdescLeft"> </td><td class="mdescRight">Slot size = 32 bits; User Protocol only (ignored otherwise) <a href="group__sai__slot__control.html#gaaa5c4cc18a0f5668bc9f117874cd83dd">More...</a><br/></td></tr>
<tr class="separator:gaaa5c4cc18a0f5668bc9f117874cd83dd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a502fb0ed58535dfc41f47db570105af4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a502fb0ed58535dfc41f47db570105af4">ARM_SAI_SLOT_OFFSET_Pos</a>   27</td></tr>
<tr class="separator:a502fb0ed58535dfc41f47db570105af4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae45ed9a4e8a4bb6861ddc0752b716ea3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#ae45ed9a4e8a4bb6861ddc0752b716ea3">ARM_SAI_SLOT_OFFSET_Msk</a>   (0x1FU << ARM_SAI_SLOT_OFFSET_Pos)</td></tr>
<tr class="separator:ae45ed9a4e8a4bb6861ddc0752b716ea3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga48d4a142f3a1bb0fa4e88c9e427932a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__slot__control.html#ga48d4a142f3a1bb0fa4e88c9e427932a0">ARM_SAI_SLOT_OFFSET</a>(n)   (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos)</td></tr>
<tr class="memdesc:ga48d4a142f3a1bb0fa4e88c9e427932a0"><td class="mdescLeft"> </td><td class="mdescRight">Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) <a href="group__sai__slot__control.html#ga48d4a142f3a1bb0fa4e88c9e427932a0">More...</a><br/></td></tr>
<tr class="separator:ga48d4a142f3a1bb0fa4e88c9e427932a0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac923ba4673588d3839a48c8a873b1248"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#ac923ba4673588d3839a48c8a873b1248">ARM_SAI_AUDIO_FREQ_Msk</a>   (0x0FFFFFU)</td></tr>
<tr class="memdesc:ac923ba4673588d3839a48c8a873b1248"><td class="mdescLeft"> </td><td class="mdescRight">Audio frequency mask. <a href="#ac923ba4673588d3839a48c8a873b1248">More...</a><br/></td></tr>
<tr class="separator:ac923ba4673588d3839a48c8a873b1248"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2d4fa5bf0272869fe80f7a35844c296b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#a2d4fa5bf0272869fe80f7a35844c296b">ARM_SAI_MCLK_PRESCALER_Pos</a>   20</td></tr>
<tr class="separator:a2d4fa5bf0272869fe80f7a35844c296b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adaa62519270d171df9b087ea004a3bb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SAI_8h.html#adaa62519270d171df9b087ea004a3bb9">ARM_SAI_MCLK_PRESCALER_Msk</a>   (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos)</td></tr>
<tr class="separator:adaa62519270d171df9b087ea004a3bb9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2afa85cd335e75d8b9b06c9f47f3f4b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__mclk__pres__control.html#ga2afa85cd335e75d8b9b06c9f47f3f4b0">ARM_SAI_MCLK_PRESCALER</a>(n)   ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos)</td></tr>
<tr class="memdesc:ga2afa85cd335e75d8b9b06c9f47f3f4b0"><td class="mdescLeft"> </td><td class="mdescRight">MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) <a href="group__sai__mclk__pres__control.html#ga2afa85cd335e75d8b9b06c9f47f3f4b0">More...</a><br/></td></tr>
<tr class="separator:ga2afa85cd335e75d8b9b06c9f47f3f4b0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga711cd889b4209df3f8fb01e4f2413c61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga711cd889b4209df3f8fb01e4f2413c61">ARM_SAI_ERROR_SYNCHRONIZATION</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td></tr>
<tr class="memdesc:ga711cd889b4209df3f8fb01e4f2413c61"><td class="mdescLeft"> </td><td class="mdescRight">Specified Synchronization not supported. <a href="group__sai__execution__status.html#ga711cd889b4209df3f8fb01e4f2413c61">More...</a><br/></td></tr>
<tr class="separator:ga711cd889b4209df3f8fb01e4f2413c61"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf4892425930608ad7a41fa5b49603b10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#gaf4892425930608ad7a41fa5b49603b10">ARM_SAI_ERROR_PROTOCOL</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 2)</td></tr>
<tr class="memdesc:gaf4892425930608ad7a41fa5b49603b10"><td class="mdescLeft"> </td><td class="mdescRight">Specified Protocol not supported. <a href="group__sai__execution__status.html#gaf4892425930608ad7a41fa5b49603b10">More...</a><br/></td></tr>
<tr class="separator:gaf4892425930608ad7a41fa5b49603b10"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5c51cbd8c2d2fe4baae110d390cefdc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga5c51cbd8c2d2fe4baae110d390cefdc2">ARM_SAI_ERROR_DATA_SIZE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 3)</td></tr>
<tr class="memdesc:ga5c51cbd8c2d2fe4baae110d390cefdc2"><td class="mdescLeft"> </td><td class="mdescRight">Specified Data size not supported. <a href="group__sai__execution__status.html#ga5c51cbd8c2d2fe4baae110d390cefdc2">More...</a><br/></td></tr>
<tr class="separator:ga5c51cbd8c2d2fe4baae110d390cefdc2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadcd0d44f0f6b691c4e84b30960c096e4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#gadcd0d44f0f6b691c4e84b30960c096e4">ARM_SAI_ERROR_BIT_ORDER</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 4)</td></tr>
<tr class="memdesc:gadcd0d44f0f6b691c4e84b30960c096e4"><td class="mdescLeft"> </td><td class="mdescRight">Specified Bit order not supported. <a href="group__sai__execution__status.html#gadcd0d44f0f6b691c4e84b30960c096e4">More...</a><br/></td></tr>
<tr class="separator:gadcd0d44f0f6b691c4e84b30960c096e4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga912bf004fce3a37709bbf69734802b4a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga912bf004fce3a37709bbf69734802b4a">ARM_SAI_ERROR_MONO_MODE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 5)</td></tr>
<tr class="memdesc:ga912bf004fce3a37709bbf69734802b4a"><td class="mdescLeft"> </td><td class="mdescRight">Specified Mono mode not supported. <a href="group__sai__execution__status.html#ga912bf004fce3a37709bbf69734802b4a">More...</a><br/></td></tr>
<tr class="separator:ga912bf004fce3a37709bbf69734802b4a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4683468c258e1a8706afcce1e81356d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga4683468c258e1a8706afcce1e81356d1">ARM_SAI_ERROR_COMPANDING</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 6)</td></tr>
<tr class="memdesc:ga4683468c258e1a8706afcce1e81356d1"><td class="mdescLeft"> </td><td class="mdescRight">Specified Companding not supported. <a href="group__sai__execution__status.html#ga4683468c258e1a8706afcce1e81356d1">More...</a><br/></td></tr>
<tr class="separator:ga4683468c258e1a8706afcce1e81356d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7810e77ec599b0f86073a8711c0655df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga7810e77ec599b0f86073a8711c0655df">ARM_SAI_ERROR_CLOCK_POLARITY</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 7)</td></tr>
<tr class="memdesc:ga7810e77ec599b0f86073a8711c0655df"><td class="mdescLeft"> </td><td class="mdescRight">Specified Clock polarity not supported. <a href="group__sai__execution__status.html#ga7810e77ec599b0f86073a8711c0655df">More...</a><br/></td></tr>
<tr class="separator:ga7810e77ec599b0f86073a8711c0655df"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5021651816da0aa92561eed634ba7578"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga5021651816da0aa92561eed634ba7578">ARM_SAI_ERROR_AUDIO_FREQ</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 8)</td></tr>
<tr class="memdesc:ga5021651816da0aa92561eed634ba7578"><td class="mdescLeft"> </td><td class="mdescRight">Specified Audio frequency not supported. <a href="group__sai__execution__status.html#ga5021651816da0aa92561eed634ba7578">More...</a><br/></td></tr>
<tr class="separator:ga5021651816da0aa92561eed634ba7578"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0d910d4a638433e3b2326fc776da0f53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga0d910d4a638433e3b2326fc776da0f53">ARM_SAI_ERROR_MCLK_PIN</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 9)</td></tr>
<tr class="memdesc:ga0d910d4a638433e3b2326fc776da0f53"><td class="mdescLeft"> </td><td class="mdescRight">Specified MCLK Pin setting not supported. <a href="group__sai__execution__status.html#ga0d910d4a638433e3b2326fc776da0f53">More...</a><br/></td></tr>
<tr class="separator:ga0d910d4a638433e3b2326fc776da0f53"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabab9495d6c57e56604cb1a2ac7e75431"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#gabab9495d6c57e56604cb1a2ac7e75431">ARM_SAI_ERROR_MCLK_PRESCALER</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 10)</td></tr>
<tr class="memdesc:gabab9495d6c57e56604cb1a2ac7e75431"><td class="mdescLeft"> </td><td class="mdescRight">Specified MCLK Prescaler not supported. <a href="group__sai__execution__status.html#gabab9495d6c57e56604cb1a2ac7e75431">More...</a><br/></td></tr>
<tr class="separator:gabab9495d6c57e56604cb1a2ac7e75431"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf0448bdd6d1ae33511d170b9ecc1e2d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#gaf0448bdd6d1ae33511d170b9ecc1e2d6">ARM_SAI_ERROR_FRAME_LENGHT</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 11)</td></tr>
<tr class="memdesc:gaf0448bdd6d1ae33511d170b9ecc1e2d6"><td class="mdescLeft"> </td><td class="mdescRight">Specified Frame length not supported. <a href="group__sai__execution__status.html#gaf0448bdd6d1ae33511d170b9ecc1e2d6">More...</a><br/></td></tr>
<tr class="separator:gaf0448bdd6d1ae33511d170b9ecc1e2d6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga993da1bc0f6745795b364d84dec24e99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga993da1bc0f6745795b364d84dec24e99">ARM_SAI_ERROR_FRAME_SYNC_WIDTH</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 12)</td></tr>
<tr class="memdesc:ga993da1bc0f6745795b364d84dec24e99"><td class="mdescLeft"> </td><td class="mdescRight">Specified Frame Sync width not supported. <a href="group__sai__execution__status.html#ga993da1bc0f6745795b364d84dec24e99">More...</a><br/></td></tr>
<tr class="separator:ga993da1bc0f6745795b364d84dec24e99"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0561b0cc9577d944e0d39b582612e061"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga0561b0cc9577d944e0d39b582612e061">ARM_SAI_ERROR_FRAME_SYNC_POLARITY</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 13)</td></tr>
<tr class="memdesc:ga0561b0cc9577d944e0d39b582612e061"><td class="mdescLeft"> </td><td class="mdescRight">Specified Frame Sync polarity not supported. <a href="group__sai__execution__status.html#ga0561b0cc9577d944e0d39b582612e061">More...</a><br/></td></tr>
<tr class="separator:ga0561b0cc9577d944e0d39b582612e061"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga09fe9b65d2be54ee1441606523291011"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga09fe9b65d2be54ee1441606523291011">ARM_SAI_ERROR_FRAME_SYNC_EARLY</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 14)</td></tr>
<tr class="memdesc:ga09fe9b65d2be54ee1441606523291011"><td class="mdescLeft"> </td><td class="mdescRight">Specified Frame Sync early not supported. <a href="group__sai__execution__status.html#ga09fe9b65d2be54ee1441606523291011">More...</a><br/></td></tr>
<tr class="separator:ga09fe9b65d2be54ee1441606523291011"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf52ee0cd13b6cb9c63acfe767ed5dfde"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#gaf52ee0cd13b6cb9c63acfe767ed5dfde">ARM_SAI_ERROR_SLOT_COUNT</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 15)</td></tr>
<tr class="memdesc:gaf52ee0cd13b6cb9c63acfe767ed5dfde"><td class="mdescLeft"> </td><td class="mdescRight">Specified Slot count not supported. <a href="group__sai__execution__status.html#gaf52ee0cd13b6cb9c63acfe767ed5dfde">More...</a><br/></td></tr>
<tr class="separator:gaf52ee0cd13b6cb9c63acfe767ed5dfde"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7bf825043ba857950a89817ff9b853d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga7bf825043ba857950a89817ff9b853d1">ARM_SAI_ERROR_SLOT_SIZE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 16)</td></tr>
<tr class="memdesc:ga7bf825043ba857950a89817ff9b853d1"><td class="mdescLeft"> </td><td class="mdescRight">Specified Slot size not supported. <a href="group__sai__execution__status.html#ga7bf825043ba857950a89817ff9b853d1">More...</a><br/></td></tr>
<tr class="separator:ga7bf825043ba857950a89817ff9b853d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4658a3143c891d8972446630b6a978cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__execution__status.html#ga4658a3143c891d8972446630b6a978cd">ARM_SAI_ERROR_SLOT_OFFESET</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 17)</td></tr>
<tr class="memdesc:ga4658a3143c891d8972446630b6a978cd"><td class="mdescLeft"> </td><td class="mdescRight">Specified Slot offset not supported. <a href="group__sai__execution__status.html#ga4658a3143c891d8972446630b6a978cd">More...</a><br/></td></tr>
<tr class="separator:ga4658a3143c891d8972446630b6a978cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3dfa64375859f40d157c224187d2885e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SAI__events.html#ga3dfa64375859f40d157c224187d2885e">ARM_SAI_EVENT_SEND_COMPLETE</a>   (1U << 0)</td></tr>
<tr class="memdesc:ga3dfa64375859f40d157c224187d2885e"><td class="mdescLeft"> </td><td class="mdescRight">Send completed. <a href="group__SAI__events.html#ga3dfa64375859f40d157c224187d2885e">More...</a><br/></td></tr>
<tr class="separator:ga3dfa64375859f40d157c224187d2885e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a9bde0b096aafe53279529a0adbef55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SAI__events.html#ga5a9bde0b096aafe53279529a0adbef55">ARM_SAI_EVENT_RECEIVE_COMPLETE</a>   (1U << 1)</td></tr>
<tr class="memdesc:ga5a9bde0b096aafe53279529a0adbef55"><td class="mdescLeft"> </td><td class="mdescRight">Receive completed. <a href="group__SAI__events.html#ga5a9bde0b096aafe53279529a0adbef55">More...</a><br/></td></tr>
<tr class="separator:ga5a9bde0b096aafe53279529a0adbef55"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6a0be7aaf9d700e5259f741641bc37ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SAI__events.html#ga6a0be7aaf9d700e5259f741641bc37ca">ARM_SAI_EVENT_TX_UNDERFLOW</a>   (1U << 2)</td></tr>
<tr class="memdesc:ga6a0be7aaf9d700e5259f741641bc37ca"><td class="mdescLeft"> </td><td class="mdescRight">Transmit data not available. <a href="group__SAI__events.html#ga6a0be7aaf9d700e5259f741641bc37ca">More...</a><br/></td></tr>
<tr class="separator:ga6a0be7aaf9d700e5259f741641bc37ca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac83e9df0238803ef2c88f16605f73bf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SAI__events.html#gac83e9df0238803ef2c88f16605f73bf5">ARM_SAI_EVENT_RX_OVERFLOW</a>   (1U << 3)</td></tr>
<tr class="memdesc:gac83e9df0238803ef2c88f16605f73bf5"><td class="mdescLeft"> </td><td class="mdescRight">Receive data overflow. <a href="group__SAI__events.html#gac83e9df0238803ef2c88f16605f73bf5">More...</a><br/></td></tr>
<tr class="separator:gac83e9df0238803ef2c88f16605f73bf5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6ffcf96fe404b48421a57fbd122b26bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SAI__events.html#ga6ffcf96fe404b48421a57fbd122b26bc">ARM_SAI_EVENT_FRAME_ERROR</a>   (1U << 4)</td></tr>
<tr class="memdesc:ga6ffcf96fe404b48421a57fbd122b26bc"><td class="mdescLeft"> </td><td class="mdescRight">Sync Frame error in Slave mode (optional) <a href="group__SAI__events.html#ga6ffcf96fe404b48421a57fbd122b26bc">More...</a><br/></td></tr>
<tr class="separator:ga6ffcf96fe404b48421a57fbd122b26bc"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gad8ca8e2459e540928f6315b3df6da0ee"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sai__interface__gr.html#gad8ca8e2459e540928f6315b3df6da0ee">ARM_SAI_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:gad8ca8e2459e540928f6315b3df6da0ee"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__sai__interface__gr.html#gaedf3347cb25d6bf2faad1bbb35ad79f4">ARM_SAI_SignalEvent</a> : Signal SAI Event. <a href="group__sai__interface__gr.html#gad8ca8e2459e540928f6315b3df6da0ee">More...</a><br/></td></tr>
<tr class="separator:gad8ca8e2459e540928f6315b3df6da0ee"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a228007626e6f533b7a86a85e73e74d1e"></a>
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<td class="memname">#define ARM_SAI_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(1,1) /* API version */</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="abe35f330af97ad488b28f580f7105b27"></a>
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<td class="memname">#define ARM_SAI_CONTROL_Msk   (0xFFU)</td>
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</div>
</div>
<a class="anchor" id="a8779654f638207bcee1b86a508b3a486"></a>
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<td class="memname">#define ARM_SAI_MODE_Pos   8</td>
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</div>
</div>
<a class="anchor" id="ae949aad131ef68cde3190e3ab772f5bc"></a>
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<td class="memname">#define ARM_SAI_MODE_Msk   (1U << ARM_SAI_MODE_Pos)</td>
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</div>
</div>
<a class="anchor" id="a07e9aff784158ff76feab30b9c1b39ec"></a>
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<td class="memname">#define ARM_SAI_SYNCHRONIZATION_Pos   9</td>
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<a class="anchor" id="a42244bcaa347e43405cc356c00458c2e"></a>
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<td class="memname">#define ARM_SAI_SYNCHRONIZATION_Msk   (1U << ARM_SAI_SYNCHRONIZATION_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a9d46c20d74fc28cd23c61efec5d7e264"></a>
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<td class="memname">#define ARM_SAI_PROTOCOL_Pos   10</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="aff67558883dcbaaed0feb28ddb5104a9"></a>
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<td class="memname">#define ARM_SAI_PROTOCOL_Msk   (7U << ARM_SAI_PROTOCOL_Pos)</td>
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</div>
</div>
<a class="anchor" id="a78090bb0f32ce2b2d1214164d875f1f5"></a>
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<td class="memname">#define ARM_SAI_DATA_SIZE_Pos   13</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a1e2b0edcbfbdcb5c452d18830af7c010"></a>
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<td class="memname">#define ARM_SAI_DATA_SIZE_Msk   (0x1FU << ARM_SAI_DATA_SIZE_Pos)</td>
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</div>
</div>
<a class="anchor" id="a662f3dbd09ce9c8c4df8490ba6fd430d"></a>
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<td class="memname">#define ARM_SAI_BIT_ORDER_Pos   18</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a91d4cec3990025090d2fb31437bc57d2"></a>
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<td class="memname">#define ARM_SAI_BIT_ORDER_Msk   (1U << ARM_SAI_BIT_ORDER_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a81a330ce8d7c6fe4ebae73b55af6adb9"></a>
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<td class="memname">#define ARM_SAI_COMPANDING_Pos   20</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a14371d4016e5863aa2033f47c213e271"></a>
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<td class="memname">#define ARM_SAI_COMPANDING_Msk   (3U << ARM_SAI_COMPANDING_Pos)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a7652e9ea76805425bd1380d386fa956d"></a>
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<td class="memname">#define ARM_SAI_CLOCK_POLARITY_Pos   23</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a593bd6efd49b976a12243c2b429bd94f"></a>
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<div class="memproto">
<table class="memname">
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<td class="memname">#define ARM_SAI_CLOCK_POLARITY_Msk   (1U << ARM_SAI_CLOCK_POLARITY_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a62e1f07e62ec45d44a4b35a975323233"></a>
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<div class="memproto">
<table class="memname">
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<td class="memname">#define ARM_SAI_MCLK_PIN_Pos   24</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a1fcfc4708ec7324563be3d0d840a72bf"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define ARM_SAI_MCLK_PIN_Msk   (3U << ARM_SAI_MCLK_PIN_Pos)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a330fef2eea5b47e38951600c36ee2a1b"></a>
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<td class="memname">#define ARM_SAI_FRAME_LENGTH_Pos   0</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a23789f916975a203d0f17831452540cd"></a>
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<div class="memproto">
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<td class="memname">#define ARM_SAI_FRAME_LENGTH_Msk   (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a1012f372276699c44b38b5e093802864"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_SAI_FRAME_SYNC_WIDTH_Pos   10</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a319e93ff4c5ac4f067c47118a3334776"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_SAI_FRAME_SYNC_WIDTH_Msk   (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="abc50a101bbf53b0fb438ad6682b2745d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a887b40a5223f2febd4a8b6cc7b7386f1"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_SAI_FRAME_SYNC_POLARITY_Msk   (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)</td>
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</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ac2b8807f6651d6f72e0ec35ccfaea467"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define ARM_SAI_SLOT_COUNT_Pos   20</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a4c650eb9f59911ea332bbc090e0176ec"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_SLOT_COUNT_Msk   (0x1FU << ARM_SAI_SLOT_COUNT_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a6c17885d8e10e8befe7d04bca108ffda"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_SLOT_SIZE_Pos   25</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a91b6372d62b46f5608f3de2c66186137"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_SLOT_SIZE_Msk   (3U << ARM_SAI_SLOT_SIZE_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a502fb0ed58535dfc41f47db570105af4"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_SLOT_OFFSET_Pos   27</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ae45ed9a4e8a4bb6861ddc0752b716ea3"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_SLOT_OFFSET_Msk   (0x1FU << ARM_SAI_SLOT_OFFSET_Pos)</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="ac923ba4673588d3839a48c8a873b1248"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_AUDIO_FREQ_Msk   (0x0FFFFFU)</td>
</tr>
</table>
</div><div class="memdoc">
<p>Audio frequency mask. </p>
</div>
</div>
<a class="anchor" id="a2d4fa5bf0272869fe80f7a35844c296b"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_MCLK_PRESCALER_Pos   20</td>
</tr>
</table>
</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="adaa62519270d171df9b087ea004a3bb9"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define ARM_SAI_MCLK_PRESCALER_Msk   (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos)</td>
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Functions</h2></td></tr>
<tr class="memitem:gad5db9209ef1d64a7915a7278d6a402c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gad5db9209ef1d64a7915a7278d6a402c8">ARM_SPI_GetVersion</a> (void)</td></tr>
<tr class="memdesc:gad5db9209ef1d64a7915a7278d6a402c8"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__spi__interface__gr.html#gad5db9209ef1d64a7915a7278d6a402c8">More...</a><br/></td></tr>
<tr class="separator:gad5db9209ef1d64a7915a7278d6a402c8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf4823a11ab5efcd47c79b13801513ddc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__spi__interface__gr.html#structARM__SPI__CAPABILITIES">ARM_SPI_CAPABILITIES</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gaf4823a11ab5efcd47c79b13801513ddc">ARM_SPI_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:gaf4823a11ab5efcd47c79b13801513ddc"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__spi__interface__gr.html#gaf4823a11ab5efcd47c79b13801513ddc">More...</a><br/></td></tr>
<tr class="separator:gaf4823a11ab5efcd47c79b13801513ddc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1a3c11ed523a4355cd91069527945906"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga1a3c11ed523a4355cd91069527945906">ARM_SPI_Initialize</a> (<a class="el" href="group__spi__interface__gr.html#gafde9205364241ee81290adc0481c6640">ARM_SPI_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga1a3c11ed523a4355cd91069527945906"><td class="mdescLeft"> </td><td class="mdescRight">Initialize SPI Interface. <a href="group__spi__interface__gr.html#ga1a3c11ed523a4355cd91069527945906">More...</a><br/></td></tr>
<tr class="separator:ga1a3c11ed523a4355cd91069527945906"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0c480ee3eabb82fc746e89741ed2e03e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga0c480ee3eabb82fc746e89741ed2e03e">ARM_SPI_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:ga0c480ee3eabb82fc746e89741ed2e03e"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize SPI Interface. <a href="group__spi__interface__gr.html#ga0c480ee3eabb82fc746e89741ed2e03e">More...</a><br/></td></tr>
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<tr class="memitem:ga1a1e7e80ea32ae381b75213c32aa8067"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga1a1e7e80ea32ae381b75213c32aa8067">ARM_SPI_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga1a1e7e80ea32ae381b75213c32aa8067"><td class="mdescLeft"> </td><td class="mdescRight">Control SPI Interface Power. <a href="group__spi__interface__gr.html#ga1a1e7e80ea32ae381b75213c32aa8067">More...</a><br/></td></tr>
<tr class="separator:ga1a1e7e80ea32ae381b75213c32aa8067"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab2a303d1071e926280d50682f4808479"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gab2a303d1071e926280d50682f4808479">ARM_SPI_Send</a> (const void *data, uint32_t num)</td></tr>
<tr class="memdesc:gab2a303d1071e926280d50682f4808479"><td class="mdescLeft"> </td><td class="mdescRight">Start sending data to SPI transmitter. <a href="group__spi__interface__gr.html#gab2a303d1071e926280d50682f4808479">More...</a><br/></td></tr>
<tr class="separator:gab2a303d1071e926280d50682f4808479"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga726aff54e782ed9b47f7ba1280a3d8f6"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga726aff54e782ed9b47f7ba1280a3d8f6">ARM_SPI_Receive</a> (void *data, uint32_t num)</td></tr>
<tr class="memdesc:ga726aff54e782ed9b47f7ba1280a3d8f6"><td class="mdescLeft"> </td><td class="mdescRight">Start receiving data from SPI receiver. <a href="group__spi__interface__gr.html#ga726aff54e782ed9b47f7ba1280a3d8f6">More...</a><br/></td></tr>
<tr class="separator:ga726aff54e782ed9b47f7ba1280a3d8f6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa24026b3822c10272e301f1505136ec2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gaa24026b3822c10272e301f1505136ec2">ARM_SPI_Transfer</a> (const void *data_out, void *data_in, uint32_t num)</td></tr>
<tr class="memdesc:gaa24026b3822c10272e301f1505136ec2"><td class="mdescLeft"> </td><td class="mdescRight">Start sending/receiving data to/from SPI transmitter/receiver. <a href="group__spi__interface__gr.html#gaa24026b3822c10272e301f1505136ec2">More...</a><br/></td></tr>
<tr class="separator:gaa24026b3822c10272e301f1505136ec2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaaecaaf4ec1922f22e7f9de63af5ccdb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gaaaecaaf4ec1922f22e7f9de63af5ccdb">ARM_SPI_GetDataCount</a> (void)</td></tr>
<tr class="memdesc:gaaaecaaf4ec1922f22e7f9de63af5ccdb"><td class="mdescLeft"> </td><td class="mdescRight">Get transferred data count. <a href="group__spi__interface__gr.html#gaaaecaaf4ec1922f22e7f9de63af5ccdb">More...</a><br/></td></tr>
<tr class="separator:gaaaecaaf4ec1922f22e7f9de63af5ccdb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad18d229992598d6677bec250015e5d1a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:gad18d229992598d6677bec250015e5d1a"><td class="mdescLeft"> </td><td class="mdescRight">Control SPI Interface. <a href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">More...</a><br/></td></tr>
<tr class="separator:gad18d229992598d6677bec250015e5d1a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga60d33d8788a76c388cc36e066240b817"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__spi__interface__gr.html#structARM__SPI__STATUS">ARM_SPI_STATUS</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga60d33d8788a76c388cc36e066240b817">ARM_SPI_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga60d33d8788a76c388cc36e066240b817"><td class="mdescLeft"> </td><td class="mdescRight">Get SPI status. <a href="group__spi__interface__gr.html#ga60d33d8788a76c388cc36e066240b817">More...</a><br/></td></tr>
<tr class="separator:ga60d33d8788a76c388cc36e066240b817"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga505b2d787348d51351d38fee98ccba7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#ga505b2d787348d51351d38fee98ccba7e">ARM_SPI_SignalEvent</a> (uint32_t event)</td></tr>
<tr class="memdesc:ga505b2d787348d51351d38fee98ccba7e"><td class="mdescLeft"> </td><td class="mdescRight">Signal SPI Events. <a href="group__spi__interface__gr.html#ga505b2d787348d51351d38fee98ccba7e">More...</a><br/></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:structARM__SPI__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#structARM__SPI__STATUS">ARM_SPI_STATUS</a></td></tr>
<tr class="memdesc:structARM__SPI__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">SPI Status. <a href="group__spi__interface__gr.html#structARM__SPI__STATUS">More...</a><br/></td></tr>
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<tr class="memitem:structARM__SPI__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#structARM__SPI__CAPABILITIES">ARM_SPI_CAPABILITIES</a></td></tr>
<tr class="memdesc:structARM__SPI__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">SPI Driver Capabilities. <a href="group__spi__interface__gr.html#structARM__SPI__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="memitem:structARM__DRIVER__SPI"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#structARM__DRIVER__SPI">ARM_DRIVER_SPI</a></td></tr>
<tr class="memdesc:structARM__DRIVER__SPI"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the SPI Driver. <a href="group__spi__interface__gr.html#structARM__DRIVER__SPI">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:acf1275c15e53a573d7db89da66839d97"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#acf1275c15e53a573d7db89da66839d97">ARM_SPI_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td></tr>
<tr class="separator:acf1275c15e53a573d7db89da66839d97"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a129dc5d38b4ba2c776c0b90aecf12a63"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a129dc5d38b4ba2c776c0b90aecf12a63">ARM_SPI_CONTROL_Pos</a>   0</td></tr>
<tr class="separator:a129dc5d38b4ba2c776c0b90aecf12a63"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a646c834efef12377b372ea546459315b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a646c834efef12377b372ea546459315b">ARM_SPI_CONTROL_Msk</a>   (0xFFUL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="separator:a646c834efef12377b372ea546459315b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga974e3d7c178b76b0540d7644b977bff3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__mode__ctrls.html#ga974e3d7c178b76b0540d7644b977bff3">ARM_SPI_MODE_INACTIVE</a>   (0x00UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga974e3d7c178b76b0540d7644b977bff3"><td class="mdescLeft"> </td><td class="mdescRight">SPI Inactive. <a href="group__spi__mode__ctrls.html#ga974e3d7c178b76b0540d7644b977bff3">More...</a><br/></td></tr>
<tr class="separator:ga974e3d7c178b76b0540d7644b977bff3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3143ef07c1607b9bc57e29df35cf2fa8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__mode__ctrls.html#ga3143ef07c1607b9bc57e29df35cf2fa8">ARM_SPI_MODE_MASTER</a>   (0x01UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga3143ef07c1607b9bc57e29df35cf2fa8"><td class="mdescLeft"> </td><td class="mdescRight">SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps. <a href="group__spi__mode__ctrls.html#ga3143ef07c1607b9bc57e29df35cf2fa8">More...</a><br/></td></tr>
<tr class="separator:ga3143ef07c1607b9bc57e29df35cf2fa8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga382b394c5e68f7d1206b837843732a3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__mode__ctrls.html#ga382b394c5e68f7d1206b837843732a3e">ARM_SPI_MODE_SLAVE</a>   (0x02UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga382b394c5e68f7d1206b837843732a3e"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave (Output on MISO, Input on MOSI) <a href="group__spi__mode__ctrls.html#ga382b394c5e68f7d1206b837843732a3e">More...</a><br/></td></tr>
<tr class="separator:ga382b394c5e68f7d1206b837843732a3e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf34d849c7cde1151a768887f154e19bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__mode__ctrls.html#gaf34d849c7cde1151a768887f154e19bd">ARM_SPI_MODE_MASTER_SIMPLEX</a>   (0x03UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:gaf34d849c7cde1151a768887f154e19bd"><td class="mdescLeft"> </td><td class="mdescRight">SPI Master (Output/Input on MOSI); arg = Bus Speed in bps. <a href="group__spi__mode__ctrls.html#gaf34d849c7cde1151a768887f154e19bd">More...</a><br/></td></tr>
<tr class="separator:gaf34d849c7cde1151a768887f154e19bd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9b113d8b336047e1c22f73ad44851fdf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__mode__ctrls.html#ga9b113d8b336047e1c22f73ad44851fdf">ARM_SPI_MODE_SLAVE_SIMPLEX</a>   (0x04UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga9b113d8b336047e1c22f73ad44851fdf"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave (Output/Input on MISO) <a href="group__spi__mode__ctrls.html#ga9b113d8b336047e1c22f73ad44851fdf">More...</a><br/></td></tr>
<tr class="separator:ga9b113d8b336047e1c22f73ad44851fdf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac47e4ed093d8c054021121f89c64023e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#ac47e4ed093d8c054021121f89c64023e">ARM_SPI_FRAME_FORMAT_Pos</a>   8</td></tr>
<tr class="separator:ac47e4ed093d8c054021121f89c64023e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af459192fe14b4b725816fa0029149298"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#af459192fe14b4b725816fa0029149298">ARM_SPI_FRAME_FORMAT_Msk</a>   (7UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="separator:af459192fe14b4b725816fa0029149298"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab4ac9a609c078d1e8332cf95da34e50e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#gab4ac9a609c078d1e8332cf95da34e50e">ARM_SPI_CPOL0_CPHA0</a>   (0UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:gab4ac9a609c078d1e8332cf95da34e50e"><td class="mdescLeft"> </td><td class="mdescRight">Clock Polarity 0, Clock Phase 0 (default) <a href="group__spi__frame__format__ctrls.html#gab4ac9a609c078d1e8332cf95da34e50e">More...</a><br/></td></tr>
<tr class="separator:gab4ac9a609c078d1e8332cf95da34e50e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5498eb08c2ba8de2e1c2801428e79d71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#ga5498eb08c2ba8de2e1c2801428e79d71">ARM_SPI_CPOL0_CPHA1</a>   (1UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:ga5498eb08c2ba8de2e1c2801428e79d71"><td class="mdescLeft"> </td><td class="mdescRight">Clock Polarity 0, Clock Phase 1. <a href="group__spi__frame__format__ctrls.html#ga5498eb08c2ba8de2e1c2801428e79d71">More...</a><br/></td></tr>
<tr class="separator:ga5498eb08c2ba8de2e1c2801428e79d71"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga67193d9b5af1ec312a66d007c33b597f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#ga67193d9b5af1ec312a66d007c33b597f">ARM_SPI_CPOL1_CPHA0</a>   (2UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:ga67193d9b5af1ec312a66d007c33b597f"><td class="mdescLeft"> </td><td class="mdescRight">Clock Polarity 1, Clock Phase 0. <a href="group__spi__frame__format__ctrls.html#ga67193d9b5af1ec312a66d007c33b597f">More...</a><br/></td></tr>
<tr class="separator:ga67193d9b5af1ec312a66d007c33b597f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7fab572b2fec303e979e47eb2d13ca74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#ga7fab572b2fec303e979e47eb2d13ca74">ARM_SPI_CPOL1_CPHA1</a>   (3UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:ga7fab572b2fec303e979e47eb2d13ca74"><td class="mdescLeft"> </td><td class="mdescRight">Clock Polarity 1, Clock Phase 1. <a href="group__spi__frame__format__ctrls.html#ga7fab572b2fec303e979e47eb2d13ca74">More...</a><br/></td></tr>
<tr class="separator:ga7fab572b2fec303e979e47eb2d13ca74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga225185710ba38848a489013ba4475915"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#ga225185710ba38848a489013ba4475915">ARM_SPI_TI_SSI</a>   (4UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:ga225185710ba38848a489013ba4475915"><td class="mdescLeft"> </td><td class="mdescRight">Texas Instruments Frame Format. <a href="group__spi__frame__format__ctrls.html#ga225185710ba38848a489013ba4475915">More...</a><br/></td></tr>
<tr class="separator:ga225185710ba38848a489013ba4475915"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga44f481d32b9a9ea93673f05af82ccf86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__frame__format__ctrls.html#ga44f481d32b9a9ea93673f05af82ccf86">ARM_SPI_MICROWIRE</a>   (5UL << ARM_SPI_FRAME_FORMAT_Pos)</td></tr>
<tr class="memdesc:ga44f481d32b9a9ea93673f05af82ccf86"><td class="mdescLeft"> </td><td class="mdescRight">National Microwire Frame Format. <a href="group__spi__frame__format__ctrls.html#ga44f481d32b9a9ea93673f05af82ccf86">More...</a><br/></td></tr>
<tr class="separator:ga44f481d32b9a9ea93673f05af82ccf86"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a89e1140c07c9805112b6de4541c3b59a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a89e1140c07c9805112b6de4541c3b59a">ARM_SPI_DATA_BITS_Pos</a>   12</td></tr>
<tr class="separator:a89e1140c07c9805112b6de4541c3b59a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0b6e14fe55f4d92ddab6ca230da77f46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a0b6e14fe55f4d92ddab6ca230da77f46">ARM_SPI_DATA_BITS_Msk</a>   (0x3FUL << ARM_SPI_DATA_BITS_Pos)</td></tr>
<tr class="separator:a0b6e14fe55f4d92ddab6ca230da77f46"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf6c099a1d67256a32010120c66c55250"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__data__bits__ctrls.html#gaf6c099a1d67256a32010120c66c55250">ARM_SPI_DATA_BITS</a>(n)   (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos)</td></tr>
<tr class="memdesc:gaf6c099a1d67256a32010120c66c55250"><td class="mdescLeft"> </td><td class="mdescRight">Number of Data bits. <a href="group__spi__data__bits__ctrls.html#gaf6c099a1d67256a32010120c66c55250">More...</a><br/></td></tr>
<tr class="separator:gaf6c099a1d67256a32010120c66c55250"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a84a8f90504df32ec77832a0285a47081"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a84a8f90504df32ec77832a0285a47081">ARM_SPI_BIT_ORDER_Pos</a>   18</td></tr>
<tr class="separator:a84a8f90504df32ec77832a0285a47081"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7d407682d2cb5a7fea5e38ae62fa42f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a7d407682d2cb5a7fea5e38ae62fa42f8">ARM_SPI_BIT_ORDER_Msk</a>   (1UL << ARM_SPI_BIT_ORDER_Pos)</td></tr>
<tr class="separator:a7d407682d2cb5a7fea5e38ae62fa42f8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga98228a708cbab6e214c7ac696f77dab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__bit__order__ctrls.html#ga98228a708cbab6e214c7ac696f77dab6">ARM_SPI_MSB_LSB</a>   (0UL << ARM_SPI_BIT_ORDER_Pos)</td></tr>
<tr class="memdesc:ga98228a708cbab6e214c7ac696f77dab6"><td class="mdescLeft"> </td><td class="mdescRight">SPI Bit order from MSB to LSB (default) <a href="group__spi__bit__order__ctrls.html#ga98228a708cbab6e214c7ac696f77dab6">More...</a><br/></td></tr>
<tr class="separator:ga98228a708cbab6e214c7ac696f77dab6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga41c53c3b396a89ce78018467e561aaaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__bit__order__ctrls.html#ga41c53c3b396a89ce78018467e561aaaf">ARM_SPI_LSB_MSB</a>   (1UL << ARM_SPI_BIT_ORDER_Pos)</td></tr>
<tr class="memdesc:ga41c53c3b396a89ce78018467e561aaaf"><td class="mdescLeft"> </td><td class="mdescRight">SPI Bit order from LSB to MSB. <a href="group__spi__bit__order__ctrls.html#ga41c53c3b396a89ce78018467e561aaaf">More...</a><br/></td></tr>
<tr class="separator:ga41c53c3b396a89ce78018467e561aaaf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac467bd067b72370b23546767e63ce693"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#ac467bd067b72370b23546767e63ce693">ARM_SPI_SS_MASTER_MODE_Pos</a>   19</td></tr>
<tr class="separator:ac467bd067b72370b23546767e63ce693"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaefa5b36525296a43071968cac43a4af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#aaefa5b36525296a43071968cac43a4af">ARM_SPI_SS_MASTER_MODE_Msk</a>   (3UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="separator:aaefa5b36525296a43071968cac43a4af"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae19343adc7bd71408b51733171f99dc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gae19343adc7bd71408b51733171f99dc7">ARM_SPI_SS_MASTER_UNUSED</a>   (0UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:gae19343adc7bd71408b51733171f99dc7"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Not used (default) <a href="group__spi__slave__select__mode__ctrls.html#gae19343adc7bd71408b51733171f99dc7">More...</a><br/></td></tr>
<tr class="separator:gae19343adc7bd71408b51733171f99dc7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab5e319aa3f9d4d8c9ed92f0fe865f624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gab5e319aa3f9d4d8c9ed92f0fe865f624">ARM_SPI_SS_MASTER_SW</a>   (1UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:gab5e319aa3f9d4d8c9ed92f0fe865f624"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Software controlled. <a href="group__spi__slave__select__mode__ctrls.html#gab5e319aa3f9d4d8c9ed92f0fe865f624">More...</a><br/></td></tr>
<tr class="separator:gab5e319aa3f9d4d8c9ed92f0fe865f624"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga07762709a40dc90aca85553f500c8761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga07762709a40dc90aca85553f500c8761">ARM_SPI_SS_MASTER_HW_OUTPUT</a>   (2UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:ga07762709a40dc90aca85553f500c8761"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Hardware controlled Output. <a href="group__spi__slave__select__mode__ctrls.html#ga07762709a40dc90aca85553f500c8761">More...</a><br/></td></tr>
<tr class="separator:ga07762709a40dc90aca85553f500c8761"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8561bd0cc25ab2bb02b138c1c6a586cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga8561bd0cc25ab2bb02b138c1c6a586cd">ARM_SPI_SS_MASTER_HW_INPUT</a>   (3UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:ga8561bd0cc25ab2bb02b138c1c6a586cd"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Hardware monitored Input. <a href="group__spi__slave__select__mode__ctrls.html#ga8561bd0cc25ab2bb02b138c1c6a586cd">More...</a><br/></td></tr>
<tr class="separator:ga8561bd0cc25ab2bb02b138c1c6a586cd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4aed772149cc33c6ee70663adef90956"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a4aed772149cc33c6ee70663adef90956">ARM_SPI_SS_SLAVE_MODE_Pos</a>   21</td></tr>
<tr class="separator:a4aed772149cc33c6ee70663adef90956"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2e9a0ac10df1b90b785c5d23079873e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a2e9a0ac10df1b90b785c5d23079873e0">ARM_SPI_SS_SLAVE_MODE_Msk</a>   (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td></tr>
<tr class="separator:a2e9a0ac10df1b90b785c5d23079873e0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2bd0d1f3ade2dc0cc48cc0593336ad70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga2bd0d1f3ade2dc0cc48cc0593336ad70">ARM_SPI_SS_SLAVE_HW</a>   (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td></tr>
<tr class="memdesc:ga2bd0d1f3ade2dc0cc48cc0593336ad70"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Slave: Hardware monitored (default) <a href="group__spi__slave__select__mode__ctrls.html#ga2bd0d1f3ade2dc0cc48cc0593336ad70">More...</a><br/></td></tr>
<tr class="separator:ga2bd0d1f3ade2dc0cc48cc0593336ad70"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad371f6ba0d12a57bdcc3217c351abfb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gad371f6ba0d12a57bdcc3217c351abfb0">ARM_SPI_SS_SLAVE_SW</a>   (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td></tr>
<tr class="memdesc:gad371f6ba0d12a57bdcc3217c351abfb0"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Slave: Software controlled. <a href="group__spi__slave__select__mode__ctrls.html#gad371f6ba0d12a57bdcc3217c351abfb0">More...</a><br/></td></tr>
<tr class="separator:gad371f6ba0d12a57bdcc3217c351abfb0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5ef3d114979f3fd6010d0df16c2bf5c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__misc__ctrls.html#ga5ef3d114979f3fd6010d0df16c2bf5c1">ARM_SPI_SET_BUS_SPEED</a>   (0x10UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga5ef3d114979f3fd6010d0df16c2bf5c1"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Speed in bps; arg = value. <a href="group__spi__misc__ctrls.html#ga5ef3d114979f3fd6010d0df16c2bf5c1">More...</a><br/></td></tr>
<tr class="separator:ga5ef3d114979f3fd6010d0df16c2bf5c1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafc00fe35bb4c89b076d014b43168b2b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__misc__ctrls.html#gafc00fe35bb4c89b076d014b43168b2b3">ARM_SPI_GET_BUS_SPEED</a>   (0x11UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:gafc00fe35bb4c89b076d014b43168b2b3"><td class="mdescLeft"> </td><td class="mdescRight">Get Bus Speed in bps. <a href="group__spi__misc__ctrls.html#gafc00fe35bb4c89b076d014b43168b2b3">More...</a><br/></td></tr>
<tr class="separator:gafc00fe35bb4c89b076d014b43168b2b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae9861221dee78d52bd1522b7846535ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__misc__ctrls.html#gae9861221dee78d52bd1522b7846535ce">ARM_SPI_SET_DEFAULT_TX_VALUE</a>   (0x12UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:gae9861221dee78d52bd1522b7846535ce"><td class="mdescLeft"> </td><td class="mdescRight">Set default Transmit value; arg = value. <a href="group__spi__misc__ctrls.html#gae9861221dee78d52bd1522b7846535ce">More...</a><br/></td></tr>
<tr class="separator:gae9861221dee78d52bd1522b7846535ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5776272b82decff92da003568540c92f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>   (0x13UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga5776272b82decff92da003568540c92f"><td class="mdescLeft"> </td><td class="mdescRight">Control Slave Select; arg: 0=inactive, 1=active. <a href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">More...</a><br/></td></tr>
<tr class="separator:ga5776272b82decff92da003568540c92f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga44708b80e48984be099cd6eb11780dc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__misc__ctrls.html#ga44708b80e48984be099cd6eb11780dc3">ARM_SPI_ABORT_TRANSFER</a>   (0x14UL << ARM_SPI_CONTROL_Pos)</td></tr>
<tr class="memdesc:ga44708b80e48984be099cd6eb11780dc3"><td class="mdescLeft"> </td><td class="mdescRight">Abort current data transfer. <a href="group__spi__misc__ctrls.html#ga44708b80e48984be099cd6eb11780dc3">More...</a><br/></td></tr>
<tr class="separator:ga44708b80e48984be099cd6eb11780dc3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a335b448e07422e9c25616a693ec581cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a335b448e07422e9c25616a693ec581cc">ARM_SPI_SS_INACTIVE</a>   0</td></tr>
<tr class="memdesc:a335b448e07422e9c25616a693ec581cc"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select Signal Inactive. <a href="#a335b448e07422e9c25616a693ec581cc">More...</a><br/></td></tr>
<tr class="separator:a335b448e07422e9c25616a693ec581cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3f465cdbd1238ddd74f78e14457076c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__SPI_8h.html#a3f465cdbd1238ddd74f78e14457076c4">ARM_SPI_SS_ACTIVE</a>   1</td></tr>
<tr class="memdesc:a3f465cdbd1238ddd74f78e14457076c4"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select Signal Active. <a href="#a3f465cdbd1238ddd74f78e14457076c4">More...</a><br/></td></tr>
<tr class="separator:a3f465cdbd1238ddd74f78e14457076c4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga273a55c5d19491c565e5f05d03d66f3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__execution__status.html#ga273a55c5d19491c565e5f05d03d66f3f">ARM_SPI_ERROR_MODE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td></tr>
<tr class="memdesc:ga273a55c5d19491c565e5f05d03d66f3f"><td class="mdescLeft"> </td><td class="mdescRight">Specified Mode not supported. <a href="group__spi__execution__status.html#ga273a55c5d19491c565e5f05d03d66f3f">More...</a><br/></td></tr>
<tr class="separator:ga273a55c5d19491c565e5f05d03d66f3f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac47584fe5691889c056611bc589b25aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__execution__status.html#gac47584fe5691889c056611bc589b25aa">ARM_SPI_ERROR_FRAME_FORMAT</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 2)</td></tr>
<tr class="memdesc:gac47584fe5691889c056611bc589b25aa"><td class="mdescLeft"> </td><td class="mdescRight">Specified Frame Format not supported. <a href="group__spi__execution__status.html#gac47584fe5691889c056611bc589b25aa">More...</a><br/></td></tr>
<tr class="separator:gac47584fe5691889c056611bc589b25aa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga76f895d3380ca474124f83acbebc5651"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__execution__status.html#ga76f895d3380ca474124f83acbebc5651">ARM_SPI_ERROR_DATA_BITS</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 3)</td></tr>
<tr class="memdesc:ga76f895d3380ca474124f83acbebc5651"><td class="mdescLeft"> </td><td class="mdescRight">Specified number of Data bits not supported. <a href="group__spi__execution__status.html#ga76f895d3380ca474124f83acbebc5651">More...</a><br/></td></tr>
<tr class="separator:ga76f895d3380ca474124f83acbebc5651"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6b8ac31930ea6ca3a9635f2ac935466d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__execution__status.html#ga6b8ac31930ea6ca3a9635f2ac935466d">ARM_SPI_ERROR_BIT_ORDER</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 4)</td></tr>
<tr class="memdesc:ga6b8ac31930ea6ca3a9635f2ac935466d"><td class="mdescLeft"> </td><td class="mdescRight">Specified Bit order not supported. <a href="group__spi__execution__status.html#ga6b8ac31930ea6ca3a9635f2ac935466d">More...</a><br/></td></tr>
<tr class="separator:ga6b8ac31930ea6ca3a9635f2ac935466d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaae7b1a1feb46faa1830c92b73bd775ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__execution__status.html#gaae7b1a1feb46faa1830c92b73bd775ad">ARM_SPI_ERROR_SS_MODE</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 5)</td></tr>
<tr class="memdesc:gaae7b1a1feb46faa1830c92b73bd775ad"><td class="mdescLeft"> </td><td class="mdescRight">Specified Slave Select Mode not supported. <a href="group__spi__execution__status.html#gaae7b1a1feb46faa1830c92b73bd775ad">More...</a><br/></td></tr>
<tr class="separator:gaae7b1a1feb46faa1830c92b73bd775ad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaabdfc9e17641144cd50d36d15511a1b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPI__events.html#gaabdfc9e17641144cd50d36d15511a1b8">ARM_SPI_EVENT_TRANSFER_COMPLETE</a>   (1UL << 0)</td></tr>
<tr class="memdesc:gaabdfc9e17641144cd50d36d15511a1b8"><td class="mdescLeft"> </td><td class="mdescRight">Data Transfer completed. <a href="group__SPI__events.html#gaabdfc9e17641144cd50d36d15511a1b8">More...</a><br/></td></tr>
<tr class="separator:gaabdfc9e17641144cd50d36d15511a1b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8e63d99c80ea56de596a8d0a51fd8244"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPI__events.html#ga8e63d99c80ea56de596a8d0a51fd8244">ARM_SPI_EVENT_DATA_LOST</a>   (1UL << 1)</td></tr>
<tr class="memdesc:ga8e63d99c80ea56de596a8d0a51fd8244"><td class="mdescLeft"> </td><td class="mdescRight">Data lost: Receive overflow / Transmit underflow. <a href="group__SPI__events.html#ga8e63d99c80ea56de596a8d0a51fd8244">More...</a><br/></td></tr>
<tr class="separator:ga8e63d99c80ea56de596a8d0a51fd8244"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7eaa229003689aa18598273490b3e630"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPI__events.html#ga7eaa229003689aa18598273490b3e630">ARM_SPI_EVENT_MODE_FAULT</a>   (1UL << 2)</td></tr>
<tr class="memdesc:ga7eaa229003689aa18598273490b3e630"><td class="mdescLeft"> </td><td class="mdescRight">Master Mode Fault (SS deactivated when Master) <a href="group__SPI__events.html#ga7eaa229003689aa18598273490b3e630">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gafde9205364241ee81290adc0481c6640"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__interface__gr.html#gafde9205364241ee81290adc0481c6640">ARM_SPI_SignalEvent_t</a> )(uint32_t event)</td></tr>
<tr class="memdesc:gafde9205364241ee81290adc0481c6640"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__spi__interface__gr.html#ga505b2d787348d51351d38fee98ccba7e">ARM_SPI_SignalEvent</a> : Signal SPI Event. <a href="group__spi__interface__gr.html#gafde9205364241ee81290adc0481c6640">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="acf1275c15e53a573d7db89da66839d97"></a>
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<td class="memname">#define ARM_SPI_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td>
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</div><div class="memdoc">
</div>
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<td class="memname">#define ARM_SPI_CONTROL_Pos   0</td>
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<td class="memname">#define ARM_SPI_CONTROL_Msk   (0xFFUL << ARM_SPI_CONTROL_Pos)</td>
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</div>
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<td class="memname">#define ARM_SPI_FRAME_FORMAT_Pos   8</td>
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</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define ARM_SPI_FRAME_FORMAT_Msk   (7UL << ARM_SPI_FRAME_FORMAT_Pos)</td>
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</div><div class="memdoc">
</div>
</div>
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<td class="memname">#define ARM_SPI_DATA_BITS_Pos   12</td>
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</div>
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<a class="anchor" id="a0b6e14fe55f4d92ddab6ca230da77f46"></a>
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<td class="memname">#define ARM_SPI_DATA_BITS_Msk   (0x3FUL << ARM_SPI_DATA_BITS_Pos)</td>
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</div><div class="memdoc">
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<td class="memname">#define ARM_SPI_BIT_ORDER_Pos   18</td>
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</div><div class="memdoc">
</div>
</div>
<a class="anchor" id="a7d407682d2cb5a7fea5e38ae62fa42f8"></a>
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<td class="memname">#define ARM_SPI_BIT_ORDER_Msk   (1UL << ARM_SPI_BIT_ORDER_Pos)</td>
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<td class="memname">#define ARM_SPI_SS_MASTER_MODE_Pos   19</td>
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<td class="memname">#define ARM_SPI_SS_MASTER_MODE_Msk   (3UL << ARM_SPI_SS_MASTER_MODE_Pos)</td>
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<td class="memname">#define ARM_SPI_SS_SLAVE_MODE_Pos   21</td>
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</div><div class="memdoc">
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<a class="anchor" id="a2e9a0ac10df1b90b785c5d23079873e0"></a>
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<td class="memname">#define ARM_SPI_SS_SLAVE_MODE_Msk   (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td>
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<td class="memname">#define ARM_SPI_SS_INACTIVE   0</td>
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</div><div class="memdoc">
<p>SPI Slave Select Signal Inactive. </p>
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<td class="memname">#define ARM_SPI_SS_ACTIVE   1</td>
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<p>SPI Slave Select Signal Active. </p>
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Functions</h2></td></tr>
<tr class="memitem:gaf28193431b1a2ee64b22bfb36aed27e3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gaf28193431b1a2ee64b22bfb36aed27e3">ARM_Storage_GetVersion</a> (void)</td></tr>
<tr class="memdesc:gaf28193431b1a2ee64b22bfb36aed27e3"><td class="mdescLeft"> </td><td class="mdescRight">Get driver version. <a href="group__storage__interface__gr.html#gaf28193431b1a2ee64b22bfb36aed27e3">More...</a><br/></td></tr>
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<tr class="memitem:ga8378b3901dfe76d8f31728a50e10dae2"><td class="memItemLeft" align="right" valign="top">ARM_STOR_CAPABILITIES </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga8378b3901dfe76d8f31728a50e10dae2">ARM_Storage_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga8378b3901dfe76d8f31728a50e10dae2"><td class="mdescLeft"> </td><td class="mdescRight">Get driver capabilities. <a href="group__storage__interface__gr.html#ga8378b3901dfe76d8f31728a50e10dae2">More...</a><br/></td></tr>
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<tr class="memitem:gacc5dc090a35ac16caff8957030eaa174"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gacc5dc090a35ac16caff8957030eaa174">ARM_Storage_Initialize</a> (<a class="el" href="group__storage__interface__gr.html#ga4b290224fea782e6d2ad06f541b28a98">ARM_Storage_Callback_t</a> callback)</td></tr>
<tr class="memdesc:gacc5dc090a35ac16caff8957030eaa174"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the Storage interface. <a href="group__storage__interface__gr.html#gacc5dc090a35ac16caff8957030eaa174">More...</a><br/></td></tr>
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<tr class="memitem:ga1d14b15ddcda2836c6e3c1d0b5e60dca"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga1d14b15ddcda2836c6e3c1d0b5e60dca">ARM_Storage_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:ga1d14b15ddcda2836c6e3c1d0b5e60dca"><td class="mdescLeft"> </td><td class="mdescRight">De-initialize the Storage Interface. <a href="group__storage__interface__gr.html#ga1d14b15ddcda2836c6e3c1d0b5e60dca">More...</a><br/></td></tr>
<tr class="separator:ga1d14b15ddcda2836c6e3c1d0b5e60dca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga979a2484bf05b2986de95a5d98307d54"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga979a2484bf05b2986de95a5d98307d54">ARM_Storage_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga979a2484bf05b2986de95a5d98307d54"><td class="mdescLeft"> </td><td class="mdescRight">Control the Storage interface power. <a href="group__storage__interface__gr.html#ga979a2484bf05b2986de95a5d98307d54">More...</a><br/></td></tr>
<tr class="separator:ga979a2484bf05b2986de95a5d98307d54"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabaa24553c165add98020434c980b3ab4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gabaa24553c165add98020434c980b3ab4">ARM_Storage_ReadData</a> (uint64_t addr, void *data, uint32_t size)</td></tr>
<tr class="memdesc:gabaa24553c165add98020434c980b3ab4"><td class="mdescLeft"> </td><td class="mdescRight">Read data from Storage. <a href="group__storage__interface__gr.html#gabaa24553c165add98020434c980b3ab4">More...</a><br/></td></tr>
<tr class="separator:gabaa24553c165add98020434c980b3ab4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd20d561854c06918b0515b6c1bba230"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gabd20d561854c06918b0515b6c1bba230">ARM_Storage_ProgramData</a> (uint64_t addr, const void *data, uint32_t size)</td></tr>
<tr class="memdesc:gabd20d561854c06918b0515b6c1bba230"><td class="mdescLeft"> </td><td class="mdescRight">Program data to Storage. <a href="group__storage__interface__gr.html#gabd20d561854c06918b0515b6c1bba230">More...</a><br/></td></tr>
<tr class="separator:gabd20d561854c06918b0515b6c1bba230"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaceef4851d9181cce65c8b2d05f4429bc"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gaceef4851d9181cce65c8b2d05f4429bc">ARM_Storage_Erase</a> (uint64_t addr, uint32_t size)</td></tr>
<tr class="memdesc:gaceef4851d9181cce65c8b2d05f4429bc"><td class="mdescLeft"> </td><td class="mdescRight">Erase Storage range. <a href="group__storage__interface__gr.html#gaceef4851d9181cce65c8b2d05f4429bc">More...</a><br/></td></tr>
<tr class="separator:gaceef4851d9181cce65c8b2d05f4429bc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga04e77387a3c628d6fc661e82f7daddaa"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga04e77387a3c628d6fc661e82f7daddaa">ARM_Storage_EraseAll</a> (void)</td></tr>
<tr class="memdesc:ga04e77387a3c628d6fc661e82f7daddaa"><td class="mdescLeft"> </td><td class="mdescRight">Erase complete Storage. <a href="group__storage__interface__gr.html#ga04e77387a3c628d6fc661e82f7daddaa">More...</a><br/></td></tr>
<tr class="separator:ga04e77387a3c628d6fc661e82f7daddaa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga29e7bfe78f41abb16973bdb4e0188a20"><td class="memItemLeft" align="right" valign="top">ARM_Storage_STATUS </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga29e7bfe78f41abb16973bdb4e0188a20">ARM_Storage_GetStatus</a> (void)</td></tr>
<tr class="memdesc:ga29e7bfe78f41abb16973bdb4e0188a20"><td class="mdescLeft"> </td><td class="mdescRight">Get Storage status. <a href="group__storage__interface__gr.html#ga29e7bfe78f41abb16973bdb4e0188a20">More...</a><br/></td></tr>
<tr class="separator:ga29e7bfe78f41abb16973bdb4e0188a20"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad557e8e6e33cd4528d398ecf4dddc747"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gad557e8e6e33cd4528d398ecf4dddc747">ARM_Storage_GetInfo</a> (<a class="el" href="group__storage__interface__gr.html#structARM__STORAGE__INFO">ARM_STORAGE_INFO</a> *info)</td></tr>
<tr class="memdesc:gad557e8e6e33cd4528d398ecf4dddc747"><td class="mdescLeft"> </td><td class="mdescRight">Get Storage information. <a href="group__storage__interface__gr.html#gad557e8e6e33cd4528d398ecf4dddc747">More...</a><br/></td></tr>
<tr class="separator:gad557e8e6e33cd4528d398ecf4dddc747"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a1934750a51c74b8b0fea52588a3b9a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga5a1934750a51c74b8b0fea52588a3b9a">ARM_Storage_ResolveAddress</a> (uint64_t addr)</td></tr>
<tr class="memdesc:ga5a1934750a51c74b8b0fea52588a3b9a"><td class="mdescLeft"> </td><td class="mdescRight">Resolve an address relative to the storage controller into a memory address. <a href="group__storage__interface__gr.html#ga5a1934750a51c74b8b0fea52588a3b9a">More...</a><br/></td></tr>
<tr class="separator:ga5a1934750a51c74b8b0fea52588a3b9a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad318f8cb38626cbeea1fcf36a0977c44"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#gad318f8cb38626cbeea1fcf36a0977c44">ARM_Storage_GetNextBlock</a> (const <a class="el" href="group__storage__interface__gr.html#structARM__STORAGE__BLOCK">ARM_STORAGE_BLOCK</a> *prev_block, <a class="el" href="group__storage__interface__gr.html#structARM__STORAGE__BLOCK">ARM_STORAGE_BLOCK</a> *next_block)</td></tr>
<tr class="memdesc:gad318f8cb38626cbeea1fcf36a0977c44"><td class="mdescLeft"> </td><td class="mdescRight">Advance to the successor of the current block (iterator). <a href="group__storage__interface__gr.html#gad318f8cb38626cbeea1fcf36a0977c44">More...</a><br/></td></tr>
<tr class="separator:gad318f8cb38626cbeea1fcf36a0977c44"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5fe9d27ce8afe65124dec62566114073"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__storage__interface__gr.html#ga5fe9d27ce8afe65124dec62566114073">ARM_Storage_GetBlock</a> (uint64_t addr, <a class="el" href="group__storage__interface__gr.html#structARM__STORAGE__BLOCK">ARM_STORAGE_BLOCK</a> *block)</td></tr>
<tr class="memdesc:ga5fe9d27ce8afe65124dec62566114073"><td class="mdescLeft"> </td><td class="mdescRight">Find the storage block (iterator) encompassing a given storage address. <a href="group__storage__interface__gr.html#ga5fe9d27ce8afe65124dec62566114073">More...</a><br/></td></tr>
<tr class="separator:ga5fe9d27ce8afe65124dec62566114073"><td class="memSeparator" colspan="2"> </td></tr>
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