file_text stringlengths 1 2.1M ⌀ | language stringclasses 416
values | file_name stringlengths 1 185 ⌀ |
|---|---|---|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-- -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the x87 fpsw and fpcw regs
--- |
declare float @llvm.sqrt.f32(float)
define void @f1(float* %a, fl... | YAML | x87-reg-usage.mir |
name: timeout_service
display_name: Timeout Service
component_type: null
model_type: null
is_customizable: false
author: publisher@deeppavlov.ai
description: Timeout Service
ram_usage: 100M
gpu_usage: null
group: timeout_service
connector:
protocol: python
class_name: PredefinedTextConnector
response_text: Sorry,... | YAML | x8rLTpIWct4P.yml |
name: rule_based_selector
display_name: Rule-based Skill Selector
component_type: null
model_type: Dictionary/Pattern-based
is_customizable: false
author: publisher@deeppavlov.ai
description: Algorithm that selects list of skills to generate candidate responses
to the current context based on topics, entities, emotio... | YAML | xSwFvtAUdvtQosvzpb7oMg.yml |
---
abstract: 'Author tests making sure correct line endings are used'
author:
- 'Florian Ragwitz <rafl@debian.org>'
- 'Caleb Cushing <xenoterracide@gmail.com>'
- 'Karen Etheridge <ether@cpan.org>'
build_requires:
Build::Requires: '1.1'
Test::More: '0.88'
Test::Requires: '1.2'
configure_requires:
Module::... | YAML | x_deprecated-META.yml |
---
title: XCMetrics
author: Spotify
authorUrl: https://github.com/spotify
category: Monitoring
description: Discover valuable insights hiding inside Xcode’s build logs.
documentation: https://xcmetrics.io/
iconUrl: /img/xcmetrics-icon.png
npmPackageName: '@backstage/plugin-xcmetrics'
addedDate: '2021-08-06'
| YAML | xcmetrics.yaml |
metrics:
counters:
- name: xdp_incoming_packets_total
help: Incoming packets going through xdp by protocol and port
labels:
- name: ip
size: 2
decoders:
- name: uint
- name: static_map
static_map:
2048: ipv4
... | YAML | xdp.yaml |
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/xen,grant-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xen specific IOMMU for virtualized devices (e.g. virtio)
maintainers:
- Stefano Stabellini <sstabellini@kernel.org>
desc... | YAML | xen,grant-dma.yaml |
# An example finetuning Saleforce's XGen-7b model with 8k context using qlora
# on Tim Dettmer's Guanaco dataset.
base_model: Salesforce/xgen-7b-8k-base
trust_remote_code: true
model_type: AutoModelForCausalLM
tokenizer_type: AutoTokenizer
load_in_8bit: false
# enable 4bit for QLoRA
load_in_4bit: true
gptq: false
stric... | YAML | xgen-7b-8k-qlora.yml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title:
Xilinx Axi CAN/Zynq CANPS controller
maintainers:
- Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
properti... | YAML | xilinx,can.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.c... | YAML | xilinx-versal-cpm.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.c... | YAML | xilinx-versal-cpm_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.c... | YAML | xilinx-versal-cpm_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.c... | YAML | xilinx-versal-cpm_3.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq FPGA Manager
maintainers:
- Michal Simek <michal.simek@xilinx.com>
properties:
compatible:
const: xln... | YAML | xilinx-zynq-fpga-mgr.yaml |
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms Device Tree Bindings
maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zy... | YAML | xilinx.yaml |
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
... | YAML | xilinx_1.yaml |
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms Device Tree Bindings
maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zy... | YAML | xilinx_2.yaml |
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms Device Tree Bindings
maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zy... | YAML | xilinx_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
maintainers:
- Heiko Stuebner <heiko.stuebner@theobroma-systems.... | YAML | xinpeng,xpp055c272.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
maintainers:
- Heiko Stuebner <heiko.stuebner@theobroma-systems.... | YAML | xinpeng,xpp055c272_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
maintainers:
- Heiko Stuebner <heiko.stuebner@theobroma-systems.... | YAML | xinpeng,xpp055c272_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/xinpeng,xpp055c272.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
maintainers:
- Heiko Stuebner <heiko.stuebner@theobroma-systems.... | YAML | xinpeng,xpp055c272_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xiphera XIP8001B-trng bindings
maintainers:
- Atte Tommiska <atte.tommiska@xiphera.com>
description: |
Xiphera F... | YAML | xiphera,xip8001b-trng.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xiphera XIP8001B-trng
maintainers:
- Atte Tommiska <atte.tommiska@xiphera.com>
description: |
Xiphera FPGA-based... | YAML | xiphera,xip8001b-trng_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xiphera XIP8001B-trng bindings
maintainers:
- Atte Tommiska <atte.tommiska@xiphera.com>
description: |
Xiphera F... | YAML | xiphera,xip8001b-trng_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xiphera XIP8001B-trng bindings
maintainers:
- Atte Tommiska <atte.tommiska@xiphera.com>
description: |
Xiphera F... | YAML | xiphera,xip8001b-trng_3.yaml |
---
title: xkcd comic
author: Vity
authorUrl: https://github.com/Vity01
category: Humor
description: xkcd comic within Backstage
documentation: https://github.com/Vity01/backstage-xkcd/
iconUrl: https://raw.githubusercontent.com/Vity01/backstage-xkcd/main/docs/xkcd.svg
npmPackageName: 'backstage-plugin-xkcd'
addedDate:... | YAML | xkcd.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI PCIe Root Port Bridge
maintainers:
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
allOf:
- $ref: ... | YAML | xlnx,axi-pcie-host.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
description:
The c... | YAML | xlnx,clocking-wizard.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
description: |
The X... | YAML | xlnx,csi2rxss.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
description: |
The X... | YAML | xlnx,csi2rxss_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
description: |
The X... | YAML | xlnx,csi2rxss_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
description: |
The X... | YAML | xlnx,csi2rxss_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/xlnx,emaclite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Emaclite Ethernet controller
maintainers:
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
- Harini Katakam <ha... | YAML | xlnx,emaclite.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI GPIO controller
maintainers:
- Neeli Srinivas <srinivas.neeli@xilinx.com>
description:
The AXI GPIO design pro... | YAML | xlnx,gpio-xilinx.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx NWL PCIe Root Port Bridge
maintainers:
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
allOf:
- $ref: /sche... | YAML | xlnx,nwl-pcie.yaml |
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Axi Uartlite
maintainers:
- Peter Korsgaard <jacmet@sunsite.dk>
properties:
compatible:
contains:
enum:... | YAML | xlnx,opb-uartlite.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Triple Modular Redundancy(TMR) Inject IP
maintainers:
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd... | YAML | xlnx,tmr-inject.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Triple Modular Redundancy(TMR) Manager IP
maintainers:
- Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@a... | YAML | xlnx,tmr-manager.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/xlnx,usb2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx udc controller
maintainers:
- Manish Narani <manish.narani@xilinx.com>
properties:
compatible:
const: xlnx,usb2-d... | YAML | xlnx,usb2.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/xilinx/xlnx,vcu-settings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx VCU Settings
maintainers:
- Michael Tretter <kernel@pengutronix.de>
description: |
The Xilinx VCU Settings ... | YAML | xlnx,vcu-settings.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
... | YAML | xlnx,versal-clk.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
... | YAML | xlnx,versal-clk_1.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
... | YAML | xlnx,versal-clk_2.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
... | YAML | xlnx,versal-clk_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal FPGA driver.
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
description: |
Device Tree Vers... | YAML | xlnx,versal-fpga.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ilinx IIC controller Device Tree Bindings
maintainers:
- info@mocean-labs.com
allOf:
- $ref: /schemas/i2c/i2c-contr... | YAML | xlnx,xps-iic-2.00.a.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx IIC controller
maintainers:
- info@mocean-labs.com
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
propert... | YAML | xlnx,xps-iic-2.00.a_1.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ilinx IIC controller Device Tree Bindings
maintainers:
- info@mocean-labs.com
allOf:
- $ref: /schemas/i2c/i2c-contr... | YAML | xlnx,xps-iic-2.00.a_2.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ilinx IIC controller Device Tree Bindings
maintainers:
- info@mocean-labs.com
allOf:
- $ref: /schemas/i2c/i2c-contr... | YAML | xlnx,xps-iic-2.00.a_3.yaml |
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI/PLB softcore and window Watchdog Timer
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xili... | YAML | xlnx,xps-timebase-wdt.yaml |
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx LogiCORE IP AXI Timer
maintainers:
- Sean Anderson <sean.anderson@seco.com>
properties:
compatible:
contains:
... | YAML | xlnx,xps-timer.yaml |
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq A05 DDR Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <ma... | YAML | xlnx,zynq-ddrc-a05.yaml |
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
description: |
P... | YAML | xlnx,zynq-pinctrl.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq QSPI controller
description:
The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
memory... | YAML | xlnx,zynq-qspi.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com... | YAML | xlnx,zynqmp-aes.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com>
- Michal Simek <m... | YAML | xlnx,zynqmp-aes_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com... | YAML | xlnx,zynqmp-aes_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com... | YAML | xlnx,zynqmp-aes_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale AMS controller
maintainers:
- Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
description:... | YAML | xlnx,zynqmp-ams.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DMA Engine
description: |
The Xilinx ZynqMP DMA engine supports memory to memory transfers,
me... | YAML | xlnx,zynqmp-dma-1.0.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
description: |
These bindings describe the DMA eng... | YAML | xlnx,zynqmp-dpdma.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort DMA Controller
description: |
These bindings describe the DMA engine included in the X... | YAML | xlnx,zynqmp-dpdma_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
description: |
These bindings describe the DMA eng... | YAML | xlnx,zynqmp-dpdma_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
description: |
These bindings describe the DMA eng... | YAML | xlnx,zynqmp-dpdma_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort Subsystem
description: |
The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale... | YAML | xlnx,zynqmp-dpsub.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort Subsystem
description: |
The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale... | YAML | xlnx,zynqmp-dpsub_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort Subsystem
description: |
The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale... | YAML | xlnx,zynqmp-dpsub_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DisplayPort Subsystem
description: |
The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale... | YAML | xlnx,zynqmp-dpsub_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx firmware driver
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
description: The zynqm... | YAML | xlnx,zynqmp-firmware.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ZynqMP Mode Pin GPIO controller
description:
PS_MODE is 4-bits boot mode pins sampled on POR deassertion. M... | YAML | xlnx,zynqmp-gpio-modepin.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
description: |
The Xilinx IPI(Inter Processor In... | YAML | xlnx,zynqmp-ipi-mailbox.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com... | YAML | xlnx,zynqmp-ocmc-1.0.yaml |
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
maintainers:
- Nava kishore Manne <navam@xilinx.com>
description: |
Device... | YAML | xlnx,zynqmp-pcap-fpga.yaml |
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Rajan Vaja ... | YAML | xlnx,zynqmp-pinctrl.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq MPSoC Power Management
maintainers:
- Michal Simek <michal.simek@xilinx.com>
description: |
The ... | YAML | xlnx,zynqmp-power.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
maintainers:
- Laurent Pinchart <laurent.pinchart@ideasonboa... | YAML | xlnx,zynqmp-psgtr.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Gigabit Transceiver PHY
maintainers:
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
description:... | YAML | xlnx,zynqmp-psgtr_1.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
maintainers:
- Laurent Pinchart <laurent.pinchart@ideasonboa... | YAML | xlnx,zynqmp-psgtr_2.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
maintainers:
- Laurent Pinchart <laurent.pinchart@ideasonboa... | YAML | xlnx,zynqmp-psgtr_3.yaml |
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx R5F processor subsystem
maintainers:
- Ben Levinsky <ben.levinsky@amd.com>
- Tanmay Shah <tanmay.shah@a... | YAML | xlnx,zynqmp-r5fss.yaml |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
description:
RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
Th... | YAML | xlnx,zynqmp-rtc.yaml |
type: MeshGateway
mesh: mesh-2
name: edge-gateway
selectors:
- match:
kuma.io/service: edge-gateway
conf:
listeners:
- port: 8080
protocol: HTTP
crossMesh: true
hostname: bar.example.com
tags:
port: http/8080
| YAML | xmesh-gateway-change.change.yaml |
# mesh-1 true
type: Mesh
name: mesh-1
---
type: Mesh
name: mesh-2
---
type: Dataplane
name: gw-1
mesh: mesh-2
networking:
address: 127.0.0.1
gateway:
type: BUILTIN
tags:
kuma.io/service: edge-gateway
---
type: MeshGateway
mesh: mesh-2
name: edge-gateway
selectors:
- match:
kuma.io/service: edg... | YAML | xmesh-gateway-change.input.yaml |
type: Dataplane
name: gw-1
mesh: mesh-2
networking:
address: 127.0.0.1
gateway:
type: BUILTIN
tags:
kuma.io/service: edge-gateway
foo: bar
| YAML | xmesh-gateway-dp-change.change.yaml |
# mesh-1 true
type: Mesh
name: mesh-1
---
type: Mesh
name: mesh-2
---
type: Dataplane
name: gw-1
mesh: mesh-2
networking:
address: 127.0.0.1
gateway:
type: BUILTIN
tags:
kuma.io/service: edge-gateway
---
type: MeshGateway
mesh: mesh-2
name: edge-gateway
selectors:
- match:
kuma.io/service: edg... | YAML | xmesh-gateway-dp-change.input.yaml |
# Generated by utils.py
dataset_name: ar
doc_to_choice: '{{[premise+", صحيح? نعم, "+hypothesis,premise+", صحيح? لذا, "+hypothesis,premise+",
صحيح? رقم, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_ar
| YAML | xnli_ar.yaml |
# Generated by utils.py
dataset_name: bg
doc_to_choice: '{{[premise+", правилно? да, "+hypothesis,premise+", правилно? така,
"+hypothesis,premise+", правилно? не, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_bg
| YAML | xnli_bg.yaml |
# Generated by utils.py
dataset_name: de
doc_to_choice: '{{[premise+", richtig? Ja, "+hypothesis,premise+", richtig? Auch,
"+hypothesis,premise+", richtig? Nein, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_de
| YAML | xnli_de.yaml |
# Generated by utils.py
dataset_name: el
doc_to_choice: '{{[premise+", σωστός? Ναί, "+hypothesis,premise+", σωστός? Έτσι, "+hypothesis,premise+",
σωστός? όχι, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_el
| YAML | xnli_el.yaml |
# Generated by utils.py
dataset_name: en
doc_to_choice: '{{[premise+", right? Yes, "+hypothesis,premise+", right? Also, "+hypothesis,premise+",
right? No, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_en
| YAML | xnli_en.yaml |
# Generated by utils.py
dataset_name: es
doc_to_choice: '{{[premise+", correcto? Sí, "+hypothesis,premise+", correcto? Asi
que, "+hypothesis,premise+", correcto? No, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_es
| YAML | xnli_es.yaml |
# Generated by utils.py
dataset_name: fr
doc_to_choice: '{{[premise+", correct? Oui, "+hypothesis,premise+", correct? Aussi,
"+hypothesis,premise+", correct? Non, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_fr
| YAML | xnli_fr.yaml |
# Generated by utils.py
dataset_name: hi
doc_to_choice: '{{[premise+", सही? हाँ, "+hypothesis,premise+", सही? इसलिए, "+hypothesis,premise+",
सही? नहीं, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_hi
| YAML | xnli_hi.yaml |
# Generated by utils.py
dataset_name: ru
doc_to_choice: '{{[premise+", правильно? Да, "+hypothesis,premise+", правильно? Так,
"+hypothesis,premise+", правильно? Нет, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_ru
| YAML | xnli_ru.yaml |
# Generated by utils.py
dataset_name: sw
doc_to_choice: '{{[premise+", sahihi? Ndiyo, "+hypothesis,premise+", sahihi? Hivyo,
"+hypothesis,premise+", sahihi? Hapana, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_sw
| YAML | xnli_sw.yaml |
# Generated by utils.py
dataset_name: th
doc_to_choice: '{{[premise+", ถูกต้อง? ใช่, "+hypothesis,premise+", ถูกต้อง? ดังนั้น,
"+hypothesis,premise+", ถูกต้อง? ไม่, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_th
| YAML | xnli_th.yaml |
# Generated by utils.py
dataset_name: tr
doc_to_choice: '{{[premise+", doğru? Evet, "+hypothesis,premise+", doğru? Böylece,
"+hypothesis,premise+", doğru? Hayır, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_tr
| YAML | xnli_tr.yaml |
# Generated by utils.py
dataset_name: ur
doc_to_choice: '{{[premise+", صحیح? جی ہاں, "+hypothesis,premise+", صحیح? اس لئے,
"+hypothesis,premise+", صحیح? نہیں, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_ur
| YAML | xnli_ur.yaml |
# Generated by utils.py
dataset_name: vi
doc_to_choice: '{{[premise+", đúng? Vâng, "+hypothesis,premise+", đúng? Vì vậy, "+hypothesis,premise+",
đúng? Không, "+hypothesis]}}'
doc_to_text: ''
include: xnli_common_yaml
task: xnli_vi
| YAML | xnli_vi.yaml |
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