Proof Assistant Projects
Collection
Digesting proof assistant libraries for AI ingestion.
•
79 items
•
Updated
•
2
Datasets:
fact
stringlengths 7
4.84k
| type
stringclasses 18
values | library
stringclasses 14
values | imports
listlengths 0
27
| filename
stringclasses 205
values | symbolic_name
stringlengths 1
49
| docstring
stringlengths 6
2.5k
⌀ |
|---|---|---|---|---|---|---|
ptr64 := true.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
ptr64
| null |
big_endian := false.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
big_endian
| null |
align_int64 := 8%Z.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
align_int64
| null |
align_float64 := 8%Z.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
align_float64
| null |
splitlong := false.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
splitlong
| null |
splitlong_ptr32: splitlong = true -> ptr64 = false.
|
Lemma
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
splitlong_ptr32
| null |
default_nan_64 := (false, iter_nat 51 _ xO xH).
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
default_nan_64
| null |
default_nan_32 := (false, iter_nat 22 _ xO xH).
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
default_nan_32
| null |
choose_nan (is_signaling: positive -> bool)
(default: bool * positive)
(l0: list (bool * positive)) : bool * positive :=
let fix choose_snan (l1: list (bool * positive)) :=
match l1 with
| nil =>
match l0 with nil => default | n :: _ => n end
| ((s, p) as n) :: l1 =>
if is_signaling p then n else choose_snan l1
end
in choose_snan l0.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan
|
Choose the first signaling NaN, if any;
otherwise choose the first NaN;
otherwise use default.
|
choose_nan_idem: forall is_signaling default n,
choose_nan is_signaling default (n :: n :: nil) =
choose_nan is_signaling default (n :: nil).
|
Lemma
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan_idem
| null |
choose_nan_64 :=
choose_nan (fun p => negb (Pos.testbit p 51)) default_nan_64.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan_64
| null |
choose_nan_32 :=
choose_nan (fun p => negb (Pos.testbit p 22)) default_nan_32.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan_32
| null |
choose_nan_64_idem: forall n,
choose_nan_64 (n :: n :: nil) = choose_nan_64 (n :: nil).
|
Lemma
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan_64_idem
| null |
choose_nan_32_idem: forall n,
choose_nan_32 (n :: n :: nil) = choose_nan_32 (n :: nil).
|
Lemma
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
choose_nan_32_idem
| null |
fma_order {A: Type} (x y z: A) := (z, x, y).
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
fma_order
| null |
fma_invalid_mul_is_nan := true.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
fma_invalid_mul_is_nan
| null |
float_of_single_preserves_sNaN := false.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
float_of_single_preserves_sNaN
| null |
float_conversion_default_nan := false.
|
Definition
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
float_conversion_default_nan
| null |
abi_kind: Type :=
| AAPCS64 (**r ARM's standard as used in Linux and other ELF platforms *)
| Apple.
|
Inductive
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
abi_kind
|
Which ABI to implement
|
abi: abi_kind.
|
Parameter
|
aarch64
|
[
"Coq.ZArith",
"Coq.List",
"Flocq.Binary",
"Flocq.Bits"
] |
aarch64/Archi.v
|
abi
|
r the variant used in macOS and iOS
|
ireg: Type :=
| X0 | X1 | X2 | X3 | X4 | X5 | X6 | X7
| X8 | X9 | X10 | X11 | X12 | X13 | X14 | X15
| X16 | X17 | X18 | X19 | X20 | X21 | X22 | X23
| X24 | X25 | X26 | X27 | X28 | X29 | X30.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
ireg
|
In assembly files, [Xn] denotes the full 64-bit register
and [Wn] the low 32 bits of [Xn].
|
ireg0: Type :=
| RR0 (r: ireg) | XZR.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
ireg0
| null |
iregsp: Type :=
| RR1 (r: ireg) | XSP.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
iregsp
| null |
ireg_eq: forall (x y: ireg), {x=y} + {x<>y}.
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
ireg_eq
| null |
freg: Type :=
| D0 | D1 | D2 | D3 | D4 | D5 | D6 | D7
| D8 | D9 | D10 | D11 | D12 | D13 | D14 | D15
| D16 | D17 | D18 | D19 | D20 | D21 | D22 | D23
| D24 | D25 | D26 | D27 | D28 | D29 | D30 | D31.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
freg
|
In assembly files, [Dn] denotes the low 64-bit of a vector register,
and [Sn] the low 32 bits.
|
freg_eq: forall (x y: freg), {x=y} + {x<>y}.
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
freg_eq
| null |
crbit: Type :=
| CN: crbit (**r negative *)
| CZ: crbit (**r zero *)
| CC: crbit (**r carry *)
| CV: crbit.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
crbit
|
Bits in the condition register.
|
crbit_eq: forall (x y: crbit), {x=y} + {x<>y}.
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
crbit_eq
|
r overflow
|
preg: Type :=
| IR: ireg -> preg (**r 64- or 32-bit integer registers *)
| FR: freg -> preg (**r double- or single-precision float registers *)
| CR: crbit -> preg (**r bits in the condition register *)
| SP: preg (**r register X31 used as stack pointer *)
| PC: preg.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
preg
|
We model the following registers of the ARM architecture.
|
preg_eq: forall (x y: preg), {x=y} + {x<>y}.
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
preg_eq
| null |
t := preg.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
t
| null |
eq := preg_eq.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eq
| null |
preg_of_iregsp (r: iregsp) : preg :=
match r with RR1 r => IR r | XSP => SP end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
preg_of_iregsp
| null |
label := positive.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
label
|
The instruction set. Most instructions correspond exactly to
actual AArch64 instructions. See the ARM reference manuals for more
details. Some instructions, described below, are
pseudo-instructions: they expand to canned instruction sequences
during the printing of the assembly code.
|
isize: Type :=
| W (**r 32-bit integer operation *)
| X.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
isize
| null |
fsize: Type :=
| S (**r 32-bit, single-precision FP operation *)
| D.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
fsize
|
r 64-bit integer operation
|
testcond : Type :=
| TCeq: testcond (**r equal *)
| TCne: testcond (**r not equal *)
| TChs: testcond (**r unsigned higher or same *)
| TClo: testcond (**r unsigned lower *)
| TCmi: testcond (**r negative *)
| TCpl: testcond (**r positive *)
| TChi: testcond (**r unsigned higher *)
| TCls: testcond (**r unsigned lower or same *)
| TCge: testcond (**r signed greater or equal *)
| TClt: testcond (**r signed less than *)
| TCgt: testcond (**r signed greater *)
| TCle: testcond.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
testcond
|
r 64-bit, double-precision FP operation
|
addressing: Type :=
| ADimm (base: iregsp) (n: int64) (**r base plus immediate offset *)
| ADreg (base: iregsp) (r: ireg) (**r base plus reg *)
| ADlsl (base: iregsp) (r: ireg) (n: int) (**r base plus reg LSL n *)
| ADsxt (base: iregsp) (r: ireg) (n: int) (**r base plus SIGN-EXT(reg) LSL n *)
| ADuxt (base: iregsp) (r: ireg) (n: int) (**r base plus ZERO-EXT(reg) LSL n *)
| ADadr (base: iregsp) (id: ident) (ofs: ptrofs) (**r base plus low address of [id + ofs] *)
| ADpostincr (base: iregsp) (n: int64).
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
addressing
|
r signed less than or equal
|
shift_op: Type :=
| SOnone
| SOlsl (n: int)
| SOlsr (n: int)
| SOasr (n: int)
| SOror (n: int).
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
shift_op
|
r base plus offset; base is updated after
|
extend_op: Type :=
| EOsxtb (n: int)
| EOsxth (n: int)
| EOsxtw (n: int)
| EOuxtb (n: int)
| EOuxth (n: int)
| EOuxtw (n: int)
| EOuxtx (n: int).
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
extend_op
| null |
instruction: Type :=
| Pb (lbl: label) (**r branch *)
| Pbc (c: testcond) (lbl: label) (**r conditional branch *)
| Pbl (id: ident) (sg: signature) (**r jump to function and link *)
| Pbs (id: ident) (sg: signature) (**r jump to function *)
| Pblr (r: ireg) (sg: signature) (**r indirect jump and link *)
| Pbr (r: ireg) (sg: signature) (**r indirect jump *)
| Pret (r: ireg) (**r return *)
| Pcbnz (sz: isize) (r: ireg) (lbl: label) (**r branch if not zero *)
| Pcbz (sz: isize) (r: ireg) (lbl: label) (**r branch if zero *)
| Ptbnz (sz: isize) (r: ireg) (n: int) (lbl: label) (**r branch if bit n is not zero *)
| Ptbz (sz: isize) (r: ireg) (n: int) (lbl: label) (**r branch if bit n is zero *)
| Pldrw (rd: ireg) (a: addressing) (**r load int32 *)
| Pldrw_a (rd: ireg) (a: addressing) (**r load int32 as any32 *)
| Pldrx (rd: ireg) (a: addressing) (**r load int64 *)
| Pldrx_a (rd: ireg) (a: addressing) (**r load int64 as any64 *)
| Pldrb (sz: isize) (rd: ireg) (a: addressing) (**r load int8, zero-extend *)
| Pldrsb (sz: isize) (rd: ireg) (a: addressing) (**r load int8, sign-extend *)
| Pldrh (sz: isize) (rd: ireg) (a: addressing) (**r load int16, zero-extend *)
| Pldrsh (sz: isize) (rd: ireg) (a: addressing) (**r load int16, sign-extend *)
| Pldrzw (rd: ireg) (a: addressing) (**r load int32, zero-extend to int64 *)
| Pldrsw (rd: ireg) (a: addressing) (**r load int32, sign-extend to int64 *)
| Pldp (rd1 rd2: ireg) (a: addressing) (**r load two int64 *)
| Pstrw (rs: ireg) (a: addressing) (**r store int32 *)
| Pstrw_a (rs: ireg) (a: addressing) (**r store int32 as any32 *)
| Pstrx (rs: ireg) (a: addressing) (**r store int64 *)
| Pstrx_a (rs: ireg) (a: addressing) (**r store int64 as any64 *)
| Pstrb (rs: ireg) (a: addressing) (**r store int8 *)
| Pstrh (rs: ireg) (a: addressing) (**r store int16 *)
| Pstp (rs1 rs2: ireg) (a: addressing) (**r store two int64 *)
| Paddimm (sz: isize) (rd: iregsp) (r1: iregsp) (n: Z) (**r addition *)
| Psubimm (sz: isize) (rd: iregsp) (r1: iregsp) (n: Z) (**r subtraction *)
| Pcmpimm (sz: isize) (r1: ireg) (n: Z) (**r compare *)
| Pcmnimm (sz: isize) (r1: ireg) (n: Z) (**r compare negative *)
| Pmov (rd: iregsp) (r1: iregsp)
| Pandimm (sz: isize) (rd: ireg) (r1: ireg0) (n: Z) (**r and *)
| Peorimm (sz: isize) (rd: ireg) (r1: ireg0) (n: Z) (**r xor *)
| Porrimm (sz: isize) (rd: ireg) (r1: ireg0) (n: Z) (**r or *)
| Ptstimm (sz: isize) (r1: ireg) (n: Z) (**r and, then set flags *)
| Pmovz (sz: isize) (rd: ireg) (n: Z) (pos: Z) (**r move [n << pos] to [rd] *)
| Pmovn (sz: isize) (rd: ireg) (n: Z) (pos: Z) (**r move [NOT(n << pos)] to [rd] *)
| Pmovk (sz: isize) (rd: ireg) (n: Z) (pos: Z) (**r insert 16 bits of [n] at [pos] in rd *)
| Padrp (rd: ireg) (id: ident) (ofs: ptrofs) (**r set [rd] to high address of [id + ofs] *)
| Paddadr (rd: ireg) (r1: ireg) (id: ident) (ofs: ptrofs) (**r add the low address of [id + ofs] *)
| Psbfiz (sz: isize) (rd: ireg) (r1: ireg) (r: int) (s: Z) (**r sign extend and shift left *)
| Psbfx (sz: isize) (rd: ireg) (r1: ireg) (r: int) (s: Z) (**r shift right and sign extend *)
| Pubfiz (sz: isize) (rd: ireg) (r1: ireg) (r: int) (s: Z) (**r zero extend and shift left *)
| Pubfx (sz: isize) (rd: ireg) (r1: ireg) (r: int) (s: Z) (**r shift right and zero extend *)
| Padd (sz: isize) (rd: ireg) (r1: ireg0) (r2: ireg) (s: shift_op) (**r addition *)
| Psub (sz: isize) (rd: ireg) (r1: ireg0) (r2: ireg) (s: shift_op) (**r subtraction *)
| Pcmp (sz: isize) (r1: ireg0) (r2: ireg) (s: shift_op) (**r compare *)
...
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
instruction
| null |
code := list instruction.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
code
| null |
function : Type := mkfunction { fn_sig: signature; fn_code: code }.
|
Record
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
function
| null |
fundef := AST.fundef function.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
fundef
| null |
program := AST.program fundef unit.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
program
| null |
regset := Pregmap.t val.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
regset
|
The semantics operates over a single mapping from registers
(type [preg]) to values. We maintain (but do not enforce)
the convention that integer registers are mapped to values of
type [Tint], float registers to values of type [Tfloat],
and condition bits to either [Vzero] or [Vone].
|
genv := Genv.t fundef unit.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
genv
| null |
ir0w (rs: regset) (r: ireg0) : val :=
match r with RR0 r => rs (IR r) | XZR => Vint Int.zero end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
ir0w
|
The value of an [ireg0] is either the value of the integer register,
or 0.
|
ir0x (rs: regset) (r: ireg0) : val :=
match r with RR0 r => rs (IR r) | XZR => Vlong Int64.zero end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
ir0x
| null |
undef_regs (l: list preg) (rs: regset) : regset :=
match l with
| nil => rs
| r :: l' => undef_regs l' (rs#r <- Vundef)
end.
|
Fixpoint
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
undef_regs
|
Undefining some registers
|
undef_flags (rs: regset) : regset :=
fun r => match r with CR _ => Vundef | _ => rs r end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
undef_flags
|
Undefining the condition codes
|
set_pair (p: rpair preg) (v: val) (rs: regset) : regset :=
match p with
| One r => rs#r <- v
| Twolong rhi rlo => rs#rhi <- (Val.hiword v) #rlo <- (Val.loword v)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
set_pair
|
Assigning a register pair
|
set_res (res: builtin_res preg) (v: val) (rs: regset) : regset :=
match res with
| BR r => rs#r <- v
| BR_none => rs
| BR_splitlong hi lo => set_res lo (Val.loword v) (set_res hi (Val.hiword v) rs)
end.
|
Fixpoint
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
set_res
|
Assigning the result of a builtin
|
symbol_low: genv -> ident -> ptrofs -> val.
|
Parameter
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
symbol_low
|
The two functions below axiomatize how the linker processes
symbolic references [symbol + offset]. It computes the
difference between the address and the PC, and splits it into:
- 12 low bits usable as an offset in an addressing mode;
- 21 high bits usable as argument to the ADRP instruction.
In CompCert's model, we cannot really describe PC-relative addressing,
but we can claim that the address of [symbol + offset] decomposes
as the sum of
- a low part, usable as an offset in an addressing mode;
- a high part, usable as argument to the ADRP instruction.
|
symbol_high: genv -> ident -> ptrofs -> val.
|
Parameter
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
symbol_high
| null |
symbol_high_low:
forall (ge: genv) (id: ident) (ofs: ptrofs),
Val.addl (symbol_high ge id ofs) (symbol_low ge id ofs) = Genv.symbol_address ge id ofs.
|
Axiom
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
symbol_high_low
| null |
find_instr (pos: Z) (c: code) {struct c} : option instruction :=
match c with
| nil => None
| i :: il => if zeq pos 0 then Some i else find_instr (pos - 1) il
end.
|
Fixpoint
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
find_instr
|
Looking up instructions in a code sequence by position.
|
is_label (lbl: label) (instr: instruction) : bool :=
match instr with
| Plabel lbl' => if peq lbl lbl' then true else false
| _ => false
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
is_label
|
Position corresponding to a label
|
is_label_correct:
forall lbl instr,
if is_label lbl instr then instr = Plabel lbl else instr <> Plabel lbl.
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
is_label_correct
| null |
label_pos (lbl: label) (pos: Z) (c: code) {struct c} : option Z :=
match c with
| nil => None
| instr :: c' =>
if is_label lbl instr then Some (pos + 1) else label_pos lbl (pos + 1) c'
end.
|
Fixpoint
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
label_pos
| null |
outcome: Type :=
| Next: regset -> mem -> outcome
| Stuck: outcome.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
outcome
|
The semantics is purely small-step and defined as a function
from the current state (a register set + a memory state)
to either [Next rs' m'] where [rs'] and [m'] are the updated register
set and memory state after execution of the instruction at [rs#PC],
or [Stuck] if the processor is stuck.
|
nextinstr (rs: regset) :=
rs#PC <- (Val.offset_ptr rs#PC Ptrofs.one).
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
nextinstr
|
Manipulations over the [PC] register: continuing with the next
instruction ([nextinstr]) or branching to a label ([goto_label]).
|
goto_label (f: function) (lbl: label) (rs: regset) (m: mem) :=
match label_pos lbl 0 (fn_code f) with
| None => Stuck
| Some pos =>
match rs#PC with
| Vptr b ofs => Next (rs#PC <- (Vptr b (Ptrofs.repr pos))) m
| _ => Stuck
end
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
goto_label
| null |
eval_testcond (c: testcond) (rs: regset) : option bool :=
match c with
| TCeq => (**r equal *)
match rs#CZ with
| Vint n => Some (Int.eq n Int.one)
| _ => None
end
| TCne => (**r not equal *)
match rs#CZ with
| Vint n => Some (Int.eq n Int.zero)
| _ => None
end
| TClo => (**r unsigned less than *)
match rs#CC with
| Vint n => Some (Int.eq n Int.zero)
| _ => None
end
| TCls => (**r unsigned less or equal *)
match rs#CC, rs#CZ with
| Vint c, Vint z => Some (Int.eq c Int.zero || Int.eq z Int.one)
| _, _ => None
end
| TChs => (**r unsigned greater or equal *)
match rs#CC with
| Vint n => Some (Int.eq n Int.one)
| _ => None
end
| TChi => (**r unsigned greater *)
match rs#CC, rs#CZ with
| Vint c, Vint z => Some (Int.eq c Int.one && Int.eq z Int.zero)
| _, _ => None
end
| TClt => (**r signed less than *)
match rs#CV, rs#CN with
| Vint o, Vint s => Some (Int.eq (Int.xor o s) Int.one)
| _, _ => None
end
| TCle => (**r signed less or equal *)
match rs#CV, rs#CN, rs#CZ with
| Vint o, Vint s, Vint z => Some (Int.eq (Int.xor o s) Int.one || Int.eq z Int.one)
| _, _, _ => None
end
| TCge => (**r signed greater or equal *)
match rs#CV, rs#CN with
| Vint o, Vint s => Some (Int.eq (Int.xor o s) Int.zero)
| _, _ => None
end
| TCgt => (**r signed greater *)
match rs#CV, rs#CN, rs#CZ with
| Vint o, Vint s, Vint z => Some (Int.eq (Int.xor o s) Int.zero && Int.eq z Int.zero)
| _, _, _ => None
...
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_testcond
|
Testing a condition
|
eval_testzero (sz: isize) (v: val) (m: mem): option bool :=
match sz with
| W => Val.cmpu_bool (Mem.valid_pointer m) Ceq v (Vint Int.zero)
| X => Val.cmplu_bool (Mem.valid_pointer m) Ceq v (Vlong Int64.zero)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_testzero
|
Integer "is zero?" test
|
eval_testbit (sz: isize) (v: val) (n: int): option bool :=
match sz with
| W => Val.cmp_bool Cne (Val.and v (Vint (Int.shl Int.one n))) (Vint Int.zero)
| X => Val.cmpl_bool Cne (Val.andl v (Vlong (Int64.shl' Int64.one n))) (Vlong Int64.zero)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_testbit
|
Integer "bit is set?" test
|
eval_addressing (a: addressing) (rs: regset): val :=
match a with
| ADimm base n => Val.addl rs#base (Vlong n)
| ADreg base r => Val.addl rs#base rs#r
| ADlsl base r n => Val.addl rs#base (Val.shll rs#r (Vint n))
| ADsxt base r n => Val.addl rs#base (Val.shll (Val.longofint rs#r) (Vint n))
| ADuxt base r n => Val.addl rs#base (Val.shll (Val.longofintu rs#r) (Vint n))
| ADadr base id ofs => Val.addl rs#base (symbol_low ge id ofs)
| ADpostincr base n => Vundef (* not modeled yet *)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_addressing
|
Evaluating an addressing mode
|
exec_load (chunk: memory_chunk) (transf: val -> val)
(a: addressing) (r: preg) (rs: regset) (m: mem) :=
match Mem.loadv chunk m (eval_addressing a rs) with
| None => Stuck
| Some v => Next (nextinstr (rs#r <- (transf v))) m
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
exec_load
|
Auxiliaries for memory accesses
|
exec_store (chunk: memory_chunk)
(a: addressing) (v: val)
(rs: regset) (m: mem) :=
match Mem.storev chunk m (eval_addressing a rs) v with
| None => Stuck
| Some m' => Next (nextinstr rs) m'
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
exec_store
| null |
compare_int (rs: regset) (v1 v2: val) (m: mem) :=
rs#CN <- (Val.negative (Val.sub v1 v2))
#CZ <- (Val.cmpu (Mem.valid_pointer m) Ceq v1 v2)
#CC <- (Val.cmpu (Mem.valid_pointer m) Cge v1 v2)
#CV <- (Val.sub_overflow v1 v2).
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
compare_int
|
Comparisons
|
compare_long (rs: regset) (v1 v2: val) (m: mem) :=
rs#CN <- (Val.negativel (Val.subl v1 v2))
#CZ <- (Val.maketotal (Val.cmplu (Mem.valid_pointer m) Ceq v1 v2))
#CC <- (Val.maketotal (Val.cmplu (Mem.valid_pointer m) Cge v1 v2))
#CV <- (Val.subl_overflow v1 v2).
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
compare_long
| null |
compare_float (rs: regset) (v1 v2: val) :=
match v1, v2 with
| Vfloat f1, Vfloat f2 =>
rs#CN <- (Val.of_bool (Float.cmp Clt f1 f2))
#CZ <- (Val.of_bool (Float.cmp Ceq f1 f2))
#CC <- (Val.of_bool (negb (Float.cmp Clt f1 f2)))
#CV <- (Val.of_bool (negb (Float.ordered f1 f2)))
| _, _ =>
rs#CN <- Vundef
#CZ <- Vundef
#CC <- Vundef
#CV <- Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
compare_float
|
Semantics of [fcmp] instructions:
<<
== N=0 Z=1 C=1 V=0
< N=1 Z=0 C=0 V=0
> N=0 Z=0 C=1 V=0
unord N=0 Z=0 C=1 V=1
>>
|
compare_single (rs: regset) (v1 v2: val) :=
match v1, v2 with
| Vsingle f1, Vsingle f2 =>
rs#CN <- (Val.of_bool (Float32.cmp Clt f1 f2))
#CZ <- (Val.of_bool (Float32.cmp Ceq f1 f2))
#CC <- (Val.of_bool (negb (Float32.cmp Clt f1 f2)))
#CV <- (Val.of_bool (negb (Float32.ordered f1 f2)))
| _, _ =>
rs#CN <- Vundef
#CZ <- Vundef
#CC <- Vundef
#CV <- Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
compare_single
| null |
insert_in_int (x: val) (y: Z) (pos: Z) (len: Z) : val :=
match x with
| Vint n => Vint (Int.repr (Zinsert (Int.unsigned n) y pos len))
| _ => Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
insert_in_int
|
Insertion of bits into an integer
|
insert_in_long (x: val) (y: Z) (pos: Z) (len: Z) : val :=
match x with
| Vlong n => Vlong (Int64.repr (Zinsert (Int64.unsigned n) y pos len))
| _ => Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
insert_in_long
| null |
eval_shift_op_int (v: val) (s: shift_op): val :=
match s with
| SOnone => v
| SOlsl n => Val.shl v (Vint n)
| SOlsr n => Val.shru v (Vint n)
| SOasr n => Val.shr v (Vint n)
| SOror n => Val.ror v (Vint n)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_shift_op_int
|
Evaluation of shifted operands
|
eval_shift_op_long (v: val) (s: shift_op): val :=
match s with
| SOnone => v
| SOlsl n => Val.shll v (Vint n)
| SOlsr n => Val.shrlu v (Vint n)
| SOasr n => Val.shrl v (Vint n)
| SOror n => Val.rorl v (Vint n)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_shift_op_long
| null |
eval_extend (v: val) (x: extend_op): val :=
match x with
| EOsxtb n => Val.shll (Val.longofint (Val.sign_ext 8 v)) (Vint n)
| EOsxth n => Val.shll (Val.longofint (Val.sign_ext 16 v)) (Vint n)
| EOsxtw n => Val.shll (Val.longofint v) (Vint n)
| EOuxtb n => Val.shll (Val.longofintu (Val.zero_ext 8 v)) (Vint n)
| EOuxth n => Val.shll (Val.longofintu (Val.zero_ext 16 v)) (Vint n)
| EOuxtw n => Val.shll (Val.longofintu v) (Vint n)
| EOuxtx n => Val.shll v (Vint n)
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
eval_extend
|
Evaluation of sign- or zero- extended operands
|
float32_of_bits (v: val): val :=
match v with
| Vint n => Vsingle (Float32.of_bits n)
| _ => Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
float32_of_bits
|
Bit-level conversion from integers to FP numbers
|
float64_of_bits (v: val): val :=
match v with
| Vlong n => Vfloat (Float.of_bits n)
| _ => Vundef
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
float64_of_bits
| null |
exec_instr (f: function) (i: instruction) (rs: regset) (m: mem) : outcome :=
match i with
| Pb lbl =>
goto_label f lbl rs m
| Pbc cond lbl =>
match eval_testcond cond rs with
| Some true => goto_label f lbl rs m
| Some false => Next (nextinstr rs) m
| None => Stuck
end
| Pbl id sg =>
Next (rs#RA <- (Val.offset_ptr rs#PC Ptrofs.one) #PC <- (Genv.symbol_address ge id Ptrofs.zero)) m
| Pbs id sg =>
Next (rs#PC <- (Genv.symbol_address ge id Ptrofs.zero)) m
| Pblr r sg =>
Next (rs#RA <- (Val.offset_ptr rs#PC Ptrofs.one) #PC <- (rs#r)) m
| Pbr r sg =>
Next (rs#PC <- (rs#r)) m
| Pret r =>
Next (rs#PC <- (rs#r)) m
| Pcbnz sz r lbl =>
match eval_testzero sz rs#r m with
| Some true => Next (nextinstr rs) m
| Some false => goto_label f lbl rs m
| None => Stuck
end
| Pcbz sz r lbl =>
match eval_testzero sz rs#r m with
| Some true => goto_label f lbl rs m
| Some false => Next (nextinstr rs) m
| None => Stuck
end
| Ptbnz sz r n lbl =>
match eval_testbit sz rs#r n with
| Some true => goto_label f lbl rs m
| Some false => Next (nextinstr rs) m
| None => Stuck
end
| Ptbz sz r n lbl =>
match eval_testbit sz rs#r n with
| Some true => Next (nextinstr rs) m
| Some false => goto_label f lbl rs m
| None => Stuck
end
| Pldrw rd a =>
exec_load Mint32 (fun v => v) a rd rs m
| Pldrw_a rd a =>
exec_load Many32 (fun v => v) a rd rs m
| Pldrx rd a =>
exec_load Mint64 (fun v => v) a rd rs m
| Pldrx_a rd a =>
...
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
exec_instr
|
Execution of a single instruction [i] in initial state
[rs] and [m]. Return updated state. For instructions
that correspond to actual AArch64 instructions, the cases are
straightforward transliterations of the informal descriptions
given in the ARMv8 reference manuals. For pseudo-instructions,
refer to the informal descriptions given above.
Note that we set to [Vundef] the registers used as temporaries by
the expansions of the pseudo-instructions, so that the code we
generate cannot use those registers to hold values that must
survive the execution of the pseudo-instruction.
|
preg_of (r: mreg) : preg :=
match r with
| R0 => X0 | R1 => X1 | R2 => X2 | R3 => X3
| R4 => X4 | R5 => X5 | R6 => X6 | R7 => X7
| R8 => X8 | R9 => X9 | R10 => X10 | R11 => X11
| R12 => X12 | R13 => X13 | R14 => X14 | R15 => X15
| R17 => X17 | R19 => X19
| R20 => X20 | R21 => X21 | R22 => X22 | R23 => X23
| R24 => X24 | R25 => X25 | R26 => X26 | R27 => X27
| R28 => X28 | R29 => X29
| F0 => D0 | F1 => D1 | F2 => D2 | F3 => D3
| F4 => D4 | F5 => D5 | F6 => D6 | F7 => D7
| F8 => D8 | F9 => D9 | F10 => D10 | F11 => D11
| F12 => D12 | F13 => D13 | F14 => D14 | F15 => D15
| F16 => D16 | F17 => D17 | F18 => D18 | F19 => D19
| F20 => D20 | F21 => D21 | F22 => D22 | F23 => D23
| F24 => D24 | F25 => D25 | F26 => D26 | F27 => D27
| F28 => D28 | F29 => D29 | F30 => D30 | F31 => D31
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
preg_of
|
Translation of the LTL/Linear/Mach view of machine registers
to the AArch64 view. Note that no LTL register maps to [X16],
[X18], nor [X30].
[X18] is reserved as the platform register and never used by the
code generated by CompCert.
[X30] is used for the return address, and can also be used as temporary.
[X16] can be used as temporary.
|
undef_caller_save_regs (rs: regset) : regset :=
fun r =>
if preg_eq r SP
|| In_dec preg_eq r (List.map preg_of (List.filter is_callee_save all_mregs))
then rs r
else Vundef.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
undef_caller_save_regs
|
Undefine all registers except SP and callee-save registers
|
extcall_arg (rs: regset) (m: mem): loc -> val -> Prop :=
| extcall_arg_reg: forall r,
extcall_arg rs m (R r) (rs (preg_of r))
| extcall_arg_stack: forall ofs ty bofs v,
bofs = Stacklayout.fe_ofs_arg + 4 * ofs ->
Mem.loadv (chunk_of_type ty) m
(Val.offset_ptr rs#SP (Ptrofs.repr bofs)) = Some v ->
extcall_arg rs m (Locations.S Outgoing ofs ty) v.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
extcall_arg
|
Extract the values of the arguments of an external call.
We exploit the calling conventions from module [Conventions], except that
we use AArch64 registers instead of locations.
|
extcall_arg_pair (rs: regset) (m: mem): rpair loc -> val -> Prop :=
| extcall_arg_one: forall l v,
extcall_arg rs m l v ->
extcall_arg_pair rs m (One l) v
| extcall_arg_twolong: forall hi lo vhi vlo,
extcall_arg rs m hi vhi ->
extcall_arg rs m lo vlo ->
extcall_arg_pair rs m (Twolong hi lo) (Val.longofwords vhi vlo).
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
extcall_arg_pair
| null |
extcall_arguments
(rs: regset) (m: mem) (sg: signature) (args: list val) : Prop :=
list_forall2 (extcall_arg_pair rs m) (loc_arguments sg) args.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
extcall_arguments
| null |
loc_external_result (sg: signature) : rpair preg :=
map_rpair preg_of (loc_result sg).
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
loc_external_result
| null |
state: Type :=
| State: regset -> mem -> state.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
state
|
Execution of the instruction at [rs#PC].
|
step: state -> trace -> state -> Prop :=
| exec_step_internal:
forall b ofs f i rs m rs' m',
rs PC = Vptr b ofs ->
Genv.find_funct_ptr ge b = Some (Internal f) ->
find_instr (Ptrofs.unsigned ofs) f.(fn_code) = Some i ->
exec_instr f i rs m = Next rs' m' ->
step (State rs m) E0 (State rs' m')
| exec_step_builtin:
forall b ofs f ef args res rs m vargs t vres rs' m',
rs PC = Vptr b ofs ->
Genv.find_funct_ptr ge b = Some (Internal f) ->
find_instr (Ptrofs.unsigned ofs) f.(fn_code) = Some (Pbuiltin ef args res) ->
eval_builtin_args ge rs rs#SP m args vargs ->
external_call ef ge vargs m t vres m' ->
rs' = nextinstr
(set_res res vres
(undef_regs (IR X16 :: IR X30 :: map preg_of (destroyed_by_builtin ef)) rs)) ->
step (State rs m) t (State rs' m')
| exec_step_external:
forall b ef args res rs m t rs' m',
rs PC = Vptr b Ptrofs.zero ->
Genv.find_funct_ptr ge b = Some (External ef) ->
external_call ef ge args m t res m' ->
extcall_arguments rs m (ef_sig ef) args ->
rs' = (set_pair (loc_external_result (ef_sig ef)) res (undef_caller_save_regs rs)) #PC <- (rs RA) ->
step (State rs m) t (State rs' m').
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
step
| null |
initial_state (p: program): state -> Prop :=
| initial_state_intro: forall m0,
Genv.init_mem p = Some m0 ->
let ge := Genv.globalenv p in
let rs0 :=
(Pregmap.init Vundef)
# PC <- (Genv.symbol_address ge p.(prog_main) Ptrofs.zero)
# RA <- Vnullptr
# SP <- Vnullptr in
initial_state p (State rs0 m0).
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
initial_state
|
Execution of whole programs.
|
final_state: state -> int -> Prop :=
| final_state_intro: forall rs m r,
rs#PC = Vnullptr ->
rs#X0 = Vint r ->
final_state (State rs m) r.
|
Inductive
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
final_state
| null |
semantics (p: program) :=
Semantics step (initial_state p) final_state (Genv.globalenv p).
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
semantics
| null |
extcall_arguments_determ:
forall rs m sg args1 args2,
extcall_arguments rs m sg args1 -> extcall_arguments rs m sg args2 -> args1 = args2.
|
Remark
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
extcall_arguments_determ
|
Determinacy of the [Asm] semantics.
|
semantics_determinate: forall p, determinate (semantics p).
|
Lemma
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
semantics_determinate
| null |
data_preg (r: preg) : bool :=
match r with
| IR X16 => false
| IR X30 => false
| IR _ => true
| FR _ => true
| CR _ => false
| SP => true
| PC => false
end.
|
Definition
|
aarch64
|
[
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions"
] |
aarch64/Asm.v
|
data_preg
|
Classification functions for processor registers (used in Asmgenproof).
|
symbol_is_aligned : ident -> Z -> bool.
|
Parameter
|
aarch64
|
[
"Coq.Recdef",
"Coq.Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm"
] |
aarch64/Asmgen.v
|
symbol_is_aligned
|
Alignment check for symbols
|
ireg_of (r: mreg) : res ireg :=
match preg_of r with IR mr => OK mr | _ => Error(msg "Asmgen.ireg_of") end.
|
Definition
|
aarch64
|
[
"Coq.Recdef",
"Coq.Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm"
] |
aarch64/Asmgen.v
|
ireg_of
|
Extracting integer or float registers.
|
freg_of (r: mreg) : res freg :=
match preg_of r with FR mr => OK mr | _ => Error(msg "Asmgen.freg_of") end.
|
Definition
|
aarch64
|
[
"Coq.Recdef",
"Coq.Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm"
] |
aarch64/Asmgen.v
|
freg_of
| null |
state : Type := SA | SB | SC | SD | SE | SF | SG | Sbad.
|
Inductive
|
aarch64
|
[
"Coq.Recdef",
"Coq.Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm"
] |
aarch64/Asmgen.v
|
state
| null |
start := SA.
|
Definition
|
aarch64
|
[
"Coq.Recdef",
"Coq.Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm"
] |
aarch64/Asmgen.v
|
start
| null |
End of preview. Expand
in Data Studio
Coq-CompCert
A structured dataset of formalizations from CompCert, the verified C compiler.
License
This dataset is derived from CompCert, copyright Institut National de Recherche en Informatique et en Automatique (INRIA) and AbsInt Angewandte Informatik GmbH.
Non-Commercial Use Only. The INRIA Non-Commercial License grants the right to use CompCert for educational, research, personal, or evaluation purposes only. Commercial use is prohibited without a separate license from AbsInt.
Some source files are dual-licensed under LGPL v2.1, permitting commercial use of those components. See the LICENSE for details.
For commercial licensing: info@absint.com
Schema
| Column | Type | Description |
|---|---|---|
| fact | string | Declaration body (without type keyword) |
| type | string | Lemma, Theorem, Definition, Inductive, etc. |
| library | string | Component (backend, cfrontend, common, lib, x86, arm, aarch64, riscv, powerpc) |
| imports | list | Import statements |
| filename | string | Source file path |
| symbolic_name | string | Declaration identifier |
| docstring | string | Documentation comment |
Statistics
- Total entries: 11,445
- Lemma: 4,403
- Definition: 3,310
- Theorem: 1,419
- Inductive: 551
Source
- Downloads last month
- 24
Size of downloaded dataset files:
1.02 MB
Size of the auto-converted Parquet files:
1.02 MB
Number of rows:
11,445