bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9d6d250fcdf227616c5f5557571f8bba6d0ea45b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h\n@@ -0,0 +1,487 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_psram.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_PSRAM_CTRL_H__\n+#define __BL808_PSRAM_CTRL_H__\n+\n+#include \"psram_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PSRAM_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_CTRL_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief PSRAM ID\n+ */\n+typedef enum {\n+ PSRAM0_ID, /*!< PSRAM0 identifier */\n+} PSRAM_ID_Type;\n+\n+/**\n+ * @brief PSRAM Ctrl IO mode type definition\n+ */\n+typedef enum {\n+ PSRAM_CTRL_X8_MODE, /*!< PSRAM X8 mode */\n+ PSRAM_CTRL_X16_MODE, /*!< PSRAM X16 mode */\n+} PSRAM_Ctrl_Io_Mode_Type;\n+\n+/**\n+ * @brief PSRAM Ctrl PSRAM vendor type definition\n+ */\n+typedef enum {\n+ PSRAM_CTRL_VENDOR_WINBOND = 0x1, /*!< Winbond psram */\n+ PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB = 0x2, /*!< AP memory psram exclude 4MB size */\n+ PSRAM_CTRL_VENDOR_APMEM_4MB = 0x4, /*!< AP memory psram 4MB size */\n+} PSRAM_Ctrl_Vendor_Type;\n+\n+/**\n+ * @brief PSRAM SIZE\n+ */\n+typedef enum {\n+ PSRAM_SIZE_4MB = 0x3, /*!< PSRAM size is 4MB */\n+ PSRAM_SIZE_8MB = 0x7, /*!< PSRAM size is 8MB */\n+ PSRAM_SIZE_16MB = 0xf, /*!< PSRAM size is 16MB */\n+ PSRAM_SIZE_32MB = 0x1f, /*!< PSRAM size is 32MB */\n+} PSRAM_Ctrl_Size_Type;\n+\n+/**\n+ * @brief Winbond PSRAM configuration register type definition\n+ */\n+typedef enum {\n+ PSRAM_WINBOND_REG_ID0, /*!< Winbond register ID0 */\n+ PSRAM_WINBOND_REG_ID1, /*!< Winbond register ID1 */\n+ PSRAM_WINBOND_REG_CR0, /*!< Winbond register CR0 */\n+ PSRAM_WINBOND_REG_CR1, /*!< Winbond register CR1 */\n+ PSRAM_WINBOND_REG_CR2, /*!< Winbond register CR2 */\n+ PSRAM_WINBOND_REG_CR3, /*!< Winbond register CR3 */\n+ PSRAM_WINBOND_REG_CR4, /*!< Winbond register CR4 */\n+} PSRAM_Ctrl_Winbond_Cfg_Reg_Type;\n+\n+/**\n+ * @brief APMemory PSRAM configuration register type definition\n+ */\n+typedef enum {\n+ PSRAM_APMEM_REG_0 = 0, /*!< APMemory register 0 */\n+ PSRAM_APMEM_REG_1, /*!< APMemory register 1 */\n+ PSRAM_APMEM_REG_2, /*!< APMemory register 2 */\n+ PSRAM_APMEM_REG_3, /*!< APMemory register 3 */\n+ PSRAM_APMEM_REG_4, /*!< APMemory register 4 */\n+ PSRAM_APMEM_REG_5, /*!< APMemory register 5 */\n+ PSRAM_APMEM_REG_6, /*!< APMemory register 6 */\n+ PSRAM_APMEM_REG_8, /*!< APMemory register 8 */\n+} PSRAM_Ctrl_ApMem_Cfg_Reg_Type;\n+\n+/**\n+ * @brief PSRAM Latency Counter type definition\n+ */\n+typedef enum {\n+ PSRAM_WINBOND_5_CLOCKS_LATENCY, /*!< PSRAM 5 clocks latency 133MHZ */\n+ PSRAM_WINBOND_6_CLOCKS_LATENCY, /*!< PSRAM 6 clocks latency 166MHZ */\n+ PSRAM_WINBOND_7_CLOCKS_LATENCY, /*!< PSRAM 7 clocks latency 200MHZ */\n+ PSRAM_WINBOND_3_CLOCKS_LATENCY = 0xE, /*!< PSRAM 3 clocks latency 83MHZ */\n+ PSRAM_WINBOND_4_CLOCKS_LATENCY = 0xF, /*!< PSRAM 4 clocks latency 100MHZ */\n+ PSRAM_WINBOND_14_CLOCKS_LATENCY = 0x7, /*!< PSRAM 14 clocks latency only for Hyperbus3 400MHZ */\n+ PSRAM_WINBOND_19_CLOCKS_LATENCY = 0x9, /*!< PSRAM 19 clocks latency only for Hyperbus3 533MHZ */\n+} PSRAM_Latency_Winbond_Type;\n+\n+/**\n+ * @brief PSRAM Burst Type\n+ */\n+typedef enum {\n+ PSRAM_HYBRID_BURST, /*!< PSRAM use hybrid brust */\n+ PSRAM_WRAPPED_BURST, /*!< PSRAM use warpped brust */\n+} PSRAM_Burst_Type;\n+\n+/**\n+ * @brief PSRAM Latency Counter type definition\n+ */\n+typedef enum {\n+ PSRAM_APMEM_3_CLOCKS_LATENCY, /*!< PSRAM 3 clocks latency */\n+ PSRAM_APMEM_4_CLOCKS_LATENCY = 0x4, /*!< PSRAM 4 clocks latency */\n+ PSRAM_APMEM_5_CLOCKS_LATENCY = 0x2, /*!< PSRAM 5 clocks latency */\n+ PSRAM_APMEM_6_CLOCKS_LATENCY = 0x6, /*!< PSRAM 6 clocks latency */\n+ PSRAM_APMEM_7_CLOCKS_LATENCY = 0x1, /*!< PSRAM 7 clocks latency */\n+} PSRAM_Latency_ApMem_Type;\n+\n+/**\n+ * @brief PSRAM Drive Strength type definition for Winbon 4M\n+ */\n+typedef enum {\n+ PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M, /*!< drive strength 50 ohms for 4M size ,34 ohms for 8M size */\n+ PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, /*!< drive strength 35 ohms for 4M size ,115 ohms for 8M size */\n+ PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M, /*!< drive strength 100 ohms for 4M size ,67 ohms for 8M size */\n+ PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M, /*!< drive strength 200 ohms for 4M size ,46 ohms for 8M size */\n+ PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M, /*!< drive strength 34 ohms only for 8M size */\n+ PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M, /*!< drive strength 27 ohms only for 8M size */\n+ PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M, /*!< drive strength 22 ohms only for 8M size */\n+ PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M, /*!< drive strength 19 ohms only for 8M size */\n+} PSRAM_Winbond_Drive_Strength;\n+\n+/**\n+ * @brief PSRAM Drive Strength type definition for Winbon 8MB\n+ */\n+typedef enum {\n+ PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS, /*!< drive strength 25 ohms */\n+ PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS, /*!< drive strength 50 ohms */\n+ PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS, /*!< drive strength 100 ohms */\n+ PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS, /*!< drive strength 200 ohms */\n+} PSRAM_ApMem_Drive_Strength;\n+\n+/**\n+ * @brief PSRAM Burst Length type definition\n+ */\n+typedef enum {\n+ PSRAM_WINBOND_BURST_LENGTH_128_BYTES, /*!< Burst Length 128 bytes */\n+ PSRAM_WINBOND_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */\n+ PSRAM_WINBOND_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */\n+ PSRAM_WINBOND_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */\n+ PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */\n+} PSRAM_Winbond_Burst_Length;\n+\n+/**\n+ * @brief PSRAM Burst Length type definition\n+ */\n+typedef enum {\n+ PSRAM_APMEM_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */\n+ PSRAM_APMEM_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */\n+ PSRAM_APMEM_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */\n+ PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256, /*!< Burst Length 1K bytes for APS6408L and 2Kbytes for APS256XXN */\n+} PSRAM_ApMem_Burst_Length;\n+\n+/**\n+ * @brief PSRAM Fixed Latency Enable type definition\n+ */\n+typedef enum {\n+ PSRAM_VARIALBE_INITIAL_LATENCY, /*!< 1 or 2 times Initial Latency depending on RWDS during CA cycles */\n+ PSRAM_FIXED_2_TIMES_INITIAL_LATENCY, /*!< Fixed 2 times Initial Latency (default) */\n+} PSRAM_Fixed_Latency_Enable;\n+\n+/**\n+ * @brief PSRAM Deep Power Down Enable type definition\n+ */\n+typedef enum {\n+ PSRAM_DPD_ENTER, /*!< Writing 0 to CR0[15] causes the device to enter Deep Power Down */\n+ PSRAM_DPD_NORMAL, /*!< Normal operation (default) */\n+} PSRAM_Deep_Power_Down;\n+\n+/**\n+ * @brief Partial Array Self Refresh definition\n+ */\n+typedef enum {\n+ PSRAM_PARTIAL_REFRESH_FULL, /*!< PSRAM partial refresh full array (000000h - 1FFFFFh) */\n+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2, /*!< PSRAM partial refresh Bottom 1/2 array (000000h - 0FFFFFh) */\n+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4, /*!< PSRAM partial refresh Bottom 1/4 array (000000h - 07FFFFh) */\n+ PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8, /*!< PSRAM partial refresh Bottom 1/8 array (000000h - 03FFFFh) */\n+ PSRAM_PARTIAL_REFRESH_NONE, /*!< PSRAM partial refresh None */\n+ PSRAM_PARTIAL_REFRESH_TOP_1TO2, /*!< PSRAM partial refresh Top 1/2 array (100000h - 1FFFFFh) */\n+ PSRAM_PARTIAL_REFRESH_TOP_1TO4, /*!< PSRAM partial refresh Top 1/4 array (180000h - 1FFFFFh) */\n+ PSRAM_PARTIAL_REFRESH_TOP_1TO8, /*!< PSRAM partial refresh Top 1/8 array (1C0000h - 1FFFFFh) */\n+} PSRAM_Partial_Array_Refresh;\n+\n+/**\n+ * @brief PSRAM ApMem self-fresh freq\n+ */\n+typedef enum {\n+ PSRAM_APMEM_FAST_REFRESH, /*!< Fast Refresh (default) */\n+ PSRAM_APMEM_SLOW_REFRESH, /*!< Enables Slow Refresh when temperature allows */\n+} PSRAM_ApMem_Refresh_Speed;\n+\n+/**\n+ * @brief PSRAM Hybrid Sleep Mode type definition\n+ */\n+typedef enum {\n+ PSRAM_HYBRID_SLEEP_DISABLE, /*!< not in Hybrid Sleep Mode */\n+ PSRAM_HYBRID_SLEEP_ENABLE, /*!< entering Hybrid Sleep Mode */\n+} PSRAM_Hybrid_Sleep_Mode;\n+\n+/**\n+ * @brief PSRAM Master Clock type definition\n+ */\n+typedef enum {\n+ PSRAM_CLOCK_DIFF, /*!< PSRAM Master Clock is differential */\n+ PSRAM_CLOCK_SINGLE, /*!< PSRAM Master Clock is single end */\n+} PSRAM_Clock_Type;\n+\n+/**\n+ * @brief PSRAM delay chain configuration definition\n+ */\n+typedef struct\n+{\n+ PSRAM_Ctrl_Vendor_Type vendor; /*!< PSRAM Vendor */\n+ PSRAM_Ctrl_Io_Mode_Type ioMode; /*!< PSRAM interface mode */\n+ PSRAM_Ctrl_Size_Type size; /*!< PSRAM size */\n+} PSRAM_Ctrl_Cfg_Type;\n+\n+/**\n+ * @brief PSRAM Winbon configuration definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type rst; /*!< Winbond pSRAM CR1 - Software Reset */\n+ PSRAM_Clock_Type clockType; /*!< Winbond pSRAM CR1 - Master Clock Type */\n+ BL_Fun_Type inputPowerDownMode; /*!< Winbond pSRAM CR1 - Input Power Down */\n+ BL_Fun_Type linear_dis; /*!< Winbond pSRAM linear burst disable */\n+ BL_Fun_Type hybridSleepMode; /*!< Winbond pSRAM CR1 - Hybrid Sleep Mode configuration */\n+ PSRAM_Partial_Array_Refresh PASR; /*!< Winbond pSRAM CR1 - Partial Array Refresh + Distributed Refresh Interval */\n+ BL_Fun_Type disDeepPowerDownMode; /*!< Winbond pSRAM CR0 - Deep Power-Down Disable configuration */\n+ BL_Fun_Type fixedLatency; /*!< Winbond pSRAM CR1 - Fix Latency configuration */\n+ PSRAM_Winbond_Burst_Length brustLen; /*!< Winbond pSRAM CR0 - Burst Length configuration */\n+ PSRAM_Burst_Type brustType; /*!< Winbond pSRAM CR0 - Hybrid Burst Enable */\n+ PSRAM_Winbond_Drive_Strength driveStrength; /*!< Winbond pSRAM CR0 - Drive Strength configuration */\n+ PSRAM_Latency_Winbond_Type latency; /*!< Winbond pSRAM CR0 - Latency Counter configuration */\n+} PSRAM_Winbond_Cfg_Type;\n+\n+/**\n+ * @brief PSRAM Winbon configuration definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type rst; /*!< AP Memory pSRAM configure global reset enable */\n+ BL_Fun_Type fixedLatency; /*!< AP Memory pSRAM configure MR0 - read latency type */\n+ PSRAM_Latency_ApMem_Type readLatency; /*!< AP Memory pSRAM configure MR0 - read latency code */\n+ PSRAM_ApMem_Refresh_Speed refreshFreq; /*!< AP Memory pSRAM configure MR4 - refresh frequency */\n+ PSRAM_ApMem_Drive_Strength driveStrength; /*!< AP Memory pSRAM configure MR0 - drive strength */\n+ PSRAM_Latency_ApMem_Type writeLatency; /*!< AP Memory pSRAM configure MR4 - write latency code */\n+ PSRAM_Partial_Array_Refresh PASR; /*!< AP Memory pSRAM configure MR4 - partial array refresh */\n+ BL_Fun_Type halfSleepModeEnable; /*!< AP Memory pSRAM configure MR6 - Half Sleep enable */\n+ BL_Fun_Type deepPowerDownModeEnable; /*!< AP Memory pSRAM configure MR6 - Deep Power Down enable */\n+ BL_Fun_Type crossBoundaryEnable; /*!< AP Memory pSRAM configure MR8 - cross boundary enable 1'b0 - Read within 1K boundary 1'b1 -\n+ Read cross 1K boundary */\n+ PSRAM_Burst_Type brustType; /*!< AP Memory pSRAM configure MR8 - burst type */\n+ PSRAM_ApMem_Burst_Length brustLen; /*!< AP Memory pSRAM configure MR8 - burst length */\n+} PSRAM_APMemory_Cfg_Type;\n+\n+/*@} end of group PSRAM_CTRL_Public_Types */\n+\n+/** @defgroup PSRAM_CTRL_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_ID_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID) || \\\n+ ((type) == PSRAM1_ID))\n+\n+/** @defgroup PSRAM_CTRL_IO_MODE_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CTRL_IO_MODE_TYPE(type) (((type) == PSRAM_CTRL_X8_MODE) || \\\n+ ((type) == PSRAM_CTRL_X16_MODE))\n+\n+/** @defgroup PSRAM_CTRL_VENDOR_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CTRL_VENDOR_TYPE(type) (((type) == PSRAM_CTRL_VENDOR_WINBOND) || \\\n+ ((type) == PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB) || \\\n+ ((type) == PSRAM_CTRL_VENDOR_APMEM_4MB))\n+\n+/** @defgroup PSRAM_CTRL_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CTRL_SIZE_TYPE(type) (((type) == PSRAM_SIZE_4MB) || \\\n+ ((type) == PSRAM_SIZE_8MB) || \\\n+ ((type) == PSRAM_SIZE_16MB) || \\\n+ ((type) == PSRAM_SIZE_32MB))\n+\n+/** @defgroup PSRAM_CTRL_WINBOND_CFG_REG_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(type) (((type) == PSRAM_WINBOND_REG_ID0) || \\\n+ ((type) == PSRAM_WINBOND_REG_ID1) || \\\n+ ((type) == PSRAM_WINBOND_REG_CR0) || \\\n+ ((type) == PSRAM_WINBOND_REG_CR1) || \\\n+ ((type) == PSRAM_WINBOND_REG_CR2) || \\\n+ ((type) == PSRAM_WINBOND_REG_CR3) || \\\n+ ((type) == PSRAM_WINBOND_REG_CR4))\n+\n+/** @defgroup PSRAM_CTRL_APMEM_CFG_REG_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(type) (((type) == PSRAM_APMEM_REG_0) || \\\n+ ((type) == PSRAM_APMEM_REG_1) || \\\n+ ((type) == PSRAM_APMEM_REG_2) || \\\n+ ((type) == PSRAM_APMEM_REG_3) || \\\n+ ((type) == PSRAM_APMEM_REG_4) || \\\n+ ((type) == PSRAM_APMEM_REG_5) || \\\n+ ((type) == PSRAM_APMEM_REG_6) || \\\n+ ((type) == PSRAM_APMEM_REG_8))\n+\n+/** @defgroup PSRAM_LATENCY_WINBOND_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_LATENCY_WINBOND_TYPE(type) (((type) == PSRAM_WINBOND_5_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_6_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_7_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_3_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_4_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_14_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_WINBOND_19_CLOCKS_LATENCY))\n+\n+/** @defgroup PSRAM_BURST_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_BURST_TYPE(type) (((type) == PSRAM_HYBRID_BURST) || \\\n+ ((type) == PSRAM_WRAPPED_BURST))\n+\n+/** @defgroup PSRAM_LATENCY_APMEM_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_LATENCY_APMEM_TYPE(type) (((type) == PSRAM_APMEM_3_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_APMEM_4_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_APMEM_5_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_APMEM_6_CLOCKS_LATENCY) || \\\n+ ((type) == PSRAM_APMEM_7_CLOCKS_LATENCY))\n+\n+/** @defgroup PSRAM_WINBOND_DRIVE_STRENGTH\n+ * @{\n+ */\n+#define IS_PSRAM_WINBOND_DRIVE_STRENGTH(type) (((type) == PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M) || \\\n+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M) || \\\n+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M) || \\\n+ ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M) || \\\n+ ((type) == PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M) || \\\n+ ((type) == PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M) || \\\n+ ((type) == PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M) || \\\n+ ((type) == PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M))\n+\n+/** @defgroup PSRAM_APMEM_DRIVE_STRENGTH\n+ * @{\n+ */\n+#define IS_PSRAM_APMEM_DRIVE_STRENGTH(type) (((type) == PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS) || \\\n+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS) || \\\n+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS) || \\\n+ ((type) == PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS))\n+\n+/** @defgroup PSRAM_WINBOND_BURST_LENGTH\n+ * @{\n+ */\n+#define IS_PSRAM_WINBOND_BURST_LENGTH(type) (((type) == PSRAM_WINBOND_BURST_LENGTH_128_BYTES) || \\\n+ ((type) == PSRAM_WINBOND_BURST_LENGTH_64_BYTES) || \\\n+ ((type) == PSRAM_WINBOND_BURST_LENGTH_16_BYTES) || \\\n+ ((type) == PSRAM_WINBOND_BURST_LENGTH_32_BYTES) || \\\n+ ((type) == PSRAM_WINBOND_BURST_LENGTH_512_BYTES))\n+\n+/** @defgroup PSRAM_APMEM_BURST_LENGTH\n+ * @{\n+ */\n+#define IS_PSRAM_APMEM_BURST_LENGTH(type) (((type) == PSRAM_APMEM_BURST_LENGTH_16_BYTES) || \\\n+ ((type) == PSRAM_APMEM_BURST_LENGTH_32_BYTES) || \\\n+ ((type) == PSRAM_APMEM_BURST_LENGTH_64_BYTES) || \\\n+ ((type) == PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256))\n+\n+/** @defgroup PSRAM_FIXED_LATENCY_ENABLE\n+ * @{\n+ */\n+#define IS_PSRAM_FIXED_LATENCY_ENABLE(type) (((type) == PSRAM_VARIALBE_INITIAL_LATENCY) || \\\n+ ((type) == PSRAM_FIXED_2_TIMES_INITIAL_LATENCY))\n+\n+/** @defgroup PSRAM_DEEP_POWER_DOWN\n+ * @{\n+ */\n+#define IS_PSRAM_DEEP_POWER_DOWN(type) (((type) == PSRAM_DPD_ENTER) || \\\n+ ((type) == PSRAM_DPD_NORMAL))\n+\n+/** @defgroup PSRAM_PARTIAL_ARRAY_REFRESH\n+ * @{\n+ */\n+#define IS_PSRAM_PARTIAL_ARRAY_REFRESH(type) (((type) == PSRAM_PARTIAL_REFRESH_FULL) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_NONE) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO2) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO4) || \\\n+ ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO8))\n+\n+/** @defgroup PSRAM_APMEM_REFRESH_SPEED\n+ * @{\n+ */\n+#define IS_PSRAM_APMEM_REFRESH_SPEED(type) (((type) == PSRAM_APMEM_FAST_REFRESH) || \\\n+ ((type) == PSRAM_APMEM_SLOW_REFRESH))\n+\n+/** @defgroup PSRAM_HYBRID_SLEEP_MODE\n+ * @{\n+ */\n+#define IS_PSRAM_HYBRID_SLEEP_MODE(type) (((type) == PSRAM_HYBRID_SLEEP_DISABLE) || \\\n+ ((type) == PSRAM_HYBRID_SLEEP_ENABLE))\n+\n+/** @defgroup PSRAM_CLOCK_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_CLOCK_TYPE(type) (((type) == PSRAM_CLOCK_DIFF) || \\\n+ ((type) == PSRAM_CLOCK_SINGLE))\n+\n+/*@} end of group PSRAM_CTRL_Public_Constants */\n+\n+/** @defgroup PSRAM_CTRL_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Public_Macros */\n+\n+/** @defgroup PSRAM_CTRL_Public_Functions\n+ * @{\n+ */\n+void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);\n+void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);\n+void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,\n+ PSRAM_Winbond_Cfg_Type *reg_cfg);\n+void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);\n+void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,\n+ PSRAM_APMemory_Cfg_Type *reg_cfg);\n+void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);\n+void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);\n+void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);\n+uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID);\n+void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID);\n+void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr);\n+\n+/*@} end of group PSRAM_CTRL_Public_Functions */\n+\n+/*@} end of group PSRAM_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_PSRAM_CTRL_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..740b0180fa8210789a241ec0710cac206195ad1d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h\n@@ -0,0 +1,272 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_psram_uhs.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_PSRAM_UHS_H__\n+#define __BL808_PSRAM_UHS_H__\n+\n+#include \"psram_uhs_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PSRAM_UHS\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_UHS_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief Psram UHS Size\n+ */\n+typedef enum {\n+ PSRAM_MEM_SIZE_4MB = 0x03, /*!< PSRAM Memory Size 4M */\n+ PSRAM_MEM_SIZE_8MB = 0x07, /*!< PSRAM Memory Size 8M */\n+ PSRAM_MEM_SIZE_16MB = 0x0f, /*!< PSRAM Memory Size 16M */\n+ PSRAM_MEM_SIZE_32MB = 0x1f, /*!< PSRAM Memory Size 32M */\n+ PSRAM_MEM_SIZE_64MB = 0x3f, /*!< PSRAM Memory Size 64M */\n+} PSRAM_UHS_Mem_Size_Type;\n+\n+/**\n+ * @brief Psram UHS Page Type\n+ */\n+typedef enum {\n+ PSRAM_PAGE_SIZE_2KB = 0x0B, /*!< PSRAM Page Size 2KB */\n+ PSRAM_PAGE_SIZE_4KB = 0x16, /*!< PSRAM Page Size 4KB */\n+} PSRAM_UHS_Page_Size_Type;\n+\n+/**\n+ * @brief Psram UHS Burst Size\n+ */\n+typedef enum {\n+ PSRAM_UHS_WARP_BURST_64, /*!< PSRAM Warp Burst Size 64 */\n+ PSRAM_UHS_WARP_BURST_32, /*!< PSRAM Warp Burst Size 32 */\n+ PSRAM_UHS_WARP_BURST_16, /*!< PSRAM Warp Burst Size 16 */\n+ PSRAM_UHS_WARP_BURST_NONE, /*!< PSRAM Warp Burst NONE */\n+ PSRAM_UHS_WARP_BURST_NO_CHANGE, /*!< Not change this value */\n+} PSRAM_UHS_WARP_BURST_Type;\n+\n+/**\n+ * @brief Psram UHS Driver Strength\n+ */\n+typedef enum {\n+ PSRAM_UHS_DRIVER_ST_34P3_PDPU = 0x1, /*!< 34.3 PD/PU */\n+ PSRAM_UHS_DRIVER_ST_40_PDPU = 0x2, /*!< 40 PD/PU */\n+ PSRAM_UHS_DRIVER_ST_48_PDPU = 0x3, /*!< 48 PD/PU */\n+ PSRAM_UHS_DRIVER_ST_60_PDPU = 0x4, /*!< 60 PD/PU */\n+ PSRAM_UHS_DRIVER_ST_80_PDPU = 0x6, /*!< 80 PD/PU */\n+ PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU = 0x9, /*!< 34.3 PD & 40 PU */\n+ PSRAM_UHS_DRIVER_ST_40_PD_48_PU = 0xa, /*!< 40 PD & 48 PU */\n+ PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU = 0xb, /*!< 34.3 PD & 48 PU */\n+ PSRAM_UHS_DRIVER_ST_NO_CHANGE = 0xf, /*!< Not change this value */\n+} PSRAM_UHS_DRIVER_ST_Type;\n+\n+/**\n+ * @brief Psram UHS LATENCY\n+ */\n+typedef enum {\n+ PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ, /*!< MAX freq. = 533 MHz / Write LATENCY=10 / Read LATENCY=20 */\n+ PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ, /*!< MAX freq. = 800 MHz / Write LATENCY=14 / Read LATENCY=29 */\n+ PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ, /*!< MAX freq. = 933 MHz / Write LATENCY=16 / Read LATENCY=33 */\n+ PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, /*!< MAX freq. = 1066 MHz / Write LATENCY=18 / Read LATENCY=37 */\n+ PSRAM_UHS_LATENCY_RESERVED, /*!< Reserved */\n+ PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ, /*!< MAX freq. = 400 MHz / Write LATENCY=6 / Read LATENCY=16 */\n+ PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ, /*!< MAX freq. = 333 MHz / Write LATENCY=5 / Read LATENCY=13 */\n+ PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ, /*!< MAX freq. = 200 MHz / Write LATENCY=5 / Read LATENCY=9 */\n+ PSRAM_UHS_LATENCY_NO_CHANGE, /*!< Not change this value */\n+} PSRAM_UHS_LATENCY_Type;\n+\n+/**\n+ * @brief Psram UHS CMD Type\n+ */\n+typedef enum {\n+ PSRAM_UHS_CMD_SELF_REFRESH_IN, /*!< pSRAM self-refresh in command */\n+ PSRAM_UHS_CMD_SELF_REFRESH_EXIT, /*!< pSRAM self-refresh exit command */\n+ PSRAM_UHS_CMD_GLOBAL_RESET, /*!< pSRAM global reset command */\n+ PSRAM_UHS_CMD_ZQ_CAL_LONG, /*!<ZQ calibration, long> */\n+ PSRAM_UHS_CMD_ZQ_CAL_SHORT, /*!<ZQ calibration, short>*/\n+ PSRAM_UHS_CMD_ZQ_CAL_RESET, /*!<ZQ calibration,reset>*/\n+} PSRAM_UHS_CMD_Type;\n+\n+/**\n+ * @brief PSRAM UHS Temperature\n+ *\n+ */\n+typedef enum {\n+ PSRAM_UHS_NORMAL_TEMP,\n+ PSRAM_UHS_HIGH_TEMP,\n+} PSRAM_UHS_TEMP_Type;\n+\n+/**\n+ * @brief PSRAM_UHS_Cfg_Type\n+ */\n+typedef struct {\n+ uint32_t pck_freq; /*!< pck frequency unit is MHZ */\n+ PSRAM_UHS_Mem_Size_Type psramMemSize; /*!< psram uhm memory size */\n+ PSRAM_UHS_Page_Size_Type psramPageSize; /*!< psram uhm page size */\n+ PSRAM_UHS_TEMP_Type isHighTem; /*!< auto refresh work temperature */\n+} PSRAM_UHS_Cfg_Type;\n+\n+/**\n+ * @brief PSRAM_UHS_Phy_Latency_Pra_Type\n+ */\n+typedef struct {\n+ uint8_t phy_rl_ana; /*!< phy_rl_ana */\n+ uint8_t phy_rl_dig; /*!< phy_rl_dig*/\n+ uint8_t phy_wl_ana; /*!< phy_wl_ana */\n+ uint8_t phy_wl_dig; /*!< phy_wl_dig*/\n+ uint8_t phy_wl_dq_ana; /*!< phy_wl_dq_ana */\n+ uint8_t phy_wl_dq_dig; /*!< phy_wl_dq_dig */\n+\n+ uint8_t reg_timer_array_read; /*!< reg_timer_array_read */\n+ uint8_t reg_timer_array_write; /*!< reg_timer_array_write */\n+ uint8_t reg_timer_dqs_array_stop; /*!< reg_timer_dqs_array_stop */\n+ uint8_t reg_timer_dqs_start; /*!< reg_timer_dqs_start */\n+\n+ uint8_t reg_timer_dqs_stop; /*!< reg_timer_dqs_stop */\n+ uint8_t reg_timer_reg_read; /*!< reg_timer_reg_read */\n+ uint8_t reg_timer_reg_write; /*!< reg_timer_reg_write */\n+ uint8_t reg_timer_auto_refresh; /*!< reg_timer_auto_refresh */\n+\n+ uint16_t reg_timer_global_rst; /*!< reg_timer_global_rst */\n+ uint8_t reg_timer_self_refresh1_in; /*!< reg_timer_self_refresh1_in */\n+ uint8_t reg_timer_self_refresh1_exit; /*!< reg_timer_self_refresh1_exit */\n+\n+ uint8_t reg_timer_reg_write_busy; /*!< reg_timer_reg_write_busy */\n+ uint8_t reg_timer_reg_read_busy; /*!< reg_timer_reg_read_busy */\n+ uint8_t reg_timer_arrary_write_busy; /*!< reg_timer_arrary_write_busy */\n+ uint8_t reg_timer_arrary_read_busy; /*!< reg_timer_arrary_read_busy */\n+\n+ uint8_t en_rx_fe_dly; /*!< en_rx_fe_dly */\n+ uint8_t odt_sel_dly; /*!< odt_sel_dly */\n+\n+ uint8_t reg_trc_cycle; /*!< reg_trc_cycle */\n+ uint8_t reg_trfc_cycle; /*!< reg_trfc_cycle */\n+ uint8_t reg_tcphr_cycle; /*!< reg_tcphr_cycle */\n+ uint8_t reg_tcphw_cycle; /*!< reg_tcphw_cycle */\n+\n+} PSRAM_UHS_Phy_Latency_Pra_Type;\n+\n+/**\n+ * @brief PSRAM_UHS_Write_Reg_Cfg_Type\n+ */\n+typedef struct {\n+ PSRAM_UHS_DRIVER_ST_Type driver_st; /*!< driver strength */\n+ PSRAM_UHS_WARP_BURST_Type burst_size; /*!< burst size */\n+ PSRAM_UHS_LATENCY_Type lentency; /*!< lentency */\n+} PSRAM_UHS_Write_Reg_Cfg_Type;\n+\n+/*@} end of group PSRAM_UHS_Public_Types */\n+\n+/** @defgroup PSRAM_UHS_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_UHS_MEM_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_MEM_SIZE_TYPE(type) (((type) == PSRAM_MEM_SIZE_4MB) || \\\n+ ((type) == PSRAM_MEM_SIZE_8MB) || \\\n+ ((type) == PSRAM_MEM_SIZE_16MB) || \\\n+ ((type) == PSRAM_MEM_SIZE_32MB))\n+\n+/** @defgroup PSRAM_UHS_PAGE_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_PAGE_SIZE_TYPE(type) (((type) == PSRAM_PAGE_SIZE_2KB) || \\\n+ ((type) == PSRAM_PAGE_SIZE_4KB))\n+\n+/** @defgroup PSRAM_UHS_WARP_BURST_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_WARP_BURST_TYPE(type) (((type) == PSRAM_UHS_WARP_BURST_64) || \\\n+ ((type) == PSRAM_UHS_WARP_BURST_32) || \\\n+ ((type) == PSRAM_UHS_WARP_BURST_16))\n+\n+/** @defgroup PSRAM_UHS_DRIVER_ST_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_DRIVER_ST_TYPE(type) (((type) == PSRAM_UHS_DRIVER_ST_34P3_PUPU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_40_PUPU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_48_PUPU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_60_PUPU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_80_PUPU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_40_PD_48_PU) || \\\n+ ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU))\n+\n+/** @defgroup PSRAM_UHS_LATENCY_TYPE\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_LATENCY_TYPE(type) (((type) == PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ) || \\\n+ ((type) == PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ))\n+/** @defgroup PSRAM_UHS_CMD_Type\n+ * @{\n+ */\n+#define IS_PSRAM_UHS_CMD_TYPE(type) (((type) == PSRAM_UHS_CMD_SELF_REFRESH_IN) || \\\n+ ((type) == PSRAM_UHS_CMD_SELF_REFRESH_EXIT) || \\\n+ ((type) == PSRAM_UHS_CMD_GLOBAL_RESET)\n+\n+/*@} end of group PSRAM_UHS_Public_Constants */\n+\n+/** @defgroup PSRAM_UHS_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Public_Macros */\n+\n+/** @defgroup PSRAM_UHS_Public_Functions\n+ * @{\n+ */\n+void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg);\n+int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal);\n+int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg);\n+int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd);\n+void Psram_UHS_x16_Init(uint32_t uhs_pll_clk);\n+/*@} end of group PSRAM_UHS_Public_Functions */\n+\n+/*@} end of group PSRAM_UHS */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_PSRAM_UHS_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..efdd41cfa85b236fa8a5252365d384a98f20a027\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h\n@@ -0,0 +1,356 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_pwm.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_PWM_H__\n+#define __BL808_PWM_H__\n+\n+#include \"pwm_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PWM\n+ * @{\n+ */\n+\n+/** @defgroup PWM_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief PWM No. type definition\n+ */\n+typedef enum {\n+ PWM0_ID = 0, /*!< PWM Channel 0 define */\n+ PWM1_ID, /*!< PWM Channel 1 define */\n+ PWMx_ID_MAX, /*!< */\n+} PWMx_ID_Type;\n+\n+/**\n+ * @brief PWM Clock definition\n+ */\n+typedef enum {\n+ PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */\n+ PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */\n+ PWM_CLK_32K, /*!< PWM Clock source :32K CLK */\n+} PWM_Clk_Type;\n+\n+/**\n+ * @brief PWM Stop Mode definition\n+ */\n+typedef enum {\n+ PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */\n+ PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */\n+} PWM_Stop_Mode_Type;\n+\n+/**\n+ * @brief PWM mode type def\n+ */\n+typedef enum {\n+ PWM_POL_ACTIVE_LOW = 0, /*!< PWM active low polarity mode define */\n+ PWM_POL_ACTIVE_HIGH, /*!< PWM active high polarity mode define */\n+} PWM_Polarity_Type;\n+\n+/**\n+ * @brief PWM interrupt type def\n+ */\n+typedef enum {\n+ PWM_INT_CH0L = 0, /*!< PWM Channel 0L interrupt define */\n+ PWM_INT_CH0H, /*!< PWM Channel 0H interrupt define */\n+ PWM_INT_CH1L, /*!< PWM Channel 1H interrupt define */\n+ PWM_INT_CH1H, /*!< PWM Channel 1H interrupt define */\n+ PWM_INT_CH2L, /*!< PWM Channel 2L interrupt define */\n+ PWM_INT_CH2H, /*!< PWM Channel 2H interrupt define */\n+ PWM_INT_CH3L, /*!< PWM Channel 3L interrupt define */\n+ PWM_INT_CH3H, /*!< PWM Channel 3H interrupt define */\n+ PWM_INT_PRDE, /*!< PWM Period end interrupt define */\n+ PWM_INT_BRK, /*!< PWM break interrupt define */\n+ PWM_INT_REPT, /*!< PWM repeat interrupt define */\n+ PWM_INT_ALL, /*!< */\n+} PWM_INT_Type;\n+\n+/**\n+ * @brief PWM Channel No. type definition\n+ */\n+typedef enum {\n+ PWM_CH0 = 0, /*!< PWM Channel 0 define */\n+ PWM_CH1, /*!< PWM Channel 1 define */\n+ PWM_CH2, /*!< PWM Channel 2 define */\n+ PWM_CH3, /*!< PWM Channel 3 define */\n+ PWM_CHx_MAX, /*!< */\n+} PWM_CHx_Type;\n+\n+/**\n+ * @brief PWM Mode type definition\n+ */\n+typedef enum {\n+ PWM_MODE_DISABLE = 0, /*!< PWM Mode Disable define */\n+ PWM_MODE_ENABLE, /*!< PWM Mode Enable define */\n+} PWM_Mode_Type;\n+\n+/**\n+ * @brief PWM Idel State type definition\n+ */\n+typedef enum {\n+ PWM_IDLE_STATE_INACTIVE = 0, /*!< PWM Idle State Inactive define */\n+ PWM_IDLE_STATE_ACTIVE, /*!< PWM Idle State Active define */\n+} PWM_Idle_State_Type;\n+\n+/**\n+ * @brief PWM break State type definition\n+ */\n+typedef enum {\n+ PWM_BREAK_STATE_INACTIVE = 0, /*!< PWM Break State Inactive define */\n+ PWM_BREAK_STATE_ACTIVE, /*!< PWM Break State Active define */\n+} PWM_Break_State_Type;\n+\n+/**\n+ * @brief PWM EXT break Polarity Level type definition\n+ */\n+typedef enum {\n+ PWM_BREAK_Polarity_LOW = 0, /*!< PWM EXT Break Polarity Low Level define */\n+ PWM_BREAK_Polarity_HIGH, /*!< PWM EXT Break Polarity High Level define */\n+} PWM_EXT_Break_Polarity_Type;\n+\n+/**\n+ * @brief PWM Trig ADC Source type definition\n+ */\n+typedef enum {\n+ PWM_TRIGADC_SOURCE_0L = 0, /*!< PWM Channel 0 Threshold L Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_0H, /*!< PWM Channel 0 Threshold H Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_1L, /*!< PWM Channel 1 Threshold L Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_1H, /*!< PWM Channel 1 Threshold H Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_2L, /*!< PWM Channel 2 Threshold L Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_2H, /*!< PWM Channel 2 Threshold H Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_3L, /*!< PWM Channel 3 Threshold L Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_3H, /*!< PWM Channel 3 Threshold H Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_PRDE, /*!< PWM Period End Reached Trig ADC Source define */\n+ PWM_TRIGADC_SOURCE_NONE = 0xF, /*!< PWM None Trig ADC Source define */\n+} PWM_TrigADC_Source_Type;\n+\n+/**\n+ * @brief PWM configuration structure type definition\n+ */\n+typedef struct {\n+ PWM_Clk_Type clk; /*!< PWM Clock */\n+ PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */\n+ PWM_EXT_Break_Polarity_Type extPol; /*!< PWM EXT_Break Polarity */\n+ PWM_TrigADC_Source_Type adcSrc; /*!< PWM TrigADC Source */\n+ BL_Fun_Type stpRept; /*!< PWM Stop On Rept */\n+ uint16_t clkDiv; /*!< PWM clkDiv num */\n+ uint16_t period; /*!< PWM period set */\n+ uint16_t intPulseCnt; /*!< PWM interrupt pulse count */\n+} PWMx_CFG_Type;\n+\n+/**\n+ * @brief PWM CC configuration structure type definition\n+ */\n+typedef struct {\n+ PWM_Mode_Type modP; /*!< PWM Channelx Positive PWM mode type */\n+ PWM_Mode_Type modN; /*!< PWM Channelx Negative PWM mode type */\n+ PWM_Polarity_Type polP; /*!< PWM Channelx Positive polarity type */\n+ PWM_Polarity_Type polN; /*!< PWM Channelx Negative polarity type */\n+ PWM_Idle_State_Type idlP; /*!< PWM Channelx Positive idle state type */\n+ PWM_Idle_State_Type idlN; /*!< PWM Channelx Negative idle state type */\n+ PWM_Break_State_Type brkP; /*!< PWM Channelx Positive break state type */\n+ PWM_Break_State_Type brkN; /*!< PWM Channelx Negative break state type */\n+ uint16_t thresholdL; /*!< PWM thresholdL number */\n+ uint16_t thresholdH; /*!< PWM thresholdH number */\n+ uint8_t dtg; /*!< PWM Channelx deadtime generator */\n+} PWM_CHx_CFG_Type;\n+\n+/*@} end of group PWM_Public_Types */\n+\n+/** @defgroup PWM_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup PWMx_ID_TYPE\n+ * @{\n+ */\n+#define IS_PWMx_ID_TYPE(type) (((type) == PWM0_ID) || \\\n+ ((type) == PWM1_ID) || \\\n+ ((type) == PWM_CH_MAX))\n+\n+/** @defgroup PWM_CLK_TYPE\n+ * @{\n+ */\n+#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \\\n+ ((type) == PWM_CLK_BCLK) || \\\n+ ((type) == PWM_CLK_32K))\n+\n+/** @defgroup PWM_STOP_MODE_TYPE\n+ * @{\n+ */\n+#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \\\n+ ((type) == PWM_STOP_GRACEFUL))\n+\n+/** @defgroup PWM_POLARITY_TYPE\n+ * @{\n+ */\n+#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_ACTIVE_LOW) || \\\n+ ((type) == PWM_POL_ACTIVE_HIGH))\n+\n+/** @defgroup PWM_INT_TYPE\n+ * @{\n+ */\n+#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_CH0L) || \\\n+ ((type) == PWM_INT_CH0H) || \\\n+ ((type) == PWM_INT_CH1L) || \\\n+ ((type) == PWM_INT_CH1H) || \\\n+ ((type) == PWM_INT_CH2L) || \\\n+ ((type) == PWM_INT_CH2H) || \\\n+ ((type) == PWM_INT_CH3L) || \\\n+ ((type) == PWM_INT_CH3H) || \\\n+ ((type) == PWM_INT_PRDE) || \\\n+ ((type) == PWM_INT_BRK) || \\\n+ ((type) == PWM_INT_REPT) || \\\n+ ((type) == PWM_INT_ALL))\n+\n+/** @defgroup PWM_CHx_TYPE\n+ * @{\n+ */\n+#define IS_PWM_CHx_TYPE(type) (((type) == PWM_CH0) || \\\n+ ((type) == PWM_CH1) || \\\n+ ((type) == PWM_CH2) || \\\n+ ((type) == PWM_CH3) || \\\n+ ((type) == PWM_CH_MAX))\n+\n+/** @defgroup PWM_MODE_TYPE\n+ * @{\n+ */\n+#define IS_PWM_MODE_TYPE(type) (((type) == PWM_MODE_DISABLE) || \\\n+ ((type) == PWM_Mode_ENABLE))\n+\n+/** @defgroup PWM_IDLE_STATE_TYPE\n+ * @{\n+ */\n+#define IS_PWM_IDLE_STATE_TYPE(type) (((type) == PWM_IDLE_STATE_INACTIVE) || \\\n+ ((type) == PWM_IDLE_STATE_ACTIVE))\n+\n+/** @defgroup PWM_BREAK_STATE_TYPE\n+ * @{\n+ */\n+#define IS_PWM_BREAK_STATE_TYPE(type) (((type) == PWM_BREAK_STATE_INACTIVE) || \\\n+ ((type) == PWM_BREAK_STATE_ACTIVE))\n+\n+/** @defgroup PWM_EXT_BREAK_POLARITY_TYPE\n+ * @{\n+ */\n+#define IS_PWM_EXT_BREAK_POLARITY_TYPE(type) (((type) == PWM_BREAK_Polarity_LOW) || \\\n+ ((type) == PWM_BREAK_Polarity_HIGH))\n+\n+/** @defgroup PWM_TRIGADC_SOURCE_TYPE\n+ * @{\n+ */\n+#define IS_PWM_TRIGADC_SOURCE_TYPE(type) (((type) == PWM_TRIGADC_SOURCE_0L) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_0H) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_1L) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_1H) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_2L) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_2H) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_3L) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_3H) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_PRDE) || \\\n+ ((type) == PWM_TRIGADC_SOURCE_NONE))\n+\n+/*@} end of group PWM_Public_Constants */\n+\n+/** @defgroup PWM_Public_Macros\n+ * @{\n+ */\n+#define IS_PWMx_ID(CH) ((CH) < PWMx_ID_MAX)\n+#define IS_PWM_CHx(CH) ((CH) < PWM_CHx_MAX)\n+\n+/*@} end of group PWM_Public_Macros */\n+\n+/** @defgroup PWM_Public_Functions\n+ * @{\n+ */\n+\n+/**\n+ * @brief PWM Functions\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+void PWM_IRQHandler(void);\n+#endif\n+BL_Err_Type PWMx_Init(PWMx_ID_Type pwmx, PWMx_CFG_Type *cfg);\n+void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div);\n+void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period);\n+void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period);\n+void PWMx_Enable(PWMx_ID_Type id);\n+void PWMx_Disable(PWMx_ID_Type id);\n+void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg);\n+void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH);\n+void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL);\n+void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH);\n+void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH);\n+void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN);\n+void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod);\n+void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod);\n+void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN);\n+void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol);\n+void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol);\n+void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN);\n+void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl);\n+void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl);\n+void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN);\n+void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk);\n+void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk);\n+void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg);\n+void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg);\n+void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg);\n+void PWM_SW_Break_Enable(PWMx_ID_Type id);\n+void PWM_SW_Break_Disable(PWMx_ID_Type id);\n+void PWM_EXT_Break_Enable(PWMx_ID_Type id);\n+void PWM_EXT_Break_Disable(PWMx_ID_Type id);\n+void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol);\n+void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src);\n+void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask);\n+void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType);\n+BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType);\n+#ifndef BFLB_USE_HAL_DRIVER\n+void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun);\n+void PWM_IRQHandler(void);\n+#endif\n+/*@} end of group PWM_Public_Functions */\n+\n+/*@} end of group PWM */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_PWM_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..453ff3e34553f5117699f62e5ea0a52f3d4ca5f3\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h\n@@ -0,0 +1,56 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_romapi_patch.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_ROMAPI_PATCH_H__\n+#define __BL808_ROMAPI_PATCH_H__\n+\n+#include \"bl808_uart.h\"\n+#include \"bl808_pds.h\"\n+#include \"bl808_sflash.h\"\n+#include \"bl808_xip_sflash.h\"\n+#include \"bl808_ef_ctrl.h\"\n+#include \"bl808_clock.h\"\n+#include \"bl808_hbn.h\"\n+#include \"softcrc.h\"\n+#include \"bl808_sf_ctrl.h\"\n+\n+\n+BL_Err_Type GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk);\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,\n+ SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..52ed7d5057cf6f1d7a0f2062af6c5e3c2fac80dc\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h\n@@ -0,0 +1,2134 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_romdriver_e907.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_ROMDRIVER_E907_H__\n+#define __BL808_ROMDRIVER_E907_H__\n+\n+#include \"bl808_glb.h\"\n+#include \"bl808_pds.h\"\n+#include \"bl808_hbn.h\"\n+#include \"bl808_clock.h\"\n+#include \"bl808_uart.h\"\n+#include \"bl808_sflash.h\"\n+#include \"bl808_xip_sflash.h\"\n+#include \"bl808_ef_ctrl.h\"\n+\n+/** @addtogroup bl808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup ROMDRIVER\n+ * @{\n+ */\n+\n+/** @defgroup ROMDRIVER_Public_Types\n+ * @{\n+ */\n+\n+#define ROMAPI_INDEX_SECT_SIZE (0x800)\n+#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1)\n+\n+typedef enum {\n+ ROM_API_INDEX_VERSION = 0,\n+ ROM_API_INDEX_RSVD_0 ,\n+ ROM_API_INDEX_RSVD_1,\n+ ROM_API_INDEX_RSVD_LAST,\n+\n+\n+ ROM_API_INDEX_AON_LowPower_Enter_PDS0,\n+ ROM_API_INDEX_AON_LowPower_Exit_PDS0,\n+ ROM_API_INDEX_AON_Power_Off_BG,\n+ ROM_API_INDEX_AON_Power_Off_LDO15_RF,\n+ ROM_API_INDEX_AON_Power_Off_MBG,\n+ ROM_API_INDEX_AON_Power_Off_SFReg,\n+ ROM_API_INDEX_AON_Power_Off_XTAL,\n+ ROM_API_INDEX_AON_Power_On_BG,\n+ ROM_API_INDEX_AON_Power_On_LDO15_RF,\n+ ROM_API_INDEX_AON_Power_On_MBG,\n+ ROM_API_INDEX_AON_Power_On_SFReg,\n+ ROM_API_INDEX_AON_Power_On_XTAL,\n+ ROM_API_INDEX_AON_Set_DCDC11_Top_Vout,\n+ ROM_API_INDEX_AON_Set_Xtal_CapCode,\n+ ROM_API_INDEX_AON_Trim_DCDC11_Vout,\n+ ROM_API_INDEX_AON_Trim_DCDC18_Vout,\n+ ROM_API_INDEX_AON_Trim_USB20_RCAL,\n+ ROM_API_INDEX_AON_Get_Xtal_CapCode,\n+\n+ ROM_API_INDEX_ASM_Delay_Us,\n+\n+ ROM_API_INDEX_arch_delay_ms,\n+ ROM_API_INDEX_arch_delay_us,\n+\n+ ROM_API_INDEX_EF_Ctrl_Crc_Result,\n+ ROM_API_INDEX_EF_Ctrl_Get_Customer_PIDVID,\n+ ROM_API_INDEX_EF_Ctrl_Read_Chip_ID,\n+ ROM_API_INDEX_EF_Ctrl_Read_MAC_Address,\n+ ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Raw,\n+ ROM_API_INDEX_EF_Ctrl_AutoLoad_Done,\n+ ROM_API_INDEX_EF_Ctrl_Busy,\n+ ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy,\n+ ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,\n+ ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero,\n+ ROM_API_INDEX_EF_Ctrl_Clear,\n+ ROM_API_INDEX_EF_Ctrl_Crc_Enable,\n+ ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden,\n+ ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,\n+ ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1,\n+ ROM_API_INDEX_EF_Ctrl_Program_Direct,\n+ ROM_API_INDEX_EF_Ctrl_Program_Direct_R0,\n+ ROM_API_INDEX_EF_Ctrl_Program_Direct_R1,\n+ ROM_API_INDEX_EF_Ctrl_Program_Efuse_0,\n+ ROM_API_INDEX_EF_Ctrl_Program_Efuse_1,\n+ ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_AES_Key,\n+ ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd,\n+ ROM_API_INDEX_EF_Ctrl_Read_Device_Info,\n+ ROM_API_INDEX_EF_Ctrl_Read_Direct,\n+ ROM_API_INDEX_EF_Ctrl_Read_Direct_R0,\n+ ROM_API_INDEX_EF_Ctrl_Read_Direct_R1,\n+ ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot,\n+ ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg,\n+ ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage,\n+ ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim,\n+ ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M,\n+ ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key,\n+ ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd,\n+ ROM_API_INDEX_EF_Ctrl_Set_sf_key_re_sel,\n+ ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,\n+ ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1,\n+ ROM_API_INDEX_EF_Ctrl_Write_AES_Key,\n+ ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd,\n+ ROM_API_INDEX_EF_Ctrl_Write_MAC_Address,\n+ ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot,\n+ ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg,\n+ ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage,\n+ ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key,\n+ ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd,\n+ ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address,\n+ ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage,\n+\n+ ROM_API_INDEX_GLB_AHB_DSP_Software_Reset,\n+ ROM_API_INDEX_GLB_AHB_MCU_Software_Reset,\n+ ROM_API_INDEX_GLB_BMX_TO_Init,\n+ ROM_API_INDEX_GLB_Clr_BMX_TO_Status,\n+ ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate,\n+ ROM_API_INDEX_GLB_Config_AUDIO_PLL,\n+ ROM_API_INDEX_GLB_Config_CPU_PLL,\n+ ROM_API_INDEX_GLB_Config_MIPI_PLL,\n+ ROM_API_INDEX_GLB_Config_MIPI_PLL_Div,\n+ ROM_API_INDEX_GLB_Config_UHS_PLL,\n+ ROM_API_INDEX_GLB_Config_WIFI_PLL,\n+ ROM_API_INDEX_GLB_DSP0_Clock_Disable,\n+ ROM_API_INDEX_GLB_DSP0_Clock_Enable,\n+ ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus,\n+ ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset,\n+ ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset,\n+ ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset,\n+ ROM_API_INDEX_GLB_DSP_Peripheral_Reset,\n+ ROM_API_INDEX_GLB_DSP_SW_System_Reset,\n+ ROM_API_INDEX_GLB_DSP_Set_LP_IntEn,\n+ ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask,\n+ ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type,\n+ ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div,\n+ ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div,\n+ ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div,\n+ ROM_API_INDEX_GLB_Halt_CPU,\n+ ROM_API_INDEX_GLB_IR_LED_Driver_Disable,\n+ ROM_API_INDEX_GLB_IR_LED_Driver_Enable,\n+ ROM_API_INDEX_GLB_IR_RX_GPIO_Sel,\n+ ROM_API_INDEX_GLB_Invert_ETH_REF_O_CLK,\n+ ROM_API_INDEX_GLB_Invert_ETH_RX_CLK,\n+ ROM_API_INDEX_GLB_Invert_ETH_TX_CLK,\n+ ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus,\n+ ROM_API_INDEX_GLB_MCU_SW_System_Reset,\n+ ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask,\n+ ROM_API_INDEX_GLB_Output_EMAC_CLK,\n+ ROM_API_INDEX_GLB_PER_Clock_Gate,\n+ ROM_API_INDEX_GLB_PER_Clock_UnGate,\n+ ROM_API_INDEX_GLB_PLL_CGEN_Clock_Gate,\n+ ROM_API_INDEX_GLB_PLL_CGEN_Clock_UnGate,\n+ ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable,\n+ ROM_API_INDEX_GLB_Power_Off_MU_PLL,\n+ ROM_API_INDEX_GLB_Power_Off_WAC_PLL,\n+ ROM_API_INDEX_GLB_Power_On_MU_PLL,\n+ ROM_API_INDEX_GLB_Power_On_WAC_PLL,\n+ ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK,\n+ ROM_API_INDEX_GLB_Release_CPU,\n+ ROM_API_INDEX_GLB_SW_CPU_Reset,\n+ ROM_API_INDEX_GLB_SW_POR_Reset,\n+ ROM_API_INDEX_GLB_SW_System_Reset,\n+ ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock,\n+ ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock,\n+ ROM_API_INDEX_GLB_Set_ADC_CLK,\n+ ROM_API_INDEX_GLB_Set_Audio_ADC_CLK,\n+ ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK,\n+ ROM_API_INDEX_GLB_Set_Audio_DAC_CLK,\n+ ROM_API_INDEX_GLB_Set_Audio_PDM_CLK,\n+ ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type,\n+ ROM_API_INDEX_GLB_Set_CAM_CLK,\n+ ROM_API_INDEX_GLB_Set_CPU_Reset_Address,\n+ ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel,\n+ ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel,\n+ ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel,\n+ ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel,\n+ ROM_API_INDEX_GLB_Set_DIG_32K_CLK,\n+ ROM_API_INDEX_GLB_Set_DIG_512K_CLK,\n+ ROM_API_INDEX_GLB_Set_DIG_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_DMA_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_CNN_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_DP_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_H264_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size,\n+ ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_PBCLK,\n+ ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div,\n+ ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel,\n+ ROM_API_INDEX_GLB_Set_DSP_SPI_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_System_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div,\n+ ROM_API_INDEX_GLB_Set_DSP_UART0_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_UART1_CLK,\n+ ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel,\n+ ROM_API_INDEX_GLB_Set_Display_CLK,\n+ ROM_API_INDEX_GLB_Set_EMAC_CLK,\n+ ROM_API_INDEX_GLB_Set_EMI_CLK,\n+ ROM_API_INDEX_GLB_Set_EM_Sel,\n+ ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_Flash_IO_PARM,\n+ ROM_API_INDEX_GLB_Set_Flash_Id_Value,\n+ ROM_API_INDEX_GLB_Set_I2C_CLK,\n+ ROM_API_INDEX_GLB_Set_I2S_CLK,\n+ ROM_API_INDEX_GLB_Set_IR_CLK,\n+ ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK,\n+ ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel,\n+ ROM_API_INDEX_GLB_Set_MCU_Muxpll_80M_Sel,\n+ ROM_API_INDEX_GLB_Set_MCU_SPI_0_ACT_MOD_Sel,\n+ ROM_API_INDEX_GLB_Set_MCU_System_CLK,\n+ ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div,\n+ ROM_API_INDEX_GLB_Set_PADC_CLK,\n+ ROM_API_INDEX_GLB_Set_PDM_IO_Sel,\n+ ROM_API_INDEX_GLB_Set_PKA_CLK_Sel,\n+ ROM_API_INDEX_GLB_Set_PSram_CLK,\n+ ROM_API_INDEX_GLB_Set_PWM1_IO_Sel,\n+ ROM_API_INDEX_GLB_Set_PWM2_IO_Sel,\n+ ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN,\n+ ROM_API_INDEX_GLB_Set_SDH_CLK,\n+ ROM_API_INDEX_GLB_Set_SF_CLK,\n+ ROM_API_INDEX_GLB_Set_SPI_CLK,\n+ ROM_API_INDEX_GLB_Set_SRAM_PARM,\n+ ROM_API_INDEX_GLB_Set_SRAM_RET,\n+ ROM_API_INDEX_GLB_Set_SRAM_SLP,\n+ ROM_API_INDEX_GLB_Set_UART2_IO_Sel,\n+ ROM_API_INDEX_GLB_Set_UART_CLK,\n+ ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL,\n+ ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO,\n+ ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO,\n+ ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout,\n+ ROM_API_INDEX_GLB_Trim_LDO18IO_Vout,\n+ ROM_API_INDEX_GLB_UART_Fun_Sel,\n+ ROM_API_INDEX_GLB_UART_Sig_Swap_Set,\n+ ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus,\n+ ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus,\n+ ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus,\n+ ROM_API_INDEX_GLB_Get_Core_Type,\n+ ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel,\n+ ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel,\n+ ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel,\n+ ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel,\n+ ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel,\n+ ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel,\n+ ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel,\n+ ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel,\n+ ROM_API_INDEX_GLB_Get_Flash_Id_Value,\n+ ROM_API_INDEX_GLB_Get_SRAM_PARM,\n+ ROM_API_INDEX_GLB_Get_SRAM_RET,\n+ ROM_API_INDEX_GLB_Get_SRAM_SLP,\n+ ROM_API_INDEX_GLB_Get_BMX_TO_Status,\n+ ROM_API_INDEX_GLB_Clr_GPIO_IntStatus,\n+ ROM_API_INDEX_GLB_Embedded_Flash_Pad_Enable,\n+ ROM_API_INDEX_GLB_GPIO_Clr,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_Clear,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_Init,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_IntClear,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_IntMask,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_Push,\n+ ROM_API_INDEX_GLB_GPIO_Func_Init,\n+ ROM_API_INDEX_GLB_GPIO_Init,\n+ ROM_API_INDEX_GLB_GPIO_Input_Disable,\n+ ROM_API_INDEX_GLB_GPIO_Input_Enable,\n+ ROM_API_INDEX_GLB_GPIO_IntMask,\n+ ROM_API_INDEX_GLB_GPIO_Int_Init,\n+ ROM_API_INDEX_GLB_GPIO_Output_Disable,\n+ ROM_API_INDEX_GLB_GPIO_Output_Enable,\n+ ROM_API_INDEX_GLB_GPIO_Set,\n+ ROM_API_INDEX_GLB_GPIO_Set_HZ,\n+ ROM_API_INDEX_GLB_GPIO_Write,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_Disable,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_Enable,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_GetIntStatus,\n+ ROM_API_INDEX_GLB_Get_GPIO_IntStatus,\n+ ROM_API_INDEX_GLB_GPIO_Fifo_GetCount,\n+ ROM_API_INDEX_GLB_GPIO_Read,\n+ ROM_API_INDEX_GLB_GPIO_Get_Fun,\n+\n+ ROM_API_INDEX_HBN_32K_Sel,\n+ ROM_API_INDEX_HBN_Aon_Pad_Cfg,\n+ ROM_API_INDEX_HBN_Aon_Pad_Ctrl,\n+ ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg,\n+ ROM_API_INDEX_HBN_Clear_IRQ,\n+ ROM_API_INDEX_HBN_Clear_RTC_Counter,\n+ ROM_API_INDEX_HBN_Clear_RTC_INT,\n+ ROM_API_INDEX_HBN_Disable_AComp0_IRQ,\n+ ROM_API_INDEX_HBN_Disable_AComp1_IRQ,\n+ ROM_API_INDEX_HBN_Disable_BOD_IRQ,\n+ ROM_API_INDEX_HBN_Enable_AComp0_IRQ,\n+ ROM_API_INDEX_HBN_Enable_AComp1_IRQ,\n+ ROM_API_INDEX_HBN_Enable_BOD_IRQ,\n+ ROM_API_INDEX_HBN_Enable_RTC_Counter,\n+ ROM_API_INDEX_HBN_GPIO_INT_Disable,\n+ ROM_API_INDEX_HBN_GPIO_INT_Enable,\n+ ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg,\n+ ROM_API_INDEX_HBN_Get_RTC_Timer_Val,\n+ ROM_API_INDEX_HBN_Get_Xtal_Type,\n+ ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg,\n+ ROM_API_INDEX_HBN_PD_RC32K_All_State,\n+ ROM_API_INDEX_HBN_PD_RC32K_In_Poff,\n+ ROM_API_INDEX_HBN_PIR_Disable,\n+ ROM_API_INDEX_HBN_PIR_Enable,\n+ ROM_API_INDEX_HBN_PIR_HPF_Sel,\n+ ROM_API_INDEX_HBN_PIR_INT_Config,\n+ ROM_API_INDEX_HBN_PIR_LPF_Sel,\n+ ROM_API_INDEX_HBN_Pin_WakeUp_Mask,\n+ ROM_API_INDEX_HBN_Power_Off_RC32K,\n+ ROM_API_INDEX_HBN_Power_Off_Xtal_32K,\n+ ROM_API_INDEX_HBN_Power_On_RC32K,\n+ ROM_API_INDEX_HBN_Power_On_Xtal_32K,\n+ ROM_API_INDEX_HBN_Reset,\n+ ROM_API_INDEX_HBN_Set_BOD_Cfg,\n+ ROM_API_INDEX_HBN_Set_BOD_Config,\n+ ROM_API_INDEX_HBN_Set_Core_Reboot_Config,\n+ ROM_API_INDEX_HBN_Set_HRAM_Ret,\n+ ROM_API_INDEX_HBN_Set_HRAM_slp,\n+ ROM_API_INDEX_HBN_Set_Hand_Off_Config,\n+ ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO,\n+ ROM_API_INDEX_HBN_Set_Ldo11_All_Vout,\n+ ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout,\n+ ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout,\n+ ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout,\n+ ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay,\n+ ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel,\n+ ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel,\n+ ROM_API_INDEX_HBN_Set_MM_Power_Config,\n+ ROM_API_INDEX_HBN_Set_PIR_Interval,\n+ ROM_API_INDEX_HBN_Set_PIR_Threshold,\n+ ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg,\n+ ROM_API_INDEX_HBN_Set_RTC_Timer,\n+ ROM_API_INDEX_HBN_Set_Status_Flag,\n+ ROM_API_INDEX_HBN_Set_UART_CLK_Sel,\n+ ROM_API_INDEX_HBN_Set_Wakeup_Addr,\n+ ROM_API_INDEX_HBN_Set_Xtal_Type,\n+ ROM_API_INDEX_HBN_Trim_RC32K,\n+ ROM_API_INDEX_HBN_Get_BOD_OUT_State,\n+ ROM_API_INDEX_HBN_Get_INT_State,\n+ ROM_API_INDEX_HBN_Get_MCU_Root_CLK_Sel,\n+ ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel,\n+ ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config,\n+ ROM_API_INDEX_HBN_Get_PIR_Interval,\n+ ROM_API_INDEX_HBN_Get_PIR_Threshold,\n+ ROM_API_INDEX_HBN_Get_Status_Flag,\n+ ROM_API_INDEX_HBN_Get_Wakeup_Addr,\n+ ROM_API_INDEX_HBN_Get_Core_Unhalt_Config,\n+ ROM_API_INDEX_HBN_Get_Hand_Off_Config,\n+ ROM_API_INDEX_HBN_Get_MM_Power_Config,\n+ ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode,\n+ ROM_API_INDEX_HBN_Enable,\n+ ROM_API_INDEX_HBN_Mode_Enter,\n+ ROM_API_INDEX_HBN_Power_Down_Flash,\n+\n+ ROM_API_INDEX_L1C_DCache_Clean_All,\n+ ROM_API_INDEX_L1C_DCache_Clean_By_Addr,\n+ ROM_API_INDEX_L1C_DCache_Clean_Invalid_All,\n+ ROM_API_INDEX_L1C_DCache_Clean_Invalid_By_Addr,\n+ ROM_API_INDEX_L1C_DCache_Disable,\n+ ROM_API_INDEX_L1C_DCache_Enable,\n+ ROM_API_INDEX_L1C_DCache_Invalid_All,\n+ ROM_API_INDEX_L1C_DCache_Invalid_By_Addr,\n+ ROM_API_INDEX_L1C_ICache_Disable,\n+ ROM_API_INDEX_L1C_ICache_Enable,\n+ ROM_API_INDEX_L1C_ICache_Invalid_All,\n+ ROM_API_INDEX_L1C_ICache_Invalid_By_Addr,\n+ ROM_API_INDEX_L1C_Set_Cache_Setting_By_ID,\n+ ROM_API_INDEX_L1C_Set_Wrap,\n+ ROM_API_INDEX_L1C_Get_None_Cache_Addr,\n+ ROM_API_INDEX_L1C_Is_DCache_Range,\n+ ROM_API_INDEX_L1C_DCache_Write_Set,\n+\n+ ROM_API_INDEX_PDS_Default_Level_Config,\n+ ROM_API_INDEX_PDS_Enable,\n+ ROM_API_INDEX_PDS_Force_Config,\n+ ROM_API_INDEX_PDS_IntClear,\n+ ROM_API_INDEX_PDS_IntMask,\n+ ROM_API_INDEX_PDS_Power_On_MM_System,\n+ ROM_API_INDEX_PDS_RAM_Config,\n+ ROM_API_INDEX_PDS_Reset_LP_RTC,\n+ ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None,\n+ ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast,\n+ ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr,\n+ ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask,\n+ ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode,\n+ ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie,\n+ ROM_API_INDEX_PDS_Set_LP_Clock_Disable,\n+ ROM_API_INDEX_PDS_Set_LP_Clock_Enable,\n+ ROM_API_INDEX_PDS_Set_LP_RTC_CLK,\n+ ROM_API_INDEX_PDS_Set_LP_Reset_Address,\n+ ROM_API_INDEX_PDS_Set_LP_System_CLK,\n+ ROM_API_INDEX_PDS_Set_LP_System_CLK_Div,\n+ ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable,\n+ ROM_API_INDEX_PDS_Set_MCU0_Clock_Enable,\n+ ROM_API_INDEX_PDS_Set_MCU0_Reset_Address,\n+ ROM_API_INDEX_PDS_Set_USB_Resume,\n+ ROM_API_INDEX_PDS_Set_USB_Suspend,\n+ ROM_API_INDEX_PDS_Trim_RC32M,\n+ ROM_API_INDEX_PDS_Turn_Off_USB,\n+ ROM_API_INDEX_PDS_Turn_On_USB,\n+ ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus,\n+ ROM_API_INDEX_PDS_Get_IntStatus,\n+ ROM_API_INDEX_PDS_Get_MM_System_Power_On_State,\n+\n+ ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,\n+ ROM_API_INDEX_SF_Cfg_Flash_Init,\n+ ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,\n+ ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext,\n+ ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,\n+ ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,\n+ ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init,\n+ ROM_API_INDEX_SF_Cfg_Flash_Identify,\n+ ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext,\n+ ROM_API_INDEX_SF_Ctrl_GetBusyState,\n+ ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,\n+ ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable,\n+ ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,\n+ ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,\n+ ROM_API_INDEX_SF_Ctrl_Get_Wrap_Queue_Value,\n+ ROM_API_INDEX_SF_Ctrl_32bits_Addr_En,\n+ ROM_API_INDEX_SF_Ctrl_AES_Disable,\n+ ROM_API_INDEX_SF_Ctrl_AES_Enable,\n+ ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,\n+ ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_IV,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_Key,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_Mode,\n+ ROM_API_INDEX_SF_Ctrl_AES_Set_Region,\n+ ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV,\n+ ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE,\n+ ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key,\n+ ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE,\n+ ROM_API_INDEX_SF_Ctrl_Bank2_Enable,\n+ ROM_API_INDEX_SF_Ctrl_Cmds_Set,\n+ ROM_API_INDEX_SF_Ctrl_Disable,\n+ ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access,\n+ ROM_API_INDEX_SF_Ctrl_Enable,\n+ ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set,\n+ ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set,\n+ ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset,\n+ ROM_API_INDEX_SF_Ctrl_Remap_Set,\n+ ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram,\n+ ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram,\n+ ROM_API_INDEX_SF_Ctrl_Sbus2_Replace,\n+ ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace,\n+ ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay,\n+ ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank,\n+ ROM_API_INDEX_SF_Ctrl_Select_Pad,\n+ ROM_API_INDEX_SF_Ctrl_SendCmd,\n+ ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,\n+ ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,\n+ ROM_API_INDEX_SF_Ctrl_Set_IO_Delay,\n+ ROM_API_INDEX_SF_Ctrl_Set_Owner,\n+\n+ ROM_API_INDEX_SFlash_Blk32_Erase,\n+ ROM_API_INDEX_SFlash_Blk64_Erase,\n+ ROM_API_INDEX_SFlash_Chip_Erase,\n+ ROM_API_INDEX_SFlash_Erase,\n+ ROM_API_INDEX_SFlash_Erase_Security_Register,\n+ ROM_API_INDEX_SFlash_IDbus_Read_Enable,\n+ ROM_API_INDEX_SFlash_Program,\n+ ROM_API_INDEX_SFlash_Program_Security_Register,\n+ ROM_API_INDEX_SFlash_Qspi_Disable,\n+ ROM_API_INDEX_SFlash_Qspi_Enable,\n+ ROM_API_INDEX_SFlash_RCV_Enable,\n+ ROM_API_INDEX_SFlash_Read,\n+ ROM_API_INDEX_SFlash_Read_Reg,\n+ ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,\n+ ROM_API_INDEX_SFlash_Read_Security_Register,\n+ ROM_API_INDEX_SFlash_Restore_From_Powerdown,\n+ ROM_API_INDEX_SFlash_Sector_Erase,\n+ ROM_API_INDEX_SFlash_Set32BitsAddrMode,\n+ ROM_API_INDEX_SFlash_SetSPIMode,\n+ ROM_API_INDEX_SFlash_Set_IDbus_Cfg,\n+ ROM_API_INDEX_SFlash_Software_Reset,\n+ ROM_API_INDEX_SFlash_Write_Enable,\n+ ROM_API_INDEX_SFlash_Write_Reg,\n+ ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,\n+ ROM_API_INDEX_SFlash_Busy,\n+ ROM_API_INDEX_SFlash_DisableBurstWrap,\n+ ROM_API_INDEX_SFlash_GetDeviceId,\n+ ROM_API_INDEX_SFlash_GetJedecId,\n+ ROM_API_INDEX_SFlash_GetUniqueId,\n+ ROM_API_INDEX_SFlash_IDbus_Read_Disable,\n+ ROM_API_INDEX_SFlash_Init,\n+ ROM_API_INDEX_SFlash_Powerdown,\n+ ROM_API_INDEX_SFlash_Release_Powerdown,\n+ ROM_API_INDEX_SFlash_Reset_Continue_Read,\n+ ROM_API_INDEX_SFlash_SetBurstWrap,\n+ ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,\n+\n+ ROM_API_INDEX_UART_ApplyAbrResult,\n+ ROM_API_INDEX_UART_AutoBaudDetection,\n+ ROM_API_INDEX_UART_ClrRtsValue,\n+ ROM_API_INDEX_UART_ClrTxValue,\n+ ROM_API_INDEX_UART_DeInit,\n+ ROM_API_INDEX_UART_Disable,\n+ ROM_API_INDEX_UART_Enable,\n+ ROM_API_INDEX_UART_FifoConfig,\n+ ROM_API_INDEX_UART_GetBitWidth0X55,\n+ ROM_API_INDEX_UART_Init,\n+ ROM_API_INDEX_UART_IntClear,\n+ ROM_API_INDEX_UART_IntMask,\n+ ROM_API_INDEX_UART_IrConfig,\n+ ROM_API_INDEX_UART_RxFifoClear,\n+ ROM_API_INDEX_UART_SendData,\n+ ROM_API_INDEX_UART_SendDataBlock,\n+ ROM_API_INDEX_UART_SetAllowableError0X55,\n+ ROM_API_INDEX_UART_SetBaudRate,\n+ ROM_API_INDEX_UART_SetDeglitchCount,\n+ ROM_API_INDEX_UART_SetRS485,\n+ ROM_API_INDEX_UART_SetRtsValue,\n+ ROM_API_INDEX_UART_SetRxByteCount,\n+ ROM_API_INDEX_UART_SetRxDataLength,\n+ ROM_API_INDEX_UART_SetRxTimeoutValue,\n+ ROM_API_INDEX_UART_SetTxDataLength,\n+ ROM_API_INDEX_UART_SetTxValue,\n+ ROM_API_INDEX_UART_TxFifoClear,\n+ ROM_API_INDEX_UART_TxFreeRun,\n+ ROM_API_INDEX_UART_GetIntStatus,\n+ ROM_API_INDEX_UART_GetOverflowStatus,\n+ ROM_API_INDEX_UART_GetRxBusBusyStatus,\n+ ROM_API_INDEX_UART_GetTxBusBusyStatus,\n+ ROM_API_INDEX_UART_GetAutoBaudCount,\n+ ROM_API_INDEX_UART_GetRxByteCount,\n+ ROM_API_INDEX_UART_ReceiveData,\n+ ROM_API_INDEX_UART_GetRxFifoCount,\n+ ROM_API_INDEX_UART_GetTxFifoCount,\n+\n+ ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_State_Restore,\n+ ROM_API_INDEX_XIP_SFlash_State_Save,\n+ ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,\n+ ROM_API_INDEX_XIP_SFlash_Opt_Enter,\n+ ROM_API_INDEX_XIP_SFlash_Opt_Exit,\n+\n+ ROM_API_INDEX_FUNC_EMPTY_START,\n+\n+ ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX\n+\n+} ROM_API_INDEX_e;\n+\n+/*@} end of group ROMDRIVER_Public_Types */\n+\n+/** @defgroup ROMDRIVER_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Public_Constants */\n+\n+/** @defgroup ROMDRIVER_Public_Macros\n+ * @{\n+ */\n+\n+\n+#define ROM_APITABLE ((uint32_t *)0x90014800)\n+\n+\n+#define RomDriver_AON_LowPower_Enter_PDS0 \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0])\n+\n+#define RomDriver_AON_LowPower_Exit_PDS0 \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0])\n+\n+#define RomDriver_AON_Power_Off_BG \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG])\n+\n+#define RomDriver_AON_Power_Off_LDO15_RF \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF])\n+\n+#define RomDriver_AON_Power_Off_MBG \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])\n+\n+#define RomDriver_AON_Power_Off_SFReg \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg])\n+\n+#define RomDriver_AON_Power_Off_XTAL \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])\n+\n+#define RomDriver_AON_Power_On_BG \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG])\n+\n+#define RomDriver_AON_Power_On_LDO15_RF \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF])\n+\n+#define RomDriver_AON_Power_On_MBG \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])\n+\n+#define RomDriver_AON_Power_On_SFReg \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg])\n+\n+#define RomDriver_AON_Power_On_XTAL \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])\n+\n+#define RomDriver_AON_Set_DCDC11_Top_Vout \\\n+ ((BL_Err_Type (*) (AON_DCDC_LEVEL_Type dcdcLevel))ROM_APITABLE[ROM_API_INDEX_AON_Set_DCDC11_Top_Vout])\n+\n+#define RomDriver_AON_Set_Xtal_CapCode \\\n+ ((BL_Err_Type (*) (uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])\n+\n+#define RomDriver_AON_Trim_DCDC11_Vout \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DCDC11_Vout])\n+\n+#define RomDriver_AON_Trim_DCDC18_Vout \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DCDC18_Vout])\n+\n+#define RomDriver_AON_Trim_USB20_RCAL \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_USB20_RCAL])\n+\n+#define RomDriver_AON_Get_Xtal_CapCode \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode])\n+\n+#define RomDriver_ASM_Delay_Us \\\n+ ((void (*) (uint32_t core, uint32_t cnt, uint32_t loopT))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])\n+\n+#define RomDriver_arch_delay_ms \\\n+ ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_arch_delay_ms])\n+\n+#define RomDriver_arch_delay_us \\\n+ ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_arch_delay_us])\n+\n+#define RomDriver_EF_Ctrl_Crc_Result \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Result])\n+\n+#define RomDriver_EF_Ctrl_Get_Customer_PIDVID \\\n+ ((BL_Err_Type (*) (uint16_t pid[1], uint16_t vid[1]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Customer_PIDVID])\n+\n+#define RomDriver_EF_Ctrl_Read_Chip_ID \\\n+ ((BL_Err_Type (*) (uint8_t chipID[8]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Chip_ID])\n+\n+#define RomDriver_EF_Ctrl_Read_MAC_Address \\\n+ ((BL_Err_Type (*) (uint8_t mac[6]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_MAC_Address])\n+\n+#define RomDriver_EF_Ctrl_Read_MAC_Address_Raw \\\n+ ((BL_Err_Type (*) (uint8_t mac[7]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Raw])\n+\n+#define RomDriver_EF_Ctrl_AutoLoad_Done \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done])\n+\n+#define RomDriver_EF_Ctrl_Busy \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])\n+\n+#define RomDriver_EF_Ctrl_Crc_Is_Busy \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy])\n+\n+#define RomDriver_EF_Ctrl_Get_Trim_Parity \\\n+ ((uint8_t (*) (uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])\n+\n+#define RomDriver_EF_Ctrl_Is_All_Bits_Zero \\\n+ ((uint8_t (*) (uint32_t val, uint8_t start, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero])\n+\n+#define RomDriver_EF_Ctrl_Clear \\\n+ ((void (*) (uint8_t region, uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])\n+\n+#define RomDriver_EF_Ctrl_Crc_Enable \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Enable])\n+\n+#define RomDriver_EF_Ctrl_Crc_Set_Golden \\\n+ ((void (*) (uint32_t goldenValue))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden])\n+\n+#define RomDriver_EF_Ctrl_Load_Efuse_R0 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])\n+\n+#define RomDriver_EF_Ctrl_Load_Efuse_R1 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1])\n+\n+#define RomDriver_EF_Ctrl_Program_Direct \\\n+ ((void (*) (uint32_t region, uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct])\n+\n+#define RomDriver_EF_Ctrl_Program_Direct_R0 \\\n+ ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct_R0])\n+\n+#define RomDriver_EF_Ctrl_Program_Direct_R1 \\\n+ ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct_R1])\n+\n+#define RomDriver_EF_Ctrl_Program_Efuse_0 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0])\n+\n+#define RomDriver_EF_Ctrl_Program_Efuse_1 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_1])\n+\n+#define RomDriver_EF_Ctrl_Read_ADC_Gain_Trim \\\n+ ((void (*) (Efuse_ADC_Gain_Coeff_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_AES_Key \\\n+ ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_AES_Key])\n+\n+#define RomDriver_EF_Ctrl_Read_DCDC11_Trim \\\n+ ((void (*) (Efuse_Ana_DCDC11_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_DCDC18_Trim \\\n+ ((void (*) (Efuse_Ana_DCDC18_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_Dbg_Pwd \\\n+ ((void (*) (uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd])\n+\n+#define RomDriver_EF_Ctrl_Read_Device_Info \\\n+ ((void (*) (Efuse_Device_Info_Type *deviceInfo))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Device_Info])\n+\n+#define RomDriver_EF_Ctrl_Read_Direct \\\n+ ((void (*) (uint32_t region, uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct])\n+\n+#define RomDriver_EF_Ctrl_Read_Direct_R0 \\\n+ ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct_R0])\n+\n+#define RomDriver_EF_Ctrl_Read_Direct_R1 \\\n+ ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct_R1])\n+\n+#define RomDriver_EF_Ctrl_Read_LDO18FLASH_Trim \\\n+ ((void (*) (Efuse_Ana_LDO18FLASH_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_LDO18IO_Vout_Trim \\\n+ ((void (*) (Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_RC32K_Trim \\\n+ ((void (*) (Efuse_Ana_RC32K_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_RC32M_Trim \\\n+ ((void (*) (Efuse_Ana_RC32M_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_Secure_Boot \\\n+ ((void (*) (EF_Ctrl_SF_AES_Type aes[2]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot])\n+\n+#define RomDriver_EF_Ctrl_Read_Secure_Cfg \\\n+ ((void (*) (EF_Ctrl_Sec_Param_Type *cfg))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg])\n+\n+#define RomDriver_EF_Ctrl_Read_Sw_Usage \\\n+ ((void (*) (uint32_t index, uint32_t *usage))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage])\n+\n+#define RomDriver_EF_Ctrl_Read_TSEN_Trim \\\n+ ((void (*) (Efuse_TSEN_Refcode_Corner_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_USB20RCAL_Trim \\\n+ ((void (*) (Efuse_Ana_USB20RCAL_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim])\n+\n+#define RomDriver_EF_Ctrl_Read_Xtal_Trim_RC32M \\\n+ ((void (*) (uint8_t *forceNoTrim, uint8_t *noXtal))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M])\n+\n+#define RomDriver_EF_Ctrl_Readlock_AES_Key \\\n+ ((void (*) (uint8_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key])\n+\n+#define RomDriver_EF_Ctrl_Readlock_Dbg_Pwd \\\n+ ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd])\n+\n+#define RomDriver_EF_Ctrl_Set_sf_key_re_sel \\\n+ ((void (*) (uint8_t ef_sf_key_re_sel))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Set_sf_key_re_sel])\n+\n+#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])\n+\n+#define RomDriver_EF_Ctrl_Sw_AHB_Clk_1 \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1])\n+\n+#define RomDriver_EF_Ctrl_Write_AES_Key \\\n+ ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_AES_Key])\n+\n+#define RomDriver_EF_Ctrl_Write_Dbg_Pwd \\\n+ ((void (*) (uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd])\n+\n+#define RomDriver_EF_Ctrl_Write_MAC_Address \\\n+ ((void (*) (uint8_t mac[6], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_MAC_Address])\n+\n+#define RomDriver_EF_Ctrl_Write_Secure_Boot \\\n+ ((void (*) (EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot])\n+\n+#define RomDriver_EF_Ctrl_Write_Secure_Cfg \\\n+ ((void (*) (EF_Ctrl_Sec_Param_Type *cfg, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg])\n+\n+#define RomDriver_EF_Ctrl_Write_Sw_Usage \\\n+ ((void (*) (uint32_t index, uint32_t usage, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage])\n+\n+#define RomDriver_EF_Ctrl_Writelock_AES_Key \\\n+ ((void (*) (uint8_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key])\n+\n+#define RomDriver_EF_Ctrl_Writelock_Dbg_Pwd \\\n+ ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd])\n+\n+#define RomDriver_EF_Ctrl_Writelock_MAC_Address \\\n+ ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address])\n+\n+#define RomDriver_EF_Ctrl_Writelock_Sw_Usage \\\n+ ((void (*) (uint32_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage])\n+\n+#define RomDriver_GLB_AHB_DSP_Software_Reset \\\n+ ((BL_Err_Type (*) (GLB_AHB_DSP_SW_Type swrst))ROM_APITABLE[ROM_API_INDEX_GLB_AHB_DSP_Software_Reset])\n+\n+#define RomDriver_GLB_AHB_MCU_Software_Reset \\\n+ ((BL_Err_Type (*) (GLB_AHB_MCU_SW_Type swrst))ROM_APITABLE[ROM_API_INDEX_GLB_AHB_MCU_Software_Reset])\n+\n+#define RomDriver_GLB_BMX_TO_Init \\\n+ ((BL_Err_Type (*) (BMX_TO_Cfg_Type *BmxCfg))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_TO_Init])\n+\n+#define RomDriver_GLB_Clr_BMX_TO_Status \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_BMX_TO_Status])\n+\n+#define RomDriver_GLB_Clr_EMI_Reset_Gate \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate])\n+\n+#define RomDriver_GLB_Config_AUDIO_PLL \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_AUDIO_PLL])\n+\n+#define RomDriver_GLB_Config_CPU_PLL \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_CPU_PLL])\n+\n+#define RomDriver_GLB_Config_MIPI_PLL \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_MIPI_PLL])\n+\n+#define RomDriver_GLB_Config_MIPI_PLL_Div \\\n+ ((BL_Err_Type (*) (uint8_t divEn, uint8_t divRatio))ROM_APITABLE[ROM_API_INDEX_GLB_Config_MIPI_PLL_Div])\n+\n+#define RomDriver_GLB_Config_UHS_PLL \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_UHS_PLL])\n+\n+#define RomDriver_GLB_Config_WIFI_PLL \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_WIFI_PLL])\n+\n+#define RomDriver_GLB_DSP0_Clock_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_DSP0_Clock_Disable])\n+\n+#define RomDriver_GLB_DSP0_Clock_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_DSP0_Clock_Enable])\n+\n+#define RomDriver_GLB_DSP_Clr_MCU_IntStatus \\\n+ ((BL_Err_Type (*) (GLB_MCU_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus])\n+\n+#define RomDriver_GLB_DSP_Codec_Sub_Reset \\\n+ ((BL_Err_Type (*) (GLB_DSP_CODEC_SUB_Type codecPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset])\n+\n+#define RomDriver_GLB_DSP_DSP2_Sub_Reset \\\n+ ((BL_Err_Type (*) (GLB_DSP_DSP2_SUB_Type dsp2Part))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset])\n+\n+#define RomDriver_GLB_DSP_Image_Sensor_Reset \\\n+ ((BL_Err_Type (*) (GLB_DSP_IMAGE_SENSOR_Type imageSensorPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset])\n+\n+#define RomDriver_GLB_DSP_Peripheral_Reset \\\n+ ((BL_Err_Type (*) (GLB_DSP_PERIPHERAL_Type periPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Peripheral_Reset])\n+\n+#define RomDriver_GLB_DSP_SW_System_Reset \\\n+ ((BL_Err_Type (*) (GLB_DSP_SW_SYSTEM_Type sysPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_SW_System_Reset])\n+\n+#define RomDriver_GLB_DSP_Set_LP_IntEn \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_LP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Set_LP_IntEn])\n+\n+#define RomDriver_GLB_DSP_Set_MCU_IntMask \\\n+ ((BL_Err_Type (*) (GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask])\n+\n+#define RomDriver_GLB_Get_Auto_Calc_Xtal_Type \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type *calcXtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type])\n+\n+#define RomDriver_GLB_Get_DSP_PBCLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t *dspPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div])\n+\n+#define RomDriver_GLB_Get_DSP_System_CLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t *dspClkDiv, uint8_t *dspBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div])\n+\n+#define RomDriver_GLB_Get_MCU_System_CLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div])\n+\n+#define RomDriver_GLB_Halt_CPU \\\n+ ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID))ROM_APITABLE[ROM_API_INDEX_GLB_Halt_CPU])\n+\n+#define RomDriver_GLB_IR_LED_Driver_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Disable])\n+\n+#define RomDriver_GLB_IR_LED_Driver_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Enable])\n+\n+#define RomDriver_GLB_IR_RX_GPIO_Sel \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpio))ROM_APITABLE[ROM_API_INDEX_GLB_IR_RX_GPIO_Sel])\n+\n+#define RomDriver_GLB_Invert_ETH_REF_O_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Invert_ETH_REF_O_CLK])\n+\n+#define RomDriver_GLB_Invert_ETH_RX_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Invert_ETH_RX_CLK])\n+\n+#define RomDriver_GLB_Invert_ETH_TX_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Invert_ETH_TX_CLK])\n+\n+#define RomDriver_GLB_MCU_Clr_DSP_IntStatus \\\n+ ((BL_Err_Type (*) (GLB_DSP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus])\n+\n+#define RomDriver_GLB_MCU_SW_System_Reset \\\n+ ((BL_Err_Type (*) (GLB_MCU_SW_SYSTEM_Type sysPart))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_SW_System_Reset])\n+\n+#define RomDriver_GLB_MCU_Set_DSP_IntMask \\\n+ ((BL_Err_Type (*) (GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask])\n+\n+#define RomDriver_GLB_Output_EMAC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t gpio))ROM_APITABLE[ROM_API_INDEX_GLB_Output_EMAC_CLK])\n+\n+#define RomDriver_GLB_PER_Clock_Gate \\\n+ ((BL_Err_Type (*) (uint64_t ips))ROM_APITABLE[ROM_API_INDEX_GLB_PER_Clock_Gate])\n+\n+#define RomDriver_GLB_PER_Clock_UnGate \\\n+ ((BL_Err_Type (*) (uint64_t ips))ROM_APITABLE[ROM_API_INDEX_GLB_PER_Clock_UnGate])\n+\n+#define RomDriver_GLB_PLL_CGEN_Clock_Gate \\\n+ ((BL_Err_Type (*) (GLB_PLL_CGEN_Type clk))ROM_APITABLE[ROM_API_INDEX_GLB_PLL_CGEN_Clock_Gate])\n+\n+#define RomDriver_GLB_PLL_CGEN_Clock_UnGate \\\n+ ((BL_Err_Type (*) (GLB_PLL_CGEN_Type clk))ROM_APITABLE[ROM_API_INDEX_GLB_PLL_CGEN_Clock_UnGate])\n+\n+#define RomDriver_GLB_Platform_Wakeup_PDS_Enable \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable])\n+\n+#define RomDriver_GLB_Power_Off_MU_PLL \\\n+ ((BL_Err_Type (*) (GLB_MU_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_MU_PLL])\n+\n+#define RomDriver_GLB_Power_Off_WAC_PLL \\\n+ ((BL_Err_Type (*) (GLB_WAC_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_WAC_PLL])\n+\n+#define RomDriver_GLB_Power_On_MU_PLL \\\n+ ((BL_Err_Type (*) (GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_MU_PLL])\n+\n+#define RomDriver_GLB_Power_On_WAC_PLL \\\n+ ((BL_Err_Type (*) (GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_WAC_PLL])\n+\n+#define RomDriver_GLB_Power_On_XTAL_And_PLL_CLK \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, GLB_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK])\n+\n+#define RomDriver_GLB_Release_CPU \\\n+ ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID))ROM_APITABLE[ROM_API_INDEX_GLB_Release_CPU])\n+\n+#define RomDriver_GLB_SW_CPU_Reset \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])\n+\n+#define RomDriver_GLB_SW_POR_Reset \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])\n+\n+#define RomDriver_GLB_SW_System_Reset \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])\n+\n+#define RomDriver_GLB_Sel_DSP_TMR_GPIO_Clock \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock])\n+\n+#define RomDriver_GLB_Sel_MCU_TMR_GPIO_Clock \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock])\n+\n+#define RomDriver_GLB_Set_ADC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_ADC_CLK])\n+\n+#define RomDriver_GLB_Set_Audio_ADC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_ADC_CLK])\n+\n+#define RomDriver_GLB_Set_Audio_AUTO_CLK \\\n+ ((BL_Err_Type (*) (uint8_t divEn))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK])\n+\n+#define RomDriver_GLB_Set_Audio_DAC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_DAC_CLK])\n+\n+#define RomDriver_GLB_Set_Audio_PDM_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_PDM_CLK])\n+\n+#define RomDriver_GLB_Set_Auto_Calc_Xtal_Type \\\n+ ((BL_Err_Type (*) (GLB_XTAL_Type calcXtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type])\n+\n+#define RomDriver_GLB_Set_CAM_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_CAM_CLK])\n+\n+#define RomDriver_GLB_Set_CPU_Reset_Address \\\n+ ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID, uint32_t addr))ROM_APITABLE[ROM_API_INDEX_GLB_Set_CPU_Reset_Address])\n+\n+#define RomDriver_GLB_Set_CSI_DSI_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_Chip_Clock_Out0_Sel \\\n+ ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_0_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel])\n+\n+#define RomDriver_GLB_Set_Chip_Clock_Out1_Sel \\\n+ ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_1_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel])\n+\n+#define RomDriver_GLB_Set_Chip_Clock_Out2_Sel \\\n+ ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_2_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel])\n+\n+#define RomDriver_GLB_Set_Chip_Clock_Out3_Sel \\\n+ ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_3_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel])\n+\n+#define RomDriver_GLB_Set_DIG_32K_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint8_t compensationEn, uint16_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DIG_32K_CLK])\n+\n+#define RomDriver_GLB_Set_DIG_512K_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint8_t compensationEn, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DIG_512K_CLK])\n+\n+#define RomDriver_GLB_Set_DIG_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_DIG_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DIG_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_DMA_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DMA_CLK_ID_Type clk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DMA_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_CNN_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_CNN_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_DP_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_DP_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_H264_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_H264_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_I2C0_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_I2C1_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_DSP2_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_L2SRAM_Available_Size \\\n+ ((BL_Err_Type (*) (uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size])\n+\n+#define RomDriver_GLB_Set_DSP_MTimer_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint16_t div, uint8_t rst))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_MUXPLL_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_Muxpll_160M_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_Muxpll_240M_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_Muxpll_320M_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_PBCLK \\\n+ ((BL_Err_Type (*) (GLB_DSP_SYS_PBCLK_Type pbClkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBCLK])\n+\n+#define RomDriver_GLB_Set_DSP_PBCLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t dspPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div])\n+\n+#define RomDriver_GLB_Set_DSP_PBROOT_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_PBROOT_CLK_Type pbrootClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_ROOT_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_SPI_0_ACT_MOD_Sel \\\n+ ((BL_Err_Type (*) (GLB_SPI_PAD_ACT_AS_Type mod))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel])\n+\n+#define RomDriver_GLB_Set_DSP_SPI_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_SPI_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_System_CLK \\\n+ ((BL_Err_Type (*) (GLB_DSP_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_System_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_System_CLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t dspClkDiv, uint8_t dspBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div])\n+\n+#define RomDriver_GLB_Set_DSP_UART0_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_UART0_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_UART1_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_UART1_CLK])\n+\n+#define RomDriver_GLB_Set_DSP_XCLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_DSP_XCLK_Type xclk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel])\n+\n+#define RomDriver_GLB_Set_Display_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Display_CLK])\n+\n+#define RomDriver_GLB_Set_EMAC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EMAC_CLK])\n+\n+#define RomDriver_GLB_Set_EMI_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EMI_CLK])\n+\n+#define RomDriver_GLB_Set_EM_Sel \\\n+ ((BL_Err_Type (*) (GLB_EM_Type emType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EM_Sel])\n+\n+#define RomDriver_GLB_Set_ETH_REF_O_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_ETH_REF_CLK_OUT_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_Flash_IO_PARM \\\n+ ((BL_Err_Type (*) (uint8_t selEmbedded, uint8_t swap))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_IO_PARM])\n+\n+#define RomDriver_GLB_Set_Flash_Id_Value \\\n+ ((BL_Err_Type (*) (uint32_t idValue))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_Id_Value])\n+\n+#define RomDriver_GLB_Set_I2C_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_I2C_CLK])\n+\n+#define RomDriver_GLB_Set_I2S_CLK \\\n+ ((BL_Err_Type (*) (uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef))ROM_APITABLE[ROM_API_INDEX_GLB_Set_I2S_CLK])\n+\n+#define RomDriver_GLB_Set_IR_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_IR_CLK])\n+\n+#define RomDriver_GLB_Set_MCU_MTimer_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint16_t div, uint8_t rst))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK])\n+\n+#define RomDriver_GLB_Set_MCU_Muxpll_160M_Sel \\\n+ ((BL_Err_Type (*) (GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel])\n+\n+#define RomDriver_GLB_Set_MCU_Muxpll_80M_Sel \\\n+ ((BL_Err_Type (*) (GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_Muxpll_80M_Sel])\n+\n+#define RomDriver_GLB_Set_MCU_SPI_0_ACT_MOD_Sel \\\n+ ((BL_Err_Type (*) (GLB_SPI_PAD_ACT_AS_Type mod))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_SPI_0_ACT_MOD_Sel])\n+\n+#define RomDriver_GLB_Set_MCU_System_CLK \\\n+ ((BL_Err_Type (*) (GLB_MCU_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_System_CLK])\n+\n+#define RomDriver_GLB_Set_MCU_System_CLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div])\n+\n+#define RomDriver_GLB_Set_PADC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint16_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PADC_CLK])\n+\n+#define RomDriver_GLB_Set_PDM_IO_Sel \\\n+ ((BL_Err_Type (*) (GLB_PDM_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PDM_IO_Sel])\n+\n+#define RomDriver_GLB_Set_PKA_CLK_Sel \\\n+ ((BL_Err_Type (*) (GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel])\n+\n+#define RomDriver_GLB_Set_PSram_CLK \\\n+ ((BL_Err_Type (*) (uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PSram_CLK])\n+\n+#define RomDriver_GLB_Set_PWM1_IO_Sel \\\n+ ((BL_Err_Type (*) (GLB_PWM1_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PWM1_IO_Sel])\n+\n+#define RomDriver_GLB_Set_PWM2_IO_Sel \\\n+ ((BL_Err_Type (*) (GLB_PWM2_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PWM2_IO_Sel])\n+\n+#define RomDriver_GLB_Set_Peripheral_DMA_CN \\\n+ ((BL_Err_Type (*) (GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN])\n+\n+#define RomDriver_GLB_Set_SDH_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SDH_CLK])\n+\n+#define RomDriver_GLB_Set_SF_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])\n+\n+#define RomDriver_GLB_Set_SPI_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SPI_CLK])\n+\n+#define RomDriver_GLB_Set_SRAM_PARM \\\n+ ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SRAM_PARM])\n+\n+#define RomDriver_GLB_Set_SRAM_RET \\\n+ ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SRAM_RET])\n+\n+#define RomDriver_GLB_Set_SRAM_SLP \\\n+ ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SRAM_SLP])\n+\n+#define RomDriver_GLB_Set_UART2_IO_Sel \\\n+ ((BL_Err_Type (*) (GLB_UART2_IO_SEL_Type ioType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_UART2_IO_Sel])\n+\n+#define RomDriver_GLB_Set_UART_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_UART_CLK])\n+\n+#define RomDriver_GLB_Set_USB_CLK_From_WIFIPLL \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL])\n+\n+#define RomDriver_GLB_Swap_DSP_SPI_0_MOSI_With_MISO \\\n+ ((BL_Err_Type (*) (BL_Fun_Type newState))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO])\n+\n+#define RomDriver_GLB_Swap_MCU_SPI_0_MOSI_With_MISO \\\n+ ((BL_Err_Type (*) (BL_Fun_Type newState))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO])\n+\n+#define RomDriver_GLB_Trim_LDO18FLASH_Vout \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout])\n+\n+#define RomDriver_GLB_Trim_LDO18IO_Vout \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_LDO18IO_Vout])\n+\n+#define RomDriver_GLB_UART_Fun_Sel \\\n+ ((BL_Err_Type (*) (GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun))ROM_APITABLE[ROM_API_INDEX_GLB_UART_Fun_Sel])\n+\n+#define RomDriver_GLB_UART_Sig_Swap_Set \\\n+ ((BL_Err_Type (*) (GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap))ROM_APITABLE[ROM_API_INDEX_GLB_UART_Sig_Swap_Set])\n+\n+#define RomDriver_GLB_DSP_Get_LP_IntStatus \\\n+ ((BL_Sts_Type (*) (GLB_LP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus])\n+\n+#define RomDriver_GLB_DSP_Get_MCU_IntStatus \\\n+ ((BL_Sts_Type (*) (GLB_MCU_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus])\n+\n+#define RomDriver_GLB_MCU_Get_DSP_IntStatus \\\n+ ((BL_Sts_Type (*) (GLB_DSP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus])\n+\n+#define RomDriver_GLB_Get_Core_Type \\\n+ ((GLB_CORE_ID_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Core_Type])\n+\n+#define RomDriver_GLB_Get_DSP_Muxpll_160M_Sel \\\n+ ((GLB_DSP_MUXPLL_160M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel])\n+\n+#define RomDriver_GLB_Get_DSP_Muxpll_240M_Sel \\\n+ ((GLB_DSP_MUXPLL_240M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel])\n+\n+#define RomDriver_GLB_Get_DSP_Muxpll_320M_Sel \\\n+ ((GLB_DSP_MUXPLL_320M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel])\n+\n+#define RomDriver_GLB_Get_DSP_PBROOT_CLK_Sel \\\n+ ((GLB_DSP_PBROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel])\n+\n+#define RomDriver_GLB_Get_DSP_ROOT_CLK_Sel \\\n+ ((GLB_DSP_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel])\n+\n+#define RomDriver_GLB_Get_DSP_XCLK_Sel \\\n+ ((GLB_DSP_XCLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel])\n+\n+#define RomDriver_GLB_Get_MCU_Muxpll_160M_Sel \\\n+ ((GLB_MCU_MUXPLL_160M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel])\n+\n+#define RomDriver_GLB_Get_MCU_Muxpll_80M_Sel \\\n+ ((GLB_MCU_MUXPLL_80M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel])\n+\n+#define RomDriver_GLB_Get_Flash_Id_Value \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Flash_Id_Value])\n+\n+#define RomDriver_GLB_Get_SRAM_PARM \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_SRAM_PARM])\n+\n+#define RomDriver_GLB_Get_SRAM_RET \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_SRAM_RET])\n+\n+#define RomDriver_GLB_Get_SRAM_SLP \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_SRAM_SLP])\n+\n+#define RomDriver_GLB_Get_BMX_TO_Status \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BMX_TO_Status])\n+\n+#define RomDriver_GLB_Clr_GPIO_IntStatus \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_GPIO_IntStatus])\n+\n+#define RomDriver_GLB_Embedded_Flash_Pad_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Embedded_Flash_Pad_Enable])\n+\n+#define RomDriver_GLB_GPIO_Clr \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Clr])\n+\n+#define RomDriver_GLB_GPIO_Fifo_Clear \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_Clear])\n+\n+#define RomDriver_GLB_GPIO_Fifo_Init \\\n+ ((BL_Err_Type (*) (GLB_GPIO_FIFO_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_Init])\n+\n+#define RomDriver_GLB_GPIO_Fifo_IntClear \\\n+ ((BL_Err_Type (*) (GLB_GPIO_FIFO_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_IntClear])\n+\n+#define RomDriver_GLB_GPIO_Fifo_IntMask \\\n+ ((BL_Err_Type (*) (GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_IntMask])\n+\n+#define RomDriver_GLB_GPIO_Fifo_Push \\\n+ ((BL_Err_Type (*) (uint16_t *data, uint16_t len))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_Push])\n+\n+#define RomDriver_GLB_GPIO_Func_Init \\\n+ ((BL_Err_Type (*) (GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Func_Init])\n+\n+#define RomDriver_GLB_GPIO_Init \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])\n+\n+#define RomDriver_GLB_GPIO_Input_Disable \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Input_Disable])\n+\n+#define RomDriver_GLB_GPIO_Input_Enable \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Input_Enable])\n+\n+#define RomDriver_GLB_GPIO_IntMask \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_IntMask])\n+\n+#define RomDriver_GLB_GPIO_Int_Init \\\n+ ((BL_Err_Type (*) (GLB_GPIO_INT_Cfg_Type *intCfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Int_Init])\n+\n+#define RomDriver_GLB_GPIO_Output_Disable \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Output_Disable])\n+\n+#define RomDriver_GLB_GPIO_Output_Enable \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Output_Enable])\n+\n+#define RomDriver_GLB_GPIO_Set \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set])\n+\n+#define RomDriver_GLB_GPIO_Set_HZ \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])\n+\n+#define RomDriver_GLB_GPIO_Write \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin, uint32_t val))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Write])\n+\n+#define RomDriver_GLB_GPIO_Fifo_Disable \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_Disable])\n+\n+#define RomDriver_GLB_GPIO_Fifo_Enable \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_Enable])\n+\n+#define RomDriver_GLB_GPIO_Fifo_GetIntStatus \\\n+ ((BL_Sts_Type (*) (GLB_GPIO_FIFO_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_GetIntStatus])\n+\n+#define RomDriver_GLB_Get_GPIO_IntStatus \\\n+ ((BL_Sts_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Get_GPIO_IntStatus])\n+\n+#define RomDriver_GLB_GPIO_Fifo_GetCount \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Fifo_GetCount])\n+\n+#define RomDriver_GLB_GPIO_Read \\\n+ ((uint32_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Read])\n+\n+#define RomDriver_GLB_GPIO_Get_Fun \\\n+ ((uint8_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])\n+\n+#define RomDriver_HBN_32K_Sel \\\n+ ((BL_Err_Type (*) (HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel])\n+\n+#define RomDriver_HBN_Aon_Pad_Cfg \\\n+ ((BL_Err_Type (*) (uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_Cfg])\n+\n+#define RomDriver_HBN_Aon_Pad_Ctrl \\\n+ ((BL_Err_Type (*) (uint32_t aonPadCtl1, uint32_t aonPadCtl2))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_Ctrl])\n+\n+#define RomDriver_HBN_Aon_Pad_WakeUpCfg \\\n+ ((BL_Err_Type (*) (BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg])\n+\n+#define RomDriver_HBN_Clear_IRQ \\\n+ ((BL_Err_Type (*) (HBN_INT_Type irqType))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_IRQ])\n+\n+#define RomDriver_HBN_Clear_RTC_Counter \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_RTC_Counter])\n+\n+#define RomDriver_HBN_Clear_RTC_INT \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_RTC_INT])\n+\n+#define RomDriver_HBN_Disable_AComp0_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_AComp0_IRQ])\n+\n+#define RomDriver_HBN_Disable_AComp1_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_AComp1_IRQ])\n+\n+#define RomDriver_HBN_Disable_BOD_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_BOD_IRQ])\n+\n+#define RomDriver_HBN_Enable_AComp0_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_AComp0_IRQ])\n+\n+#define RomDriver_HBN_Enable_AComp1_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_AComp1_IRQ])\n+\n+#define RomDriver_HBN_Enable_BOD_IRQ \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_BOD_IRQ])\n+\n+#define RomDriver_HBN_Enable_RTC_Counter \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_RTC_Counter])\n+\n+#define RomDriver_HBN_GPIO_INT_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_INT_Disable])\n+\n+#define RomDriver_HBN_GPIO_INT_Enable \\\n+ ((BL_Err_Type (*) (HBN_GPIO_INT_Trigger_Type gpioIntTrigType))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_INT_Enable])\n+\n+#define RomDriver_HBN_Get_RTC_Misc_Cfg \\\n+ ((BL_Err_Type (*) (HBN_RTC_MISC_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg])\n+\n+#define RomDriver_HBN_Get_RTC_Timer_Val \\\n+ ((BL_Err_Type (*) (uint32_t *valLow, uint32_t *valHigh))ROM_APITABLE[ROM_API_INDEX_HBN_Get_RTC_Timer_Val])\n+\n+#define RomDriver_HBN_Get_Xtal_Type \\\n+ ((BL_Err_Type (*) (uint8_t *xtalType))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Xtal_Type])\n+\n+#define RomDriver_HBN_Hw_Pu_Pd_Cfg \\\n+ ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg])\n+\n+#define RomDriver_HBN_PD_RC32K_All_State \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PD_RC32K_All_State])\n+\n+#define RomDriver_HBN_PD_RC32K_In_Poff \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PD_RC32K_In_Poff])\n+\n+#define RomDriver_HBN_PIR_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_Disable])\n+\n+#define RomDriver_HBN_PIR_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_Enable])\n+\n+#define RomDriver_HBN_PIR_HPF_Sel \\\n+ ((BL_Err_Type (*) (HBN_PIR_HPF_Type hpf))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_HPF_Sel])\n+\n+#define RomDriver_HBN_PIR_INT_Config \\\n+ ((BL_Err_Type (*) (HBN_PIR_INT_CFG_Type *pirIntCfg))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_INT_Config])\n+\n+#define RomDriver_HBN_PIR_LPF_Sel \\\n+ ((BL_Err_Type (*) (HBN_PIR_LPF_Type lpf))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_LPF_Sel])\n+\n+#define RomDriver_HBN_Pin_WakeUp_Mask \\\n+ ((BL_Err_Type (*) (uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask])\n+\n+#define RomDriver_HBN_Power_Off_RC32K \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K])\n+\n+#define RomDriver_HBN_Power_Off_Xtal_32K \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K])\n+\n+#define RomDriver_HBN_Power_On_RC32K \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K])\n+\n+#define RomDriver_HBN_Power_On_Xtal_32K \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K])\n+\n+#define RomDriver_HBN_Reset \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])\n+\n+#define RomDriver_HBN_Set_BOD_Cfg \\\n+ ((BL_Err_Type (*) (HBN_BOD_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_BOD_Cfg])\n+\n+#define RomDriver_HBN_Set_BOD_Config \\\n+ ((BL_Err_Type (*) (uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode))ROM_APITABLE[ROM_API_INDEX_HBN_Set_BOD_Config])\n+\n+#define RomDriver_HBN_Set_Core_Reboot_Config \\\n+ ((BL_Err_Type (*) (uint8_t core, uint8_t hcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Core_Reboot_Config])\n+\n+#define RomDriver_HBN_Set_HRAM_Ret \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_Ret])\n+\n+#define RomDriver_HBN_Set_HRAM_slp \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_slp])\n+\n+#define RomDriver_HBN_Set_Hand_Off_Config \\\n+ ((BL_Err_Type (*) (uint8_t dcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Hand_Off_Config])\n+\n+#define RomDriver_HBN_Set_IO4041_As_Xtal_32K_IO \\\n+ ((BL_Err_Type (*) (uint8_t xtal32kIoEn))ROM_APITABLE[ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO])\n+\n+#define RomDriver_HBN_Set_Ldo11_All_Vout \\\n+ ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_All_Vout])\n+\n+#define RomDriver_HBN_Set_Ldo11_Aon_Vout \\\n+ ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout])\n+\n+#define RomDriver_HBN_Set_Ldo11_Rt_Vout \\\n+ ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout])\n+\n+#define RomDriver_HBN_Set_Ldo11_Rtc_Vout \\\n+ ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout])\n+\n+#define RomDriver_HBN_Set_Ldo18flash_Repower_Delay \\\n+ ((BL_Err_Type (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay])\n+\n+#define RomDriver_HBN_Set_MCU_Root_CLK_Sel \\\n+ ((BL_Err_Type (*) (HBN_MCU_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel])\n+\n+#define RomDriver_HBN_Set_MCU_XCLK_Sel \\\n+ ((BL_Err_Type (*) (HBN_MCU_XCLK_Type xclk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel])\n+\n+#define RomDriver_HBN_Set_MM_Power_Config \\\n+ ((BL_Err_Type (*) (uint8_t pcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MM_Power_Config])\n+\n+#define RomDriver_HBN_Set_PIR_Interval \\\n+ ((BL_Err_Type (*) (uint16_t interval))ROM_APITABLE[ROM_API_INDEX_HBN_Set_PIR_Interval])\n+\n+#define RomDriver_HBN_Set_PIR_Threshold \\\n+ ((BL_Err_Type (*) (uint16_t threshold))ROM_APITABLE[ROM_API_INDEX_HBN_Set_PIR_Threshold])\n+\n+#define RomDriver_HBN_Set_RTC_Misc_Cfg \\\n+ ((BL_Err_Type (*) (HBN_RTC_MISC_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg])\n+\n+#define RomDriver_HBN_Set_RTC_Timer \\\n+ ((BL_Err_Type (*) (HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode))ROM_APITABLE[ROM_API_INDEX_HBN_Set_RTC_Timer])\n+\n+#define RomDriver_HBN_Set_Status_Flag \\\n+ ((BL_Err_Type (*) (uint32_t flag))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Status_Flag])\n+\n+#define RomDriver_HBN_Set_UART_CLK_Sel \\\n+ ((BL_Err_Type (*) (HBN_UART_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_UART_CLK_Sel])\n+\n+#define RomDriver_HBN_Set_Wakeup_Addr \\\n+ ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Wakeup_Addr])\n+\n+#define RomDriver_HBN_Set_Xtal_Type \\\n+ ((BL_Err_Type (*) (uint8_t xtalType))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Xtal_Type])\n+\n+#define RomDriver_HBN_Trim_RC32K \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])\n+\n+#define RomDriver_HBN_Get_BOD_OUT_State \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_BOD_OUT_State])\n+\n+#define RomDriver_HBN_Get_INT_State \\\n+ ((BL_Sts_Type (*) (HBN_INT_Type irqType))ROM_APITABLE[ROM_API_INDEX_HBN_Get_INT_State])\n+\n+#define RomDriver_HBN_Get_MCU_Root_CLK_Sel \\\n+ ((HBN_MCU_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_MCU_Root_CLK_Sel])\n+\n+#define RomDriver_HBN_Get_MCU_XCLK_Sel \\\n+ ((HBN_MCU_XCLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel])\n+\n+#define RomDriver_HBN_Get_Ldo18flash_Repower_Config \\\n+ ((uint16_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config])\n+\n+#define RomDriver_HBN_Get_PIR_Interval \\\n+ ((uint16_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_PIR_Interval])\n+\n+#define RomDriver_HBN_Get_PIR_Threshold \\\n+ ((uint16_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_PIR_Threshold])\n+\n+#define RomDriver_HBN_Get_Status_Flag \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Status_Flag])\n+\n+#define RomDriver_HBN_Get_Wakeup_Addr \\\n+ ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Wakeup_Addr])\n+\n+#define RomDriver_HBN_Get_Core_Unhalt_Config \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Core_Unhalt_Config])\n+\n+#define RomDriver_HBN_Get_Hand_Off_Config \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Hand_Off_Config])\n+\n+#define RomDriver_HBN_Get_MM_Power_Config \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_MM_Power_Config])\n+\n+#define RomDriver_HBN_Get_Pin_Wakeup_Mode \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode])\n+\n+#define RomDriver_HBN_Enable \\\n+ ((void (*) (uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])\n+\n+#define RomDriver_HBN_Mode_Enter \\\n+ ((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])\n+\n+#define RomDriver_HBN_Power_Down_Flash \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])\n+\n+#define RomDriver_L1C_DCache_Clean_All \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_All])\n+\n+#define RomDriver_L1C_DCache_Clean_By_Addr \\\n+ ((BL_Err_Type (*) (uintptr_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_By_Addr])\n+\n+#define RomDriver_L1C_DCache_Clean_Invalid_All \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_Invalid_All])\n+\n+#define RomDriver_L1C_DCache_Clean_Invalid_By_Addr \\\n+ ((BL_Err_Type (*) (uintptr_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_Invalid_By_Addr])\n+\n+#define RomDriver_L1C_DCache_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Disable])\n+\n+#define RomDriver_L1C_DCache_Enable \\\n+ ((BL_Err_Type (*) (uint8_t wayDsiable))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Enable])\n+\n+#define RomDriver_L1C_DCache_Invalid_All \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Invalid_All])\n+\n+#define RomDriver_L1C_DCache_Invalid_By_Addr \\\n+ ((BL_Err_Type (*) (uintptr_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Invalid_By_Addr])\n+\n+#define RomDriver_L1C_ICache_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_ICache_Disable])\n+\n+#define RomDriver_L1C_ICache_Enable \\\n+ ((BL_Err_Type (*) (uint8_t wayDsiable))ROM_APITABLE[ROM_API_INDEX_L1C_ICache_Enable])\n+\n+#define RomDriver_L1C_ICache_Invalid_All \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_ICache_Invalid_All])\n+\n+#define RomDriver_L1C_ICache_Invalid_By_Addr \\\n+ ((BL_Err_Type (*) (uintptr_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_L1C_ICache_Invalid_By_Addr])\n+\n+#define RomDriver_L1C_Set_Cache_Setting_By_ID \\\n+ ((BL_Err_Type (*) (uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Cache_Setting_By_ID])\n+\n+#define RomDriver_L1C_Set_Wrap \\\n+ ((BL_Err_Type (*) (uint8_t en))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])\n+\n+#define RomDriver_L1C_Get_None_Cache_Addr \\\n+ ((int (*) (uintptr_t addr))ROM_APITABLE[ROM_API_INDEX_L1C_Get_None_Cache_Addr])\n+\n+#define RomDriver_L1C_Is_DCache_Range \\\n+ ((int (*) (uintptr_t addr))ROM_APITABLE[ROM_API_INDEX_L1C_Is_DCache_Range])\n+\n+#define RomDriver_L1C_DCache_Write_Set \\\n+ ((void (*) (BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Write_Set])\n+\n+#define RomDriver_PDS_Default_Level_Config \\\n+ ((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config])\n+\n+#define RomDriver_PDS_Enable \\\n+ ((BL_Err_Type (*) (PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Enable])\n+\n+#define RomDriver_PDS_Force_Config \\\n+ ((BL_Err_Type (*) (PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5))ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config])\n+\n+#define RomDriver_PDS_IntClear \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_IntClear])\n+\n+#define RomDriver_PDS_IntMask \\\n+ ((BL_Err_Type (*) (PDS_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_PDS_IntMask])\n+\n+#define RomDriver_PDS_Power_On_MM_System \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_MM_System])\n+\n+#define RomDriver_PDS_RAM_Config \\\n+ ((BL_Err_Type (*) (PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])\n+\n+#define RomDriver_PDS_Reset_LP_RTC \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset_LP_RTC])\n+\n+#define RomDriver_PDS_Set_Flash_Pad_Pull_None \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None])\n+\n+#define RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast])\n+\n+#define RomDriver_PDS_Set_GPIO_Pad_IntClr \\\n+ ((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr])\n+\n+#define RomDriver_PDS_Set_GPIO_Pad_IntMask \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type pad, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask])\n+\n+#define RomDriver_PDS_Set_GPIO_Pad_IntMode \\\n+ ((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode])\n+\n+#define RomDriver_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie \\\n+ ((BL_Err_Type (*) (GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie])\n+\n+#define RomDriver_PDS_Set_LP_Clock_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Clock_Disable])\n+\n+#define RomDriver_PDS_Set_LP_Clock_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Clock_Enable])\n+\n+#define RomDriver_PDS_Set_LP_RTC_CLK \\\n+ ((BL_Err_Type (*) (uint8_t enable, uint16_t div))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_RTC_CLK])\n+\n+#define RomDriver_PDS_Set_LP_Reset_Address \\\n+ ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Reset_Address])\n+\n+#define RomDriver_PDS_Set_LP_System_CLK \\\n+ ((BL_Err_Type (*) (PDS_LP_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_System_CLK])\n+\n+#define RomDriver_PDS_Set_LP_System_CLK_Div \\\n+ ((BL_Err_Type (*) (uint8_t div))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_System_CLK_Div])\n+\n+#define RomDriver_PDS_Set_MCU0_Clock_Disable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable])\n+\n+#define RomDriver_PDS_Set_MCU0_Clock_Enable \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_MCU0_Clock_Enable])\n+\n+#define RomDriver_PDS_Set_MCU0_Reset_Address \\\n+ ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_PDS_Set_MCU0_Reset_Address])\n+\n+#define RomDriver_PDS_Set_USB_Resume \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_USB_Resume])\n+\n+#define RomDriver_PDS_Set_USB_Suspend \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_USB_Suspend])\n+\n+#define RomDriver_PDS_Trim_RC32M \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])\n+\n+#define RomDriver_PDS_Turn_Off_USB \\\n+ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Turn_Off_USB])\n+\n+#define RomDriver_PDS_Turn_On_USB \\\n+ ((BL_Err_Type (*) (uint8_t waitReady))ROM_APITABLE[ROM_API_INDEX_PDS_Turn_On_USB])\n+\n+#define RomDriver_PDS_Get_GPIO_Pad_IntStatus \\\n+ ((BL_Sts_Type (*) (GLB_GPIO_Type pad))ROM_APITABLE[ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus])\n+\n+#define RomDriver_PDS_Get_IntStatus \\\n+ ((BL_Sts_Type (*) (PDS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_IntStatus])\n+\n+#define RomDriver_PDS_Get_MM_System_Power_On_State \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Get_MM_System_Power_On_State])\n+\n+#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \\\n+ ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])\n+\n+#define RomDriver_SF_Cfg_Flash_Init \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init])\n+\n+#if 0\n+#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \\\n+ ((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])\n+#endif\n+\n+#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext \\\n+ ((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext])\n+\n+#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \\\n+ ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])\n+\n+#define RomDriver_SF_Cfg_Init_Flash_Gpio \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])\n+\n+#define RomDriver_SF_Cfg_Sbus2_Flash_Init \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init])\n+\n+#define RomDriver_SF_Cfg_Flash_Identify \\\n+ ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])\n+\n+#define RomDriver_SF_Cfg_Flash_Identify_Ext \\\n+ ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext])\n+\n+#define RomDriver_SF_Ctrl_GetBusyState \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])\n+\n+#define RomDriver_SF_Ctrl_Is_AES_Enable \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])\n+\n+#define RomDriver_SF_Ctrl_Is_Sbus2_Enable \\\n+ ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable])\n+\n+#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \\\n+ ((uint32_t (*) (uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])\n+\n+#define RomDriver_SF_Ctrl_Get_Clock_Delay \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])\n+\n+#define RomDriver_SF_Ctrl_Get_Wrap_Queue_Value \\\n+ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Wrap_Queue_Value])\n+\n+#define RomDriver_SF_Ctrl_32bits_Addr_En \\\n+ ((void (*) (BL_Fun_Type en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_32bits_Addr_En])\n+\n+#define RomDriver_SF_Ctrl_AES_Disable \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])\n+\n+#define RomDriver_SF_Ctrl_AES_Enable \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])\n+\n+#define RomDriver_SF_Ctrl_AES_Enable_BE \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])\n+\n+#define RomDriver_SF_Ctrl_AES_Enable_LE \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_IV \\\n+ ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_IV_BE \\\n+ ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_Key \\\n+ ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_Key_BE \\\n+ ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_Mode \\\n+ ((void (*) (SF_Ctrl_AES_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode])\n+\n+#define RomDriver_SF_Ctrl_AES_Set_Region \\\n+ ((void (*) (uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])\n+\n+#define RomDriver_SF_Ctrl_AES_XTS_Set_IV \\\n+ ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV])\n+\n+#define RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE \\\n+ ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE])\n+\n+#define RomDriver_SF_Ctrl_AES_XTS_Set_Key \\\n+ ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key])\n+\n+#define RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE \\\n+ ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE])\n+\n+#define RomDriver_SF_Ctrl_Bank2_Enable \\\n+ ((void (*) (const SF_Ctrl_Bank2_Cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable])\n+\n+#define RomDriver_SF_Ctrl_Cmds_Set \\\n+ ((void (*) (SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])\n+\n+#define RomDriver_SF_Ctrl_Disable \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])\n+\n+#define RomDriver_SF_Ctrl_Disable_Wrap_Access \\\n+ ((void (*) (uint8_t disable))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access])\n+\n+#define RomDriver_SF_Ctrl_Enable \\\n+ ((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])\n+\n+#define RomDriver_SF_Ctrl_Flash2_Read_Icache_Set \\\n+ ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set])\n+\n+#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \\\n+ ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])\n+\n+#define RomDriver_SF_Ctrl_Lock_Flash_Image_Offset \\\n+ ((void (*) (uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset])\n+\n+#define RomDriver_SF_Ctrl_Remap_Set \\\n+ ((void (*) (SF_Ctrl_Remap_Type remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set])\n+\n+#define RomDriver_SF_Ctrl_Sbus2_Hold_Sram \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram])\n+\n+#define RomDriver_SF_Ctrl_Sbus2_Release_Sram \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram])\n+\n+#define RomDriver_SF_Ctrl_Sbus2_Replace \\\n+ ((void (*) (SF_Ctrl_Pad_Type pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace])\n+\n+#define RomDriver_SF_Ctrl_Sbus2_Revoke_replace \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace])\n+\n+#define RomDriver_SF_Ctrl_Sbus2_Set_Delay \\\n+ ((void (*) (uint8_t clkDelay, uint8_t rxClkInvert))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay])\n+\n+#define RomDriver_SF_Ctrl_Sbus_Select_Bank \\\n+ ((void (*) (SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank])\n+\n+#define RomDriver_SF_Ctrl_Select_Pad \\\n+ ((void (*) (SF_Ctrl_Pin_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])\n+\n+#define RomDriver_SF_Ctrl_SendCmd \\\n+ ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])\n+\n+#define RomDriver_SF_Ctrl_Set_Clock_Delay \\\n+ ((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])\n+\n+#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \\\n+ ((void (*) (uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])\n+\n+#define RomDriver_SF_Ctrl_Set_IO_Delay \\\n+ ((void (*) (SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay])\n+\n+#define RomDriver_SF_Ctrl_Set_Owner \\\n+ ((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])\n+\n+#define RomDriver_SFlash_Blk32_Erase \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])\n+\n+#define RomDriver_SFlash_Blk64_Erase \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])\n+\n+#define RomDriver_SFlash_Chip_Erase \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])\n+\n+#define RomDriver_SFlash_Erase \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])\n+\n+#define RomDriver_SFlash_Erase_Security_Register \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register])\n+\n+#define RomDriver_SFlash_IDbus_Read_Enable \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])\n+\n+#define RomDriver_SFlash_Program \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])\n+\n+#define RomDriver_SFlash_Program_Security_Register \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register])\n+\n+#define RomDriver_SFlash_Qspi_Disable \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable])\n+\n+#define RomDriver_SFlash_Qspi_Enable \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])\n+\n+#define RomDriver_SFlash_RCV_Enable \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable])\n+\n+#define RomDriver_SFlash_Read \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])\n+\n+#define RomDriver_SFlash_Read_Reg \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])\n+\n+#define RomDriver_SFlash_Read_Reg_With_Cmd \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])\n+\n+#define RomDriver_SFlash_Read_Security_Register \\\n+ ((BL_Err_Type (*) (SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register])\n+\n+#define RomDriver_SFlash_Restore_From_Powerdown \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])\n+\n+#define RomDriver_SFlash_Sector_Erase \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])\n+\n+#define RomDriver_SFlash_Set32BitsAddrMode \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode])\n+\n+#define RomDriver_SFlash_SetSPIMode \\\n+ ((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])\n+\n+#define RomDriver_SFlash_Set_IDbus_Cfg \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])\n+\n+#define RomDriver_SFlash_Software_Reset \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])\n+\n+#define RomDriver_SFlash_Write_Enable \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])\n+\n+#define RomDriver_SFlash_Write_Reg \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])\n+\n+#define RomDriver_SFlash_Write_Reg_With_Cmd \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])\n+\n+#define RomDriver_SFlash_Busy \\\n+ ((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])\n+\n+#define RomDriver_SFlash_DisableBurstWrap \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])\n+\n+#define RomDriver_SFlash_GetDeviceId \\\n+ ((void (*) (uint8_t *data, BL_Fun_Type is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])\n+\n+#define RomDriver_SFlash_GetJedecId \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])\n+\n+#define RomDriver_SFlash_GetUniqueId \\\n+ ((void (*) (uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])\n+\n+#define RomDriver_SFlash_IDbus_Read_Disable \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Disable])\n+\n+#define RomDriver_SFlash_Init \\\n+ ((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])\n+\n+#define RomDriver_SFlash_Powerdown \\\n+ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])\n+\n+#define RomDriver_SFlash_Release_Powerdown \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown])\n+\n+#define RomDriver_SFlash_Reset_Continue_Read \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])\n+\n+#define RomDriver_SFlash_SetBurstWrap \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])\n+\n+#define RomDriver_SFlash_Volatile_Reg_Write_Enable \\\n+ ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])\n+\n+#define RomDriver_UART_ApplyAbrResult \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_ApplyAbrResult])\n+\n+#define RomDriver_UART_AutoBaudDetection \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type autoBaud))ROM_APITABLE[ROM_API_INDEX_UART_AutoBaudDetection])\n+\n+#define RomDriver_UART_ClrRtsValue \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_ClrRtsValue])\n+\n+#define RomDriver_UART_ClrTxValue \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_ClrTxValue])\n+\n+#define RomDriver_UART_DeInit \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_DeInit])\n+\n+#define RomDriver_UART_Disable \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_UART_Disable])\n+\n+#define RomDriver_UART_Enable \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_UART_Enable])\n+\n+#define RomDriver_UART_FifoConfig \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg))ROM_APITABLE[ROM_API_INDEX_UART_FifoConfig])\n+\n+#define RomDriver_UART_GetBitWidth0X55 \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t *width))ROM_APITABLE[ROM_API_INDEX_UART_GetBitWidth0X55])\n+\n+#define RomDriver_UART_Init \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_CFG_Type *uartCfg))ROM_APITABLE[ROM_API_INDEX_UART_Init])\n+\n+#define RomDriver_UART_IntClear \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_UART_IntClear])\n+\n+#define RomDriver_UART_IntMask \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_UART_IntMask])\n+\n+#define RomDriver_UART_IrConfig \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, UART_IrCfg_Type *irCfg))ROM_APITABLE[ROM_API_INDEX_UART_IrConfig])\n+\n+#define RomDriver_UART_RxFifoClear \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_RxFifoClear])\n+\n+#define RomDriver_UART_SendData \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_UART_SendData])\n+\n+#define RomDriver_UART_SendDataBlock \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_UART_SendDataBlock])\n+\n+#define RomDriver_UART_SetAllowableError0X55 \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t allowableError))ROM_APITABLE[ROM_API_INDEX_UART_SetAllowableError0X55])\n+\n+#define RomDriver_UART_SetBaudRate \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint32_t baudRate))ROM_APITABLE[ROM_API_INDEX_UART_SetBaudRate])\n+\n+#define RomDriver_UART_SetDeglitchCount \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t deglitchCnt))ROM_APITABLE[ROM_API_INDEX_UART_SetDeglitchCount])\n+\n+#define RomDriver_UART_SetRS485 \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity))ROM_APITABLE[ROM_API_INDEX_UART_SetRS485])\n+\n+#define RomDriver_UART_SetRtsValue \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_SetRtsValue])\n+\n+#define RomDriver_UART_SetRxByteCount \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t count))ROM_APITABLE[ROM_API_INDEX_UART_SetRxByteCount])\n+\n+#define RomDriver_UART_SetRxDataLength \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t length))ROM_APITABLE[ROM_API_INDEX_UART_SetRxDataLength])\n+\n+#define RomDriver_UART_SetRxTimeoutValue \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t time))ROM_APITABLE[ROM_API_INDEX_UART_SetRxTimeoutValue])\n+\n+#define RomDriver_UART_SetTxDataLength \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t length))ROM_APITABLE[ROM_API_INDEX_UART_SetTxDataLength])\n+\n+#define RomDriver_UART_SetTxValue \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_SetTxValue])\n+\n+#define RomDriver_UART_TxFifoClear \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_TxFifoClear])\n+\n+#define RomDriver_UART_TxFreeRun \\\n+ ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type txFreeRun))ROM_APITABLE[ROM_API_INDEX_UART_TxFreeRun])\n+\n+#define RomDriver_UART_GetIntStatus \\\n+ ((BL_Sts_Type (*) (UART_ID_Type uartId, UART_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_UART_GetIntStatus])\n+\n+#define RomDriver_UART_GetOverflowStatus \\\n+ ((BL_Sts_Type (*) (UART_ID_Type uartId, UART_Overflow_Type overflow))ROM_APITABLE[ROM_API_INDEX_UART_GetOverflowStatus])\n+\n+#define RomDriver_UART_GetRxBusBusyStatus \\\n+ ((BL_Sts_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxBusBusyStatus])\n+\n+#define RomDriver_UART_GetTxBusBusyStatus \\\n+ ((BL_Sts_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxBusBusyStatus])\n+\n+#define RomDriver_UART_GetAutoBaudCount \\\n+ ((uint16_t (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_GetAutoBaudCount])\n+\n+#define RomDriver_UART_GetRxByteCount \\\n+ ((uint16_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxByteCount])\n+\n+#define RomDriver_UART_ReceiveData \\\n+ ((uint32_t (*) (UART_ID_Type uartId, uint8_t *data, uint32_t maxLen))ROM_APITABLE[ROM_API_INDEX_UART_ReceiveData])\n+\n+#define RomDriver_UART_GetRxFifoCount \\\n+ ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxFifoCount])\n+\n+#define RomDriver_UART_GetTxFifoCount \\\n+ ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxFifoCount])\n+\n+#define RomDriver_XIP_SFlash_Erase_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_Read_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \\\n+ ((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_State_Restore \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])\n+\n+#define RomDriver_XIP_SFlash_State_Save \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])\n+\n+#define RomDriver_XIP_SFlash_Write_Need_Lock \\\n+ ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])\n+\n+#define RomDriver_XIP_SFlash_Opt_Enter \\\n+ ((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])\n+\n+#define RomDriver_XIP_SFlash_Opt_Exit \\\n+ ((void (*) (uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit])\n+\n+/*@} end of group ROMDRIVER_Public_Macros */\n+\n+/** @defgroup ROMDRIVER_Public_Functions\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Public_Functions */\n+\n+/*@} end of group ROMDRIVER */\n+\n+/*@} end of group bl808_Peripheral_Driver */\n+\n+#endif /* __bl808_ROMDRIVER_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5497548d341c1ba3585ee4c8368d971c340c2d73\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h\n@@ -0,0 +1,979 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sdh.h\n+ * @version V1.2\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2018 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SDH_H__\n+#define __BL808_SDH_H__\n+\n+#include \"sdh_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SDH\n+ * @{\n+ */\n+\n+/** @defgroup SDH_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief SDH status type definition\n+ */\n+typedef enum {\n+ SDH_STAT_SUCCESS = 0, /*!< SDH status success */\n+ SDH_STAT_BUSY, /*!< SDH status busy */\n+ SDH_STAT_INVLAID_PARA, /*!< SDH status invalid parameter */\n+ SDH_STAT_NOT_SUPPORT, /*!< SDH not support this feature */\n+ SDH_STAT_OUTOF_RANGE, /*!< SDH out of range */\n+ SDH_STAT_PREPARE_DESC, /*!< SDH status prepare ADMA descriptor */\n+ SDH_STAT_SEND_CMD_FAIL, /*!< SDH status send command fail */\n+ SDH_STAT_SEND_DATA_FAIL, /*!< SDH status send data fail */\n+ SDH_STAT_RECV_DATA_FAIL, /*!< SDH status receive data fail */\n+ SDH_STAT_DMA_ADDR_NOT_ALIGN, /*!< SDH status DMA address not align */\n+ SDH_STAT_RETUNE_REQ, /*!< SDH status re-tune request */\n+ SDH_STAT_TUNE_ERROR, /*!< SDH status tune error */\n+} SDH_Stat_Type;\n+\n+/**\n+ * @brief SDH capability type definition\n+ */\n+typedef enum {\n+ SDH_CAP_SUPPORT_8BITS = 0x00000004, /*!< SDH support 8 bits */\n+ SDH_CAP_SUPPORT_ADMA2 = 0x00000008, /*!< SDH support ADMA 2 */\n+ SDH_CAP_SUPPORT_ADMA1 = 0x00000010, /*!< SDH support ADMA 1 */\n+ SDH_CAP_SUPPORT_HIGHSPEED = 0x00000020, /*!< SDH support SDMA */\n+ SDH_CAP_SUPPORT_SDMA = 0x00000040, /*!< SDH support high speed */\n+ SDH_CAP_SUPPORT_SUS_RES = 0x00000080, /*!< SDH support suspend and resume */\n+ SDH_CAP_SUPPORT_VLT33 = 0x00000100, /*!< SDH support voltgae 3.3V */\n+ SDH_CAP_SUPPORT_VLT30 = 0x00000200, /*!< SDH support voltage 3.0V */\n+ SDH_CAP_SUPPORT_VLT18 = 0x00000400, /*!< SDH support voltage 1.8V */\n+ SDH_CAP_SUPPORT_SBUS_64BITS = 0x00001000, /*!< SDH support system bus 64 bits */\n+ SDH_CAP_SUPPORT_ASYNC_INT = 0x00002000, /*!< SDH support async interrupt */\n+ SDH_CAP_SUPPORT_DDR50 = 0x00010000, /*!< SDH support DDR 50MHz */\n+ SDH_CAP_SUPPORT_SDR104 = 0x00020000, /*!< SDH support SDR 104MHz */\n+ SDH_CAP_SUPPORT_SDR50 = 0x00040000, /*!< SDH support SDR 50MHz */\n+ SDH_CAP_SUPPORT_DRV_TYPE_A = 0x00100000, /*!< SDH support driver type C */\n+ SDH_CAP_SUPPORT_DRV_TYPE_C = 0x00200000, /*!< SDH support driver type A */\n+ SDH_CAP_SUPPORT_DRV_TYPE_D = 0x00400000, /*!< SDH support driver type A */\n+ SDH_CAP_SUPPORT_SDR50_TUNE = 0x20000000, /*!< SDH support SDR 50MHz tuning */\n+} SDH_Cap_Support_Type;\n+\n+/**\n+ * @brief SDH wakeup event type definition\n+ */\n+typedef enum {\n+ SDH_WAKEUP_EVENT_INT, /*!< Wakeup on card interrupt */\n+ SDH_WAKEUP_EVENT_INSERT, /*!< Wakeup on card insertion */\n+ SDH_WAKEUP_EVENT_REMOVE, /*!< Wakeup on card remove */\n+} SDH_Wakeup_Event_Type;\n+\n+/**\n+ * @brief SDH trnasfer flag type definition\n+ */\n+typedef enum {\n+ SDH_TRANS_FLAG_NONE = 0x00000000,\n+ SDH_TRANS_FLAG_EN_DMA = 0x00000001, /*!< Enable DMA */\n+ SDH_TRANS_FLAG_EN_BLK_COUNT = 0x00000002, /*!< Enable block count */\n+ SDH_TRANS_FLAG_EN_AUTO_CMD12 = 0x00000004, /*!< Enable auto CMD12 */\n+ SDH_TRANS_FLAG_EN_AUTO_CMD23 = 0x00000008, /*!< Enable auto CMD23 */\n+ SDH_TRANS_FLAG_READ_DATA = 0x00000010, /*!< Enable read data */\n+ SDH_TRANS_FLAG_MULTI_BLK = 0x00000020, /*!< Enable multi-block data operation */\n+ SDH_TRANS_FLAG_RESP_136BITS = 0x00010000, /*!< Response is 136 bits length */\n+ SDH_TRANS_FLAG_RESP_48BITS = 0x00020000, /*!< Response is 48 bits length */\n+ SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY = 0x00030000, /*!< Response is 48 bits length with busy status */\n+ SDH_TRANS_FLAG_EN_CRC_CHECK = 0x00080000, /*!< Enable CRC check */\n+ SDH_TRANS_FLAG_EN_INDEX_CHECK = 0x00100000, /*!< Enable index check */\n+ SDH_TRANS_FLAG_DATA_PRESENT = 0x00200000, /*!< Data present */\n+ SDH_TRANS_FLAG_SUSPEND = 0x00400000, /*!< Suspend command */\n+ SDH_TRANS_FLAG_RESUME = 0x00800000, /*!< Resume command */\n+ SDH_TRANS_FLAG_ABORT = 0x00C00000, /*!< Abort command */\n+} SDH_Trans_Flag_Type;\n+\n+/**\n+ * @brief SDH present flag type definition\n+ */\n+typedef enum {\n+ SDH_PRESENT_FLAG_CMD_INHBIT = 0x00000001, /*!< Command inhbit */\n+ SDH_PRESENT_FLAG_DATA_INHBIT = 0x00000002, /*!< Data inhbit */\n+ SDH_PRESENT_FLAG_DATA_LINE_ACTIVE = 0x00000004, /*!< Data line active */\n+ SDH_PRESENT_FLAG_RETUNE_REQ = 0x00000008, /*!< Retuning request */\n+ SDH_PRESENT_FLAG_TX_ACTIVE = 0x00000100, /*!< Write trnasfer atcive */\n+ SDH_PRESENT_FLAG_RX_ACTIVE = 0x00000200, /*!< Read transfer active */\n+ SDH_PRESENT_FLAG_BUF_WRITE_ENABLE = 0x00000400, /*!< Buffer write enabled */\n+ SDH_PRESENT_FLAG_BUF_READ_ENABLE = 0x00000800, /*!< Buffer read enabled */\n+ SDH_PRESENT_FLAG_CARD_INSERT = 0x00010000, /*!< Card intert */\n+ SDH_PRESENT_FLAG_CARD_STABLE = 0x00020000, /*!< Card stable */\n+ SDH_PRESENT_FLAG_CARD_DET = 0x00040000, /*!< Card detect */\n+ SDH_PRESENT_FLAG_CARD_WP = 0x00080000, /*!< Card write protect */\n+ SDH_PRESENT_FLAG_DATA0_LINE_LEVEL = 0x00100000, /*!< Data 0 line signal level */\n+ SDH_PRESENT_FLAG_DATA1_LINE_LEVEL = 0x00200000, /*!< Data 1 line signal level */\n+ SDH_PRESENT_FLAG_DATA2_LINE_LEVEL = 0x00400000, /*!< Data 2 line signal level */\n+ SDH_PRESENT_FLAG_DATA3_LINE_LEVEL = 0x00800000, /*!< Data 3 line signal level */\n+ SDH_PRESENT_FLAG_CMD_LINE_LEVEL = 0x01000000, /*!< Command line signal level */\n+} SDH_Present_Flag_Type;\n+\n+/**\n+ * @brief SDH interrupt type definition\n+ */\n+#define SDH_INT_CMD_COMPLETED ((uint32_t)(0x00000001)) /*!< SDH command complete interrupt */\n+#define SDH_INT_DATA_COMPLETED ((uint32_t)(0x00000002)) /*!< SDH data complete interrupt */\n+#define SDH_INT_BLK_GAP_EVENT ((uint32_t)(0x00000004)) /*!< SDH block gap event interrupt */\n+#define SDH_INT_DMA_COMPLETED ((uint32_t)(0x00000008)) /*!< SDH DMA complete interrupt */\n+#define SDH_INT_BUFFER_WRITE_READY ((uint32_t)(0x00000010)) /*!< SDH buffer write ready interrupt */\n+#define SDH_INT_BUFFER_READ_READY ((uint32_t)(0x00000020)) /*!< SDH buffer read ready interrupt */\n+#define SDH_INT_CARD_INSERT ((uint32_t)(0x00000040)) /*!< SDH card insert interrupt */\n+#define SDH_INT_CARD_REMOVE ((uint32_t)(0x00000080)) /*!< SDH card remove interrupt */\n+#define SDH_INT_CARD ((uint32_t)(0x00000100)) /*!< SDH card produce interrupt */\n+#define SDH_INT_DRIVER_TA ((uint32_t)(0x00000200)) /*!< SDH driver type A interrupt */\n+#define SDH_INT_DRIVER_TB ((uint32_t)(0x00000400)) /*!< SDH driver type B interrupt */\n+#define SDH_INT_DRIVER_TC ((uint32_t)(0x00000800)) /*!< SDH driver type C interrupt */\n+#define SDH_INT_RETUNE_EVENT ((uint32_t)(0x00001000)) /*!< SDH re-tuning event interrupt */\n+#define SDH_INT_CMD_TIMEOUT ((uint32_t)(0x00010000)) /*!< SDH command timeout interrupt */\n+#define SDH_INT_CMD_CRC_ERROR ((uint32_t)(0x00020000)) /*!< SDH command CRC error interrupt */\n+#define SDH_INT_CMD_ENDBIT_ERROR ((uint32_t)(0x00040000)) /*!< SDH command endbit error interrupt */\n+#define SDH_INT_CMD_INDEX_ERROR ((uint32_t)(0x00080000)) /*!< SDH command index error interrupt */\n+#define SDH_INT_DATA_TIMEOUT ((uint32_t)(0x00100000)) /*!< SDH data timeout interrupt */\n+#define SDH_INT_DATA_CRC_ERROR ((uint32_t)(0x00200000)) /*!< SDH data CRC error interrupt */\n+#define SDH_INT_DATA_ENDBIT_ERROR ((uint32_t)(0x00400000)) /*!< SDH data endbit error interrupt */\n+#define SDH_INT_CURRENT_ERROR ((uint32_t)(0x00800000)) /*!< SDH current error interrupt */\n+#define SDH_INT_AUTO_CMD12_ERROR ((uint32_t)(0x01000000)) /*!< SDH auto command12 error */\n+#define SDH_INT_DMA_ERROR ((uint32_t)(0x02000000)) /*!< SDH DMA error interrupt */\n+#define SDH_INT_TUNE_ERROR ((uint32_t)(0x04000000)) /*!< SDH tuning maybe fail,this bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure */\n+#define SDH_INT_SPI_ERROR ((uint32_t)(0x10000000)) /*!< SDH SPI mode error,read <SPI Error Token> field in the SPI mode register */\n+#define SDH_INT_AXI_RESP_ERROR ((uint32_t)(0x20000000)) /*!< SDH AXI bus response error */\n+#define SDH_INT_CPL_TIMEOUT_ERROR ((uint32_t)(0x40000000)) /*!< SDH command completion signal timeout error,this field is applicable for CE-ATA mode only */\n+#define SDH_INT_CRC_STAT_ERROR ((uint32_t)(0x80000000)) /*!< SDH CRC status start bit or CRC status end bit or boot ack status, returned from the card in write transaction has errors */\n+#define SDH_INT_CMD_ERRORS ((uint32_t)(0x000f0000)) /*!< SDH all command errors */\n+#define SDH_INT_DATA_ERRORS ((uint32_t)(0x01700000)) /*!< SDH all data errors */\n+#define SDH_INT_ALL ((uint32_t)(0xffffffff)) /*!< SDH all interrupt */\n+\n+/**\n+ * @brief SDH boot mode type definition\n+ */\n+typedef enum {\n+ SDH_BOOT_MODE_NORMAL, /*!< SDH normal boot mode */\n+ SDH_BOOT_MODE_ALT, /*!< SDH alternative boot mode */\n+} SDH_Boot_Mode_Type;\n+\n+/**\n+ * @brief SDH auto command 12 error status type definition\n+ */\n+typedef enum {\n+ SDH_AUTO_CMD12_ERR_NOT_EXE, /*!< SDH auto command not execute error */\n+ SDH_AUTO_CMD12_ERR_TIMEOUT, /*!< SDH auto command timeout error */\n+ SDH_AUTO_CMD12_ERR_ENDBIT, /*!< SDH auto command endbit error */\n+ SDH_AUTO_CMD12_ERR_INDEX, /*!< SDH auto command index error */\n+ SDH_AUTO_CMD12_ERR_CRC, /*!< SDH auto command CRC error */\n+ SDH_AUTO_CMD12_ERR_NOT_ISSUE, /*!< SDH auto command not issue error */\n+} SDH_AUTO_CMD12_ERR_Type;\n+\n+/**\n+ * @brief SDH ADMA error type definition\n+ */\n+typedef enum {\n+ SDH_ADMA_ERR_LEN_MISMATCH, /*!< SDH ADMA length mismatch */\n+ SDH_ADMA_ERR_DESC_ERROR, /*!< SDH ADMA descriptor error */\n+} SDH_ADMA_ERR_Type;\n+\n+/**\n+ * @brief SDH ADMA error status type definition\n+ */\n+typedef enum {\n+ SDH_ADMA_ERR_STAT_STOP_DMA, /*!< SDH ADMA stop */\n+ SDH_ADMA_ERR_STAT_FETCH_DESC, /*!< SDH ADMA fetch descriptor */\n+ SDH_ADMA_ERR_STAT_CHANGE_ADDR, /*!< SDH ADMA change address */\n+ SDH_ADMA_ERR_STAT_TRANS_DATA, /*!< SDH ADMA transfer data */\n+ SDH_ADMA_ERR_STAT_INVALID_LEN, /*!< SDH ADMA invalid length */\n+ SDH_ADMA_ERR_STAT_INVALID_DESC, /*!< SDH ADMA invalid descriptor */\n+} SDH_ADMA_ERR_Stat_Type;\n+\n+/**\n+ * @brief SDH force event type definition\n+ */\n+typedef enum {\n+ SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE, /*!< SDH force event auto command 12 not executed */\n+ SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT, /*!< SDH force event auto command 12 timeout */\n+ SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR, /*!< SDH force event auto command 12 crc error */\n+ SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR, /*!< SDH force event auto command 12 index error */\n+ SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE, /*!< SDH force event auto command 12 not issue */\n+ SDH_FORCE_EVENT_ENDBIT_ERROR, /*!< SDH force event end bit error */\n+ SDH_FORCE_EVENT_CMD_TIMEOUT, /*!< SDH force event command timeout */\n+ SDH_FORCE_EVENT_CMD_CRC_ERROR, /*!< SDH force event command crc error */\n+ SDH_FORCE_EVENT_CMD_ENDBIT_ERROR, /*!< SDH force event command end bit error */\n+ SDH_FORCE_EVENT_CMD_INDEX_ERROR, /*!< SDH force event command index error */\n+ SDH_FORCE_EVENT_DATA_TIMEOUT, /*!< SDH force event data timeout */\n+ SDH_FORCE_EVENT_DATA_CRC_ERROR, /*!< SDH force event data crc error */\n+ SDH_FORCE_EVENT_DATA_ENDBIT_ERROR, /*!< SDH force event data end bit error */\n+ SDH_FORCE_EVENT_DATA_INDEX_ERROR, /*!< SDH force event data index error */\n+ SDH_FORCE_EVENT_AUTO_CMD12_ERROR, /*!< SDH force event auto command 12 error */\n+ SDH_FORCE_EVENT_CARD_INT, /*!< SDH force event card interrupt */\n+ SDH_FORCE_EVENT_DMA_ERROR, /*!< SDH force event DMA error */\n+} SDH_Force_Event_Type;\n+\n+/**\n+ * @brief SDH speed mode type definition\n+ */\n+typedef enum {\n+ SDH_SPEED_MODE_SDR12, /*!< SDH speed :12.5MHZ */\n+ SDH_SPEED_MODE_SDR25, /*!< SDH speed :25MHZ */\n+ SDH_SPEED_MODE_SDR50, /*!< SDH speed :50MHZ */\n+ SDH_SPEED_MODE_SDR104, /*!< SDH speed :104MHZ */\n+ SDH_SPEED_MODE_DDR50, /*!< SDH speed :50MHZ (DDR mode) */\n+} SDH_Speed_Mode_Type;\n+\n+/**\n+ * @brief SDH data bus width type definition\n+ */\n+typedef enum {\n+ SDH_DATA_BUS_WIDTH_1BIT, /*!< SDH data bus width 1 bit */\n+ SDH_DATA_BUS_WIDTH_4BITS, /*!< SDH data bus width 4 bits */\n+ SDH_DATA_BUS_WIDTH_8BITS, /*!< SDH data bus width 8 bits */\n+} SDH_Data_Bus_Width_Type;\n+\n+/**\n+ * @brief SDH voltage type definition\n+ */\n+typedef enum {\n+ SDH_VOLTAGE_3P3V = 0x07, /*!< SDH voltage 3.3V */\n+ SDH_VOLTAGE_3P0V = 0x06, /*!< SDH voltage 3.0V */\n+ SDH_VOLTAGE_1P8V = 0x05, /*!< SDH voltage 1.8V */\n+} SDH_Voltage_Type;\n+\n+/**\n+ * @brief SDH DMA mode type definition\n+ */\n+typedef enum {\n+ SDH_DMA_MODE_SIMPLE, /*!< SDH DMA mode:simple */\n+ SDH_DMA_MODE_ADMA1, /*!< SDH DMA mode:ADMA1 */\n+ SDH_DMA_MODE_ADMA2, /*!< SDH DMA mode:ADMA2 */\n+} SDH_DMA_Mode_Type;\n+\n+/**\n+ * @brief SDH control flag type definition\n+ */\n+typedef enum {\n+ SDH_CTRL_FLAG_STOP_AT_BLK_GAP, /*!< SDH control flag: stop at block gap */\n+ SDH_CTRL_FLAG_READ_WAIT, /*!< SDH control flag: read wait */\n+ SDH_CTRL_FLAG_INT_AT_BLK_GAP, /*!< SDH control flag: interrupt at block gap */\n+ SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS, /*!< SDH control flag: read done without 8 clks for block gap */\n+ SDH_CTRL_FLAG_EXACT_BLK_NUM_READ, /*!< SDH control flag: Exact block number read */\n+} SDH_Ctrl_Flag_Type;\n+\n+/**\n+ * @brief SDH Command type definition\n+ */\n+typedef enum {\n+ SDH_CMD_NORMAL, /*!< SDH command type:normal */\n+ SDH_CMD_SUSPEND, /*!< SDH command type:suspend */\n+ SDH_CMD_RESUME, /*!< SDH command type:resume */\n+ SDH_CMD_ABORT, /*!< SDH command type:abort */\n+ SDH_CMD_EMPTY, /*!< SDH command type:empty */\n+} SDH_Cmd_Type;\n+\n+/**\n+ * @brief SDH response type definition\n+ */\n+typedef enum {\n+ SDH_RESP_NONE, /*!< SDH response type:none */\n+ SDH_RESP_136LEN,\n+ SDH_RESP_48LEN,\n+ SDH_RESP_48LEN_BUSY,\n+ SDH_RESP_R1, /*!< SDH response type:r1 */\n+ SDH_RESP_R1B, /*!< SDH response type:r1b */\n+ SDH_RESP_R2, /*!< SDH response type:r2 */\n+ SDH_RESP_R3, /*!< SDH response type:r3 */\n+ SDH_RESP_R4, /*!< SDH response type:r4 */\n+ SDH_RESP_R5, /*!< SDH response type:r5 */\n+ SDH_RESP_R5B, /*!< SDH response type:r5b */\n+ SDH_RESP_R6, /*!< SDH response type:r6 */\n+ SDH_RESP_R7, /*!< SDH response type:r7 */\n+} SDH_Resp_Type;\n+\n+/**\n+ * @brief SDH ADMA descriptor chain type definition\n+ */\n+typedef enum {\n+ SDH_ADMA_FLAG_SINGLE_DESC, /*!< SDH transfer a single ADMA descriptor */\n+ SDH_ADMA_FLAG_MULTI_DESC, /*!< SDH create multiple ADMA descriptor within the ADMA table(mmc boot mode) */\n+} SDH_ADMA_Flag_Type;\n+\n+/**\n+ * @brief SDH ADMA1 descriptor flag type definition\n+ */\n+typedef enum {\n+ SDH_ADMA1_DESC_FLAG_VALID = 0X01, /*!< SDH ADMA1 descriptor valid flag */\n+ SDH_ADMA1_DESC_FLAG_END = 0X02, /*!< SDH ADMA1 descriptor end flag */\n+ SDH_ADMA1_DESC_FLAG_INT = 0X04, /*!< SDH ADMA1 descriptor interrupt flag */\n+ SDH_ADMA1_DESC_FLAG_ACTIVE1 = 0X10, /*!< SDH ADMA1 descriptor atcive1 flag */\n+ SDH_ADMA1_DESC_FLAG_ACTIVE2 = 0X20, /*!< SDH ADMA1 descriptor active2 flag */\n+ SDH_ADMA1_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA1 trnasfer descriptor flag\\ */\n+ SDH_ADMA1_DESC_FLAG_LINK = 0x31, /*!< SDH ADMA1 link descriptor flag */\n+ SDH_ADMA1_DESC_FLAG_SETLEN = 0x11, /*!< SDH ADMA1 set length descriptor flag */\n+} SDH_ADMA1_Desc_Flag_Type;\n+\n+/**\n+ * @brief SDH ADMA2 descriptor flag type definition\n+ */\n+typedef enum {\n+ SDH_ADMA2_DESC_FLAG_VALID = 0X01, /*!< SDH ADMA2 descriptor valid flag */\n+ SDH_ADMA2_DESC_FLAG_END = 0X02, /*!< SDH ADMA2 descriptor end flag */\n+ SDH_ADMA2_DESC_FLAG_INT = 0X04, /*!< SDH ADMA2 descriptor interrupt flag */\n+ SDH_ADMA2_DESC_FLAG_ACTIVE1 = 0X10, /*!< SDH ADMA2 descriptor atcive1 flag */\n+ SDH_ADMA2_DESC_FLAG_ACTIVE2 = 0X20, /*!< SDH ADMA2 descriptor active2 flag */\n+ SDH_ADMA2_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA2 trnasfer descriptor flag\\ */\n+ SDH_ADMA2_DESC_FLAG_LINK = 0x31, /*!< SDH ADMA2 link descriptor flag */\n+} SDH_ADMA2_Desc_Flag_Type;\n+\n+/**\n+ * @brief SDH burst length type definition\n+ */\n+typedef enum {\n+ SDH_BUSRT_INCR, /*!< SDH burst length incremental */\n+ SDH_BUSRT_INCR4, /*!< SDH ADMA2 length INCR4 */\n+ SDH_BUSRT_WRAP4, /*!< SDH ADMA2 length Wrap 4 */\n+} SDH_Burst_Type;\n+\n+/**\n+ * @brief SDH FIFO threshold type definition\n+ */\n+typedef enum {\n+ SDH_FIFO_THRESHOLD_64_BYTES, /*!< SDH FIFO threshold is 64 bytes to generate DMA request */\n+ SDH_FIFO_THRESHOLD_128_BYTES, /*!< SDH FIFO threshold is 128 bytes to generate DMA request */\n+ SDH_FIFO_THRESHOLD_192_BYTES, /*!< SDH FIFO threshold is 192 bytes to generate DMA request */\n+ SDH_FIFO_THRESHOLD_256_BYTES, /*!< SDH FIFO threshold is 256 bytes to generate DMA request */\n+} SDH_FIFO_Threshold_Type;\n+\n+/**\n+ * @brief SDH burst length type definition\n+ */\n+typedef enum {\n+ SDH_BURST_SIZE_32_BYTES, /*!< SDH busrt size is 32 bytes */\n+ SDH_BURST_SIZE_64_BYTES, /*!< SDH busrt size is 64 bytes */\n+ SDH_BURST_SIZE_128_BYTES, /*!< SDH busrt size is 128 bytes */\n+ SDH_BURST_SIZE_256_BYTES, /*!< SDH busrt size is 256 bytes */\n+} SDH_Burst_Size_Type;\n+\n+/**\n+ * @brief SDH transferd data type definition\n+ */\n+typedef enum {\n+ SDH_TRANS_DATA_NORMAL, /*!< SDH transfer normal data */\n+ SDH_TRANS_DATA_TUNING, /*!< SDH transfer tuning data */\n+ SDH_TRANS_DATA_BOOT, /*!< SDH transfer boot data */\n+ SDH_TRANS_DATA_BOOT_CONT, /*!< SDH transfer boot data continous */\n+} SDH_Trans_Data_Type;\n+\n+/**\n+ * @brief SDH ADMA2 descriptor structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t attribute; /*!< SDH ADMA2 descriptor attribute */\n+ uint32_t address; /*!< SDH ADMA2 descriptor address pointer */\n+} SDH_ADMA2_Desc_Type;\n+/**\n+ * @brief SDH capability structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t sdVersion; /*!< SDH support SD card/sdio version */\n+ uint32_t mmcVersion; /*!< SDH support emmc card version */\n+ uint32_t maxBlockLength; /*!< SDH maximum block length united as byte */\n+ uint32_t maxBlockCount; /*!< SDH maximum block count can be set one time */\n+ uint32_t flags; /*!< SDH capability flags to indicate the support information */\n+} SDH_Cap_Cfg_Type;\n+\n+/**\n+ * @brief SDH boot config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t ackTimeoutCount; /*!< SDH timeout value for the boot ACK. The available range is 0 ~ 15 */\n+ SDH_Boot_Mode_Type bootMode; /*!< SDH boot mode selection */\n+ uint32_t blockCount; /*!< SDH stop at block gap value of automatic mode. Available range is 0 ~ 65535 */\n+ uint32_t blockSize; /*!< SDH block size */\n+ uint8_t enableBootAck; /*!< SDH enable or disable boot ACK */\n+ uint8_t enableAutoStopAtBlockGap; /*!< SDH enable or disable auto stop at block gap function in boot period */\n+} SDH_Boot_Cfg_Type;\n+\n+/**\n+ * @brief SDH config structure type definition\n+ */\n+typedef struct\n+{\n+ SDH_Speed_Mode_Type speed; /*!< SDH host controller speed */\n+ BL_Fun_Type vlot18Enable; /*!< SDH enable 1.8V */\n+ BL_Fun_Type highSpeed; /*!< SDH enable high speed */\n+ SDH_Data_Bus_Width_Type dataWidth; /*!< SDH data bus width */\n+ SDH_Voltage_Type volt; /*!< SDH voltage */\n+ uint32_t srcClock; /*!< SDH source clock frequency in HZ */\n+ uint32_t busClock; /*!< SDH bus clock frequency in HZ */\n+ uint32_t dataTimeout; /*!< SDH data timeout value */\n+ uint8_t readWatermarkLevel; /*!< SDH watermark level for DMA read operation. Available range is 1 ~ 128. */\n+ uint8_t writeWatermarkLevel; /*!< SDH watermark level for DMA write operation. Available range is 1 ~ 128. */\n+ uint8_t readBurstLen; /*!< SDH read burst len */\n+ uint8_t writeBurstLen; /*!< SDH write burst len */\n+} SDH_Cfg_Type;\n+\n+/**\n+ * @brief SDH config structure type definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type enableAutoCommand12; /*!< SDH enable auto CMD12 */\n+ BL_Fun_Type enableAutoCommand23; /*!< SDH enable auto CMD23 */\n+ BL_Fun_Type enableIgnoreError; /*!< SDH enable to ignore error event to read/write all the data */\n+ SDH_Trans_Data_Type dataType; /*!< SDH this is used to distinguish the normal/tuning/boot data */\n+ uint32_t blockSize; /*!< SDH block size */\n+ uint32_t blockCount; /*!< SDH block count */\n+ uint32_t rxDataLen; /*!< SDH RX data length */\n+ uint32_t *rxData; /*!< SDH buffer to save data read */\n+ const uint32_t *txData; /*!< SDH data buffer to write */\n+ uint32_t txDataLen; /*!< SDH TX data length */\n+} SDH_Data_Cfg_Type;\n+\n+/**\n+ * @brief SDH command config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t index; /*!< SDH command index */\n+ uint32_t argument; /*!< SDH command argument */\n+ SDH_Cmd_Type type; /*!< SDH command type */\n+ SDH_Resp_Type respType; /*!< SDH command response type */\n+ uint32_t response[4U]; /*!< SDH response for this command */\n+ uint32_t flag; /*!< SDH cmd flag */\n+} SDH_CMD_Cfg_Type;\n+\n+/**\n+ * @brief SDH DMA config structure type definition\n+ */\n+typedef struct\n+{\n+ SDH_DMA_Mode_Type dmaMode; /*!< SDH DMA mode */\n+ //SDH_Burst_Type burstType; /*!< SDH burst type config */\n+ SDH_Burst_Size_Type burstSize; /*!< SDH DMA burst size type */\n+ SDH_FIFO_Threshold_Type fifoThreshold; /*!< SDH FIFO threshold */\n+ uint32_t *admaEntries; /*!< SDH ADMA table entries address */\n+ uint32_t maxEntries; /*!< SDH ADMA table entries size */\n+} SDH_DMA_Cfg_Type;\n+\n+/**\n+ * @brief SDH transfer config structure type definition\n+ */\n+typedef struct\n+{\n+ SDH_Data_Cfg_Type *dataCfg; /*!< SDH data config */\n+ SDH_CMD_Cfg_Type *cmdCfg; /*!< SDH command config */\n+} SDH_Trans_Cfg_Type;\n+\n+typedef struct SDH_Handle_Cfg_Tag SDH_Handle_Cfg_Type;\n+\n+/**\n+ * @brief SDH transfer callback function config structure type definition\n+ */\n+typedef struct\n+{\n+ void (*SDH_CallBack_CardInserted)(void *userData); /*!< SDH card inserted occurs when DAT3/CD pin is for card detect */\n+ void (*SDH_CallBack_CardRemoved)(void *userData); /*!< SDH card removed occurs */\n+ void (*SDH_CallBack_SdioInterrupt)(void *userData); /*!< SDH SDIO card interrupt occurs */\n+ void (*SDH_CallBack_BlockGap)(void *userData); /*!< SDH stopped at block gap event */\n+ void (*SDH_CallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData); /*!< SDH transfer complete callback */\n+ void (*SDH_CMDCallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData); /*!< SDH transfer complete callback */\n+ void (*SDH_CallBack_ReTuning)(void *userData); /*!< SDH handle the re-tuning */\n+ void (*SDH_CallBack_Vendor)(void *userData); /*!< SDH handle vendor specified interrupt callback */\n+} SDH_Trans_Callback_Cfg_Type;\n+\n+struct SDH_Handle_Cfg_Tag {\n+ SDH_Data_Cfg_Type *dataCfg; /*!< SDH data config to transfer */\n+ SDH_CMD_Cfg_Type *cmdCfg; /*!< SDH command config to transfer */\n+ uint32_t intFlag; /*!< SDH interrupt flags of last transaction */\n+ SDH_Trans_Callback_Cfg_Type callBack; /*!< SDH callback function */\n+ void *userData; /*!< SDH parameter for transfer complete callback */\n+};\n+\n+/*@} end of group SDH_Public_Types */\n+\n+/** @defgroup SDH_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup SDH_STAT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_STAT_TYPE(type) (((type) == SDH_STAT_SUCCESS) || \\\n+ ((type) == SDH_STAT_BUSY) || \\\n+ ((type) == SDH_STAT_INVLAID_PARA) || \\\n+ ((type) == SDH_STAT_NOT_SUPPORT) || \\\n+ ((type) == SDH_STAT_OUTOF_RANGE) || \\\n+ ((type) == SDH_STAT_PREPARE_DESC) || \\\n+ ((type) == SDH_STAT_SEND_CMD_FAIL) || \\\n+ ((type) == SDH_STAT_SEND_DATA_FAIL) || \\\n+ ((type) == SDH_STAT_RECV_DATA_FAIL) || \\\n+ ((type) == SDH_STAT_DMA_ADDR_NOT_ALIGN) || \\\n+ ((type) == SDH_STAT_RETUNE_REQ) || \\\n+ ((type) == SDH_STAT_TUNE_ERROR))\n+\n+/** @defgroup SDH_CAP_SUPPORT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_CAP_SUPPORT_TYPE(type) (((type) == SDH_CAP_SUPPORT_8BITS) || \\\n+ ((type) == SDH_CAP_SUPPORT_ADMA2) || \\\n+ ((type) == SDH_CAP_SUPPORT_ADMA1) || \\\n+ ((type) == SDH_CAP_SUPPORT_HIGHSPEED) || \\\n+ ((type) == SDH_CAP_SUPPORT_SDMA) || \\\n+ ((type) == SDH_CAP_SUPPORT_SUS_RES) || \\\n+ ((type) == SDH_CAP_SUPPORT_VLT33) || \\\n+ ((type) == SDH_CAP_SUPPORT_VLT30) || \\\n+ ((type) == SDH_CAP_SUPPORT_VLT18) || \\\n+ ((type) == SDH_CAP_SUPPORT_SBUS_64BITS) || \\\n+ ((type) == SDH_CAP_SUPPORT_ASYNC_INT) || \\\n+ ((type) == SDH_CAP_SUPPORT_DDR50) || \\\n+ ((type) == SDH_CAP_SUPPORT_SDR104) || \\\n+ ((type) == SDH_CAP_SUPPORT_SDR50) || \\\n+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_A) || \\\n+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_C) || \\\n+ ((type) == SDH_CAP_SUPPORT_DRV_TYPE_D) || \\\n+ ((type) == SDH_CAP_SUPPORT_SDR50_TUNE))\n+\n+/** @defgroup SDH_WAKEUP_EVENT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_WAKEUP_EVENT_TYPE(type) (((type) == SDH_WAKEUP_EVENT_INT) || \\\n+ ((type) == SDH_WAKEUP_EVENT_INSERT) || \\\n+ ((type) == SDH_WAKEUP_EVENT_REMOVE))\n+\n+/** @defgroup SDH_TRANS_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_TRANS_FLAG_TYPE(type) (((type) == SDH_TRANS_FLAG_EN_DMA) || \\\n+ ((type) == SDH_TRANS_FLAG_EN_BLK_COUNT) || \\\n+ ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD12) || \\\n+ ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD23) || \\\n+ ((type) == SDH_TRANS_FLAG_READ_DATA) || \\\n+ ((type) == SDH_TRANS_FLAG_MULTI_BLK) || \\\n+ ((type) == SDH_TRANS_FLAG_RESP_136BITS) || \\\n+ ((type) == SDH_TRANS_FLAG_RESP_48BITS) || \\\n+ ((type) == SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY) || \\\n+ ((type) == SDH_TRANS_FLAG_EN_CRC_CHECK) || \\\n+ ((type) == SDH_TRANS_FLAG_EN_INDEX_CHECK) || \\\n+ ((type) == SDH_TRANS_FLAG_DATA_PRESENT) || \\\n+ ((type) == SDH_TRANS_FLAG_SUSPEND) || \\\n+ ((type) == SDH_TRANS_FLAG_RESUME) || \\\n+ ((type) == SDH_TRANS_FLAG_ABORT))\n+\n+/** @defgroup SDH_PRESENT_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_PRESENT_FLAG_TYPE(type) (((type) == SDH_PRESENT_FLAG_CMD_INHBIT) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA_INHBIT) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA_LINE_ACTIVE) || \\\n+ ((type) == SDH_PRESENT_FLAG_RETUNE_REQ) || \\\n+ ((type) == SDH_PRESENT_FLAG_TX_ACTIVE) || \\\n+ ((type) == SDH_PRESENT_FLAG_RX_ACTIVE) || \\\n+ ((type) == SDH_PRESENT_FLAG_BUF_WRITE_ENABLE) || \\\n+ ((type) == SDH_PRESENT_FLAG_BUF_READ_ENABLE) || \\\n+ ((type) == SDH_PRESENT_FLAG_CARD_INSERT) || \\\n+ ((type) == SDH_PRESENT_FLAG_CARD_STABLE) || \\\n+ ((type) == SDH_PRESENT_FLAG_CARD_DET) || \\\n+ ((type) == SDH_PRESENT_FLAG_CARD_WP) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA0_LINE_LEVEL) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA1_LINE_LEVEL) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA2_LINE_LEVEL) || \\\n+ ((type) == SDH_PRESENT_FLAG_DATA3_LINE_LEVEL) || \\\n+ ((type) == SDH_PRESENT_FLAG_CMD_LINE_LEVEL))\n+\n+/** @defgroup SDH_INT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_INT_TYPE(type) (((type) == SDH_INT_CMD_COMPLETED) || \\\n+ ((type) == SDH_INT_DATA_COMPLETED) || \\\n+ ((type) == SDH_INT_BLK_GAP_EVENT) || \\\n+ ((type) == SDH_INT_DMA_COMPLETED) || \\\n+ ((type) == SDH_INT_BUFFER_WRITE_READY) || \\\n+ ((type) == SDH_INT_BUFFER_READ_READY) || \\\n+ ((type) == SDH_INT_CARD_INSERT) || \\\n+ ((type) == SDH_INT_CARD_REMOVE) || \\\n+ ((type) == SDH_INT_CARD) || \\\n+ ((type) == SDH_INT_DRIVER_TA) || \\\n+ ((type) == SDH_INT_DRIVER_TB) || \\\n+ ((type) == SDH_INT_DRIVER_TC) || \\\n+ ((type) == SDH_INT_RETUNE_EVENT) || \\\n+ ((type) == SDH_INT_CMD_TIMEOUT) || \\\n+ ((type) == SDH_INT_CMD_CRC_ERROR) || \\\n+ ((type) == SDH_INT_CMD_ENDBIT_ERROR) || \\\n+ ((type) == SDH_INT_CMD_INDEX_ERROR) || \\\n+ ((type) == SDH_INT_DATA_TIMEOUT) || \\\n+ ((type) == SDH_INT_DATA_CRC_ERROR) || \\\n+ ((type) == SDH_INT_DATA_ENDBIT_ERROR) || \\\n+ ((type) == SDH_INT_CURRENT_ERROR) || \\\n+ ((type) == SDH_INT_AUTO_CMD12_ERROR) || \\\n+ ((type) == SDH_INT_DMA_ERROR) || \\\n+ ((type) == SDH_INT_TUNE_ERROR) || \\\n+ ((type) == SDH_INT_SPI_ERROR) || \\\n+ ((type) == SDH_INT_AXI_RESP_ERROR) || \\\n+ ((type) == SDH_INT_CPL_TIMEOUT_ERROR) || \\\n+ ((type) == SDH_INT_CRC_STAT_ERROR) || \\\n+ ((type) == SDH_INT_CMD_ERRORS) || \\\n+ ((type) == SDH_INT_DATA_ERRORS) || \\\n+ ((type) == SDH_INT_ALL))\n+\n+/** @defgroup SDH_BOOT_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SDH_BOOT_MODE_TYPE(type) (((type) == SDH_BOOT_MODE_NORMAL) || \\\n+ ((type) == SDH_BOOT_MODE_ALT))\n+\n+/** @defgroup SDH_AUTO_CMD12_ERR_TYPE\n+ * @{\n+ */\n+#define IS_SDH_AUTO_CMD12_ERR_TYPE(type) (((type) == SDH_AUTO_CMD12_ERR_NOT_EXE) || \\\n+ ((type) == SDH_AUTO_CMD12_ERR_TIMEOUT) || \\\n+ ((type) == SDH_AUTO_CMD12_ERR_ENDBIT) || \\\n+ ((type) == SDH_AUTO_CMD12_ERR_INDEX) || \\\n+ ((type) == SDH_AUTO_CMD12_ERR_CRC) || \\\n+ ((type) == SDH_AUTO_CMD12_ERR_NOT_ISSUE))\n+\n+/** @defgroup SDH_ADMA_ERR_TYPE\n+ * @{\n+ */\n+#define IS_SDH_ADMA_ERR_TYPE(type) (((type) == SDH_ADMA_ERR_LEN_MISMATCH) || \\\n+ ((type) == SDH_ADMA_ERR_DESC_ERROR))\n+\n+/** @defgroup SDH_ADMA_ERR_STAT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_ADMA_ERR_STAT_TYPE(type) (((type) == SDH_ADMA_ERR_STAT_STOP_DMA) || \\\n+ ((type) == SDH_ADMA_ERR_STAT_FETCH_DESC) || \\\n+ ((type) == SDH_ADMA_ERR_STAT_CHANGE_ADDR) || \\\n+ ((type) == SDH_ADMA_ERR_STAT_TRANS_DATA) || \\\n+ ((type) == SDH_ADMA_ERR_STAT_INVALID_LEN) || \\\n+ ((type) == SDH_ADMA_ERR_STAT_INVALID_DESC))\n+\n+/** @defgroup SDH_FORCE_EVENT_TYPE\n+ * @{\n+ */\n+#define IS_SDH_FORCE_EVENT_TYPE(type) (((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE) || \\\n+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT) || \\\n+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE) || \\\n+ ((type) == SDH_FORCE_EVENT_ENDBIT_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_CMD_TIMEOUT) || \\\n+ ((type) == SDH_FORCE_EVENT_CMD_CRC_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_CMD_ENDBIT_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_CMD_INDEX_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_DATA_TIMEOUT) || \\\n+ ((type) == SDH_FORCE_EVENT_DATA_CRC_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_DATA_ENDBIT_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_DATA_INDEX_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_AUTO_CMD12_ERROR) || \\\n+ ((type) == SDH_FORCE_EVENT_CARD_INT) || \\\n+ ((type) == SDH_FORCE_EVENT_DMA_ERROR))\n+\n+/** @defgroup SDH_SPEED_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SDH_SPEED_MODE_TYPE(type) (((type) == SDH_SPEED_MODE_SDR12) || \\\n+ ((type) == SDH_SPEED_MODE_SDR25) || \\\n+ ((type) == SDH_SPEED_MODE_SDR50) || \\\n+ ((type) == SDH_SPEED_MODE_SDR104) || \\\n+ ((type) == SDH_SPEED_MODE_DDR50))\n+\n+/** @defgroup SDH_DATA_BUS_WIDTH_TYPE\n+ * @{\n+ */\n+#define IS_SDH_DATA_BUS_WIDTH_TYPE(type) (((type) == SDH_DATA_BUS_WIDTH_1BIT) || \\\n+ ((type) == SDH_DATA_BUS_WIDTH_4BITS) || \\\n+ ((type) == SDH_DATA_BUS_WIDTH_8BITS))\n+\n+/** @defgroup SDH_VOLTAGE_TYPE\n+ * @{\n+ */\n+#define IS_SDH_VOLTAGE_TYPE(type) (((type) == SDH_VOLTAGE_3P3V) || \\\n+ ((type) == SDH_VOLTAGE_3P0V) || \\\n+ ((type) == SDH_VOLTAGE_1P8V))\n+\n+/** @defgroup SDH_DMA_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SDH_DMA_MODE_TYPE(type) (((type) == SDH_DMA_MODE_SIMPLE) || \\\n+ ((type) == SDH_DMA_MODE_ADMA1) || \\\n+ ((type) == SDH_DMA_MODE_ADMA2))\n+\n+/** @defgroup SDH_CTRL_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_CTRL_FLAG_TYPE(type) (((type) == SDH_CTRL_FLAG_STOP_AT_BLK_GAP) || \\\n+ ((type) == SDH_CTRL_FLAG_READ_WAIT) || \\\n+ ((type) == SDH_CTRL_FLAG_INT_AT_BLK_GAP) || \\\n+ ((type) == SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS) || \\\n+ ((type) == SDH_CTRL_FLAG_EXACT_BLK_NUM_READ))\n+\n+/** @defgroup SDH_CMD_TYPE\n+ * @{\n+ */\n+#define IS_SDH_CMD_TYPE(type) (((type) == SDH_CMD_NORMAL) || \\\n+ ((type) == SDH_CMD_SUSPEND) || \\\n+ ((type) == SDH_CMD_RESUME) || \\\n+ ((type) == SDH_CMD_ABORT) || \\\n+ ((type) == SDH_CMD_EMPTY))\n+\n+/** @defgroup SDH_RESP_TYPE\n+ * @{\n+ */\n+#define IS_SDH_RESP_TYPE(type) (((type) == SDH_RESP_NONE) || \\\n+ ((type) == SDH_RESP_R1) || \\\n+ ((type) == SDH_RESP_R1B) || \\\n+ ((type) == SDH_RESP_R2) || \\\n+ ((type) == SDH_RESP_R3) || \\\n+ ((type) == SDH_RESP_R4) || \\\n+ ((type) == SDH_RESP_R5) || \\\n+ ((type) == SDH_RESP_R5B) || \\\n+ ((type) == SDH_RESP_R6) || \\\n+ ((type) == SDH_RESP_R7))\n+\n+/** @defgroup SDH_ADMA_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_ADMA_FLAG_TYPE(type) (((type) == SDH_ADMA_FLAG_SINGLE_DESC) || \\\n+ ((type) == SDH_ADMA_FLAG_MULTI_DESC))\n+\n+/** @defgroup SDH_ADMA1_DESC_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_ADMA1_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA1_DESC_FLAG_VALID) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_END) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_INT) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE1) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE2) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_TRANSFER) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_LINK) || \\\n+ ((type) == SDH_ADMA1_DESC_FLAG_SETLEN))\n+\n+/** @defgroup SDH_ADMA2_DESC_FLAG_TYPE\n+ * @{\n+ */\n+#define IS_SDH_ADMA2_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA2_DESC_FLAG_VALID) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_END) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_INT) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE1) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE2) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_TRANSFER) || \\\n+ ((type) == SDH_ADMA2_DESC_FLAG_LINK))\n+\n+/** @defgroup SDH_BURST_TYPE\n+ * @{\n+ */\n+#define IS_SDH_BURST_TYPE(type) (((type) == SDH_BUSRT_INCR) || \\\n+ ((type) == SDH_BUSRT_INCR4) || \\\n+ ((type) == SDH_BUSRT_WRAP4))\n+\n+/** @defgroup SDH_FIFO_THRESHOLD_TYPE\n+ * @{\n+ */\n+#define IS_SDH_FIFO_THRESHOLD_TYPE(type) (((type) == SDH_FIFO_THRESHOLD_64_BYTES) || \\\n+ ((type) == SDH_FIFO_THRESHOLD_128_BYTES) || \\\n+ ((type) == SDH_FIFO_THRESHOLD_192_BYTES) || \\\n+ ((type) == SDH_FIFO_THRESHOLD_256_BYTES))\n+\n+/** @defgroup SDH_BURST_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_SDH_BURST_SIZE_TYPE(type) (((type) == SDH_BURST_SIZE_32_BYTES) || \\\n+ ((type) == SDH_BURST_SIZE_64_BYTES) || \\\n+ ((type) == SDH_BURST_SIZE_128_BYTES) || \\\n+ ((type) == SDH_BURST_SIZE_256_BYTES))\n+\n+/** @defgroup SDH_TRANS_DATA_TYPE\n+ * @{\n+ */\n+#define IS_SDH_TRANS_DATA_TYPE(type) (((type) == SDH_TRANS_DATA_NORMAL) || \\\n+ ((type) == SDH_TRANS_DATA_TUNING) || \\\n+ ((type) == SDH_TRANS_DATA_BOOT) || \\\n+ ((type) == SDH_TRANS_DATA_BOOT_CONT))\n+\n+/*@} end of group SDH_Public_Constants */\n+\n+/** @defgroup SDH_Public_Macros\n+ * @{\n+ */\n+/* The alignment size for ADDRESS filed in SDMA */\n+#define SDH_SDMA_ADDRESS_ALIGN (1U)\n+/* The alignment size for LENGTH field in SDMA */\n+#define SDH_SDMA_LENGTH_ALIGN (1U)\n+/* The alignment size for ADDRESS filed in ADMA1's descriptor */\n+#define SDH_ADMA1_ADDRESS_ALIGN (4096U)\n+/* The alignment size for ADDRESS field in ADMA2's descriptor */\n+#define SDH_ADMA2_ADDRESS_ALIGN (1U)\n+/* The alignment size for LENGTH filed in ADMA2's descriptor */\n+#define SDH_ADMA2_LENGTH_ALIGN (1U)\n+/* ADMA1 descriptor table\n+* |------------------------|---------|--------------------------|\n+* | Address/page field |Reserved | Attribute |\n+* |------------------------|---------|--------------------------|\n+* |31 12|11 6|05 |04 |03|02 |01 |00 |\n+* |------------------------|---------|----|----|--|---|---|-----|\n+* | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|\n+* |------------------------|---------|----|----|--|---|---|-----|\n+*\n+*\n+* |------|------|-----------------|-------|-------------|\n+* | Act2 | Act1 | Comment | 31-28 | 27 - 12 |\n+* |------|------|-----------------|---------------------|\n+* | 0 | 0 | No op | Don't care |\n+* |------|------|-----------------|-------|-------------|\n+* | 0 | 1 | Set data length | 0000 | Data Length |\n+* |------|------|-----------------|-------|-------------|\n+* | 1 | 0 | Transfer data | Data address |\n+* |------|------|-----------------|---------------------|\n+* | 1 | 1 | Link descriptor | Descriptor address |\n+* |------|------|-----------------|---------------------|\n+*/\n+/* The bit shift for ADDRESS filed in ADMA1's descriptor */\n+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_POS (12U)\n+/* The bit mask for ADDRESS field in ADMA1's descriptor */\n+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)\n+/* The bit shift for LENGTH filed in ADMA1's descriptor */\n+#define SDH_ADMA1_DESCRIPTOR_LENGTH_POS (12U)\n+/* The mask for LENGTH field in ADMA1's descriptor */\n+#define SDH_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)\n+/* The maximum value of LENGTH filed in ADMA1's descriptor */\n+#define SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA1_DESCRIPTOR_LENGTH_MASK - 511U)\n+/* ADMA2 descriptor table\n+* |----------------|---------------|-------------|--------------------------|\n+* | Address field | Length | Reserved | Attribute |\n+* |----------------|---------------|-------------|--------------------------|\n+* |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |\n+* |----------------|---------------|-------------|----|----|--|---|---|-----|\n+* | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|\n+* |----------------|---------------|-------------|----|----|--|---|---|-----|\n+*\n+*\n+* | Act2 | Act1 | Comment | Operation |\n+* |------|------|-----------------|-------------------------------------------------------------------|\n+* | 0 | 0 | No op | Don't care |\n+* |------|------|-----------------|-------------------------------------------------------------------|\n+* | 0 | 1 | Reserved | Read this line and go to next one |\n+* |------|------|-----------------|-------------------------------------------------------------------|\n+* | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |\n+* |------|------|-----------------|-------------------------------------------------------------------|\n+* | 1 | 1 | Link descriptor | Link to another descriptor |\n+* |------|------|-----------------|-------------------------------------------------------------------|\n+*/\n+/* The bit shift for LENGTH field in ADMA2's descriptor */\n+#define SDH_ADMA2_DESCRIPTOR_LENGTH_POS (16U)\n+/* The bit mask for LENGTH field in ADMA2's descriptor */\n+#define SDH_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)\n+/* The maximum value of LENGTH field in ADMA2's descriptor */\n+#define SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA2_DESCRIPTOR_LENGTH_MASK - 511U)\n+#define SDH_EnableIntStatus(mask) \\\n+ do { \\\n+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN, \\\n+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) | (mask)); \\\n+ } while (0)\n+#define SDH_DisableIntStatus(mask) \\\n+ do { \\\n+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN, \\\n+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) & (~(mask))); \\\n+ } while (0)\n+#define SDH_EnableIntSource(mask) \\\n+ do { \\\n+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN, \\\n+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) | (mask)); \\\n+ } while (0)\n+#define SDH_DisableIntSource(mask) \\\n+ do { \\\n+ BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN, \\\n+ BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) & (~(mask))); \\\n+ } while (0)\n+#define SDH_GetIntStatus() BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS);\n+#define SDH_GetIntEnableStatus() BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN);\n+#define SDH_ClearIntStatus(mask) BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS, (mask));\n+#define SDH_AutoCmd12ErrStatus() BL_RD_SHORT(SDH_BASE + SDH_SD_AUTO_CMD12_ERROR_STATUS_OFFSET);\n+#define SDH_GetDMAErrStatus() BL_RD_SHORT(SDH_BASE + SDH_SD_ADMA_ERROR_STATUS_OFFSET);\n+#define SDH_GetPresentStatus() BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);\n+#define SDH_MAX_BLOCK_COUNT 0xffff\n+//#define SDH_CMD_INDEX(x) (x)\n+\n+/*@} end of group SDH_Public_Macros */\n+\n+/** @defgroup SDH_Public_Functions\n+ * @{\n+ */\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+void SDH_MMC1_IRQHandler(void);\n+#endif\n+void SDH_Reset(void);\n+void SDH_Set_Timeout(uint8_t tmo);\n+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);\n+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState);\n+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg);\n+void SDH_Powon(void);\n+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd);\n+void SDH_DisableDMA(void);\n+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);\n+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd);\n+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg);\n+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd);\n+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg);\n+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA);\n+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);\n+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);\n+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle, const SDH_Trans_Callback_Cfg_Type *callBack, void *userData);\n+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode);\n+void SDH_EnableStatus(void);\n+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg);\n+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg);\n+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg);\n+void SDH_DisableSdClock(void);\n+void SDH_Deinit(void);\n+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability);\n+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,\n+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);\n+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,\n+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);\n+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23);\n+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag);\n+/*@} end of group SDH_Public_Functions */\n+\n+/*@} end of group SDH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SDH_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..099764d1348dfb3a548e736fd300e5a0cce4f04b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h\n@@ -0,0 +1,83 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sec_dbg.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SEC_DBG_H__\n+#define __BL808_SEC_DBG_H__\n+\n+#include \"sec_dbg_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_DBG\n+ * @{\n+ */\n+\n+/** @defgroup SEC_DBG_Public_Types\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Public_Types */\n+\n+/** @defgroup SEC_DBG_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Public_Constants */\n+\n+/** @defgroup SEC_DBG_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Public_Macros */\n+\n+/** @defgroup SEC_DBG_Public_Functions\n+ * @{\n+ */\n+void Sec_Dbg_Read_Chip_ID(uint8_t id[8]);\n+void Sec_Dbg_Set_Dbg_Pwd(const uint32_t pwd[4]);\n+uint32_t Sec_Dbg_Read_Dbg_Mode(void);\n+uint32_t Sec_Dbg_Read_Dbg_Enable(void);\n+void Sec_Dbg_Set_Dbg_Trigger(void);\n+\n+/*@} end of group SEC_DBG_Public_Functions */\n+\n+/*@} end of group SEC_DBG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SEC_DBG_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..101c8890489a97e13f740e2b68bb80acf80fd6c5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h\n@@ -0,0 +1,778 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sec_eng.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SEC_ENG_H__\n+#define __BL808_SEC_ENG_H__\n+\n+#include \"sec_eng_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_ENG\n+ * @{\n+ */\n+\n+/** @defgroup SEC_ENG_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief AES port type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_ID0, /*!< AES0 port define */\n+} SEC_ENG_AES_ID_Type;\n+\n+/**\n+ * @brief SHA port type definition\n+ */\n+typedef enum {\n+ SEC_ENG_SHA_ID0, /*!< SHA0 port define */\n+} SEC_ENG_SHA_ID_Type;\n+\n+/**\n+ * @brief SHA type definition\n+ */\n+typedef enum {\n+ SEC_ENG_SHA256, /*!< SHA type:SHA256 */\n+ SEC_ENG_SHA224, /*!< SHA type:SHA224 */\n+ SEC_ENG_SHA1, /*!< SHA type:SHA1 */\n+ SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */\n+ SEC_ENG_SHA512, /*!< SHA type:SHA512 */\n+ SEC_ENG_SHA384, /*!< SHA type:SHA384 */\n+ SEC_ENG_SHA512T224, /*!< SHA type:SHA512T224 */\n+ SEC_ENG_SHA512T256, /*!< SHA type:SHA512T156 */\n+ SEC_ENG_MD5, /*!< MD5 */\n+ SEC_ENG_CRC16, /*!< CRC-16 */\n+ SEC_ENG_CRC32, /*!< CRC-32 */\n+} SEC_ENG_SHA_Type;\n+\n+/**\n+ * @brief AES type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_ECB, /*!< AES mode type:ECB */\n+ SEC_ENG_AES_CTR, /*!< AES mode type:CTR */\n+ SEC_ENG_AES_CBC, /*!< AES mode type:CBC */\n+ SEC_ENG_AES_XTS, /*!< AES mode type:XTS */\n+} SEC_ENG_AES_Type;\n+\n+/**\n+ * @brief AES XTS mode type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_XTS_MODE1, /*!< AES xts mode type:mode1 */\n+ SEC_ENG_AES_XTS_MODE2, /*!< AES xts mode type:mode2 */\n+} SEC_ENG_AES_XTS_MODE_Type;\n+\n+/**\n+ * @brief AES KEY type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */\n+ SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */\n+ SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */\n+ SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */\n+} SEC_ENG_AES_Key_Type;\n+\n+/**\n+ * @brief AES CTR mode counter type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */\n+ SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */\n+ SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */\n+ SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */\n+} SEC_ENG_AES_Counter_Type;\n+\n+/**\n+ * @brief AES use new or old value type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_USE_NEW, /*!< Use new value */\n+ SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */\n+} SEC_ENG_AES_ValueUsed_Type;\n+\n+/**\n+ * @brief AES KEY source type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */\n+ SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */\n+} SEC_ENG_AES_Key_Src_Type;\n+\n+/**\n+ * @brief AES KEY source type definition\n+ */\n+typedef enum {\n+ SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */\n+ SEC_ENG_AES_DECRYPTION, /*!< AES decryption */\n+} SEC_ENG_AES_EnDec_Type;\n+\n+/**\n+ * @brief AES PKA register size type definition\n+ */\n+typedef enum {\n+ SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is 8 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */\n+ SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */\n+} SEC_ENG_PKA_REG_SIZE_Type;\n+\n+/**\n+ * @brief AES PKA register size type definition\n+ */\n+typedef enum {\n+ SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MOD2N = 0x11, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LDIV2N = 0x12, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LMUL2N = 0x13, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LDIV = 0x14, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LSQR = 0x15, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LMUL = 0x16, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LSUB = 0x17, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LADD = 0x18, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_LCMP = 0x19, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MDIV2 = 0x21, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MINV = 0x22, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MEXP = 0x23, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MSQR = 0x24, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MMUL = 0x25, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MREM = 0x26, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MSUB = 0x27, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MADD = 0x28, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_RESIZE = 0x31, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_MOVDAT = 0x32, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_NLIR = 0x33, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_SLIR = 0x34, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_CLIR = 0x35, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38, /*!< PKA operation type */\n+ SEC_ENG_PKA_OP_CTLIR_PLD = 0x39, /*!< PKA operation type */\n+} SEC_ENG_PKA_OP_Type;\n+\n+/**\n+ * @brief Sec Eng Interrupt Type Def\n+ */\n+typedef enum {\n+ SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */\n+ SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */\n+ SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */\n+ SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */\n+ SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */\n+ SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */\n+ SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */\n+} SEC_ENG_INT_Type;\n+\n+/**\n+ * @brief SEC_ENG SHA256 context\n+ */\n+typedef struct\n+{\n+ uint32_t total[2]; /*!< Number of bytes processed */\n+ uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */\n+ uint32_t *shaPadding; /*!< Padding data */\n+ uint8_t shaFeed; /*!< Sha has feed data */\n+} SEC_Eng_SHA256_Ctx;\n+\n+/**\n+ * @brief SEC_ENG SHA512 context\n+ */\n+typedef struct\n+{\n+ uint64_t total[2]; /*!< Number of bytes processed */\n+ uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */\n+ uint64_t *shaPadding; /*!< Padding data */\n+ uint8_t shaFeed; /*!< Sha has feed data */\n+} SEC_Eng_SHA512_Ctx;\n+\n+/**\n+ * @brief SEC_ENG MD5 context\n+ */\n+typedef struct\n+{\n+ uint32_t total[2]; /*!< Number of bytes processed */\n+ uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */\n+ uint32_t *md5Padding; /*!< Padding data */\n+ uint8_t md5Feed; /*!< md5 has feed data */\n+} SEC_Eng_MD5_Ctx;\n+\n+/**\n+ * @brief SEC_ENG SHA256 link mode context\n+ */\n+typedef struct\n+{\n+ uint32_t total[2]; /*!< Number of bytes processed */\n+ uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */\n+ uint32_t *shaPadding; /*!< Padding data */\n+ uint32_t linkAddr; /*!< Link configure address */\n+} SEC_Eng_SHA256_Link_Ctx;\n+\n+/**\n+ * @brief SEC_ENG MD5 link mode context\n+ */\n+typedef struct\n+{\n+ uint64_t total[2]; /*!< Number of bytes processed */\n+ uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */\n+ uint64_t *shaPadding; /*!< Padding data */\n+ uint32_t linkAddr; /*!< Link configure address */\n+} SEC_Eng_SHA512_Link_Ctx;\n+\n+/**\n+ * @brief SEC_ENG SHA256 link mode context\n+ */\n+typedef struct\n+{\n+ uint32_t total[2]; /*!< Number of bytes processed */\n+ uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */\n+ uint32_t *md5Padding; /*!< Padding data */\n+ uint32_t linkAddr; /*!< Link configure address */\n+} SEC_Eng_MD5_Link_Ctx;\n+\n+/**\n+ * @brief SEC_ENG AES context\n+ */\n+typedef struct\n+{\n+ uint8_t aesFeed; /*!< AES has feed data */\n+ SEC_ENG_AES_Type mode; /*!< AES mode */\n+} SEC_Eng_AES_Ctx;\n+\n+/**\n+ * @brief SEC_ENG SHA link config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t : 2; /*!< [1:0]Reserved */\n+ uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */\n+ uint32_t : 1; /*!< [5]Reserved */\n+ uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */\n+ uint32_t : 2; /*!< [8:7]Reserved */\n+ uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */\n+ uint32_t shaIntSet : 1; /*!< [10]Set interrupt */\n+ uint32_t : 1; /*!< [11]Reserved */\n+ uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */\n+ uint32_t : 2; /*!< [15:14]Reserved */\n+ uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */\n+ uint32_t shaSrcAddr; /*!< Message source address */\n+ uint32_t result[16]; /*!< Result of SHA */\n+} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type;\n+\n+/**\n+ * @brief SEC_ENG SHA link config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t : 2; /*!< [1:0]Reserved */\n+ uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */\n+ uint32_t : 1; /*!< [5]Reserved */\n+ uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */\n+ uint32_t : 2; /*!< [8:7]Reserved */\n+ uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */\n+ uint32_t shaIntSet : 1; /*!< [10]Set interrupt */\n+ uint32_t : 1; /*!< [11]Reserved */\n+ uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */\n+ uint32_t : 2; /*!< [15:14]Reserved */\n+ uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */\n+ uint32_t shaSrcAddr; /*!< Message source address */\n+ uint32_t poly; /*!< poly of CRC */\n+ uint32_t dout_inv : 1; /*!< [0]dout inv of CRC */\n+ uint32_t dout_ref : 1; /*!< [1]dout ref of CRC */\n+ uint32_t din_ref : 1; /*!< [2]din ref of CRC */\n+ uint32_t : 29; /*!< [31:3]Reserved */\n+ uint32_t ivAndHash; /*!< CRC hash and also used as iv in 1st block */\n+} __attribute__((aligned(4))) SEC_Eng_CRC_Link_Config_Type;\n+\n+/**\n+ * @brief SEC_ENG AES link config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t : 3; /*!< [2:0]Reserved */\n+ uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */\n+ uint32_t aesDecEn : 1; /*!< [5]Encode or decode */\n+ uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */\n+ uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */\n+ uint32_t : 1; /*!< [8]Reserved */\n+ uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */\n+ uint32_t aesIntSet : 1; /*!< [10]Set interrupt */\n+ uint32_t : 1; /*!< [11]Reserved */\n+ uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */\n+ uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */\n+ uint32_t aesXTS : 1; /*!< [15]XTS mode select */\n+ uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */\n+ uint32_t aesSrcAddr; /*!< Message source address */\n+ uint32_t aesDstAddr; /*!< Message destination address */\n+ uint32_t aesIV0; /*!< Big endian initial vector(MSB) */\n+ uint32_t aesIV1; /*!< Big endian initial vector */\n+ uint32_t aesIV2; /*!< Big endian initial vector */\n+ uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */\n+ uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */\n+ uint32_t aesKey1; /*!< Big endian aes key */\n+ uint32_t aesKey2; /*!< Big endian aes key */\n+ uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */\n+ uint32_t aesKey4; /*!< Big endian aes key */\n+ uint32_t aesKey5; /*!< Big endian aes key */\n+ uint32_t aesKey6; /*!< Big endian aes key */\n+ uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */\n+} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type;\n+\n+/**\n+ * @brief SEC_ENG AES XTS mode1 link config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t : 3; /*!< [2:0]Reserved */\n+ uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */\n+ uint32_t aesDecEn : 1; /*!< [5]Encode or decode */\n+ uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */\n+ uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */\n+ uint32_t : 1; /*!< [8]Reserved */\n+ uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */\n+ uint32_t aesIntSet : 1; /*!< [10]Set interrupt */\n+ uint32_t : 1; /*!< [11]Reserved */\n+ uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */\n+ uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */\n+ uint32_t aesXTS : 1; /*!< [15]XTS mode select */\n+ uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */\n+ uint32_t aesSrcAddr; /*!< Message source address */\n+ uint32_t aesDstAddr; /*!< Message destination address */\n+ uint32_t aesIV0; /*!< Big endian initial vector(MSB) */\n+ uint32_t aesIV1; /*!< Big endian initial vector */\n+ uint32_t aesIV2; /*!< Big endian initial vector */\n+ uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */\n+ uint32_t aesKey10; /*!< Big endian aes key1(aes-128/256 key MSB) */\n+ uint32_t aesKey11; /*!< Big endian aes key1 */\n+ uint32_t aesKey12; /*!< Big endian aes key1 */\n+ uint32_t aesKey13; /*!< Big endian aes key1(aes-128 key LSB) */\n+ uint32_t aesKey14; /*!< Big endian aes key1 */\n+ uint32_t aesKey15; /*!< Big endian aes key1 */\n+ uint32_t aesKey16; /*!< Big endian aes key1 */\n+ uint32_t aesKey17; /*!< Big endian aes key1(aes-256 key LSB) */\n+ uint32_t : 16; /*!< [15:0]Reserved */\n+ uint32_t aesUnitLen : 16; /*!< [31:16]Big endian aes unit len */\n+ uint32_t aesKey20; /*!< Big endian aes key2(aes-128/256 key MSB) */\n+ uint32_t aesKey21; /*!< Big endian aes key2 */\n+ uint32_t aesKey22; /*!< Big endian aes key2 */\n+ uint32_t aesKey23; /*!< Big endian aes key2(aes-128 key LSB) */\n+ uint32_t aesKey24; /*!< Big endian aes key2 */\n+ uint32_t aesKey25; /*!< Big endian aes key2 */\n+ uint32_t aesKey26; /*!< Big endian aes key2 */\n+ uint32_t aesKey27; /*!< Big endian aes key2(aes-256 key LSB) */\n+} __attribute__((aligned(4))) SEC_Eng_AES_XTS_Mode1_Link_Config_Type;\n+\n+/**\n+ * @brief SEC_ENG GMAC link config structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t : 9; /*!< [8:0]reserved */\n+ uint32_t gmacIntClr : 1; /*!< [9]Clear interrupt */\n+ uint32_t gmacIntSet : 1; /*!< [10]Set interrupt */\n+ uint32_t : 5; /*!< [15:11]reserved */\n+ uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */\n+ uint32_t gmacSrcAddr; /*!< Message source address */\n+ uint32_t gmacKey0; /*!< GMAC key */\n+ uint32_t gmacKey1; /*!< GMAC key */\n+ uint32_t gmacKey2; /*!< GMAC key */\n+ uint32_t gmacKey3; /*!< GMAC key */\n+ uint32_t result[4]; /*!< Result of GMAC */\n+} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type;\n+\n+/**\n+ * @brief SEC_ENG PKA status type definition\n+ */\n+typedef struct\n+{\n+ uint16_t primeFail : 1; /*!< [0]Prime fail */\n+ uint16_t errUnknown : 1; /*!< [1]Err unknown opc */\n+ uint16_t errOverflow : 1; /*!< [2]Err opq overflow */\n+ uint16_t errSrc2 : 1; /*!< [3]Err invalid src2 */\n+ uint16_t errSrc1 : 1; /*!< [4]Err invalid src1 */\n+ uint16_t errSrc0 : 1; /*!< [5]Err invalid src0 */\n+ uint16_t errDiv0 : 1; /*!< [6]Err div by 0 */\n+ uint16_t errFull : 1; /*!< [7]Err cam full */\n+ uint16_t lastOpc : 1; /*!< [8]Last opc */\n+ uint16_t opqFull : 1; /*!< [9]Opq full */\n+ uint16_t cmdIndex : 5; /*!< [14:10]Cmd err index */\n+ uint16_t errCmd : 1; /*!< [15]Err cmd */\n+} SEC_Eng_PKA_Status_Type;\n+\n+/*@} end of group SEC_ENG_Public_Types */\n+\n+/** @defgroup SEC_ENG_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup SEC_ENG_AES_ID_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0))\n+\n+/** @defgroup SEC_ENG_SHA_ID_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0))\n+\n+/** @defgroup SEC_ENG_SHA_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \\\n+ ((type) == SEC_ENG_SHA224) || \\\n+ ((type) == SEC_ENG_SHA1) || \\\n+ ((type) == SEC_ENG_SHA1_RSVD) || \\\n+ ((type) == SEC_ENG_SHA512) || \\\n+ ((type) == SEC_ENG_SHA384) || \\\n+ ((type) == SEC_ENG_SHA512T224) || \\\n+ ((type) == SEC_ENG_SHA512T256) || \\\n+ ((type) == SEC_ENG_MD5) || \\\n+ ((type) == SEC_ENG_CRC16) || \\\n+ ((type) == SEC_ENG_CRC32))\n+\n+/** @defgroup SEC_ENG_AES_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \\\n+ ((type) == SEC_ENG_AES_CTR) || \\\n+ ((type) == SEC_ENG_AES_CBC) || \\\n+ ((type) == SEC_ENG_AES_XTS))\n+\n+/** @defgroup SEC_ENG_AES_XTS_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_XTS_MODE_TYPE(type) (((type) == SEC_ENG_AES_XTS_MODE1) || \\\n+ ((type) == SEC_ENG_AES_XTS_MODE2))\n+\n+/** @defgroup SEC_ENG_AES_KEY_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \\\n+ ((type) == SEC_ENG_AES_KEY_256BITS) || \\\n+ ((type) == SEC_ENG_AES_KEY_192BITS) || \\\n+ ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS))\n+\n+/** @defgroup SEC_ENG_AES_COUNTER_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \\\n+ ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \\\n+ ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \\\n+ ((type) == SEC_ENG_AES_COUNTER_BYTE_3))\n+\n+/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \\\n+ ((type) == SEC_ENG_AES_USE_OLD))\n+\n+/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \\\n+ ((type) == SEC_ENG_AES_KEY_HW))\n+\n+/** @defgroup SEC_ENG_AES_ENDEC_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \\\n+ ((type) == SEC_ENG_AES_DECRYPTION))\n+\n+/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_16) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_32) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_64) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_96) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_128) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_192) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_256) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_384) || \\\n+ ((type) == SEC_ENG_PKA_REG_SIZE_512))\n+\n+/** @defgroup SEC_ENG_PKA_OP_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \\\n+ ((type) == SEC_ENG_PKA_OP_MOD2N) || \\\n+ ((type) == SEC_ENG_PKA_OP_LDIV2N) || \\\n+ ((type) == SEC_ENG_PKA_OP_LMUL2N) || \\\n+ ((type) == SEC_ENG_PKA_OP_LDIV) || \\\n+ ((type) == SEC_ENG_PKA_OP_LSQR) || \\\n+ ((type) == SEC_ENG_PKA_OP_LMUL) || \\\n+ ((type) == SEC_ENG_PKA_OP_LSUB) || \\\n+ ((type) == SEC_ENG_PKA_OP_LADD) || \\\n+ ((type) == SEC_ENG_PKA_OP_LCMP) || \\\n+ ((type) == SEC_ENG_PKA_OP_MDIV2) || \\\n+ ((type) == SEC_ENG_PKA_OP_MINV) || \\\n+ ((type) == SEC_ENG_PKA_OP_MEXP) || \\\n+ ((type) == SEC_ENG_PKA_OP_MSQR) || \\\n+ ((type) == SEC_ENG_PKA_OP_MMUL) || \\\n+ ((type) == SEC_ENG_PKA_OP_MREM) || \\\n+ ((type) == SEC_ENG_PKA_OP_MSUB) || \\\n+ ((type) == SEC_ENG_PKA_OP_MADD) || \\\n+ ((type) == SEC_ENG_PKA_OP_RESIZE) || \\\n+ ((type) == SEC_ENG_PKA_OP_MOVDAT) || \\\n+ ((type) == SEC_ENG_PKA_OP_NLIR) || \\\n+ ((type) == SEC_ENG_PKA_OP_SLIR) || \\\n+ ((type) == SEC_ENG_PKA_OP_CLIR) || \\\n+ ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \\\n+ ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \\\n+ ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \\\n+ ((type) == SEC_ENG_PKA_OP_CTLIR_PLD))\n+\n+/** @defgroup SEC_ENG_INT_TYPE\n+ * @{\n+ */\n+#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \\\n+ ((type) == SEC_ENG_INT_AES) || \\\n+ ((type) == SEC_ENG_INT_SHA) || \\\n+ ((type) == SEC_ENG_INT_PKA) || \\\n+ ((type) == SEC_ENG_INT_CDET) || \\\n+ ((type) == SEC_ENG_INT_GMAC) || \\\n+ ((type) == SEC_ENG_INT_ALL))\n+\n+/*@} end of group SEC_ENG_Public_Constants */\n+\n+/** @defgroup SEC_ENG_Public_Macros\n+ * @{\n+ */\n+#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24\n+#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000\n+\n+/*@} end of group SEC_ENG_Public_Macros */\n+\n+/** @defgroup SEC_ENG_Public_Functions\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEC_GMAC_IRQHandler(void);\n+void SEC_CDET_IRQHandler(void);\n+void SEC_TRNG_IRQHandler(void);\n+void SEC_PKA_IRQHandler(void);\n+void SEC_AES_IRQHandler(void);\n+void SEC_SHA_IRQHandler(void);\n+#endif\n+void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType,\n+ uint32_t shaTmpBuf[16], uint32_t padding[16]);\n+void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType,\n+ uint64_t shaTmpBuf[16], uint64_t padding[16]);\n+void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType,\n+ uint32_t md5TmpBuf[16], uint32_t padding[16]);\n+void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo);\n+BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input,\n+ uint32_t len);\n+BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input,\n+ uint64_t len);\n+BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input,\n+ uint32_t len);\n+BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);\n+BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);\n+BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);\n+void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo);\n+void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo);\n+void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr,\n+ uint32_t shaTmpBuf[16], uint32_t padding[16]);\n+void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr,\n+ uint64_t shaTmpBuf[16], uint64_t padding[16]);\n+void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr,\n+ uint32_t md5TmpBuf[16], uint32_t padding[16]);\n+void Sec_Eng_Set_MD5_Din(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_Set_MD5_Din_Be(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_Set_MD5_Dout(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_Set_MD5_Dout_BE(SEC_ENG_AES_ID_Type aesNo);\n+BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,\n+ const uint8_t *input, uint32_t len);\n+BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,\n+ const uint8_t *input, uint64_t len);\n+BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo,\n+ const uint8_t *input, uint32_t len);\n+BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,\n+ uint8_t *hash);\n+BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo,\n+ uint8_t *hash);\n+BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo,\n+ uint8_t *hash);\n+BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void);\n+BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void);\n+BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType,\n+ SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType);\n+void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo);\n+void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo);\n+BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len,\n+ uint8_t *out);\n+BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len,\n+ uint8_t *out);\n+BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len,\n+ uint8_t *out);\n+void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src);\n+void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key,\n+ const uint8_t *iv);\n+void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key,\n+ const uint8_t *iv);\n+void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType);\n+BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len,\n+ uint8_t *out);\n+BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo);\n+BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void);\n+BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void);\n+BL_Err_Type Sec_Eng_Trng_Enable(void);\n+void Sec_Eng_Trng_Int_Enable(void);\n+void Sec_Eng_Trng_Int_Disable(void);\n+BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]);\n+BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len);\n+void Sec_Eng_Trng_Int_Read_Trigger(void);\n+void Sec_Eng_Trng_Int_Read(uint8_t data[32]);\n+void Sec_Eng_Trng_Disable(void);\n+BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void);\n+BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void);\n+void Sec_Eng_PKA_Reset(void);\n+void Sec_Eng_PKA_BigEndian_Enable(void);\n+void Sec_Eng_PKA_LittleEndian_Enable(void);\n+void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status);\n+void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size,\n+ uint8_t lastOp);\n+void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize);\n+void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp);\n+void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp);\n+void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType,\n+ uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType,\n+ uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType,\n+ uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType,\n+ uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx);\n+void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType,\n+ uint8_t s1RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType,\n+ uint8_t s2RegIdx, uint8_t lastOp);\n+void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift,\n+ uint8_t lastOp);\n+void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift,\n+ uint8_t lastOp);\n+void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift,\n+ uint8_t lastOp);\n+void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size,\n+ uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx);\n+void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType,\n+ uint8_t invrRegIdx,\n+ uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx);\n+BL_Err_Type Sec_Eng_Group0_Request_PKA_Access(void);\n+BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void);\n+void Sec_Eng_GMAC_Enable_LE(void);\n+void Sec_Eng_GMAC_Enable_BE(void);\n+void Sec_Eng_GMAC_Enable_Link(void);\n+void Sec_Eng_GMAC_Disable_Link(void);\n+BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out);\n+BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void);\n+BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void);\n+BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void);\n+void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask);\n+void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType);\n+void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun);\n+BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType);\n+/*----------*/\n+void SEC_Eng_Turn_On_Sec_Ring(void);\n+void SEC_Eng_Turn_Off_Sec_Ring(void);\n+void Sec_Eng_PKA_Clear_Int(void);\n+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len);\n+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len);\n+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len);\n+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len);\n+/*----------*/;\n+\n+/*@} end of group SEC_ENG_Public_Functions */\n+\n+/*@} end of group SEC_ENG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SEC_ENG_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ee315f7f9808f2031ed195b98ee1a15e0afb0c92\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h\n@@ -0,0 +1,106 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_cfg.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SF_CFG_H__\n+#define __BL808_SF_CFG_H__\n+\n+#include \"string.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_glb_gpio.h\"\n+#include \"bl808_sflash.h\"\n+#include \"bl808_sf_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CFG\n+ * @{\n+ */\n+\n+/** @defgroup SF_CFG_Public_Types\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_Public_Types */\n+\n+/** @defgroup SF_CFG_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_Public_Constants */\n+\n+/** @defgroup SF_CFG_Public_Macros\n+ * @{\n+ */\n+/* Flash option sf2 */\n+/* Flash CLK */\n+#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_34\n+/* FLASH CS */\n+#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_35\n+/* FLASH DATA */\n+#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_36\n+#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_37\n+#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_38\n+#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_39\n+#define BFLB_FLASH_ID_VALID_FLAG 0x80000000\n+#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF\n+\n+/*@} end of group SF_CFG_Public_Macros */\n+\n+/** @defgroup SF_CFG_Public_Functions\n+ * @{\n+ */\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault);\n+BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);\n+BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);\n+uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,\n+ SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);\n+uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,\n+ SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);\n+BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);\n+\n+/*@} end of group SF_CFG_Public_Functions */\n+\n+/*@} end of group SF_CFG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SF_CFG_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..187024d224d11a2b91883c266f10877969da9eef\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h\n@@ -0,0 +1,82 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_cfg_ext.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SF_CFG_EXT_H__\n+#define __BL808_SF_CFG_EXT_H__\n+\n+#include \"string.h\"\n+#include \"bl808_sflash.h\"\n+#include \"bl808_sf_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CFG_EXT\n+ * @{\n+ */\n+\n+/** @defgroup SF_CFG_EXT_Public_Types\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_EXT_Public_Types */\n+\n+/** @defgroup SF_CFG_EXT_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_EXT_Public_Constants */\n+\n+/** @defgroup SF_CFG_EXT_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_EXT_Public_Macros */\n+\n+/** @defgroup SF_CFG_EXT_Public_Functions\n+ * @{\n+ */\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);\n+uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,\n+ SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);\n+\n+/*@} end of group SF_CFG_EXT_Public_Functions */\n+\n+/*@} end of group SF_CFG_EXT */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SF_CFG_EXT_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..eea942a1e6c3e12f4e45ff93d20e8be1b1341caf\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h\n@@ -0,0 +1,470 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_ctrl.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SF_CTRL_H__\n+#define __BL808_SF_CTRL_H__\n+\n+#include \"sf_ctrl_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup SF_CTRL_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief Serial flash pad type definition\n+ */\n+typedef enum {\n+ SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */\n+ SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */\n+ SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */\n+} SF_Ctrl_Pad_Type;\n+\n+/**\n+ * @brief Serial flash config pin select type definition\n+ */\n+typedef enum {\n+ SF_IO_EMB_SWAP_IO0_IO3 = 0x0, /*!< SF select embedded flash swap io0 with io3 */\n+ SF_IO_EMB_SWAP_DUAL_IO0_IO3 = 0x1, /*!< SF select embedded flash swap dual io0 with io3 */\n+ SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */\n+ SF_IO_EMB_SWAP_NONE_DUAL_IO0 = 0x3, /*!< SF select embedded flash no swap and use dual io0 */\n+ SF_IO_EXT_SF2 = 0x4, /*!< SF select external flash SF2 use gpio34-39 */\n+ SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 = 0x14, /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */\n+ SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 = 0x15, /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */\n+ SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 = 0x16, /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */\n+ SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 = 0x17, /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */\n+} SF_Ctrl_Pin_Select;\n+\n+/**\n+ * @brief Serial flash select bank control type definition\n+ */\n+typedef enum {\n+ SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */\n+ SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */\n+} SF_Ctrl_Bank_Select;\n+\n+/**\n+ * @brief Serial flash controller wrap mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */\n+ SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */\n+ SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */\n+ SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */\n+} SF_Ctrl_Wrap_Mode;\n+\n+/**\n+ * @brief Serail flash controller wrap mode len type definition\n+ */\n+typedef enum {\n+ SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */\n+ SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */\n+ SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */\n+ SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */\n+ SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */\n+ SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */\n+ SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */\n+ SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */\n+ SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */\n+ SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */\n+} SF_Ctrl_Wrap_Len_Type;\n+\n+/**\n+ * @brief Serail flash controller memory remap type define\n+ */\n+typedef enum {\n+ SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */\n+ SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */\n+ SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */\n+ SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */\n+} SF_Ctrl_Remap_Type;\n+\n+/**\n+ * @brief Serial flash controller owner type definition\n+ */\n+typedef enum {\n+ SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */\n+ SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */\n+} SF_Ctrl_Owner_Type;\n+\n+/**\n+ * @brief Read and write type definition\n+ */\n+typedef enum {\n+ SF_CTRL_READ, /*!< Serail flash read command flag */\n+ SF_CTRL_WRITE, /*!< Serail flash write command flag */\n+} SF_Ctrl_RW_Type;\n+\n+/**\n+ * @brief Serail flash interface IO type definition\n+ */\n+typedef enum {\n+ SF_CTRL_NIO_MODE, /*!< Normal IO mode define */\n+ SF_CTRL_DO_MODE, /*!< Dual Output mode define */\n+ SF_CTRL_QO_MODE, /*!< Quad Output mode define */\n+ SF_CTRL_DIO_MODE, /*!< Dual IO mode define */\n+ SF_CTRL_QIO_MODE, /*!< Quad IO mode define */\n+} SF_Ctrl_IO_Type;\n+\n+/**\n+ * @brief Serail flash controller interface mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_SPI_MODE, /*!< SPI mode define */\n+ SF_CTRL_QPI_MODE, /*!< QPI mode define */\n+} SF_Ctrl_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller command mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */\n+ SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */\n+} SF_Ctrl_Cmd_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller address mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */\n+ SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */\n+ SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */\n+} SF_Ctrl_Addr_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller dummy mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */\n+ SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */\n+ SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */\n+} SF_Ctrl_Dmy_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller data mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */\n+ SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */\n+ SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */\n+} SF_Ctrl_Data_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller AES mode type definition\n+ */\n+typedef enum {\n+ SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */\n+ SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */\n+} SF_Ctrl_AES_Mode_Type;\n+\n+/**\n+ * @brief Serail flash controller AES key len type definition\n+ */\n+typedef enum {\n+ SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */\n+ SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */\n+ SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */\n+ SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */\n+} SF_Ctrl_AES_Key_Type;\n+\n+/**\n+ * @brief Serail flash controller configuration structure type definition\n+ */\n+typedef struct\n+{\n+ SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */\n+ BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */\n+ uint8_t clkDelay; /*!< Clock count for read due to pad delay */\n+ uint8_t clkInvert; /*!< Clock invert */\n+ uint8_t rxClkInvert; /*!< RX clock invert */\n+ uint8_t doDelay; /*!< Data out delay */\n+ uint8_t diDelay; /*!< Data in delay */\n+ uint8_t oeDelay; /*!< Output enable delay */\n+} SF_Ctrl_Cfg_Type;\n+\n+/**\n+ * @brief SF Ctrl bank2 controller configuration structure type definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */\n+ BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */\n+ BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */\n+ BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */\n+ uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */\n+ uint8_t doDelay; /*!< Data out delay */\n+ uint8_t diDelay; /*!< Data in delay */\n+ uint8_t oeDelay; /*!< Output enable delay */\n+ SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */\n+ uint8_t remapLock; /*!< Select memory remap lock */\n+} SF_Ctrl_Bank2_Cfg;\n+\n+/**\n+ * @brief SF Ctrl cmds configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */\n+ BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */\n+ BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */\n+ SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */\n+ SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */\n+} SF_Ctrl_Cmds_Cfg;\n+\n+/**\n+ * @brief Serail flash command configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t rwFlag; /*!< Read write flag */\n+ SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */\n+ SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */\n+ uint8_t addrSize; /*!< Address size */\n+ uint8_t dummyClks; /*!< Dummy clocks */\n+ SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */\n+ SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */\n+ uint8_t rsv[1]; /*!< */\n+ uint32_t nbData; /*!< Transfer number of bytes */\n+ uint32_t cmdBuf[2]; /*!< Command buffer */\n+} SF_Ctrl_Cmd_Cfg_Type;\n+\n+/*@} end of group SF_CTRL_Public_Types */\n+\n+/** @defgroup SF_CTRL_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup SF_CTRL_PAD_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \\\n+ ((type) == SF_CTRL_PAD2) || \\\n+ ((type) == SF_CTRL_PAD3))\n+\n+/** @defgroup SF_CTRL_PIN_SELECT\n+ * @{\n+ */\n+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \\\n+ ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \\\n+ ((type) == SF_IO_EMB_SWAP_NONE) || \\\n+ ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \\\n+ ((type) == SF_IO_EXT_SF2) || \\\n+ ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \\\n+ ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \\\n+ ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \\\n+ ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2))\n+\n+/** @defgroup SF_CTRL_BANK_SELECT\n+ * @{\n+ */\n+#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \\\n+ ((type) == SF_CTRL_FLASH_BANK1))\n+\n+/** @defgroup SF_CTRL_WRAP_MODE\n+ * @{\n+ */\n+#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \\\n+ ((type) == SF_CTRL_WRAP_MODE_1) || \\\n+ ((type) == SF_CTRL_WRAP_MODE_2) || \\\n+ ((type) == SF_CTRL_WRAP_MODE_3))\n+\n+/** @defgroup SF_CTRL_WRAP_LEN_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_16) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_32) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_64) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_128) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_256) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_512) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_1024) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_2048) || \\\n+ ((type) == SF_CTRL_WRAP_LEN_4096))\n+\n+/** @defgroup SF_CTRL_REMAP_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \\\n+ ((type) == SF_CTRL_REMAP_16MB) || \\\n+ ((type) == SF_CTRL_REMAP_8MB) || \\\n+ ((type) == SF_CTRL_REMAP_4MB))\n+\n+/** @defgroup SF_CTRL_OWNER_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \\\n+ ((type) == SF_CTRL_OWNER_IAHB))\n+\n+/** @defgroup SF_CTRL_RW_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \\\n+ ((type) == SF_CTRL_WRITE))\n+\n+/** @defgroup SF_CTRL_IO_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \\\n+ ((type) == SF_CTRL_DO_MODE) || \\\n+ ((type) == SF_CTRL_QO_MODE) || \\\n+ ((type) == SF_CTRL_DIO_MODE) || \\\n+ ((type) == SF_CTRL_QIO_MODE))\n+\n+/** @defgroup SF_CTRL_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \\\n+ ((type) == SF_CTRL_QPI_MODE))\n+\n+/** @defgroup SF_CTRL_CMD_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \\\n+ ((type) == SF_CTRL_CMD_4_LINES))\n+\n+/** @defgroup SF_CTRL_ADDR_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \\\n+ ((type) == SF_CTRL_ADDR_2_LINES) || \\\n+ ((type) == SF_CTRL_ADDR_4_LINES))\n+\n+/** @defgroup SF_CTRL_DMY_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \\\n+ ((type) == SF_CTRL_DUMMY_2_LINES) || \\\n+ ((type) == SF_CTRL_DUMMY_4_LINES))\n+\n+/** @defgroup SF_CTRL_DATA_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \\\n+ ((type) == SF_CTRL_DATA_2_LINES) || \\\n+ ((type) == SF_CTRL_DATA_4_LINES))\n+\n+/** @defgroup SF_CTRL_AES_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \\\n+ ((type) == SF_CTRL_AES_XTS_MODE))\n+\n+/** @defgroup SF_CTRL_AES_KEY_TYPE\n+ * @{\n+ */\n+#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \\\n+ ((type) == SF_CTRL_AES_256BITS) || \\\n+ ((type) == SF_CTRL_AES_192BITS) || \\\n+ ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))\n+\n+/*@} end of group SF_CTRL_Public_Constants */\n+\n+/** @defgroup SF_CTRL_Public_Macros\n+ * @{\n+ */\n+#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF\n+#define NOR_FLASH_CTRL_BUF_SIZE 256\n+#define NAND_FLASH_CTRL_BUF_SIZE 512\n+\n+/*@} end of group SF_CTRL_Public_Macros */\n+\n+/** @defgroup SF_CTRL_Public_Functions\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SF_Ctrl_IRQHandler(void);\n+#endif\n+void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);\n+void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg);\n+void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay);\n+void SF_Ctrl_Sbus2_Hold_Sram(void);\n+void SF_Ctrl_Sbus2_Release_Sram(void);\n+BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void);\n+void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad);\n+void SF_Ctrl_Sbus2_Revoke_replace(void);\n+void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert);\n+void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr);\n+uint8_t SF_Ctrl_Get_Clock_Delay(void);\n+void SF_Ctrl_Set_Clock_Delay(uint8_t delay);\n+uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void);\n+void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank);\n+void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock);\n+void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel);\n+void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank);\n+void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);\n+void SF_Ctrl_Disable(void);\n+void SF_Ctrl_AES_Enable_BE(void);\n+void SF_Ctrl_AES_Enable_LE(void);\n+void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr,\n+ uint8_t locked);\n+void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);\n+void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);\n+void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);\n+void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);\n+void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);\n+void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode);\n+void SF_Ctrl_AES_Enable(void);\n+void SF_Ctrl_AES_Disable(void);\n+BL_Sts_Type SF_Ctrl_Is_AES_Enable(void);\n+void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank);\n+uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank);\n+void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock);\n+void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);\n+void SF_Ctrl_Disable_Wrap_Access(uint8_t disable);\n+void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);\n+void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);\n+BL_Sts_Type SF_Ctrl_GetBusyState(void);\n+\n+/*@} end of group SF_CTRL_Public_Functions */\n+\n+/*@} end of group SF_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SF_CTRL_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..51f9bc2e1e6ddd5169e7e2decb9a8ebac30b517d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h\n@@ -0,0 +1,218 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sflah.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SFLAH_H__\n+#define __BL808_SFLAH_H__\n+\n+#include \"bl808_common.h\"\n+#include \"bl808_sf_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SFLAH\n+ * @{\n+ */\n+\n+/** @defgroup SFLAH_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief Serial flash configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */\n+ uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */\n+ uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */\n+ uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */\n+ uint8_t resetEnCmd; /*!< Flash enable reset command */\n+ uint8_t resetCmd; /*!< Flash reset command */\n+ uint8_t resetCreadCmd; /*!< Flash reset continuous read command */\n+ uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */\n+ uint8_t jedecIdCmd; /*!< JEDEC ID command */\n+ uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */\n+ uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */\n+ uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */\n+ uint8_t sectorSize; /*!< *1024bytes */\n+ uint8_t mid; /*!< Manufacturer ID */\n+ uint16_t pageSize; /*!< Page size */\n+ uint8_t chipEraseCmd; /*!< Chip erase cmd */\n+ uint8_t sectorEraseCmd; /*!< Sector erase command */\n+ uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */\n+ uint8_t blk64EraseCmd; /*!< Block 64K erase command */\n+ uint8_t writeEnableCmd; /*!< Need before every erase or program */\n+ uint8_t pageProgramCmd; /*!< Page program cmd */\n+ uint8_t qpageProgramCmd; /*!< QIO page program cmd */\n+ uint8_t qppAddrMode; /*!< QIO page program address mode */\n+ uint8_t fastReadCmd; /*!< Fast read command */\n+ uint8_t frDmyClk; /*!< Fast read command dummy clock */\n+ uint8_t qpiFastReadCmd; /*!< QPI fast read command */\n+ uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */\n+ uint8_t fastReadDoCmd; /*!< Fast read dual output command */\n+ uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */\n+ uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */\n+ uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */\n+ uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */\n+ uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */\n+ uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */\n+ uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */\n+ uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */\n+ uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */\n+ uint8_t qpiPageProgramCmd; /*!< QPI program command */\n+ uint8_t writeVregEnableCmd; /*!< Enable write reg */\n+ uint8_t wrEnableIndex; /*!< Write enable register index */\n+ uint8_t qeIndex; /*!< Quad mode enable register index */\n+ uint8_t busyIndex; /*!< Busy status register index */\n+ uint8_t wrEnableBit; /*!< Write enable bit pos */\n+ uint8_t qeBit; /*!< Quad enable bit pos */\n+ uint8_t busyBit; /*!< Busy status bit pos */\n+ uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */\n+ uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */\n+ uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */\n+ uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */\n+ uint8_t releasePowerDown; /*!< Release power down command */\n+ uint8_t busyReadRegLen; /*!< Register length of contain busy status */\n+ uint8_t readRegCmd[4]; /*!< Read register command buffer */\n+ uint8_t writeRegCmd[4]; /*!< Write register command buffer */\n+ uint8_t enterQpi; /*!< Enter qpi command */\n+ uint8_t exitQpi; /*!< Exit qpi command */\n+ uint8_t cReadMode; /*!< Config data for continuous read mode */\n+ uint8_t cRExit; /*!< Config data for exit continuous read mode */\n+ uint8_t burstWrapCmd; /*!< Enable burst wrap command */\n+ uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */\n+ uint8_t burstWrapDataMode; /*!< Data and address mode for this command */\n+ uint8_t burstWrapData; /*!< Data to enable burst wrap */\n+ uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */\n+ uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */\n+ uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */\n+ uint8_t deBurstWrapData; /*!< Data to disable burst wrap */\n+ uint16_t timeEsector; /*!< 4K erase time */\n+ uint16_t timeE32k; /*!< 32K erase time */\n+ uint16_t timeE64k; /*!< 64K erase time */\n+ uint16_t timePagePgm; /*!< Page program time */\n+ uint16_t timeCe; /*!< Chip erase time in ms */\n+ uint8_t pdDelay; /*!< Release power down command delay time for wake up */\n+ uint8_t qeData; /*!< QE set data */\n+} __attribute__((packed)) SPI_Flash_Cfg_Type;\n+\n+/**\n+ * @brief Serial flash security register configuration\n+ */\n+typedef struct\n+{\n+ uint8_t eraseCmd; /*!< Erase security register command */\n+ uint8_t programCmd; /*!< Program security register command */\n+ uint8_t readCmd; /*!< Read security register command */\n+ uint8_t enterSecOptCmd; /*!< Enter security register option mode command */\n+ uint8_t exitSecOptCmd; /*!< Exit security register option mode command */\n+ uint8_t blockNum; /*!< Security register block number */\n+ uint8_t *data; /*!< Data pointer to be program/read */\n+ uint32_t addr; /*!< Start address to be program/read */\n+ uint32_t len; /*!< Data length to be program/read */\n+} SFlash_Sec_Reg_Cfg;\n+/*@} end of group SFLAH_Public_Types */\n+\n+/** @defgroup SFLAH_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group SFLAH_Public_Constants */\n+\n+/** @defgroup SFLAH_Public_Macros\n+ * @{\n+ */\n+#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)\n+#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)\n+#define BFLB_SPIFLASH_CMD_INVALID 0xff\n+\n+/*@} end of group SFLAH_Public_Macros */\n+\n+/** @defgroup SFLAH_Public_Functions\n+ * @{\n+ */\n+void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);\n+BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);\n+BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);\n+BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);\n+BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,\n+ uint8_t regLen);\n+BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,\n+ uint8_t regLen);\n+BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg);\n+void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);\n+BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);\n+BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);\n+BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);\n+void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);\n+void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);\n+void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr);\n+void SFlash_Powerdown(void);\n+void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead,\n+ SF_Ctrl_Bank_Select bank);\n+void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);\n+void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr);\n+BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);\n+void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);\n+BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,\n+ uint32_t len, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,\n+ SF_Ctrl_Bank_Select bank);\n+void SFlash_IDbus_Read_Disable(void);\n+BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos);\n+BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg);\n+BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg,\n+ SFlash_Sec_Reg_Cfg *pSecRegCfg);\n+BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg);\n+BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,\n+ uint32_t len);\n+BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);\n+\n+/*@} end of group SFLAH_Public_Functions */\n+\n+/*@} end of group SFLAH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SFLAH_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bddd2ee8750c16bfafaf99eb136f45c222d858cc\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h\n@@ -0,0 +1,321 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_spi.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_SPI_H__\n+#define __BL808_SPI_H__\n+\n+#include \"spi_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SPI\n+ * @{\n+ */\n+\n+/** @defgroup SPI_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief SPI No. type definition\n+ */\n+typedef enum {\n+ SPI0_ID, /*!< SPI0 port define */\n+ SPI0_MM_ID, /*!< MM system SPI0 port define */\n+ SPI_ID_MAX, /*!< SPI MAX ID define */\n+} SPI_ID_Type;\n+\n+/**\n+ * @brief SPI slave pin mode type definition\n+ */\n+typedef enum {\n+ SPI_SLAVE_PIN_4, /*!< SPI 4-pin mode(CS is enabled) */\n+ SPI_SLAVE_PIN_3, /*!< SPI 3-pin mode(CS don't case) */\n+} SPI_Slave_Pin_Type;\n+\n+/**\n+ * @brief SPI byte inverse type definition\n+ */\n+typedef enum {\n+ SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */\n+ SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */\n+} SPI_BYTE_INVERSE_Type;\n+\n+/**\n+ * @brief SPI bit inverse type definition\n+ */\n+typedef enum {\n+ SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */\n+ SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */\n+} SPI_BIT_INVERSE_Type;\n+\n+/**\n+ * @brief SPI clock phase inverse type definition\n+ */\n+typedef enum {\n+ SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */\n+ SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */\n+} SPI_CLK_PHASE_INVERSE_Type;\n+\n+/**\n+ * @brief SPI clock polarity type definition\n+ */\n+typedef enum {\n+ SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */\n+ SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */\n+} SPI_CLK_POLARITY_Type;\n+\n+/**\n+ * @brief SPI frame size(also the valid width for each fifo entry) type definition\n+ */\n+typedef enum {\n+ SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */\n+ SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */\n+ SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */\n+ SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */\n+} SPI_FrameSize_Type;\n+\n+/**\n+ * @brief SPI work mode select type definition\n+ */\n+typedef enum {\n+ SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */\n+ SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */\n+} SPI_WORK_MODE_Type;\n+\n+/**\n+ * @brief SPI enable or disable timeout judgment definition\n+ */\n+typedef enum {\n+ SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */\n+ SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */\n+} SPI_Timeout_Type;\n+\n+/**\n+ * @brief SPI fifo overflow/underflow flag type definition\n+ */\n+typedef enum {\n+ SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */\n+ SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */\n+ SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */\n+ SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */\n+} SPI_FifoStatus_Type;\n+\n+/**\n+ * @brief SPI interrupt type definition\n+ */\n+typedef enum {\n+ SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */\n+ SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */\n+ SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */\n+ SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */\n+ SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */\n+ SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */\n+ SPI_INT_ALL, /*!< All the interrupt */\n+} SPI_INT_Type;\n+\n+/**\n+ * @brief SPI configuration type definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */\n+ SPI_Slave_Pin_Type slavePin; /*!< Slave 4/3 pin mode */\n+ BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */\n+ SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */\n+ SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */\n+ SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */\n+ SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */\n+ SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */\n+} SPI_CFG_Type;\n+\n+/**\n+ * @brief SPI configuration type definition\n+ */\n+typedef struct\n+{\n+ uint8_t startLen; /*!< Length of start condition */\n+ uint8_t stopLen; /*!< Length of stop condition */\n+ uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */\n+ uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */\n+ uint8_t intervalLen; /*!< Length of interval between frame */\n+} SPI_ClockCfg_Type;\n+\n+/**\n+ * @brief SPI DMA configuration type definition\n+ */\n+typedef struct\n+{\n+ uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */\n+ uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */\n+ BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */\n+ BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */\n+} SPI_FifoCfg_Type;\n+\n+/*@} end of group SPI_Public_Types */\n+\n+/** @defgroup SPI_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup SPI_ID_TYPE\n+ * @{\n+ */\n+#define IS_SPI_ID_TYPE(type) (((type) == SPI0_ID) || \\\n+ ((type) == SPI0_MM_ID) || \\\n+ ((type) == SPI_ID_MAX))\n+\n+/** @defgroup SPI_SLAVE_PIN_TYPE\n+ * @{\n+ */\n+#define IS_SPI_SLAVE_PIN_TYPE(type) (((type) == SPI_SLAVE_PIN_4) || \\\n+ ((type) == SPI_SLAVE_PIN_3))\n+\n+/** @defgroup SPI_BYTE_INVERSE_TYPE\n+ * @{\n+ */\n+#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \\\n+ ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST))\n+\n+/** @defgroup SPI_BIT_INVERSE_TYPE\n+ * @{\n+ */\n+#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \\\n+ ((type) == SPI_BIT_INVERSE_LSB_FIRST))\n+\n+/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE\n+ * @{\n+ */\n+#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \\\n+ ((type) == SPI_CLK_PHASE_INVERSE_1))\n+\n+/** @defgroup SPI_CLK_POLARITY_TYPE\n+ * @{\n+ */\n+#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \\\n+ ((type) == SPI_CLK_POLARITY_HIGH))\n+\n+/** @defgroup SPI_FRAMESIZE_TYPE\n+ * @{\n+ */\n+#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \\\n+ ((type) == SPI_FRAME_SIZE_16) || \\\n+ ((type) == SPI_FRAME_SIZE_24) || \\\n+ ((type) == SPI_FRAME_SIZE_32))\n+\n+/** @defgroup SPI_WORK_MODE_TYPE\n+ * @{\n+ */\n+#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \\\n+ ((type) == SPI_WORK_MODE_MASTER))\n+\n+/** @defgroup SPI_TIMEOUT_TYPE\n+ * @{\n+ */\n+#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \\\n+ ((type) == SPI_TIMEOUT_ENABLE))\n+\n+/** @defgroup SPI_FIFOSTATUS_TYPE\n+ * @{\n+ */\n+#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \\\n+ ((type) == SPI_FIFO_TX_UNDERFLOW) || \\\n+ ((type) == SPI_FIFO_RX_OVERFLOW) || \\\n+ ((type) == SPI_FIFO_RX_UNDERFLOW))\n+\n+/** @defgroup SPI_INT_TYPE\n+ * @{\n+ */\n+#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \\\n+ ((type) == SPI_INT_TX_FIFO_REQ) || \\\n+ ((type) == SPI_INT_RX_FIFO_REQ) || \\\n+ ((type) == SPI_INT_SLAVE_TIMEOUT) || \\\n+ ((type) == SPI_INT_SLAVE_UNDERRUN) || \\\n+ ((type) == SPI_INT_FIFO_ERROR) || \\\n+ ((type) == SPI_INT_ALL))\n+\n+/*@} end of group SPI_Public_Constants */\n+\n+/** @defgroup SPI_Public_Macros\n+ * @{\n+ */\n+#define SPI_RX_FIFO_SIZE 32\n+#define SPI_TX_FIFO_SIZE 32\n+\n+/*@} end of group SPI_Public_Macros */\n+\n+/** @defgroup SPI_Public_Functions\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SPI0_IRQHandler(void);\n+void SPI1_IRQHandler(void);\n+#endif\n+BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg);\n+BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo);\n+BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg);\n+BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg);\n+BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);\n+BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);\n+BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize);\n+BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value);\n+BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt);\n+BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint);\n+BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo);\n+BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo);\n+BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo);\n+BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);\n+BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask);\n+BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun);\n+BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType);\n+BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType);\n+BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length,\n+ SPI_Timeout_Type timeoutType);\n+uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo);\n+uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo);\n+BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);\n+BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts);\n+BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo);\n+BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk);\n+/*@} end of group SPI_Public_Functions */\n+\n+/*@} end of group SPI */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_SPI_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ac1c58efad14e788ab5ffef8b4431d13f4dde56b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h\n@@ -0,0 +1,312 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_timer.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_TIMER_H__\n+#define __BL808_TIMER_H__\n+\n+#include \"timer_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TIMER\n+ * @{\n+ */\n+\n+/** @defgroup TIMER_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief TIMER port type definition\n+ */\n+typedef enum {\n+ TIMER0_ID, /*!< TIMER0 port define */\n+ TIMER1_ID, /*!< TIMER1 port define */\n+ TIMER_ID_MAX, /*!< TIMER MAX ID define */\n+} TIMER_ID_Type;\n+\n+/**\n+ * @brief Watchdog timer port type definition\n+ */\n+typedef enum {\n+ WDT0_ID, /*!< Watchdog0 port define */\n+ WDT1_ID, /*!< Watchdog1 port define */\n+ WDT_ID_MAX, /*!< Watchdog MAX ID define */\n+} WDT_ID_Type;\n+\n+/**\n+ * @brief TIMER channel type definition\n+ */\n+typedef enum {\n+ TIMER_CH0, /*!< TIMER channel 0 port define */\n+ TIMER_CH1, /*!< TIMER channel 1 port define */\n+ TIMER_CH_MAX, /*!< */\n+} TIMER_Chan_Type;\n+\n+/**\n+ * @brief TIMER clock source type definition\n+ */\n+typedef enum {\n+ TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */\n+ TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */\n+ TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */\n+ TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */\n+ TIMER_CLKSRC_GPIO, /*!< TIMER clock source :GPIO */\n+ TIMER_CLKSRC_NO, /*!< TIMER clock source :No CLK */\n+} TIMER_ClkSrc_Type;\n+\n+/**\n+ * @brief TIMER match compare ID type definition\n+ */\n+typedef enum {\n+ TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */\n+ TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */\n+ TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */\n+} TIMER_Comp_ID_Type;\n+\n+/**\n+ * @brief TIMER preload source type definition\n+ */\n+typedef enum {\n+ TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */\n+ TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */\n+ TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */\n+ TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */\n+} TIMER_PreLoad_Trig_Type;\n+\n+/**\n+ * @brief TIMER count register run mode type definition\n+ */\n+typedef enum {\n+ TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */\n+ TIMER_COUNT_FREERUN, /*!< TIMER count register free run */\n+} TIMER_CountMode_Type;\n+\n+/**\n+ * @brief TIMER gpio polarity type definition\n+ */\n+typedef enum {\n+ TIMER_GPIO_POS, /*!< TIMER gpio plarity posedge */\n+ TIMER_GPIO_NEG, /*!< TIMER gpio plarity negedge */\n+} TIMER_GPIO_Polarity_Type;\n+\n+/**\n+ * @brief TIMER interrupt type definition\n+ */\n+typedef enum {\n+ TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */\n+ TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */\n+ TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */\n+ TIMER_INT_ALL, /*!< */\n+} TIMER_INT_Type;\n+\n+/**\n+ * @brief Watchdog timer interrupt type definition\n+ */\n+typedef enum {\n+ WDT_INT, /*!< Comparator 0 match cause interrupt */\n+ WDT_INT_ALL, /*!< */\n+} WDT_INT_Type;\n+\n+/**\n+ * @brief TIMER configuration structure type definition\n+ */\n+typedef struct\n+{\n+ TIMER_Chan_Type timerCh; /*!< Timer channel */\n+ TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */\n+ TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */\n+ TIMER_CountMode_Type countMode; /*!< Timer count mode */\n+ uint8_t clockDivision; /*!< Timer clock divison value */\n+ uint32_t matchVal0; /*!< Timer match 0 value 0 */\n+ uint32_t matchVal1; /*!< Timer match 1 value 0 */\n+ uint32_t matchVal2; /*!< Timer match 2 value 0 */\n+ uint32_t preLoadVal; /*!< Timer preload value */\n+} TIMER_CFG_Type;\n+\n+/*@} end of group TIMER_Public_Types */\n+\n+/** @defgroup TIMER_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup TIMER_ID_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_ID_TYPE(type) (((type) == TIMER0_ID) || \\\n+ ((type) == TIMER1_ID) || \\\n+ ((type) == TIMER_ID_MAX))\n+\n+/** @defgroup WDT_ID_TYPE\n+ * @{\n+ */\n+#define IS_WDT_ID_TYPE(type) (((type) == WDT0_ID) || \\\n+ ((type) == WDT1_ID) || \\\n+ ((type) == WDT_ID_MAX))\n+\n+/** @defgroup TIMER_CHAN_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \\\n+ ((type) == TIMER_CH1) || \\\n+ ((type) == TIMER_CH_MAX))\n+\n+/** @defgroup TIMER_CLKSRC_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \\\n+ ((type) == TIMER_CLKSRC_32K) || \\\n+ ((type) == TIMER_CLKSRC_1K) || \\\n+ ((type) == TIMER_CLKSRC_XTAL) || \\\n+ ((type) == TIMER_CLKSRC_GPIO) || \\\n+ ((type) == TIMER_CLKSRC_NO))\n+\n+/** @defgroup TIMER_COMP_ID_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \\\n+ ((type) == TIMER_COMP_ID_1) || \\\n+ ((type) == TIMER_COMP_ID_2))\n+\n+/** @defgroup TIMER_PRELOAD_TRIG_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \\\n+ ((type) == TIMER_PRELOAD_TRIG_COMP0) || \\\n+ ((type) == TIMER_PRELOAD_TRIG_COMP1) || \\\n+ ((type) == TIMER_PRELOAD_TRIG_COMP2))\n+\n+/** @defgroup TIMER_COUNTMODE_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \\\n+ ((type) == TIMER_COUNT_FREERUN))\n+\n+/** @defgroup TIMER_GPIO_POLARITY_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_GPIO_POLARITY_TYPE(type) (((type) == TIMER_GPIO_POS) || \\\n+ ((type) == TIMER_GPIO_NEG))\n+\n+/** @defgroup TIMER_INT_TYPE\n+ * @{\n+ */\n+#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \\\n+ ((type) == TIMER_INT_COMP_1) || \\\n+ ((type) == TIMER_INT_COMP_2) || \\\n+ ((type) == TIMER_INT_ALL))\n+\n+/** @defgroup WDT_INT_TYPE\n+ * @{\n+ */\n+#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \\\n+ ((type) == WDT_INT_ALL))\n+\n+/*@} end of group TIMER_Public_Constants */\n+\n+/** @defgroup TIMER_Public_Macros\n+ * @{\n+ */\n+#define WDT_ENABLE_ACCESS(baseAddr) \\\n+ { \\\n+ BL_WR_REG(baseAddr, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \\\n+ BL_WR_REG(baseAddr, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \\\n+ }\n+\n+/*@} end of group TIMER_Public_Macros */\n+\n+/** @defgroup TIMER_Public_Functions\n+ * @{\n+ */\n+\n+/**\n+ * @brief UART Functions\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER0_CH0_IRQHandler(void);\n+void TIMER0_CH1_IRQHandler(void);\n+void TIMER0_WDT_IRQHandler(void);\n+void TIMER1_CH0_IRQHandler(void);\n+void TIMER1_CH1_IRQHandler(void);\n+void TIMER1_WDT_IRQHandler(void);\n+#endif\n+BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg);\n+BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId);\n+uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);\n+void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val);\n+void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable);\n+uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);\n+uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val);\n+void TIMER_SetPreloadSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc);\n+void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode);\n+void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);\n+void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask);\n+void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity);\n+void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable);\n+uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId);\n+void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc);\n+void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun);\n+\n+void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div);\n+uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId);\n+void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val);\n+void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable);\n+uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId);\n+void WDT_ResetCounterValue(WDT_ID_Type wdtId);\n+BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId);\n+void WDT_ClearResetStatus(WDT_ID_Type wdtId);\n+void WDT_Enable(WDT_ID_Type wdtId);\n+void WDT_Disable(WDT_ID_Type wdtId);\n+void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask);\n+void WDT_ForceClockDivision(WDT_ID_Type wdtId);\n+void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun);\n+void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity);\n+\n+/*@} end of group TIMER_Public_Functions */\n+\n+/*@} end of group TIMER */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_TIMER_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3768b9298e72528447054aeaee48a86ff47e1a0d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h\n@@ -0,0 +1,480 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_touch.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_TOUCH_H__\n+#define __BL808_TOUCH_H__\n+\n+#include \"pds_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TOUCH\n+ * @{\n+ */\n+\n+/** @defgroup TOUCH_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief TOUCH ID type definition\n+ */\n+typedef enum {\n+ TOUCH_ID_0, /*!< TOUCH ID 0 */\n+} TOUCH_ID_Type;\n+\n+/**\n+ * @brief TOUCH run mode select type definition\n+ */\n+typedef enum {\n+ TOUCH_RUN_MODE_SINGLE_SHOT, /*!< TOUCH run in single shot mode */\n+ TOUCH_RUN_MODE_CONTINUE, /*!< TOUCH run in continue mode */\n+} TOUCH_RUN_MODE_Type;\n+\n+/**\n+ * @brief TOUCH pcharge low type definition\n+ */\n+typedef enum {\n+ TOUCH_PCHARGE_LOW_127, /*!< for one channel, the max external cap leakage cycle is 127 */\n+ TOUCH_PCHARGE_LOW_255, /*!< for one channel, the max external cap leakage cycle is 255 */\n+ TOUCH_PCHARGE_LOW_511, /*!< for one channel, the max external cap leakage cycle is 511 */\n+ TOUCH_PCHARGE_LOW_1023, /*!< for one channel, the max external cap leakage cycle is 1023 */\n+ TOUCH_PCHARGE_LOW_2047, /*!< for one channel, the max external cap leakage cycle is 2047 */\n+ TOUCH_PCHARGE_LOW_4095, /*!< for one channel, the max external cap leakage cycle is 4095 */\n+} TOUCH_PCHARGE_LOW_Type;\n+\n+/**\n+ * @brief TOUCH pcharge high type definition\n+ */\n+typedef enum {\n+ TOUCH_PCHARGE_HIGH_511, /*!< for one channel, the max external cap charge-transfer cycle is 511 */\n+ TOUCH_PCHARGE_HIGH_1023, /*!< for one channel, the max external cap charge-transfer cycle is 1023 */\n+ TOUCH_PCHARGE_HIGH_2047, /*!< for one channel, the max external cap charge-transfer cycle is 2047 */\n+ TOUCH_PCHARGE_HIGH_4095, /*!< for one channel, the max external cap charge-transfer cycle is 4095 */\n+ TOUCH_PCHARGE_HIGH_8191, /*!< for one channel, the max external cap charge-transfer cycle is 8191 */\n+ TOUCH_PCHARGE_HIGH_16383, /*!< for one channel, the max external cap charge-transfer cycle is 16383 */\n+ TOUCH_PCHARGE_HIGH_32767, /*!< for one channel, the max external cap charge-transfer cycle is 32767 */\n+ TOUCH_PCHARGE_HIGH_65535, /*!< for one channel, the max external cap charge-transfer cycle is 65535 */\n+} TOUCH_PCHARGE_HIGH_Type;\n+\n+/**\n+ * @brief TOUCH clock divider type definition\n+ */\n+typedef enum {\n+ TOUCH_CLK_DIV_1, /*!< TOUCH clock div 1 */\n+ TOUCH_CLK_DIV_2, /*!< TOUCH clock div 2 */\n+ TOUCH_CLK_DIV_4, /*!< TOUCH clock div 4 */\n+ TOUCH_CLK_DIV_8, /*!< TOUCH clock div 8 */\n+ TOUCH_CLK_DIV_16, /*!< TOUCH clock div 16 */\n+ TOUCH_CLK_DIV_32, /*!< TOUCH clock div 32 */\n+ TOUCH_CLK_DIV_64, /*!< TOUCH clock div 64 */\n+ TOUCH_CLK_DIV_128, /*!< TOUCH clock div 128 */\n+} TOUCH_CLK_DIV_Type;\n+\n+/**\n+ * @brief TOUCH clock source select type definition\n+ */\n+typedef enum {\n+ TOUCH_CLK_SEL_32K, /*!< select 32K as TOUCH clock */\n+ TOUCH_CLK_SEL_32M, /*!< select 32M as TOUCH clock */\n+} TOUCH_CLK_SEL_Type;\n+\n+/**\n+ * @brief TOUCH current source select type definition\n+ */\n+typedef enum {\n+ TOUCH_POWER_SEL_AON, /*!< select touch current from AON bandgap,power up touch current in rf707_aon */\n+ TOUCH_POWER_SEL_INTERNAL_BG, /*!< select touch current from internal bandgap,power off touch current in rf707_aon */\n+} TOUCH_POWER_SEL_Type;\n+\n+/**\n+ * @brief TOUCH comparator hystersis voltage type definition\n+ */\n+typedef enum {\n+ TOUCH_HYSTERSIS_VOLTAGE_30mV, /*!< set 30mV comparator hystersis voltage */\n+ TOUCH_HYSTERSIS_VOLTAGE_80mV, /*!< set 80mV comparator hystersis voltage */\n+} TOUCH_HYSTERSIS_VOLTAGE_Type;\n+\n+/**\n+ * @brief TOUCH LDO voltage control type definition\n+ */\n+typedef enum {\n+ TOUCH_LDO_VOLTAGE_0P6V, /*!< LDO output 0.6V */\n+ TOUCH_LDO_VOLTAGE_0P8V, /*!< LDO output 0.8V */\n+ TOUCH_LDO_VOLTAGE_1P0V, /*!< LDO output 1.0V */\n+ TOUCH_LDO_VOLTAGE_1P2V, /*!< LDO output 1.2V */\n+ TOUCH_LDO_VOLTAGE_1P4V, /*!< LDO output 1.4V */\n+ TOUCH_LDO_VOLTAGE_1P6V, /*!< LDO output 1.6V */\n+ TOUCH_LDO_VOLTAGE_1P8V, /*!< LDO output 1.8V */\n+ TOUCH_LDO_VOLTAGE_2P0V, /*!< LDO output 2.0V */\n+} TOUCH_LDO_VOLTAGE_Type;\n+\n+/**\n+ * @brief TOUCH reference voltage control type definition\n+ */\n+typedef enum {\n+ TOUCH_VREF_VOLTAGE_0P4V, /*!< LDO output 0.4V */\n+ TOUCH_VREF_VOLTAGE_0P6V, /*!< LDO output 0.6V */\n+ TOUCH_VREF_VOLTAGE_0P8V, /*!< LDO output 0.8V */\n+ TOUCH_VREF_VOLTAGE_1P0V, /*!< LDO output 1.0V */\n+ TOUCH_VREF_VOLTAGE_1P2V, /*!< LDO output 1.2V */\n+ TOUCH_VREF_VOLTAGE_1P4V, /*!< LDO output 1.4V */\n+ TOUCH_VREF_VOLTAGE_1P6V, /*!< LDO output 1.6V */\n+ TOUCH_VREF_VOLTAGE_1P8V, /*!< LDO output 1.8V */\n+} TOUCH_VREF_VOLTAGE_Type;\n+\n+/**\n+ * @brief TOUCH compensation cap control type definition\n+ */\n+typedef enum {\n+ TOUCH_COMPENSATION_CAP_12pF, /*!< compensation cap is 12pF */\n+ TOUCH_COMPENSATION_CAP_13pF, /*!< compensation cap is 13pF */\n+ TOUCH_COMPENSATION_CAP_14pF, /*!< compensation cap is 14pF */\n+ TOUCH_COMPENSATION_CAP_15pF, /*!< compensation cap is 15pF */\n+} TOUCH_COMPENSATION_CAP_Type;\n+\n+/**\n+ * @brief TOUCH mode select type definition\n+ */\n+typedef enum {\n+ TOUCH_WORK_MODE_SELF_CAP, /*!< self cap mode,each channel detection result can judge if this channel is touched */\n+ TOUCH_WORK_MODE_MUTUAL, /*!< mutual mode,channel 6~0 works,higher 3 channel-->column,lower 4 channel-->row */\n+} TOUCH_WORK_MODE_Type;\n+\n+/**\n+ * @brief TOUCH filter long time average order control,FLT(new)=(data_raw+FLT(former)*(2^N-1))/2^N\n+ */\n+typedef enum {\n+ TOUCH_FILTER_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */\n+ TOUCH_FILTER_ORDER_CTRL_1, /*!< N=1 */\n+ TOUCH_FILTER_ORDER_CTRL_2, /*!< N=2 */\n+ TOUCH_FILTER_ORDER_CTRL_3, /*!< N=3 */\n+ TOUCH_FILTER_ORDER_CTRL_4, /*!< N=4 */\n+ TOUCH_FILTER_ORDER_CTRL_5, /*!< N=5 */\n+ TOUCH_FILTER_ORDER_CTRL_6, /*!< N=6 */\n+ TOUCH_FILTER_ORDER_CTRL_7, /*!< N=7 */\n+} TOUCH_FILTER_ORDER_CTRL_Type;\n+\n+/**\n+ * @brief TOUCH LTA long time average order control,LTA(new)=(data_raw+LTA(former)*(2^N-1))/2^N\n+ */\n+typedef enum {\n+ TOUCH_LTA_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */\n+ TOUCH_LTA_ORDER_CTRL_1, /*!< N=1 */\n+ TOUCH_LTA_ORDER_CTRL_2, /*!< N=2 */\n+ TOUCH_LTA_ORDER_CTRL_3, /*!< N=3 */\n+ TOUCH_LTA_ORDER_CTRL_4, /*!< N=4 */\n+ TOUCH_LTA_ORDER_CTRL_5, /*!< N=5 */\n+ TOUCH_LTA_ORDER_CTRL_6, /*!< N=6 */\n+ TOUCH_LTA_ORDER_CTRL_7, /*!< N=7 */\n+} TOUCH_LTA_ORDER_CTRL_Type;\n+\n+/**\n+ * @brief TOUCH configuration type definition\n+ */\n+typedef struct\n+{\n+ TOUCH_CLK_SEL_Type clkSel; /*!< TOUCH clock source select */\n+ TOUCH_CLK_DIV_Type clkDiv; /*!< TOUCH clock divider */\n+ TOUCH_POWER_SEL_Type powerSel; /*!< TOUCH power source select */\n+ BL_Fun_Type calibrationEn; /*!< touch_channel calibration option, when enable,the counting number will be set as LTA data */\n+ TOUCH_WORK_MODE_Type workMode; /*!< touch_channel work mode select */\n+ TOUCH_RUN_MODE_Type runMode; /*!< 0-->single shot mode, 1-->continous mode */\n+ BL_Fun_Type ulpEn; /*!< ultra low power mode enable */\n+ BL_Fun_Type cycleEn; /*!< configure for low power mode with single shot, sleep for a time and then turn on */\n+ uint32_t sleepTime; /*!< Sleep clock_ana cycle, can save power by reduce turn on time */\n+ TOUCH_PCHARGE_LOW_Type pchargeLow; /*!< the max external cap leakage cycle */\n+ TOUCH_PCHARGE_HIGH_Type pchargeHigh; /*!< the max external cap charge-transfer cycle */\n+ TOUCH_LDO_VOLTAGE_Type ldoVol; /*!< TOUCH LDO voltage */\n+ TOUCH_VREF_VOLTAGE_Type vrefVol; /*!< TOUCH reference voltage control */\n+ TOUCH_HYSTERSIS_VOLTAGE_Type hystersisVol; /*!< TOUCH comparator hystersis voltage */\n+ TOUCH_COMPENSATION_CAP_Type compensationCap; /*!< TOUCH compensation cap control */\n+ BL_Fun_Type filterEn; /*!< touch_channel output data filter control, will do average(low pass filter) when enable */\n+ TOUCH_FILTER_ORDER_CTRL_Type filterCtrl; /*!< TOUCH filter long time average order control */\n+ BL_Fun_Type ltaEn; /*!< touch_channel long time average control, will do average(low pass filter) when enable */\n+ TOUCH_LTA_ORDER_CTRL_Type ltaCtrl; /*!< TOUCH LTA long time average order control */\n+ BL_Fun_Type dataHystersisEn; /*!< touch_channel hystersis data for touch action judgement, can reduce the false trigger */\n+ uint16_t dataHysCtrl; /*!< Hystersis data for data and dectection judgement */\n+} TOUCH_CFG_Type;\n+\n+/**\n+ * @brief TOUCH channel type definition\n+ */\n+typedef enum {\n+ TOUCH_CHANNEL_0, /*!< TOUCH channel 0 */\n+ TOUCH_CHANNEL_1, /*!< TOUCH channel 1 */\n+ TOUCH_CHANNEL_2, /*!< TOUCH channel 2 */\n+ TOUCH_CHANNEL_3, /*!< TOUCH channel 3 */\n+ TOUCH_CHANNEL_4, /*!< TOUCH channel 4 */\n+ TOUCH_CHANNEL_5, /*!< TOUCH channel 5 */\n+ TOUCH_CHANNEL_6, /*!< TOUCH channel 6 */\n+ TOUCH_CHANNEL_7, /*!< TOUCH channel 7 */\n+ TOUCH_CHANNEL_8, /*!< TOUCH channel 8 */\n+ TOUCH_CHANNEL_9, /*!< TOUCH channel 9 */\n+ TOUCH_CHANNEL_10, /*!< TOUCH channel 10 */\n+ TOUCH_CHANNEL_11, /*!< TOUCH channel 11 */\n+} TOUCH_CHANNEL_Type;\n+\n+/**\n+ * @brief TOUCH channel config type definition\n+ */\n+typedef enum {\n+ TOUCH_CHANNEL_HIGHZ_CFG_GND, /*!< channel tie to ground */\n+ TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ, /*!< channel HighZ output */\n+} TOUCH_CHANNEL_HIGHZ_CFG_Type;\n+\n+/**\n+ * @brief TOUCH channel configuration type definition\n+ */\n+typedef struct\n+{\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch0; /*!< TOUCH channel 0 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch1; /*!< TOUCH channel 1 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch2; /*!< TOUCH channel 2 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch3; /*!< TOUCH channel 3 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch4; /*!< TOUCH channel 4 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch5; /*!< TOUCH channel 5 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch6; /*!< TOUCH channel 6 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch7; /*!< TOUCH channel 7 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch8; /*!< TOUCH channel 8 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch9; /*!< TOUCH channel 9 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch10; /*!< TOUCH channel 10 HighZ config */\n+ TOUCH_CHANNEL_HIGHZ_CFG_Type ch11; /*!< TOUCH channel 11 HighZ config */\n+} TOUCH_CHANNEL_CFG_Type;\n+\n+/**\n+ * @brief TOUCH interrupt type definition\n+ */\n+typedef enum {\n+ TOUCH_INT_INTERRUPT, /*!< TOUCH has only one interrupt */\n+} TOUCH_INT_Type;\n+\n+/*@} end of group TOUCH_Public_Types */\n+\n+/** @defgroup TOUCH_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup TOUCH_ID_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_ID_TYPE(type) (((type) == TOUCH_ID_0))\n+\n+/** @defgroup TOUCH_RUN_MODE_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_RUN_MODE_TYPE(type) (((type) == TOUCH_RUN_MODE_SINGLE_SHOT) || \\\n+ ((type) == TOUCH_RUN_MODE_CONTINUE))\n+\n+/** @defgroup TOUCH_PCHARGE_LOW_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_PCHARGE_LOW_TYPE(type) (((type) == TOUCH_PCHARGE_LOW_127) || \\\n+ ((type) == TOUCH_PCHARGE_LOW_255) || \\\n+ ((type) == TOUCH_PCHARGE_LOW_511) || \\\n+ ((type) == TOUCH_PCHARGE_LOW_1023) || \\\n+ ((type) == TOUCH_PCHARGE_LOW_2047) || \\\n+ ((type) == TOUCH_PCHARGE_LOW_4095))\n+\n+/** @defgroup TOUCH_PCHARGE_HIGH_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_PCHARGE_HIGH_TYPE(type) (((type) == TOUCH_PCHARGE_HIGH_511) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_1023) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_2047) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_4095) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_8191) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_16383) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_32767) || \\\n+ ((type) == TOUCH_PCHARGE_HIGH_65535))\n+\n+/** @defgroup TOUCH_CLK_DIV_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_CLK_DIV_TYPE(type) (((type) == TOUCH_CLK_DIV_1) || \\\n+ ((type) == TOUCH_CLK_DIV_2) || \\\n+ ((type) == TOUCH_CLK_DIV_4) || \\\n+ ((type) == TOUCH_CLK_DIV_8) || \\\n+ ((type) == TOUCH_CLK_DIV_16) || \\\n+ ((type) == TOUCH_CLK_DIV_32) || \\\n+ ((type) == TOUCH_CLK_DIV_64) || \\\n+ ((type) == TOUCH_CLK_DIV_128))\n+\n+/** @defgroup TOUCH_CLK_SEL_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_CLK_SEL_TYPE(type) (((type) == TOUCH_CLK_SEL_32K) || \\\n+ ((type) == TOUCH_CLK_SEL_32M))\n+\n+/** @defgroup TOUCH_POWER_SEL_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_POWER_SEL_TYPE(type) (((type) == TOUCH_POWER_SEL_AON) || \\\n+ ((type) == TOUCH_POWER_SEL_INTERNAL_BG))\n+\n+/** @defgroup TOUCH_HYSTERSIS_VOLTAGE_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(type) (((type) == TOUCH_HYSTERSIS_VOLTAGE_30mV) || \\\n+ ((type) == TOUCH_HYSTERSIS_VOLTAGE_80mV))\n+\n+/** @defgroup TOUCH_LDO_VOLTAGE_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_LDO_VOLTAGE_TYPE(type) (((type) == TOUCH_LDO_VOLTAGE_0P6V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_0P8V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_1P0V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_1P2V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_1P4V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_1P6V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_1P8V) || \\\n+ ((type) == TOUCH_LDO_VOLTAGE_2P0V))\n+\n+/** @defgroup TOUCH_VREF_VOLTAGE_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_VREF_VOLTAGE_TYPE(type) (((type) == TOUCH_VREF_VOLTAGE_0P4V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_0P6V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_0P8V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_1P0V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_1P2V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_1P4V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_1P6V) || \\\n+ ((type) == TOUCH_VREF_VOLTAGE_1P8V))\n+\n+/** @defgroup TOUCH_COMPENSATION_CAP_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_COMPENSATION_CAP_TYPE(type) (((type) == TOUCH_COMPENSATION_CAP_12pF) || \\\n+ ((type) == TOUCH_COMPENSATION_CAP_13pF) || \\\n+ ((type) == TOUCH_COMPENSATION_CAP_14pF) || \\\n+ ((type) == TOUCH_COMPENSATION_CAP_15pF))\n+\n+/** @defgroup TOUCH_WORK_MODE_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_WORK_MODE_TYPE(type) (((type) == TOUCH_WORK_MODE_SELF_CAP) || \\\n+ ((type) == TOUCH_WORK_MODE_MUTUAL))\n+\n+/** @defgroup TOUCH_FILTER_ORDER_CTRL_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_FILTER_ORDER_CTRL_TYPE(type) (((type) == TOUCH_FILTER_ORDER_CTRL_0) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_1) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_2) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_3) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_4) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_5) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_6) || \\\n+ ((type) == TOUCH_FILTER_ORDER_CTRL_7))\n+\n+/** @defgroup TOUCH_LTA_ORDER_CTRL_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_LTA_ORDER_CTRL_TYPE(type) (((type) == TOUCH_LTA_ORDER_CTRL_0) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_1) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_2) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_3) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_4) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_5) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_6) || \\\n+ ((type) == TOUCH_LTA_ORDER_CTRL_7))\n+\n+/** @defgroup TOUCH_CHANNEL_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_CHANNEL_TYPE(type) (((type) == TOUCH_CHANNEL_0) || \\\n+ ((type) == TOUCH_CHANNEL_1) || \\\n+ ((type) == TOUCH_CHANNEL_2) || \\\n+ ((type) == TOUCH_CHANNEL_3) || \\\n+ ((type) == TOUCH_CHANNEL_4) || \\\n+ ((type) == TOUCH_CHANNEL_5) || \\\n+ ((type) == TOUCH_CHANNEL_6) || \\\n+ ((type) == TOUCH_CHANNEL_7) || \\\n+ ((type) == TOUCH_CHANNEL_8) || \\\n+ ((type) == TOUCH_CHANNEL_9) || \\\n+ ((type) == TOUCH_CHANNEL_10) || \\\n+ ((type) == TOUCH_CHANNEL_11))\n+\n+/** @defgroup TOUCH_CHANNEL_HIGHZ_CFG_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(type) (((type) == TOUCH_CHANNEL_HIGHZ_CFG_GND) || \\\n+ ((type) == TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ))\n+\n+/** @defgroup TOUCH_INT_TYPE\n+ * @{\n+ */\n+#define IS_TOUCH_INT_TYPE(type) (((type) == TOUCH_INT_INTERRUPT))\n+\n+/*@} end of group TOUCH_Public_Constants */\n+\n+/** @defgroup TOUCH_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Public_Macros */\n+\n+/** @defgroup TOUCH_Public_Functions\n+ * @{\n+ */\n+BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg);\n+BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel);\n+BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId);\n+BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId);\n+BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value);\n+uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh);\n+uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh);\n+uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh);\n+uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh);\n+BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId);\n+BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType);\n+BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType);\n+BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask);\n+BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh);\n+BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh);\n+BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh,\n+ intCallback_Type *cbFun);\n+\n+/*@} end of group TOUCH_Public_Functions */\n+\n+/*@} end of group TOUCH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_TOUCH_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..15ddd5bf5bf7424e7557bf1961c178bb80d650c1\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h\n@@ -0,0 +1,295 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_tzc_sec.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_TZC_SEC_H__\n+#define __BL808_TZC_SEC_H__\n+\n+#include \"tzc_sec_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TZC_SEC\n+ * @{\n+ */\n+\n+/** @defgroup TZC_SEC_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief TZC_SEC master type definition\n+ */\n+typedef enum {\n+ TZC_SEC_MASTER_LP, /*!< TZC Master:LP CPU */\n+ TZC_SEC_MASTER_MM_BUS, /*!< TZC Master:MM Bus */\n+ TZC_SEC_MASTER_USB, /*!< TZC Master:USB */\n+ TZC_SEC_MASTER_WIFI, /*!< TZC Master:WIFI */\n+ TZC_SEC_MASTER_CCI, /*!< TZC Master:CCI */\n+ TZC_SEC_MASTER_SDH, /*!< TZC Master:SDH */\n+ TZC_SEC_MASTER_EMAC, /*!< TZC Master:EMAC */\n+ TZC_SEC_MASTER_M0, /*!< TZC Master:M0 CPU */\n+ TZC_SEC_MASTER_DMA0, /*!< TZC Master:DMA0 */\n+ TZC_SEC_MASTER_DMA1, /*!< TZC Master:DMA1 */\n+ TZC_SEC_MASTER_LZ4, /*!< TZC Master:LZ4 */\n+ TZC_SEC_MASTER_D0, /*!< TZC Master:D0 */\n+ TZC_SEC_MASTER_BLAI, /*!< TZC Master:BLAI */\n+ TZC_SEC_MASTER_CODEC, /*!< TZC Master:CODEC */\n+ TZC_SEC_MASTER_DSP2, /*!< TZC Master:DSP2 */\n+ TZC_SEC_MASTER_2DDMA, /*!< TZC Master:2D DMA */\n+ TZC_SEC_MASTER_DMA2, /*!< TZC Master:DMA2 */\n+ TZC_SEC_MASTER_MAX, /*!< TZC Master max */\n+} TZC_SEC_Master_Type;\n+\n+/**\n+ * @brief TZC_SEC slave type definition\n+ */\n+typedef enum {\n+ TZC_SEC_SLAVE_GLB = 0, /*!< TZC Slave:GLB */\n+ TZC_SEC_SLAVE_MIX, /*!< TZC Slave:MIX */\n+ TZC_SEC_SLAVE_GPIP, /*!< TZC Slave:GPIP */\n+ TZC_SEC_SLAVE_DBG, /*!< TZC Slave:DBG */\n+ TZC_SEC_SLAVE_RSVD, /*!< TZC Slave:Reserved */\n+ TZC_SEC_SLAVE_TZC1, /*!< TZC Slave:TZC1 */\n+ TZC_SEC_SLAVE_TZC2, /*!< TZC Slave:TZC2 */\n+ TZC_SEC_SLAVE_RSVD2, /*!< TZC Slave:Reserved */\n+ TZC_SEC_SLAVE_CCI, /*!< TZC Slave:CCI */\n+ TZC_SEC_SLAVE_MCU_MISC, /*!< TZC Slave:MCU_MISC */\n+ TZC_SEC_SLAVE_PERIPHERAL, /*!< TZC Slave:Peripheral */\n+ TZC_SEC_SLAVE_EMI_MISC = 16, /*!< TZC Slave:emi misc */\n+ TZC_SEC_SLAVE_PSRAMA, /*!< TZC Slave:PSRAMA */\n+ TZC_SEC_SLAVE_PSRAMB, /*!< TZC Slave:PSRAMB */\n+ TZC_SEC_SLAVE_USB, /*!< TZC Slave:USB */\n+ TZC_SEC_SLAVE_RF2, /*!< TZC Slave:RF2 */\n+ TZC_SEC_SLAVE_AUDIO, /*!< TZC Slave:Audio */\n+ TZC_SEC_SLAVE_EF_CTRL, /*!< TZC Slave:efuse control*/\n+\n+ TZC_SEC_SLAVE_MM = 32, /*!< TZC Slave:MM */\n+ TZC_SEC_SLAVE_DMA0, /*!< TZC Slave:DMA0 */\n+ TZC_SEC_SLAVE_DMA1, /*!< TZC Slave:DMA1 */\n+ TZC_SEC_SLAVE_PWR, /*!< TZC Slave:Power */\n+\n+ TZC_SEC_SLAVE_MAX, /*!< TZC slave max*/\n+} TZC_SEC_Slave_Type;\n+\n+/**\n+ * @brief TZC_SEC MM slave type definition\n+ */\n+typedef enum {\n+ TZC_SEC_MM_SLAVE_MISC, /*!< TZC MM Slave:MISC */\n+ TZC_SEC_MM_SLAVE_DMA, /*!< TZC MM Slave:DMA */\n+ TZC_SEC_MM_SLAVE_UART, /*!< TZC MM Slave:UART */\n+ TZC_SEC_MM_SLAVE_I2C0, /*!< TZC MM Slave:I2C0 */\n+ TZC_SEC_MM_SLAVE_I2C1, /*!< TZC MM Slave:I2C1 */\n+ TZC_SEC_MM_SLAVE_IPC, /*!< TZC MM Slave:IPC */\n+ TZC_SEC_MM_SLAVE_2DDMA, /*!< TZC MM Slave:2DDMA */\n+ TZC_SEC_MM_SLAVE_CLKRST, /*!< TZC MM Slave:Clock and reset */\n+ TZC_SEC_MM_SLAVE_SPI, /*!< TZC MM Slave:SPI */\n+ TZC_SEC_MM_SLAVE_TIMER, /*!< TZC MM Slave:Timer */\n+ TZC_SEC_MM_SLAVE_RSVD1, /*!< TZC MM Slave:reserved1 */\n+ TZC_SEC_MM_SLAVE_RSVD2, /*!< TZC MM Slave:reserved2 */\n+ TZC_SEC_MM_SLAVE_RSVD3, /*!< TZC MM Slave:reserved3 */\n+ TZC_SEC_MM_SLAVE_RSVD4, /*!< TZC MM Slave:reserved4 */\n+ TZC_SEC_MM_SLAVE_RSVD5, /*!< TZC MM Slave:reserved5 */\n+ TZC_SEC_MM_SLAVE_UHS_PSRAM, /*!< TZC MM Slave:uhs psram */\n+\n+ TZC_SEC_MM_SLAVE_DSP2_MISC = 16, /*!< TZC MM Slave:DSP2 MISC */\n+ TZC_SEC_MM_SLAVE_DSP2_TOP, /*!< TZC MM Slave:DSP2 TOP */\n+ TZC_SEC_MM_SLAVE_DVP_MISC, /*!< TZC MM Slave:DVP MISC */\n+ TZC_SEC_MM_SLAVE_OSD_A, /*!< TZC MM Slave:OSD_A */\n+ TZC_SEC_MM_SLAVE_OSD_B, /*!< TZC MM Slave:OSD_B */\n+ TZC_SEC_MM_SLAVE_OSD_DP, /*!< TZC MM Slave:OSD_DP */\n+ TZC_SEC_MM_SLAVE_AWB3_CORE, /*!< TZC MM Slave:AWB3 core */\n+ TZC_SEC_MM_SLAVE_AWB3_SRAM, /*!< TZC MM Slave:AWB3 SRAM */\n+ TZC_SEC_MM_SLAVE_RSVD6, /*!< TZC MM Slave:Reserved */\n+ TZC_SEC_MM_SLAVE_DSP2_AE_SRAM, /*!< TZC MM Slave:DSP2 AE SRAM */\n+ TZC_SEC_MM_SLAVE_MIPI, /*!< TZC MM Slave:MIPI(DSI & CSI )*/\n+ TZC_SEC_MM_SLAVE_DBI, /*!< TZC MM Slave:DBI */\n+ TZC_SEC_MM_SLAVE_DSP2_AWB_SRAM, /*!< TZC MM Slave:DSP2 AWB SRAM */\n+\n+ TZC_SEC_MM_SLAVE_CODEC_MISC = 32, /*!< TZC MM Slave:Codec misc */\n+ TZC_SEC_MM_SLAVE_MJPEG, /*!< TZC MM Slave:MJPEG */\n+ TZC_SEC_MM_SLAVE_VIDEO, /*!< TZC MM Slave:Video */\n+ TZC_SEC_MM_SLAVE_MJPEG_DEC, /*!< TZC MM Slave:MJPEG Decoder */\n+ TZC_SEC_MM_SLAVE_BLAI, /*!< TZC MM Slave:BLAI */\n+\n+ TZC_SEC_MM_SLAVE_MAX, /*!< TZC MM slave max*/\n+} TZC_SEC_MM_Slave_Type;\n+\n+/**\n+ * @brief TZC_SEC GLB Ctrl type definition\n+ */\n+typedef enum {\n+ TZC_SEC_GLB_CTRL_POR_RESET, /*!< TZC GLB Ctrl: Power on reset */\n+ TZC_SEC_GLB_CTRL_CPU_RESET, /*!< TZC GLB Ctrl: CPU reset */\n+ TZC_SEC_GLB_CTRL_SYS_RESET, /*!< TZC GLB Ctrl: System reset */\n+ TZC_SEC_GLB_CTRL_CCPU_RESET, /*!< TZC GLB Ctrl: Coupled CPU reset */\n+ TZC_SEC_GLB_CTRL_MISC, /*!< TZC GLB Ctrl: MISC */\n+ TZC_SEC_GLB_CTRL_SRAM, /*!< TZC GLB Ctrl: SRAM */\n+ TZC_SEC_GLB_CTRL_SWRESET, /*!< TZC GLB Ctrl: Software reset */\n+ TZC_SEC_GLB_CTRL_BMX, /*!< TZC GLB Ctrl: BMX */\n+ TZC_SEC_GLB_CTRL_DBG, /*!< TZC GLB Ctrl: DBG */\n+ TZC_SEC_GLB_CTRL_MBIST, /*!< TZC GLB Ctrl: MBIST */\n+ TZC_SEC_GLB_CTRL_CLK, /*!< TZC GLB Ctrl: CLK */\n+ TZC_SEC_GLB_CTRL_INT, /*!< TZC GLB Ctrl: Interrupt */\n+ TZC_SEC_GLB_CTRL_PWR, /*!< TZC GLB Ctrl: Power */\n+ TZC_SEC_GLB_CTRL_MAX,\n+} TZC_SEC_GLB_Ctrl_Type;\n+\n+/**\n+ * @brief TZC_SEC MM GLB Ctrl type definition\n+ */\n+typedef enum {\n+ TZC_SEC_MM_GLB_CTRL_POR_RESET, /*!< TZC MM GLB Ctrl: Power on reset */\n+ TZC_SEC_MM_GLB_CTRL_CPU_RESET, /*!< TZC MM GLB Ctrl: CPU reset */\n+ TZC_SEC_MM_GLB_CTRL_SYS_RESET, /*!< TZC MM GLB Ctrl: System reset */\n+ TZC_SEC_MM_GLB_CTRL_CCPU_RESET, /*!< TZC MM GLB Ctrl: Coupled CPU reset */\n+ TZC_SEC_MM_GLB_CTRL_RSVD1, /*!< TZC MM GLB Ctrl: Reserved */\n+ TZC_SEC_MM_GLB_CTRL_SRAM, /*!< TZC MM GLB Ctrl: SRAM */\n+ TZC_SEC_MM_GLB_CTRL_SWRESET, /*!< TZC MM GLB Ctrl: Software reset */\n+ TZC_SEC_MM_GLB_CTRL_RSVD2, /*!< TZC MM GLB Ctrl: Reserved */\n+ TZC_SEC_MM_GLB_CTRL_RSVD3, /*!< TZC MM GLB Ctrl: Reserved */\n+ TZC_SEC_MM_GLB_CTRL_RSVD4, /*!< TZC MM GLB Ctrl: Reserved */\n+ TZC_SEC_MM_GLB_CTRL_CLK, /*!< TZC MM GLB Ctrl: CLK */\n+ TZC_SEC_MM_GLB_CTRL_MAX,\n+} TZC_SEC_MM_GLB_Ctrl_Type;\n+\n+/**\n+ * @brief TZC_SEC SE Ctrl type definition\n+ */\n+typedef enum {\n+ TZC_SEC_SE_CTRL_SHA, /*!< TZC SE Ctrl: SHA */\n+ TZC_SEC_SE_CTRL_AES, /*!< TZC SE Ctrl: AES */\n+ TZC_SEC_SE_CTRL_TRNG, /*!< TZC SE Ctrl: TRNG */\n+ TZC_SEC_SE_CTRL_PKA, /*!< TZC SE Ctrl: PKA */\n+ TZC_SEC_SE_CTRL_CDET, /*!< TZC SE Ctrl: CEDT */\n+ TZC_SEC_SE_CTRL_GMAC, /*!< TZC SE Ctrl: GMAC */\n+ TZC_SEC_SE_CTRL_MAX,\n+} TZC_SEC_SE_Ctrl_Type;\n+\n+/**\n+ * @brief TZC_SEC SF Ctrl type definition\n+ */\n+typedef enum {\n+ TZC_SEC_SF_CTRL_CR, /*!< TZC SF Ctrl: control register */\n+ TZC_SEC_SF_CTRL_SEC, /*!< TZC SF Ctrl: security register */\n+ TZC_SEC_SF_CTRL_MAX,\n+} TZC_SEC_SF_Ctrl_Type;\n+\n+/**\n+ * @brief TZC_SEC SE Ctrl mode definition\n+ */\n+typedef enum {\n+ TZC_SEC_SE_MODE_ARB, /*!< TZC SE Ctrl mode: cpus arbitrate */\n+ TZC_SEC_SE_MODE_TZC, /*!< TZC SE Ctrl: TZC control as group */\n+} TZC_SEC_SE_Ctrl_Mode;\n+\n+/**\n+ * @brief TZC_SEC SF Ctrl mode definition\n+ */\n+typedef enum {\n+ TZC_SEC_SF_MODE_ARB, /*!< TZC SF Ctrl mode: cpus arbitrate */\n+ TZC_SEC_SF_MODE_TZC, /*!< TZC SF Ctrl: TZC control as group */\n+} TZC_SEC_SF_Ctrl_Mode;\n+\n+/**\n+ * @brief TZC_SEC Auth group\n+ */\n+typedef enum {\n+ TZC_SEC_AUTH_GRP_0, /*!< TZC auth group 0 */\n+ TZC_SEC_AUTH_GRP_1, /*!< TZC auth group 1 */\n+} TZC_SEC_Auth_Group;\n+\n+/**\n+ * @brief TZC_SEC Advance Auth group\n+ */\n+typedef enum {\n+ TZC_SEC_ADV_AUTH_GRP_0_IBUS = 0x01, /*!< TZC advance auth group 0 IBUS */\n+ TZC_SEC_ADV_AUTH_GRP_0_DBUS = 0x02, /*!< TZC advance auth group 0 DBUS */\n+ TZC_SEC_ADV_AUTH_GRP_1_IBUS = 0x04, /*!< TZC advance auth group 1 IBUS */\n+ TZC_SEC_ADV_AUTH_GRP_1_DBUS = 0x08, /*!< TZC advance auth group 1 DBUS */\n+} TZC_SEC_Advance_Auth_Group;\n+\n+/*@} end of group TZC_SEC_Public_Types */\n+\n+/** @defgroup TZC_SEC_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group TZC_SEC_Public_Constants */\n+\n+/** @defgroup TZC_SEC_Public_Macros\n+ * @{\n+ */\n+\n+#define TZC_SEC_MAX_AUTH_GRP 3\n+/*@} end of group TZC_SEC_Public_Macros */\n+\n+/** @defgroup TZC_SEC_Public_Functions\n+ * @{\n+ */\n+void Tzc_Sec_Set_Sboot_Done(void);\n+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group);\n+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group);\n+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group);\n+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group);\n+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group);\n+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group);\n+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group);\n+void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_PSRAMA_Access_Release(void);\n+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_PSRAMB_Access_Release(void);\n+void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);\n+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);\n+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);\n+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group);\n+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group);\n+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue);\n+/*@} end of group TZC_SEC_Public_Functions */\n+\n+/*@} end of group TZC_SEC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_TZC_SEC_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1dd38360d3ce6f08b1bfa57cac7d8ecbdee2e382\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h\n@@ -0,0 +1,359 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_uart.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_UART_H__\n+#define __BL808_UART_H__\n+\n+#include \"uart_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup UART\n+ * @{\n+ */\n+\n+/** @defgroup UART_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief UART port type definition\n+ */\n+typedef enum {\n+ UART0_ID, /*!< UART0 port define */\n+ UART1_ID, /*!< UART1 port define */\n+ UART2_ID, /*!< UART2 port define */\n+ UART0_MM_ID, /*!< MM system UART0 port define */\n+ UART_ID_MAX, /*!< UART MAX ID define */\n+} UART_ID_Type;\n+\n+/**\n+ * @brief UART direction type definition\n+ */\n+typedef enum {\n+ UART_TX, /*!< UART TX Direction */\n+ UART_RX, /*!< UART RX Direction */\n+ UART_TXRX, /*!< UART TX and RX Direction */\n+} UART_Direction_Type;\n+\n+/**\n+ * @brief UART parity type definition\n+ */\n+typedef enum {\n+ UART_PARITY_NONE, /*!< UART parity none define */\n+ UART_PARITY_ODD, /*!< UART parity odd define */\n+ UART_PARITY_EVEN, /*!< UART parity even define */\n+} UART_Parity_Type;\n+\n+/**\n+ * @brief UART data bits type definiton\n+ */\n+typedef enum {\n+ UART_DATABITS_5, /*!< UART data bits length:5 bits */\n+ UART_DATABITS_6, /*!< UART data bits length:6 bits */\n+ UART_DATABITS_7, /*!< UART data bits length:7 bits */\n+ UART_DATABITS_8, /*!< UART data bits length:8 bits */\n+} UART_DataBits_Type;\n+\n+/**\n+ * @brief UART stop bits type definiton\n+ */\n+typedef enum {\n+ UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */\n+ UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */\n+ UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */\n+ UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */\n+} UART_StopBits_Type;\n+\n+/**\n+ * @brief UART each data byte is send out LSB-first or MSB-first type definiton\n+ */\n+typedef enum {\n+ UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */\n+ UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */\n+} UART_ByteBitInverse_Type;\n+\n+/**\n+ * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton\n+ */\n+typedef enum {\n+ UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */\n+ UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */\n+} UART_AutoBaudDetection_Type;\n+\n+/**\n+ * @brief UART RS-485 mode DE pin polarity definiton\n+ */\n+typedef enum {\n+ UART_RS485_DE_ACTIVE_LOW, /*!< UART DE is active-low */\n+ UART_RS485_DE_ACTIVE_HIGH, /*!< UART DE is active-high */\n+} UART_RS485Polarity_Type;\n+\n+/**\n+ * @brief UART interrupt type definition\n+ */\n+typedef enum {\n+ UART_INT_TX_END, /*!< UART tx transfer end interrupt */\n+ UART_INT_RX_END, /*!< UART rx transfer end interrupt */\n+ UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */\n+ UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */\n+ UART_INT_RTO, /*!< UART rx time-out interrupt */\n+ UART_INT_PCE, /*!< UART rx parity check error interrupt */\n+ UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */\n+ UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */\n+ UART_INT_LSE, /*!< UART rx lin mode sync field error interrupt */\n+ UART_INT_BCR, /*!< UART rx byte count reached interrupt */\n+ UART_INT_STARTBIT, /*!< UART rx auto baudrate detection finish interrupt using start bit */\n+ UART_INT_0X55, /*!< UART rx auto baudrate detection finish interrupt using codeword 0x55 */\n+ UART_INT_ALL, /*!< All the interrupt */\n+} UART_INT_Type;\n+\n+/**\n+ * @brief UART overflow or underflow type definition\n+ */\n+typedef enum {\n+ UART_TX_OVERFLOW, /*!< UART tx fifo overflow */\n+ UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */\n+ UART_RX_OVERFLOW, /*!< UART rx fifo overflow */\n+ UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */\n+} UART_Overflow_Type;\n+\n+/**\n+ * @brief UART configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint32_t uartClk; /*!< Uart module clock */\n+ uint32_t baudRate; /*!< Uart baudrate */\n+ UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */\n+ UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */\n+ UART_Parity_Type parity; /*!< Uart parity check type */\n+ BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */\n+ BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */\n+ BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */\n+ BL_Fun_Type txSoftwareControl; /*!< Enable or disable tx output SW control mode */\n+ BL_Fun_Type txLinMode; /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */\n+ BL_Fun_Type rxLinMode; /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */\n+ uint8_t txBreakBitCnt; /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at\n+ least 13 bit times */\n+ UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */\n+} UART_CFG_Type;\n+\n+/**\n+ * @brief UART FIFO configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */\n+ uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */\n+ BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */\n+ BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */\n+} UART_FifoCfg_Type;\n+\n+/**\n+ * @brief UART infrared configuration structure type definition\n+ */\n+typedef struct\n+{\n+ BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */\n+ BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */\n+ BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */\n+ BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */\n+ uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */\n+ uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */\n+ uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */\n+} UART_IrCfg_Type;\n+\n+/*@} end of group UART_Public_Types */\n+\n+/** @defgroup UART_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup UART_ID_TYPE\n+ * @{\n+ */\n+#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \\\n+ ((type) == UART1_ID) || \\\n+ ((type) == UART2_ID) || \\\n+ ((type) == UART0_MM_ID) || \\\n+ ((type) == UART_ID_MAX))\n+\n+/** @defgroup UART_DIRECTION_TYPE\n+ * @{\n+ */\n+#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \\\n+ ((type) == UART_RX) || \\\n+ ((type) == UART_TXRX))\n+\n+/** @defgroup UART_PARITY_TYPE\n+ * @{\n+ */\n+#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \\\n+ ((type) == UART_PARITY_ODD) || \\\n+ ((type) == UART_PARITY_EVEN))\n+\n+/** @defgroup UART_DATABITS_TYPE\n+ * @{\n+ */\n+#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \\\n+ ((type) == UART_DATABITS_6) || \\\n+ ((type) == UART_DATABITS_7) || \\\n+ ((type) == UART_DATABITS_8))\n+\n+/** @defgroup UART_STOPBITS_TYPE\n+ * @{\n+ */\n+#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \\\n+ ((type) == UART_STOPBITS_1_5) || \\\n+ ((type) == UART_STOPBITS_2))\n+\n+/** @defgroup UART_BYTEBITINVERSE_TYPE\n+ * @{\n+ */\n+#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \\\n+ ((type) == UART_MSB_FIRST))\n+\n+/** @defgroup UART_AUTOBAUDDETECTION_TYPE\n+ * @{\n+ */\n+#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \\\n+ ((type) == UART_AUTOBAUD_STARTBIT))\n+\n+/** @defgroup UART_RS485POLARITY_TYPE\n+ * @{\n+ */\n+#define IS_UART_RS485POLARITY_TYPE(type) (((type) == UART_RS485_DE_ACTIVE_LOW) || \\\n+ ((type) == UART_RS485_DE_ACTIVE_HIGH))\n+\n+/** @defgroup UART_INT_TYPE\n+ * @{\n+ */\n+#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \\\n+ ((type) == UART_INT_RX_END) || \\\n+ ((type) == UART_INT_TX_FIFO_REQ) || \\\n+ ((type) == UART_INT_RX_FIFO_REQ) || \\\n+ ((type) == UART_INT_RTO) || \\\n+ ((type) == UART_INT_PCE) || \\\n+ ((type) == UART_INT_TX_FER) || \\\n+ ((type) == UART_INT_RX_FER) || \\\n+ ((type) == UART_INT_LSE) || \\\n+ ((type) == UART_INT_BCR) || \\\n+ ((type) == UART_INT_STARTBIT) || \\\n+ ((type) == UART_INT_0X55) || \\\n+ ((type) == UART_INT_ALL))\n+\n+/** @defgroup UART_OVERFLOW_TYPE\n+ * @{\n+ */\n+#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \\\n+ ((type) == UART_TX_UNDERFLOW) || \\\n+ ((type) == UART_RX_OVERFLOW) || \\\n+ ((type) == UART_RX_UNDERFLOW))\n+\n+/*@} end of group UART_Public_Constants */\n+\n+/** @defgroup UART_Public_Macros\n+ * @{\n+ */\n+#define UART_RX_FIFO_SIZE 128\n+#define UART_TX_FIFO_SIZE 128\n+#define UART_DEFAULT_RECV_TIMEOUT 80\n+\n+/*@} end of group UART_Public_Macros */\n+\n+/** @defgroup UART_Public_Functions\n+ * @{\n+ */\n+\n+/**\n+ * @brief UART Functions\n+ */\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER)\n+void UART0_IRQHandler(void);\n+void UART1_IRQHandler(void);\n+void UART2_IRQHandler(void);\n+void UART3_IRQHandler(void);\n+void UART4_IRQHandler(void);\n+#endif\n+BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate);\n+BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg);\n+BL_Err_Type UART_DeInit(UART_ID_Type uartId);\n+BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg);\n+BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg);\n+BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct);\n+BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct);\n+BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length);\n+BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length);\n+BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time);\n+BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count);\n+BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt);\n+BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);\n+BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);\n+BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);\n+BL_Err_Type UART_SetTxValue(UART_ID_Type uartId);\n+BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId);\n+BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun);\n+BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud);\n+BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError);\n+BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width);\n+BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity);\n+BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId);\n+BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId);\n+BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask);\n+BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType);\n+BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun);\n+BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len);\n+BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len);\n+uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen);\n+uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);\n+uint16_t UART_GetRxByteCount(UART_ID_Type uartId);\n+uint8_t UART_GetTxFifoCount(UART_ID_Type uartId);\n+uint8_t UART_GetRxFifoCount(UART_ID_Type uartId);\n+BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType);\n+BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId);\n+BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId);\n+BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow);\n+\n+/*@} end of group UART_Public_Functions */\n+\n+/*@} end of group UART */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_UART_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..cecf66282ce9539f89db1809da3dfdef13f9217f\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h\n@@ -0,0 +1,46 @@\n+#ifndef __UHS_PHY_H__\n+#define __UHS_PHY_H__\n+\n+#include \"bl808_common.h\"\n+// /** @addtogroup Configuration_section_for_RISCV\n+// * @{\n+// */\n+// #define BL_RD_WORD(addr) (*((volatile uint32_t*)(addr)))\n+// #define BL_WR_WORD(addr,val) ((*(volatile uint32_t*)(addr))=(val))\n+// #define BL_RD_SHORT(addr) (*((volatile uint16_t*)(addr)))\n+// #define BL_WR_SHORT(addr,val) ((*(volatile uint16_t*)(addr))=(val))\n+// #define BL_RD_BYTE(addr) (*((volatile uint8_t*)(addr)))\n+// #define BL_WR_BYTE(addr,val) ((*(volatile uint8_t*)(addr))=(val))\n+// #define BL_RDWD_FRM_BYTEP(p) ((p[3]<<24)|(p[2]<<16)|(p[1]<<8)|(p[0]))\n+// #define BL_WRWD_TO_BYTEP(p,val) {p[0]=val&0xff;p[1]=(val>>8)&0xff;p[2]=(val>>16)&0xff;p[3]=(val>>24)&0xff;}\n+// /**\n+// * @brief Register access macro\n+// */\n+// #define BL_RD_REG16(addr,regname) BL_RD_SHORT(addr+regname##_OFFSET)\n+// #define BL_WR_REG16(addr,regname,val) BL_WR_SHORT(addr+regname##_OFFSET,val)\n+// #define BL_RD_REG(addr,regname) BL_RD_WORD(addr+regname##_OFFSET)\n+// #define BL_WR_REG(addr,regname,val) BL_WR_WORD(addr+regname##_OFFSET,val)\n+// #define BL_SET_REG_BIT(val,bitname) ( (val) |(1U<<bitname##_POS))\n+// #define BL_CLR_REG_BIT(val,bitname) ( (val) & bitname##_UMSK )\n+// #define BL_GET_REG_BITS_VAL(val,bitname) ( ((val) & bitname##_MSK) >> bitname##_POS )\n+// #define BL_SET_REG_BITS_VAL(val,bitname,bitval) ( ((val)&bitname##_UMSK) | ((uint32_t)(bitval)<<bitname##_POS) )\n+// #define BL_IS_REG_BIT_SET(val,bitname) ( ((val)&(1U<<(bitname##_POS))) !=0 )\n+// #define BL_DRV_DUMMY {__NOP();__NOP();__NOP();__NOP();}\n+\n+enum {\n+ UHS_LATENCY_CODE_533 = 3, // \"0\"\n+ UHS_LATENCY_CODE_800 = 3, // \"1\"\n+ UHS_LATENCY_CODE_933 = 3, // \"2\"\n+ UHS_LATENCY_CODE_1066 = 3,\n+ UHS_LATENCY_CODE_RESERVED = 3, //\"4\"\n+ UHS_LATENCY_CODE_400 = 3, //\"5\"\n+ UHS_LATENCY_CODE_333 = 3, //\"6\"\n+ UHS_LATENCY_CODE_200 = 3, //\"7\"\n+};\n+\n+// function call \n+void uhs_phy_init(uint32_t datarate); \n+void uhs_phy_pwr_down(void);\n+void soft_reset(void);\n+\n+#endif // __UHS_PHY_H__\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_usb.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_usb.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_usb.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7ab853e4365cd3e8282a192af080f9dffce5d8d5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_usb.h\n@@ -0,0 +1,643 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_usb.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_USB_H__\n+#define __BL808_USB_H__\n+\n+#include \"usb_reg.h\"\n+#include \"bl808_common.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup USB\n+ * @{\n+ */\n+\n+/** @defgroup USB_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief USB LPM response type definition\n+ */\n+typedef enum {\n+ USB_LPM_RESP_NYET = 0, /*!< response LPM with NYET */\n+ USB_LPM_RESP_ACK = 1, /*!< response LPM with ACK */\n+} USB_LPM_RESP_Type;\n+\n+/**\n+ * @brief USB LPM configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t lpmEn; /*!< response LPM or not */\n+ USB_LPM_RESP_Type resp; /*!< response LPM with ACK or NAK */\n+ uint8_t minBesl; /*!< BESL min value */\n+ uint8_t maxBesl; /*!< BESL max value */\n+ uint8_t lpmWakeUpEn; /*!< LPM wakeup enable */\n+} USB_LPM_Cfg_Type;\n+\n+/**\n+ * @brief USB global interrupt type definition\n+ */\n+typedef enum {\n+ USB_GLOBAL_INT_DEV = 0, /*!< USB device interrupt type */\n+ USB_GLOBAL_INT_OTG = 1, /*!< USB OTG interrupt type */\n+ USB_GLOBAL_INT_HC = 2, /*!< USB host interrupt type */\n+} USB_GLOBAL_INT_Type;\n+\n+/**\n+ * @brief USB global interrupt type definition\n+ */\n+typedef enum {\n+ USB_DEVICE_SPEED_FULL_SPEED = 0, /*!< USB device interrupt type */\n+ USB_DEVICE_SPEED_HIGH_SPEED = 1, /*!< USB OTG interrupt type */\n+} USB_DEVICE_SPEED_Type;\n+\n+/**\n+ * @brief USB normal configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t forceFullSpeed; /*!< force device to full speed */\n+ uint8_t chipEn; /*!< chip enable */\n+ uint8_t swRst; /*!< software reset */\n+ uint8_t remoteWakeupEn; /*!< remote wakeup capability enable */\n+ uint32_t rstTimeOut; /*!< software reset timeout count */\n+} USB_NORMAL_Cfg_Type;\n+\n+/**\n+ * @brief USB FIFO empty type definition\n+ */\n+typedef enum {\n+ USB_FIFO_EMPTY_FIFO_0 = 8, /*!< USB FIFO 0 empty type */\n+ USB_FIFO_EMPTY_FIFO_1 = 9, /*!< USB FIFO 1 empty type */\n+ USB_FIFO_EMPTY_FIFO_2 = 10, /*!< USB FIFO 2 empty type */\n+ USB_FIFO_EMPTY_FIFO_3 = 11, /*!< USB FIFO 3 empty type */\n+} USB_FIFO_EMPTY_Type;\n+\n+/**\n+ * @brief USB endpoint ID type definition\n+ */\n+typedef enum {\n+ USB_Endpoint_0 = 0, /*!< USB endpoint ID 0 */\n+ USB_Endpoint_1 = 1, /*!< USB endpoint ID 1 */\n+ USB_Endpoint_2 = 2, /*!< USB endpoint ID 2 */\n+ USB_Endpoint_3 = 3, /*!< USB endpoint ID 3 */\n+ USB_Endpoint_4 = 4, /*!< USB endpoint ID 4 */\n+ USB_Endpoint_5 = 5, /*!< USB endpoint ID 5 */\n+ USB_Endpoint_6 = 6, /*!< USB endpoint ID 6 */\n+ USB_Endpoint_7 = 7, /*!< USB endpoint ID 7 */\n+ USB_Endpoint_8 = 8, /*!< USB endpoint ID 8 */\n+} USB_Endpoint_Type;\n+\n+/**\n+ * @brief USB FIFO ID type definition\n+ */\n+typedef enum {\n+ USB_FIFO_0 = 0, /*!< USB endpoint ID 0 */\n+ USB_FIFO_1 = 1, /*!< USB endpoint ID 1 */\n+ USB_FIFO_2 = 2, /*!< USB endpoint ID 2 */\n+ USB_FIFO_3 = 3, /*!< USB endpoint ID 3 */\n+} USB_FIFO_Type;\n+\n+/**\n+ * @brief USB FIFO direction type definition\n+ */\n+typedef enum {\n+ USB_FIFO_DIR_OUT = 0, /*!< USB FIFO direction out */\n+ USB_FIFO_DIR_IN = 1, /*!< USB FIFO direction in */\n+ USB_FIFO_DIR_BID = 2, /*!< USB FIFO direction bidirectional */\n+} USB_FIFO_DIR_Type;\n+\n+/**\n+ * @brief USB FIFO block max size type definition\n+ */\n+typedef enum {\n+ USB_FIFO_BLOCK_MAX_SIZE_512 = 0, /*!< USB FIFO block max packet size 512 */\n+ USB_FIFO_BLOCK_MAX_SIZE_1024 = 1, /*!< USB FIFO block max packet size 1024 */\n+} USB_FIFO_BLOCK_MAX_SIZE_Type;\n+\n+/**\n+ * @brief USB FIFO block count type definition\n+ */\n+typedef enum {\n+ USB_FIFO_BLOCK_CNT_SINGLE_BLOCK = 0, /*!< USB FIFO single block */\n+ USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS = 1, /*!< USB FIFO double block */\n+ USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS = 2, /*!< USB FIFO triple block */\n+} USB_FIFO_BLOCK_CNT_Type;\n+\n+/**\n+ * @brief USB FIFO transfer type definition\n+ */\n+typedef enum {\n+ USB_FIFO_TRANSFER_RSV = 0, /*!< USB FIFO transfer type is reserved */\n+ USB_FIFO_TRANSFER_ISO = 1, /*!< USB FIFO transfer type is isochronous */\n+ USB_FIFO_TRANSFER_BULK = 2, /*!< USB FIFO transfer type is bulk */\n+ USB_FIFO_TRANSFER_INT = 3, /*!< USB FIFO transfer type is interrupt */\n+} USB_FIFO_TRANSFER_Type;\n+\n+/**\n+ * @brief USB FIFO configuration structure type definition\n+ */\n+typedef struct\n+{\n+ uint8_t enable; /*!< FIFO enable or disable */\n+ USB_FIFO_DIR_Type dir; /*!< FIFO direction */\n+ USB_Endpoint_Type epID; /*!< Endpoint number of FIFO */\n+ USB_FIFO_BLOCK_MAX_SIZE_Type blockSize; /*!< FIFO block max size */\n+ USB_FIFO_BLOCK_CNT_Type blockType; /*!< FIFO block type */\n+ USB_FIFO_TRANSFER_Type fifoType; /*!< FIFO transfer type */\n+} USB_FIFO_Cfg_Type;\n+\n+/**\n+ * @brief USB DMA target FIFO type definition\n+ */\n+typedef enum {\n+ USB_DMA_TARGET_FIFO_CTRL = 0, /*!< USB DMA target FIFO is control FIFO */\n+ USB_DMA_TARGET_FIFO_0 = 1, /*!< USB DMA target FIFO is FIFO 0 */\n+ USB_DMA_TARGET_FIFO_1 = 2, /*!< USB DMA target FIFO is FIFO 1 */\n+ USB_DMA_TARGET_FIFO_2 = 3, /*!< USB DMA target FIFO is FIFO 2 */\n+ USB_DMA_TARGET_FIFO_3 = 4, /*!< USB DMA target FIFO is FIFO 3 */\n+} USB_DMA_TARGET_FIFO_Type;\n+\n+/**\n+ * @brief USB DMA transfer type definition\n+ */\n+typedef enum {\n+ USB_DMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB DMA transfer type is FIFO to memory */\n+ USB_DMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB DMA transfer type is memory to FIFO */\n+ USB_DMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB DMA transfer type is FIFO to FIFO */\n+} USB_DMA_TRANS_DIR_Type;\n+\n+/**\n+ * @brief USB DMA configuration structure type definition\n+ */\n+typedef struct\n+{\n+ USB_DMA_TRANS_DIR_Type dir; /*!< USB DMA transfer direction */\n+ uint32_t memAddr; /*!< USB DMA target memory address */\n+ uint32_t length; /*!< USB DMA transfer length */\n+} USB_DMA_Cfg_Type;\n+\n+/**\n+ * @brief USB Virtual DMA target FIFO type definition\n+ */\n+typedef enum {\n+ USB_VDMA_TARGET_FIFO_CTRL = 0, /*!< USB VDMA target FIFO is control FIFO */\n+ USB_VDMA_TARGET_FIFO_0 = 1, /*!< USB VDMA target FIFO is FIFO 0 */\n+ USB_VDMA_TARGET_FIFO_1 = 2, /*!< USB VDMA target FIFO is FIFO 1 */\n+ USB_VDMA_TARGET_FIFO_2 = 3, /*!< USB VDMA target FIFO is FIFO 2 */\n+ USB_VDMA_TARGET_FIFO_3 = 4, /*!< USB VDMA target FIFO is FIFO 3 */\n+} USB_VDMA_TARGET_FIFO_Type;\n+\n+/**\n+ * @brief USB Virtual DMA transfer type definition\n+ */\n+typedef enum {\n+ USB_VDMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB VDMA transfer type is FIFO to memory */\n+ USB_VDMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB VDMA transfer type is memory to FIFO */\n+ USB_VDMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB VDMA transfer type is FIFO to FIFO */\n+} USB_VDMA_TRANS_DIR_Type;\n+\n+/**\n+ * @brief USB Virtual DMA configuration structure type definition\n+ */\n+typedef struct\n+{\n+ USB_VDMA_TRANS_DIR_Type dir; /*!< USB VDMA transfer direction */\n+ uint32_t memAddr; /*!< USB VDMA target memory address */\n+ uint32_t length; /*!< USB VDMA transfer length */\n+} USB_VDMA_Cfg_Type;\n+\n+/**\n+ * @brief USB interrupt group type definition\n+ */\n+typedef enum {\n+ USB_GRP_INT_G0 = 0, /*!< USB group 0 interrupt type */\n+ USB_GRP_INT_G1 = 1, /*!< USB group 1 interrupt type */\n+ USB_GRP_INT_G2 = 2, /*!< USB group 2 interrupt type */\n+ USB_GRP_INT_G3 = 3, /*!< USB group 3 interrupt type */\n+ USB_GRP_INT_G4 = 4, /*!< USB group 4 interrupt type */\n+} USB_GRP_INT_Type;\n+\n+/**\n+ * @brief USB interrupt group0 type definition\n+ */\n+typedef enum {\n+ USB_SUB_GRP0_INT_CX_SETUP = 0, /*!< group0 endpoint 0 setup data received */\n+ USB_SUB_GRP0_INT_CX_IN = 1, /*!< group0 endpoint 0 IN */\n+ USB_SUB_GRP0_INT_CX_OUT = 2, /*!< group0 endpoint 0 OUT */\n+ USB_SUB_GRP0_INT_CX_COMFAIL = 3, /*!< group0 endpoint 0 COMFAIL */\n+ USB_SUB_GRP0_INT_CX_COMABORT = 4, /*!< group0 endpoint 0 COMABORT */\n+ USB_SUB_GRP1_INT_F0_OUT = 5, /*!< group1 OUT interrupt of FIFO 0 */\n+ USB_SUB_GRP1_INT_F0_SPK = 6, /*!< group1 short packet interrupt of FIFO 0 */\n+ USB_SUB_GRP1_INT_F1_OUT = 7, /*!< group1 OUT interrupt of FIFO 1 */\n+ USB_SUB_GRP1_INT_F1_SPK = 8, /*!< group1 short packet interrupt of FIFO 1 */\n+ USB_SUB_GRP1_INT_F2_OUT = 9, /*!< group1 OUT interrupt of FIFO 2 */\n+ USB_SUB_GRP1_INT_F2_SPK = 10, /*!< group1 short packet interrupt of FIFO 2 */\n+ USB_SUB_GRP1_INT_F3_OUT = 11, /*!< group1 OUT interrupt of FIFO 3 */\n+ USB_SUB_GRP1_INT_F3_SPK = 12, /*!< group1 short packet interrupt of FIFO 3 */\n+ USB_SUB_GRP1_INT_F0_IN = 13, /*!< group1 IN interrupt of FIFO 0 */\n+ USB_SUB_GRP1_INT_F1_IN = 14, /*!< group1 IN interrupt of FIFO 1 */\n+ USB_SUB_GRP1_INT_F2_IN = 15, /*!< group1 IN interrupt of FIFO 2 */\n+ USB_SUB_GRP1_INT_F3_IN = 16, /*!< group1 IN interrupt of FIFO 3 */\n+ USB_SUB_GRP2_INT_RESET = 17, /*!< group2 USB reset interrupt */\n+ USB_SUB_GRP2_INT_SUSPEND = 18, /*!< group2 suspend interrupt */\n+ USB_SUB_GRP2_INT_RESUME = 19, /*!< group2 resume interrupt */\n+ USB_SUB_GRP2_INT_TX0BYTE = 20, /*!< group2 transferred zero-length data packet interrupt */\n+ USB_SUB_GRP2_INT_RX0BYTE = 21, /*!< group2 received zero-length data packet interrupt */\n+ USB_SUB_GRP2_INT_DMA_CMPLT = 22, /*!< group2 DMA completion interrupt */\n+ USB_SUB_GRP2_INT_DMA_ERROR = 23, /*!< group2 DMA error interrupt */\n+ USB_SUB_GRP2_INT_IDLE = 24, /*!< group2 dev_idle interrupt */\n+ USB_SUB_GRP2_INT_WAKEUP_BY_VBUS = 25, /*!< group2 dev_wakeup_byVBUS interrupt */\n+ USB_SUB_GRP3_INT_VDMA_CMPLT_CXF = 26, /*!< group3 Virtual DMA completion interrupt for FIFO CXF */\n+ USB_SUB_GRP3_INT_VDMA_CMPLT_F0 = 27, /*!< group3 Virtual DMA completion interrupt for FIFO 0 */\n+ USB_SUB_GRP3_INT_VDMA_CMPLT_F1 = 28, /*!< group3 Virtual DMA completion interrupt for FIFO 1 */\n+ USB_SUB_GRP3_INT_VDMA_CMPLT_F2 = 29, /*!< group3 Virtual DMA completion interrupt for FIFO 2 */\n+ USB_SUB_GRP3_INT_VDMA_CMPLT_F3 = 30, /*!< group3 Virtual DMA completion interrupt for FIFO 3 */\n+ USB_SUB_GRP3_INT_VDMA_ERROR_CXF = 31, /*!< group3 Virtual DMA error interrupt for FIFO CXF */\n+ USB_SUB_GRP3_INT_VDMA_ERROR_F0 = 32, /*!< group3 Virtual DMA error interrupt for FIFO 0 */\n+ USB_SUB_GRP3_INT_VDMA_ERROR_F1 = 33, /*!< group3 Virtual DMA error interrupt for FIFO 1 */\n+ USB_SUB_GRP3_INT_VDMA_ERROR_F2 = 34, /*!< group3 Virtual DMA error interrupt for FIFO 2 */\n+ USB_SUB_GRP3_INT_VDMA_ERROR_F3 = 35, /*!< group3 Virtual DMA error interrupt for FIFO 3 */\n+ USB_SUB_GRP4_INT_L1 = 36, /*!< group4 L1-state-change interrupt */\n+} USB_SUB_GRP_INT_Type;\n+\n+/*@} end of group USB_Public_Types */\n+\n+/** @defgroup USB_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup USB_LPM_RESP_TYPE\n+ * @{\n+ */\n+#define IS_USB_LPM_RESP_TYPE(type) (((type) == USB_LPM_RESP_NYET) || \\\n+ ((type) == USB_LPM_RESP_ACK))\n+\n+/** @defgroup USB_GLOBAL_INT_TYPE\n+ * @{\n+ */\n+#define IS_USB_GLOBAL_INT_TYPE(type) (((type) == USB_GLOBAL_INT_DEV) || \\\n+ ((type) == USB_GLOBAL_INT_OTG) || \\\n+ ((type) == USB_GLOBAL_INT_HC))\n+\n+/** @defgroup USB_DEVICE_SPEED_TYPE\n+ * @{\n+ */\n+#define IS_USB_DEVICE_SPEED_TYPE(type) (((type) == USB_DEVICE_SPEED_FULL_SPEED) || \\\n+ ((type) == USB_DEVICE_SPEED_HIGH_SPEED))\n+\n+/** @defgroup USB_FIFO_EMPTY_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_EMPTY_TYPE(type) (((type) == USB_FIFO_EMPTY_FIFO_0) || \\\n+ ((type) == USB_FIFO_EMPTY_FIFO_1) || \\\n+ ((type) == USB_FIFO_EMPTY_FIFO_2) || \\\n+ ((type) == USB_FIFO_EMPTY_FIFO_3))\n+\n+/** @defgroup USB_ENDPOINT_TYPE\n+ * @{\n+ */\n+#define IS_USB_ENDPOINT_TYPE(type) (((type) == USB_Endpoint_1) || \\\n+ ((type) == USB_Endpoint_2) || \\\n+ ((type) == USB_Endpoint_3) || \\\n+ ((type) == USB_Endpoint_4) || \\\n+ ((type) == USB_Endpoint_5) || \\\n+ ((type) == USB_Endpoint_6) || \\\n+ ((type) == USB_Endpoint_7) || \\\n+ ((type) == USB_Endpoint_8))\n+\n+/** @defgroup USB_FIFO_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_TYPE(type) (((type) == USB_FIFO_0) || \\\n+ ((type) == USB_FIFO_1) || \\\n+ ((type) == USB_FIFO_2) || \\\n+ ((type) == USB_FIFO_3))\n+\n+/** @defgroup USB_FIFO_DIR_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_DIR_TYPE(type) (((type) == USB_FIFO_DIR_OUT) || \\\n+ ((type) == USB_FIFO_DIR_IN) || \\\n+ ((type) == USB_FIFO_DIR_BID))\n+\n+/** @defgroup USB_FIFO_BLOCK_MAX_SIZE_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(type) (((type) == USB_FIFO_BLOCK_MAX_SIZE_512) || \\\n+ ((type) == USB_FIFO_BLOCK_MAX_SIZE_1024))\n+\n+/** @defgroup USB_FIFO_BLOCK_CNT_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_BLOCK_CNT_TYPE(type) (((type) == USB_FIFO_BLOCK_CNT_SINGLE_BLOCK) || \\\n+ ((type) == USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS) || \\\n+ ((type) == USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS))\n+\n+/** @defgroup USB_FIFO_TRANSFER_TYPE\n+ * @{\n+ */\n+#define IS_USB_FIFO_TRANSFER_TYPE(type) (((type) == USB_FIFO_TRANSFER_RSV) || \\\n+ ((type) == USB_FIFO_TRANSFER_ISO) || \\\n+ ((type) == USB_FIFO_TRANSFER_BULK) || \\\n+ ((type) == USB_FIFO_TRANSFER_INT))\n+\n+/** @defgroup USB_DMA_TARGET_FIFO_TYPE\n+ * @{\n+ */\n+#define IS_USB_DMA_TARGET_FIFO_TYPE(type) (((type) == USB_DMA_TARGET_FIFO_0) || \\\n+ ((type) == USB_DMA_TARGET_FIFO_1) || \\\n+ ((type) == USB_DMA_TARGET_FIFO_2) || \\\n+ ((type) == USB_DMA_TARGET_FIFO_3) || \\\n+ ((type) == USB_DMA_TARGET_FIFO_CTRL))\n+\n+/** @defgroup USB_DMA_TRANS_DIR_TYPE\n+ * @{\n+ */\n+#define IS_USB_DMA_TRANS_DIR_TYPE(type) (((type) == USB_DMA_TRANS_DIR_FIFO_2_MEM) || \\\n+ ((type) == USB_DMA_TRANS_DIR_MEM_2_FIFO) || \\\n+ ((type) == USB_DMA_TRANS_DIR_FIFO_2_FIFO))\n+\n+/** @defgroup USB_VDMA_TARGET_FIFO_TYPE\n+ * @{\n+ */\n+#define IS_USB_VDMA_TARGET_FIFO_TYPE(type) (((type) == USB_VDMA_TARGET_FIFO_0) || \\\n+ ((type) == USB_VDMA_TARGET_FIFO_1) || \\\n+ ((type) == USB_VDMA_TARGET_FIFO_2) || \\\n+ ((type) == USB_VDMA_TARGET_FIFO_3) || \\\n+ ((type) == USB_VDMA_TARGET_FIFO_CTRL))\n+\n+/** @defgroup USB_VDMA_TRANS_DIR_TYPE\n+ * @{\n+ */\n+#define IS_USB_VDMA_TRANS_DIR_TYPE(type) (((type) == USB_VDMA_TRANS_DIR_FIFO_2_MEM) || \\\n+ ((type) == USB_VDMA_TRANS_DIR_MEM_2_FIFO) || \\\n+ ((type) == USB_VDMA_TRANS_DIR_FIFO_2_FIFO))\n+\n+/** @defgroup USB_GRP_INT_TYPE\n+ * @{\n+ */\n+#define IS_USB_GRP_INT_TYPE(type) (((type) == USB_GRP_INT_G0) || \\\n+ ((type) == USB_GRP_INT_G1) || \\\n+ ((type) == USB_GRP_INT_G2) || \\\n+ ((type) == USB_GRP_INT_G3) || \\\n+ ((type) == USB_GRP_INT_G4))\n+\n+/** @defgroup USB_SUB_GRP_INT_TYPE\n+ * @{\n+ */\n+#define IS_USB_SUB_GRP_INT_TYPE(type) (((type) == USB_SUB_GRP0_INT_CX_SETUP) || \\\n+ ((type) == USB_SUB_GRP0_INT_CX_IN) || \\\n+ ((type) == USB_SUB_GRP0_INT_CX_OUT) || \\\n+ ((type) == USB_SUB_GRP0_INT_CX_COMFAIL) || \\\n+ ((type) == USB_SUB_GRP0_INT_CX_COMABORT) || \\\n+ ((type) == USB_SUB_GRP1_INT_F0_OUT) || \\\n+ ((type) == USB_SUB_GRP1_INT_F0_SPK) || \\\n+ ((type) == USB_SUB_GRP1_INT_F1_OUT) || \\\n+ ((type) == USB_SUB_GRP1_INT_F1_SPK) || \\\n+ ((type) == USB_SUB_GRP1_INT_F2_OUT) || \\\n+ ((type) == USB_SUB_GRP1_INT_F2_SPK) || \\\n+ ((type) == USB_SUB_GRP1_INT_F3_OUT) || \\\n+ ((type) == USB_SUB_GRP1_INT_F3_SPK) || \\\n+ ((type) == USB_SUB_GRP1_INT_F0_IN) || \\\n+ ((type) == USB_SUB_GRP1_INT_F1_IN) || \\\n+ ((type) == USB_SUB_GRP1_INT_F2_IN) || \\\n+ ((type) == USB_SUB_GRP1_INT_F3_IN) || \\\n+ ((type) == USB_SUB_GRP2_INT_RESET) || \\\n+ ((type) == USB_SUB_GRP2_INT_SUSPEND) || \\\n+ ((type) == USB_SUB_GRP2_INT_RESUME) || \\\n+ ((type) == USB_SUB_GRP2_INT_TX0BYTE) || \\\n+ ((type) == USB_SUB_GRP2_INT_RX0BYTE) || \\\n+ ((type) == USB_SUB_GRP2_INT_DMA_CMPLT) || \\\n+ ((type) == USB_SUB_GRP2_INT_DMA_ERROR) || \\\n+ ((type) == USB_SUB_GRP2_INT_IDLE) || \\\n+ ((type) == USB_SUB_GRP2_INT_WAKEUP_BY_VBUS) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_CXF) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F0) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F1) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F2) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F3) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_CXF) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F0) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F1) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F2) || \\\n+ ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F3) || \\\n+ ((type) == USB_SUB_GRP4_INT_L1))\n+\n+/*@} end of group USB_Public_Constants */\n+\n+/** @defgroup USB_Public_Macros\n+ * @{\n+ */\n+#define USB_SUB_GRP0_INT_OFS (0)\n+#define USB_SUB_GRP1_INT_OFS (32)\n+#define USB_SUB_GRP2_INT_OFS (64)\n+#define USB_SUB_GRP3_INT_OFS (96)\n+#define USB_SUB_GRP4_INT_OFS (128)\n+#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)\n+#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)\n+\n+#define USB_INT_CX_SETUP (1ULL << USB_SUB_GRP0_INT_CX_SETUP)\n+#define USB_INT_CX_IN (1ULL << USB_SUB_GRP0_INT_CX_IN)\n+#define USB_INT_CX_OUT (1ULL << USB_SUB_GRP0_INT_CX_OUT)\n+#define USB_INT_CX_COMFAIL (1ULL << USB_SUB_GRP0_INT_CX_COMFAIL)\n+#define USB_INT_CX_COMABORT (1ULL << USB_SUB_GRP0_INT_CX_COMABORT)\n+#define USB_INT_F0_OUT (1ULL << USB_SUB_GRP1_INT_F0_OUT)\n+#define USB_INT_F0_SPK (1ULL << USB_SUB_GRP1_INT_F0_SPK)\n+#define USB_INT_F1_OUT (1ULL << USB_SUB_GRP1_INT_F1_OUT)\n+#define USB_INT_F1_SPK (1ULL << USB_SUB_GRP1_INT_F1_SPK)\n+#define USB_INT_F2_OUT (1ULL << USB_SUB_GRP1_INT_F2_OUT)\n+#define USB_INT_F2_SPK (1ULL << USB_SUB_GRP1_INT_F2_SPK)\n+#define USB_INT_F3_OUT (1ULL << USB_SUB_GRP1_INT_F3_OUT)\n+#define USB_INT_F3_SPK (1ULL << USB_SUB_GRP1_INT_F3_SPK)\n+#define USB_INT_F0_IN (1ULL << USB_SUB_GRP1_INT_F0_IN)\n+#define USB_INT_F1_IN (1ULL << USB_SUB_GRP1_INT_F1_IN)\n+#define USB_INT_F2_IN (1ULL << USB_SUB_GRP1_INT_F2_IN)\n+#define USB_INT_F3_IN (1ULL << USB_SUB_GRP1_INT_F3_IN)\n+#define USB_INT_RESET (1ULL << USB_SUB_GRP2_INT_RESET)\n+#define USB_INT_SUSPEND (1ULL << USB_SUB_GRP2_INT_SUSPEND)\n+#define USB_INT_RESUME (1ULL << USB_SUB_GRP2_INT_RESUME)\n+#define USB_INT_TX0BYTE (1ULL << USB_SUB_GRP2_INT_TX0BYTE)\n+#define USB_INT_RX0BYTE (1ULL << USB_SUB_GRP2_INT_RX0BYTE)\n+#define USB_INT_DMA_CMPLT (1ULL << USB_SUB_GRP2_INT_DMA_CMPLT)\n+#define USB_INT_DMA_ERROR (1ULL << USB_SUB_GRP2_INT_DMA_ERROR)\n+#define USB_INT_IDLE (1ULL << USB_SUB_GRP2_INT_IDLE)\n+#define USB_INT_WAKEUP_BY_VBUS (1ULL << USB_SUB_GRP2_INT_WAKEUP_BY_VBUS)\n+#define USB_INT_VDMA_CMPLT_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_CXF)\n+#define USB_INT_VDMA_CMPLT_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F0)\n+#define USB_INT_VDMA_CMPLT_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F1)\n+#define USB_INT_VDMA_CMPLT_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F2)\n+#define USB_INT_VDMA_CMPLT_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F3)\n+#define USB_INT_VDMA_ERROR_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_CXF)\n+#define USB_INT_VDMA_ERROR_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F0)\n+#define USB_INT_VDMA_ERROR_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F1)\n+#define USB_INT_VDMA_ERROR_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F2)\n+#define USB_INT_VDMA_ERROR_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F3)\n+#define USB_INT_L1 (1ULL << USB_SUB_GRP4_INT_L1)\n+\n+#define USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK (0x00000001)\n+#define USB_SUB_GROUP_0_CX_IN_BIT_MUSK (0x00000002)\n+#define USB_SUB_GROUP_0_CX_OUT_BIT_MUSK (0x00000004)\n+#define USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK (0x00000010)\n+#define USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK (0x00000020)\n+#define USB_SUB_GROUP_1_F0_OUT_BIT_MUSK (0x00000001)\n+#define USB_SUB_GROUP_1_F0_SPK_BIT_MUSK (0x00000002)\n+#define USB_SUB_GROUP_1_F1_OUT_BIT_MUSK (0x00000004)\n+#define USB_SUB_GROUP_1_F1_SPK_BIT_MUSK (0x00000008)\n+#define USB_SUB_GROUP_1_F2_OUT_BIT_MUSK (0x00000010)\n+#define USB_SUB_GROUP_1_F2_SPK_BIT_MUSK (0x00000020)\n+#define USB_SUB_GROUP_1_F3_OUT_BIT_MUSK (0x00000040)\n+#define USB_SUB_GROUP_1_F3_SPK_BIT_MUSK (0x00000080)\n+#define USB_SUB_GROUP_1_F0_IN_BIT_MUSK (0x00010000)\n+#define USB_SUB_GROUP_1_F1_IN_BIT_MUSK (0x00020000)\n+#define USB_SUB_GROUP_1_F2_IN_BIT_MUSK (0x00040000)\n+#define USB_SUB_GROUP_1_F3_IN_BIT_MUSK (0x00080000)\n+#define USB_SUB_GROUP_2_RESET_BIT_MUSK (0x00000001)\n+#define USB_SUB_GROUP_2_SUSPEND_BIT_MUSK (0x00000002)\n+#define USB_SUB_GROUP_2_RESUME_BIT_MUSK (0x00000004)\n+#define USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK (0x00000020)\n+#define USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK (0x00000040)\n+#define USB_SUB_GROUP_2_CMPLT_BIT_MUSK (0x00000080)\n+#define USB_SUB_GROUP_2_ERROR_BIT_MUSK (0x00000100)\n+#define USB_SUB_GROUP_2_IDLE_BIT_MUSK (0x00000200)\n+#define USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK (0x00000400)\n+#define USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK (0x00000001)\n+#define USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK (0x00000002)\n+#define USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK (0x00000004)\n+#define USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK (0x00000008)\n+#define USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK (0x00000010)\n+#define USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK (0x00010000)\n+#define USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK (0x00020000)\n+#define USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK (0x00040000)\n+#define USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK (0x00080000)\n+#define USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK (0x00100000)\n+#define USB_SUB_GROUP_4_L1_BIT_MUSK (0x00000001)\n+\n+/*@} end of group USB_Public_Macros */\n+\n+/** @defgroup USB_Public_Functions\n+ * @{\n+ */\n+\n+/**\n+ * @brief USB Functions\n+ */\n+BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg);\n+BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void);\n+BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void);\n+BL_Err_Type USB_SoftDetach_Enable(void);\n+BL_Err_Type USB_SoftDetach_Disable(void);\n+USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void);\n+BL_Err_Type USB_Go_Suspend(uint8_t enable);\n+BL_Err_Type USB_Set_Device_Address(uint8_t addr);\n+uint8_t USB_Get_Device_Address(void);\n+BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void);\n+BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void);\n+BL_Err_Type USB_Clear_CTRL_FIFO(void);\n+BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void);\n+BL_Sts_Type USB_Is_CTRL_FIFO_Full(void);\n+BL_Err_Type USB_Clear_FIFO(void);\n+BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID);\n+BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum);\n+BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID);\n+BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID);\n+BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg);\n+uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID);\n+BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max);\n+BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max);\n+BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void);\n+BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable);\n+BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable);\n+BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void);\n+BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID);\n+BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID);\n+BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2]);\n+void USB_Reset_DMA_Accessing_Fifo(void);\n+BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length);\n+BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg);\n+BL_Err_Type USB_Set_DMA_Start(void);\n+BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg);\n+BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN);\n+BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN);\n+BL_Err_Type USB_Set_VDMA_Enable(void);\n+BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg);\n+uint8_t USB_Get_LPM_BESL(void);\n+/*----------*/\n+BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms);\n+/*----------*/\n+BL_Err_Type USB_Global_IntEnable(uint8_t enable);\n+BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask);\n+BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType);\n+/*----------*/\n+BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask);\n+BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType);\n+/*----------*/\n+BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType);\n+BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType);\n+/*----------*/\n+uint32_t USB_Get_Sub_Group_0_IntStatus(void);\n+uint32_t USB_Get_Sub_Group_1_IntStatus(void);\n+uint32_t USB_Get_Sub_Group_2_IntStatus(void);\n+uint32_t USB_Get_Sub_Group_3_IntStatus(void);\n+uint32_t USB_Get_Sub_Group_4_IntStatus(void);\n+uint32_t USB_Get_Sub_Group_0_IntMask(void);\n+uint32_t USB_Get_Sub_Group_1_IntMask(void);\n+uint32_t USB_Get_Sub_Group_2_IntMask(void);\n+uint32_t USB_Get_Sub_Group_3_IntMask(void);\n+uint32_t USB_Get_Sub_Group_4_IntMask(void);\n+BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal);\n+BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal);\n+BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal);\n+BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal);\n+BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal);\n+/*----------*/;\n+\n+/*@} end of group USB_Public_Functions */\n+\n+/*@} end of group USB */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_USB_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fe9918e4cf7301337506bf0f4d4da1a674c6bae2\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h\n@@ -0,0 +1,98 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_xip_sflash.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __BL808_XIP_SFLASH_H__\n+#define __BL808_XIP_SFLASH_H__\n+\n+#include \"bl808_common.h\"\n+#include \"bl808_sflash.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup XIP_SFLASH\n+ * @{\n+ */\n+\n+/** @defgroup XIP_SFLASH_Public_Types\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Public_Types */\n+\n+/** @defgroup XIP_SFLASH_Public_Constants\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Public_Constants */\n+\n+/** @defgroup XIP_SFLASH_Public_Macros\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Public_Macros */\n+\n+/** @defgroup XIP_SFLASH_Public_Functions\n+ * @{\n+ */\n+BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr,\n+ int len, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,\n+ uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,\n+ uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,\n+ BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,\n+ uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank);\n+BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank);\n+void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);\n+void XIP_SFlash_Opt_Exit(uint8_t aesEnable);\n+\n+/*@} end of group XIP_SFLASH_Public_Functions */\n+\n+/*@} end of group XIP_SFLASH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n+\n+#endif /* __BL808_XIP_SFLASH_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bb4dfe39eb5277ccfe1d8c1b2b5995d42b20e736\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c\n@@ -0,0 +1,209 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_acomp.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_acomp.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup ACOMP\n+ * @{\n+ */\n+\n+/** @defgroup ACOMP_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Private_Macros */\n+\n+/** @defgroup ACOMP_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Private_Types */\n+\n+/** @defgroup ACOMP_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Private_Variables */\n+\n+/** @defgroup ACOMP_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Global_Variables */\n+\n+/** @defgroup ACOMP_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Private_Fun_Declaration */\n+\n+/** @defgroup ACOMP_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group ACOMP_Private_Functions */\n+\n+/** @defgroup ACOMP_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Analog compare init\n+ *\n+ * @param acompNo: Compare ID\n+ * @param cfg: Compare consideration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));\n+\n+ if (acompNo == AON_ACOMP0_ID) {\n+ /* Disable ACOMP first */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);\n+\n+ /* Set ACOMP config */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->scalingFactor);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt);\n+\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);\n+ } else {\n+ /* Disable ACOMP first */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);\n+\n+ /* Set ACOMP config */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->scalingFactor);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt);\n+\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);\n+ }\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP_VREF_SEL, cfg->vioSel);\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Analog compare enable\n+ *\n+ * @param acompNo: Compare ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));\n+\n+ if (acompNo == AON_ACOMP0_ID) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);\n+ tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Analog compare enable\n+ *\n+ * @param acompNo: Compare ID\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);\n+\n+ /* Disable ACOMP first */\n+ if (acompNo == AON_ACOMP0_ID) {\n+ if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+}\n+\n+/*@} end of group ACOMP_Public_Functions */\n+\n+/*@} end of group ACOMP */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0226b9d70574ab6a72db08890e5894aa51961af3\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c\n@@ -0,0 +1,1487 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_adc.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_adc.h\"\n+#include \"bl808_ef_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup ADC\n+ * @{\n+ */\n+\n+/** @defgroup ADC_Private_Macros\n+ * @{\n+ */\n+#undef MSG\n+#define MSG(...)\n+#define AON_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+#define ADC_RESTART_DUMMY_WAIT arch_delay_us(100)\n+\n+/*@} end of group ADC_Private_Macros */\n+\n+/** @defgroup ADC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group ADC_Private_Types */\n+\n+/** @defgroup ADC_Private_Variables\n+ * @{\n+ */\n+static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL };\n+static ADC_Gain_Coeff_Type adcGainCoeffCal = {\n+ .adcGainCoeffEnable = DISABLE,\n+ .adcgainCoeffVal = 0,\n+ .coe = 1,\n+};\n+\n+/*@} end of group ADC_Private_Variables */\n+\n+/** @defgroup ADC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group ADC_Global_Variables */\n+\n+/** @defgroup ADC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group ADC_Private_Fun_Declaration */\n+\n+/** @defgroup ADC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group ADC_Private_Functions */\n+\n+/** @defgroup ADC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Software reset the whole ADC\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Reset(void)\n+{\n+ uint32_t regCmd;\n+\n+ /* reset ADC */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST));\n+ AON_CLK_SET_DUMMY_WAIT;\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC glable enable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC glable disable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC normal mode init\n+ *\n+ * @param cfg: ADC normal mode configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Init(ADC_CFG_Type *cfg)\n+{\n+ uint32_t regCfg1;\n+ uint32_t regCfg2;\n+ uint32_t regCalib;\n+ uint32_t regCmd;\n+\n+ CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel));\n+ CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel));\n+ CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv));\n+ CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1));\n+ CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2));\n+ CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode));\n+ CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel));\n+ CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm));\n+ CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref));\n+ CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode));\n+ CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth));\n+\n+ /* config 1 */\n+ regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel);\n+ regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN);\n+ regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv);\n+ regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);\n+ AON_CLK_SET_DUMMY_WAIT;\n+\n+ /* config 2 */\n+ regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode);\n+ /* pga_vcmi_en is for mic */\n+ regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN);\n+\n+ if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) {\n+ regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN);\n+ } else {\n+ regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN);\n+ }\n+\n+ /* pga_os_cal is for mic */\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref);\n+ regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode);\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2);\n+\n+ /* mic2 diff enable */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_MIC2_DIFF);\n+ if (cfg->inputMode == ADC_INPUT_SINGLE_END) {\n+ regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_NEG_GND);\n+ } else {\n+ regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_NEG_GND);\n+ }\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);\n+\n+ /* calibration offset */\n+ regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE);\n+ regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler);\n+#endif\n+\n+ ADC_Gain_Trim();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC normal mode channel config\n+ *\n+ * @param posCh: ADC pos channel type\n+ * @param negCh: ADC neg channel type\n+ * @param contEn: ENABLE or DISABLE continuous mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn)\n+{\n+ uint32_t regCmd;\n+ uint32_t regCfg1;\n+\n+ CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh));\n+ CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh));\n+\n+ /* set channel */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh);\n+ regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);\n+\n+ /* set continuous mode */\n+ regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);\n+ regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn);\n+ regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC scan mode channel config\n+ *\n+ * @param posChList[]: ADC pos channel list type\n+ * @param negChList[]: ADC neg channel list type\n+ * @param scanLength: ADC scan length\n+ * @param contEn: ENABLE or DISABLE continuous mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn)\n+{\n+ uint32_t tmpVal, i;\n+ uint32_t dealLen;\n+\n+ CHECK_PARAM((scanLength < 13));\n+\n+ /* Deal with the first 6 */\n+ dealLen = 6;\n+\n+ if (scanLength < dealLen) {\n+ dealLen = scanLength;\n+ }\n+\n+ /* Set first 6 scan channels */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1);\n+\n+ for (i = 0; i < dealLen; i++) {\n+ tmpVal = tmpVal & (~(0x1F << (i * 5)));\n+ tmpVal |= (posChList[i] << (i * 5));\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1);\n+\n+ for (i = 0; i < dealLen; i++) {\n+ tmpVal = tmpVal & (~(0x1F << (i * 5)));\n+ tmpVal |= (negChList[i] << (i * 5));\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal);\n+\n+ /* Set the left channels */\n+ if (scanLength > dealLen) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2);\n+\n+ for (i = 0; i < scanLength - dealLen; i++) {\n+ tmpVal = tmpVal & (~(0x1F << (i * 5)));\n+ tmpVal |= (posChList[i + dealLen] << (i * 5));\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2);\n+\n+ for (i = 0; i < scanLength - dealLen; i++) {\n+ tmpVal = tmpVal & (~(0x1F << (i * 5)));\n+ tmpVal |= (negChList[i + dealLen] << (i * 5));\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal);\n+ }\n+\n+ /* Scan mode */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC normal mode convert start\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Start(void)\n+{\n+ uint32_t regCmd;\n+\n+ /* disable convert start */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);\n+\n+ ADC_RESTART_DUMMY_WAIT;\n+\n+ /* enable convert start */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC normal mode convert stop\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Stop(void)\n+{\n+ uint32_t regCmd;\n+\n+ /* disable convert start */\n+ regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC FIFO configuration\n+ *\n+ * @param fifoCfg: ADC FIFO confifuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold));\n+\n+ /*\n+ * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur\n+ * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt\n+ */\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold);\n+\n+ /* Enable DMA */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn);\n+\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC get DMA FIFO data count\n+ *\n+ * @param None\n+ *\n+ * @return data count in FIFO\n+ *\n+*******************************************************************************/\n+uint8_t ADC_Get_FIFO_Count(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC get DMA FIFO full status\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ADC_FIFO_Is_Full(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC get DMA FIFO empty status\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ADC_FIFO_Is_Empty(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) {\n+ return RESET;\n+ } else {\n+ return SET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC read DMA FIFO data\n+ *\n+ * @param None\n+ *\n+ * @return ADC result if return 0 that means this is error data,user should ignore this data.\n+ *\n+*******************************************************************************/\n+uint32_t ADC_Read_FIFO(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA);\n+\n+ return (tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC parse result\n+ *\n+ * @param orgVal: Original A to D value\n+ * @param len: Original AD vaule count\n+ * @param result: Final Result array pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result)\n+{\n+ uint8_t neg = 0;\n+ uint32_t tmpVal1 = 0, tmpVal2 = 0;\n+ ADC_Data_Width_Type dataType;\n+ ADC_SIG_INPUT_Type sigType;\n+ float ref = 2.0;\n+ uint32_t i = 0;\n+\n+ float coe = 1.0;\n+\n+ if (adcGainCoeffCal.adcGainCoeffEnable) {\n+ coe = adcGainCoeffCal.coe;\n+ }\n+\n+ tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);\n+ tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL);\n+ sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE);\n+\n+ if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) {\n+ ref = 3.2;\n+ }\n+\n+ if (sigType == ADC_INPUT_SINGLE_END) {\n+ for (i = 0; i < len; i++) {\n+ result[i].posChan = orgVal[i] >> 21;\n+ result[i].negChan = -1;\n+\n+ if (dataType == ADC_DATA_WIDTH_12) {\n+ result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);\n+ result[i].volt = result[i].value / 4096.0 * ref;\n+ } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) ||\n+ (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {\n+ result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);\n+ result[i].volt = result[i].value / 16384.0 * ref;\n+ } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) ||\n+ (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {\n+ result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);\n+ result[i].volt = result[i].value / 65536.0 * ref;\n+ }\n+ }\n+ } else {\n+ for (i = 0; i < len; i++) {\n+ neg = 0;\n+ result[i].posChan = orgVal[i] >> 21;\n+ result[i].negChan = (orgVal[i] >> 16) & 0x1F;\n+\n+ if (orgVal[i] & 0x8000) {\n+ orgVal[i] = ~orgVal[i];\n+ orgVal[i] += 1;\n+ neg = 1;\n+ }\n+\n+ if (dataType == ADC_DATA_WIDTH_12) {\n+ result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);\n+ result[i].volt = result[i].value / 2048.0 * ref;\n+ } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) ||\n+ (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {\n+ result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);\n+ result[i].volt = result[i].value / 8192.0 * ref;\n+ } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) ||\n+ (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {\n+ result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);\n+ result[i].volt = result[i].value / 32768.0 * ref;\n+ }\n+\n+ if (neg) {\n+ result[i].volt = -result[i].volt;\n+ }\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC mask or unmask certain or all interrupt\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: mask or unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ switch (intType) {\n+ case ADC_INT_POS_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK);\n+ break;\n+\n+ case ADC_INT_NEG_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK);\n+ break;\n+\n+ case ADC_INT_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);\n+ break;\n+\n+ case ADC_INT_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);\n+ break;\n+\n+ case ADC_INT_ADC_READY:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ return 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC mask or unmask certain or all interrupt\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: mask or unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ switch (intType) {\n+ case ADC_INT_POS_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+ break;\n+\n+ case ADC_INT_NEG_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);\n+ }\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+ break;\n+\n+ case ADC_INT_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);\n+ }\n+\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+ break;\n+\n+ case ADC_INT_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);\n+ }\n+\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+ break;\n+\n+ case ADC_INT_ADC_READY:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);\n+ }\n+\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+ break;\n+\n+ case ADC_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC clear certain or all interrupt\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_IntClr(ADC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case ADC_INT_POS_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ break;\n+\n+ case ADC_INT_NEG_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ break;\n+\n+ case ADC_INT_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ break;\n+\n+ case ADC_INT_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ break;\n+\n+ case ADC_INT_ADC_READY:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ break;\n+\n+ case ADC_INT_ALL:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ /*Manual reset*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC get interrupt status\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ BL_Sts_Type bitStatus = RESET;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case ADC_INT_POS_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET;\n+ break;\n+\n+ case ADC_INT_NEG_SATURATION:\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);\n+ bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET;\n+ break;\n+\n+ case ADC_INT_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET;\n+ break;\n+\n+ case ADC_INT_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET;\n+ break;\n+\n+ case ADC_INT_ADC_READY:\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET;\n+ break;\n+\n+ case ADC_INT_ALL:\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return bitStatus;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC install interrupt callback\n+ *\n+ * @param intType: ADC interrupt type\n+ * @param cbFun: ADC interrupt callback\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));\n+\n+ adcIntCbfArra[intType] = cbFun;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC DMA interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void GPADC_DMA_IRQHandler(void)\n+{\n+ if (ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) {\n+ ADC_IntClr(ADC_INT_POS_SATURATION);\n+\n+ if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) {\n+ adcIntCbfArra[ADC_INT_POS_SATURATION]();\n+ }\n+ }\n+\n+ if (ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) {\n+ ADC_IntClr(ADC_INT_NEG_SATURATION);\n+\n+ if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) {\n+ adcIntCbfArra[ADC_INT_NEG_SATURATION]();\n+ }\n+ }\n+\n+ if (ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) {\n+ ADC_IntClr(ADC_INT_FIFO_UNDERRUN);\n+\n+ if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) {\n+ adcIntCbfArra[ADC_INT_FIFO_UNDERRUN]();\n+ }\n+ }\n+\n+ if (ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) {\n+ ADC_IntClr(ADC_INT_FIFO_OVERRUN);\n+\n+ if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) {\n+ adcIntCbfArra[ADC_INT_FIFO_OVERRUN]();\n+ }\n+ }\n+\n+ if (ADC_IntGetMask(ADC_INT_ADC_READY) == UNMASK && ADC_GetIntStatus(ADC_INT_ADC_READY) == SET) {\n+ ADC_IntClr(ADC_INT_ADC_READY);\n+\n+ if (adcIntCbfArra[ADC_INT_ADC_READY] != NULL) {\n+ adcIntCbfArra[ADC_INT_ADC_READY]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief ADC VBAT enable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Vbat_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC VBAT disable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Vbat_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC TSEN Config\n+ *\n+ * @param tsenMod: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type));\n+\n+ /* config gpadc_reg_cmd */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ /* enable sensor dc test mux*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN);\n+ /*selected sen output current channel*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0);\n+ /* enable chip sensor*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU);\n+ /*dwa_en */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+\n+ /* config 2 */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ /*tsvbe low=0*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);\n+ /*dly_sel=2*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2);\n+ /*test_sel=0*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0);\n+ /*test_en=0*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN);\n+ /*ts_en*/\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);\n+ /*select tsen ext or inner*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2);\n+ /*pga vcmi enable*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);\n+ /*0:512uS;1:16mS;2:32mS;3:64mS*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0);\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+\n+ /* config 3 */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);\n+ /* set gpadc_dither_en */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);\n+\n+ /* set 4000F90C[19](gpadc_mic2_diff) = 1\n+ * debug advise form Ran\n+ * 2020.08.26\n+ */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC TSEN Enable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Tsen_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC TSEN Disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_Tsen_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC Clear fifo\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_FIFO_Clear(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief config pga\n+ *\n+ * @param pga_vcmi_enable: enable or not vcmi\n+ * @param pga_os_cal: pga os cal value\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+\n+ if (pga_vcmi_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal);\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+/****************************************************************************/ /**\n+ * @brief TSEN_Get_V_Error\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+uint32_t TSEN_Get_V_Error(void)\n+{\n+ uint32_t v0 = 0, v1 = 0;\n+ uint32_t v_error = 0;\n+ uint32_t regVal = 0;\n+ ADC_Result_Type result;\n+ uint32_t tmpVal;\n+ uint8_t gainCalEnabled = 0;\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ ADC_SET_TSVBE_LOW();\n+\n+ ADC_Start();\n+\n+ while (ADC_Get_FIFO_Count() == 0)\n+ ;\n+\n+ regVal = ADC_Read_FIFO();\n+ gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable;\n+ adcGainCoeffCal.adcGainCoeffEnable = 0;\n+ ADC_Parse_Result(®Val, 1, &result);\n+ adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;\n+ v0 = result.value;\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ ADC_SET_TSVBE_HIGH();\n+\n+ ADC_Start();\n+\n+ while (ADC_Get_FIFO_Count() == 0)\n+ ;\n+\n+ regVal = ADC_Read_FIFO();\n+ gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable;\n+ adcGainCoeffCal.adcGainCoeffEnable = 0;\n+ ADC_Parse_Result(®Val, 1, &result);\n+ adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;\n+ v1 = result.value;\n+\n+ v_error = v0 - v1;\n+\n+ return v_error;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Trim TSEN\n+ *\n+ * @param tsen_offset: None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset)\n+{\n+ Efuse_TSEN_Refcode_Corner_Type trim;\n+\n+ EF_Ctrl_Read_TSEN_Trim(&trim);\n+ if (trim.tsenRefcodeCornerEn) {\n+ if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {\n+ *tsen_offset = trim.tsenRefcodeCorner;\n+\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SET ADC TSEN TSVBE LOW/HIGH\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_SET_TSVBE_LOW(void)\n+{\n+ uint32_t tmpVal;\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SET ADC TSEN TSVBE LOW/HIGH\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_SET_TSVBE_HIGH(void)\n+{\n+ uint32_t tmpVal;\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SET ADC TSEN TSVBE LOW/HIGH\n+ *\n+ * @param tsen_offset: tsen_offset form efuse trim data\n+ *\n+ * @return tempture\n+ *\n+*******************************************************************************/\n+float TSEN_Get_Temp(uint32_t tsen_offset)\n+{\n+ uint32_t v0 = 0, v1 = 0;\n+ float temp = 0;\n+ uint32_t regVal = 0;\n+ ADC_Result_Type result;\n+ uint32_t tmpVal;\n+ uint8_t gainCalEnabled = 0;\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ ADC_SET_TSVBE_LOW();\n+\n+ ADC_Start();\n+\n+ while (ADC_Get_FIFO_Count() == 0)\n+ ;\n+\n+ regVal = ADC_Read_FIFO();\n+\n+ gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable;\n+ adcGainCoeffCal.adcGainCoeffEnable = 0;\n+ ADC_Parse_Result(®Val, 1, &result);\n+ adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;\n+ v0 = result.value;\n+\n+ /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);\n+\n+ ADC_SET_TSVBE_HIGH();\n+\n+ ADC_Start();\n+\n+ while (ADC_Get_FIFO_Count() == 0)\n+ ;\n+\n+ regVal = ADC_Read_FIFO();\n+ gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable;\n+ adcGainCoeffCal.adcGainCoeffEnable = 0;\n+ ADC_Parse_Result(®Val, 1, &result);\n+ adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;\n+ v1 = result.value;\n+\n+ if (v0 > v1) {\n+ temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;\n+ } else {\n+ temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753;\n+ }\n+\n+ return temp;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC MIC Config\n+ *\n+ * @param adc_mic_config: adc_mic_config\n+ *\n+ * @return success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config)\n+{\n+ uint32_t tmpVal1 = 0, tmpVal2 = 0;\n+\n+ CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb));\n+ CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain));\n+ CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode));\n+ CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode));\n+ CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn));\n+ CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn));\n+ CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn));\n+ CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn));\n+\n+ tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);\n+\n+ tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) {\n+ /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/\n+ return ERROR;\n+ } else {\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn);\n+ }\n+\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn);\n+\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC MIC bias control\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_MIC_Bias_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief ADC MIC bias control\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ADC_MIC_Bias_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);\n+ BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Trim ADC Gain\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void)\n+{\n+ Efuse_ADC_Gain_Coeff_Type trim;\n+ uint32_t tmp;\n+\n+ EF_Ctrl_Read_ADC_Gain_Trim(&trim);\n+\n+ if (trim.adcGainCoeffEn) {\n+ if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) {\n+ adcGainCoeffCal.adcGainCoeffEnable = ENABLE;\n+ adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff;\n+ tmp = adcGainCoeffCal.adcgainCoeffVal;\n+\n+ if (tmp & 0x800) {\n+ tmp = ~tmp;\n+ tmp += 1;\n+ tmp = tmp & 0xfff;\n+ //printf(\"val==%08x\\r\\n\",(unsigned int)tmp);\n+ adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0));\n+ //printf(\"coe==%0f\\r\\n\",adcGainCoeffCal.coe);\n+ } else {\n+ adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0));\n+ //printf(\"coe==%0f\\r\\n\",adcGainCoeffCal.coe);\n+ }\n+\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/*@} end of group ADC_Public_Functions */\n+\n+/*@} end of group ADC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9e1684aabbc84bd2e2bff206ceaa49209ba72852\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c\n@@ -0,0 +1,537 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_aon.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_aon.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup AON\n+ * @{\n+ */\n+\n+/** @defgroup AON_Private_Macros\n+ * @{\n+ */\n+#define AON_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+\n+/*@} end of group AON_Private_Macros */\n+\n+/** @defgroup AON_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group AON_Private_Types */\n+\n+/** @defgroup AON_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group AON_Private_Variables */\n+\n+/** @defgroup AON_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group AON_Global_Variables */\n+\n+/** @defgroup AON_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group AON_Private_Fun_Declaration */\n+\n+/** @defgroup AON_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group AON_Private_Functions */\n+\n+/** @defgroup AON_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Power on MXX band gap\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Power up RF for PLL to work */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(55);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off MXX band gap\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Power OFF */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on XTAL\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ /* Polling for ready */\n+ do {\n+ arch_delay_us(10);\n+ timeOut++;\n+ tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);\n+\n+ if (timeOut >= 120) {\n+ return TIMEOUT;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set XTAL cap code\n+ *\n+ * @param capIn: Cap code in\n+ * @param capOut: Cap code out\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);\n+ BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);\n+\n+ arch_delay_us(100);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get XTAL cap code\n+ *\n+ * @param None\n+ *\n+ * @return Cap code\n+ *\n+*******************************************************************************/\n+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off XTAL\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on bandgap system\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* power up RF for PLL to work */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);\n+ BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);\n+\n+ arch_delay_us(55);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off bandgap system\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* power up RF for PLL to work */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);\n+ BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);\n+\n+ arch_delay_us(55);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim dcdc11 vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC11_Vout(void)\n+{\n+ Efuse_Ana_DCDC11_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_DCDC11_Trim(&trim);\n+ if (trim.trimDcdc11VoutAonEn) {\n+ if (trim.trimDcdc11VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc11VoutAon, 4)) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_TRIM_AON, trim.trimDcdc11VoutAon);\n+ BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim dcdc18 vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_DCDC18_Vout(void)\n+{\n+ Efuse_Ana_DCDC18_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_DCDC18_Trim(&trim);\n+ if (trim.trimDcdc18VoutAonEn) {\n+ if (trim.trimDcdc18VoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimDcdc18VoutAon, 4)) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_TRIM_AON, trim.trimDcdc18VoutAon);\n+ BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim usb20 rcal vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_USB20_RCAL(void)\n+{\n+ Efuse_Ana_USB20RCAL_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_USB20RCAL_Trim(&trim);\n+ if (trim.trimUsb20rcalAonEn) {\n+ if (trim.trimUsb20rcalAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimUsb20rcalAon, 6)) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.trimUsb20rcalAon);\n+ BL_WR_REG(AON_BASE, AON_PSW_IRRCV, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on LDO15_RF\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* ldo15rf power on */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(90);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off LDO15_RF\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* ldo15rf power off */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power on source follow regular\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* power on sfreg */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(10);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power off source follow regular\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* power off sfreg */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off the power can be shut down in PDS0\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* power off sfreg */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_MISC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);\n+ BL_WR_REG(AON_BASE, AON_MISC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ /* gating Clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpVal = tmpVal & (~(1 << 6));\n+ tmpVal = tmpVal & (~(1 << 7));\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on the power powered down in PDS0\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(20);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(60);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);\n+ BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);\n+\n+ arch_delay_us(20);\n+\n+ /* power on wb */\n+ tmpVal = BL_RD_REG(AON_BASE, AON_MISC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);\n+ BL_WR_REG(AON_BASE, AON_MISC, tmpVal);\n+\n+ /* ungating Clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpVal = tmpVal | ((1 << 6));\n+ tmpVal = tmpVal | ((1 << 7));\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AON set DCDC11_Top voltage out\n+ *\n+ * @param dcdcLevel: DCDC11_Top volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel));\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel);\n+ BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+/*@} end of group AON_Public_Functions */\n+\n+/*@} end of group AON */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ed3e902940f6d1377e96c47a19d9817be0212ab5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c\n@@ -0,0 +1,2814 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_audio.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_audio.h\"\n+#include \"audio_reg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup AUDIO\n+ * @{\n+ */\n+\n+/** @defgroup AUDIO_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group AUDIO_Private_Macros */\n+\n+/** @defgroup AUDIO_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group AUDIO_Private_Types */\n+\n+/** @defgroup AUDIO_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *audioIntCbfArra[AUDIO_INT_NUM_ALL] = { NULL };\n+#endif\n+/*@} end of group AUDIO_Private_Variables */\n+\n+/** @defgroup AUDIO_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group AUDIO_Global_Variables */\n+\n+/** @defgroup AUDIO_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group AUDIO_Private_Fun_Declaration */\n+\n+/** @defgroup AUDIO_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group AUDIO_Private_Functions */\n+\n+/** @defgroup AUDIO_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Select Tx channel source Defaule is tx0-dac_0,tx1-dac_1\n+ *\n+ * @param tx_channel: tx_channel index . Note tx_channel <=2\n+ * @param dac_id: tx[rx_channel] conect to dac_id\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_Tx_Source_DAC_Sel(uint8_t tx_channel, Audio_DAC_ID_Type dac_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+\n+ if (tx_channel > 2) {\n+ return ERROR;\n+ /*tx channel sel can not larger than 2*/\n+ }\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+\n+ if (tx_channel == 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX0_SEL, dac_id);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX1_SEL, dac_id);\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select Rx channel form ADC Channel . source Default selction is\n+ * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1\n+ *\n+ * @param rx_channel: rx_channel index . Note tx_channel <=4\n+ * @param adc_id: rx[rx_channel] conect to adc_id\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_Rx_Source_ADC_Sel(uint8_t rx_channel, Audio_ADC_ID_Type adc_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ if (rx_channel > 4) {\n+ return ERROR;\n+ /*rx channel sel can not larger than 4*/\n+ }\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+\n+ switch (rx_channel) {\n+ case 0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, adc_id);\n+ break;\n+ case 1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, adc_id);\n+ break;\n+ case 2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, adc_id);\n+ break;\n+ case 3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, adc_id);\n+ break;\n+ case 4:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, adc_id);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select Rx channel form AEC Channel . source Default selction is\n+ * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1\n+ *\n+ * @param rx_channel: tx_channel index . Note tx_channel <=4\n+ * @param aec_id: rx[rx_channel] conect to aec_id\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_Rx_Source_AEC_Sel(uint8_t rx_channel, Audio_AEC_ID_Type aec_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id));\n+\n+ if (rx_channel > 4) {\n+ return ERROR;\n+ /*rx channel sel can not larger than 4*/\n+ }\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+\n+ switch (rx_channel) {\n+ case 0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, aec_id + 3);\n+ break;\n+ case 1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, aec_id + 3);\n+ break;\n+ case 2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, aec_id + 3);\n+ break;\n+ case 3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, aec_id + 3);\n+ break;\n+ case 4:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, aec_id + 3);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio Set HPF Parameter\n+ *\n+ * @param id: ADC ID\n+ * @param k1_enable: k1 parameter enable\n+ * @param k1: k1 parameter in range 4 bit\n+ * @param k2_enable: k2 parameter enable\n+ * @param k2: k1 parameter in range 4 bit\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_HPF_Parameter(Audio_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_1);\n+\n+ switch (id) {\n+ case AUDIO_ADC_0:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN);\n+ }\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN);\n+ }\n+ break;\n+ case AUDIO_ADC_1:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN);\n+ }\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN);\n+ }\n+ break;\n+ case AUDIO_ADC_2:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN);\n+ }\n+\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN);\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio Set ADC Source PDM or Analog\n+ *\n+ * @param id: k1 parameter in range 4 bit ,when k0=0 k0 parameter will disabled\n+ * @param adc_source: k2 parameter in range 4 bit ,when k1=0 k1 parameter will disabled\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_ADC_Source(Audio_ADC_ID_Type id, Audio_ADC_Source_Type adc_source)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0);\n+\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SRC, adc_source);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SRC, adc_source);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SRC, adc_source);\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio AEC enable\n+ *\n+ * @param id: Auido AEC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_AEC_Enable(Audio_AEC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_AEC_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_0_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_1_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio AEC disable\n+ *\n+ * @param id: Auido AEC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_AEC_Disable(Audio_AEC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_AEC_0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_0_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_1_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio ADC enable\n+ *\n+ * @param id: Auido ADC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_Enable(Audio_ADC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_EN);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio ADC disable\n+ *\n+ * @param id: Auido ADC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_Disable(Audio_ADC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_EN);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio DAC disable\n+ *\n+ * @param id: Auido DAC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_DAC_Enable(Audio_DAC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_DAC_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_0_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_1_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio DAC disable\n+ *\n+ * @param id: Auido DAC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_DAC_Disable(Audio_DAC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ if (id == AUDIO_DAC_0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_0_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_1_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dac amp\n+ *\n+ * @param enable: enable or noy\n+ * @param amp: amp\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_Dither(uint8_t enable, uint8_t amp)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_AMP, amp);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 0);\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dac scaling\n+ *\n+ * @param enable: enable or noy\n+ * @param scaling: scaling\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_Scaling(uint8_t enable, uint8_t scaling)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_FACTOR, scaling);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 0);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set order\n+ *\n+ * @param order: order\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_Order(Audio_DAC_Order_Type order)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ORDER_TYPE(order));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_ORDER, order);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_Set_DAC_Dwa_Swap\n+ *\n+ * @param swap: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_Dwa_Swap(uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_OUT_SWAP, swap);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_Set_DAC_Dsm_Bypass\n+ *\n+ * @param bypass: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_Dwa_Bypass(uint8_t bypass)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_BYPASS, bypass);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set adc lfsr\n+ *\n+ * @param lfsrType: Auido ADC LFSR TYPE\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_DAC_LFSR(Audio_LFSR_Type lfsrType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_LFSR_TYPE(lfsrType));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_LFSR_MODE, lfsrType);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief read LSFR\n+ *\n+ * @param None\n+ *\n+ * @return read LSFR out\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_Get_ADC_LFSR(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0);\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_DITHER_DATA);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set adc scaling value\n+ *\n+ * @param id: Auido ADC ID\n+ * @param scalingVal: scaling value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_ADC_Scaling_Value(Audio_ADC_ID_Type id, uint8_t scalingVal)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0);\n+\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SCAL, scalingVal);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SCAL, scalingVal);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SCAL, scalingVal);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set fir mode\n+ *\n+ * @param id: Auido ADC ID\n+ * @param enable: enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_Fir_Mode(Audio_ADC_ID_Type id, uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0);\n+\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_FIR_MODE, enable);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_FIR_MODE, enable);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_FIR_MODE, enable);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mixer setting function\n+ *\n+ * @param enable: enbale mixer or not,if disable mixer then other parameter is invalid\n+ * @param mixerId: mixer Id,audio have two mixer to selected\n+ * @param mode: mixer mode selection , debug mode or sidetone mode(other source is come form\n+ * adc0-adc2)\n+ * @param sidetoneChannel: mixer adc channel selection , if debug mode is selected this paramter is\n+ * used , or user must select which adc source will be mixed with dac output.\n+ * @param Volume: mixer Volume select\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_Mixer_Mode(uint8_t enable, Audio_Mixer_ID_Type mixerId, Audio_Mixer_Mode mode, Audio_ADC_ID_Type sidetoneChannel, Audio_Mixer_Volume_Type Volume)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_MIXER_ID_TYPE(sidetoneChannel));\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(sidetoneChannel));\n+ CHECK_PARAM(IS_AUDIO_MIXER_VOLUME_TYPE(Volume));\n+ CHECK_PARAM(IS_AUDIO_MIXER_MODE(mode));\n+\n+ if (mixerId == AUDIO_MIXER_ID_0) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1);\n+ }\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, mode);\n+ if (mode == AUDIO_SECOND_DEBUG_MODE) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE1, Volume);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_SEL, sidetoneChannel + 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE2, Volume);\n+ }\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, 0);\n+ }\n+\n+ if (mixerId == AUDIO_MIXER_ID_0) {\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal);\n+ } else {\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set adc swap\n+ *\n+ * @param id: Auido ADC ID\n+ * @param swap: swap\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_Mash_Bit_Swap(Audio_ADC_ID_Type id, uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0);\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_MASH_BIT_SWAP, swap);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_MASH_BIT_SWAP, swap);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_MASH_BIT_SWAP, swap);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set pdm inv\n+ *\n+ * @param id: Auido ADC ID\n+ * @param swap: inv\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_PDM_Inv_Swap(Audio_ADC_ID_Type id, uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0);\n+ if (id == AUDIO_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap);\n+ } else if (id == AUDIO_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set pdm value\n+ *\n+ * @param pdm_l: pdm l\n+ * @param pdm_h: pdm h\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_L, pdm_l);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_H, pdm_l);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_Set_AEC_Record_Vid\n+ *\n+ * @param enable: enable or not\n+ * @param div: div\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_AEC_Record_Vid(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_DIV, div);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 0);\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_Set_AEC_Atten_mode\n+ *\n+ * @param aec_id: AEC ID\n+ * @param mode: Atten Mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Set_AEC_Atten_mode(Audio_AEC_ID_Type aec_id, Audio_AEC_Atten_Mode mode)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0);\n+\n+ if (aec_id == AUDIO_AEC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_0_ATTEN_MODE, mode);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_1_ATTEN_MODE, mode);\n+ }\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio support three channel for pdm .Meanwhile Audio support two DMIC Interface which\n+ * supporting four pdm data source input.This function is used to select channel with pdm\n+ * source.\n+ *\n+ * @param id: pdm channel,cannot be larger than 3\n+ * @param pdmSel: pdm source select\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+void Audio_ADC_PDM_Channel_Sel(Audio_PDM_ID_Type id, Audio_PDM_Source_Type pdmSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_PDM_SOURCE_TYPE(pdmSel));\n+ CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0);\n+\n+ if (id == AUDIO_PDM_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_PDM_SEL, pdmSel);\n+ } else if (id == AUDIO_PDM_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_SEL, pdmSel);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_PDM_SEL, pdmSel);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio Enable PDM\n+ *\n+ * @param id: PDM ID\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+void Audio_ADC_PDM_Enable(Audio_PDM_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0);\n+\n+ if (id == AUDIO_PDM_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_0_EN);\n+ } else if (id == AUDIO_PDM_1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_1_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_2_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio Disable PDM\n+ *\n+ * @param id: None\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+void Audio_ADC_PDM_Disable(Audio_PDM_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0);\n+\n+ if (id == AUDIO_PDM_0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN);\n+ } else if (id == AUDIO_PDM_1) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief debug 0x24 reigister\n+ *\n+ * @param wCmd: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Debug0_Write(uint32_t wCmd)\n+{\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DBG_0, wCmd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief debug 0x28 reigister\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+uint32_t Debug1_Read(void)\n+{\n+ return BL_RD_REG(AUDIO_BASE, AUDIO_DBG_1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief debug 0x2c reigister\n+ *\n+ * @param wCmd: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Debug2_Write(uint32_t wCmd)\n+{\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DBG_2, wCmd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief debug 0x30 reigister\n+ *\n+ * @param wCmd: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Debug3_Write(uint32_t wCmd)\n+{\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DBG_3, wCmd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUDIO Interrupt mask\n+ *\n+ * @param intType: intType\n+ * @param intMask: intMask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Auido_IntMask(Audio_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ switch (intType) {\n+ case AUDIO_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUDIO_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUDIO_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+ break;\n+\n+ case AUDIO_INT_TX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUDIO_INT_TX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUDIO_INT_TX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN);\n+ }\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+ break;\n+\n+ case AUDIO_INT_ADC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_ADC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+\n+ case AUDIO_INT_ADC2_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_DAC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_DAC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_VAD:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, intMask);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_NUM_ALL:\n+ if (intMask) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0x40A0A80);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0);\n+ }\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear audio Interrupt flag\n+ *\n+ * @param intType: intType\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Auido_IntClear(Audio_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case AUDIO_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(AUDIO_BASE, AUDIO_RXU_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal);\n+ break;\n+\n+ case AUDIO_INT_TX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_TX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUDIO_INT_TX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal);\n+ break;\n+\n+ case AUDIO_INT_ADC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+ case AUDIO_INT_ADC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+\n+ case AUDIO_INT_ADC2_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+ case AUDIO_INT_DAC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+ case AUDIO_INT_DAC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+ case AUDIO_INT_VAD:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ tmpVal2 = tmpVal;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2);\n+ break;\n+ case AUDIO_INT_NUM_ALL:\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal | 0x40A0A80);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal);\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief register interrupt callback function pointer\n+ *\n+ * @param intType: intType\n+ * @param cbFun: cbFun\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type Audio_Int_Callback_Install(Audio_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ CHECK_PARAM(IS_AUDIO_INT_TYPE(intType));\n+\n+ audioIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief read int flag\n+ *\n+ * @param intType: intType\n+ *\n+ * @return flag status\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_GetIntStatus(Audio_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+ BL_Sts_Type rlt = RESET;\n+\n+ CHECK_PARAM(IS_AUDIO_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case AUDIO_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXA_INT);\n+ break;\n+ case AUDIO_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXO_INT);\n+ break;\n+ case AUDIO_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXU_INT);\n+ break;\n+\n+ case AUDIO_INT_TX_FIFO_THR:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXA_INT);\n+ break;\n+ case AUDIO_INT_TX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXO_INT);\n+ break;\n+ case AUDIO_INT_TX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXU_INT);\n+ break;\n+\n+ case AUDIO_INT_ADC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S0_INT);\n+ break;\n+ case AUDIO_INT_ADC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S1_INT);\n+ break;\n+\n+ case AUDIO_INT_ADC2_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S2_INT);\n+ break;\n+ case AUDIO_INT_DAC0_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S0_INT);\n+ break;\n+ case AUDIO_INT_DAC1_SET_VOLUME_DONE:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S1_INT);\n+ break;\n+ case AUDIO_INT_VAD:\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_VAD_INT);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return rlt;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief rx fifo flush\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_RxFifoClear(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RX_FIFO_FLUSH);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Rx FIFO Count\n+ *\n+ * @param None\n+ *\n+ * @return fifi count\n+ *\n+*******************************************************************************/\n+uint32_t Audio_GetRxFifoCount(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RXA_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read RX FIFO\n+ *\n+ * @param None\n+ *\n+ * @return fifo data\n+ *\n+*******************************************************************************/\n+uint32_t Audio_ReadRxFifo(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_DATA);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief tx fifo flush\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_TxFifoClear(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TX_FIFO_FLUSH);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Tx FIFO Count\n+ *\n+ * @param None\n+ *\n+ * @return fifi count\n+ *\n+*******************************************************************************/\n+uint32_t Audio_GetTxFifoCount(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TXA_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Wirte TX FIFO\n+ *\n+ * @param da: None\n+ *\n+ * @return fifo data\n+ *\n+*******************************************************************************/\n+void Audio_WriteTxFifo(uint32_t da)\n+{\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_DATA, da);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Configure rx fifo\n+ *\n+ * @param cfg: fifo cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_RxFifoConfig(Audio_FifoCfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution));\n+ CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode));\n+ CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_RES, cfg->resolution);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_MODE, cfg->ailgnMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_CNT, cfg->dmaThresholdMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_TRG_LEVEL, cfg->FifoIntThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_EN, cfg->dmaEn);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_EN, cfg->dmaEn);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief enable rx fifo\n+ *\n+ * @param ch: ch\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_RxFifoEnable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, ch);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief disable rx fifo\n+ *\n+ * @param ch: fifo cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_RxFifoDisable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN);\n+\n+ tmpVal2 &= ~ch;\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, tmpVal2);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief enable rx fifo\n+ *\n+ * @param ch: ch\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_TxFifoEnable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, ch);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief disable rx fifo\n+ *\n+ * @param ch: fifo cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_TxFifoDisable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN);\n+\n+ tmpVal2 &= ~ch;\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, tmpVal2);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Tx FIFO Count\n+ *\n+ * @param cfg: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_TxFifoConfig(Audio_FifoCfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution));\n+ CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode));\n+ CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_RES, cfg->resolution);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_MODE, cfg->ailgnMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_CNT, cfg->dmaThresholdMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_TRG_LEVEL, cfg->FifoIntThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_EN, cfg->dmaEn);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_EN, cfg->dmaEn);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_PEQ_Config\n+ *\n+ * @param peq_index: PEQ index should be in range[0,19]\n+ * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild\n+ * @param qtfm: PEQ qtfm\n+ * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3\n+ * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2\n+ *\n+ * @return PEQ Setting is success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_PEQ_Config(uint8_t peq_index, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t peqAddr = 0;\n+ if (peq_index > 19) {\n+ return ERROR;\n+ /* PEQ only support [0,19] index */\n+ }\n+ peqAddr = AUDIO_BASE + 0x200 + (peq_index * 0x14);\n+\n+ if (peqBypass == 0) {\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_B0, b_pra[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_QFMT, qtfm);\n+\n+ BL_WR_WORD(peqAddr, tmpVal);\n+\n+ BL_WR_WORD(peqAddr + 0x04, b_pra[1]);\n+ BL_WR_WORD(peqAddr + 0x08, b_pra[2]);\n+ BL_WR_WORD(peqAddr + 0x0c, a_pra[0]);\n+ BL_WR_WORD(peqAddr + 0x10, a_pra[1]);\n+\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass);\n+ BL_WR_WORD(peqAddr, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass);\n+ BL_WR_WORD(peqAddr, tmpVal);\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio_ADC_PEQ_Config\n+ *\n+ * @param peq_index: PEQ index should be in range[0,19]\n+ * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild\n+ * @param qtfm: PEQ qtfm\n+ * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3\n+ * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2\n+ *\n+ * @return PEQ Setting is success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_PEQ_Config(uint8_t peq_index, Audio_ADC_ID_Type adcChannel, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t peqAddr = 0;\n+ if (peq_index > 19) {\n+ return ERROR;\n+ /* PEQ only support [0,19] index */\n+ }\n+ peqAddr = AUDIO_BASE + 0x390 + (peq_index * 0x14);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x390);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PEQ_IN_SEL, adcChannel);\n+ BL_WR_WORD(peqAddr, tmpVal);\n+\n+ if (peqBypass == 0) {\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_B0, b_pra[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_QFMT, qtfm);\n+\n+ BL_WR_WORD(peqAddr, tmpVal);\n+\n+ BL_WR_WORD(peqAddr + 0x04, b_pra[1]);\n+ BL_WR_WORD(peqAddr + 0x08, b_pra[2]);\n+ BL_WR_WORD(peqAddr + 0x0c, a_pra[0]);\n+ BL_WR_WORD(peqAddr + 0x10, a_pra[1]);\n+\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass);\n+ BL_WR_WORD(peqAddr, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(peqAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass);\n+ BL_WR_WORD(peqAddr, tmpVal);\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio adc Mute\n+ *\n+ * @param muteSyncAllAdc: mute Sync All ADC Channle\n+ * @param adc_id: adc id\n+ * @param mute: Mute Or Not\n+ *\n+ * @return success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Set_Mute(BL_Fun_Type muteSyncAllAdc, Audio_ADC_ID_Type adc_id, Audio_Mute_Type mute)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+ CHECK_PARAM(IS_AUDIO_MUTE_TYPE(mute));\n+\n+ if (muteSyncAllAdc) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_MUTE, mute);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal);\n+ } else {\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE, mute);\n+ BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio adc Mute\n+ *\n+ * @param muteSyncAllDac: mute Sync All DAC Channle\n+ * @param dac_id: dac id\n+ * @param mute: Mute Or Not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_Set_Mute(BL_Fun_Type muteSyncAllDac, Audio_DAC_ID_Type dac_id, Audio_Mute_Type mute)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id));\n+ CHECK_PARAM(IS_AUDIO_MUTE_TYPE(Mute));\n+\n+ if (muteSyncAllDac) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_MUTE, mute);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal);\n+ } else {\n+ if (dac_id > 1) {\n+ return ERROR;\n+ /*only support 2 dac*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE, mute);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio adc Volume Config\n+ *\n+ * @param adc_id: adc id\n+ * @param cfg: volume config cfg pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Software_Volume_Config(Audio_ADC_ID_Type adc_id, Audio_Volume_Cfg_Type *cfg)\n+{\n+ uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+ CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate));\n+ CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode));\n+ CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate));\n+\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_SOFTMODE, cfg->muteMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_MODE, cfg->volumeCtrMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate);\n+ BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout);\n+ BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio DAC Volume Config\n+ *\n+ * @param dac_id: dac id\n+ * @param cfg: volume config cfg pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_Software_Volume_Config(Audio_DAC_ID_Type dac_id, Audio_Volume_Cfg_Type *cfg)\n+{\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+ CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate));\n+ CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode));\n+ CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate));\n+\n+ if (dac_id > 1) {\n+ return ERROR;\n+ /*only support 2 dac*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_SOFTMODE, cfg->muteMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_MODE, cfg->volumeCtrMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset + 0x04, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set adc volume\n+ *\n+ * @param volumeSyncAllAdc: sync volume configuration for three adc channel\n+ * @param adc_id: adc id\n+ * @param volume: volume\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Set_Volume(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume)\n+{\n+ uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ if (volumeSyncAllAdc) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal);\n+\n+ //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+\n+ //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set dac volume\n+ *\n+ * @param volumeSyncAllDac: sync volume configuration for two dac channel\n+ * @param dac_id: dac id\n+ * @param volume: volume\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_Set_Volume(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume)\n+{\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+\n+ if (dac_id > 1) {\n+ return ERROR;\n+ /*only support 2 dac*/\n+ }\n+\n+ if (volumeSyncAllDac) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal);\n+\n+ //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+\n+ //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear adc update bit\n+ *\n+ * @param adc_id: adc id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type adc_id)\n+{\n+ uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ if (adc_id > 2) {\n+ return;\n+ /*only support 3 adc*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, 0);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear dac update bit\n+ *\n+ * @param dac_id: dac id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_DAC_Reset_Volume_Update(Audio_DAC_ID_Type dac_id)\n+{\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+\n+ if (dac_id > 1) {\n+ return;\n+ /*only support 2 dac*/\n+ }\n+\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, 0);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear adc or dac all update bit, when enable sync bit to set all channel dac/adc volume\n+ * ,user should use this function to clear all update flag.\n+ *\n+ * @param isAdcOrDac: IS ADC or DAC,ADC=1 DAC=0\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Reset_Volume_All_Update(uint8_t isAdcOrDac)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+ if (isAdcOrDac) {\n+ BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal);\n+ } else {\n+ BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set all adc volume Reg Without seting update bit\n+ *\n+ * @param volumeSyncAllAdc: is set all adc\n+ * @param adc_id: adc id\n+ * @param volume: volume\n+ *\n+ * @return Success or Not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume)\n+{\n+ uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ if (volumeSyncAllAdc) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set all DAC volume Reg Without seting update bit\n+ *\n+ * @param volumeSyncAllDac: is set all dac\n+ * @param dac_id: dac id\n+ * @param volume: volume\n+ *\n+ * @return Success or Not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume)\n+{\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+\n+ if (dac_id > 1) {\n+ return ERROR;\n+ /*only support 2 dac*/\n+ }\n+\n+ if (volumeSyncAllDac) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set adc volume\n+ *\n+ * @param volumeSyncAllAdc: sync volume configuration for three adc channel,This function will\n+ * blocking CPU until volume adjust task done\n+ * @param adc_id: adc id\n+ * @param volume: volume\n+ * @param blockTimeout: volume block timeout\n+ *\n+ * @return Configuration is success\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Set_Volume_Block(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume, uint32_t blockTimeout)\n+{\n+ uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ if (volumeSyncAllAdc) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal);\n+\n+ while (Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_0) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_1) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_2)) {\n+ blockTimeout--;\n+ if (blockTimeout) {\n+ return TIMEOUT;\n+ }\n+ }\n+ //clear update\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+\n+ while (Audio_IS_ADC_Volume_Set_Busy(adc_id)) {\n+ blockTimeout--;\n+ if (blockTimeout) {\n+ return TIMEOUT;\n+ }\n+ }\n+ //clear update\n+ tmpVal = BL_RD_WORD(adcVolumeAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 0);\n+ BL_WR_WORD(adcVolumeAddrOffset, tmpVal);\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set dac volume\n+ *\n+ * @param volumeSyncAllDac: sync volume configuration for two dac channel ,This function will\n+ * blocking CPU until volume adjust task done\n+ * @param dac_id: adc id\n+ * @param volume: volume\n+ * @param blockTimeout: volume block timeout\n+ *\n+ * @return is success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_DAC_Set_Volume_Block(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume, uint32_t blockTimeout)\n+{\n+ uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id));\n+\n+ if (dac_id > 1) {\n+ return ERROR;\n+ /*only support 2 dac*/\n+ }\n+\n+ if (volumeSyncAllDac) {\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume);\n+ BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal);\n+\n+ while (Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_0) && Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_1)) {\n+ blockTimeout--;\n+ if (blockTimeout) {\n+ return TIMEOUT;\n+ }\n+ }\n+ //clear update\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1);\n+ BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal);\n+\n+ //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr\n+ }\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio set adc agc hardware volume config\n+ *\n+ * @param cfg: cfg pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Audio_ADC_Hardware_Volume_Config(Audio_Volume_Cfg_Type *cfg)\n+{\n+ uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + AUDIO_ADC_H_OFFSET;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate));\n+ CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode));\n+ CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution));\n+ CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate));\n+\n+ tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE, cfg->muteMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPDN_RATE, cfg->muteRmpdnRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPUP_RATE, cfg->muteRmpupRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_MODE, cfg->volumeCtrMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_RMP_RATE, cfg->volumeRmpRate);\n+ BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal);\n+\n+ tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout);\n+ BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this\n+ * function\n+ *\n+ * @param None\n+ *\n+ * @return AGC ctr result\n+ *\n+*******************************************************************************/\n+uint16_t Audio_ADC_Get_Hardware_Volume(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint16_t volume = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_H);\n+ volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_VOLUME);\n+\n+ return volume;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this\n+ * function\n+ *\n+ * @param adc_id: adc id\n+ *\n+ * @return adc volume\n+ *\n+*******************************************************************************/\n+uint16_t Audio_ADC_Get_Volume(Audio_ADC_ID_Type adc_id)\n+{\n+ uint32_t tmpVal = 0;\n+ uint16_t volume = 0;\n+\n+ if (adc_id == AUDIO_ADC_0) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0);\n+ } else if (adc_id == AUDIO_ADC_1) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S1);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S2);\n+ }\n+\n+ volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME);\n+\n+ return volume;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this\n+ * function\n+ *\n+ * @param dac_id: dac id\n+ *\n+ * @return dac volume\n+ *\n+*******************************************************************************/\n+uint16_t Audio_DAC_Get_Volume(Audio_DAC_ID_Type dac_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (dac_id == AUDIO_DAC_0) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S1);\n+ }\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute done or not .\n+ *\n+ * @param adc_id: adc id\n+ *\n+ * @return is adc mute done\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_IS_ADC_Mute_Done(Audio_ADC_ID_Type adc_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+\n+ if (adc_id == AUDIO_ADC_0) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_MUTE_DONE);\n+ } else if (adc_id == AUDIO_ADC_1) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_MUTE_DONE);\n+ } else {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_MUTE_DONE);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute & volume set are busy or not .\n+ *\n+ * @param adc_id: adc id\n+ *\n+ * @return is adc volume set done\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_IS_ADC_Volume_Set_Busy(Audio_ADC_ID_Type adc_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+\n+ if (adc_id == AUDIO_ADC_0) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_BUSY);\n+ } else if (adc_id == AUDIO_ADC_1) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_BUSY);\n+ } else {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_BUSY);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute done or not .\n+ *\n+ * @param dac_id: dac id\n+ *\n+ * @return is dac mute done\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_IS_DAC_Mute_Set_Done(Audio_DAC_ID_Type dac_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+\n+ if (dac_id == AUDIO_DAC_0) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_MUTE_DONE);\n+ } else {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_MUTE_DONE);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute & volume set are busy or not .\n+ *\n+ * @param dac_id: dac id\n+ *\n+ * @return is dac_id done\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Audio_IS_DAC_Volume_Set_Busy(Audio_DAC_ID_Type dac_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS);\n+\n+ if (dac_id == AUDIO_DAC_0) {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_BUSY);\n+ } else {\n+ return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_BUSY);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute & volume set are busy or not .\n+ *\n+ * @param enable: enable agc\n+ * @param cfg: agc cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_AGC_Init(uint8_t enable, Audio_AGC_Config_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_AGC_SRC_TYPE(cfg->agc_src_select));\n+ CHECK_PARAM(IS_AUDIO_AGC_DETECT_MODE(cfg->agc_detect_mode));\n+\n+ if (enable) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_EN, cfg->agc_force_gain_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_IND, cfg->agc_force_gain_ind);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MAX_GAIN_QDB, cfg->agc_max_gain_qdb);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MIN_GAIN_QDB, cfg->agc_min_gain_qdb);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_TARGET, cfg->agc_level_target);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_ATTACK, cfg->agc_level_hyst_attack);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_DECAY, cfg->agc_level_hyst_decay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_HOLD_TIME_MS, cfg->agc_hold_time_ms);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DECAY_TIME_MS, cfg->agc_decay_time_ms);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME_MS, cfg->agc_attack_time_ms);\n+ //tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AUDIO_ADC3_PGA_HW_CTRL,cfg->adc3_pga_hw_ctrl); //TODO\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_HW_CTRL, cfg->adc2_pga_hw_ctrl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_HW_CTRL, cfg->adc1_pga_hw_ctrl);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_TH, cfg->agc_noise_gate_th);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_HYST, cfg->agc_noise_gate_hyst);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_QDB, cfg->agc_silence_gain_qdb);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_WAIT_MS, cfg->agc_silence_gain_wait_ms);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_ENTER_TIME_MS, cfg->agc_noise_enter_time_ms);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_EXIT_TIME_MS, cfg->agc_noise_exit_time_ms);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DBV_SETTLE_TIME, cfg->agc_dbv_settle_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SRC_SELECT, cfg->agc_src_select);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DETECT_MODE, cfg->agc_detect_mode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME, cfg->agc_attack_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_RELEASE_TIME, cfg->agc_release_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_AVERAGE_TIME, cfg->agc_average_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_PGA_CTRL_EN, cfg->agc_pga_ctrl_en);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is audio mute & volume set are busy or not .\n+ *\n+ * @param enable: enable drc\n+ * @param cfg: drc cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_DRC_Init(uint8_t enable, Audio_DRC_Config_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_raw_sel));\n+ CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_peak_sel));\n+ CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_avg_sel));\n+ CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->ngt_src_sel));\n+\n+ if (enable) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RAW_SEL, cfg->drc_raw_sel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_PEAK_SEL, cfg->drc_peak_sel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_SEL, cfg->drc_avg_sel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_EN, cfg->drc_avg_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_TIME, cfg->drc_avg_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATT_TIME, cfg->drc_att_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RLS_TIME, cfg->drc_rls_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_NGT_DOWNSAMPLE_EN, cfg->drc_ngt_downsample_en);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_L, cfg->drc_threshold_l);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_C, cfg->drc_threshold_c);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_E, cfg->drc_threshold_e);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_C, cfg->drc_slope_mode_c);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_E, cfg->drc_slope_mode_e);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_MAKEUP_GAIN, cfg->drc_makeup_gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATTACK_TIME, cfg->drc_attack_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RELEASE_TIME, cfg->drc_release_time);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_NGT_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_EN, cfg->ngt_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SRC_SEL, cfg->ngt_src_sel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_AVG_TIME, cfg->ngt_avg_time);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_THRESHOLD, cfg->ngt_threshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_HYSTERESIS, cfg->ngt_hysteresis);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_EN, cfg->ngt_noise_hold_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_TIME_K, cfg->ngt_noise_hold_time_k);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_EN, cfg->ngt_signal_hold_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_TIME_K, cfg->ngt_signal_hold_time_k);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_DMUTE_ON, cfg->ngt_dmute_on);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_NGT_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_ZD_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_EN, cfg->zd_en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_TIME, cfg->zd_time);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_ZD_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Audio interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AUDIO_IRQHandler(void)\n+{\n+ uint8_t intIndex = 0;\n+\n+ for (intIndex = 0; intIndex < AUDIO_INT_NUM_ALL; intIndex++) {\n+ if (Audio_GetIntStatus(intIndex) == SET) {\n+ if (audioIntCbfArra[intIndex] != NULL) {\n+ audioIntCbfArra[intIndex]();\n+ }\n+ Auido_IntClear(intIndex);\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Audio Clock Initialization Function\n+ *\n+ * @param cfg: clock configuration pra\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Clock_Init(Audio_Clock_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_ADC_CLOCK_TYPE(cfg->adc_clock));\n+ CHECK_PARAM(IS_AUDIO_DAC_CLOCK_TYPE(cfg->dac_clock));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_TOP);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_RATE, cfg->adc_clock);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RATE, cfg->dac_clock);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PDM_ITF_INV_SEL, cfg->pdm_clk_inv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_INV_SEL, cfg->adc_clk_inv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_INV_SEL, cfg->dac_clk_inv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CKG_EN, 1);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_AUD_TOP, tmpVal);\n+\n+ //TODO to select postion of register interrupt\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(AUDIO_IRQn, AUDIO_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief VAD Configuration function\n+ *\n+ * @param cfg: VAD configuration pra\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_VAD_Init(Audio_VAD_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUDIO_VAD_SOURCE_TYPE(cfg->vadSource));\n+ CHECK_PARAM(IS_AUDIO_VAD_FRAMINGSHIFT_TYPE(cfg->vadFramingShift));\n+ CHECK_PARAM(IS_AUDIO_VAD_FRAMINGTIME_TYPE(cfg->vadFramingTime));\n+ CHECK_PARAM(IS_AUDIO_VAD_IRQ_SOURCE_TYPE(cfg->vadIRQSource));\n+ CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERLEN_TYPE(cfg->vadNoisyBufferLen));\n+ CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERMONITOR_TYPE(cfg->vadNoisyBufferMonitor));\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_EN, cfg->vadNoisyBufferMonitorEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_CTRL, cfg->vadNoisyBufferMonitor);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_LEN_CTRL, cfg->vadNoisyBufferLen);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_OUT_SEL, cfg->vadIRQSource);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMETIME_CTRL, cfg->vadFramingTime);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMESHIFT_CTRL, cfg->vadFramingShift);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_IN_SEL, cfg->vadSource);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT_EN, cfg->vadNoisyMaxLimitEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT_EN, cfg->vadNoisyMinLimitEnable);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT, cfg->vadNoisyMinLimit);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT, cfg->vadNoisyMaxLimit);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_FALL, cfg->vadSmoothFall);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_RISE, cfg->vadSmoothRise);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_SCALE, cfg->noisyBufferThrScale);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_BIAS, cfg->noisyBufferThrBais);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_DISCARD, cfg->noisyBufferDiscardNumber);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NOISE_TH, cfg->noisyBufferThr);\n+\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief enable VAD\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_VAD_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_VAD_EN);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief disable VAD\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_VAD_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_VAD_EN);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief VAD set EK function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+uint32_t Audio_VAD_Get_EK(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_4);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief audio power on\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Audio_Poweron(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* common */\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MICBIAS_PU, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_VRDA_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_IBIAS_CTRL, 5);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_LDO25_PU, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_HPBG_PU, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER2, tmpVal);\n+\n+ /*DAC power on*/\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_SDAC_LINEOUT, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_MODE, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_DAC, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_LINEOUT, 1);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_SDAC_LINEOUT, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_MODE, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_DAC, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_LINEOUT, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_PU_VREF_RAMP, 1);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP, tmpVal);\n+\n+ /*ADC Power on */\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_SDM, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_PGA, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, 8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_ICTRL_ADC2, 3);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_SDM, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_PGA, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, 8);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_SDM, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_PGA, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, 8);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal);\n+\n+ /* best digital filter configuration*/\n+ Audio_Set_DAC_Scaling(1, 14);\n+}\n+\n+void Audio_SetADCAnalogGain(Audio_ADC_ID_Type adc, uint8_t analogGain)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (adc == AUDIO_ADC_0) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, analogGain);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal);\n+ } else if (adc == AUDIO_ADC_1) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, analogGain);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, analogGain);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal);\n+ }\n+}\n+\n+void Audio_SetDACAnalogGain(Audio_DAC_ID_Type dac, uint8_t analogGain)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (dac == AUDIO_DAC_0) {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_GAIN, analogGain);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_GAIN, analogGain);\n+ BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal);\n+ }\n+}\n+\n+/*@} end of group AUDIO_Public_Functions */\n+\n+/*@} end of group AUDIO */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..374422e2299de006ba9f24985501cb7ed5eb5970\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c\n@@ -0,0 +1,777 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_pdm.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_aupdm.h\"\n+#include \"pdm_reg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup AUDIOPDM\n+ * @{\n+ */\n+\n+/** @defgroup AUDIOPDM_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group AUDIOPDM_Private_Macros */\n+\n+/** @defgroup AUDIOPDM_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group AUDIOPDM_Private_Types */\n+\n+/** @defgroup AUDIOPDM_Private_Variables\n+ * @{\n+ */\n+static intCallback_Type *aupdmIntCbfArra[AUPDM_INT_NUM_ALL] = { NULL };\n+\n+/*@} end of group AUDIOPDM_Private_Variables */\n+\n+/** @defgroup AUDIOPDM_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group AUDIOPDM_Global_Variables */\n+\n+/** @defgroup AUDIOPDM_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group AUDIOPDM_Private_Fun_Declaration */\n+\n+/** @defgroup AUDIOPDM_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group AUDIOPDM_Private_Functions */\n+\n+/** @defgroup AUDIOPDM_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief AUDIO Interrupt mask\n+ *\n+ * @param intType: intType\n+ * @param intMask: intMask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_IntMask(Aupdm_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ switch (intType) {\n+ case AUPDM_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUPDM_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+ break;\n+ case AUPDM_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ if (intMask) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+ break;\n+\n+ case AUPDM_INT_NUM_ALL:\n+ if (intMask) {\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+\n+ } else {\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+ }\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief read int flag\n+ *\n+ * @param intType: intType\n+ *\n+ * @return flag status\n+ *\n+*******************************************************************************/\n+BL_Sts_Type Aupdm_GetIntStatus(Aupdm_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+ BL_Sts_Type rlt = RESET;\n+\n+ CHECK_PARAM(IS_AUPDM_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case AUPDM_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXA_INT);\n+ break;\n+ case AUPDM_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXO_INT);\n+ break;\n+ case AUPDM_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXU_INT);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return rlt;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear audio Interrupt flag\n+ *\n+ * @param intType: intType\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_IntClear(Aupdm_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case AUPDM_INT_RX_FIFO_THR:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUPDM_INT_RX_FIFO_OVERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal);\n+ break;\n+ case AUPDM_INT_RX_FIFO_UNDERRUN:\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ tmpVal = BL_SET_REG_BIT(PDM0_BASE, PDM_RXU_INT);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal);\n+ break;\n+\n+ case AUPDM_INT_NUM_ALL:\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT);\n+\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal);\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM PDM interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void AUPDM_PDM_IRQHandler(void)\n+{\n+ uint8_t intIndex = 0;\n+\n+ for (intIndex = 0; intIndex < AUPDM_INT_NUM_ALL; intIndex++) {\n+ if (Aupdm_GetIntStatus(intIndex) == SET) {\n+ aupdmIntCbfArra[intIndex]();\n+ Aupdm_IntClear(intIndex);\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM PDM Clock Initialization Function\n+ *\n+ * @param cfg: clock configuration pra\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_Clock_Init(Aupdm_Clock_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_CLOCK_TYPE(cfg->adc_clock));\n+ CHECK_PARAM(IS_AUPDM_DAC_CLOCK_TYPE(cfg->dac_clock));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_TOP);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_RATE, cfg->adc_clock);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ITF_INV_SEL, cfg->pdm_clk_inv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_INV_SEL, cfg->adc_clk_inv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUDIO_CKG_EN, 1);\n+\n+ BL_WR_REG(PDM0_BASE, PDM_AUDPDM_TOP, tmpVal);\n+\n+//TODO to select postion of register interrupt\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(AUPDM_TOUCH_IRQn, AUPDM_PDM_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM support three channel for pdm .Meanwhile AUPDM support two DMIC Interface which\n+ * supporting four pdm data source input.This function is used to select channel with pdm\n+ * source.\n+ *\n+ * @param id: pdm channel,cannot be larger than 3\n+ * @param pdmSel: pdm source select\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+void Aupdm_PDM_Channel_Sel(Aupdm_PDM_ID_Type id, Aupdm_PDM_Source_Type pdmSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_PDM_SOURCE_TYPE(pdmSel));\n+ CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0);\n+\n+ if (id == AUPDM_PDM_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_SEL, pdmSel);\n+ } else if (id == AUPDM_PDM_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_SEL, pdmSel);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_SEL, pdmSel);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM Enable PDM\n+ *\n+ * @param id: PDM ID\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+void Aupdm_PDM_Enable(Aupdm_PDM_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0);\n+\n+ if (id == AUPDM_PDM_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_0_EN);\n+ } else if (id == AUPDM_PDM_1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_1_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_2_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief register interrupt callback function pointer\n+ *\n+ * @param intType: intType\n+ * @param cbFun: cbFun\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Aupdm_Int_Callback_Install(Aupdm_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ CHECK_PARAM(IS_AUPDM_INT_TYPE(intType));\n+\n+ aupdmIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief rx fifo flush\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_RxFifoClear(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RX_FIFO_FLUSH);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Rx FIFO Count\n+ *\n+ * @param None\n+ *\n+ * @return fifi count\n+ *\n+*******************************************************************************/\n+uint32_t Aupdm_GetRxFifoCount(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDM_RXA_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read RX FIFO\n+ *\n+ * @param None\n+ *\n+ * @return fifo data\n+ *\n+*******************************************************************************/\n+uint32_t Aupdm_ReadRxFifo(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_DATA);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Configure rx fifo\n+ *\n+ * @param cfg: fifo cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_RxFifoConfig(Aupdm_FifoCfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_RESOLUTION_TYPE(cfg->resolution));\n+ CHECK_PARAM(IS_AUPDM_FIFO_AILGN_MODE(cfg->ailgnMode));\n+ CHECK_PARAM(IS_AUPDM_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_RES, cfg->resolution);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_MODE, cfg->ailgnMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_CNT, cfg->dmaThresholdMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_TRG_LEVEL, cfg->FifoIntThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_EN, cfg->dmaEn);\n+\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_EN, cfg->dmaEn);\n+ BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief enable rx fifo\n+ *\n+ * @param ch: ch\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_RxFifoEnable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, ch);\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief disable rx fifo\n+ *\n+ * @param ch: fifo cfg\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_RxFifoDisable(uint8_t ch)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN);\n+\n+ tmpVal2 &= ~ch;\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, tmpVal2);\n+\n+ BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select Rx channel form ADC Channel . source Default selction is\n+ * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1\n+ *\n+ * @param rx_channel: rx_channel index . Note tx_channel <=4\n+ * @param adc_id: rx[rx_channel] conect to adc_id\n+ *\n+ * @return Success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type Aupdm_Rx_Source_ADC_Sel(uint8_t rx_channel, Aupdm_ADC_ID_Type adc_id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(adc_id));\n+\n+ if (rx_channel > 4) {\n+ return ERROR;\n+ /*rx channel sel can not larger than 4*/\n+ }\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF);\n+\n+ switch (rx_channel) {\n+ case 0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX0_SEL, adc_id);\n+ break;\n+ case 1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX1_SEL, adc_id);\n+ break;\n+ case 2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX2_SEL, adc_id);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM ADC enable\n+ *\n+ * @param id: Auido ADC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_ADC_Enable(Aupdm_ADC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF);\n+ if (id == AUPDM_ADC_0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_EN);\n+ } else if (id == AUPDM_ADC_1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_EN);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM ADC disable\n+ *\n+ * @param id: Auido ADC ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_ADC_Disable(Aupdm_ADC_ID_Type id)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF);\n+ if (id == AUPDM_ADC_0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_EN);\n+ } else if (id == AUPDM_ADC_1) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_EN);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set adc scaling value\n+ *\n+ * @param id: Auido ADC ID\n+ * @param scalingVal: scaling value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_Set_ADC_Scaling_Value(Aupdm_ADC_ID_Type id, uint8_t scalingVal)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0);\n+\n+ if (id == AUPDM_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_SCAL, scalingVal);\n+ } else if (id == AUPDM_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_SCAL, scalingVal);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_SCAL, scalingVal);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set fir mode\n+ *\n+ * @param id: Auido ADC ID\n+ * @param enable: enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_Set_Fir_Mode(Aupdm_ADC_ID_Type id, uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0);\n+\n+ if (id == AUPDM_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_FIR_MODE, enable);\n+ } else if (id == AUPDM_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_FIR_MODE, enable);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_FIR_MODE, enable);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM Set HPF Parameter\n+ *\n+ * @param id: ADC ID\n+ * @param k1_enable: k1 parameter enable\n+ * @param k1: k1 parameter in range 4 bit\n+ * @param k2_enable: k2 parameter enable\n+ * @param k2: k1 parameter in range 4 bit\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_Set_HPF_Parameter(Aupdm_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_1);\n+\n+ switch (id) {\n+ case AUPDM_ADC_0:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K1_EN);\n+ }\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K2_EN);\n+ }\n+ break;\n+ case AUPDM_ADC_1:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K1_EN);\n+ }\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K2_EN);\n+ }\n+ break;\n+ case AUPDM_ADC_2:\n+ if (k1_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K1_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K1, k1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K1_EN);\n+ }\n+\n+ if (k2_enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K2_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K2, k2);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K2_EN);\n+ }\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set pdm inv\n+ *\n+ * @param id: Auido ADC ID\n+ * @param swap: inv\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_ADC_PDM_Inv_Swap(Aupdm_ADC_ID_Type id, uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0);\n+ if (id == AUPDM_ADC_0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_LVL_SWAP, swap);\n+ } else if (id == AUPDM_ADC_1) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_LVL_SWAP, swap);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_LVL_SWAP, swap);\n+ }\n+ BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set pdm value\n+ *\n+ * @param pdm_l: pdm l\n+ * @param pdm_h: pdm h\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Aupdm_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_L, pdm_l);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_H, pdm_l);\n+ BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AUPDM adc Volume Config\n+ *\n+ * @param adc_id: adc id\n+ * @param volume: volume config cfg pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type Aupdm_ADC_Volume_Config(Aupdm_ADC_ID_Type adc_id, uint8_t volume)\n+{\n+ if (adc_id > 2) {\n+ return ERROR;\n+ /*only support 3 adc*/\n+ }\n+\n+ if (adc_id == AUPDM_ADC_0) {\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_S0, volume);\n+ } else if (adc_id == AUPDM_ADC_1) {\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_S1, volume);\n+ } else {\n+ BL_WR_REG(PDM0_BASE, PDM_ADC_S2, volume);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group AUPDMPDM_Public_Functions */\n+\n+/*@} end of group AUPDMPDM */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..45f6c65da26ddc00c9014b3763d66e8235a24467\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c\n@@ -0,0 +1,979 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_cam.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_cam.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup CAM\n+ * @{\n+ */\n+\n+/** @defgroup CAM_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group CAM_Private_Macros */\n+\n+/** @defgroup CAM_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group CAM_Private_Types */\n+\n+/** @defgroup CAM_Private_Variables\n+ * @{\n+ */\n+static const uint32_t camAddr[CAM_ID_MAX] = { DVP0_BASE, DVP1_BASE, DVP2_BASE, DVP3_BASE,\n+ DVP4_BASE, DVP5_BASE, DVP6_BASE, DVP7_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *camIntCbfArra[CAM_ID_MAX][CAM_INT_ALL] = { { NULL } };\n+#endif\n+\n+/*@} end of group CAM_Private_Variables */\n+\n+/** @defgroup CAM_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group CAM_Global_Variables */\n+\n+/** @defgroup CAM_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void CAM_IntHandler(CAM_ID_Type camId);\n+#endif\n+\n+/*@} end of group CAM_Private_Fun_Declaration */\n+\n+/** @defgroup CAM_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Camera interrupt common handler function\n+ *\n+ * @param camId: Camera ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void CAM_IntHandler(CAM_ID_Type camId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT)) {\n+ CAM_IntClr(camId, CAM_INT_NORMAL);\n+\n+ if (camIntCbfArra[camId][CAM_INT_NORMAL] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_NORMAL]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT)) {\n+ CAM_IntClr(camId, CAM_INT_MEMORY_OVERWRITE);\n+\n+ if (camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT)) {\n+ CAM_IntClr(camId, CAM_INT_FRAME_OVERWRITE);\n+\n+ if (camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT)) {\n+ CAM_IntClr(camId, CAM_INT_FIFO_OVERWRITE);\n+\n+ if (camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {\n+ CAM_IntClr(camId, CAM_INT_HSYNC_CNT_ERROR);\n+\n+ if (camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {\n+ CAM_IntClr(camId, CAM_INT_VSYNC_CNT_ERROR);\n+\n+ if (camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR] != NULL) {\n+ /* call the callback function */\n+ camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group CAM_Private_Functions */\n+\n+/** @defgroup CAM_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Camera module init\n+ *\n+ * @param camId: CAM ID type\n+ * @param cfg: Camera configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Init(CAM_ID_Type camId, CAM_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode));\n+ CHECK_PARAM(IS_CAM_INPUT_PIX_WIDTH_TYPE(cfg->pixWidth));\n+ CHECK_PARAM(IS_CAM_OUTPUT_DROP_MODE_TYPE(cfg->dropMode));\n+ CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol));\n+ CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol));\n+ CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType));\n+ CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode));\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_CAM);\n+\n+ /* Set camera configuration */\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_MODE, cfg->pixWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_XLEN, cfg->burstType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount);\n+\n+ switch (cfg->dropMode) {\n+ case CAM_DROP_NONE:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN);\n+ break;\n+\n+ case CAM_DROP_ODD_ROW_ODD_PIXEL:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL);\n+ break;\n+\n+ case CAM_DROP_ODD_ROW_EVEN_PIXEL:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL);\n+ break;\n+\n+ case CAM_DROP_ALL_ODD_PIXEL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN);\n+ break;\n+\n+ case CAM_DROP_ALL_EVEN_PIXEL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+\n+ /* Set frame count to issue interrupt at sw mode */\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt);\n+ BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal);\n+\n+ /* Set camera memory start address, memory brust size and frame byte size */\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_ADDR_START, cfg->memStart & 0xFFFFFFF0);\n+\n+ switch (cfg->burstType) {\n+ case CAM_BURST_TYPE_SINGLE:\n+ tmpVal = cfg->memSize / 8;\n+ break;\n+\n+ case CAM_BURST_TYPE_INCR4:\n+ tmpVal = cfg->memSize / 32;\n+ break;\n+\n+ case CAM_BURST_TYPE_INCR8:\n+ tmpVal = cfg->memSize / 64;\n+ break;\n+\n+ case CAM_BURST_TYPE_INCR16:\n+ tmpVal = cfg->memSize / 128;\n+ break;\n+\n+ case CAM_BURST_TYPE_INCR32:\n+ tmpVal = cfg->memSize / 256;\n+ break;\n+\n+ case CAM_BURST_TYPE_INCR64:\n+ tmpVal = cfg->memSize / 512;\n+ break;\n+\n+ default:\n+ tmpVal = 0;\n+ break;\n+ }\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_MEM_BCNT, tmpVal);\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT, cfg->frameSize);\n+\n+ /* Clear interrupt */\n+ BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(DVP2BUS_INT0_IRQn, CAM0_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT1_IRQn, CAM1_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT2_IRQn, CAM2_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT3_IRQn, CAM3_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT4_IRQn, CAM4_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT5_IRQn, CAM5_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT6_IRQn, CAM6_IRQHandler);\n+ Interrupt_Handler_Register(DVP2BUS_INT7_IRQn, CAM7_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Deinit camera module\n+ *\n+ * @param camId: CAM ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Deinit(CAM_ID_Type camId)\n+{\n+ switch(camId){\n+ case CAM0_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSA);\n+ break;\n+ case CAM1_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSB);\n+ break;\n+ case CAM2_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSC);\n+ break;\n+ case CAM3_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSD);\n+ break;\n+ case CAM4_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSE);\n+ break;\n+ case CAM5_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSF);\n+ break;\n+ case CAM6_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSG);\n+ break;\n+ case CAM7_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSH);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable camera module\n+ *\n+ * @param camId: CAM ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Enable(CAM_ID_Type camId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ /* Enable camera module */\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable camera module\n+ *\n+ * @param camId: CAM ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Disable(CAM_ID_Type camId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ /* Disable camera module */\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera clock gate function\n+ *\n+ * @param camId: CAM ID type\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Clock_Gate(CAM_ID_Type camId, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera hsync crop function\n+ *\n+ * @param camId: CAM ID type\n+ * @param start: Valid hsync start count\n+ * @param end: Valid hsync end count\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Hsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end)\n+{\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_HSYNC_CROP, (start << 16) + end);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera vsync crop function\n+ *\n+ * @param camId: CAM ID type\n+ * @param start: Valid vsync start count\n+ * @param end: Valid vsync end count\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Vsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end)\n+{\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_VSYNC_CROP, (start << 16) + end);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera set total valid pix count in a line function\n+ *\n+ * @param camId: CAM ID type\n+ * @param count: Count value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Set_Hsync_Total_Count(CAM_ID_Type camId, uint16_t count)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera set total valid line count in a frame function\n+ *\n+ * @param camId: CAM ID type\n+ * @param count: Count value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Set_Vsync_Total_Count(CAM_ID_Type camId, uint16_t count)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get one camera frame\n+ *\n+ * @param camId: CAM ID type\n+ * @param info: Camera frame infomation pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Get_Frame_Info(CAM_ID_Type camId, CAM_Frame_Info *info)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR);\n+\n+ info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT);\n+ info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_FRAME_ID_STS01), CAM_FRAME_ID_0);\n+ info->curFrameAddr = BL_RD_REG(CAMx, CAM_FRAME_START_ADDR0);\n+ info->curFrameBytes = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT);\n+ info->status = tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get available count of frames\n+ *\n+ * @param camId: CAM ID type\n+ *\n+ * @return Frames count\n+ *\n+*******************************************************************************/\n+uint8_t CAM_Get_Frame_Count(CAM_ID_Type camId)\n+{\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Pop one camera frame\n+ *\n+ * @param camId: CAM ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Pop_Frame(CAM_ID_Type camId)\n+{\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ /* Pop one frame */\n+ BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA Enable Disable Interrupt\n+ *\n+ * @param camId: CAM ID type\n+ * @param intType: CAMERA Interrupt Type\n+ * @param intMask: Enable or Disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_IntMask(CAM_ID_Type camId, CAM_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_CAM_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR);\n+\n+ switch (intType) {\n+ case CAM_INT_NORMAL:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_MEMORY_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_FRAME_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_FIFO_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_VSYNC_CNT_ERROR:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_HSYNC_CNT_ERROR:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);\n+ }\n+\n+ break;\n+\n+ case CAM_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* Enable all interrupt */\n+ tmpVal |= 0xFC0;\n+ } else {\n+ /* Disable all interrupt */\n+ tmpVal &= 0xFFFFF03F;\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA Interrupt Clear\n+ *\n+ * @param camId: CAM ID type\n+ * @param intType: CAMERA Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_IntClr(CAM_ID_Type camId, CAM_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP_FRAME_FIFO_POP);\n+\n+ switch (intType) {\n+ case CAM_INT_NORMAL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR);\n+ break;\n+\n+ case CAM_INT_MEMORY_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR);\n+ break;\n+\n+ case CAM_INT_FRAME_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR);\n+ break;\n+\n+ case CAM_INT_FIFO_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR);\n+ break;\n+\n+ case CAM_INT_VSYNC_CNT_ERROR:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR);\n+ break;\n+\n+ case CAM_INT_HSYNC_CNT_ERROR:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR);\n+ break;\n+\n+ case CAM_INT_ALL:\n+ tmpVal = 0xFFFF0;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install camera interrupt callback function\n+ *\n+ * @param camId: CAM ID type\n+ * @param intType: CAMERA interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM_Int_Callback_Install(CAM_ID_Type camId, CAM_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_CAM_INT_TYPE(intType));\n+\n+ camIntCbfArra[camId][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA input 8-bit mode lower/upper byte select function\n+ *\n+ * @param camId: CAM ID type\n+ * @param byteType: Byte type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_8_Bit_Byte_Select(CAM_ID_Type camId, CAM_8_Bit_Byte_Type byteType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_CAM_8_BIT_BYTE_TYPE(byteType));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_BSEL, byteType);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA input 16-bit mode RGB order select function\n+ *\n+ * @param camId: CAM ID type\n+ * @param rgbType: RGB order type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_16_Bit_RGB_order(CAM_ID_Type camId, CAM_16_Bit_RGB_Type rgbType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_CAM_16_BIT_RGB_TYPE(rgbType));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FORMAT_565, rgbType);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA input 32-bit mode alpha value set function\n+ *\n+ * @param camId: CAM ID type\n+ * @param alpha: Alpha value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_32_Bit_Alpha_Set(CAM_ID_Type camId, uint8_t alpha)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_ALPHA, alpha);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAMERA set frame period and bitwise frame valid in period function\n+ *\n+ * @param camId: CAM ID type\n+ * @param period: Frame period count\n+ * @param validBit: Bitwise frame valid in period\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_Set_Frame_Valid_Period(CAM_ID_Type camId, uint8_t period, uint32_t validBit)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_PERIOD, period);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD, tmpVal);\n+\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_VLD, validBit);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable or disable function that covers first frame memory everytime in hardware mode\n+ *\n+ * @param camId: CAM ID type\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void CAM_HW_Cover_First_Frame_Everytime(CAM_ID_Type camId, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t CAMx = camAddr[camId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(camId));\n+\n+ tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable);\n+ BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM0_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM1_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM1_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 2 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM2_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 3 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM3_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM3_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 4 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM4_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM4_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 5 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM5_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM5_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 6 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM6_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM6_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Camera 7 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void CAM7_IRQHandler(void)\n+{\n+ CAM_IntHandler(CAM7_ID);\n+}\n+#endif\n+\n+/*@} end of group CAM_Public_Functions */\n+\n+/*@} end of group CAM */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6e1e001ecc40bc6412a0de99dfef89376b18d9ff\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c\n@@ -0,0 +1,671 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_can.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_glb.h\"\n+#include \"bl808_can.h\"\n+#include \"bflb_platform.h\"\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type * canIntCbfArra[CAN_INT_ALL] = { NULL };\n+static void CAN_IntHandler(void);\n+static void CAN_IRQHandler(void);\n+#endif\n+\n+void CAN_Init(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable CAN clock witch share with UART2 */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2);\n+\n+ /* Enable UART clock*/\n+ tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0);\n+ tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN);\n+ BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal);\n+\n+ /* UART2 and CAN can not work together */\n+ GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_CAN_FD);\n+\n+ /* Need to enter reset mode before operating */\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET);\n+\n+ /* Force using PeliCAN not BasicCAN */\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_CLOCK_DIVIDER);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_MODE);\n+ BL_WR_REG(CAN_BASE, CAN_CLOCK_DIVIDER, tmpVal);\n+\n+ /* Disable all interrupts */\n+ BL_WR_REG(CAN_BASE, CAN_INTERRUPT_ENABLE, 0);\n+\n+ /* Set clock and sample point */\n+ CAN_Clock_Div_Set(0);\n+ CAN_Synchronization_Jump_Width_Set(3);\n+ CAN_Sample_Parameter_Set(1, 8, 5);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(UART2_IRQn, CAN_IRQHandler);\n+#endif\n+}\n+\n+void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_MODE_TYPE(type));\n+ CHECK_PARAM(IS_CAN_MODE_VALUE_TYPE(value));\n+\n+ /* Set mode value */\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE);\n+ tmpVal &= ~(1 << type);\n+ tmpVal |= (value << type); \n+\n+ /* Write back */\n+ BL_WR_REG(CAN_BASE, CAN_MODE, tmpVal);\n+}\n+\n+CAN_MODE_VALUE_Type CAN_Mode_Get(CAN_MODE_Type type)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_MODE_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE);\n+ tmpVal &= (1 << type);\n+ tmpVal >>= type;\n+ return (CAN_MODE_VALUE_Type)tmpVal;\n+}\n+\n+void CAN_Int_Enable(CAN_INT_Type intType, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT_ENABLE);\n+ /* Enable or Disable certain or all interrupt */\n+ if(CAN_INT_ALL == intType){\n+ if(ENABLE == enable){\n+ tmpVal |= 0xFF;\n+ }else{\n+ tmpVal &= 0;\n+ }\n+ }else{\n+ if(ENABLE == enable){\n+ tmpVal |= 1<<intType;\n+ }else{\n+ tmpVal &= ~(1<<intType);\n+ }\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(CAN_BASE, CAN_INTERRUPT_ENABLE, tmpVal);\n+}\n+\n+void CAN_Cmd_Request_Transmit(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_TRANSMIT_REQUEST);\n+ BL_WR_REG(CAN_BASE, CAN_COMMAND, tmpVal);\n+}\n+void CAN_Cmd_Abort_Transmit(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_ABORT_TRANSMISSION);\n+ BL_WR_REG(CAN_BASE, CAN_COMMAND, tmpVal);\n+}\n+void CAN_Cmd_Release_Recv_Buff(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_RELEASE_RECEIVE_BUFFER);\n+ BL_WR_REG(CAN_BASE, CAN_COMMAND, tmpVal);\n+}\n+void CAN_Cmd_Clear_Data_Overrun(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_CLEAR_DATA_OVERRUN);\n+ BL_WR_REG(CAN_BASE, CAN_COMMAND, tmpVal);\n+}\n+void CAN_Cmd_Request_Self_Reception(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CAN_SELF_REQUEST);\n+ BL_WR_REG(CAN_BASE, CAN_COMMAND, tmpVal);\n+}\n+\n+CAN_STATUS_VALUE_Type CAN_Status_Get(CAN_STATUS_Type type)\n+{\n+ volatile uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_STATUS_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_STATUS);\n+ tmpVal &= (1 << type);\n+ tmpVal >>= type;\n+ return (CAN_STATUS_VALUE_Type)tmpVal;\n+}\n+\n+uint8_t CAN_Arbitration_Lost_Position_Get(void)\n+{\n+ uint8_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_ARB_LOST_CAPTURE);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, CAN_ALC4_0);\n+ return tmpVal;\n+}\n+\n+void CAN_Error_Get(CAN_ERROR_Type *const type)\n+{\n+ uint8_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_ERROR_CODE_CAPTURE);\n+ type->code = BL_GET_REG_BITS_VAL(tmpVal, CAN_ERR_CODE);\n+ type->dir = BL_GET_REG_BITS_VAL(tmpVal, CAN_DIR);\n+ type->location = BL_GET_REG_BITS_VAL(tmpVal, CAN_SEGMENT4_0);\n+}\n+\n+BL_Err_Type CAN_Error_Warning_Limit_Set(uint8_t limit)\n+{\n+ if(CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+ BL_WR_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT, limit);\n+ return SUCCESS;\n+}\n+\n+uint8_t CAN_Error_Warning_Limit_Get(void)\n+{\n+ return BL_RD_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT);\n+}\n+\n+uint8_t CAN_Error_Rx_Counter_Get(void)\n+{\n+ return BL_RD_REG(CAN_BASE, CAN_RX_ERR_COUNT);\n+}\n+\n+uint8_t CAN_Error_Tx_Counter_Get(void)\n+{\n+ return BL_RD_REG(CAN_BASE, CAN_TX_ERR_COUNT);\n+}\n+\n+BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg)\n+{\n+ uint32_t timeOut;\n+ uint32_t tmpVal;\n+ uint32_t i;\n+ volatile uint32_t *pData;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr));\n+ CHECK_PARAM(IS_CAN_FRAME_TYPE(cfg->frameType));\n+ CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->frameFormat));\n+\n+ timeOut = cfg->timeout;\n+\n+ /* Chcek Timeout type */\n+ while(CAN_STATUS_TRANSMIT_BUFFER_LOCKED == CAN_Status_Get(CAN_STATUS_TRANSMIT_BUFFER))\n+ {\n+ /* Wait no time */\n+ if (cfg->timeout == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ /* Wait until transmit buffer accessible */\n+ if (cfg->timeout >= CAN_TIMEOUT_MAX)\n+ {\n+\n+ }\n+ /* Wait time = cfg->timeOut */\n+ else\n+ {\n+ if(timeOut == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ timeOut--;\n+ }\n+ }\n+\n+ /* Config information register */\n+ tmpVal = cfg->dataLen;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_FF, cfg->frameFormat);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_RTR, cfg->frameType);\n+ BL_WR_REG(CAN_BASE, CAN_INFORMATION, tmpVal);\n+\n+ tmpVal = cfg->id;\n+ /* Transmit format with 11 bits ID, SFF */\n+ if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat)\n+ {\n+ /* Config identifier registers */\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 3) & 0xFF);\n+ tmpVal <<= 5;\n+ tmpVal |= (cfg->frameType << 4);\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, tmpVal & 0xFF);\n+ /* Config SFF data registers start address */\n+ pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET);\n+ }\n+ /* Transmit format with 29 bits ID, EFF */\n+ else\n+ {\n+ /* Config identifier registers */\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 21) & 0xFF);\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, (tmpVal >> 13) & 0xFF);\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_3, (tmpVal >> 5) & 0xFF);\n+ tmpVal <<= 3;\n+ tmpVal |= (cfg->frameType << 2);\n+ BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_4, tmpVal & 0xFF);\n+ /* Config EFF data registers start address */\n+ pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET);\n+ }\n+ /* Move data from user buff to registers */\n+ for (i = 0; i < cfg->dataLen; i++)\n+ {\n+ *(pData + i) = (uint32_t)(*(cfg->dataAddr + i));\n+ }\n+\n+ /* Trig a request for transmit */\n+ if(CAN_MODE_VALUE_RESET == CAN_Mode_Get(CAN_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+ else if(CAN_MODE_VALUE_LISTEN_ONLY == CAN_Mode_Get(CAN_MODE_TYPE_LISTEN_ONLY))\n+ {\n+ return ERROR;\n+ }\n+ else if(CAN_MODE_VALUE_SELF_TSET == CAN_Mode_Get(CAN_MODE_TYPE_SELF_TSET))\n+ {\n+ CAN_Cmd_Request_Self_Reception();\n+ }\n+ else\n+ {\n+ CAN_Cmd_Request_Transmit();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+BL_Err_Type CAN_Receive(CAN_CFG_Type *cfg)\n+{\n+ uint32_t timeOut;\n+ uint32_t tmpVal;\n+ uint32_t i;\n+ uint32_t id;\n+ volatile uint32_t *pData;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr));\n+\n+ timeOut = cfg->timeout;\n+\n+ /* Chcek Timeout type */\n+ while(CAN_STATUS_RECEIVE_BUFFER_EMPTY == CAN_Status_Get(CAN_STATUS_RECEIVE_BUFFER))\n+ {\n+ /* Wait no time */\n+ if (cfg->timeout == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ /* Wait until transmit buffer accessible */\n+ if (cfg->timeout >= CAN_TIMEOUT_MAX)\n+ {\n+\n+ }\n+ /* Wait time = cfg->timeOut */\n+ else\n+ {\n+ if(timeOut == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ timeOut--;\n+ }\n+ }\n+\n+ /* Read information register */\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_INFORMATION);\n+ cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_FF);\n+ cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_RTR);\n+ cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_DLC);\n+\n+ /* Receive with 11 bits ID */\n+ if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat)\n+ {\n+ /* Read identifier registers */\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1);\n+ id = ((tmpVal & 0xFF) << 3);\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2);\n+ id |= (tmpVal & 0xFF) >> 5;\n+ /* Config SFF data registers start address */\n+ pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET);\n+ }\n+ /* Receive with 29 bits ID */\n+ else\n+ {\n+ /* Read identifier registers */\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1);\n+ id = ((tmpVal & 0xFF) << 21);\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2);\n+ id |= (tmpVal & 0xFF) << 13;\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_3);\n+ id |= (tmpVal & 0xFF) << 5;\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_4);\n+ id |= (tmpVal & 0xFF) >> 3;\n+ /* Config EFF data registers start address */\n+ pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET);\n+ }\n+ cfg->id = id;\n+\n+ /* Move data from registers to user buff */\n+ for (i = 0; i < cfg->dataLen; i++)\n+ {\n+ *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF);\n+ }\n+\n+ CAN_Cmd_Release_Recv_Buff();\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t CAN_Receive_Buff_Frame_Count_Get(void)\n+{\n+ volatile uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_RX_MESSAGE_COUNT);\n+ return (uint8_t)(tmpVal & 0xFF);\n+}\n+\n+BL_Err_Type CAN_Clock_Div_Set(uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Must be operated in reset mode */\n+ if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER, div);\n+ BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t CAN_Clock_Div_Get(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0);\n+ return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER);\n+}\n+\n+BL_Err_Type CAN_Synchronization_Jump_Width_Set(uint8_t width)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Must be operated in reset mode */\n+ if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH, width);\n+ BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t CAN_Synchronization_Jump_Width_Get(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0);\n+ return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH);\n+}\n+\n+BL_Err_Type CAN_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Must be operated in reset mode */\n+ if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1, head);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2, tail);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SAMPLING, num);\n+ BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_1, tmpVal & 0xFF);\n+\n+ return SUCCESS;\n+}\n+\n+void CAN_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_1);\n+ *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1);\n+ *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2);\n+ *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SAMPLING);\n+}\n+\n+void CAN_Filter_Set(const CAN_FILTER_CFG_Type *cfg)\n+{\n+ uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask\n+\n+ /* Config filter must be in reset mode */\n+ CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET);\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET);\n+\n+\n+ /* Single filter mode */\n+ if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode)\n+ {\n+ CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE);\n+ /* Filter: ID10~0 + RTR + Data1 + Data2 */\n+ if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 << 5);\n+ tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4);\n+ tmpVal[2] = cfg->matchData1;\n+ tmpVal[3] = cfg->matchData2;\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 << 5);\n+ tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4);\n+ tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0\n+ tmpVal[6] = cfg->maskData1;\n+ tmpVal[7] = cfg->maskData2;\n+ }\n+ /* Filter: ID28~0 + RTR */\n+ else if(CAN_FRAME_FORMAT_EXTENDED == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13);\n+ tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5);\n+ tmpVal[3] = (uint8_t)(cfg->matchId1 << 3);\n+ tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13);\n+ tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5);\n+ tmpVal[7] = (uint8_t)(cfg->maskId1 << 3);\n+ tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2);\n+ tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0\n+ }\n+ }\n+ /* Dual filter mode */\n+ else if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode)\n+ {\n+ CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL);\n+ /* Filter1: ID10~0 + RTR + Data1 */\n+ /* Filter2: ID10~0 + RTR */\n+ if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 << 5);\n+ tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4);\n+ tmpVal[1] |= (cfg->matchData1 >> 4);\n+ tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3);\n+ tmpVal[3] = (uint8_t)(cfg->matchId2 << 5);\n+ tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4);\n+ tmpVal[3] |= (cfg->matchData1 & 0xF);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 << 5);\n+ tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4);\n+ tmpVal[5] |= (cfg->maskData1 >> 4);\n+ tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3);\n+ tmpVal[7] = (uint8_t)(cfg->maskId2 << 5);\n+ tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4);\n+ tmpVal[7] |= (cfg->maskData1 & 0xF);\n+ }\n+ /* Filter1: ID28~13 */\n+ /* Filter2: ID28~13 */\n+ else if (CAN_FRAME_FORMAT_EXTENDED == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13);\n+ tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21);\n+ tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13);\n+ tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21);\n+ tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13);\n+ }\n+ }\n+ /* Write configuration to Registers*/\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)tmpVal[4]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)tmpVal[5]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)tmpVal[6]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)tmpVal[7]);\n+\n+ /* Recovery reset mode value */\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset);\n+}\n+\n+void CAN_Filter_Register_Set(CAN_FILTER_REGISTER_Type reg, uint8_t value)\n+{\n+ /* Config filter must be in reset mode */\n+ CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET);\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET);\n+\n+ /* Write configuration to Register*/\n+ BL_WR_WORD(CAN_BASE + CAN_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value);\n+\n+ /* Recovery reset mode value */\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset);\n+}\n+\n+void CAN_Filter_Registers_Set(uint8_t *valueArr)\n+{\n+ /* Config filter must be in reset mode */\n+ CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET);\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET);\n+\n+ /* Write configuration to Registers*/\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)valueArr[4]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)valueArr[5]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)valueArr[6]);\n+ BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)valueArr[7]);\n+\n+ /* Recovery reset mode value */\n+ CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset);\n+}\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type CAN_Int_Callback_Install(CAN_INT_Type intType,intCallback_Type* cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cbFun));\n+ CHECK_PARAM(IS_CAN_INT_TYPE(intType));\n+\n+ canIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+\n+static void CAN_IntHandler(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t i = 0;\n+\n+ tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT);\n+\n+ for(i=0; i<CAN_INT_ALL; i++)\n+ {\n+ if(tmpVal & (1 << i))\n+ {\n+ if (canIntCbfArra[i])\n+ {\n+ canIntCbfArra[i]();\n+ }\n+ }\n+ }\n+}\n+\n+void CAN_IRQHandler(void)\n+{\n+ CAN_IntHandler();\n+}\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5274d840de02b0101716ca3c231ae617dec1fb02\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c\n@@ -0,0 +1,2304 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_clock.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_clock.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup CLOCK\n+ * @{\n+ */\n+\n+/** @defgroup CLOCK_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Private_Macros */\n+\n+/** @defgroup CLOCK_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Private_Types */\n+\n+/** @defgroup CLOCK_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Private_Variables */\n+\n+/** @defgroup CLOCK_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Global_Variables */\n+\n+/** @defgroup CLOCK_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Private_Fun_Declaration */\n+\n+/** @defgroup CLOCK_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group CLOCK_Private_Functions */\n+\n+/** @defgroup CLOCK_Public_Functions\n+ * @{\n+ */\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)\n+{\n+ uint8_t xtalType = 0;\n+ uint32_t tmpVal = 0;\n+ uint32_t vcoFreq = 0;\n+ uint32_t calculationDiv = (1 << 19);\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG6), GLB_WIFIPLL_SDMIN);\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType)\n+ {\n+ /* Calculation method:* wifipll_sdmin / calculationDiv * xtal_freq * 1000 * 1000 / cpupll_refdiv_ratio */\n+ case GLB_XTAL_NONE:\n+ return (0);\n+ case GLB_XTAL_24M:\n+ /* 960000000 */\n+ vcoFreq = tmpVal / calculationDiv * 24 * 1000 * 1000;\n+ break; \n+ case GLB_XTAL_32M:\n+ /* 960000000 */\n+ vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);\n+ break; \n+ case GLB_XTAL_38P4M:\n+ /* 960000000 */\n+ vcoFreq = tmpVal / calculationDiv * 384 * 100 * (1000 / 2);\n+ break;\n+ case GLB_XTAL_40M:\n+ /* 960000000 */\n+ vcoFreq = tmpVal / calculationDiv * 40 * 1000 * (1000 / 2);\n+ break;\n+ case GLB_XTAL_26M:\n+ /* 959920000 */\n+ vcoFreq = 200 * tmpVal / calculationDiv * 26 * 5000;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ /* 960000000 */\n+ vcoFreq = tmpVal / calculationDiv * 32 * 1000 * (1000 / 2);\n+ break; \n+ default:\n+ return (0);\n+ }\n+ } else {\n+ return (0);\n+ }\n+\n+ if ( (vcoFreq >= 955000000) && (vcoFreq <= 965000000) ) {\n+ /* vcoFreq:959920000~960000000 */\n+ return (pllOut);\n+ } else {\n+ return (0);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t pllOut)\n+{\n+ uint8_t xtalType = 0;\n+ uint32_t tmpVal = 0;\n+ uint32_t vcoFreq = 0;\n+ uint32_t calculationDiv = (1 << 11);\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_CPU_PLL_CFG6), CCI_CPUPLL_SDMIN);\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType)\n+ {\n+ /* Calculation method:xtal_freq * 1000 * cpupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */\n+ case GLB_XTAL_NONE:\n+ return (0);\n+ case GLB_XTAL_24M:\n+ /* 480000000;399996000;379998000 */\n+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);\n+ break; \n+ case GLB_XTAL_32M:\n+ /* 480000000;400000000;380000000 */\n+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break; \n+ case GLB_XTAL_38P4M:\n+ /* 480000000;399998250;379996750 */\n+ vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4); \n+ break;\n+ case GLB_XTAL_40M:\n+ /* 480000000;400000000;380000000 */\n+ vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break;\n+ case GLB_XTAL_26M:\n+ /* 479997000;399997500;379996000 */\n+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);\n+ break;\n+ case GLB_XTAL_RC32M:\n+ /* 480000000;400000000;380000000 */\n+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break; \n+ default:\n+ return (0);\n+ }\n+ } else {\n+ return (0);\n+ }\n+\n+ if ( (vcoFreq >= 475000000) && (vcoFreq <= 485000000) ) {\n+ /* vcoFreq:479997000~480000000 */\n+ return (pllOut / 100 * 120);\n+ } else if ( (vcoFreq >= 395000000 && vcoFreq <= 405000000) ) {\n+ /* vcoFreq:399996000~400000000 */\n+ return (pllOut);\n+ } else if ( (vcoFreq >= 375000000 && vcoFreq <= 385000000) ) {\n+ /* vcoFreq:379996000~380000000 */\n+ return (pllOut / 100 * 95);\n+ } else {\n+ return (0);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)\n+{\n+ uint8_t xtalType = 0;\n+ uint32_t tmpVal = 0;\n+ uint32_t vcoFreq = 0;\n+ uint32_t calculationDiv = (1 << 11);\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN);\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType)\n+ {\n+ /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */\n+ case GLB_XTAL_NONE:\n+ return (0);\n+ case GLB_XTAL_24M:\n+ /* 442365000;451582000 */\n+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);\n+ break; \n+ case GLB_XTAL_32M:\n+ /* 442367000;451582000 */\n+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break; \n+ case GLB_XTAL_38P4M:\n+ /* 442364000;451579500; */\n+ vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4); \n+ break;\n+ case GLB_XTAL_40M:\n+ /* 442368000;451582000 */\n+ vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break;\n+ case GLB_XTAL_26M:\n+ /* 442368000;451578500 */\n+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);\n+ break;\n+ case GLB_XTAL_RC32M:\n+ /* 442367000;451582000 */\n+ vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);\n+ break; \n+ default:\n+ return (0);\n+ }\n+ } else {\n+ return (0);\n+ }\n+\n+ if ( (vcoFreq >= 451000000) && (vcoFreq <= 452000000) ) {\n+ /* vcoFreq:451578500~451582000 */\n+ vcoFreq = 451584000;\n+ } else if ( (vcoFreq >= 442000000) && (vcoFreq <= 443000000) ) {\n+ /* vcoFreq:442364000~442368000 */\n+ vcoFreq = 442368000;\n+ } else {\n+ return (0);\n+ }\n+\n+ switch (clockAupllType) {\n+ case CLOCK_AUPLL_DIV1:\n+ return (vcoFreq);\n+ case CLOCK_AUPLL_DIV2:\n+ return (vcoFreq / 2);\n+ case CLOCK_AUPLL_DIV2P5:\n+ return (vcoFreq * 2 / 5);\n+ case CLOCK_AUPLL_DIV3:\n+ return (vcoFreq / 3);\n+ case CLOCK_AUPLL_DIV4:\n+ return (vcoFreq / 4);\n+ case CLOCK_AUPLL_DIV5:\n+ return (vcoFreq / 5);\n+ case CLOCK_AUPLL_DIV6:\n+ return (vcoFreq / 6);\n+ case CLOCK_AUPLL_DIV10:\n+ return (vcoFreq / 10);\n+ case CLOCK_AUPLL_DIV15:\n+ return (vcoFreq / 15);\n+ default:\n+ return (0);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);\n+\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;\n+ \n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()\n+{\n+ uint8_t xtalType = 0;\n+ uint32_t tmpVal = 0;\n+ uint32_t vcoFreq = 0;\n+ uint32_t calculationDiv = (1 << 11);\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG6), GLB_MIPIPLL_SDMIN);\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType)\n+ {\n+ /* Calculation method:xtal_freq * 1000 or 500 * mipipll_sdmin / calculationDiv * 1000 or 2000 / cpupll_refdiv_ratio */\n+ case GLB_XTAL_NONE:\n+ return (0);\n+ case GLB_XTAL_24M:\n+ /* 1500000000 */\n+ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * 1000;\n+ break; \n+ case GLB_XTAL_32M:\n+ /* 1500000000 */\n+ vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);\n+ break; \n+ case GLB_XTAL_38P4M:\n+ /* 1500000000 */\n+ vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000 / 2); \n+ break;\n+ case GLB_XTAL_40M:\n+ /* 1500000000 */\n+ vcoFreq = 40 * 500 * tmpVal / calculationDiv * (2000 / 2);\n+ break;\n+ case GLB_XTAL_26M:\n+ /* 1499989000 */\n+ vcoFreq = 26 * 1000 * tmpVal / calculationDiv * 1000;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ /* 1500000000 */\n+ vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);\n+ break; \n+ default:\n+ return (0);\n+ }\n+ } else {\n+ return (0);\n+ }\n+\n+ if ( (vcoFreq >= 1490000000) && (vcoFreq <= 1510000000) ) {\n+ /* vcoFreq:1499989000~1500000000 */\n+ return (1500000000);\n+ } else {\n+ return (0);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()\n+{\n+ uint8_t xtalType = 0;\n+ uint32_t tmpVal = 0;\n+ uint32_t vcoFreq = 0;\n+ uint32_t calculationDiv = (1 << 11);\n+\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG6), GLB_UHSPLL_SDMIN);\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType)\n+ {\n+ /* Calculation method:xtal_freq * 500 or 250 * uhspll_sdmin / calculationDiv * 2000 or 4000 / cpupll_refdiv_ratio */\n+ case GLB_XTAL_NONE:\n+ return (0);\n+ case GLB_XTAL_24M:\n+ /* 2299992000;2199996000;2100000000;1999992000;1599996000;1500000000;1399992000;1065996000;799992000;666996000;399996000 */\n+ vcoFreq = 24 * 500 * tmpVal / calculationDiv * 2000;\n+ break; \n+ case GLB_XTAL_32M:\n+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */\n+ vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);\n+ break; \n+ case GLB_XTAL_38P4M:\n+ /* 2299996000;2199992000;2100000000;1999996000;1599992000;1500000000;1399996000;1065992000;799996000;666992000;399992000 */\n+ vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000 / 2); \n+ break;\n+ case GLB_XTAL_40M:\n+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1065996000;800000000;666992000;400000000 */\n+ vcoFreq = 40 * 250 * tmpVal / calculationDiv * (4000 / 2);\n+ break;\n+ case GLB_XTAL_26M:\n+ /* 2299996000;2199996000;2099994000;1999994000;1599990000;1499988000;1399988000;1066000000;799994000;666998000;399990000 */\n+ vcoFreq = 26 * 500 * tmpVal / calculationDiv * 2000;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */\n+ vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);\n+ break; \n+ default:\n+ return (0);\n+ }\n+ } else {\n+ return (0);\n+ }\n+\n+ if ( (vcoFreq >= 2295000000) && (vcoFreq <= 2305000000) ) {\n+ /* vcoFreq:2299992000~2300000000 */\n+ return (2300000000);\n+ } else if ( (vcoFreq >= 2195000000) && (vcoFreq <= 2205000000) ) {\n+ /* vcoFreq:2199992000~2200000000 */\n+ return (2200000000);\n+ } else if ( (vcoFreq >= 2095000000) && (vcoFreq <= 2105000000) ) {\n+ /* vcoFreq:2099994000~2100000000 */\n+ return (2100000000);\n+ } else if ( (vcoFreq >= 1995000000 && vcoFreq <= 2005000000) ) {\n+ /* vcoFreq:1999992000~2000000000 */\n+ return (2000000000);\n+ } else if ( (vcoFreq >= 1595000000 && vcoFreq <= 1605000000) ) {\n+ /* vcoFreq:1599990000~1600000000 */\n+ return (1600000000);\n+ } else if ( (vcoFreq >= 1495000000 && vcoFreq <= 1505000000) ) {\n+ /* vcoFreq:1499988000~1500000000 */\n+ return (1500000000);\n+ } else if ( (vcoFreq >= 1395000000 && vcoFreq <= 1405000000) ) {\n+ /* vcoFreq:1399988000~1400000000 */\n+ return (1400000000);\n+ } else if ( (vcoFreq >= 1064000000 && vcoFreq <= 1068000000) ) {\n+ /* vcoFreq:1065992000~1066000000 */\n+ return (1066000000);\n+ } else if ( (vcoFreq >= 799000000 && vcoFreq <= 801000000) ) {\n+ /* vcoFreq:799992000~800000000 */\n+ return (800000000);\n+ } else if ( (vcoFreq >= 666000000 && vcoFreq <= 668000000) ) {\n+ /* vcoFreq:666992000~667000000 */\n+ return (667000000);\n+ } else if ( (vcoFreq >= 399000000 && vcoFreq <= 401000000) ) {\n+ /* vcoFreq:399990000~400000000 */\n+ return (400000000);\n+ } else {\n+ return (0);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut)\n+{\n+ return Clock_Get_WIFI_PLL_Output(pllOut);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut)\n+{\n+ return Clock_Get_WIFI_PLL_Output(pllOut);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut)\n+{\n+ return Clock_Get_CPU_PLL_Output(pllOut);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)\n+{\n+ uint8_t xtalType = 0;\n+\n+ if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {\n+ switch (xtalType) {\n+ case GLB_XTAL_NONE:\n+ return 0;\n+ case GLB_XTAL_24M:\n+ return 24 * 1000 * 1000;\n+ case GLB_XTAL_32M:\n+ return 32 * 1000 * 1000;\n+ case GLB_XTAL_38P4M:\n+ return 38.4 * 1000 * 1000;\n+ case GLB_XTAL_40M:\n+ return 40 * 1000 * 1000;\n+ case GLB_XTAL_26M:\n+ return 26 * 1000 * 1000;\n+ case GLB_XTAL_RC32M:\n+ return 32 * 1000 * 1000;\n+ default:\n+ return 0;\n+ }\n+ } else {\n+ return 40 * 1000 * 1000;\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* rc32m */\n+ return (32 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* xtal */\n+ return Clock_Xtal_Output();\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)\n+{\n+ uint32_t tmpVal;\n+ uint32_t div = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);\n+\n+ if (sel == 0) {\n+ /* src32K */\n+ return (32 * 1000);\n+ } else if (sel == 1) {\n+ /* xtal 32K */\n+ return (32 * 1000);\n+ } else {\n+ return Clock_Xtal_Output() / (div + 1);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm wifi pll 320m */\n+ return Clock_DSP_Get_WIFI_PLL_Output(320 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* mm aupll div1 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm wifi pll 240m */\n+ return Clock_DSP_Get_WIFI_PLL_Output(240 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* mm aupll div2 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm wifi pll 160m */\n+ return Clock_DSP_Get_WIFI_PLL_Output(160 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* cpu pll 160m */\n+ return Clock_Get_CPU_PLL_Output(160 * 1000 * 1000);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* wifi pll 160m */\n+ return Clock_Get_WIFI_PLL_Output(160 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* top cpu pll 160m */\n+ return Clock_Get_CPU_PLL_Output(160 * 1000 * 1000);\n+ } else if (sel == 2) {\n+ /* top aupll div2 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);\n+ } else if (sel == 3) {\n+ /* aupll div2p5 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2P5);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* wifi pll 80m */\n+ return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* top cpu pll 80m */\n+ return Clock_Get_CPU_PLL_Output(80 * 1000 * 1000);\n+ } else if (sel == 2) {\n+ /* aupll div5 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);\n+ } else if (sel == 3) {\n+ /* aupll div6 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* cpu pll 400m */\n+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* aupll div1 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);\n+ } else if (sel == 2) {\n+ /* wifi pll 240m */\n+ return Clock_Get_WIFI_PLL_Output(240 * 1000 * 1000);\n+ } else if (sel == 3) {\n+ /* wifi pll 320m */\n+ return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);\n+\n+ return (tmpVal & 0x1);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);\n+\n+ return ((tmpVal >> 1) & 0x1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)\n+{\n+ uint32_t tmpVal;\n+\n+ if (sel == 0) {\n+ /* xclk */\n+ return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());\n+ } else if (sel == 1) {\n+ /* pll */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);\n+ sel = BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL);\n+ return Clock_MCU_Clk_Mux_Output(sel);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* rc32m */\n+ return (32 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* xtal */\n+ return Clock_Xtal_Output();\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm mux 240m */\n+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());\n+ } else if (sel == 1) {\n+ /* mm mux 320m */\n+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());\n+ } else if (sel == 2 || sel == 3) {\n+ /* cpu pll 400m */\n+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel)\n+{\n+ uint32_t tmpVal;\n+\n+ if (sel == 0) {\n+ /* xclk */\n+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());\n+ } else if (sel == 1) {\n+ /* pll */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ sel = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL);\n+ return Clock_DSP_Clk_Mux_Output(sel);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0 || sel == 1) {\n+ /* mm xclk */\n+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());\n+ } else if (sel == 2) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 3) {\n+ /* mm mux 240m */\n+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get System Clock\n+ *\n+ * @param type: System clock type\n+ *\n+ * @return System clock value\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type)\n+{\n+ uint32_t clock = 0;\n+ uint32_t div = 0;\n+\n+ switch (type) {\n+ case BL_SYSTEM_CLOCK_MCU_XCLK:\n+ /*!< mcu xclk clock */\n+ return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());\n+ case BL_SYSTEM_CLOCK_MCU_ROOT_CLK:\n+ /*!< mcu root clock */\n+ return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());\n+\n+ case BL_SYSTEM_CLOCK_MCU_CLK:\n+ /*!< mcu fast clock/cpu clock */\n+ clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());\n+ div = Clock_Get_MCU_HClk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_MCU_BCLK:\n+ ATTR_FALLTHROUGH();\n+\n+ case BL_SYSTEM_CLOCK_MCU_PBCLK:\n+ /*!< mcu peri bus clock */\n+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+ div = Clock_Get_Peri_BClk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_DSP_XCLK:\n+ /*!< dsp xclk clock */\n+ return Clock_DSP_XClk_Mux_Output(Clock_Get_DSP_XClk_Sel_Val());\n+\n+ case BL_SYSTEM_CLOCK_DSP_ROOT_CLK:\n+ /*!< dsp root clock */\n+ return Clock_DSP_Root_Clk_Mux_Output(Clock_Get_DSP_Root_Clk_Sel_Val());\n+\n+ case BL_SYSTEM_CLOCK_DSP_CLK:\n+ /*!< dsp fast clock/cpu clock */\n+ clock = Clock_DSP_Root_Clk_Mux_Output(Clock_Get_DSP_Root_Clk_Sel_Val());\n+ div = Clock_Get_DSP_HClk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_DSP_BCLK:\n+ /*!< dsp bus clock */\n+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+ div = Clock_Get_DSP_BClk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_DSP_PBCLK:\n+ /*!< DSP mm bus clock */\n+ clock = Clock_DSP_MM_BCLK_Mux_Output(Clock_Get_DSP_MM_Bclk_Sel_Val());\n+ div = Clock_Get_MM_BClk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_LP_CLK:\n+ /*!< lp clock */\n+ clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ div = Clock_Get_LP_Clk_Div_Val();\n+ return clock / (div + 1);\n+\n+ case BL_SYSTEM_CLOCK_F32K:\n+ /*!< f32k clock */\n+ return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());\n+\n+ case BL_SYSTEM_CLOCK_XTAL:\n+ /*!< xtal clock */\n+ return Clock_Xtal_Output();\n+\n+ default:\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mcu pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ } else if (sel == 1 || sel == 5) {\n+ /* emi aupll div1 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);\n+ } else if (sel == 2 || sel == 6) {\n+ /* emi wifi pll 320m */\n+ return Clock_EMI_Get_WIFI_PLL_Output(320 * 1000 * 1000);\n+ } else if (sel == 3 || sel == 7) {\n+ /* emi cpu pll 400m */\n+ return Clock_EMI_Get_CPU_PLL_Output(400 * 1000 * 1000);\n+ } else if (sel == 4) {\n+ /* emi cpu pll 200m */\n+ return Clock_EMI_Get_CPU_PLL_Output(200 * 1000 * 1000);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_EMI_Clk_Div_Val();\n+\n+ return Clock_EMI_Clk_Mux_Output(Clock_Get_EMI_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* emi cpu pll 400m */\n+ return Clock_EMI_Get_CPU_PLL_Output(400 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* emi wifi pll 320m */\n+ return Clock_EMI_Get_WIFI_PLL_Output(320 * 1000 * 1000);\n+ } else if (sel == 2 || sel == 3) {\n+ /* mm aupll div1 clk */\n+ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_PSRAMB_Clk_Div_Val();\n+\n+ return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP2_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 1) {\n+ /* mm mux 240m */\n+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());\n+ } else if (sel == 2) {\n+ /* cpu pll 400m */\n+ return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);\n+ } else if (sel == 3) {\n+ /* mm xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);;\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_DSP2_Clk_Div_Val();\n+\n+ return Clock_DSP2_Clk_Mux_Output(Clock_Get_DSP2_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_H264_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 1) {\n+ /* mm mux 240m */\n+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());\n+ } else if (sel == 2 || sel == 3) {\n+ /* mm mux 320m */\n+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_H264_Clk_Div_Val();\n+\n+ return Clock_H264_Clk_Mux_Output(Clock_Get_H264_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_BLAI_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 1) {\n+ /* mm mux 240m */\n+ return Clock_DSP_240M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_240M_Sel_Val());\n+ } else if (sel == 2 || sel == 3) {\n+ /* mm mux 320m */\n+ return Clock_DSP_320M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_320M_Sel_Val());\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_BLAI_Clk_Div_Val();\n+\n+ return Clock_BLAI_Clk_Mux_Output(Clock_Get_BLAI_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MIPI_Clk_Mux_Output(void)\n+{ \n+ return Clock_Get_MIPI_PLL_Output();\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Display_Clk_Mux_Output(uint8_t sel)\n+{\n+ uint32_t div = 0;\n+\n+ if (sel == 0) {\n+ /* displ pll clk */\n+ div = Clock_Get_MIPI_Div_Val();\n+ return Clock_MIPI_Clk_Mux_Output() / div;\n+ } else if (sel == 1) {\n+ /* mm xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk(void)\n+{\n+ uint32_t div = 0;\n+\n+ div = Clock_Get_Display_Clk_Div_Val();\n+\n+ return Clock_Display_Clk_Mux_Output(Clock_Get_Display_Clk_Sel_Val()) / (div + 1);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mcu pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ } else if (sel == 1) {\n+ /* mux 160Mkz */\n+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());\n+ } else {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+\n+ return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL));\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_UART_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);\n+ } else if (sel == 1) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 2 || sel == 3) {\n+ /* mm xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART0_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART1_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mcu pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ } else if (sel == 1) {\n+ /* mux 160m */\n+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void)\n+{\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* wifi pll 120m */\n+ return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* xtal */\n+ return Clock_Xtal_Output();\n+ } else if (sel == 2) {\n+ /* wifi pll 120m */\n+ return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);\n+ } else {\n+ /* cpu pll 100m */\n+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* sf sel2 */\n+ return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());\n+ } else if (sel == 1) {\n+ /* mux 80m */\n+ return Clock_80M_Clk_Mux_Output(Clock_Get_Muxpll_80M_Sel_Val());\n+ } else if (sel == 2) {\n+ /* mcu pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ } else {\n+ /* wifi 96m */\n+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mux 160Mkz */\n+ return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());\n+ } else {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm mux 160m */\n+ return Clock_DSP_160M_Clk_Mux_Output(Clock_DSP_Get_Muxpll_160M_Sel_Val());\n+ } else if (sel == 1) {\n+ /* mm xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mcu pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+ } else if (sel == 1) {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* mm pbclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);\n+ } else {\n+ /* mm xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C0_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C1_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+ } else {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel)\n+{\n+ uint32_t div = 0;\n+\n+ if (sel == 1) {\n+ /* f32k bclk */\n+ return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());\n+ } else {\n+ div = Clock_Get_GPADC_Div_Val();\n+ return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);\n+ }\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PDM_Clk_Mux_Output(void)\n+{\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PDM_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_I2S_Clk_Mux_Output(void)\n+{\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_ADC_Clk_Mux_Output(void)\n+{\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* wifi pll 32m */\n+ return Clock_Get_WIFI_PLL_Output(32 * 1000 * 1000);\n+ } else if (sel == 1) {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ } else {\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DAC_Clk_Mux_Output(void)\n+{\n+ /* audio pll clk */\n+ return Clock_Get_Audio_PLL_Output();\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DAC_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* wifi pll 96m */\n+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);\n+ } else {\n+ /* cpu pll 100m */\n+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV);\n+}\n+\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel)\n+{\n+ if (sel == 0) {\n+ /* xclk */\n+ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);\n+ } else if (sel == 1) {\n+ /* wifi pull 960m */\n+ return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);\n+ } else if (sel == 2 || sel == 3) {\n+ /* cpu pll 100m */\n+ return Clock_Get_CPU_PLL_Output(100 * 1000 * 1000);\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);\n+}\n+\n+__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);\n+}\n+\n+/****************************************************************************/ /**\n+\n+ * @brief Get Audio ADC Clock\n+ *\n+ * @return Audio ADC clock value\n+ *\n+*******************************************************************************/\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void)\n+{\n+ uint32_t clock = 0;\n+ uint32_t div = 0;\n+\n+ clock = Clock_ADC_Clk_Mux_Output();\n+ div = Clock_Get_ADC_Div_Val();\n+\n+ return clock / (div + 1);\n+}\n+\n+/****************************************************************************/ /**\n+\n+ * @brief Get Audio DAC Clock\n+ *\n+ * @return Audio DAC clock value\n+ *\n+*******************************************************************************/\n+__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_DAC_Clock_Get(void)\n+{\n+ uint32_t clock = 0;\n+ uint32_t div = 0;\n+\n+ clock = Clock_DAC_Clk_Mux_Output();\n+ div = Clock_Get_DAC_Div_Val();\n+\n+ return clock / (div + 1);\n+}\n+\n+/****************************************************************************/ /**\n+\n+ * @brief Get Peripheral1 Clock\n+ *\n+ * @param type: Peripheral1 clock type\n+ *\n+ * @return Peripheral1 clock value\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)\n+{\n+ uint32_t clock = 0;\n+ uint32_t div = 0;\n+\n+ switch (type) {\n+ /*!< uart0 clock */\n+ case BL_PERIPHERAL_CLOCK_UART0:\n+ ATTR_FALLTHROUGH();\n+\n+ /*!< uart1 clock */\n+ case BL_PERIPHERAL_CLOCK_UART1:\n+ ATTR_FALLTHROUGH();\n+\n+ /*!< uart2 clock */\n+ case BL_PERIPHERAL_CLOCK_UART2:\n+ clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());\n+ div = Clock_Get_UART_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< uart3 clock */\n+ case BL_PERIPHERAL_CLOCK_UART3:\n+ clock = Clock_DSP_UART_Clk_Mux_Output(Clock_Get_DSP_UART_Clk_Sel_Val());\n+ div = Clock_Get_DSP_UART0_Div_Val();\n+ return clock / (div + 1);\n+\n+#ifndef CONFIG_SUPPORT_UART_CLOCK_GET_ONLY\n+ /*!< spi0 clock */\n+ case BL_PERIPHERAL_CLOCK_SPI0:\n+ clock = Clock_SPI_Clk_Mux_Output(Clock_Get_SPI_Clk_Sel_Val());\n+ div = Clock_Get_SPI_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< spi1 clock */\n+ case BL_PERIPHERAL_CLOCK_SPI1:\n+ clock = Clock_DSP_SPI_Clk_Mux_Output(Clock_Get_DSP_SPI_Clk_Sel_Val());\n+ div = Clock_Get_DSP_SPI_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< i2c0 clock */\n+ case BL_PERIPHERAL_CLOCK_I2C0:\n+ ATTR_FALLTHROUGH();\n+\n+ /*!< i2c1 clock */\n+ case BL_PERIPHERAL_CLOCK_I2C1:\n+ clock = Clock_I2C_Clk_Mux_Output(Clock_Get_I2C_Clk_Sel_Val());\n+ div = Clock_Get_I2C_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< i2c2 clock */\n+ case BL_PERIPHERAL_CLOCK_I2C2:\n+ clock = Clock_DSP_I2C_Clk_Mux_Output(Clock_Get_DSP_I2C_Clk_Sel_Val());\n+ div = Clock_Get_DSP_I2C0_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< i2c3 clock */\n+ case BL_PERIPHERAL_CLOCK_I2C3:\n+ clock = Clock_DSP_I2C_Clk_Mux_Output(Clock_Get_DSP_I2C_Clk_Sel_Val());\n+ div = Clock_Get_DSP_I2C1_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< PSRAMA clock */\n+ case BL_PERIPHERAL_CLOCK_PSRAMA:\n+ return Clock_Get_UHS_PLL_Output(); \n+\n+ /*!< PSRAMB clock */\n+ case BL_PERIPHERAL_CLOCK_PSRAMB:\n+ return Clock_Get_PSRAMB_Clk();\n+\n+ /*!< FLASH clock */\n+ case BL_PERIPHERAL_CLOCK_FLASH:\n+ clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());\n+ div = Clock_Get_SF_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< I2S clock */\n+ case BL_PERIPHERAL_CLOCK_I2S:\n+ clock = Clock_I2S_Clk_Mux_Output();\n+ div = Clock_Get_I2S_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< BLAI clock */\n+ case BL_PERIPHERAL_CLOCK_BLAI:\n+ return Clock_Get_BLAI_Clk();\n+\n+ /*!< DISPLAY clock */\n+ case BL_PERIPHERAL_CLOCK_DISPLAY:\n+ return Clock_Get_Display_Clk();\n+\n+ /*!< IR clock */\n+ case BL_PERIPHERAL_CLOCK_IR:\n+ clock = Clock_IR_Clk_Mux_Output();\n+ div = Clock_Get_IR_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< PDM clock */\n+ case BL_PERIPHERAL_CLOCK_PDM:\n+ clock = Clock_PDM_Clk_Mux_Output();\n+ div = Clock_Get_PDM_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< ADC clock */\n+ case BL_PERIPHERAL_CLOCK_ADC:\n+ return Clock_Audio_ADC_Clock_Get();\n+\n+ /*!< DAC clock */\n+ case BL_PERIPHERAL_CLOCK_DAC:\n+ return Clock_Audio_DAC_Clock_Get();\n+\n+ /*!< GPADC clock */\n+ case BL_PERIPHERAL_CLOCK_GPADC:\n+ return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());\n+\n+ /*!< GPDAC clock */\n+ case BL_PERIPHERAL_CLOCK_GPDAC:\n+ clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());\n+ div = Clock_Get_GPDAC_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< CAM clock */\n+ case BL_PERIPHERAL_CLOCK_CAM:\n+ clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());\n+ div = Clock_Get_CAM_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< SDH clock */\n+ case BL_PERIPHERAL_CLOCK_SDH:\n+ clock = Clock_SDH_Clk_Mux_Output(Clock_Get_SDH_Clk_Sel_Val());\n+ div = Clock_Get_SDH_Div_Val();\n+ return clock / (div + 1);\n+\n+ /*!< PKA clock */\n+ case BL_PERIPHERAL_CLOCK_PKA:\n+ return Clock_PKA_Clk_Mux_Output(Clock_Get_PKA_Clk_Sel_Val());\n+\n+ /*!< EMI clock */\n+ case BL_PERIPHERAL_CLOCK_EMI:\n+ return Clock_Get_EMI_Clk();\n+\n+ /*!< H264 clock */\n+ case BL_PERIPHERAL_CLOCK_H264:\n+ return Clock_Get_H264_Clk();\n+\n+ /*!< DSP2 clock */\n+ case BL_PERIPHERAL_CLOCK_DSP2:\n+ return Clock_Get_DSP2_Clk();\n+#endif\n+ default:\n+ return 0;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get system core clock\n+ *\n+ * @param None\n+ *\n+ * @return system core clock value\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_CLOCK_SECTION SystemCoreClockGet(void)\n+{\n+ uint32_t clockVal = 0;\n+\n+ switch (GLB_Get_Core_Type()) {\n+ case GLB_CORE_ID_M0:\n+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);\n+ break;\n+ default:\n+ clockVal = 0;\n+ break;\n+ }\n+ clockVal = clockVal ? clockVal : (32 * 1000 * 1000);\n+\n+ return clockVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu rtc reset\n+ *\n+ * @param rstEn: hold reset or not\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_RST(uint8_t rstEn)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t address = 0;\n+\n+ switch (GLB_Get_Core_Type()) {\n+ case GLB_CORE_ID_M0:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ break;\n+ case GLB_CORE_ID_D0:\n+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;\n+ break;\n+ case GLB_CORE_ID_LP:\n+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;\n+ break;\n+ default:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ break;\n+ }\n+\n+ /* set reset */\n+ /* MCU RTC_RST is [30] */\n+ /* DSP RTC_RST is [30] */\n+ /* LP RTC_RST is [30] */\n+ tmpVal = BL_RD_WORD(address);\n+ if (rstEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ }\n+ BL_WR_WORD(address, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu rtc reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION CPU_Reset_MTimer(void)\n+{\n+ CPU_Set_MTimer_RST(1);\n+ CPU_Set_MTimer_RST(0);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set mcu rtc clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_CLK(uint8_t enable, uint16_t div)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t address = 0;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ switch (GLB_Get_Core_Type()) {\n+ case GLB_CORE_ID_M0:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ break;\n+ case GLB_CORE_ID_D0:\n+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;\n+ break;\n+ case GLB_CORE_ID_LP:\n+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;\n+ break;\n+ default:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ break;\n+ }\n+\n+ /* disable rtc first */\n+ /* MCU RTC_EN is [31] */\n+ /* DSP RTC_EN is [31] */\n+ /* LP RTC_EN is [31] */\n+ tmpVal = BL_RD_WORD(address);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ BL_WR_WORD(address, tmpVal);\n+\n+ /* set div */\n+ /* MCU RTC_DIV is [9:0] */\n+ /* DSP RTC_DIV is [9:0] */\n+ /* LP RTC_DIV is [9:0] */\n+ tmpVal = BL_RD_WORD(address);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);\n+ BL_WR_WORD(address, tmpVal);\n+\n+ /* enable or not */\n+ /* MCU RTC_EN is [31] */\n+ /* DSP RTC_EN is [31] */\n+ /* LP RTC_EN is [31] */\n+ tmpVal = BL_RD_WORD(address);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ }\n+ BL_WR_WORD(address, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get cpu rtc source clock\n+ *\n+ * @param None\n+ *\n+ * @return cpu rtc source clock\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Source_Clock(void)\n+{\n+ uint32_t coreFreq = 0;\n+\n+ /* get cpu core clock */\n+ switch (GLB_Get_Core_Type()) {\n+ case GLB_CORE_ID_M0:\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);\n+ break;\n+ default:\n+ coreFreq = 0;\n+ break;\n+ }\n+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);\n+\n+ return coreFreq;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu rtc clock\n+ *\n+ * @param None\n+ *\n+ * @return mcu rtc counter clock\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Clock(void)\n+{\n+ uint32_t coreFreq = 0;\n+ uint32_t address = 0;\n+ uint32_t div = 0;\n+\n+ /* get cpu core clock */\n+ /* get mtimer clock div */\n+ switch (GLB_Get_Core_Type()) {\n+ case GLB_CORE_ID_M0:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET;\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET;\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);\n+ break;\n+ default:\n+ address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;\n+ coreFreq = 0;\n+ break;\n+ }\n+ /* MCU RTC_DIV is [9:0] */\n+ /* DSP RTC_DIV is [9:0] */\n+ /* LP RTC_DIV is [9:0] */\n+ div = BL_GET_REG_BITS_VAL(BL_RD_WORD(address), MCU_MISC_REG_MCU_RTC_DIV);\n+ div += 1;\n+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);\n+ coreFreq = coreFreq / div; /* mtimer clock = cpu clock / mtimer div */\n+\n+ return coreFreq;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu rtc counter\n+ *\n+ * @param None\n+ *\n+ * @return mcu rtc counter\n+ *\n+*******************************************************************************/\n+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Counter(void)\n+{\n+#if (__riscv_xlen == 64)\n+ return (uint64_t)csi_coret_get_value();\n+#else\n+ volatile uint32_t tmpValLow, tmpValHigh, tmpValHigh1;\n+ uint32_t cnt = 0;\n+\n+ do {\n+ tmpValHigh = csi_coret_get_valueh();\n+ tmpValLow = csi_coret_get_value();\n+ tmpValHigh1 = csi_coret_get_valueh();\n+ cnt++;\n+ if (cnt > 5000) {\n+ break;\n+ }\n+ } while (tmpValHigh != tmpValHigh1);\n+\n+ return (uint64_t)(((uint64_t)tmpValHigh << 32) + tmpValLow);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu cycle\n+ *\n+ * @param None\n+ *\n+ * @return mcu cycle\n+ *\n+*******************************************************************************/\n+uint64_t ATTR_CLOCK_SECTION CPU_Get_CPU_Cycle(void)\n+{\n+#if (__riscv_xlen == 64)\n+ return (uint64_t)__get_MCYCLE();\n+#else\n+ volatile uint32_t tmpValLow, tmpValHigh, tmpValHigh1;\n+ uint32_t cnt = 0;\n+\n+ do {\n+ tmpValHigh = __get_MCYCLEH();\n+ tmpValLow = __get_MCYCLE();\n+ tmpValHigh1 = __get_MCYCLEH();\n+ cnt++;\n+ if (cnt > 5000) {\n+ break;\n+ }\n+ } while (tmpValHigh != tmpValHigh1);\n+\n+ return (uint64_t)(((uint64_t)tmpValHigh << 32) + tmpValLow);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu rtc counter in us\n+ *\n+ * @param None\n+ *\n+ * @return mcu rtc counter in us\n+ *\n+*******************************************************************************/\n+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_US(void)\n+{\n+ uint32_t clk = SystemCoreClockGet();\n+ uint64_t mtimer_counter = CPU_Get_MTimer_Counter();\n+\n+ if (mtimer_counter < 10) {\n+ mtimer_counter = CPU_Get_CPU_Cycle();\n+ return (uint32_t)mtimer_counter/(clk/1000000);\n+ }\n+\n+ if(clk>1000*1000){\n+ /* system_clock > 1MHz ==> mtimer_clock is 1MHz */\n+ /* return mtimer_count after mtimer_init_1MHz */\n+ return CPU_Get_MTimer_Counter();\n+ }else{\n+ /* system_clock < 1MHz ==> mtimer_clock is 1KHz */\n+ /* return mtimer_count*1000 after mtimer_init_1KHz */\n+ return CPU_Get_MTimer_Counter()*1000;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu rtc counter in ms\n+ *\n+ * @param None\n+ *\n+ * @return mcu rtc counter in ms\n+ *\n+*******************************************************************************/\n+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_MS(void)\n+{\n+ uint32_t clk = SystemCoreClockGet();\n+ uint64_t mtimer_counter = CPU_Get_MTimer_Counter();\n+\n+ if (mtimer_counter < 10) {\n+ mtimer_counter = CPU_Get_CPU_Cycle();\n+ return (uint32_t)mtimer_counter/(clk/1000);\n+ }\n+\n+ if(clk>1000*1000){\n+ /* system_clock > 1MHz ==> mtimer_clock is 1MHz */\n+ /* return mtimer_count/1000 after mtimer_init_1MHz */\n+ mtimer_counter = CPU_Get_MTimer_Counter();\n+#ifndef CONFIG_SUPPORT_U32_DIV_ONLY\n+ return mtimer_counter/1000;\n+#else\n+ if(mtimer_counter<(1<<30)){\n+ return (uint32_t)mtimer_counter/1000;\n+ }else{\n+ //return CPU_Get_MTimer_Counter()/1000;\n+ return (mtimer_counter>>10)+(mtimer_counter>>15)-(mtimer_counter>>17)+(mtimer_counter>>21);\n+ }\n+#endif\n+ }else{\n+ /* system_clock < 1MHz ==> mtimer_clock is 1KHz */\n+ /* return mtimer_count after mtimer_init_1KHz */\n+ return CPU_Get_MTimer_Counter();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu timer delay us\n+ *\n+ * @param cnt: us\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_US(uint32_t cnt)\n+{\n+ volatile uint64_t us1 = 0;\n+ volatile uint64_t us2 = 0;\n+\n+ us1 = CPU_Get_MTimer_US();\n+ do {\n+ us2 = CPU_Get_MTimer_US();\n+ } while (((us2 - us1) < (uint64_t)(cnt)));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu timer delay ms\n+ *\n+ * @param cnt: ms\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_MS(uint32_t cnt)\n+{\n+ volatile uint64_t ms1 = 0;\n+ volatile uint64_t ms2 = 0;\n+\n+ ms1 = CPU_Get_MTimer_MS();\n+ do {\n+ ms2 = CPU_Get_MTimer_MS();\n+ } while (((ms2 - ms1) < (uint64_t)(cnt)));\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group CLOCK_Public_Functions */\n+\n+/*@} end of group CLOCK */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..995a7b80a75395ebcbe7fc4f9540cc9a764f3f82\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c\n@@ -0,0 +1,406 @@\n+#include \"bl808_common.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_clock.h\"\n+\n+/** @addtogroup BL808_Periph_Driver\n+ * @{\n+ */\n+\n+/** @defgroup DRIVER_COMMON DRIVER_COMMON\n+ * @brief Digger driver common functions\n+ * @{\n+ */\n+\n+/** @defgroup DRIVER_Private_Type\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Private_Type*/\n+\n+/** @defgroup DRIVER_Private_Defines\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Private_Defines */\n+\n+/** @defgroup DRIVER_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Private_Variables */\n+\n+/** @defgroup DRIVER_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Global_Variables */\n+\n+/** @defgroup DRIVER_Private_FunctionDeclaration\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Private_FunctionDeclaration */\n+\n+/** @defgroup DRIVER_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DRIVER_Private_Functions */\n+\n+/** @defgroup DRIVER_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief delay us\n+ *\n+ * @param[in] core: systemcoreclock\n+ *\n+ * @param[in] cnt: delay cnt us\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+#ifdef ARCH_RISCV\n+__WEAK\n+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)\n+{\n+ volatile uint32_t divVal = loopT;\n+ volatile uint32_t speed = 0;\n+ volatile uint32_t cycNum = 0;\n+\n+ /* 1M=100K*10, so multiple is 10 */\n+ /* loop function take 4 instructions, so instructionNum is 4 */\n+ /* divVal = multiple*instructionNum */\n+\n+ if (core >= 1 * 1000 * 1000) {\n+ /* CPU clock >= 1MHz */\n+ speed = core / (100 * 1000);\n+ cycNum = speed * cnt;\n+ cycNum = cycNum / 10;\n+ cycNum = cycNum / divVal;\n+ /* cycNum >= 0 */\n+ } else {\n+ /* CPU clock < 1MHz */\n+ speed = core / 1000;\n+ cycNum = speed * cnt;\n+ cycNum = cycNum / 1000;\n+ cycNum = cycNum / divVal;\n+ /* cycNum >= 0 */\n+ }\n+\n+ if (!cycNum) {\n+ return;\n+ }\n+\n+ __asm__ __volatile__(\n+ \"mv a4,%0\\n\\t\"\n+ \"li a5,0x0\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \".align 4\\n\\t\"\n+ \"1 :\\n\"\n+ \"beq a5,a4,2f\\n\\t\"\n+ \"addi a5,a5,0x1\\n\\t\"\n+ \"lui a3,0xF0000\\n\\t\"\n+ \"lw a3,0(a3)\\n\\t\"\n+ \"j 1b\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"2 :\\n\\t\"\n+ \"nop\\n\"\n+ : /* output */\n+ : \"r\"(cycNum) /* input */\n+ : \"a3\", \"a4\", \"a5\" /* destruct description */\n+ );\n+}\n+#endif\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief delay us\n+ *\n+ * @param[in] cnt: delay cnt us\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc00[] = {46,46,66,69};\n+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc10[] = {10,10,66,69};\n+const uint32_t ATTR_TCM_CONST_SECTION m0Cyc11[] = {10,10,66,69};\n+const uint32_t ATTR_TCM_CONST_SECTION d0Cyc00[] = { 5, 5,62,34};\n+const uint32_t ATTR_TCM_CONST_SECTION d0Cyc11[] = { 5, 5,13,13};\n+const uint32_t ATTR_TCM_CONST_SECTION lpCyc00[] = { 6, 6,55,85};\n+__WEAK\n+void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)\n+{\n+ GLB_CORE_ID_Type coreID;\n+ uint32_t coreFreq;\n+ uint32_t loopTick = 5;\n+ const uint32_t *pCyc = NULL;\n+ uint32_t iCacheEn = 1;\n+ uint32_t dCacheEn = 1;\n+\n+ /* requirement: icache enable && dcache enable */\n+ /* otherwise the latency depends on the code address */\n+\n+ coreID = GLB_Get_Core_Type();\n+\n+ if(GLB_CORE_ID_M0 == coreID){\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+#ifdef __RV32\n+ iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos;\n+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;\n+#endif\n+ if(iCacheEn && dCacheEn){\n+ pCyc = m0Cyc11;\n+ }else if(iCacheEn && !dCacheEn){\n+ pCyc = m0Cyc10;\n+ }else if(!iCacheEn && !dCacheEn){\n+ pCyc = m0Cyc00;\n+ }else{\n+ pCyc = m0Cyc11;\n+ }\n+ }else if(GLB_CORE_ID_D0 == coreID){\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+#ifdef __RV64\n+ iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos;\n+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;\n+#endif\n+ if(iCacheEn && dCacheEn){\n+ pCyc = d0Cyc11;\n+ }else if(!iCacheEn && !dCacheEn){\n+ pCyc = d0Cyc00;\n+ }else{\n+ pCyc = d0Cyc11;\n+ }\n+ }else if(GLB_CORE_ID_LP == coreID){\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);\n+ pCyc = lpCyc00;\n+ }else{\n+ coreFreq = 32 * 1000 * 1000;\n+ pCyc = lpCyc00;\n+ }\n+\n+ switch(((uint32_t)(uintptr_t)&ASM_Delay_Us)>>24){\n+ case 0x22:\n+ loopTick = pCyc[0];\n+ break;\n+ case 0x62:\n+ loopTick = pCyc[0];\n+ break;\n+ case 0x3F:\n+ loopTick = pCyc[2];\n+ break;\n+ case 0x3E:\n+ loopTick = pCyc[3];\n+ break;\n+ default :\n+ break;\n+ }\n+\n+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);\n+\n+ ASM_Delay_Us(coreFreq, cnt, loopTick);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief delay ms\n+ *\n+ * @param[in] cnt: delay cnt ms\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)\n+{\n+ uint32_t i = 0;\n+ uint32_t count = 0;\n+\n+ if (cnt >= 1024) {\n+ /* delay (n*1024) ms */\n+ for (i = 0; i < (cnt / 1024); i++) {\n+ arch_delay_us(1024 * 1000);\n+ }\n+ }\n+\n+ count = cnt & 0x3FF;\n+\n+ if (count) {\n+ /* delay (1-1023)ms */\n+ arch_delay_us(count * 1000);\n+ }\n+}\n+#endif\n+\n+#ifdef DEBUG\n+/*******************************************************************************\n+* @brief Reports the name of the source file and the source line number\n+* where the CHECK_PARAM error has occurred.\n+\n+* @param file: Pointer to the source file name\n+* @param line: assert_param error line source number\n+\n+* @return None\n+*******************************************************************************/\n+void ATTR_TCM_SECTION check_failed(uint8_t *file, uint32_t line)\n+{\n+ /* Infinite loop */\n+ while (1)\n+ ;\n+}\n+#endif /* DEBUG */\n+\n+/****************************************************************************/ /**\n+ * @brief MM_Sys All interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+ *******************************************************************************/\n+#if defined(CPU_M0) || defined(CPU_LP)\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AWB2_IRQHandler(void);\n+void UART4_IRQHandler(void);\n+void UART3_IRQHandler(void);\n+void I2C2_IRQHandler(void);\n+void I2C3_IRQHandler(void);\n+void SPI1_IRQHandler(void);\n+void AE_IRQHandler(void);\n+void AWB0_IRQHandler(void);\n+void SEOF0_IRQHandler(void);\n+void SEOF1_IRQHandler(void);\n+void SEOF2_IRQHandler(void);\n+void CAM0_IRQHandler(void);\n+void CAM1_IRQHandler(void);\n+void CAM2_IRQHandler(void);\n+void CAM3_IRQHandler(void);\n+void MJPEG_IRQHandler(void);\n+void DMA2_INT0_IRQHandler(void);\n+void DMA2_INT1_IRQHandler(void);\n+void DMA2_INT2_IRQHandler(void);\n+void DMA2_INT3_IRQHandler(void);\n+void DMA2_INT4_IRQHandler(void);\n+void DMA2_INT5_IRQHandler(void);\n+void DMA2_INT6_IRQHandler(void);\n+void DMA2_INT7_IRQHandler(void);\n+void IPC_D0_IRQHandler(void);\n+void MJDEC_IRQHandler(void);\n+void CAM4_IRQHandler(void);\n+void CAM5_IRQHandler(void);\n+void CAM6_IRQHandler(void);\n+void CAM7_IRQHandler(void);\n+void DMA2D_INT0_IRQHandler(void);\n+void DMA2D_INT1_IRQHandler(void);\n+void Display_IRQHandler(void);\n+void PWM_IRQHandler(void);\n+void SEOF3_IRQHandler(void);\n+void DBI_IRQHandler(void);\n+void WDR_IRQHandler(void);\n+void OSD_PB_IRQHandler(void);\n+void AWB1_IRQHandler(void);\n+void DSI_IRQHandler(void);\n+void AE_HIST_IRQHandler(void);\n+void TIMER1_CH0_IRQHandler(void);\n+void TIMER1_CH1_IRQHandler(void);\n+void TIMER1_WDT_IRQHandler(void);\n+void AUDIO_IRQHandler(void);\n+\n+\n+\n+void C906_ALL_IRQHandler(void)\n+{\n+ AWB2_IRQHandler();\n+ UART4_IRQHandler();\n+ UART3_IRQHandler();\n+ I2C2_IRQHandler();\n+ I2C3_IRQHandler();\n+ SPI1_IRQHandler();\n+ AE_IRQHandler();\n+ AWB0_IRQHandler();\n+ SEOF0_IRQHandler();\n+ SEOF1_IRQHandler();\n+ SEOF2_IRQHandler();\n+ CAM0_IRQHandler();\n+ CAM1_IRQHandler();\n+ CAM2_IRQHandler();\n+ CAM3_IRQHandler();\n+ MJPEG_IRQHandler();\n+ DMA2_INT0_IRQHandler();\n+ DMA2_INT1_IRQHandler();\n+ DMA2_INT2_IRQHandler();\n+ DMA2_INT3_IRQHandler();\n+ DMA2_INT4_IRQHandler();\n+ DMA2_INT5_IRQHandler();\n+ DMA2_INT6_IRQHandler();\n+ DMA2_INT7_IRQHandler();\n+ IPC_D0_IRQHandler();\n+ MJDEC_IRQHandler();\n+ CAM4_IRQHandler();\n+ CAM5_IRQHandler();\n+ CAM6_IRQHandler();\n+ CAM7_IRQHandler();\n+ DMA2D_INT0_IRQHandler();\n+ DMA2D_INT1_IRQHandler();\n+ Display_IRQHandler();\n+ PWM_IRQHandler();\n+ SEOF3_IRQHandler();\n+ DBI_IRQHandler();\n+ WDR_IRQHandler();\n+ OSD_PB_IRQHandler();\n+ AWB1_IRQHandler();\n+ DSI_IRQHandler();\n+ AE_HIST_IRQHandler();\n+ TIMER1_CH0_IRQHandler();\n+ TIMER1_CH1_IRQHandler();\n+ TIMER1_WDT_IRQHandler();\n+ AUDIO_IRQHandler();\n+}\n+#endif\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable MM_Sys All interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+ *******************************************************************************/\n+#if defined(CPU_M0) || defined(CPU_LP)\n+void C906_All_Int_Enable(void)\n+{\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(MM_ALL_IRQn, C906_ALL_IRQHandler);\n+#endif\n+ CPU_Interrupt_Enable(MM_ALL_IRQn);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Dsiable MM_Sys All interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+ *******************************************************************************/\n+#if defined(CPU_M0) || defined(CPU_LP)\n+void C906_All_Int_Disable(void)\n+{\n+ CPU_Interrupt_Disable(MM_ALL_IRQn);\n+}\n+#endif\n+\n+/*@} end of group DRIVER_Public_Functions */\n+\n+/*@} end of group DRIVER_COMMON */\n+\n+/*@} end of group BL808_Periph_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dac.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dac.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5fa2950dec7ce2e93ac56c2a3a6a9e78d866bfd5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dac.c\n@@ -0,0 +1,518 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dac.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dac.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DAC\n+ * @{\n+ */\n+\n+/** @defgroup DAC_Private_Macros\n+ * @{\n+ */\n+#define GPIP_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+\n+/*@} end of group DAC_Private_Macros */\n+\n+/** @defgroup DAC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DAC_Private_Types */\n+\n+/** @defgroup DAC_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DAC_Private_Variables */\n+\n+/** @defgroup DAC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DAC_Global_Variables */\n+\n+/** @defgroup DAC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DAC_Private_Fun_Declaration */\n+\n+/** @defgroup DAC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DAC_Private_Functions */\n+\n+/** @defgroup DAC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DAC initialization\n+ *\n+ * @param cfg: DAC configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));\n+\n+ /* Set DAC config */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);\n+\n+ if (ENABLE == cfg->resetChanA) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ }\n+\n+ if (ENABLE == cfg->resetChanB) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ }\n+\n+ /* Clear reset */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DAC channel A initialization\n+ *\n+ * @param cfg: DAC channel configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));\n+\n+ /* Set channel A config */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn);\n+\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DAC channel B initialization\n+ *\n+ * @param cfg: DAC channel configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));\n+\n+ /* Set channel A config */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn);\n+\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DAC channel B source\n+ *\n+ * @param src: DAC channel B source selection type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src));\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DAC channel A source\n+ *\n+ * @param src: DAC channel A source selection type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src));\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable DAC channel B\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_DAC_ChanB_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable DAC channel B\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_DAC_ChanB_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable DAC channel A\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_DAC_ChanA_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable DAC channel A\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_DAC_ChanA_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DAC DMA TX format\n+ *\n+ * @param fmt: DAC DMA TX format selection type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt));\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable DAC DMA TX\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_Set_DAC_DMA_TX_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable DAC DMA TX\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_Set_DAC_DMA_TX_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable DAC DMA TX\n+ *\n+ * @param data: The data to be send\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GPIP_DAC_DMA_WriteData(uint32_t data)\n+{\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AON and GPIP DAC config\n+ *\n+ * @param cfg: AON and GPIP DAC configuration\n+ *\n+ * @return config success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));\n+ CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div));\n+ CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt));\n+\n+ /* AON Set DAC config */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);\n+\n+ if (ENABLE == cfg->resetChanA) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ }\n+\n+ if (ENABLE == cfg->resetChanB) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ }\n+\n+ /* AON Clear reset */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal);\n+\n+ /* GPIP Set DAC config */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+\n+ /* GPIP Set DMA config */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AON and GPIP DAC channel A config\n+ *\n+ * @param cfg: AON and GPIP DAC channel A configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src));\n+\n+ /* GPIP select source */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+\n+ /* GPIP enable or disable channel */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+\n+ /* AON enable or disable channel */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AON and GPIP DAC channel B config\n+ *\n+ * @param cfg: AON and GPIP DAC channel B configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src));\n+\n+ /* GPIP select source */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+\n+ /* GPIP enable or disable channel */\n+ tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn);\n+ BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);\n+\n+ /* AON enable or disable channel */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DAC channel A set value\n+ *\n+ * @param val: DAC value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_DAC_Set_ChanA_Value(uint16_t val)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DAC channel B set value\n+ *\n+ * @param val: DAC value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void GLB_DAC_Set_ChanB_Value(uint16_t val)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val);\n+ tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal);\n+}\n+\n+/*@} end of group DAC_Public_Functions */\n+\n+/*@} end of group DAC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bde60e85a73917ce76ca836195f4c9333d094d5d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c\n@@ -0,0 +1,802 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dbi.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dbi.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DBI\n+ * @{\n+ */\n+\n+/** @defgroup DBI_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group DBI_Private_Macros */\n+\n+/** @defgroup DBI_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DBI_Private_Types */\n+\n+/** @defgroup DBI_Private_Variables\n+ * @{\n+ */\n+\n+/**\n+ * @brief DBI interrupt callback function address array\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *DBIIntCbfArra[DBI_INT_ALL] = {\n+ NULL\n+};\n+#endif\n+\n+/*@} end of group DBI_Private_Variables */\n+\n+/** @defgroup DBI_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DBI_Global_Variables */\n+\n+/** @defgroup DBI_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DBI_Private_Fun_Declaration */\n+\n+/** @defgroup DBI_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DBI_Private_Functions */\n+\n+/** @defgroup DBI_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DBI interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DBI_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS);\n+\n+ /* DBI transfer end interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, DBI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_END_MASK)) {\n+ BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR));\n+\n+ if (DBIIntCbfArra[DBI_INT_END] != NULL) {\n+ DBIIntCbfArra[DBI_INT_END]();\n+ }\n+ }\n+\n+ /* DBI tx fifo ready interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, DBI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_TXF_MASK)) {\n+ if (DBIIntCbfArra[DBI_INT_TX_FIFO_REQ] != NULL) {\n+ DBIIntCbfArra[DBI_INT_TX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* DBI tx fifo ready interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, DBI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_FER_MASK)) {\n+ if (DBIIntCbfArra[DBI_INT_FIFO_ERR] != NULL) {\n+ DBIIntCbfArra[DBI_INT_FIFO_ERR]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief DBI init\n+ *\n+ * @param dbiCfg: DBI configuration\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DBI_Init(DBI_CFG_Type *dbiCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DBI_MODE_TYPE(dbiCfg->mode));\n+ CHECK_PARAM(IS_DBI_PIXEL_FORMAT_TYPE(dbiCfg->pixelFormat));\n+ CHECK_PARAM(IS_DBI_FIFO_FORMAT_TYPE(dbiCfg->fifoFormat));\n+ CHECK_PARAM(IS_DBI_SCL_CLK_PHASE_TYPE(dbiCfg->clkPhase));\n+ CHECK_PARAM(IS_DBI_SCL_CLK_POLARITY_TYPE(dbiCfg->clkPolarity));\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+\n+ /* Select DBI type B or C */\n+ if (dbiCfg->mode == DBI_TYPE_B) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_SEL);\n+ } else if (dbiCfg->mode == DBI_TYPE_C_3_WIRE) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CONT_EN, dbiCfg->continueEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_EN, dbiCfg->dummyEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_CNT, dbiCfg->dummyCnt);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_PH, dbiCfg->clkPhase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_POL, dbiCfg->clkPolarity);\n+\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+\n+ /* Set data period */\n+ DBI_SetPeriod(&(dbiCfg->period));\n+\n+ /* Set pixel format */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_PIX_CNT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PIX_FORMAT, dbiCfg->pixelFormat);\n+ BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal);\n+\n+ /* Set fifo format */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_FIFO_FORMAT, dbiCfg->fifoFormat);\n+ BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(DBI_IRQn, DBI_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI command and data configuration\n+ *\n+ * @param cdCfg: Pointer of DBI CD configure type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_CDConfig(DBI_CD_CFG_Type *cdCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DBI_DATA_TYPE(cdCfg->dataType));\n+ CHECK_PARAM(IS_DBI_DATA_DIRECTION_TYPE(cdCfg->dataDir));\n+\n+ /* Set command and data comfiguration */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, cdCfg->commandEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, cdCfg->command);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, cdCfg->dataEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, cdCfg->dataType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, cdCfg->dataDir);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, cdCfg->dataCnt);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+ BL_WR_REG(DBI_BASE, DBI_WDATA, cdCfg->data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI enable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI disable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI enable\n+ *\n+ * @param period: DBI period configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetPeriod(DBI_Period_CFG_Type *period)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Set data period */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_PRD);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_S, period->startLen);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_0, period->dataPhase0Len);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_1, period->dataPhase1Len);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_I, period->intervalLen);\n+\n+ BL_WR_REG(DBI_BASE, DBI_PRD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI set Command\n+ *\n+ * @param Command: start Command (frist byte)\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetCommand(uint8_t Command )\n+{\n+ uint32_t tmpVal;\n+\n+ /* Set command */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, Command);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI set Command and Data enable signal\n+ *\n+ * @param CommandEn: DISABLE:No command phase, ENABLE:Command will be sent\n+ * @param dataEn: DISABLE:No data phase, ENABLE:data will be sent\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetPhaseState(BL_Fun_Type commandEn, BL_Fun_Type dataEn)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Set command */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, commandEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, dataEn);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI set Data type and count, Automatically change data phase settings\n+ *\n+ * @param datatype: Data type select\n+ * @param dataCount: count of data (Not the size of the data)\n+ * normal data: max 4\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetDataTypeAndCount(DBI_Data_Type dataType, uint32_t dataCount)\n+{\n+ uint32_t tmpVal, tmpVal2;\n+\n+ /* Set dbi config */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ /* Set data type */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, dataType);\n+\n+ if(!dataCount){\n+ /* No data phase */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN);\n+ }else{\n+ /* data will be sent */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN);\n+\n+ if(dataType == DBI_DATA_NORMAL){\n+ if(dataCount > 4){\n+ dataCount = 4;\n+ }\n+ /* data byte count of normal-data */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, dataCount-1);\n+ }else{\n+ /* pixel count of pixel-data */\n+ tmpVal2 = BL_RD_REG(DBI_BASE, DBI_PIX_CNT);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, DBI_CR_DBI_PIX_CNT, dataCount-1);\n+ BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal2);\n+ }\n+ }\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI set normal data direction (It only works in normal data)\n+ *\n+ * @param dataDir: write or read\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetNormalDataDir(DBI_Data_Direction_Type dataDir)\n+{\n+ uint32_t tmpVal;\n+ /* Set dbi config */\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG);\n+ /* set normal data direction */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, dataDir);\n+ BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI Read Norml-Data from rdata-register\n+ *\n+ * @param dataSize: size of data (max 4-byte)\n+ * @param dataBuff: buff of data\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_ReadNormlData(uint8_t dataSize, uint8_t *dataBuff)\n+{\n+ if(dataSize > 4){\n+ dataSize = 4;\n+ }\n+\n+ /* get receive data from registers*/\n+ uint32_t para_data = 0;\n+ para_data = BL_RD_REG(DBI_BASE, DBI_RDATA);\n+\n+ /* copy to buff */\n+ memcpy(dataBuff, ¶_data, dataSize);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI Write Norml-Data to rdata-register\n+ *\n+ * @param dataSize: size of data (max 4-byte)\n+ * @param dataBuff: buff of data\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_WriteNormlData(uint8_t dataSize, uint8_t *dataBuff)\n+{\n+ uint32_t para_data = 0;\n+\n+ if(dataSize > 4){\n+ dataSize = 4;\n+ }\n+\n+ for(uint8_t i=0; i<dataSize; i++){\n+ ((uint8_t *)(¶_data))[dataSize-i-1] = dataBuff[i];\n+ }\n+\n+ BL_WR_REG(DBI_BASE, DBI_WDATA, para_data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI Wirte Data to FIFO.\n+ * You should have configured Data byte count(normal or pixel) before,\n+ * And the transfer has been started.\n+ * note : The sum of data Count must be for the configured Count(normal or pixel),\n+ * Before the next transmission, you should wait for send done.\n+ *\n+ * @param wordCount: the WordsCount of data (Not data count)\n+ * @param pixelBuff: buff of data\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_WirteData2FIFO(uint32_t wordCount, uint32_t *dataBuff)\n+{\n+ for(uint32_t i = 0; i < wordCount; ){\n+ if (DBI_GetTxFifoCount() > 0) {\n+ BL_WR_REG(DBI_BASE, DBI_FIFO_WDATA, dataBuff[i++]);\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI Calculate the WordCount of data in different pixel formats\n+ * You should have configured the FIFO-format before\n+ * @param PixelCount: pixel count\n+ * @return Words Count\n+ *\n+*******************************************************************************/\n+uint32_t DBI_GetWordCountOfPixelData(int32_t PixelCount)\n+{\n+ uint32_t wordCount;\n+ /* get pixel-formats of fifo*/\n+ DBI_FIFO_Format_Type fifoFormat = BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0), DBI_FIFO_FORMAT);\n+\n+ if(fifoFormat == DBI_FIFO_888_NBGR || fifoFormat == DBI_FIFO_888_NRGB){\n+ wordCount = PixelCount;\n+ }else if(fifoFormat == DBI_FIFO_565_BGRBGR || fifoFormat == DBI_FIFO_565_RGBRGB){\n+ wordCount = (PixelCount + 1) >> 1;\n+ }else{\n+ wordCount = (PixelCount * 3 + 3) >> 2;\n+ }\n+ return wordCount;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI send Command and write normal-data function\n+ *\n+ * @param command: Command to send (if command phase enable)\n+ * @param dataSize: write size of NormalData (write max 4)\n+ * @param dataBuff: buff of NormalData\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SendCmdWithNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff)\n+{\n+ /* disable transfer */\n+ DBI_Disable();\n+\n+ /* clear fifo and interrupt */\n+ DBI_IntClear();\n+\n+ /* set command */\n+ DBI_SetCommand(command);\n+\n+ /* set data direction */\n+ DBI_SetNormalDataDir(DBI_DATA_WRITE);\n+\n+ /* Data type select, and set data count */\n+ DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize);\n+\n+ /* Fill the data into the register */\n+ DBI_WriteNormlData(dataSize, dataBuff);\n+\n+ /* enable transfer */\n+ DBI_Enable();\n+\n+ /* Wait transfer end */\n+ while (DBI_GetIntStatus(DBI_INT_END) != SET) {\n+ }\n+\n+ /* clear interrupt */\n+ DBI_IntClear();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI send Command and read normal-data function\n+ *\n+ * @param command: Command to send (if command phase enable)\n+ * @param dataSize: read size of NormalData (read max 4 )\n+ * @param dataBuff: buff of NormalData\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SendCmdAndReadNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff)\n+{\n+ /* disable transfer */\n+ DBI_Disable();\n+\n+ /* clear interrupt */\n+ DBI_IntClear();\n+\n+ /* set command */\n+ DBI_SetCommand(command);\n+\n+ /* set data direction */\n+ DBI_SetNormalDataDir(DBI_DATA_READ);\n+\n+ /* Data type select, and set data count */\n+ DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize);\n+\n+ /* enable transfer */\n+ DBI_Enable();\n+\n+ /* Wait transfer end */\n+ while (DBI_GetIntStatus(DBI_INT_END) != SET) {\n+ }\n+\n+ /* get data */\n+ DBI_ReadNormlData(dataSize, dataBuff);\n+\n+ /* clear interrupt */\n+ DBI_IntClear();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DBI send Command and write pixel-data function\n+ *\n+ * @param command: Command to send (if command phase enable)\n+ * @param dataSize: write size of Pixel-Data\n+ * @param dataBuff: buff of Pixel-Data\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SendCmdWithPixelData(uint8_t command, int32_t PixelCount, uint32_t *pixelBuff)\n+{\n+ /* disable transfer */\n+ DBI_Disable();\n+\n+ /* clear fifo and interrupt */\n+ DBI_TxFifoClear();\n+ DBI_IntClear();\n+\n+ /* set command */\n+ DBI_SetCommand(command);\n+\n+ /* set data direction */\n+ DBI_SetNormalDataDir(DBI_DATA_WRITE);\n+\n+ /* Data type select, and set data count */\n+ DBI_SetDataTypeAndCount(DBI_DATA_PIXEL, PixelCount);\n+\n+ /* enable transfer */\n+ DBI_Enable();\n+\n+ /* get words count */\n+ uint32_t wordsCount = DBI_GetWordCountOfPixelData(PixelCount);\n+ /* send data */\n+ DBI_WirteData2FIFO(wordsCount, pixelBuff);\n+\n+ /* Wait transfer end */\n+ while (DBI_GetIntStatus(DBI_INT_END) != SET) {\n+ }\n+\n+ /* clear interrupt */\n+ DBI_IntClear();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear tx fifo,overflow/underflow flag and fifo error interrupt will be cleared\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_TxFifoClear(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DBI_TX_FIFO_CLR);\n+ BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable or disable signal of dma interface\n+ *\n+ * @param dmaEn: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetDMA(BL_Fun_Type dmaEn)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_DMA_TX_EN, dmaEn);\n+ BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set tx fifo threshold\n+ *\n+ * @param threshold: Threshold value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_SetTxFifoThreshold(uint8_t threshold)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_TX_FIFO_TH, threshold);\n+ BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get tx fifo count value\n+ *\n+ * @param None\n+ *\n+ * @return Count value\n+ *\n+*******************************************************************************/\n+uint8_t DBI_GetTxFifoCount(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1), DBI_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get interrupt status\n+ *\n+ * @param intType: DBI interrupt type\n+ *\n+ * @return Status of interrupt\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DBI_GetIntStatus(DBI_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS);\n+\n+ if ((tmpVal >> intType & 1) == 1) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get tx fifo overflow/underflow status\n+ *\n+ * @param overflow: Select overflow or underflow\n+ *\n+ * @return Status of tx fifo\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DBI_GetOverflowStatus(DBI_Overflow_Type overflow)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DBI_OVERFLOW_TYPE(overflow));\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0);\n+\n+ if (overflow == DBI_TX_OVERFLOW) {\n+ if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_OVERFLOW)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_UNDERFLOW)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get DBI bus busy status\n+ *\n+ * @param None\n+ *\n+ * @return Status of DBI bus\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DBI_GetBusBusyStatus(void)\n+{\n+ if (BL_IS_REG_BIT_SET(BL_RD_REG(DBI_BASE, DBI_BUS_BUSY), DBI_STS_DBI_BUS_BUSY)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask the DBI interrupt\n+ *\n+ * @param intType: DBI interrupt type\n+ * @param intMask: Mask/Unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_IntMask(DBI_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DBI_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS);\n+\n+ switch (intType) {\n+ case DBI_INT_END:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask);\n+ break;\n+\n+ case DBI_INT_TX_FIFO_REQ:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask);\n+ break;\n+\n+ case DBI_INT_FIFO_ERR:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask);\n+ break;\n+\n+ case DBI_INT_ALL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(DBI_BASE, DBI_INT_STS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear DBI interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DBI_IntClear(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS);\n+ BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install DBI interrupt callback function\n+ *\n+ * @param intType: DBI interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DBI_Int_Callback_Install(DBI_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DBI_INT_TYPE(intType));\n+\n+ DBIIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/*@} end of group DBI_Public_Functions */\n+\n+/*@} end of group DBI */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9375503143df9175298822c418565ec5a8ca4280\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c\n@@ -0,0 +1,1060 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dma.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_dma.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DMA\n+ * @{\n+ */\n+\n+/** @defgroup DMA_Private_Macros\n+ * @{\n+ */\n+#define DMA_CHANNEL_OFFSET 0x100\n+#define DMA_Get_Channel(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100)\n+\n+/*@} end of group DMA_Private_Macros */\n+\n+/** @defgroup DMA_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DMA_Private_Types */\n+\n+/** @defgroup DMA_Private_Variables\n+ * @{\n+ */\n+static const uint32_t dmaAddr[DMA_ID_MAX] = { DMA0_BASE, DMA1_BASE, DMA2_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *dmaIntCbfArra[DMA_ID_MAX][DMA_CH_MAX][DMA_INT_ALL] = {\n+ { { NULL } }\n+};\n+#endif\n+static DMA_LLI_Ctrl_Type PingPongListArra[DMA_ID_MAX][DMA_CH_MAX][2];\n+\n+/*@} end of group DMA_Private_Variables */\n+\n+/** @defgroup DMA_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DMA_Global_Variables */\n+\n+/** @defgroup DMA_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void DMA_IntHandler(DMA_ID_Type dmaId);\n+#endif\n+static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId);\n+static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId);\n+\n+/*@} end of group DMA_Private_Fun_Declaration */\n+\n+/** @defgroup DMA_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DMA interrupt handler\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void DMA_IntHandler(DMA_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t intClr;\n+ uint8_t ch;\n+ /* Get DMA register */\n+ uint32_t DMAChs = dmaAddr[dmaId];\n+\n+ for (ch = 0; ch < DMA_CH_MAX; ch++) {\n+ tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);\n+\n+ if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) {\n+ /* Clear interrupt */\n+ tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);\n+ intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);\n+ intClr |= (1 << ch);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);\n+ BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);\n+\n+ if (dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED] != NULL) {\n+ /* Call the callback function */\n+ dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED]();\n+ }\n+ }\n+ }\n+\n+ for (ch = 0; ch < DMA_CH_MAX; ch++) {\n+ tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);\n+\n+ if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) {\n+ /*Clear interrupt */\n+ tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);\n+ intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);\n+ intClr |= (1 << ch);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);\n+ BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);\n+\n+ if (dmaIntCbfArra[dmaId][ch][DMA_INT_ERR] != NULL) {\n+ /* Call the callback function */\n+ dmaIntCbfArra[dmaId][ch][DMA_INT_ERR]();\n+ }\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief CPU enable DMA interrupt\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+\n+ if (DMA0_ID == dmaId) {\n+ CPU_Interrupt_Enable(DMA0_ALL_IRQn);\n+ } else if (DMA1_ID == dmaId) {\n+ CPU_Interrupt_Enable(DMA1_ALL_IRQn);\n+ } else {\n+ CPU_Interrupt_Enable(DMA2_INT0_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT1_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT2_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT3_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT4_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT5_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT6_IRQn);\n+ CPU_Interrupt_Enable(DMA2_INT7_IRQn);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CPU disable DMA interrupt\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+\n+ if (DMA0_ID == dmaId) {\n+ CPU_Interrupt_Disable(DMA0_ALL_IRQn);\n+ } else if (DMA1_ID == dmaId) {\n+ CPU_Interrupt_Disable(DMA1_ALL_IRQn);\n+ } else {\n+ CPU_Interrupt_Disable(DMA2_INT0_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT1_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT2_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT3_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT4_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT5_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT6_IRQn);\n+ CPU_Interrupt_Disable(DMA2_INT7_IRQn);\n+ }\n+}\n+\n+/*@} end of group DMA_Private_Functions */\n+\n+/** @defgroup DMA_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DMA enable\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Enable(DMA_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA register */\n+ uint32_t DMAChs = dmaAddr[dmaId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);\n+ BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(DMA0_ALL_IRQn, DMA0_ALL_IRQHandler);\n+ Interrupt_Handler_Register(DMA1_ALL_IRQn, DMA1_ALL_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT0_IRQn, DMA2_INT0_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT1_IRQn, DMA2_INT1_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT2_IRQn, DMA2_INT2_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT3_IRQn, DMA2_INT3_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT4_IRQn, DMA2_INT4_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT5_IRQn, DMA2_INT5_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT6_IRQn, DMA2_INT6_IRQHandler);\n+ Interrupt_Handler_Register(DMA2_INT7_IRQn, DMA2_INT7_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA disable\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Disable(DMA_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA register */\n+ uint32_t DMAChs = dmaAddr[dmaId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);\n+ BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA channel init\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param chCfg: DMA configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Channel_Init(DMA_ID_Type dmaId, DMA_Channel_Cfg_Type *chCfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], chCfg->ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch));\n+ CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth));\n+ CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth));\n+ CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSize));\n+ CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSize));\n+ CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir));\n+ CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph));\n+ CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph));\n+\n+ /* Disable clock gate when use DMA0 */\n+ if (DMA0_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0);\n+ } else if (DMA1_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1);\n+ } else if (DMA2_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2);\n+ }\n+\n+ /* Config channel config */\n+ BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr);\n+ BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr);\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSize);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSize);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA set default value of all registers function\n+ *\n+ * @param dmaId: DMA ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+void DMA_DeInit(DMA_ID_Type dmaId)\n+{\n+ switch (dmaId) {\n+ case DMA0_ID:\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA);\n+ break;\n+\n+ case DMA1_ID:\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA2);\n+ break;\n+\n+ case DMA2_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA channel update source memory address and len\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel\n+ * @param memAddr: source memoty address\n+ * @param len: source memory data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Channel_Update_SrcMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ /* config channel config*/\n+ BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr);\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA channel update destination memory address and len\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel\n+ * @param memAddr: destination memoty address\n+ * @param len: destination memory data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Channel_Update_DstMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ /* config channel config*/\n+ BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr);\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get DMA channel tranfersize\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel\n+ *\n+ * @return tranfersize size\n+ *\n+*******************************************************************************/\n+uint32_t DMA_Channel_TranferSize(DMA_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get DMA channel busy status\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DMA_Channel_Is_Busy(DMA_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA enable\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Channel_Enable(DMA_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA disable\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_Channel_Disable(DMA_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA init LLI transfer\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ * @param lliCfg: LLI configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_Init(DMA_ID_Type dmaId, uint8_t ch, DMA_LLI_Cfg_Type *lliCfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+ CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir));\n+ CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph));\n+ CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph));\n+\n+ /* Disable clock gate when use DMA0 */\n+ if (DMA0_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0);\n+ } else if (DMA1_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1);\n+ } else if (DMA2_ID == dmaId) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2);\n+ }\n+\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA channel update LLI\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ * @param LLI: LLI addr\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_Update(DMA_ID_Type dmaId, uint8_t ch, uint32_t LLI)\n+{\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ /* Config channel config */\n+ //BL_WR_REG(DMAChs, DMA_LLI, LLI);\n+ ARCH_MemCpy4((uint32_t *)(uintptr_t)DMAChs, (uint32_t *)(uintptr_t)LLI, 4);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA channel get LLI counter\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ *\n+ * @return LLI counter\n+ *\n+*******************************************************************************/\n+uint32_t DMA_LLI_Get_Counter(DMA_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_LLICOUNTER);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI PingPong Structure Start\n+ *\n+ * @param dmaPpStruct: dma pp struct pointer\n+ * @param Ping_Transfer_len: ping len\n+ * @param Pong_Transfer_len: pong len\n+ *\n+ * @return Succrss or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len)\n+{\n+ struct DMA_Control_Reg dmaCtrlRegVal_temp;\n+\n+ if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) {\n+ return ERROR;\n+ }\n+\n+ dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl;\n+ dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;\n+\n+ dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl;\n+ dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;\n+\n+ DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg);\n+ DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI Start New Transmit for Ping-Pong Buf\n+ *\n+ * @param dmaPpBuf: DMA LLI Ping-Pong Buf\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf)\n+{\n+ CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId);\n+\n+ if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) {\n+ DMA_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]);\n+ DMA_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan);\n+ dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0;\n+ }\n+\n+ CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI Remove Completed Ping-Pong Buf List\n+ *\n+ * @param dmaPpBuf: DMA LLI Ping-Pong Buf\n+ *\n+ * @return Next Ping-Pong Buf List Header\n+ *\n+*******************************************************************************/\n+DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf)\n+{\n+ CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId);\n+\n+ dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL;\n+ CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId);\n+ return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex];\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI Append Buf to List\n+ *\n+ * @param dmaPpBuf: DMA LLI Ping-Pong Buf\n+ * @param dmaLliList: New LLI Buf to Append\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList)\n+{\n+ DMA_LLI_Ctrl_Type *pLliList = NULL;\n+ CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId);\n+\n+ pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex];\n+\n+ if (pLliList == NULL) {\n+ dmaLliList->nextLLI = 0;\n+ dmaLliList->dmaCtrl.I = 1;\n+ dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList;\n+ } else {\n+ /*Append to last */\n+ while (pLliList->nextLLI != 0) {\n+ pLliList = (DMA_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI;\n+ }\n+\n+ pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList;\n+ pLliList->dmaCtrl.I = 0;\n+ dmaLliList->nextLLI = 0;\n+ dmaLliList->dmaCtrl.I = 1;\n+ }\n+\n+ if (DMA_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) {\n+ /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable)\n+\t\t or has already stopped before this function is called */\n+ if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) {\n+ /* DMA has already stopped before this function is called */\n+ DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf);\n+ }\n+ }\n+\n+ CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLi Destroy Ping-Pong Buf\n+ *\n+ * @param dmaPpBuf: DMA LLI Ping-Pong Buf\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf)\n+{\n+ /* DMA LLI Disable */\n+ DMA_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan);\n+\n+ if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) {\n+ dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]);\n+ }\n+\n+ dmaPpBuf->lliListHeader[0] = NULL;\n+\n+ if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) {\n+ dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]);\n+ }\n+\n+ dmaPpBuf->lliListHeader[1] = NULL;\n+ dmaPpBuf->idleIndex = 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask the DMA interrupt\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param ch: DMA channel number\n+ * @param intType: Specifies the interrupt type\n+ * @param intMask: Enable/Disable Specified interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_IntMask(DMA_ID_Type dmaId, uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));\n+ CHECK_PARAM(IS_DMA_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case DMA_INT_TCOMPLETED:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+ }\n+\n+ break;\n+\n+ case DMA_INT_ERR:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ }\n+\n+ break;\n+\n+ case DMA_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE);\n+ BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);\n+ tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I);\n+ BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install DMA interrupt callback function\n+ *\n+ * @param dmaId: DMA ID type\n+ * @param dmaChan: DMA Channel type\n+ * @param intType: DMA interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA_Int_Callback_Install(DMA_ID_Type dmaId, DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan));\n+ CHECK_PARAM(IS_DMA_INT_TYPE(intType));\n+\n+ dmaIntCbfArra[dmaId][dmaChan][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief WLSYS DMA0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA0_ALL_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief WLSYS DMA1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA1_ALL_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA1_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT0_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT1_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 2 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT2_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 3 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT3_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 4 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT4_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 5 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT5_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 6 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT6_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA channel 7 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2_INT7_IRQHandler(void)\n+{\n+ DMA_IntHandler(DMA2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI PingPong Structure Initial\n+ *\n+ * @param dmaPpStruct: DMA LLI PingPong Config Parameter\n+ *\n+ * @return start success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct)\n+{\n+ //setup lliList\n+ dmaPpStruct->dmaCtrlRegVal.I = 1;\n+ dmaPpStruct->pingpongIndex = 0;\n+\n+ if (dmaPpStruct->lliCfg->dir == DMA_TRNS_M2P) {\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ } else if (dmaPpStruct->lliCfg->dir == DMA_TRNS_P2M) {\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0];\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1];\n+ } else {\n+ return ERROR;\n+ /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/\n+ }\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;\n+\n+ DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg);\n+\n+ DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI PingPong Structure Start\n+ *\n+ * @param dmaPpStruct: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct)\n+{\n+ DMA_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA LLI PingPong Structure Stop\n+ *\n+ * @param dmaPpStruct: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct)\n+{\n+ DMA_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan);\n+}\n+\n+/*@} end of group DMA_Public_Functions */\n+\n+/*@} end of group DMA */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d406f906f040f0e41f7f3f35b06539c73aab4806\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c\n@@ -0,0 +1,1228 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dma2d.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_dma2d.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DMA2D\n+ * @{\n+ */\n+\n+/** @defgroup DMA2D_Private_Macros\n+ * @{\n+ */\n+#define DMA2D_Get_Channel(id_base, ch) ((id_base) + (ch)*0x100)\n+\n+/*@} end of group DMA2D_Private_Macros */\n+\n+/** @defgroup DMA2D_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DMA2D_Private_Types */\n+\n+/** @defgroup DMA2D_Private_Variables\n+ * @{\n+ */\n+static const uint32_t dma2dAddr[DMA2D_ID_MAX] = { DMA2D_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *dma2dIntCbfArra[DMA2D_ID_MAX][DMA2D_CH_MAX][DMA2D_INT_ALL] = {\n+ { { NULL } }\n+};\n+#endif\n+static DMA2D_LLI_Ctrl_Type PingPongListArra[DMA2D_ID_MAX][DMA2D_CH_MAX][2];\n+\n+/*@} end of group DMA2D_Private_Variables */\n+\n+/** @defgroup DMA2D_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DMA2D_Global_Variables */\n+\n+/** @defgroup DMA2D_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void DMA2D_IntHandler(DMA2D_ID_Type dmaId);\n+#endif\n+static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId);\n+static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId);\n+\n+/*@} end of group DMA2D_Private_Fun_Declaration */\n+\n+/** @defgroup DMA2D_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D interrupt handler\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void DMA2D_IntHandler(DMA2D_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ uint8_t ch;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = dma2dAddr[dmaId];\n+\n+ for (ch = 0; ch < DMA2D_CH_MAX; ch++) {\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_INTSTATUS);\n+\n+ if ((BL_GET_REG_BITS_VAL(tmpVal, DMA2D_INTSTATUS) & (1 << ch)) != 0) {\n+ /* Clear interrupt */\n+ BL_WR_REG(DMA2DChs, DMA2D_DMA_INTTCCLEAR, 1 << ch);\n+\n+ if (dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED] != NULL) {\n+ /* Call the callback function */\n+ dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED]();\n+ }\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief CPU enable DMA2D interrupt\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+\n+ CPU_Interrupt_Enable(DMA2D_INT0_IRQn);\n+ CPU_Interrupt_Enable(DMA2D_INT1_IRQn);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CPU disable DMA2D interrupt\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+\n+ CPU_Interrupt_Disable(DMA2D_INT0_IRQn);\n+ CPU_Interrupt_Disable(DMA2D_INT1_IRQn);\n+}\n+\n+/*@} end of group DMA2D_Private_Functions */\n+\n+/** @defgroup DMA2D_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D enable\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Enable(DMA2D_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = dma2dAddr[dmaId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_E);\n+ BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal);\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(DMA2D_INT0_IRQn, DMA2D_INT0_IRQHandler);\n+ Interrupt_Handler_Register(DMA2D_INT1_IRQn, DMA2D_INT1_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D disable\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Disable(DMA2D_ID_Type dmaId)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = dma2dAddr[dmaId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_E);\n+ BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D configure function\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+void DMA2D_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, BL_SET_REG_BIT(tmpVal, DMA2D_REG_DMA_2D_EN));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_SRC_CNT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_X_CNT, cfg->srcCntX);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_Y_CNT, cfg->srcCntY);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_CNT, tmpVal);\n+\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_XIC, cfg->srcIncrX);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_YIC, cfg->srcIncrY);\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_DST_CNT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_X_CNT, cfg->dstCntX);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_DST_CNT, tmpVal);\n+\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_DST_XIC, cfg->dstIncrX);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_DST_YIC, cfg->dstIncrY);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D channel init\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param chCfg: DMA2D configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Channel_Init(DMA2D_ID_Type dmaId, DMA2D_Channel_Cfg_Type *chCfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], chCfg->ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(chCfg->ch));\n+ CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth));\n+ CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth));\n+ CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->srcBurstSize));\n+ CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->dstBurstSize));\n+ CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(chCfg->dir));\n+ CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->dstPeriph));\n+ CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->srcPeriph));\n+\n+ /* Config channel config */\n+ BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, chCfg->srcDmaAddr);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, chCfg->destDmaAddr);\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, chCfg->transfLength);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_SIZE, chCfg->srcTransfWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_SIZE, chCfg->dstTransfWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_BURST, chCfg->srcBurstSize);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_BURST, chCfg->dstBurstSize);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SI, chCfg->srcAddrInc);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DI, chCfg->destAddrInc);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, chCfg->dir);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, chCfg->dstPeriph);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, chCfg->srcPeriph);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D set default value of all registers function\n+ *\n+ * @param dmaId: DMA2D ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+void DMA2D_DeInit(DMA2D_ID_Type dmaId)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA2D);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D channel update source memory address and len\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel\n+ * @param memAddr: source memoty address\n+ * @param len: source memory data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Channel_Update_SrcMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ /* config channel config*/\n+ BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, memAddr);\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D channel update destination memory address and len\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel\n+ * @param memAddr: destination memoty address\n+ * @param len: destination memory data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Channel_Update_DstMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ /* config channel config*/\n+ BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, memAddr);\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get DMA2D channel tranfersize\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel\n+ *\n+ * @return tranfersize size\n+ *\n+*******************************************************************************/\n+uint32_t DMA2D_Channel_TranferSize(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_TRANSFERSIZE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get DMA2D channel busy status\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DMA2D_Channel_Is_Busy(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ return BL_IS_REG_BIT_SET(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_CH_EN) == 1 ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D enable\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Channel_Enable(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_CH_EN);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D disable\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Channel_Disable(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_CH_EN);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D init LLI transfer\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ * @param lliCfg: LLI configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Cfg_Type *lliCfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+ CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(lliCfg->dir));\n+ CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->dstPeriph));\n+ CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->srcPeriph));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, lliCfg->dir);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, lliCfg->dstPeriph);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, lliCfg->srcPeriph);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D channel update LLI\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ * @param LLI: LLI addr\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_Update(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t LLI)\n+{\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch) + 0x100;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ /* Config channel config */\n+ //BL_WR_REG(DMA2DChs, DMA2D_LLI, LLI);\n+ ARCH_MemCpy4((uint32_t *)(uintptr_t)DMA2DChs, (uint32_t *)(uintptr_t)LLI, 10);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D channel get LLI counter\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ *\n+ * @return LLI counter\n+ *\n+*******************************************************************************/\n+uint32_t DMA2D_LLI_Get_Counter(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_LLICOUNTER);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI PingPong Structure Start\n+ *\n+ * @param dmaPpStruct: dma pp struct pointer\n+ * @param Ping_Transfer_len: ping len\n+ * @param Pong_Transfer_len: pong len\n+ *\n+ * @return Succrss or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type DMA2D_LLI_PpStruct_Set_Transfer_Len(DMA2D_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len)\n+{\n+ struct DMA2D_Control_Reg dmaCtrlRegVal_temp;\n+\n+ if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) {\n+ return ERROR;\n+ }\n+\n+ dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl;\n+ dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;\n+\n+ dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl;\n+ dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;\n+\n+ DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg);\n+ DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI Start New Transmit for Ping-Pong Buf\n+ *\n+ * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_PpBuf_Start_New_Transmit(DMA2D_LLI_PP_Buf *dmaPpBuf)\n+{\n+ CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId);\n+\n+ if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) {\n+ DMA2D_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]);\n+ DMA2D_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan);\n+ dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0;\n+ }\n+\n+ CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI Remove Completed Ping-Pong Buf List\n+ *\n+ * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf\n+ *\n+ * @return Next Ping-Pong Buf List Header\n+ *\n+*******************************************************************************/\n+DMA2D_LLI_Ctrl_Type *DMA2D_LLI_PpBuf_Remove_Completed_List(DMA2D_LLI_PP_Buf *dmaPpBuf)\n+{\n+ CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId);\n+\n+ dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL;\n+ CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId);\n+ return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex];\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI Append Buf to List\n+ *\n+ * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf\n+ * @param dmaLliList: New LLI Buf to Append\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_PpBuf_Append(DMA2D_LLI_PP_Buf *dmaPpBuf, DMA2D_LLI_Ctrl_Type *dmaLliList)\n+{\n+ DMA2D_LLI_Ctrl_Type *pLliList = NULL;\n+ CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId);\n+\n+ pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex];\n+\n+ if (pLliList == NULL) {\n+ dmaLliList->nextLLI = 0;\n+ dmaLliList->dmaCtrl.I = 1;\n+ dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList;\n+ } else {\n+ /*Append to last */\n+ while (pLliList->nextLLI != 0) {\n+ pLliList = (DMA2D_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI;\n+ }\n+\n+ pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList;\n+ pLliList->dmaCtrl.I = 0;\n+ dmaLliList->nextLLI = 0;\n+ dmaLliList->dmaCtrl.I = 1;\n+ }\n+\n+ if (DMA2D_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) {\n+ /* DMA2D stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable)\n+ or has already stopped before this function is called */\n+ if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) {\n+ /* DMA2D has already stopped before this function is called */\n+ DMA2D_LLI_PpBuf_Start_New_Transmit(dmaPpBuf);\n+ }\n+ }\n+\n+ CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLi Destroy Ping-Pong Buf\n+ *\n+ * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_PpBuf_Destroy(DMA2D_LLI_PP_Buf *dmaPpBuf)\n+{\n+ /* DMA2D LLI Disable */\n+ DMA2D_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan);\n+\n+ if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) {\n+ dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]);\n+ }\n+\n+ dmaPpBuf->lliListHeader[0] = NULL;\n+\n+ if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) {\n+ dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]);\n+ }\n+\n+ dmaPpBuf->lliListHeader[1] = NULL;\n+ dmaPpBuf->idleIndex = 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask the DMA2D interrupt\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param ch: DMA2D channel number\n+ * @param intType: Specifies the interrupt type\n+ * @param intMask: Enable/Disable Specified interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_IntMask(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ /* Get channel register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch));\n+ CHECK_PARAM(IS_DMA2D_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case DMA2D_INT_TCOMPLETED:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+ }\n+\n+ break;\n+\n+ case DMA2D_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_I);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_I);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install DMA2D interrupt callback function\n+ *\n+ * @param dmaId: DMA2D ID type\n+ * @param dmaChan: DMA2D Channel type\n+ * @param intType: DMA2D interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2D_Int_Callback_Install(DMA2D_ID_Type dmaId, DMA2D_Chan_Type dmaChan, DMA2D_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId));\n+ CHECK_PARAM(IS_DMA2D_CHAN_TYPE(dmaChan));\n+ CHECK_PARAM(IS_DMA2D_INT_TYPE(intType));\n+\n+ dma2dIntCbfArra[dmaId][dmaChan][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA2D channel 0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2D_INT0_IRQHandler(void)\n+{\n+ DMA2D_IntHandler(DMA2D0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief MMSYS DMA2D channel 1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DMA2D_INT1_IRQHandler(void)\n+{\n+ DMA2D_IntHandler(DMA2D0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI PingPong Structure Initial\n+ *\n+ * @param dmaPpStruct: DMA2D LLI PingPong Config Parameter\n+ *\n+ * @return start success or not\n+ *\n+*******************************************************************************/\n+BL_Err_Type DMA2D_LLI_PpStruct_Init(DMA2D_LLI_PP_Struct *dmaPpStruct)\n+{\n+ //setup lliList\n+ dmaPpStruct->dmaCtrlRegVal.I = 1;\n+ dmaPpStruct->pingpongIndex = 0;\n+\n+ if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_M2P) {\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ } else if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_P2M) {\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0];\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1];\n+ } else {\n+ return ERROR;\n+ /*V1.0 version DMA2D LLI Ping-Pong structure not support P2P & M2M MODE*/\n+ }\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;\n+\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX];\n+ PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;\n+\n+ DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg);\n+\n+ DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI PingPong Structure Start\n+ *\n+ * @param dmaPpStruct: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_PpStruct_Start(DMA2D_LLI_PP_Struct *dmaPpStruct)\n+{\n+ DMA2D_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D LLI PingPong Structure Stop\n+ *\n+ * @param dmaPpStruct: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_LLI_PpStruct_Stop(DMA2D_LLI_PP_Struct *dmaPpStruct)\n+{\n+ DMA2D_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D translate picture\n+ *\n+ * @param cfg: Pointer of DMA2D picture configure type\n+ * @param lliCfg: Pointer of DMA2D LLI ctrl type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Picture_Translate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg)\n+{\n+ uint32_t tmpVal = 1 << cfg->transWidth;\n+ lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth;\n+ lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth;\n+\n+ DMA2D_Picture_Cfg_Type pictureCfg = {\n+ .transWidth = cfg->transWidth,\n+ .pixWidth = cfg->pixWidth,\n+ .srcAddr = cfg->srcAddr,\n+ .srcWidth = cfg->srcWidth,\n+ .srcX0 = cfg->srcX0,\n+ .srcY0 = cfg->srcY0,\n+ .srcX1 = cfg->srcX1,\n+ .srcY1 = cfg->srcY1,\n+ .dstAddr = cfg->dstAddr,\n+ .dstWidth = cfg->dstWidth,\n+ .dstX0 = cfg->dstX0,\n+ .dstY0 = cfg->dstY0,\n+ };\n+\n+ if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth;\n+ } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ }\n+\n+ lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0;\n+ lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0;\n+\n+ lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.srcIncrX = tmpVal;\n+ lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0;\n+ lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal;\n+ lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.dstIncrX = tmpVal;\n+ lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D rotate picture\n+ *\n+ * @param cfg: Pointer of DMA2D picture configure type\n+ * @param lliCfg: Pointer of DMA2D LLI ctrl type\n+ * @param rotate: Rotate degree type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Picture_Rotate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Rotate_Type rotate)\n+{\n+ uint32_t tmpVal = 1 << cfg->transWidth;\n+ lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth;\n+ lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth;\n+\n+ DMA2D_Picture_Cfg_Type pictureCfg = {\n+ .transWidth = cfg->transWidth,\n+ .pixWidth = cfg->pixWidth,\n+ .srcAddr = cfg->srcAddr,\n+ .srcWidth = cfg->srcWidth,\n+ .srcX0 = cfg->srcX0,\n+ .srcY0 = cfg->srcY0,\n+ .srcX1 = cfg->srcX1,\n+ .srcY1 = cfg->srcY1,\n+ .dstAddr = cfg->dstAddr,\n+ .dstWidth = cfg->dstWidth,\n+ .dstX0 = cfg->dstX0,\n+ .dstY0 = cfg->dstY0,\n+ };\n+\n+ if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ }\n+\n+ lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0;\n+ lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0;\n+\n+ lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.srcIncrX = tmpVal;\n+ lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0;\n+ lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal;\n+ lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.dstIncrX = pictureCfg.dstWidth * pictureCfg.pixWidth;\n+ lliCfg->dma2dCfg.dstIncrY = -((pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal * pictureCfg.pixWidth * pictureCfg.dstWidth) + pictureCfg.pixWidth * pictureCfg.dstWidth - tmpVal;\n+\n+ if (rotate == DMA2D_ROTATE_DEGREE_90) {\n+ lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * tmpVal;\n+ } else if (rotate == DMA2D_ROTATE_DEGREE_180) {\n+ lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0) * tmpVal * pictureCfg.dstWidth + (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal;\n+ lliCfg->dma2dCfg.dstIncrX = -tmpVal;\n+ lliCfg->dma2dCfg.dstIncrY = -pictureCfg.dstWidth * pictureCfg.pixWidth + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal;\n+ } else if (rotate == DMA2D_ROTATE_DEGREE_270) {\n+ lliCfg->destDmaAddr += (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal * pictureCfg.dstWidth;\n+ lliCfg->dma2dCfg.dstIncrX = -pictureCfg.dstWidth * pictureCfg.pixWidth;\n+ lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D fold picture\n+ *\n+ * @param cfg: Pointer of DMA2D picture configure type\n+ * @param lliCfg: Pointer of DMA2D LLI ctrl type\n+ * @param fold: Fold direction type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Picture_Fold_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Fold_Type fold)\n+{\n+ uint32_t tmpVal = 1 << cfg->transWidth;\n+ lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth;\n+ lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth;\n+\n+ DMA2D_Picture_Cfg_Type pictureCfg = {\n+ .transWidth = cfg->transWidth,\n+ .pixWidth = cfg->pixWidth,\n+ .srcAddr = cfg->srcAddr,\n+ .srcWidth = cfg->srcWidth,\n+ .srcX0 = cfg->srcX0,\n+ .srcY0 = cfg->srcY0,\n+ .srcX1 = cfg->srcX1,\n+ .srcY1 = cfg->srcY1,\n+ .dstAddr = cfg->dstAddr,\n+ .dstWidth = cfg->dstWidth,\n+ .dstX0 = cfg->dstX0,\n+ .dstY0 = cfg->dstY0,\n+ };\n+\n+ if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth;\n+ } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ }\n+\n+ lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0;\n+ lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal;\n+\n+ lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.srcIncrX = tmpVal;\n+ lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0;\n+ lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal;\n+ lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.dstIncrX = -tmpVal;\n+ lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth + pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal;\n+\n+ if (fold == DMA2D_FOLD_UP_DOWN) {\n+ lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * pictureCfg.pixWidth * pictureCfg.dstWidth;\n+ lliCfg->dma2dCfg.dstIncrX = tmpVal;\n+ lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D fill picture\n+ *\n+ * @param cfg: Pointer of DMA2D picture configure type\n+ * @param lliCfg: Pointer of DMA2D LLI ctrl type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Picture_Fill_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg)\n+{\n+ uint32_t tmpVal = 1 << cfg->transWidth;\n+ lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth;\n+ lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth;\n+\n+ DMA2D_Picture_Cfg_Type pictureCfg = {\n+ .transWidth = cfg->transWidth,\n+ .pixWidth = cfg->pixWidth,\n+ .srcAddr = cfg->srcAddr,\n+ .srcWidth = cfg->srcWidth,\n+ .srcX0 = cfg->srcX0,\n+ .srcY0 = cfg->srcY0,\n+ .srcX1 = cfg->srcX1,\n+ .srcY1 = cfg->srcY1,\n+ .dstAddr = cfg->dstAddr,\n+ .dstWidth = cfg->dstWidth,\n+ .dstX0 = cfg->dstX0,\n+ .dstY0 = cfg->dstY0,\n+ };\n+\n+ if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth;\n+ } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) {\n+ pictureCfg.srcX0 = cfg->srcX1;\n+ pictureCfg.srcX1 = cfg->srcX0;\n+ pictureCfg.srcY0 = cfg->srcY1;\n+ pictureCfg.srcY1 = cfg->srcY0;\n+ pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth;\n+ }\n+\n+ lliCfg->srcDmaAddr = pictureCfg.srcAddr;\n+ lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0;\n+\n+ lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.srcIncrX = 0;\n+ lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0;\n+ lliCfg->dma2dCfg.srcIncrY = 0;\n+ lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal;\n+ lliCfg->dma2dCfg.dstIncrX = tmpVal;\n+ lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D transfer start\n+ *\n+ * @param dmaId: DMA2D id\n+ * @param ch: DMA2D channel\n+ * @param lliCfg: Pointer of DMA2D LLI ctrl type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Picture_Transfer_Start(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Ctrl_Type *lliCfg)\n+{\n+ DMA2D_Channel_Cfg_Type chCfg = {\n+ .srcDmaAddr = lliCfg->srcDmaAddr,\n+ .destDmaAddr = lliCfg->destDmaAddr,\n+ .transfLength = 0,\n+ .dir = DMA2D_TRNS_M2M,\n+ .ch = ch,\n+ .srcTransfWidth = lliCfg->dmaCtrl.SRC_SIZE,\n+ .dstTransfWidth = lliCfg->dmaCtrl.DST_SIZE,\n+ .srcBurstSize = DMA2D_BURST_SIZE_16,\n+ .dstBurstSize = DMA2D_BURST_SIZE_16,\n+ .srcAddrInc = DMA2D_MINC_ENABLE,\n+ .destAddrInc = DMA2D_MINC_ENABLE,\n+ .srcPeriph = DMA2D_REQ_NONE,\n+ .dstPeriph = DMA2D_REQ_NONE,\n+ };\n+\n+ DMA2D_Channel_Disable(dmaId, ch);\n+ DMA2D_Init(dmaId, ch, &lliCfg->dma2dCfg);\n+ DMA2D_Channel_Init(dmaId, &chCfg);\n+ DMA2D_Enable(dmaId);\n+ DMA2D_Channel_Enable(dmaId, ch);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D color key mode configure\n+ *\n+ * @param dmaId: DMA2D id\n+ * @param ch: DMA2D channel\n+ * @param keyType: Color key type\n+ * @param keyValue: Color key value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Color_Key_Set(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Color_Key_Type keyType, uint32_t keyValue)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_MODE, keyType);\n+ switch(keyType)\n+ {\n+ case DMA2D_COLOR_KEY_8BIT:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x1);\n+ break;\n+ case DMA2D_COLOR_KEY_16BIT:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x3);\n+ break;\n+ case DMA2D_COLOR_KEY_24BIT:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x7);\n+ break;\n+ case DMA2D_COLOR_KEY_32BIT:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0xf);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal);\n+\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_KEY, keyValue);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D color key mode enable\n+ *\n+ * @param dmaId: DMA2D id\n+ * @param ch: DMA2D channel\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Color_Key_Enable(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_KEY_EN);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DMA2D color key mode disable\n+ *\n+ * @param dmaId: DMA2D id\n+ * @param ch: DMA2D channel\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DMA2D_Color_Key_Disable(DMA2D_ID_Type dmaId, uint8_t ch)\n+{\n+ uint32_t tmpVal;\n+ /* Get DMA2D register */\n+ uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch);\n+\n+ tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN);\n+ BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, BL_CLR_REG_BIT(tmpVal, DMA2D_KEY_EN));\n+}\n+\n+/*@} end of group DMA2D_Public_Functions */\n+\n+/*@} end of group DMA2D */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..db9302df612fd39d7e9e9af8e2d2f71209581e91\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c\n@@ -0,0 +1,1500 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dsi.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dsi.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DSI\n+ * @{\n+ */\n+\n+/** @defgroup DSI_Private_Macros\n+ * @{\n+ */\n+#define DSI_TX_TIMEOUT_COUNT (320 * 1000)\n+\n+/*@} end of group DSI_Private_Macros */\n+\n+/** @defgroup DSI_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DSI_Private_Types */\n+\n+/** @defgroup DSI_Private_Variables\n+ * @{\n+ */\n+\n+static const uint32_t dsiAddr[DSI_ID_MAX] = { DSI_BASE };\n+\n+/**\n+ * @brief DSI interrupt callback function address array\n+*/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *DSIIntCbfArra[DSI_ID_MAX][DSI_INT_COUNT] = {\n+ { NULL, NULL, NULL }\n+};\n+#endif\n+/*@} end of group DSI_Private_Variables */\n+\n+/** @defgroup DSI_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSI_Global_Variables */\n+\n+/** @defgroup DSI_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId);\n+#endif\n+\n+/*@} end of group DSI_Private_Fun_Declaration */\n+\n+/** @defgroup DSI_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DSI interrupt handle\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId)\n+{\n+ uint32_t maskVal;\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_CAM_ID_TYPE(dsiId));\n+\n+ maskVal = BL_RD_REG(DSIx, DSI_INT_MASK);\n+ tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS);\n+\n+ if (tmpVal & DSI_INT_ESCAPE_TX_END && !(maskVal & DSI_INT_ESCAPE_TX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_ESCAPE_TX_END);\n+\n+ if (DSIIntCbfArra[dsiId][0] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][0]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_LPDT_RX_END && !(maskVal & DSI_INT_LPDT_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_LPDT_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][1] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][1]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_ULPS_RX_END && !(maskVal & DSI_INT_ULPS_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_ULPS_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][2] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][2]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_TRIGGER0_RX_END && !(maskVal & DSI_INT_TRIGGER0_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_TRIGGER0_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][3] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][3]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_TRIGGER1_RX_END && !(maskVal & DSI_INT_TRIGGER1_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_TRIGGER1_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][4] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][4]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_TRIGGER2_RX_END && !(maskVal & DSI_INT_TRIGGER2_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_TRIGGER2_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][5] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][5]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_TRIGGER3_RX_END && !(maskVal & DSI_INT_TRIGGER3_RX_END)) {\n+ DSI_IntClear(dsiId, DSI_INT_TRIGGER3_RX_END);\n+\n+ if (DSIIntCbfArra[dsiId][6] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][6]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_TX_FIFO_READY && !(maskVal & DSI_INT_TX_FIFO_READY)) {\n+ DSI_IntClear(dsiId, DSI_INT_TX_FIFO_READY);\n+\n+ if (DSIIntCbfArra[dsiId][7] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][7]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_RX_FIFO_READY && !(maskVal & DSI_INT_RX_FIFO_READY)) {\n+ DSI_IntClear(dsiId, DSI_INT_RX_FIFO_READY);\n+\n+ if (DSIIntCbfArra[dsiId][8] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][8]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_DATA_OVERRUN_ERR && !(maskVal & DSI_INT_DATA_OVERRUN_ERR)) {\n+ DSI_IntClear(dsiId, DSI_INT_DATA_OVERRUN_ERR);\n+\n+ if (DSIIntCbfArra[dsiId][9] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][9]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_DATA_UNDERRUN_ERR && !(maskVal & DSI_INT_DATA_UNDERRUN_ERR)) {\n+ DSI_IntClear(dsiId, DSI_INT_DATA_UNDERRUN_ERR);\n+\n+ if (DSIIntCbfArra[dsiId][10] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][10]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_PIXEL_COUNT_SMALL_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_SMALL_ERR)) {\n+ DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_SMALL_ERR);\n+\n+ if (DSIIntCbfArra[dsiId][11] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][11]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_PIXEL_COUNT_LARGE_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_LARGE_ERR)) {\n+ DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_LARGE_ERR);\n+\n+ if (DSIIntCbfArra[dsiId][12] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][12]();\n+ }\n+ }\n+\n+ if (tmpVal & DSI_INT_FIFO_ERROR && !(maskVal & DSI_INT_FIFO_ERROR)) {\n+ DSI_IntClear(dsiId, DSI_INT_FIFO_ERROR);\n+\n+ if (DSIIntCbfArra[dsiId][13] != NULL) {\n+ /* call the callback function */\n+ DSIIntCbfArra[dsiId][13]();\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/*@} end of group DSI_Private_Functions */\n+\n+/** @defgroup DSI_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DSI module init\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param cfg: DSI configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_Init(DSI_ID_Type dsiId, DSI_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ DSI_Lane_Type lanes=0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_DATA_TYPE(cfg->dataType));\n+ CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(cfg->laneNum));\n+ CHECK_PARAM(IS_DSI_LANE_ORDER_TYPE(cfg->laneOrder));\n+ CHECK_PARAM(IS_DSI_HS_SYNC_TYPE(cfg->syncType));\n+\n+ /* Set DSI configuration */\n+ tmpVal = BL_RD_REG(DSIx, DSI_CONFIG);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_NUM, cfg->laneNum);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_MODE, cfg->syncType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_MUX_SEL, cfg->laneOrder);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_DT, cfg->dataType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_VC, cfg->virtualChan);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VFP, cfg->vfp);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VSA, cfg->vsa);\n+\n+ BL_WR_REG(DSIx, DSI_CONFIG, tmpVal);\n+\n+ if(cfg->laneNum == DSI_LANE_NUMBER_1){\n+ lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0;\n+ }else if(cfg->laneNum == DSI_LANE_NUMBER_2){\n+ lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1;\n+ }else if(cfg->laneNum == DSI_LANE_NUMBER_4){\n+ lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1|DSI_LANE_DATA2|DSI_LANE_DATA3;\n+ }\n+\n+ DSI_PHY_Enable_Lanes(dsiId,lanes);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(MIPI_DSI_IRQn, DSI_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Deinit DSI module\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_Deinit(DSI_ID_Type dsiId)\n+{\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Enable Disable Interrupt\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param intType: DSI Interrupt Type\n+ * @param intMask: mask or unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_IntMask(DSI_ID_Type dsiId, DSI_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_INT_MASK);\n+\n+ if (intMask == UNMASK) {\n+ /* Unmask this interrupt */\n+ tmpVal &= (~intType);\n+\n+ } else {\n+ /* Mask this interrupt */\n+ tmpVal |= intType;\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_INT_MASK, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Clear Interrupt\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param intType: DSI Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_IntClear(DSI_ID_Type dsiId, DSI_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_INT_CLEAR);\n+\n+ /* Clear this interrupt */\n+ tmpVal |= intType;\n+\n+ BL_WR_REG(DSIx, DSI_INT_CLEAR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Enable Interrupt\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param intType: DSI Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_IntEnable(DSI_ID_Type dsiId, DSI_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_INT_ENABLE);\n+\n+ /* Enable this interrupt */\n+ tmpVal |= intType;\n+\n+ BL_WR_REG(DSIx, DSI_INT_ENABLE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Get Interrupt status\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+DSI_INT_Type DSI_IntGet(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, DSI_INT_STATUS);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI set line buffer threshold for controller to start transmitting each line(unit:pixel)\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param frameWidth: frame width\n+ * @param dvpTsrcClock: display(dp_dvp_tsrc) clock rate\n+ * @param dsiClock: DSI bit clock rate\n+ * @param dataType: DSI data type\n+ * @param laneNumber: DSI lane number\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_Set_Line_Buffer_Threshold(DSI_ID_Type dsiId, uint32_t frameWidth, uint32_t dvpTsrcClock, uint32_t dsiClock, \\\n+ DSI_Data_Type dataType, DSI_Lane_Number_Type laneNumber)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ int64_t threshold = dvpTsrcClock;\n+ uint32_t pixelByte;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_DATA_TYPE(dataType));\n+ CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(laneNumber));\n+\n+ /* Frame Width should not exceed 1280 and should be a multiple of 4 */\n+ if(frameWidth > 1280 || frameWidth % 4){\n+ return;\n+ }\n+\n+ if(dataType < DSI_DATA_RGB666){\n+ pixelByte = 2;\n+ }else{\n+ pixelByte = 3;\n+ }\n+\n+ threshold = frameWidth - threshold*frameWidth*pixelByte/(dsiClock/8)/(1<<laneNumber);\n+\n+ if(threshold < 6){\n+ threshold = 6;\n+ }\n+ tmpVal = BL_RD_REG(DSIx, DSI_HSTX_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_PC, frameWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_OUT_TH, threshold);\n+ BL_WR_REG(DSIx, DSI_HSTX_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI set VSA and VFP\n+ *\n+ * @param dsiId: DSI ID type\n+ * @param vsa: Vertical sync active\n+ * @param vfp: Vertical front porch\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_Set_VSA_VFP(DSI_ID_Type dsiId, uint8_t vsa, uint8_t vfp)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ \n+ tmpVal = BL_RD_REG(DSIx, DSI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VFP, vfp);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VSA, vsa);\n+ BL_WR_REG(DSIx, DSI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Reinit data lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Reset(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_RESET_N);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_RESET_N);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Config DPHY\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param phyCfg: DPHY config\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Config(DSI_ID_Type dsiId, DSI_DPhy_CFG_Type *phyCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_ZERO, phyCfg->time_clk_zero);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_TRAIL, phyCfg->time_clk_trail);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_EXIT, phyCfg->time_clk_exit);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_ZERO, phyCfg->time_data_zero);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_TRAIL, phyCfg->time_data_trail);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_EXIT, phyCfg->time_data_exit);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_PREP, phyCfg->time_data_prepare);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GO, phyCfg->time_ta_go);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GET, phyCfg->time_ta_get);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_REQRDY, phyCfg->time_req_ready);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_LPX, phyCfg->time_lpx);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_WAKEUP, phyCfg->time_wakeup);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_4, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Reinit data lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param lanes: lanes\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Reinit_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_LANE_TYPE(lanes));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+\n+ if (lanes & DSI_LANE_DATA0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA2) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA3) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI enable lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param lanes: lanes\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Enable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_LANE_TYPE(lanes));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ if (lanes & DSI_LANE_DATA0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA2) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA3) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_CLOCK) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_ENABLE);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI disable lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param lanes: lanes\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Disable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_LANE_TYPE(lanes));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ if (lanes & DSI_LANE_DATA0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA1) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA2) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA3) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_ENABLE);\n+ }\n+\n+ if (lanes & DSI_LANE_CLOCK) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_ENABLE);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI stop data lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param lanes: lanes\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Stop_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_LANE_TYPE(lanes));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+\n+ if (lanes & DSI_LANE_DATA0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA2) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE);\n+ }\n+\n+ if (lanes & DSI_LANE_DATA3) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI stop data lanes\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Data_Lane0_TurnAround(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_TURNESC);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI get lanes state\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param lanes: lanes\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Get_Lanes_State(DSI_ID_Type dsiId, DSI_Lane_Type lane, DSI_Lane_State_Type *state)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ uint32_t stop_state_pos = 0;\n+ uint32_t ulp_state_pos = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_LANE_TYPE(lanes));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ *state = DSI_LANE_STAT_NORMAL;\n+\n+ if (lane == DSI_LANE_DATA0) {\n+ stop_state_pos = DSI_DL0_STOPSTATE_POS;\n+ ulp_state_pos = DSI_DL0_ULPSACTIVENOT_POS;\n+ } else if (lane == DSI_LANE_DATA1) {\n+ stop_state_pos = DSI_DL1_STOPSTATE_POS;\n+ ulp_state_pos = DSI_DL1_ULPSACTIVENOT_POS;\n+ } else if (lane == DSI_LANE_DATA2) {\n+ stop_state_pos = DSI_DL2_STOPSTATE_POS;\n+ ulp_state_pos = DSI_DL2_ULPSACTIVENOT_POS;\n+ } else if (lane == DSI_LANE_DATA3) {\n+ stop_state_pos = DSI_DL3_STOPSTATE_POS;\n+ ulp_state_pos = DSI_DL3_ULPSACTIVENOT_POS;\n+ } else if (lane == DSI_LANE_CLOCK) {\n+ stop_state_pos = DSI_CL_STOPSTATE_POS;\n+ ulp_state_pos = DSI_CL_ULPSACTIVENOT_POS;\n+ } else {\n+ return;\n+ }\n+\n+ if(!(tmpVal & (1 << ulp_state_pos))) {\n+ *state = DSI_LANE_STAT_ULP;\n+ } else if(tmpVal & (1 << stop_state_pos)) {\n+ *state = DSI_LANE_STAT_STOP;\n+ } else {\n+ if(lane == DSI_LANE_CLOCK) {\n+ if(tmpVal & (1 << DSI_CL_TXREQUESTHS_POS)) {\n+ *state = DSI_LANE_STAT_HS;\n+ } else {\n+ *state = DSI_LANE_STAT_BRIDGE;\n+ }\n+ } else {\n+ if(BL_RD_REG(DSIx, DSI_CONFIG) & (1 << DSI_CR_HSTX_EN_POS)) {\n+ *state = DSI_LANE_STAT_HS;\n+ } else {\n+ *state = DSI_LANE_STAT_BRIDGE;\n+ }\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set clock lane operation\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param opt: operation type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+ CHECK_PARAM(IS_DSI_CLOCK_LANE_OPT_TYPE(opt));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+\n+ if (opt & DSI_CLOCK_LANE_OPT_ULP_ENTER) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSCLK);\n+ }\n+\n+ if (opt & DSI_CLOCK_LANE_OPT_ULP_EXIT) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSEXIT);\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+ arch_delay_ms(1);\n+ tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXULPSCLK);\n+ }\n+\n+ if (opt & DSI_CLOCK_LANE_OPT_HS_REQ) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS);\n+ }\n+ \n+ if (opt & DSI_CLOCK_LANE_OPT_HS_EXIT) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Start HS Mode\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_HS_Mode_Start(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ DSI_Lane_State_Type state = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ /* bring clock lane to high speed */\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state);\n+ if(state == DSI_LANE_STAT_STOP){\n+ DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_REQ);\n+ }\n+\n+ /* bring data lane to high speed */\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state);\n+ if(state == DSI_LANE_STAT_STOP){\n+ tmpVal = BL_RD_REG(DSIx, DSI_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_HSTX_EN);\n+ BL_WR_REG(DSIx, DSI_CONFIG, tmpVal);\n+ }\n+\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Stop HS Mode\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ DSI_Lane_State_Type state = 0;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ /* set data lane to stop mode */\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state);\n+ if(state != DSI_LANE_STAT_STOP){\n+ tmpVal = BL_RD_REG(DSIx, DSI_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_HSTX_EN);\n+ BL_WR_REG(DSIx, DSI_CONFIG, tmpVal);\n+ do{\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state);\n+ }while(state != DSI_LANE_STAT_STOP);\n+ }\n+\n+ /* set clock lane to stop mode */\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state);\n+ if(state != DSI_LANE_STAT_STOP){\n+ DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_EXIT);\n+ do{\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state);\n+ }while(state != DSI_LANE_STAT_STOP);\n+ }\n+\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI configure fifo function\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param fifoCfg: FIFO configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_FifoConfig(DSI_ID_Type dsiId, DSI_FifoCfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ /* Deal with DSI fifo configure register */\n+ tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1);\n+ /* Configure dma tx fifo threshold */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);\n+ /* Configure dma rx fifo threshold */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);\n+ /* Write back */\n+ BL_WR_REG(DSIx, DSI_FIFO_CONFIG_1, tmpVal);\n+\n+ /* Enable or disable DSI fifo dma function */\n+ tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_0);\n+\n+ if (ENABLE == fifoCfg->txFifoDmaEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_TX_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_TX_EN);\n+ }\n+\n+ if (ENABLE == fifoCfg->rxFifoDmaEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_RX_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_RX_EN);\n+ }\n+\n+ BL_WR_REG(DSIx, DSI_FIFO_CONFIG_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI start tx for short and long packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Start_Tx(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************//**\n+ * @brief DSI wait for send done\n+ * \n+ * @param dsiId: DSI ID type\n+ * \n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Wait_For_Esc_Tx_Done(DSI_ID_Type dsiId)\n+{ \n+ DSI_INT_Type intStatus;\n+\n+ /* wait for Tx finished */\n+ do{\n+ intStatus=DSI_IntGet(dsiId);\n+ }while(!(intStatus&DSI_INT_ESCAPE_TX_END));\n+ DSI_IntClear(dsiId,DSI_INT_ESCAPE_TX_END);\n+\n+ return SUCCESS;\n+}\n+/****************************************************************************/ /**\n+ * @brief DSI start rx for short and long packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Start_Rx(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Get Rx length\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return RX length\n+ *\n+*******************************************************************************/\n+uint16_t DSI_LPDT_Get_Rx_Length(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ return BL_GET_REG_BITS_VAL(tmpVal, DSI_ST_ESC_RX_LEN);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Escape mode send trigger command\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param cmd: trigger command\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Send_Trigger_Command(DSI_ID_Type dsiId, uint8_t cmd)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ DSI_PHY_HS_Mode_Stop(dsiId);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_TRIG, cmd);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ return DSI_Wait_For_Esc_Tx_Done(dsiId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Escape mode send ULPS command\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Send_ULPS_Command(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ DSI_PHY_HS_Mode_Stop(dsiId);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 2);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ return DSI_Wait_For_Esc_Tx_Done(dsiId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI exit ULPS\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Exit_ULPS(DSI_ID_Type dsiId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ //DSI_Lane_State_Type state;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_ULPS_EXIT, 1);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ arch_delay_ms(2);\n+#if 0\n+ DSI_PHY_HS_Mode_Stop(dsiId);\n+\n+ do\n+ {\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state);\n+ } while(state != DSI_LANE_STAT_STOP);\n+\n+#endif\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 3);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ return DSI_Wait_For_Esc_Tx_Done(dsiId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI config LPDT short packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param msg: LPDT long message config\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Config_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ DSI_PHY_HS_Mode_Stop(dsiId);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ /*short packet*/\n+ tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_buf[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, msg->tx_buf[1]);\n+ BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI send LPDT short packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param msg: DSI message config\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Send_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg)\n+{\n+ DSI_LPDT_Config_Short_Packet(dsiId, msg);\n+\n+ DSI_LPDT_Start_Tx(dsiId);\n+\n+ return DSI_Wait_For_Esc_Tx_Done(dsiId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI config LPDT long packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param msg: LPDT long message config\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Config_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ DSI_PHY_HS_Mode_Stop(dsiId);\n+\n+ tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0);\n+ BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal);\n+\n+ /*long packet*/\n+ tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_len & 0xff);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, (msg->tx_len >> 8) & 0xff);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, msg->tx_len);\n+ BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI get tx fifo unoccupied count value\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return Tx fifo unoccupied count value\n+ *\n+*******************************************************************************/\n+uint8_t DSI_GetTxFifoCount(DSI_ID_Type dsiId)\n+{\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI get rx fifo count value\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @return Rx fifo count value\n+ *\n+*******************************************************************************/\n+uint8_t DSI_GetRxFifoCount(DSI_ID_Type dsiId)\n+{\n+ uint32_t DSIx = dsiAddr[dsiId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_DSI_ID_TYPE(dsiId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_RX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI full fill FIFO\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param data: Data to send buffer\n+ *\n+ * @param len: Data length to send\n+ *\n+ * @return Data length filled\n+ *\n+*******************************************************************************/\n+uint8_t DSI_Full_Fill_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len)\n+{\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ const uint8_t *pDataEnd = data + len;\n+ uint8_t filled = 0;\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Send data */\n+ while (data < pDataEnd) {\n+ if (DSI_GetTxFifoCount(dsiId) > 0) {\n+ BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data));\n+ data += 4;\n+ filled += 4;\n+ } else {\n+ return filled;\n+ }\n+ }\n+\n+ return filled;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI feed FIFO with data\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param data: Data to send buffer\n+ *\n+ * @param len: Data length to send\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Feed_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len)\n+{\n+ uint32_t timeoutCnt = DSI_TX_TIMEOUT_COUNT;\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ const uint8_t *pDataEnd = data + len;\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Send data */\n+ while (data < pDataEnd) {\n+ if (DSI_GetTxFifoCount(dsiId) > 0) {\n+ BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data));\n+ timeoutCnt = DSI_TX_TIMEOUT_COUNT;\n+ data += 4;\n+ } else {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI Read FIFO\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param data: Data to receive buffer\n+ *\n+ * @param len: Data length to receive\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_Read_FIFO(DSI_ID_Type dsiId, uint8_t *data, uint16_t len)\n+{\n+ uint32_t DSIx = dsiAddr[dsiId];\n+ uint8_t *pDataEnd = data + len;\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Receive data */\n+ while (data < pDataEnd && DSI_GetRxFifoCount(dsiId) > 0) {\n+ BL_WRWD_TO_BYTEP(data, BL_RD_WORD(DSIx + DSI_FIFO_RDATA_OFFSET));\n+ data += 4;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI send LPDT long packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param msg: DSI message config\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Send_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg)\n+{\n+ uint8_t filled = 0;\n+\n+ DSI_LPDT_Config_Long_Packet(dsiId, msg);\n+\n+ filled = DSI_Full_Fill_FIFO(dsiId, msg->tx_buf, msg->tx_len);\n+\n+ DSI_LPDT_Start_Tx(dsiId);\n+\n+ if (filled < msg->tx_len) {\n+ DSI_Feed_FIFO(dsiId, msg->tx_buf + filled, msg->tx_len - filled);\n+ }\n+\n+ return DSI_Wait_For_Esc_Tx_Done(dsiId);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI receive packet\n+ *\n+ * @param dsiId: DSI ID type\n+ *\n+ * @param msg: DSI message config\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DSI_LPDT_Recv_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg)\n+{\n+ DSI_Lane_State_Type state;\n+ DSI_INT_Type intStatus;\n+\n+ /* wait for bus stop */\n+ do {\n+ DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state);\n+ } while (state != DSI_LANE_STAT_STOP);\n+\n+ /* turn around */\n+ DSI_PHY_Data_Lane0_TurnAround(dsiId);\n+\n+ /* start rx */\n+ DSI_LPDT_Start_Rx(dsiId);\n+\n+ /* wait for rx finished */\n+ do {\n+ intStatus = DSI_IntGet(dsiId);\n+ } while (!(intStatus & DSI_INT_LPDT_RX_END));\n+ DSI_IntClear(dsiId,DSI_INT_LPDT_RX_END);\n+\n+ msg->rx_len = DSI_LPDT_Get_Rx_Length(dsiId);\n+\n+ DSI_Read_FIFO(dsiId, msg->rx_buf, msg->rx_len);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSI interrupt function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DSI_IRQHandler(void)\n+{\n+ DSI_IntHandler(DSI0_ID);\n+}\n+#endif\n+\n+/*@} end of group DSI_Public_Functions */\n+\n+/*@} end of group DSI */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..31201042eb01c337ebdcee6696805bc1b6a90523\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c\n@@ -0,0 +1,2029 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dsp2.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dsp2.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DSP2\n+ * @{\n+ */\n+\n+/** @defgroup DSP2_Private_Macros\n+ * @{\n+ */\n+#define DSP2_PRINT_LOG 0\n+#if DSP2_PRINT_LOG\n+#include \"bflb_platform.h\"\n+#endif\n+\n+/* To avoid divide-0 exception in code */\n+#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))\n+\n+#define DIV_ROUND(divident, divider) (((divident) + ((divider) >> 1)) / (divider))\n+\n+#define SIGN_EXTEND(x, num_bits) ((((int)(x)) & ((1 << num_bits) - 1)) << (32 - num_bits) >> (32 - num_bits))\n+\n+#define BL_SET_REG_BITS_VAL_2(val, bitname, bitval) \\\n+ (((val)&bitname##_UMSK) | (((uint32_t)(bitval) << bitname##_POS) & bitname##_MSK))\n+\n+#define AE_SRAM_BASE ((uint32_t)0x30019000) /*!< AE status SRAM base address */\n+#define AWB_SRAM_BASE ((uint32_t)0x3001c000) /*!< AWB status SRAM base address */\n+\n+#define DSP2_BLC_MAX 1023\n+#define DSP2_BLC_MIN 0\n+\n+#define DSP2_BNR_WEIGHT_MAX 64\n+#define DSP2_BNR_WEIGHT_MIN 0\n+#define DSP2_BNR_LPF_WEIGHT_MAX 16\n+#define DSP2_BNR_LPF_WEIGHT_MIN 0\n+\n+#define DSP2_GAIN_MAX 2047\n+#define DSP2_GAIN_MIN 0\n+\n+#define DSP2_CCM_MAX 2047\n+#define DSP2_CCM_MIN -2048\n+\n+#define DSP2_BRIGHTNESS_MAX 127\n+#define DSP2_BRIGHTNESS_MIN -128\n+\n+#define DSP2_CONTRAST_MAX 255\n+#define DSP2_CONTRAST_MIN 0\n+\n+#define DSP2_SATURATION_MAX 255\n+#define DSP2_SATURATION_MIN 0\n+\n+#define DSP2_NOISE_LEVEL_MAX 63\n+#define DSP2_NOISE_LEVEL_MIN 0\n+\n+#define DSP2_NOISE_THRESHOLD_MAX 127\n+#define DSP2_NOISE_THRESHOLD_MIN 0\n+\n+#define DSP2_NR_STRENGTH_MAX 15\n+#define DSP2_NR_STRENGTH_MIN 0\n+\n+#define DSP2_Edge_Enhance_LEVEL_MAX 127\n+#define DSP2_Edge_Enhance_LEVEL_MIN 0\n+\n+#define DSP2_Edge_Enhance_LIMIT_MAX 255\n+#define DSP2_Edge_Enhance_LIMIT_MIN 0\n+\n+#define DSP2_Edge_Enhance_HPF_MAX 8\n+#define DSP2_Edge_Enhance_HPF_MIN 0\n+\n+#define DSP2_DPC_TH_MAX 255\n+#define DSP2_DPC_TH_MIN 0\n+\n+#define DSP2_AE_ROI_START_X_RANGE_MAX 2047\n+#define DSP2_AE_ROI_START_Y_RANGE_MAX 2047\n+#define DSP2_AE_ROI_WIDTH_RANGE_MAX 2047\n+#define DSP2_AE_ROI_WIDTH_RANGE_MIN 32\n+#define DSP2_AE_ROI_HEIGHT_RANGE_MAX 2047\n+#define DSP2_AE_ROI_HEIGHT_RANGE_MIN 2\n+\n+#define DSP2_AE_GRID_WIDTH_RANGE_MAX 255\n+#define DSP2_AE_GRID_WIDTH_RANGE_MIN 32\n+#define DSP2_AE_GRID_HEIGHT_RANGE_MAX 255\n+#define DSP2_AE_GRID_HEIGHT_RANGE_MIN 2\n+#define DSP2_AE_GRID_NUM_X_RANGE_MAX 12\n+#define DSP2_AE_GRID_NUM_X_RANGE_MIN 1\n+#define DSP2_AE_GRID_NUM_Y_RANGE_MAX 8\n+#define DSP2_AE_GRID_NUM_Y_RANGE_MIN 1\n+\n+#define DSP2_AWB_ROI_START_X_RANGE_MAX 2047\n+#define DSP2_AWB_ROI_START_Y_RANGE_MAX 2047\n+#define DSP2_AWB_ROI_WIDTH_RANGE_MAX 2047\n+#define DSP2_AWB_ROI_WIDTH_RANGE_MIN 32\n+#define DSP2_AWB_ROI_HEIGHT_RANGE_MAX 2047\n+#define DSP2_AWB_ROI_HEIGHT_RANGE_MIN 2\n+\n+#define DSP2_AWB_GRID_WIDTH_RANGE_MAX 255\n+#define DSP2_AWB_GRID_WIDTH_RANGE_MIN 32\n+#define DSP2_AWB_GRID_HEIGHT_RANGE_MAX 255\n+#define DSP2_AWB_GRID_HEIGHT_RANGE_MIN 2\n+#define DSP2_AWB_GRID_NUM_X_RANGE_MAX 32\n+#define DSP2_AWB_GRID_NUM_X_RANGE_MIN 1\n+#define DSP2_AWB_GRID_NUM_Y_RANGE_MAX 32\n+#define DSP2_AWB_GRID_NUM_Y_RANGE_MIN 1\n+\n+#define DSP2_AWB_R_MAX_THR_RANGE_MAX 4095\n+#define DSP2_AWB_R_MIN_THR_RANGE_MAX 4095\n+#define DSP2_AWB_G_MAX_THR_RANGE_MAX 4095\n+#define DSP2_AWB_G_MIN_THR_RANGE_MAX 4095\n+#define DSP2_AWB_B_MAX_THR_RANGE_MAX 4095\n+#define DSP2_AWB_B_MIN_THR_RANGE_MAX 4095\n+\n+#define DSP2_LSC_OFFSET_MAX 127\n+#define DSP2_LSC_OFFSET_MIN -128\n+\n+#define DSP2_EE_DIR_SHPNSS_THRESH_MAX 127\n+#define DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX 127\n+#define DSP2_EE_FLAT_REGION_THRESH_MAX 255\n+#define DSP2_EE_TEXTURE_REGION_THRESH_MAX 511\n+#define DSP2_EE_EDGE_REGION_THRESH_MAX 65535\n+\n+#define DSP2_EE_STRENGTH_MAX 127\n+#define DSP2_EE_NR_STRENGTH_MAX 255\n+\n+#define DSP2_EE_LUMA_WEIGHT_MAX 1023\n+\n+#define DSP2_AE_SRAM_BANK1 (AE_SRAM_BASE) /*!< 0x30019000 */\n+#define DSP2_AE_SRAM_BANK2 (AE_SRAM_BASE + (768)) /*!< 0x30019300 */\n+\n+#define DSP2_AWB_SRAM_BANK1 (AWB_SRAM_BASE) /*!< 0x3001c000 */\n+#define DSP2_AWB_SRAM_BANK2 (AWB_SRAM_BASE + (1024 * 8)) /*!< 0x3001e000 */\n+\n+#define DSP2_LSC_MAX_MAX 255\n+#define DSP2_LSC_MAX_MIN 0\n+\n+#define DSP2_ERROR_ADDR 0xffffffff\n+\n+/* For 16bits reg, high 8bits offset 1Byte is low 8bits */\n+#define DSP2_REG_H_L_OFFSET 0X1\n+\n+/* Read 16 bits data consits of high 8bits and low 8bits */\n+#define BL_RD_16_H_L_REG(addr_h, addr_l) \\\n+ ((BL_RD_BYTE(addr_h)) << 8) + (BL_RD_BYTE(addr_l))\n+\n+#define DSP2_RD_16_H_L_REG(regname_h, regname_l) \\\n+ ((BL_RD_BYTE_REG(DSP2_BASE, regname_h)) << 8) + (BL_RD_BYTE_REG(DSP2_BASE, regname_l))\n+\n+#define IS_BLACK_WHITE_MODE(mode) (mode == BLACK_WHITE_MODE_ON)\n+\n+/*@} end of group DSP2_Private_Macros */\n+\n+/** @defgroup DSP2_Private_Types\n+ * @{\n+ */\n+typedef enum {\n+ DSP2_DPC_OFF = 0,\n+ DSP2_DPC_FLY,\n+} DSP2_DPC_MODE_TYPE;\n+\n+typedef enum {\n+ DSP2_HSYNC_INVERT_NORMAL = 0,\n+ DSP2_HSYNC_INVERT_INVERT,\n+} DSP2_HSYNC_INVERT_TYPE;\n+\n+typedef enum {\n+ DSP2_VSYNC_INVERT_NORMAL = 0,\n+ DSP2_VSYNC_INVERT_INVERT,\n+} DSP2_VSYNC_INVERT_TYPE;\n+\n+typedef enum {\n+ DSP2_HCNT_RST_RISING = 0,\n+ DSP2_HCNT_RST_FALLING,\n+} DSP2_HCNT_RST_TYPE;\n+\n+typedef enum {\n+ DSP2_VCNT_RST_RISING = 0,\n+ DSP2_VCNT_RST_FALLING,\n+} DSP2_VCNT_RST_TYPE;\n+\n+typedef enum {\n+ DSP2_VCNT_RST_REVERT_FALLING = 0,\n+ DSP2_VCNT_RST_REVERT_RISING,\n+} DSP2_VCNT_RST_REVERT_TYPE;\n+\n+typedef enum {\n+ DSP2_FHBLK_LINE_OFF = 0,\n+ DSP2_FHBLK_LINE_ON = 1,\n+} DSP2_FHBLK_LINE_TYPE;\n+\n+/*@} end of group DSP2_Private_Types */\n+\n+/** @defgroup DSP2_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_Private_Variables */\n+\n+/** @defgroup DSP2_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_Global_Variables */\n+\n+/** @defgroup DSP2_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_Private_Fun_Declaration */\n+\n+/** @defgroup DSP2_Private_Functions\n+ * @{\n+ */\n+static uint16_t DSP2_Calc_Total_Width(const DSP2_TG_Cfg_Type *config)\n+{\n+ // uint32_t pix_clk = config->pix_clk;\n+ // uint32_t DSP2_clk = config->DSP2_clk;\n+ // uint16_t sns_tot_width = config->total_width;\n+\n+ return (uint16_t)((uint64_t)config->DSP2_clk / config->total_height / config->fps + 48) & 0xFFFE;\n+\n+ /* the final total width must be even */\n+\n+ // return (uint16_t)((uint64_t)DSP2_clk/1125/25) & 0xFFFE;\n+ // return (uint16_t)((uint64_t)sns_tot_width * DSP2_clk / pix_clk + 48) & 0xFFFE; //TODO: remove magic number\n+}\n+\n+static bool is_LSC_Coeff_Valid(const DSP2_LSC_COEF_S *lsc)\n+{\n+ int i;\n+\n+ const int DSP2_LSC_COEF_LIMIT[LSC_COEF_NUM][2] = {\n+ { -4194304, 4194303 }, /*!< A */\n+ { -4096, 4095 }, /*!< B */\n+ { 0, 255 }, /*!< C */\n+ { -4194304, 4194303 }, /*!< D */\n+ { -4096, 4095 }, /*!< E */\n+ { -4194304, 4194303 }, /*!< G */\n+ };\n+\n+ for (i = 0; i < LSC_COEF_NUM; ++i) {\n+ if ((lsc->lsc_coef_r.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_r.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) {\n+ return false;\n+ }\n+\n+ if ((lsc->lsc_coef_g.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_g.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) {\n+ return false;\n+ }\n+\n+ if ((lsc->lsc_coef_b.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_b.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) {\n+ return false;\n+ }\n+ }\n+\n+ return true;\n+}\n+\n+static int DSP2_Calc_Clamp_Gain(int black_level)\n+{\n+ return DIV_ROUND(4095 * 4096, (4095 - black_level));\n+}\n+\n+/*@} end of group DSP2_Private_Functions */\n+\n+/** @defgroup DSP2_Public_Functions\n+ * @{\n+ */\n+\n+void DSP2_Init(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE, 77);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE, 150);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE, 29);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_B);\n+ /* yuv output 16bit mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OUT_FORMAT_W, 1);\n+ /* YUYV order */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBCR_SELECT_W, 1);\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_B, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_AWB_GAIN_SEL_W);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W);\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal);\n+}\n+\n+void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg)\n+{\n+ dsp2_tg_reg_t *dsp2_tg_reg = (dsp2_tg_reg_t *)DSP2_BASE;\n+\n+ uint16_t act_start_pixel = 0;\n+ uint16_t act_pixel_width = 0;\n+ uint16_t act_start_line = 0;\n+ uint16_t act_line_height = 0;\n+\n+ uint16_t out_pixel_width = 0;\n+ uint16_t out_line_height = 0;\n+\n+ uint16_t out_start_pixel = 0;\n+ uint16_t out_start_line = 0;\n+\n+ /* TODO: crop the best window */\n+ if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) {\n+ act_start_pixel = 0; /* hcount reset in rising edge, so H blanking is put after valid line */\n+ act_pixel_width = cfg->active_width;\n+ act_start_line = 0;\n+ act_line_height = cfg->active_height;\n+ } else {\n+ act_start_pixel = cfg->total_width - cfg->active_width;\n+ act_pixel_width = cfg->active_width;\n+ act_start_line = cfg->total_height - cfg->active_height;\n+ act_line_height = cfg->active_height;\n+ }\n+\n+ out_pixel_width = cfg->out_width;\n+ out_line_height = cfg->out_height;\n+\n+ out_start_pixel = (act_pixel_width - out_pixel_width) / 2;\n+ out_start_line = (act_line_height - out_line_height) / 2;\n+\n+ /* further reduce frame latency by enabling act_vsync reset mode on vsync edge */\n+ dsp2_tg_reg->dvp_mode.BF.reg_act_vsync_rst_en_w = 1;\n+\n+ /* set sync mode */\n+ dsp2_tg_reg->dvp_mode.BF.sync_mode_w = cfg->sync_mode_value;\n+ dsp2_tg_reg->dvp_mode.BF.hsync_in_inv_w = DSP2_HSYNC_INVERT_NORMAL;\n+ /* dvp_tsrc would do vsync invert so vsync pulse is always active low */\n+ dsp2_tg_reg->dvp_mode.BF.vsync_in_inv_w = DSP2_VSYNC_INVERT_NORMAL;\n+ dsp2_tg_reg->dvp_mode.BF.fhblk_line_on_w = DSP2_FHBLK_LINE_OFF;\n+\n+ /* note: if vsync invert, vcnt reset mode set 0, means falling\n+\t else if vsync not invert, vcont reset mode set 1, also means falling\n+\t this value will not open to user now.\n+\t*/\n+ if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) {\n+ /* hcnt reset in rising edge, so H blanking is put after valid line\n+\t\t vcnt reset mode must be 0, to make sure vcnt is reset to 4095 instead of 0. */\n+ dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_RISING;\n+ dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_VCNT_RST_RISING;\n+ } else {\n+ dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_FALLING;\n+ dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_HCNT_RST_FALLING;\n+ }\n+\n+ /* set total pixels and total lines */\n+ dsp2_tg_reg->total_pixels.BF.total_hpixels_w =\n+ DSP2_Calc_Total_Width(cfg);\n+\n+ dsp2_tg_reg->total_pixels.BF.total_vlines_w = cfg->total_height;\n+ ;\n+\n+ /* act start pixel, act pixel width */\n+ dsp2_tg_reg->act_pixels_1.BF.act_start_pixel_w = act_start_pixel;\n+ dsp2_tg_reg->act_pixels_1.BF.act_pixel_width_w = act_pixel_width;\n+\n+ /* act start line, act line height */\n+ dsp2_tg_reg->act_pixels_2.BF.act_start_line_w = act_start_line;\n+ dsp2_tg_reg->act_pixels_2.BF.act_line_height_w = act_line_height;\n+\n+ /* out start pixel, out pixel width */\n+ dsp2_tg_reg->fact_pixels_1.BF.fact_start_pixel_w = out_start_pixel;\n+ dsp2_tg_reg->fact_pixels_1.BF.fact_pixel_width_w = out_pixel_width;\n+\n+ /* out start line, out line height*/\n+ dsp2_tg_reg->fact_pixels_2.BF.fact_start_line_w = out_start_line;\n+\n+ dsp2_tg_reg->fact_pixels_2.BF.fact_line_height_w = out_line_height;\n+}\n+\n+int DSP2_Get_Output_Window(BL_Img_Size_T *out_win)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_1);\n+ out_win->width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_PIXEL_WIDTH_W);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_2);\n+ out_win->height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_LINE_HEIGHT_W);\n+\n+ return 0;\n+}\n+\n+void DSP2_Set_Bayer_Pattern(const BAYER_PATTERN_E *pattern)\n+{\n+ dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE;\n+\n+ dsp2_front_reg->pattern_mode.BF.pattern_mode_w = 0;\n+\n+ /* fix issue: bayer pattern highly sensitive to total width setting */\n+ dsp2_front_reg->pattern_mode.BF.reg_bl_lpid_sel_w = 1;\n+\n+ if (*pattern == BAYER_PATTERN_BG) {\n+ /* lid invert depends on the total height */\n+ dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1;\n+ dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1;\n+ } else if (*pattern == BAYER_PATTERN_RG) {\n+ dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0;\n+ dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0;\n+ } else if (*pattern == BAYER_PATTERN_GR) {\n+ dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1;\n+ dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0;\n+ } else if (*pattern == BAYER_PATTERN_GB) {\n+ dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0;\n+ dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1;\n+ } else {\n+#if DSP2_PRINT_LOG\n+ MSG(\"Error bayer pattern!\\n\");\n+#endif\n+ return;\n+ }\n+\n+ /* hack for CISTA sensor */\n+ //dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1;\n+ //dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0;\n+}\n+\n+void DSP2_Set_AE_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal);\n+}\n+\n+void DSP2_Set_AE_Stats_Conf(const dsp2_ae_stats_conf_t *ae_stats_conf)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(ae_stats_conf->roi_start_x, DSP2_AE_ROI_START_X_RANGE_MAX);\n+ CHECK_PARAM_MAX(ae_stats_conf->roi_start_y, DSP2_AE_ROI_START_Y_RANGE_MAX);\n+ CHECK_PARAM_RANGE(ae_stats_conf->roi_width,\n+ DSP2_AE_ROI_WIDTH_RANGE_MIN, DSP2_AE_ROI_WIDTH_RANGE_MAX);\n+ CHECK_PARAM_RANGE(ae_stats_conf->roi_height,\n+ DSP2_AE_ROI_HEIGHT_RANGE_MIN, DSP2_AE_ROI_HEIGHT_RANGE_MAX);\n+ CHECK_PARAM_MIN(ae_stats_conf->grid_width, DSP2_AE_GRID_WIDTH_RANGE_MIN);\n+ CHECK_PARAM_MIN(ae_stats_conf->grid_height, DSP2_AE_GRID_HEIGHT_RANGE_MIN);\n+ CHECK_PARAM_RANGE(ae_stats_conf->grid_num_x,\n+ DSP2_AE_GRID_NUM_X_RANGE_MIN, DSP2_AE_GRID_NUM_X_RANGE_MAX);\n+ CHECK_PARAM_RANGE(ae_stats_conf->grid_num_y,\n+ DSP2_AE_GRID_NUM_Y_RANGE_MIN, DSP2_AE_GRID_NUM_Y_RANGE_MAX);\n+\n+ /* special check */\n+\n+ /* AE ROI must be in the active image region */\n+ if ((ae_stats_conf->roi_start_x + ae_stats_conf->roi_width > ae_stats_conf->img_width) ||\n+ (ae_stats_conf->roi_start_y + ae_stats_conf->roi_height > ae_stats_conf->img_height)) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"AE ROI must be in the active image region!\\r\\n\");\n+#endif\n+ }\n+\n+ /* grid width/height must be even number */\n+ if ((ae_stats_conf->grid_width & 0x1) & (ae_stats_conf->grid_height & 0x1)) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"Grid width/height must be even number!\\r\\n\");\n+#endif\n+ }\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE, ae_stats_conf->roi_start_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE, ae_stats_conf->roi_width);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE, ae_stats_conf->roi_start_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE, ae_stats_conf->roi_height);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE, ae_stats_conf->img_width);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE, ae_stats_conf->img_height);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE, ae_stats_conf->grid_width);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE, ae_stats_conf->grid_height);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE, ae_stats_conf->grid_num_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE, ae_stats_conf->grid_num_y);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W);\n+ /* AE occupies 2 bank of memory*/\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal);\n+}\n+\n+void DSP2_Get_AE_Stats_Conf(dsp2_ae_stats_conf_t *ae_stats_conf)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X);\n+ ae_stats_conf->roi_start_x = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE);\n+ ae_stats_conf->roi_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y);\n+ ae_stats_conf->roi_start_y = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE);\n+ ae_stats_conf->roi_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE);\n+ ae_stats_conf->img_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE);\n+ ae_stats_conf->img_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE);\n+ ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE);\n+ ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE);\n+ ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE);\n+ ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE);\n+}\n+\n+int DSP2_Get_AE_Stats(int grid_num, uint32_t *data)\n+{\n+ uint32_t tmpVal;\n+ uint32_t buf_idx;\n+ uint32_t buf_addr;\n+ uint32_t w_cnt_idx_start;\n+ uint32_t w_cnt_idx_end;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R);\n+ w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R);\n+\n+ buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2;\n+ ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid\n+\n+ w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R);\n+\n+ if (w_cnt_idx_start != w_cnt_idx_end) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"AE statistics overwrite!\\n\");\n+#endif\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+void DSP2_Get_AE_Sum(int grid_idx, AE_GRID_DATA_TYPE_E data_type, uint32_t *data)\n+{\n+ dsp2_ae_sum_t *grid_array;\n+ uint32_t tmpVal;\n+ uint32_t buf_idx;\n+ uint32_t buf_addr;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R);\n+\n+ buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2;\n+ grid_array = (dsp2_ae_sum_t *)(uintptr_t)buf_addr;\n+ *data = grid_array[grid_idx].y_sum;\n+}\n+\n+void DSP2_Set_AWB_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal);\n+}\n+\n+void DSP2_Set_AWB_Stats_Conf(const dsp2_awb_stats_conf_t *awb_stats_conf)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ CHECK_PARAM_MAX(awb_stats_conf->roi_start_x, DSP2_AWB_ROI_START_X_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->roi_start_y, DSP2_AWB_ROI_START_Y_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->roi_width, DSP2_AWB_ROI_WIDTH_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->roi_height, DSP2_AWB_ROI_HEIGHT_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->grid_num_x, DSP2_AWB_GRID_NUM_X_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->grid_num_y, DSP2_AWB_GRID_NUM_Y_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->r_max_thr, DSP2_AWB_R_MAX_THR_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->r_min_thr, DSP2_AWB_R_MIN_THR_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->g_max_thr, DSP2_AWB_G_MAX_THR_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->g_min_thr, DSP2_AWB_G_MIN_THR_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->b_max_thr, DSP2_AWB_B_MAX_THR_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->b_min_thr, DSP2_AWB_B_MIN_THR_RANGE_MAX);\n+\n+ CHECK_PARAM_MIN(awb_stats_conf->grid_width, DSP2_AWB_GRID_WIDTH_RANGE_MIN);\n+ CHECK_PARAM_MIN(awb_stats_conf->grid_height, DSP2_AWB_GRID_HEIGHT_RANGE_MIN);\n+\n+ /* special check */\n+ /* AWB ROI must be in the active image region */\n+ if ((awb_stats_conf->roi_start_x + awb_stats_conf->roi_width > awb_stats_conf->img_width) ||\n+ (awb_stats_conf->roi_start_y + awb_stats_conf->roi_height > awb_stats_conf->img_height)) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"AWB ROI must be in the active image region!\\r\\n\");\n+#endif\n+ }\n+\n+ /* grid width/height must be even number */\n+ if ((awb_stats_conf->grid_width & 0x1) & (awb_stats_conf->grid_height & 0x1)) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"Grid width/height must be even number!\\r\\n\");\n+#endif\n+ }\n+\n+ dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w = awb_stats_conf->roi_start_x;\n+ dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w = awb_stats_conf->roi_width;\n+ dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w = awb_stats_conf->roi_start_y;\n+ dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w = awb_stats_conf->roi_height;\n+\n+ dsp2_middle_reg->awb_image_size.BF.awb_image_width_w = awb_stats_conf->img_width;\n+ dsp2_middle_reg->awb_image_size.BF.awb_image_height_w = awb_stats_conf->img_height;\n+\n+ dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w = awb_stats_conf->grid_width;\n+ dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w = awb_stats_conf->grid_height;\n+\n+ dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w = awb_stats_conf->grid_num_x;\n+ dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w = awb_stats_conf->grid_num_y;\n+\n+ dsp2_middle_reg->awb_r_thre.BF.awb_r_max_thr_w = awb_stats_conf->r_max_thr;\n+ dsp2_middle_reg->awb_r_thre.BF.awb_r_min_thr_w = awb_stats_conf->r_min_thr;\n+\n+ dsp2_middle_reg->awb_g_thre.BF.awb_g_max_thr_w = awb_stats_conf->g_max_thr;\n+ dsp2_middle_reg->awb_g_thre.BF.awb_g_min_thr_w = awb_stats_conf->g_min_thr;\n+\n+ dsp2_middle_reg->awb_b_thre.BF.awb_b_max_thr_w = awb_stats_conf->b_max_thr;\n+ dsp2_middle_reg->awb_b_thre.BF.awb_b_min_thr_w = awb_stats_conf->b_min_thr;\n+\n+ dsp2_middle_reg->awb_setting.BF.new_awb_sta_enable_w = 1;\n+\n+ /* AWB occupies 2 banks of memory */\n+ dsp2_middle_reg->awb_setting.BF.awb_switch_bank_en_w = 1;\n+}\n+\n+void DSP2_Get_AWB_Stats_Conf(dsp2_awb_stats_conf_t *awb_stats_conf)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ awb_stats_conf->roi_start_x = dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w;\n+ awb_stats_conf->roi_start_y = dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w;\n+ awb_stats_conf->roi_width = dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w;\n+ awb_stats_conf->roi_height = dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w;\n+ awb_stats_conf->img_width = dsp2_middle_reg->awb_image_size.BF.awb_image_width_w;\n+ awb_stats_conf->img_height = dsp2_middle_reg->awb_image_size.BF.awb_image_height_w;\n+\n+ awb_stats_conf->grid_width = dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w;\n+ awb_stats_conf->grid_height = dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w;\n+\n+ awb_stats_conf->grid_num_x = dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w;\n+ awb_stats_conf->grid_num_y = dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w;\n+}\n+\n+int DSP2_Get_AWB_Stats(int grid_num, uint32_t *data)\n+{\n+ uint32_t tmpVal;\n+ uint32_t buf_idx;\n+ uint32_t buf_addr;\n+ uint32_t w_cnt_idx_start;\n+ uint32_t w_cnt_idx_end;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R);\n+ w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R);\n+\n+ buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2;\n+ ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid\n+\n+ w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R);\n+\n+ if (w_cnt_idx_start != w_cnt_idx_end) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"AWB statistics overwrite!\\n\");\n+#endif\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+void DSP2_Get_AWB_Sum(int grid_idx, RGB_SUM_S *rgb_sum)\n+{\n+ uint32_t tmpVal;\n+ uint32_t buf_idx;\n+ uint32_t buf_addr;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R);\n+\n+ buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2;\n+\n+ // dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t*)DSP2_BASE;\n+ dsp2_awb_sum_t *grid_array = (dsp2_awb_sum_t *)(uintptr_t)buf_addr;\n+\n+ rgb_sum->r_sum = grid_array[grid_idx].r_sum;\n+ rgb_sum->g_sum = grid_array[grid_idx].g_sum;\n+ rgb_sum->b_sum = grid_array[grid_idx].b_sum;\n+\n+ // *buf_idx = dsp2_middle_reg->awb_sta_dbg1.BF.blawb_buf_idx_r;\n+}\n+\n+void DSP2_Get_AWB_ValidGridNum(int *valid_grid_num)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ *valid_grid_num = dsp2_middle_reg->awb_setting.BF.grid_cnt_within_thre_r;\n+}\n+\n+void DSP2_Set_AWB_Gain(const DSP2_RGB_Gain_Type *rgb_gain)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE, rgb_gain->r_gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE, rgb_gain->g_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE, rgb_gain->b_gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GB_GAIN_PRE, rgb_gain->g_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN, tmpVal);\n+}\n+\n+void DSP2_Get_AWB_Gain(DSP2_RGB_Gain_Type *rgb_gain)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN);\n+\n+ rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE);\n+ rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN);\n+ rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE);\n+}\n+\n+void DSP2_Set_AWB2_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal);\n+}\n+\n+void DSP2_Set_AWB2_Gain_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal);\n+}\n+\n+int DSP2_Get_AWB2_Sum(dsp2_awb2_sum_t *sum)\n+{\n+ uint32_t tmpVal;\n+ uint64_t tmpVal64;\n+ uint32_t buf_idx;\n+ uint32_t w_cnt_idx_start;\n+ uint32_t w_cnt_idx_end;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BUF_IDX_R);\n+ w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R);\n+\n+ if (0 == buf_idx) {\n+ sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_R_AVG0_R);\n+ sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_G_AVG0_R);\n+ sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_B_AVG0_R);\n+ sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R);\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R4);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML0_R);\n+ sum->white_r_sum = (tmpVal64 << 9) + tmpVal;\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R7);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R);\n+ sum->white_g_sum = (tmpVal64 << 9) + tmpVal;\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RA);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R);\n+ sum->white_b_sum = (tmpVal64 << 9) + tmpVal;\n+ } else {\n+ sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_R_AVG1_R);\n+ sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_G_AVG1_R);\n+ sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_B_AVG1_R);\n+ sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R);\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R6);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML1_R);\n+ sum->white_r_sum = (tmpVal64 << 9) + tmpVal;\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R9);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R);\n+ sum->white_g_sum = (tmpVal64 << 9) + tmpVal;\n+\n+ tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RC);\n+ tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R);\n+ sum->white_b_sum = (tmpVal64 << 9) + tmpVal;\n+ }\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT);\n+ w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R);\n+\n+ // TODO: chang the algo\n+ if (w_cnt_idx_start != w_cnt_idx_end) {\n+#if DSP2_PRINT_LOG\n+ MSG(\"w_cnt_idx_start %d, w_cnt_idx_end %d \\r\\n\", w_cnt_idx_start, w_cnt_idx_end);\n+ MSG(\"AWB2 statistics overwrite!\\n\");\n+#endif\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+void DSP2_Set_AWB2_Gain(const DSP2_RGB_Gain_Type *rgb_gain)\n+{\n+ DSP2_Set_AWB_Gain(rgb_gain);\n+ // uint32_t tmpVal;\n+\n+ // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE, rgb_gain->r_gain);\n+ // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal);\n+\n+ // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE, rgb_gain->g_gain);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE, rgb_gain->b_gain);\n+ // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2, tmpVal);\n+}\n+\n+void DSP2_Get_AWB2_Gain(DSP2_RGB_Gain_Type *rgb_gain)\n+{\n+ DSP2_Get_AWB_Gain(rgb_gain);\n+ // uint32_t tmpVal;\n+\n+ // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1);\n+ // rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE);\n+\n+ // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2);\n+ // rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE);\n+ // rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE);\n+}\n+\n+void DSP2_Set_AWB2_Stats_Conf(const dsp2_awb2_stats_conf_t *awb_stats_conf)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(awb_stats_conf->stat_x_min, DSP2_AWB_ROI_START_X_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->stat_x_max, DSP2_AWB_ROI_START_X_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->stat_y_min, DSP2_AWB_ROI_START_Y_RANGE_MAX);\n+ CHECK_PARAM_MAX(awb_stats_conf->stat_y_max, DSP2_AWB_ROI_START_Y_RANGE_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MIN_PRE, awb_stats_conf->stat_x_min);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MAX_PRE, awb_stats_conf->stat_x_max);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MIN_PRE, awb_stats_conf->stat_y_min);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MAX_PRE, awb_stats_conf->stat_y_max);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE, awb_stats_conf->stat_pixel_num);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE, awb_stats_conf->stat_g_gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE, awb_stats_conf->stat_r_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE, awb_stats_conf->stat_b_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_VGAIN_PRE, awb_stats_conf->stat_v_gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_UGAIN_PRE, awb_stats_conf->stat_u_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH1_PRE, awb_stats_conf->y_th[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH2_PRE, awb_stats_conf->y_th[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH3_PRE, awb_stats_conf->y_th[3]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH4_PRE, awb_stats_conf->y_th[4]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH0_PRE, awb_stats_conf->y_th[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE, awb_stats_conf->y_weight[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE, awb_stats_conf->y_weight[3]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE, awb_stats_conf->y_weight[4]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE, awb_stats_conf->y_weight[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE, awb_stats_conf->y_weight[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE4_PRE, awb_stats_conf->y_slope[4]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE3_PRE, awb_stats_conf->y_slope[3]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE2_PRE, awb_stats_conf->y_slope[2]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE1_PRE, awb_stats_conf->y_slope[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE0_PRE, awb_stats_conf->y_slope[0]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG4_PRE, awb_stats_conf->u[4]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG5_PRE, awb_stats_conf->u[5]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG6_PRE, awb_stats_conf->u[6]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG7_PRE, awb_stats_conf->u[7]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->u[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->u[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->u[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->u[3]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG4_PRE, awb_stats_conf->v[4]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG5_PRE, awb_stats_conf->v[5]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG6_PRE, awb_stats_conf->v[6]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG7_PRE, awb_stats_conf->v[7]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->v[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->v[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->v[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->v[3]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH4_PRE, awb_stats_conf->c_th[4]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH5_PRE, awb_stats_conf->c_th[5]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH6_PRE, awb_stats_conf->c_th[6]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH7_PRE, awb_stats_conf->c_th[7]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH0_PRE, awb_stats_conf->c_th[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH1_PRE, awb_stats_conf->c_th[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH2_PRE, awb_stats_conf->c_th[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH3_PRE, awb_stats_conf->c_th[3]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE4_PRE, awb_stats_conf->c_slope[4]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE5_PRE, awb_stats_conf->c_slope[5]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE6_PRE, awb_stats_conf->c_slope[6]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE7_PRE, awb_stats_conf->c_slope[7]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE0_PRE, awb_stats_conf->c_slope[0]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE1_PRE, awb_stats_conf->c_slope[1]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE2_PRE, awb_stats_conf->c_slope[2]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE3_PRE, awb_stats_conf->c_slope[3]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7, tmpVal);\n+}\n+\n+void DSP2_Set_RB_Gain(const DSP2_RB_Gain_Type *rb_gain)\n+{\n+ DSP2_RGB_Gain_Type rgb_gain;\n+\n+ rgb_gain.r_gain = rb_gain->r_gain;\n+ rgb_gain.g_gain = 4096;\n+ rgb_gain.b_gain = rb_gain->b_gain;\n+\n+ DSP2_Set_AWB_Gain(&rgb_gain);\n+}\n+\n+int DSP2_Set_BLC(const DSP2_CLAMP_S *clamp)\n+{\n+ dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE;\n+\n+ CHECK_PARAM_RANGE(clamp->clamp_r, DSP2_BLC_MIN, DSP2_BLC_MAX);\n+ CHECK_PARAM_RANGE(clamp->clamp_gr, DSP2_BLC_MIN, DSP2_BLC_MAX);\n+ CHECK_PARAM_RANGE(clamp->clamp_gb, DSP2_BLC_MIN, DSP2_BLC_MAX);\n+ CHECK_PARAM_RANGE(clamp->clamp_b, DSP2_BLC_MIN, DSP2_BLC_MAX);\n+\n+ dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre = clamp->clamp_r;\n+ dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre = clamp->clamp_gr;\n+ dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre = clamp->clamp_gb;\n+ dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre = clamp->clamp_b;\n+\n+ dsp2_front_reg->gain_R_G.BF.rgain1_pre = 128;\n+ dsp2_front_reg->gain_R_G.BF.ggain1_pre = 128;\n+ dsp2_front_reg->gain_B.BF.bgain1_pre = 128;\n+\n+ /* compensate back the lost dynamic range for bayer image */\n+ dsp2_front_reg->clp_rgr_gain.BF.clp_gain_en_pre = 1;\n+ dsp2_front_reg->clp_rgr_gain.BF.clp_r_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_r);\n+ dsp2_front_reg->clp_rgr_gain.BF.clp_gr_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gr);\n+ dsp2_front_reg->clp_bgb_gain.BF.clp_gb_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gb);\n+ dsp2_front_reg->clp_bgb_gain.BF.clp_b_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_b);\n+\n+ return 0;\n+}\n+\n+int DSP2_Get_BLC(DSP2_CLAMP_S *clamp)\n+{\n+ dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE;\n+\n+ clamp->clamp_r = dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre;\n+ clamp->clamp_gr = dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre;\n+ clamp->clamp_gb = dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre;\n+ clamp->clamp_b = dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre;\n+\n+ return 0;\n+}\n+\n+void DSP2_Set_DPC_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal);\n+}\n+\n+void DSP2_Enable_DPC(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal);\n+}\n+\n+void DSP2_Disable_DPC(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal);\n+}\n+\n+int DSP2_Set_Defect_Correction_Enhance_Group(const DSP2_DPC_ENHANCE_GROUP_TYPE *value)\n+{\n+ int i;\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ for (i = 0; i < DSP2_DPC_Enhance_Num; i++) {\n+ if ((DISABLE != value->data[i]) && (ENABLE != value->data[i])) {\n+ return -1;\n+ }\n+ }\n+\n+ dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w = value->data[DSP2_DPC_Enhance1];\n+ dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w = value->data[DSP2_DPC_Enhance2];\n+ dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w = value->data[DSP2_DPC_Enhance3];\n+\n+ return 0;\n+}\n+\n+int DSP2_Get_Defect_Correction_Enhance_Group(DSP2_DPC_ENHANCE_GROUP_TYPE *value)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ value->data[DSP2_DPC_Enhance1] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w;\n+ value->data[DSP2_DPC_Enhance2] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w;\n+ value->data[DSP2_DPC_Enhance3] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w;\n+\n+ return 0;\n+}\n+\n+int DSP2_Set_Defect_Correction_Threshold_Group(const DSP2_DPC_THRESHOLD_GROUP_TYPE *value)\n+{\n+ int i;\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ for (i = 0; i < DSP2_DPC_th_Num; i++) {\n+ CHECK_PARAM_RANGE(value->data[i], DSP2_DPC_TH_MIN, DSP2_DPC_TH_MAX);\n+ }\n+\n+ dsp2_middle_reg->defect_th_A.BF.defect_th1_w = value->data[DSP2_DPC_th1];\n+ dsp2_middle_reg->defect_th_A.BF.defect_th2_w = value->data[DSP2_DPC_th2];\n+ dsp2_middle_reg->defect_th_A.BF.defect_th3_w = value->data[DSP2_DPC_th3];\n+ dsp2_middle_reg->defect_th_A.BF.defect_th4_w = value->data[DSP2_DPC_th4];\n+ dsp2_middle_reg->defect_th_B.BF.defect_th5_w = value->data[DSP2_DPC_th5];\n+\n+ return 0;\n+}\n+\n+int DSP2_Get_Defect_Correction_Threshold_Group(DSP2_DPC_THRESHOLD_GROUP_TYPE *value)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ value->data[DSP2_DPC_th1] = dsp2_middle_reg->defect_th_A.BF.defect_th1_w;\n+ value->data[DSP2_DPC_th2] = dsp2_middle_reg->defect_th_A.BF.defect_th2_w;\n+ value->data[DSP2_DPC_th3] = dsp2_middle_reg->defect_th_A.BF.defect_th3_w;\n+ value->data[DSP2_DPC_th4] = dsp2_middle_reg->defect_th_A.BF.defect_th4_w;\n+ value->data[DSP2_DPC_th5] = dsp2_middle_reg->defect_th_B.BF.defect_th5_w;\n+\n+ return 0;\n+}\n+\n+void DSP2_Set_BNR_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal);\n+}\n+\n+void DSP2_Get_BNR_State(BL_Fun_Type *state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE)) {\n+ *state = ENABLE;\n+ } else {\n+ *state = DISABLE;\n+ }\n+}\n+\n+/*\n+ Set/Get BNR Weight\n+ value range: 0~64\n+*/\n+void DSP2_Set_BNR_Weight(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_BNR_WEIGHT_MIN, DSP2_BNR_WEIGHT_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal);\n+}\n+\n+void DSP2_Get_BNR_Weight(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE);\n+}\n+\n+/*\n+ Set/Get BNR LPF Weight\n+ value range: 0~16\n+*/\n+void DSP2_Set_BNR_LPF_Weight(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_BNR_LPF_WEIGHT_MIN, DSP2_BNR_LPF_WEIGHT_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal);\n+}\n+\n+void DSP2_Get_BNR_LPF_Weight(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE);\n+}\n+\n+void DSP2_Set_BNR_Threshold(const DSP2_BNR_THRESHOLD_TYPE *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE, value->th_base_b);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE, value->th_base_g);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE, value->th_base_r);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE, value->th_slope_b);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE, value->th_slope_g);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE, value->th_slope_r);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE, value->slope_gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2, tmpVal);\n+}\n+\n+void DSP2_Get_BNR_Threshold(DSP2_BNR_THRESHOLD_TYPE *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0);\n+ value->th_base_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1);\n+ value->th_base_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE);\n+ value->th_base_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2);\n+ value->th_slope_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE);\n+ value->th_slope_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE);\n+ value->th_slope_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE);\n+ value->slope_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE);\n+}\n+\n+void DSP2_Set_BNR_Fallback(const DSP2_BNR_FALLBACK_TYPE *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE, value->fb_level);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE, value->fb_lpf_weight);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3, tmpVal);\n+}\n+\n+void DSP2_Get_BNR_Fallback(DSP2_BNR_FALLBACK_TYPE *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3);\n+ value->fb_lpf_weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE);\n+ value->fb_level = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE);\n+}\n+\n+void DSP2_Set_LSC_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal);\n+}\n+\n+void DSP2_Enable_LSC(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal);\n+}\n+\n+void DSP2_Disable_LSC(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal);\n+}\n+\n+void DSP2_Get_LSC_State(BL_Fun_Type *state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE_LSC_ON_W)) {\n+ *state = ENABLE;\n+ } else {\n+ *state = DISABLE;\n+ }\n+}\n+\n+/*\n+ xoffset and yoffset caculated by active and out window\n+ */\n+int DSP2_Set_LSC_Offset(int xoffset, int yoffset)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ CHECK_PARAM_RANGE(xoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX);\n+ CHECK_PARAM_RANGE(yoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX);\n+\n+ dsp2_middle_reg->LSC_setting.BF.X_offset_w = xoffset;\n+ dsp2_middle_reg->LSC_setting.BF.Y_offset_w = yoffset;\n+\n+ return 0;\n+}\n+\n+int DSP2_Set_LSC_Coeff(const DSP2_LSC_COEF_S *lsc)\n+{\n+ uint32_t tmpVal;\n+\n+ if (!is_LSC_Coeff_Valid(lsc)) {\n+ return -1;\n+ }\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ACOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_A]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_BCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_B]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ECOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_E]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_CCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_C]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_DCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_D]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_GCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_G]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ACOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_A]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_BCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_B]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ECOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_E]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_CCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_C]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_DCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_D]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_GCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_G]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ACOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_A]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_BCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_B]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ECOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_E]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_CCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_C]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_DCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_D]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_GCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_G]);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G, tmpVal);\n+\n+ return 0;\n+}\n+\n+int DSP2_Get_LSC_Coeff(DSP2_LSC_COEF_S *lsc)\n+{\n+ uint32_t tmpVal;\n+\n+ /* channel R */\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A);\n+ lsc->lsc_coef_r.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ACOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE);\n+ lsc->lsc_coef_r.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_BCOEFF_W), 13);\n+ lsc->lsc_coef_r.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ECOEFF_W), 13);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD);\n+ lsc->lsc_coef_r.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_CCOEFF_W);\n+ lsc->lsc_coef_r.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_DCOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G);\n+ lsc->lsc_coef_r.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_GCOEFF_W), 23);\n+\n+ /* channel G */\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A);\n+ lsc->lsc_coef_g.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ACOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE);\n+ lsc->lsc_coef_g.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_BCOEFF_W), 13);\n+ lsc->lsc_coef_g.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ECOEFF_W), 13);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD);\n+ lsc->lsc_coef_g.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_CCOEFF_W);\n+ lsc->lsc_coef_g.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_DCOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G);\n+ lsc->lsc_coef_g.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_GCOEFF_W), 23);\n+\n+ /* channel B */\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A);\n+ lsc->lsc_coef_b.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ACOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE);\n+ lsc->lsc_coef_b.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_BCOEFF_W), 13);\n+ lsc->lsc_coef_b.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ECOEFF_W), 13);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD);\n+ lsc->lsc_coef_b.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_CCOEFF_W);\n+ lsc->lsc_coef_b.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_DCOEFF_W), 23);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G);\n+ lsc->lsc_coef_b.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_GCOEFF_W), 23);\n+\n+ return 0;\n+}\n+\n+int DSP2_Set_LSC_Max(const DSP2_LSC_MAX_S *lsc_max)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ CHECK_PARAM_RANGE(lsc_max->max_r, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX);\n+ CHECK_PARAM_RANGE(lsc_max->max_g, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX);\n+ CHECK_PARAM_RANGE(lsc_max->max_b, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX);\n+\n+ dsp2_middle_reg->MAX_R_G.BF.MAXR_w = lsc_max->max_r;\n+ dsp2_middle_reg->MAX_R_G.BF.MAXG_w = lsc_max->max_g;\n+ dsp2_middle_reg->MAX_B.BF.MAXB_w = lsc_max->max_b;\n+\n+ return 0;\n+}\n+\n+int DSP2_Get_LSC_Max(DSP2_LSC_MAX_S *lsc_max)\n+{\n+ dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE;\n+\n+ lsc_max->max_r = dsp2_middle_reg->MAX_R_G.BF.MAXR_w;\n+ lsc_max->max_g = dsp2_middle_reg->MAX_R_G.BF.MAXG_w;\n+ lsc_max->max_b = dsp2_middle_reg->MAX_B.BF.MAXB_w;\n+\n+ return 0;\n+}\n+\n+void DSP2_Set_Digital_Gain(uint16_t dgain)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE, dgain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_R_GAIN_PRE, dgain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE, dgain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_B_GAIN_PRE, dgain);\n+ BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN, tmpVal);\n+}\n+\n+void DSP2_Set_CCM_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0, tmpVal);\n+}\n+\n+void DSP2_Get_CCM_State(BL_Fun_Type *state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE)) {\n+ *state = ENABLE;\n+ } else {\n+ *state = DISABLE;\n+ }\n+}\n+\n+void DSP2_Set_CCM_Coef(const DSP2_CCM_COEF_S *ccm)\n+{\n+ int i;\n+ uint32_t tmpVal;\n+\n+ for (i = 0; i < CCM_COEF_NUM; i++) {\n+ CHECK_PARAM_RANGE(ccm->ccm_coef[i], DSP2_CCM_MIN, DSP2_CCM_MAX);\n+ }\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE, ccm->ccm_coef[DSP2_CCM_11]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE, ccm->ccm_coef[DSP2_CCM_12]);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE, ccm->ccm_coef[DSP2_CCM_13]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE, ccm->ccm_coef[DSP2_CCM_21]);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE, ccm->ccm_coef[DSP2_CCM_22]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE, ccm->ccm_coef[DSP2_CCM_23]);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE, ccm->ccm_coef[DSP2_CCM_31]);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE, ccm->ccm_coef[DSP2_CCM_32]);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE, ccm->ccm_coef[DSP2_CCM_33]);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal);\n+}\n+\n+void DSP2_Get_CCM_Coef(DSP2_CCM_COEF_S *ccm)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0);\n+ ccm->ccm_coef[DSP2_CCM_11] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE), DSP2_BLBACK_CC_MATRIX00_PRE_LEN);\n+ ccm->ccm_coef[DSP2_CCM_12] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE), DSP2_BLBACK_CC_MATRIX01_PRE_LEN);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1);\n+ ccm->ccm_coef[DSP2_CCM_13] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE), DSP2_BLBACK_CC_MATRIX02_PRE_LEN);\n+ ccm->ccm_coef[DSP2_CCM_21] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE), DSP2_BLBACK_CC_MATRIX10_PRE_LEN);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2);\n+ ccm->ccm_coef[DSP2_CCM_22] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE), DSP2_BLBACK_CC_MATRIX11_PRE_LEN);\n+ ccm->ccm_coef[DSP2_CCM_23] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE), DSP2_BLBACK_CC_MATRIX12_PRE_LEN);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3);\n+ ccm->ccm_coef[DSP2_CCM_31] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE), DSP2_BLBACK_CC_MATRIX20_PRE_LEN);\n+ ccm->ccm_coef[DSP2_CCM_32] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE), DSP2_BLBACK_CC_MATRIX21_PRE_LEN);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX);\n+ ccm->ccm_coef[DSP2_CCM_33] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE), DSP2_BLBACK_CC_MATRIX22_PRE_LEN);\n+}\n+\n+void DSP2_Set_Gamma_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A, tmpVal);\n+}\n+\n+void DSP2_Get_Gamma_State(BL_Fun_Type *state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE)) {\n+ *state = ENABLE;\n+ } else {\n+ *state = DISABLE;\n+ }\n+}\n+\n+void DSP2_Set_Gamma_Coef(const DSP2_Gamma_Curve_Type *gamma_curve)\n+{\n+ ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET), (uint32_t *)&gamma_curve->curve_coef[0],\n+ GAMMA_COEF_NUM / 2);\n+}\n+\n+void DSP2_Get_Gamma_Coef(DSP2_Gamma_Curve_Type *gamma_curve)\n+{\n+ ARCH_MemCpy4((uint32_t *)&gamma_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET),\n+ GAMMA_COEF_NUM / 2);\n+}\n+\n+/*\n+ should not change, yuv range should change in yuv adjust module\n+*/\n+void DSP2_Init_Color_Enhancement()\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX00_PRE, 0x99);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX01_PRE, 0x12D);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX02_PRE, 0x3A);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX10_PRE, 0xFA9);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX11_PRE, 0xF57);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX12_PRE, 0x100);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX20_PRE, 0x100);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX21_PRE, 0xF29);\n+ tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX22_PRE, 0xFD7);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3, tmpVal);\n+}\n+\n+void DSP2_Set_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE type)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_YUV_CONV_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CONV_MODE_W, type);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE, tmpVal);\n+}\n+\n+void DSP2_Get_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE *type)\n+{\n+ *type = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE), DSP2_BLBACK_CONV_MODE_W);\n+}\n+\n+void DSP2_Set_Brightness(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_BRIGHTNESS_MIN, DSP2_BRIGHTNESS_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal);\n+}\n+\n+void DSP2_Get_Brightness(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ *value = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W), DSP2_BLBACK_YBRIGHTNESS_W_LEN);\n+}\n+\n+void DSP2_Set_Contrast(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_CONTRAST_MIN, DSP2_CONTRAST_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal);\n+}\n+\n+void DSP2_Get_Contrast(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W);\n+}\n+\n+void DSP2_Set_Saturation(const DSP2_SATURATION_S *saturation)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(saturation->saturation_cb, DSP2_SATURATION_MAX);\n+ CHECK_PARAM_MAX(saturation->saturation_cr, DSP2_SATURATION_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE, saturation->saturation_cb);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE, saturation->saturation_cr);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal);\n+}\n+\n+void DSP2_Get_Saturation(DSP2_SATURATION_S *saturation)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A);\n+ saturation->saturation_cb = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE);\n+ saturation->saturation_cr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE);\n+}\n+\n+void DSP2_Set_Noise_Level(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_NOISE_LEVEL_MIN, DSP2_NOISE_LEVEL_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal);\n+}\n+\n+void DSP2_Get_Noise_Level(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE);\n+}\n+\n+void DSP2_Set_2D_NR(int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal);\n+}\n+\n+void DSP2_Get_2D_NR(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE);\n+}\n+\n+void DSP2_Set_3D_NR(const int value)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE, value);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal);\n+}\n+\n+void DSP2_Get_3D_NR(int *value)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A);\n+ *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE);\n+}\n+\n+void DSP2_Set_EE_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+}\n+\n+void DSP2_Enable_EE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+}\n+\n+void DSP2_Disable_EE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+}\n+\n+void DSP2_EnableEEOverShoot(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+}\n+\n+void DSP2_DisableEEOverShoot(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+}\n+\n+void DSP2_Set_EE_Thresh(const DSP2_EE_Thresh_Type *threshCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(threshCfg->dirShpnessThresh, DSP2_EE_DIR_SHPNSS_THRESH_MAX);\n+ CHECK_PARAM_MAX(threshCfg->noDirShpnessThresh, DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX);\n+ CHECK_PARAM_RANGE(threshCfg->textureThresh, (threshCfg->flatThresh + 1), DSP2_EE_TEXTURE_REGION_THRESH_MAX);\n+ CHECK_PARAM_MIN(threshCfg->edgeThresh, (threshCfg->textureThresh + 1));\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE, threshCfg->textureThresh);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE, threshCfg->dirShpnessThresh);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE, threshCfg->noDirShpnessThresh);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE, threshCfg->flatThresh);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3);\n+ ;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE, threshCfg->edgeThresh);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal);\n+}\n+\n+void DSP2_Get_EE_Thresh(DSP2_EE_Thresh_Type *threshCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0);\n+ threshCfg->textureThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1);\n+ threshCfg->dirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE);\n+ threshCfg->noDirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE);\n+ threshCfg->flatThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3);\n+ threshCfg->edgeThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE);\n+}\n+\n+void DSP2_Set_EE_Strength(const DSP2_EE_Str_Type *strCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(strCfg->posEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX);\n+ CHECK_PARAM_MAX(strCfg->negEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX);\n+ CHECK_PARAM_MAX(strCfg->posEdgeStr, DSP2_EE_STRENGTH_MAX);\n+ CHECK_PARAM_MAX(strCfg->negEdgeStr, DSP2_EE_STRENGTH_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE, strCfg->posEdgeOvrshtStr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE, strCfg->negEdgeOvrshtStr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE, strCfg->posEdgeStr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE, strCfg->negEdgeStr);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3);\n+ ;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE, strCfg->nrStr);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal);\n+}\n+\n+void DSP2_Get_EE_Strength(DSP2_EE_Str_Type *strCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2);\n+ strCfg->posEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE);\n+ strCfg->negEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE);\n+ strCfg->posEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE);\n+ strCfg->negEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3);\n+ ;\n+ strCfg->nrStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE);\n+}\n+\n+void DSP2_Set_EE_LumaWeight(const DSP2_EE_Luma_Weight_Type *lumaWgtCfg)\n+{\n+ int i;\n+ uint32_t tmpVal;\n+ uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET;\n+\n+ for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) {\n+ CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i], DSP2_EE_LUMA_WEIGHT_MAX);\n+ CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i + 1], DSP2_EE_LUMA_WEIGHT_MAX);\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE, lumaWgtCfg->lumaWgtTbl[i]);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE, lumaWgtCfg->lumaWgtTbl[i + 1]);\n+ BL_WR_WORD(tmpAddr, tmpVal);\n+ }\n+}\n+\n+void DSP2_Get_EE_LumaWeight(DSP2_EE_Luma_Weight_Type *lumaWgtCfg)\n+{\n+ int i;\n+ uint32_t tmpVal;\n+ uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET;\n+\n+ for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) {\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+ lumaWgtCfg->lumaWgtTbl[i] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE);\n+ lumaWgtCfg->lumaWgtTbl[i + 1] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE);\n+ }\n+}\n+\n+void DSP2_Set_ChromaSuppress_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal);\n+}\n+\n+void DSP2_Enable_ChromaSuppress(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal);\n+}\n+\n+void DSP2_Disable_ChromaSuppress(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal);\n+}\n+\n+void DSP2_Set_ChromaSuppress(const DSP2_Chroma_Suppress_Type *chromaSupprCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE, chromaSupprCfg->gain);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE, chromaSupprCfg->weight);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE, chromaSupprCfg->gain_thresh);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal);\n+}\n+\n+void DSP2_Get_ChromaSuppress(DSP2_Chroma_Suppress_Type *chromaSupprCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2);\n+ chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE);\n+ chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE);\n+ chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE);\n+}\n+\n+/*@} end of group DSP2_Public_Functions */\n+\n+/*@} end of group DSP2 */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..67b078763f583d0954d2d6a65a2b1ccd0a1b1cc4\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c\n@@ -0,0 +1,234 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dsp2_axi_ctrl.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dsp2_axi_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DSP2_AXI_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup DSP2_AXI_CTRL_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Private_Macros */\n+\n+/** @defgroup DSP2_AXI_CTRL_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Private_Types */\n+\n+/** @defgroup DSP2_AXI_CTRL_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Private_Variables */\n+\n+/** @defgroup DSP2_AXI_CTRL_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Global_Variables */\n+\n+/** @defgroup DSP2_AXI_CTRL_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Private_Fun_Declaration */\n+\n+/** @defgroup DSP2_AXI_CTRL_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_AXI_CTRL_Private_Functions */\n+\n+/** @defgroup DSP2_AXI_CTRL_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR init function\n+ *\n+ * @param dsp23DNRCfg: 3DNR configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_3DNR_Init(DSP2_3DNR_Cfg_Type *dsp23DNRCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_3DNR_BURST_TYPE(dsp23DNRCfg->burst));\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_AXI_CTRL_REG_XLEN, dsp23DNRCfg->burst);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, tmpVal);\n+\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HADDR_START_ADDRESS, dsp23DNRCfg->memStart);\n+\n+ /*Set memory brust size */\n+ switch (dsp23DNRCfg->burst) {\n+ case DSP2_3DNR_BURST_TYPE_SINGLE:\n+ tmpVal = dsp23DNRCfg->memSize / 8;\n+ break;\n+\n+ case DSP2_3DNR_BURST_TYPE_INCR4:\n+ tmpVal = dsp23DNRCfg->memSize / 32;\n+ break;\n+\n+ case DSP2_3DNR_BURST_TYPE_INCR8:\n+ tmpVal = dsp23DNRCfg->memSize / 64;\n+ break;\n+\n+ case DSP2_3DNR_BURST_TYPE_INCR16:\n+ tmpVal = dsp23DNRCfg->memSize / 128;\n+ break;\n+\n+ case DSP2_3DNR_BURST_TYPE_INCR32:\n+ tmpVal = dsp23DNRCfg->memSize / 256;\n+ break;\n+\n+ case DSP2_3DNR_BURST_TYPE_INCR64:\n+ tmpVal = dsp23DNRCfg->memSize / 512;\n+ break;\n+\n+ default:\n+ tmpVal = 0;\n+ break;\n+ }\n+\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_MEMORY_BURST_COUNT, tmpVal);\n+\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HSYNC_CONTROL, dsp23DNRCfg->hsyncStart << 16 | dsp23DNRCfg->hsyncEnd);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_VSYNC_CONTROL, dsp23DNRCfg->vsyncStart << 16 | dsp23DNRCfg->vsyncEnd);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR enable function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_3DNR_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR disable function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_3DNR_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_CLR_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR clear write fifo overflow error function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_3DNR_Clear_Write_Overflow(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_OVERFLOW_CLR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR clear read fifo drain error function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_3DNR_Clear_Read_Drain(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL);\n+ BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_DRAIN_CLR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief 3DNR get write and read status function\n+ *\n+ * @param dsp23DNRStatus: 3DNR write and read status type\n+ *\n+ * @return Set or reset\n+ *\n+*******************************************************************************/\n+BL_Sts_Type DSP2_3DNR_Get_status(DSP2_3DNR_Status_Type dsp23DNRStatus)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_STATUS);\n+\n+ if (tmpVal & 1 << dsp23DNRStatus) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/*@} end of group DSP2_AXI_CTRL_Public_Functions */\n+\n+/*@} end of group DSP2_AXI_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d9a43dc74a305aba7eddff3bea5c97d46194ce17\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c\n@@ -0,0 +1,1575 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dsp2_misc.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dsp2_misc.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DSP2_MISC\n+ * @{\n+ */\n+\n+/** @defgroup DSP2_MISC_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_MISC_Private_Macros */\n+\n+/** @defgroup DSP2_MISC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_MISC_Private_Types */\n+\n+/** @defgroup DSP2_MISC_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *dsp2MiscIntCbfArra[DSP2_MISC_INT_ALL] = {\n+ NULL\n+};\n+#endif\n+\n+/*@} end of group DSP2_MISC_Private_Variables */\n+\n+/** @defgroup DSP2_MISC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_MISC_Global_Variables */\n+\n+/** @defgroup DSP2_MISC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_MISC_Private_Fun_Declaration */\n+\n+/** @defgroup DSP2_MISC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_MISC_Private_Functions */\n+\n+/** @defgroup DSP2_MISC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************//**\n+ * @brief DVP AS 2X function init\n+ *\n+ * @param dvp2xCfg: DVP AS 2X configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg)\n+{\n+ uint32_t tmpVal;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->hSyncLevel));\n+ CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->vSyncLevel));\n+ CHECK_PARAM(IS_DSP2_MISC_2X_DATA_ORDER_TYPE(dvp2xCfg->dataOrder));\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_HS_INV, dvp2xCfg->hSyncLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_VS_INV, dvp2xCfg->vSyncLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_DA_ORDER, dvp2xCfg->dataOrder);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_FIFO_TH, dvp2xCfg->fifoThreshold & 0x7ff);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief DVP AS 2X function enable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_2X_Enable(void)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE));\n+}\n+\n+/****************************************************************************//**\n+ * @brief DVP AS 2X function disable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_2X_Disable(void)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAM input selection\n+ *\n+ * @param camId: CAM id\n+ * @param inputType: CAM input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_CAM_Input_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_CAM_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_DSP2_MISC_CAM_INPUT_TYPE(inputType));\n+\n+ if (camId < DSP2_MISC_CAM_4_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1);\n+ tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal);\n+ } else {\n+ camId -= 4;\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2);\n+ tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CAM frame id type selection\n+ *\n+ * @param camId: CAM id\n+ * @param idType: Frame id type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_CAM_Frame_ID_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_Frame_ID_Type idType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId));\n+ CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType));\n+\n+ if (camId < DSP2_MISC_CAM_4_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1);\n+ tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal);\n+ } else {\n+ camId -= 4;\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2);\n+ tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Frame id init\n+ *\n+ * @param idType: Frame id type\n+ * @param edgeType: Frame id edge type\n+ * @param vsyncCnt: Vsync count to trigger id increment\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Frame_ID_Init(DSP2_MISC_Frame_ID_Type idType, DSP2_MISC_Frame_ID_Edge_Type edgeType, uint16_t vsyncCnt)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType));\n+ CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_EDGE_TYPE(edgeType));\n+\n+ if (idType == DSP2_MISC_FRAME_BAYER_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_EDGE, edgeType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR, vsyncCnt);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_EDGE, edgeType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_CNT_INCR, vsyncCnt);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Reset frame id\n+ *\n+ * @param idType: Frame id type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Frame_ID_Reset(DSP2_MISC_Frame_ID_Type idType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType));\n+\n+ if (idType == DSP2_MISC_FRAME_BAYER_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_RST));\n+ } else {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_YUV_IDGEN_RST));\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief OSD input selection\n+ *\n+ * @param osdId: OSD id\n+ * @param inputType: OSD input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_OSD_Input_Select(DSP2_MISC_OSD_ID_Type osdId, DSP2_MISC_OSD_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t osdAddr = DSP2_MISC_BASE + DSP2_MISC_OSDA_I_CTRL_OFFSET + 4 * osdId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_OSD_ID_TYPE(osdId));\n+ CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType));\n+\n+ tmpVal = BL_RD_WORD(osdAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDA_SEL, inputType);\n+ BL_WR_WORD(osdAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief OSD probe input selection\n+ *\n+ * @param inputType: OSD input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_OSD_Probe_Input_Select(DSP2_MISC_OSD_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType));\n+\n+ if (inputType > DSP2_MISC_OSD_DSP2_INPUT) {\n+ return;\n+ }\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_SEL, inputType);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Crop init\n+ *\n+ * @param cropId: Crop id\n+ * @param cropCfg: Crop configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Crop_Init(DSP2_MISC_Crop_ID_Type cropId, DSP2_MISC_Crop_Cfg_Type *cropCfg)\n+{\n+ uint32_t cropAddr = DSP2_MISC_BASE + DSP2_MISC_CROPA_HSYNC_OFFSET + 8 * cropId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId));\n+\n+ BL_WR_WORD(cropAddr, cropCfg->hsyncEnd << 16 | cropCfg->hsyncStart);\n+ cropAddr += 4;\n+ BL_WR_WORD(cropAddr, cropCfg->vsyncEnd << 16 | cropCfg->vsyncStart);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Crop enable\n+ *\n+ * @param cropId: Crop id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Crop_Enable(DSP2_MISC_Crop_ID_Type cropId)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE);\n+\n+ switch (cropId) {\n+ case DSP2_MISC_CROP_0_ID:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_1_ID:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_2_ID:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_3_ID:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Crop disable\n+ *\n+ * @param cropId: Crop id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Crop_Disable(DSP2_MISC_Crop_ID_Type cropId)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE);\n+\n+ switch (cropId) {\n+ case DSP2_MISC_CROP_0_ID:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_1_ID:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_2_ID:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE);\n+ break;\n+\n+ case DSP2_MISC_CROP_3_ID:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Scaler input selection\n+ *\n+ * @param scalerId: Scaler id\n+ * @param inputType: Scaler input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Scaler_Input_Select(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_INPUT_TYPE(inputType));\n+\n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_SEL, inputType);\n+ BL_WR_WORD(scalerAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Scaler init\n+ *\n+ * @param scalerId: Scaler id\n+ * @param scalerCfg: Scaler configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Scaler_Init(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Cfg_Type *scalerCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));\n+\n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_W, scalerCfg->inputWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_H, scalerCfg->inputHeight & 0x7ff);\n+ BL_WR_WORD(scalerAddr, tmpVal);\n+\n+ scalerAddr += 4;\n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_W, scalerCfg->outputWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_H, scalerCfg->outputHeight);\n+ BL_WR_WORD(scalerAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Scaler enable\n+ *\n+ * @param scalerId: Scaler id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Scaler_Enable(DSP2_MISC_Scaler_ID_Type scalerId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));\n+\n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS);\n+ BL_WR_WORD(scalerAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Scaler disable\n+ *\n+ * @param scalerId: Scaler id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Scaler_Disable(DSP2_MISC_Scaler_ID_Type scalerId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));\n+\n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS);\n+ BL_WR_WORD(scalerAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Adjust input selection\n+ *\n+ * @param adjustId: Adjust id\n+ * @param inputType: Adjust input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId));\n+ \n+ tmpVal = BL_RD_WORD(scalerAddr);\n+ BL_WR_WORD(scalerAddr, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCLRA_SW_SH));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Adjust input selection\n+ *\n+ * @param adjustId: Adjust id\n+ * @param inputType: Adjust input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Adjust_Input_Select(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_2_OFFSET + 16 * adjustId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId));\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_INPUT_TYPE(inputType));\n+\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_ADJA_SEL, inputType);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Adjust init\n+ *\n+ * @param adjustId: Adjust id\n+ * @param adjustCfg: Adjust configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Adjust_Init(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Cfg_Type *adjustCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId));\n+\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_LUMA, adjustCfg->yLuma);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL0, adjustCfg->yMul0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL1, adjustCfg->yMul1);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+\n+ adjustAddr += 4;\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MIN, adjustCfg->yMin);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MAX, adjustCfg->yMax);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MIN, adjustCfg->uvMin);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MAX, adjustCfg->uvMax);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+\n+ adjustAddr += 4;\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL0, adjustCfg->uvMul0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL1, adjustCfg->uvMul1);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Adjust enable\n+ *\n+ * @param adjustId: Adjust id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Adjust_Enable(DSP2_MISC_Adjust_ID_Type adjustId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId));\n+\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Adjust disable\n+ *\n+ * @param adjustId: Adjust id\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Adjust_Disable(DSP2_MISC_Adjust_ID_Type adjustId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId));\n+\n+ tmpVal = BL_RD_WORD(adjustAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB);\n+ BL_WR_WORD(adjustAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Display init\n+ *\n+ * @param displayCfg: Display configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Display_Init(DSP2_MISC_Display_Cfg_Type *displayCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId));\n+ CHECK_PARAM(IS_DSP2_MISC_DISPLAY_OSD_INPUT_TYPE(displayCfg->osdType));\n+ CHECK_PARAM(IS_DSP2_MISC_DISPLAY_INPUT_TYPE(displayCfg->inputType));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_MUX_SEL, displayCfg->inputType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDDP_SEL, displayCfg->osdType);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal);\n+\n+ if (displayCfg->dpiEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN);\n+ } else if (displayCfg->hdmiEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN);\n+ } else if (displayCfg->bt1120Enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN);\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HS_W, displayCfg->hsyncWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HFP_W, displayCfg->hfpWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VS_W, displayCfg->vsyncWidth);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VFP_W, displayCfg->vfpWidth);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Display gamma init\n+ *\n+ * @param gammaCfg: Display gamma configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Display_Gamma_Init(DSP2_MISC_Display_Gamma_Cfg_Type *gammaCfg)\n+{\n+ uint32_t tmpVal, i, j;\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH0_EN, gammaCfg->ch0Enable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH1_EN, gammaCfg->ch1Enable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH2_EN, gammaCfg->ch2Enable);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG, tmpVal);\n+\n+ if (gammaCfg->gammaCurve == NULL) {\n+ return;\n+ }\n+\n+ for (i = 0; i < 64; i++) {\n+ tmpVal = 0;\n+\n+ for (j = 0; j < 4; j++) {\n+ tmpVal |= gammaCfg->gammaCurve[j + 4 * i] << (8 * j);\n+ }\n+\n+ BL_WR_WORD(DSP2_MISC_BASE + DSP2_MISC_DISP_GMA_CURVE_00_OFFSET + 4 * i, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief YUV2RGB input selection\n+ *\n+ * @param inputType: YUV2RGB input type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_YUV2RGB_Input_Select(DSP2_MISC_YUV2RGB_Input_Type inputType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_INPUT_TYPE(inputType));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_SEL, inputType);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief YUV2RGB init\n+ *\n+ * @param yuv2rgbId: YUV2RGB ID type\n+ * @param yuv2rgbCfg: YUV2RGB configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_YUV2RGB_Init(DSP2_MISC_YUV2RGB_ID_Type yuv2rgbId, DSP2_MISC_YUV2RGB_Cfg_Type *yuv2rgbCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_ID_TYPE(yuv2rgbId));\n+\n+ if (yuv2rgbId == DSP2_MISC_YUV2RGB_DISPLAY_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_0, yuv2rgbCfg->preOffset0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_1, yuv2rgbCfg->preOffset1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_2, yuv2rgbCfg->preOffset2);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_0, yuv2rgbCfg->postOffset0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_1, yuv2rgbCfg->postOffset1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_2, yuv2rgbCfg->postOffset2);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_00, yuv2rgbCfg->matrix00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_01, yuv2rgbCfg->matrix01);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_L, yuv2rgbCfg->matrix02);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_U, yuv2rgbCfg->matrix02 >> 8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_10, yuv2rgbCfg->matrix10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_11, yuv2rgbCfg->matrix11);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_L, yuv2rgbCfg->matrix12);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_U, yuv2rgbCfg->matrix12 >> 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_20, yuv2rgbCfg->matrix20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_21, yuv2rgbCfg->matrix21);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_22, yuv2rgbCfg->matrix22);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5, tmpVal);\n+\n+ /* Enable or disable function */\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_EN, yuv2rgbCfg->enable));\n+\n+ } else if (yuv2rgbId == DSP2_MISC_YUV2RGB_NORMAL_ID) {\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_0, yuv2rgbCfg->preOffset0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_0, yuv2rgbCfg->postOffset0);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_1, yuv2rgbCfg->preOffset1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_1, yuv2rgbCfg->postOffset1);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_2, yuv2rgbCfg->preOffset2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_2, yuv2rgbCfg->postOffset2);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_00, yuv2rgbCfg->matrix00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_01, yuv2rgbCfg->matrix01);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_02, yuv2rgbCfg->matrix02);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_10, yuv2rgbCfg->matrix10);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_11, yuv2rgbCfg->matrix11);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_12, yuv2rgbCfg->matrix12);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_20, yuv2rgbCfg->matrix20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_21, yuv2rgbCfg->matrix21);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_22, yuv2rgbCfg->matrix22);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_EN, yuv2rgbCfg->enable));\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief RGB2YUV init\n+ *\n+ * @param rgb2yuvCfg: YUV2RGB configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_RGB2YUV_Init(DSP2_MISC_YUV2RGB_Cfg_Type *rgb2yuvCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_0, rgb2yuvCfg->preOffset0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_1, rgb2yuvCfg->preOffset1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_2, rgb2yuvCfg->preOffset2);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_0, rgb2yuvCfg->postOffset0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_1, rgb2yuvCfg->postOffset1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_2, rgb2yuvCfg->postOffset2);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_00, rgb2yuvCfg->matrix00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_01, rgb2yuvCfg->matrix01);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_L, rgb2yuvCfg->matrix02);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_U, rgb2yuvCfg->matrix02 >> 8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_10, rgb2yuvCfg->matrix10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_11, rgb2yuvCfg->matrix11);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_L, rgb2yuvCfg->matrix12);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_U, rgb2yuvCfg->matrix12 >> 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_20, rgb2yuvCfg->matrix20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_21, rgb2yuvCfg->matrix21);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_22, rgb2yuvCfg->matrix22);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_EN, rgb2yuvCfg->enable));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear certain or all of the interrupt\n+ *\n+ * @param intType: Interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Int_Clear(DSP2_MISC_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case DSP2_MISC_INT_AWB0:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_AE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_WDR:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_WDR_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB1:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB2_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_OSD_PB:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_OSD_PB_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF0:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF1_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF1:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF2_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF2:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF3_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_AE_HIST:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_HIST_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB2:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB3_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_DISPLAY:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF3:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF4_INT_CLR);\n+ break;\n+\n+ case DSP2_MISC_INT_ALL:\n+ tmpVal = 0x7f1f;\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CLR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask certain or all of the interrupt\n+ *\n+ * @param intType: Interrupt type\n+ * @param intMask: Mask or unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Int_Mask(DSP2_MISC_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL);\n+\n+ switch (intType) {\n+ case DSP2_MISC_INT_AWB0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_AE:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_WDR:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_WDR_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB2_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_OSD_PB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_AE_HIST:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_HIST_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB3_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_DISPLAY:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_MASK, intMask);\n+ break;\n+\n+ case DSP2_MISC_INT_ALL:\n+ if (intMask == MASK) {\n+ tmpVal |= 0x1131111f;\n+ } else {\n+ tmpVal &= ~0x1131111f;\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install dsp2 misc interrupt callback function\n+ *\n+ * @param intType: DSP2 misc interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void DSP2_MISC_Int_Callback_Install(DSP2_MISC_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType));\n+\n+ switch (intType) {\n+#if defined(CPU_D0)\n+\n+ case DSP2_MISC_INT_AWB0:\n+ Interrupt_Handler_Register(DSP2_AWB0_IRQn, AWB0_IRQHandler);\n+ break;\n+#endif\n+\n+ case DSP2_MISC_INT_AE:\n+ Interrupt_Handler_Register(DSP2_AE_IRQn, AE_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_WDR:\n+ Interrupt_Handler_Register(DSP2_WDR_IRQn, WDR_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB1:\n+ Interrupt_Handler_Register(DSP2_AWB1_IRQn, AWB1_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_OSD_PB:\n+ Interrupt_Handler_Register(OSD_PB_IRQn, OSD_PB_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF0:\n+ Interrupt_Handler_Register(SEOF_INT0_IRQn, SEOF0_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF1:\n+ Interrupt_Handler_Register(SEOF_INT1_IRQn, SEOF1_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF2:\n+ Interrupt_Handler_Register(SEOF_INT2_IRQn, SEOF2_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_AE_HIST:\n+ Interrupt_Handler_Register(DSP2_AE_HIST_IRQn, AE_HIST_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_AWB2:\n+ Interrupt_Handler_Register(DSP2_AWB2_IRQn, AWB2_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_DISPLAY:\n+ Interrupt_Handler_Register(DISPLAY_IRQn, Display_IRQHandler);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF3:\n+ Interrupt_Handler_Register(SEOF_INT3_IRQn, SEOF3_IRQHandler);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ dsp2MiscIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Select SEOF interrupt vsync source\n+ *\n+ * @param intType: SEOF interrupt type\n+ * @param source: SEOF interrupt vsync source type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_SEOF_Set_Source(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Source_Type source)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(source));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL);\n+\n+ switch (intType) {\n+ case DSP2_MISC_INT_SEOF0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_SRC, source);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_SRC, source);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_SRC, source);\n+ break;\n+\n+ case DSP2_MISC_INT_DISPLAY:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_SRC, source & 0x1);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_SRC, source);\n+ break;\n+\n+ default:\n+ return;\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select SEOF interrupt vsync source\n+ *\n+ * @param intType: SEOF interrupt type\n+ * @param edge: SEOF interrupt edge type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Type edge)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL);\n+\n+ switch (intType) {\n+ case DSP2_MISC_INT_SEOF0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_EDGE, edge);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_EDGE, edge);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_EDGE, edge);\n+ break;\n+\n+ case DSP2_MISC_INT_DISPLAY:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_EDGE, edge);\n+ break;\n+\n+ case DSP2_MISC_INT_SEOF3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_EDGE, edge);\n+ break;\n+\n+ default:\n+ return;\n+ break;\n+ }\n+\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Reshape init\n+ *\n+ * @param reshapeCfg: Reshape configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg)\n+{\n+ uint32_t tmpVal;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->hSyncLevel));\n+ CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->vSyncLevel));\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_TGL_COUNT, reshapeCfg->vsyncNumber & 0x1f);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_HSYNC_INV, reshapeCfg->hSyncLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_VSYNC_INV, reshapeCfg->vSyncLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_EN, reshapeCfg->enable);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear vsync toggle counter\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Reshape_Counter_Clear(void)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_RSHP_CLR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable or disable use DE as hsync for DSP2\n+ *\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_DSP2_DE_AS_HSYNC, enable);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DVP TSRC data source\n+ *\n+ * @param sourceType: DVP or CSI\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DSP2_DTSRC_SRC, sourceType);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Configure bayer data shift function\n+ *\n+ * @param bitEnable: Enable bits used\n+ * @param shiftType: Set shift direction\n+ * @param bitShift: Set Shift bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_Bayer_Shift(uint16_t bitEnable, DSP2_MISC_Bayer_Shift_Type shiftType, uint8_t bitShift)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DSP2_MISC_BAYER_SHIFT_TYPE(shiftType));\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_CTRL, bitEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_BIT, bitShift);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_DIR, shiftType);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Reduce m frames to n frames function enable\n+ *\n+ * @param m: Total frame count\n+ * @param n: Enabled frame count\n+ * @param step: Step between enabled frames\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_M2N_Enable(uint8_t m, uint8_t n, uint8_t step)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_INTERVAL, step);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_N, n);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_M, m);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Reduce m frames to n frames function disable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DSP2_MISC_M2N_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N);\n+ BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SEOF0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEOF0_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF0);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SEOF1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEOF1_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF1);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SEOF2 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEOF2_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF2);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SEOF3 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEOF3_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF3);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AWB0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AWB0_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB0);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AWB1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AWB1_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB1);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AWB2 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AWB2_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB2);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AE interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AE_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_AE]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief AE HIST interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void AE_HIST_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE_HIST);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief WDR interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void WDR_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_WDR);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief OSD PB interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void OSD_PB_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_OSD_PB);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Display interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void Display_IRQHandler(void)\n+{\n+ DSP2_MISC_Int_Clear(DSP2_MISC_INT_DISPLAY);\n+\n+ if (dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY] != NULL) {\n+ dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY]();\n+ }\n+}\n+#endif\n+\n+/*@} end of group DSP2_MISC_Public_Functions */\n+\n+/*@} end of group DSP2_MISC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..92324196fe216e2e6493ea7baaabe71936387c10\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c\n@@ -0,0 +1,557 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dsp2_wdr.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dsp2_wdr.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DSP2_WDR\n+ * @{\n+ */\n+\n+/** @defgroup DSP2_WDR_Private_Macros\n+ * @{\n+ */\n+#define DSP2_WDR_ROI_WEIGHT_MAX (15)\n+#define DSP2_WDR_CURVE_WEIGHT_MAX (2 << 8)\n+#define DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX ((2 << 12) - 1)\n+#define DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX ((2 << 15) - 1)\n+#define DSP2_WDR_POST_ENHANCE_C_GAIN_MAX ((2 << 15) - 1)\n+\n+/*@} end of group DSP2_WDR_Private_Macros */\n+\n+/** @defgroup DSP2_WDR_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_WDR_Private_Types */\n+\n+/** @defgroup DSP2_WDR_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_WDR_Private_Variables */\n+\n+/** @defgroup DSP2_WDR_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_WDR_Global_Variables */\n+\n+/** @defgroup DSP2_WDR_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_WDR_Private_Fun_Declaration */\n+\n+/** @defgroup DSP2_WDR_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DSP2_WDR_Private_Functions */\n+\n+/** @defgroup DSP2_WDR_Public_Functions\n+ * @{\n+ */\n+\n+void DSP2_WDR_Get_WDR_State(BL_Fun_Type *state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_WDR_EN_PRE)) {\n+ *state = ENABLE;\n+ } else {\n+ *state = DISABLE;\n+ }\n+}\n+\n+void DSP2_WDR_Set_WDR_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal);\n+}\n+\n+void DSP2_WDR_Set_CS_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal);\n+}\n+\n+void DSP2_WDR_Set_CS_Config(const DSP2_Chroma_Suppress_Type *chromaSupprCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE, chromaSupprCfg->gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE, chromaSupprCfg->weight);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE, chromaSupprCfg->gain_thresh);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_CS_Config(DSP2_Chroma_Suppress_Type *chromaSupprCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0);\n+ chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0);\n+ chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE);\n+ chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE);\n+}\n+\n+void DSP2_WDR_Set_ROI_State(int roi_id, BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ switch (roi_id) {\n+ case 0:\n+ case 1:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_EN_PRE, state);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_EN_PRE, state);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal);\n+ break;\n+\n+ case 2:\n+ case 3:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_EN_PRE, state);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_EN_PRE, state);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal);\n+ break;\n+\n+ case 4:\n+ case 5:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_EN_PRE, state);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_EN_PRE, state);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal);\n+ break;\n+\n+ case 6:\n+ case 7:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_EN_PRE, state);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_EN_PRE, state);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+void DSP2_WDR_Set_ROI_Position(int roi_id, uint32_t left_x, uint32_t right_x,\n+ uint32_t top_y, uint32_t bottom_y)\n+{\n+ uint32_t tmpVal;\n+\n+ switch (roi_id) {\n+ case 0:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6, tmpVal);\n+ break;\n+\n+ case 1:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8, tmpVal);\n+ break;\n+\n+ case 2:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10, tmpVal);\n+ break;\n+\n+ case 3:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12, tmpVal);\n+ break;\n+\n+ case 4:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14, tmpVal);\n+ break;\n+\n+ case 5:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16, tmpVal);\n+ break;\n+\n+ case 6:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18, tmpVal);\n+ break;\n+\n+ case 7:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MIN_PRE, left_x);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MAX_PRE, right_x);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19, tmpVal);\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MIN_PRE, top_y);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MAX_PRE, bottom_y);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20, tmpVal);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+void DSP2_WDR_Set_ROI_Weight(int roi_id, uint32_t weight)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(weight, DSP2_WDR_ROI_WEIGHT_MAX);\n+\n+ switch (roi_id) {\n+ case 0:\n+ case 1:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE, weight);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE, weight);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal);\n+ break;\n+\n+ case 2:\n+ case 3:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE, weight);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE, weight);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal);\n+ break;\n+\n+ case 4:\n+ case 5:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE, weight);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE, weight);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal);\n+ break;\n+\n+ case 6:\n+ case 7:\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4);\n+\n+ if (roi_id & 0x01) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE, weight);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE, weight);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+int DSP2_WDR_Get_Hist_Data(DSP2_WDR_Hist_Data_Type *hist)\n+{\n+ uint32_t tmpVal;\n+ uint32_t buf_idx;\n+ uint32_t buf_addr;\n+ uint32_t w_cnt_idx_start;\n+ uint32_t w_cnt_idx_end;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0);\n+ buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_BUF_IDX_R);\n+ w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R);\n+\n+ if (0 == buf_idx) {\n+ buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST0_0_OFFSET;\n+ hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST0_64);\n+ } else {\n+ buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST1_0_OFFSET;\n+ hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST1_64);\n+ }\n+\n+ /* copy all the histogram bin except for the last one */\n+ ARCH_MemCpy4(&hist->hist_bin[0], (uint32_t *)(uintptr_t)buf_addr, 64);\n+\n+ w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R);\n+\n+ if (w_cnt_idx_start != w_cnt_idx_end) {\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+void DSP2_WDR_Set_WDR_Curve_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal);\n+}\n+\n+void DSP2_WDR_Set_WDR_Curve(const DSP2_WDR_Curve_Type *wdr_curve)\n+{\n+ ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), (uint32_t *)&wdr_curve->curve_coef[0], DSP2_WDR_CURVE_COEF_NUM / 2);\n+}\n+\n+void DSP2_WDR_Get_WDR_Curve(DSP2_WDR_Curve_Type *wdr_curve)\n+{\n+ ARCH_MemCpy4((uint32_t *)&wdr_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), DSP2_WDR_CURVE_COEF_NUM / 2);\n+}\n+\n+void DSP2_WDR_Set_WDR_Curve_Weight(uint32_t weight)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE, weight);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_WDR_Curve_Weight(uint32_t *weight)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33);\n+ *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE);\n+}\n+\n+void DSP2_WDR_Set_Post_Enhance_State(BL_Fun_Type state)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1);\n+\n+ if (ENABLE == state) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE);\n+ }\n+\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal);\n+}\n+\n+void DSP2_WDR_Set_Post_Enhance_Weight(uint32_t weight)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE, weight);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_Post_Enhance_Weight(uint32_t *weight)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1);\n+ *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE);\n+}\n+\n+void DSP2_WDR_Set_Post_Enhance_Y_Offset(uint32_t y_offset)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(y_offset, DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE, y_offset);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_Post_Enhance_Y_Offset(uint32_t *y_offset)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1);\n+ *y_offset = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE);\n+}\n+\n+void DSP2_WDR_Set_Post_Enhance_Luma_Gain(uint32_t gain)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE, gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_Post_Enhance_Luma_Gain(uint32_t *gain)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2);\n+ *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE);\n+}\n+\n+void DSP2_WDR_Set_Post_Enhance_Chroma_Gain(uint32_t gain)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_C_GAIN_MAX);\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE, gain);\n+ BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal);\n+}\n+\n+void DSP2_WDR_Get_Post_Enhance_Chroma_Gain(uint32_t *gain)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2);\n+ *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE);\n+}\n+\n+/*@} end of group DSP2_WDR_Public_Functions */\n+\n+/*@} end of group DSP2_WDR */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1be3c39d98f266a784ea9a92736fee7ba16491f6\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c\n@@ -0,0 +1,394 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_dvp_tsrc.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_dvp_tsrc.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup DVP_TSRC\n+ * @{\n+ */\n+\n+/** @defgroup DVP_TSRC_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group DVP_TSRC_Private_Macros */\n+\n+/** @defgroup DVP_TSRC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group DVP_TSRC_Private_Types */\n+\n+/** @defgroup DVP_TSRC_Private_Variables\n+ * @{\n+ */\n+static const uint32_t dvpTsrcAddr[DVP_TSRC_ID_MAX] = { DVP_TSRC0_BASE, DVP_TSRC1_BASE };\n+\n+/*@} end of group DVP_TSRC_Private_Variables */\n+\n+/** @defgroup DVP_TSRC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group DVP_TSRC_Global_Variables */\n+\n+/** @defgroup DVP_TSRC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group DVP_TSRC_Private_Fun_Declaration */\n+\n+/** @defgroup DVP_TSRC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group DVP_TSRC_Private_Functions */\n+\n+/** @defgroup DVP_TSRC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief DVP_TSRC init\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ * @param dvpTsrcCfg: DVP_TSRC configuration\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type DVP_TSRC_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Cfg_Type *dvpTsrcCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+ CHECK_PARAM(IS_DVP_TSRC_PIXEL_FORMAT_TYPE(dvpTsrcCfg->format));\n+ CHECK_PARAM(IS_DVP_TSRC_DVP2AXI_TYPE(dvpTsrcCfg->dvp2axi));\n+ CHECK_PARAM(IS_DVP_TSRC_SWAP_CONTROL_TYPE(dvpTsrcCfg->swapControl));\n+ CHECK_PARAM(IS_DVP_TSRC_BURST_TYPE(dvpTsrcCfg->burst));\n+ CHECK_PARAM(IS_DVP_TSRC_YUV420_LINE_TYPE(dvpTsrcCfg->lineType));\n+\n+ /* Enable using AXI data */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_MODE, dvpTsrcCfg->swapMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWM, dvpTsrcCfg->swapControl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SEL, dvpTsrcCfg->dvp2axi);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_DVP_DATA_MODE, dvpTsrcCfg->format);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_EN, dvpTsrcCfg->dataFromSensor);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, dvpTsrcCfg->sensorHsyncInverse);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, dvpTsrcCfg->sensorVsyncInverse);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B0_SEL, dvpTsrcCfg->byte0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B1_SEL, dvpTsrcCfg->byte1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B2_SEL, dvpTsrcCfg->byte2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_EN);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal);\n+\n+ /* Set burst length */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_MODE, dvpTsrcCfg->yuv420Enable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_UD_SEL, dvpTsrcCfg->lineType);\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_XLEN, dvpTsrcCfg->burst));\n+\n+ /* Set horizontal pixel count */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_H, dvpTsrcCfg->hTotalCnt);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_H, dvpTsrcCfg->hBlankCnt);\n+ BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H, tmpVal);\n+\n+ /* Set vertical pixel count */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_V, dvpTsrcCfg->vTotalCnt);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_V, dvpTsrcCfg->vBlankCnt);\n+ BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V, tmpVal);\n+\n+ /* Set vertical prefetch start position */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH);\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_PREFETCH_V, dvpTsrcCfg->prefetch));\n+\n+ /* Set fifo threshold for each DVP line to start to output */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS);\n+ BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, dvpTsrcCfg->fifoThreshold));\n+\n+ /* Set axi2dvp start address, Y planar in YUV420 mode, frame 0 in swap mode */\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_BY, dvpTsrcCfg->memStartY0);\n+\n+ /* Set axi2dvp memory size in burst */\n+ switch (dvpTsrcCfg->burst) {\n+ case DVP_TSRC_BURST_TYPE_SINGLE:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 8;\n+ break;\n+\n+ case DVP_TSRC_BURST_TYPE_INCR4:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 32;\n+ break;\n+\n+ case DVP_TSRC_BURST_TYPE_INCR8:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 64;\n+ break;\n+\n+ case DVP_TSRC_BURST_TYPE_INCR16:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 128;\n+ break;\n+\n+ case DVP_TSRC_BURST_TYPE_INCR32:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 256;\n+ break;\n+\n+ case DVP_TSRC_BURST_TYPE_INCR64:\n+ tmpVal = dvpTsrcCfg->memSizeY0 / 512;\n+ break;\n+\n+ default:\n+ tmpVal = 0;\n+ break;\n+ }\n+\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_BURST_CNT, tmpVal);\n+\n+ /* Set axi2dvp start address, Y planar in YUV420 mode, frame 1 in swap mode */\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_BY, dvpTsrcCfg->memStartY1);\n+\n+ /* Set axi2dvp start address, UV planar in YUV420 mode, frame 0 in swap mode */\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_UV, dvpTsrcCfg->memStartUV0);\n+\n+ /* Set axi2dvp start address, UV planar in YUV420 mode, frame 1 in swap mode */\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_UV, dvpTsrcCfg->memStartUV1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Use fake gradient data function init\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ * @param dataCfg: Fake gradient data configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Fake_Data_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Fake_Data_Cfg_Type *dataCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ /* Enable using fake gradient data */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_AXI_EN));\n+\n+ /* Set min and max value of fake gradient data */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MIN, dataCfg->minData);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MAX, dataCfg->maxData);\n+ BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE, tmpVal);\n+\n+ /* Set step value for eack line of fake gradient data */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_STEP, dataCfg->step);\n+ BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CEA-861 mode init\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ * @param ceaCfg: CEA-861 configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_CEA861_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_CEA861_Cfg_Type *ceaCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_PLACEMENT, ceaCfg->hsyncStart);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_DURATION, ceaCfg->hsyncEnd);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_PLACEMENT, ceaCfg->vsyncStart);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_DURATION, ceaCfg->vsyncEnd);\n+ BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sensor input configuration\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ * @param threshold: FIFO threshold for each DVP line to start to output\n+ * @param hsyncInv:Enable or disable inverse signal of sensor hsync\n+ * @param vsyncInv:Enable or disable inverse signal of sensor vsync\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Sensor_Input_Set(DVP_TSRC_ID_Type tsrcId, uint16_t threshold, BL_Fun_Type hsyncInv, BL_Fun_Type vsyncInv)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_SNSR_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, hsyncInv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, vsyncInv);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal);\n+\n+ /* Set fifo threshold for each DVP line to start to output */\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS);\n+ BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, threshold));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DVP_TSRC enable\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Enable(DVP_TSRC_ID_Type tsrcId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_ENABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DVP_TSRC disable\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Disable(DVP_TSRC_ID_Type tsrcId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_ENABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DVP_TSRC set swap index in software mode\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ * @param index: Swap index used\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Set_Swap_Index(DVP_TSRC_ID_Type tsrcId, uint8_t index)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG);\n+ BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWV, index));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AXI2DVP clear drain error function\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void DVP_TSRC_Clear_Drain_Error(DVP_TSRC_ID_Type tsrcId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING);\n+ BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_DRAIN_ERR_CLR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get AXI2DVP status function\n+ *\n+ * @param tsrcId: DVP_TSRC ID type\n+ *\n+ * @return Status\n+ *\n+*******************************************************************************/\n+uint32_t DVP_TSRC_Get_Status(DVP_TSRC_ID_Type tsrcId)\n+{\n+ uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId));\n+\n+ return (BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_STATUS));\n+}\n+\n+/*@} end of group DVP_TSRC_Public_Functions */\n+\n+/*@} end of group DVP_TSRC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..05c3efc134aa9eb846ba68b50bd46aa4157bcd64\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c\n@@ -0,0 +1,610 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_ef_cfg.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_ef_ctrl.h\"\n+#include \"bl808_ef_cfg.h\"\n+#include \"ef_data_0_reg.h\"\n+#include \"ef_data_1_reg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_EF_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Macros\n+ * @{\n+ */\n+#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0()\n+#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1()\n+\n+/*@} end of group SEC_EF_CTRL_Private_Macros */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Types */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Variables */\n+\n+/** @defgroup SEC_EF_CTRL_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Global_Variables */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse get zero bit count\n+ *\n+ * @param val: Value to count\n+ *\n+ * @return Zero bit count\n+ *\n+*******************************************************************************/\n+static uint32_t EF_Cfg_Get_Byte_Zero_Cnt(uint8_t val)\n+{\n+ uint32_t cnt = 0;\n+ uint32_t i = 0;\n+\n+ for (i = 0; i < 8; i++) {\n+ if ((val & (1 << i)) == 0) {\n+ cnt += 1;\n+ }\n+ }\n+\n+ return cnt;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse get chip info\n+ *\n+ * @param chipInfo: info pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);\n+ chipInfo->chipInfo = (tmpVal>>29)&0x7;\n+ chipInfo->memoryInfo = (tmpVal>>27)&0x3;\n+ chipInfo->psramInfo = (tmpVal>>25)&0x3;\n+ chipInfo->deviceInfo = (tmpVal>>22)&0x7;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+ chipInfo->psramInfo |= ((tmpVal>>20)&0x1) << 2;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read xtal trim rc32m configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);\n+ trim->trimLDO15RFVoutAon = (tmpVal >> 27) & 0x07;\n+ trim->trimLDO15RFVoutAonParity = (tmpVal >> 30) & 0x01;\n+ trim->trimLDO15RFVoutAonEn = (tmpVal >> 31) & 0x01;\n+}\n+\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read rcal iptat code configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);\n+ trim->trimRcalIptatCode = (tmpVal >> 22) & 0x1f;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);\n+ trim->trimRcalIptatCodeParity = (tmpVal >> 30) & 0x01;\n+ trim->trimRcalIptatCodeEn = (tmpVal >> 31) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read rcal icx code configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);\n+ trim->trimRcalIcxCode = (tmpVal >> 22) & 0x3f;\n+ trim->trimRcalIcxCodeParity = (tmpVal >> 28) & 0x01;\n+ trim->trimRcalIcxCodeEn = (tmpVal >> 29) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read LDO28CIS vout trim configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimLDO28CISVout = (tmpVal >> 8) & 0xf;\n+ trim->trimLDO28CISVoutParity = (tmpVal >> 12) & 0x01;\n+ trim->trimLDO28CISVoutEn = (tmpVal >> 13) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read LDO15CIS vout trim configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimLDO15CISVout = (tmpVal >> 8) & 0xf;\n+ trim->trimLDO15CISVoutParity = (tmpVal >> 12) & 0x01;\n+ trim->trimLDO15CISVoutEn = (tmpVal >> 13) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read LDO12UHS vout trim configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);\n+ trim->trimLDO12UHSVout = (tmpVal >> 20) & 0xf;\n+ trim->trimLDO12UHSVoutParity = (tmpVal >> 24) & 0x01;\n+ trim->trimLDO12UHSVoutEn = (tmpVal >> 25) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read xtal capcode 1 inout configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);\n+ trim->trimXtalCapcode1 = (tmpVal >> 0) & 0x3f;\n+ trim->trimXtalCapcode1Parity = (tmpVal >> 6) & 0x01;\n+ trim->trimXtalCapcode1En = (tmpVal >> 7) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read xtal capcode 2 inout configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);\n+ trim->trimXtalCapcode2 = (tmpVal >> 26) & 0x3f;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0);\n+ trim->trimXtalCapcode2Parity = (tmpVal >> 30) & 0x01;\n+ trim->trimXtalCapcode2En = (tmpVal >> 31) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read xtal capcode 3 inout configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);\n+ trim->trimXtalCapcode3 = (tmpVal >> 20) & 0x3f;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0);\n+ trim->trimXtalCapcode3Parity = (tmpVal >> 28) & 0x01;\n+ trim->trimXtalCapcode3En = (tmpVal >> 29) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read gauge vpack offset configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);\n+ trim->trimGaugeVpackOffset = (tmpVal >> 2) & 0xffff;\n+ trim->trimGaugeVpackOffsetParity = (tmpVal >> 18) & 0x01;\n+ trim->trimGaugeVpackOffsetEn = (tmpVal >> 19) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read gauge vtemp offset configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2);\n+ trim->trimGaugeVtempOffset = (tmpVal >> 16) & 0xffff;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);\n+ trim->trimGaugeVtempOffsetParity = (tmpVal >> 0) & 0x01;\n+ trim->trimGaugeVtempOffsetEn = (tmpVal >> 1) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read psram trim configuration\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2);\n+ trim->psramTrim = (tmpVal >> 0) & 0x7ff;\n+ trim->psramTrimParity = (tmpVal >> 11) & 0x01;\n+ trim->psramTrimEn = (tmpVal >> 12) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write psram trim configuration\n+ *\n+ * @param trim: Trim data pointer\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2);\n+ tmpVal |= (trim->psramTrim<<0);\n+ tmpVal |= (trim->psramTrimParity<<11);\n+ tmpVal |= (trim->psramTrimEn<<12);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_1();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Whether MAC address slot is empty\n+ *\n+ * @param slot: MAC address slot\n+ * @param reload: whether reload to check\n+ *\n+ * @return 0 for all slots full,1 for others\n+ *\n+*******************************************************************************/\n+uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)\n+{\n+ uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;\n+ uint32_t part1Empty = 0, part2Empty = 0;\n+\n+ if (slot == 0) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ if (reload) {\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+ }\n+\n+ tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);\n+ tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);\n+ } else if (slot == 1) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ if (reload) {\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+ }\n+\n+ tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2);\n+ tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);\n+ } else if (slot == 2) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ if (reload) {\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+ }\n+\n+ tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1);\n+ tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);\n+ }\n+\n+ part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32));\n+ part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22));\n+\n+ return (part1Empty && part2Empty);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write optional MAC address\n+ *\n+ * @param slot: MAC address slot\n+ * @param mac[6]: MAC address buffer\n+ * @param program: Whether program\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program)\n+{\n+ uint8_t *maclow = (uint8_t *)mac;\n+ uint8_t *machigh = (uint8_t *)(mac + 4);\n+ uint32_t tmpVal;\n+ uint32_t i = 0, cnt;\n+\n+ if (slot >= 3) {\n+ return ERROR;\n+ }\n+\n+ /* Change to local order */\n+ for (i = 0; i < 3; i++) {\n+ tmpVal = mac[i];\n+ mac[i] = mac[5 - i];\n+ mac[5 - i] = tmpVal;\n+ }\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ /* The low 32 bits */\n+ if (slot == 0) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));\n+ } else if (slot == 1) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, BL_RDWD_FRM_BYTEP(maclow));\n+ } else if (slot == 2) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1, BL_RDWD_FRM_BYTEP(maclow));\n+ }\n+\n+ /* The high 16 bits */\n+ tmpVal = machigh[0] + (machigh[1] << 8);\n+ cnt = 0;\n+\n+ for (i = 0; i < 6; i++) {\n+ cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]);\n+ }\n+\n+ tmpVal |= ((cnt & 0x3f) << 16);\n+\n+ if (slot == 0) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);\n+ } else if (slot == 1) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, tmpVal);\n+ } else if (slot == 2) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2, tmpVal);\n+ }\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read optional MAC address\n+ *\n+ * @param slot: MAC address slot\n+ * @param mac[6]: MAC address buffer\n+ * @param reload: Whether reload\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload)\n+{\n+ uint8_t *maclow = (uint8_t *)mac;\n+ uint8_t *machigh = (uint8_t *)(mac + 4);\n+ uint32_t tmpVal = 0;\n+ uint32_t i = 0;\n+ uint32_t cnt = 0;\n+\n+ if (slot >= 3) {\n+ return ERROR;\n+ }\n+\n+ /* Trigger read data from efuse */\n+ if (reload) {\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+ }\n+\n+ if (slot == 0) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);\n+ } else if (slot == 1) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2);\n+ } else if (slot == 2) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1);\n+ }\n+\n+ BL_WRWD_TO_BYTEP(maclow, tmpVal);\n+\n+ if (slot == 0) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);\n+ } else if (slot == 1) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);\n+ } else if (slot == 2) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);\n+ }\n+\n+ machigh[0] = tmpVal & 0xff;\n+ machigh[1] = (tmpVal >> 8) & 0xff;\n+\n+ /* Check parity */\n+ for (i = 0; i < 6; i++) {\n+ cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]);\n+ }\n+\n+ if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) {\n+ /* Change to network order */\n+ for (i = 0; i < 3; i++) {\n+ tmpVal = mac[i];\n+ mac[i] = mac[5 - i];\n+ mac[5 - i] = tmpVal;\n+ }\n+\n+ return SUCCESS;\n+ } else {\n+ return ERROR;\n+ }\n+}\n+\n+/*@} end of group SEC_EF_CTRL_Public_Functions */\n+\n+/*@} end of group SEC_EF_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0ee328cda822bd6f148feb65d442a395afde5061\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c\n@@ -0,0 +1,1727 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_ef_ctrl.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_ef_ctrl.h\"\n+#include \"ef_data_0_reg.h\"\n+#include \"ef_data_1_reg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_EF_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Macros\n+ * @{\n+ */\n+#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)\n+#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8)\n+#define EF_CTRL_DFT_TIMEOUT_VAL (320 * 1000)\n+#ifndef BOOTROM\n+#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0()\n+#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1()\n+#else\n+#define EF_CTRL_LOAD_BEFORE_READ_R0\n+#define EF_CTRL_LOAD_BEFORE_READ_R1\n+#endif\n+#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, 0, EF_CTRL_EFUSE_R0_SIZE / 4)\n+#define EF_CTRL_DATA1_CLEAR EF_Ctrl_Clear(1, 0, EF_CTRL_EFUSE_R1_SIZE / 4)\n+\n+/*@} end of group SEC_EF_CTRL_Private_Macros */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Types */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Variables */\n+\n+/** @defgroup SEC_EF_CTRL_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Global_Variables */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */\n+\n+/** @defgroup SEC_EF_CTRL_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief get custom USB PID VID\n+ *\n+ * @param PID\n+ *\n+ * @param VID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1])\n+{\n+ uint32_t tmpVal;\n+\n+ EF_Ctrl_Read_Sw_Usage(4, &tmpVal);\n+\n+ pid[0] = (uint16_t)(tmpVal & 0xFFFF);\n+ vid[0] = (uint16_t)(tmpVal >> 16);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Switch efuse region 0 control to AHB clock\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;\n+\n+ while (EF_Ctrl_Busy() == SET) {\n+ timeout--;\n+\n+ if (timeout == 0) {\n+ break;\n+ }\n+ }\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Switch efuse region 1 control to AHB clock\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_1(void)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;\n+\n+ while (EF_Ctrl_Busy() == SET) {\n+ timeout--;\n+\n+ if (timeout == 0) {\n+ break;\n+ }\n+ }\n+\n+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,\n+\t so we select it(them) in ef_if_ctrl_0 */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Program efuse region 0\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Select auto mode and select ef clock */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ /* Program */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (1 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ /* Add delay for POR to be stable */\n+ arch_delay_us(4);\n+\n+ /* Trigger */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (1 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (1 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Program efuse region 1\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Select auto mode and select ef clock */\n+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,\n+\t so we select it(them) in ef_if_ctrl_0 */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+\n+ /* Program */\n+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,\n+\tso we select it(them) in ef_if_ctrl_0 */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (1 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ /* Add delay for POR to be stable */\n+ arch_delay_us(4);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (1 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (1 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (1 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Load efuse region 0\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;\n+\n+ EF_CTRL_DATA0_CLEAR;\n+\n+ /* Trigger read */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (1 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ arch_delay_us(10);\n+\n+ /* Wait for efuse control idle */\n+ do {\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);\n+ timeout--;\n+\n+ if (timeout == 0) {\n+ break;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) ||\n+\n+ (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)));\n+\n+ /* Switch to AHB clock */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Load efuse region 1\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void EF_Ctrl_Load_Efuse_R1(void)\n+{\n+ uint32_t tmpVal;\n+\n+ EF_CTRL_DATA1_CLEAR;\n+\n+ /* Trigger read */\n+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,\n+\tso we select it(them) in ef_if_ctrl_0 */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (1 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+\n+ arch_delay_us(10);\n+\n+ /* Wait for efuse control idle */\n+ do {\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1);\n+ } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_1_BUSY));\n+\n+ do {\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE));\n+\n+ /* Switch to AHB clock since often read efuse data after load */\n+ /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,\n+\t so we select it(them) in ef_if_ctrl_0 */\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |\n+ (0 << EF_CTRL_EF_IF_POR_DIG_POS) |\n+ (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_0_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_0_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);\n+\n+ tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) |\n+ (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |\n+ (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |\n+ (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |\n+ (0 << EF_CTRL_EF_IF_1_RW_POS) |\n+ (0 << EF_CTRL_EF_IF_1_TRIG_POS);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Check efuse busy status\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void)\n+{\n+ if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY) ||\n+ BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1), EF_CTRL_EF_IF_1_BUSY)) {\n+ return SET;\n+ }\n+\n+ return RESET;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Check efuse whether finish loading\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write debug password\n+ *\n+ * @param slot: password slot0 or slot1\n+ * @param passWdLow: password low 32 bits\n+ * @param passWdHigh: password high 32 bits\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program)\n+{\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ if (slot == 0) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh);\n+ } else if (slot == 1) {\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW, passWdLow);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH, passWdHigh);\n+ }\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read debug password\n+ *\n+ * @param slot: password slot0 or slot1\n+ * @param passWdLow: password low 32 bits pointer to store value\n+ * @param passWdHigh: password high 32 bits pointer to store value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh)\n+{\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ if (slot == 0) {\n+ *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);\n+ *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);\n+ } else if (slot == 1) {\n+ *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW);\n+ *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse lock reading for passwd\n+ *\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse lock writing for passwd\n+ *\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read security configuration\n+ *\n+ * @param cfg: security configuration pointer\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS, cfg->ef_dbg_jtag_1_dis);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read security configuration\n+ *\n+ * @param cfg: security configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+\n+ cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE);\n+ cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS);\n+ cfg->ef_dbg_jtag_1_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS);\n+ cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write security boot configuration\n+ *\n+ * @param sign[1]: Sign configuration pointer\n+ * @param aes[1]: AES configuration pointer\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ if (aes[0] != EF_CTRL_SF_AES_NONE) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);\n+ }\n+\n+ if (EF_CTRL_SIGN_NONE != sign[0]) {\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, tmpVal);\n+ }\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write security boot configuration\n+ *\n+ * @param aes[2]: AES configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2])\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+\n+ aes[1] = aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read xtal trim rc32m configuration\n+ *\n+ * @param forceNoTrim: force no trim\n+ * @param noXtal: no xtal\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+\n+ *forceNoTrim = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_FORCE_NO_TRIM);\n+ *noXtal = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_XTAL);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse Set sf key re sel\n+ *\n+ * @param ef_sf_key_re_sel: Efuse sf key re sel\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_KEY_RE_SEL, ef_sf_key_re_sel);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Analog Trim parity calculate\n+ *\n+ * @param val: Value of efuse trim data\n+ * @param len: Length of bit to calculate\n+ *\n+ * @return Parity bit value\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len)\n+{\n+ uint8_t cnt = 0;\n+ uint8_t i = 0;\n+\n+ for (i = 0; i < len; i++) {\n+ if (val & (1 << i)) {\n+ cnt++;\n+ }\n+ }\n+\n+ return cnt & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read DCDC11 trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimDcdc11VoutAon = (tmpVal >> 26) & 0x0f;\n+ trim->trimDcdc11VoutAonParity = (tmpVal >> 30) & 0x01;\n+ trim->trimDcdc11VoutAonEn = (tmpVal >> 31) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read DCDC18 trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimDcdc18VoutAon = (tmpVal >> 20) & 0x0f;\n+ trim->trimDcdc18VoutAonParity = (tmpVal >> 24) & 0x01;\n+ trim->trimDcdc18VoutAonEn = (tmpVal >> 25) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read LDO18FLASH trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);\n+ trim->trimLdo18flashVoutAon = (tmpVal >> 26) & 0x0f;\n+ trim->trimLdo18flashVoutAonParity = (tmpVal >> 30) & 0x01;\n+ trim->trimLdo18flashVoutAonEn = (tmpVal >> 31) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read USB20RCAL trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2);\n+ trim->trimUsb20rcalAon = (tmpVal >> 8) & 0x3f;\n+ trim->trimUsb20rcalAonParity = (tmpVal >> 14) & 0x01;\n+ trim->trimUsb20rcalAonEn = (tmpVal >> 15) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read RC32M trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ trim->trimRc32mCodeFrExt = (tmpVal >> 4) & 0xff;\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimRc32mCodeFrExtParity = (tmpVal >> 0) & 0x01;\n+ trim->trimRc32mExtCodeEn = (tmpVal >> 1) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read RC32K trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);\n+ trim->trimRc32kCodeFrExt = (tmpVal >> 8) & 0x3ff;\n+ trim->trimRc32kCodeFrExtParity = (tmpVal >> 18) & 0x01;\n+ trim->trimRc32kExtCodeEn = (tmpVal >> 19) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief\n+ *\n+ * @param\n+ *\n+ * @return\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);\n+ trim->trimLdo18ioVoutVal = (tmpVal >> 14) & 0x0f;\n+ trim->trimLdo18ioVoutParity = (tmpVal >> 18) & 0x01;\n+ trim->trimLdo18ioVoutEn = (tmpVal >> 19) & 0x01;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read TSEN trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0);\n+ trim->tsenRefcodeCorner = (tmpVal >> 0) & 0xfff;\n+ trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01;\n+ trim->tsenRefcodeCornerEn = (tmpVal >> 13) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read ADC Gain trim\n+ *\n+ * @param trim: Trim data pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim)\n+{\n+ uint32_t tmpVal = 0;\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE,EF_DATA_1_EF_DAT_1_RSVD_0);\n+ trim->adcGainCoeff = (tmpVal >> 14) & 0xfff;\n+ trim->adcGainCoeffParity = (tmpVal >> 26) & 0x01;\n+ trim->adcGainCoeffEn = (tmpVal >> 27) & 0x01;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write software usage\n+ *\n+ * @param index: index of software usage\n+ * @param usage: usage value\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program)\n+{\n+ /* switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ switch (index) {\n+ case 0:\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage);\n+ break;\n+\n+ case 1:\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1, usage);\n+ break;\n+\n+ case 2:\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, usage);\n+ break;\n+\n+ case 3:\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, usage);\n+ break;\n+\n+ case 4:\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0, usage);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read software usage\n+ *\n+ * @param index: index of software usage\n+ * @param usage: usage value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage)\n+{\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ switch (index) {\n+ case 0:\n+ *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0);\n+ break;\n+\n+ case 1:\n+ *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1);\n+ break;\n+\n+ case 2:\n+ *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2);\n+ break;\n+\n+ case 3:\n+ *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);\n+ break;\n+\n+ case 4:\n+ *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read software usage\n+ *\n+ * @param index: index of software usage\n+ * @param program: usage value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+\n+ if (index == 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0);\n+ } else if (index == 1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_1);\n+ } else if (index == 2) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_2);\n+ } else if (index == 3) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_3);\n+ }\n+\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write MAC address\n+ *\n+ * @param mac[6]: MAC address buffer\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program)\n+{\n+ uint8_t *maclow = (uint8_t *)mac;\n+ uint8_t *machigh = (uint8_t *)(mac + 4);\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ /* The low 32 bits */\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));\n+ /* The high 16 bits */\n+ tmpVal = machigh[0] + (machigh[1] << 8);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse Ctrl get zero bit count\n+ *\n+ * @param val: Value to count\n+ *\n+ * @return Zero bit count\n+ *\n+*******************************************************************************/\n+static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val)\n+{\n+ uint32_t cnt = 0;\n+ uint32_t i = 0;\n+\n+ for (i = 0; i < 8; i++) {\n+ if ((val & (1 << i)) == 0) {\n+ cnt += 1;\n+ }\n+ }\n+\n+ return cnt;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read MAC address\n+ *\n+ * @param mac[6]: MAC address buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6])\n+{\n+ uint8_t *maclow = (uint8_t *)mac;\n+ uint8_t *machigh = (uint8_t *)(mac + 4);\n+ uint32_t tmpVal;\n+ uint32_t i = 0;\n+ uint32_t cnt = 0;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);\n+ BL_WRWD_TO_BYTEP(maclow, tmpVal);\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);\n+ machigh[0] = tmpVal & 0xff;\n+ machigh[1] = (tmpVal >> 8) & 0xff;\n+\n+ /* Check parity */\n+ for (i = 0; i < 6; i++) {\n+ cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);\n+ }\n+\n+ if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) {\n+ /* Change to network order */\n+ for (i = 0; i < 3; i++) {\n+ tmpVal = mac[i];\n+ mac[i] = mac[5 - i];\n+ mac[5 - i] = tmpVal;\n+ }\n+\n+ return SUCCESS;\n+ } else {\n+ return ERROR;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read MAC address\n+ *\n+ * @param mac[7]: MAC address buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7])\n+{\n+ uint8_t *maclow = (uint8_t *)mac;\n+ uint8_t *machigh = (uint8_t *)(mac + 4);\n+ uint32_t tmpVal;\n+\n+ /* Trigger read data from efuse */\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);\n+ BL_WRWD_TO_BYTEP(maclow, tmpVal);\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);\n+ machigh[0] = tmpVal & 0xff;\n+ machigh[1] = (tmpVal >> 8) & 0xff;\n+ machigh[2] = (tmpVal >> 16) & 0xff;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse lock writing for MAC address\n+ *\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Writelock_MAC_Address(uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC);\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Whether a value bits is all zero\n+ *\n+ * @param val: value to check\n+ * @param start: start bit\n+ * @param len: total length of bits to check\n+ *\n+ * @return 1 for all bits zero 0 for others\n+ *\n+*******************************************************************************/\n+uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len)\n+{\n+ uint32_t mask = 0;\n+\n+ val = (val >> start);\n+\n+ if (len >= 32) {\n+ mask = 0xffffffff;\n+ } else {\n+ mask = (1 << len) - 1;\n+ }\n+\n+ if ((val & mask) == 0) {\n+ return 1;\n+ } else {\n+ return 0;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read chip ID\n+ *\n+ * @param chipID[8]: Chip ID buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8])\n+{\n+ chipID[6] = 0;\n+ chipID[7] = 0;\n+ return EF_Ctrl_Read_MAC_Address_Raw(chipID);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse write AES key\n+ *\n+ * @param keyRegion: efuse key region\n+ * @param index: index of key slot\n+ * @param keyData: key data buffer\n+ * @param len: key data length in words\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program)\n+{\n+ uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);\n+ uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);\n+\n+ /* slot_w0~slot_w3,slot_w11 in ef_data0 \n+ slot_w4~slot_w10,in ef_data1 */\n+\n+ if ((index <= 3) || (index == 11)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ index = ((index == 11) ? 5 : index);\n+\n+ /* Every key is 4 words len*/\n+\n+ ARCH_MemCpy4(pAESKeyStart0 + index * 4, keyData, len);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+ } else if ((index < 11) && (index > 3)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ index = index - 4;\n+\n+ /* Every key is 4 words len*/\n+ ARCH_MemCpy4(pAESKeyStart1 + index * 4, keyData, len);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_1();\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse read AES key from specified region and index\n+ *\n+ * @param keyRegion: efuse key region\n+ * @param index: index of key slot\n+ * @param keyData: key data buffer\n+ * @param len: key data length in words\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len)\n+{\n+ uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);\n+ uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);\n+\n+ if ((index <= 3) || (index == 11)) {\n+ /* Trigger read data from efuse*/\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ index = ((index == 11) ? 5 : index);\n+\n+ /* Every key is 4 words len*/\n+ ARCH_MemCpy4(keyData, pAESKeyStart0 + index * 4, len);\n+ } else if ((index < 11) && (index > 3)) {\n+ /* Trigger read data from efuse*/\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+ index = index - 4;\n+ /* Every key is 4 words len*/\n+ ARCH_MemCpy4(keyData, pAESKeyStart1 + index * 4, len);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse lock writing for aes key\n+ *\n+ * @param keyRegion: efuse key region\n+ * @param index: index of key slot\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ if ((index <= 3) || (index == 11)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ index = ((index == 11) ? 8 : index);\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ tmpVal |= (1 << (index + 17));\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+ } else if ((index < 11) && (index > 3)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ index = index - 4;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK);\n+ tmpVal |= (1 << (index + 15));\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_1();\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Efuse lock reading for aes key\n+ *\n+ * @param keyRegion: efuse key region\n+ * @param index: index of key slot\n+ * @param program: program to efuse entity or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program)\n+{\n+ uint32_t tmpVal;\n+\n+ if ((index <= 3) || (index == 11)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ index = ((index == 11) ? 4 : index);\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);\n+ tmpVal |= (1 << (index + 27));\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_0();\n+ }\n+ } else if ((index < 11) && (index > 3)) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ index = index - 4;\n+\n+ tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK);\n+ tmpVal |= (1 << (index + 25));\n+ BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal);\n+\n+ if (program) {\n+ EF_Ctrl_Program_Efuse_1();\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Program data to efuse region 0\n+ *\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ /* Add delay for CLK to be stable */\n+ arch_delay_us(4);\n+\n+ if (data != NULL) {\n+ ARCH_MemCpy4(pEfuseStart0 + index, data, len);\n+ }\n+\n+ EF_Ctrl_Program_Efuse_0();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Program data to efuse region 1\n+ *\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);\n+\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ /* Add delay for CLK to be stable */\n+ arch_delay_us(4);\n+\n+ if (data != NULL) {\n+ ARCH_MemCpy4(pEfuseStart1 + index, data, len);\n+ }\n+\n+ EF_Ctrl_Program_Efuse_1();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from efuse region 0\n+ *\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R0;\n+\n+ ARCH_MemCpy4(data, pEfuseStart0 + index, len);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from efuse region 1\n+ *\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);\n+\n+ EF_CTRL_LOAD_BEFORE_READ_R1;\n+\n+ ARCH_MemCpy4(data, pEfuseStart1 + index, len);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Program data to efuse entity\n+ *\n+ * @param region: index of efuse region\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ if (region == 0) {\n+ EF_Ctrl_Program_Direct_R0(index, data, len);\n+ } else if (region == 1) {\n+ EF_Ctrl_Program_Direct_R1(index, data, len);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read efuse from register\n+ *\n+ * @param region: index of efuse region\n+ * @param index: index of efuse in word\n+ * @param data: data buffer\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len)\n+{\n+ if (region == 0) {\n+ EF_Ctrl_Read_Direct_R0(index, data, len);\n+ } else if (region == 1) {\n+ EF_Ctrl_Read_Direct_R1(index, data, len);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear efuse data register\n+ *\n+ * @param region: index efuse region\n+ * @param index: index of efuse in word\n+ * @param len: data length\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len)\n+{\n+ uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);\n+ uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80);\n+ uint32_t i = 0;\n+\n+ if (region == 0) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_0();\n+\n+ /* Clear data */\n+ for (i = 0; i < len; i++) {\n+ pEfuseStart0[index + i] = 0;\n+ }\n+ } else if (region == 1) {\n+ /* Switch to AHB clock */\n+ EF_Ctrl_Sw_AHB_Clk_1();\n+\n+ /* Clear data */\n+ for (i = 0; i < len; i++) {\n+ pEfuseStart1[index + i] = 0;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief efuse ctrl crc enable\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Crc_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN);\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief efuse ctrl get crc busy status\n+ *\n+ * @param None\n+ *\n+ * @return DISABLE or ENABLE\n+ *\n+*******************************************************************************/\n+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0);\n+ return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief efuse ctrl set golden value\n+ *\n+ * @param goldenValue: Crc golden value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue)\n+{\n+ BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief efuse ctrl get crc result\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EF_Ctrl_Crc_Result(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0);\n+ return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR);\n+}\n+\n+/*@} end of group SEC_EF_CTRL_Public_Functions */\n+\n+/*@} end of group SEC_EF_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2acaa164bf02dc3f9fb1bd27d35f2a3489c293f3\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c\n@@ -0,0 +1,785 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_emac.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_emac.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup EMAC\n+ * @{\n+ */\n+\n+/** @defgroup EMAC_Private_Macros\n+ * @{\n+ */\n+#define PHY_MAX_RETRY (0x3F)\n+\n+/*@} end of group EMAC_Private_Macros */\n+\n+/** @defgroup EMAC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group EMAC_Private_Types */\n+\n+/** @defgroup EMAC_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *emacIntCbfArra[EMAC_ID_MAX][EMAC_INT_CNT] = { {NULL} };\n+#endif\n+\n+static const uint32_t emacAddr[EMAC_ID_MAX] = { EMAC_BASE };\n+\n+/*@} end of group EMAC_Private_Variables */\n+\n+/** @defgroup EMAC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group EMAC_Global_Variables */\n+\n+/** @defgroup EMAC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group EMAC_Private_Fun_Declaration */\n+\n+/** @defgroup EMAC_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Set MAC Address\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param macAddr[6]: MAC address buffer array\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void EMAC_SetMACAddress(EMAC_ID_Type emacId, uint8_t macAddr[6])\n+{\n+ uint32_t EMACx = emacAddr[emacId];\n+ BL_WR_REG(EMACx, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]);\n+ BL_WR_REG(EMACx, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set PHY Address\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param phyAddress: Phy address\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EMAC_Phy_SetAddress(EMAC_ID_Type emacId, uint16_t phyAddress)\n+{\n+ uint32_t tmpVal;\n+\tuint32_t EMACx = emacAddr[emacId];\n+\n+ /* Set Phy Address */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress);\n+ BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set PHY Address\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param phyAddress: Phy address\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId, uint8_t fullDuplex)\n+{\n+ uint32_t tmpVal;\n+\tuint32_t EMACx = emacAddr[emacId];\n+\n+ /* Set MAC duplex config */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read PHY register\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param phyReg: PHY register\n+ * @param regValue: PHY register value pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Phy_Read(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t *regValue)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Set Register Address */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);\n+ BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal);\n+\n+ /* Trigger read */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT);\n+ BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal);\n+\n+ BL_DRV_DUMMY;\n+\n+ do {\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS);\n+ arch_delay_us(16);\n+ } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));\n+\n+ *regValue = BL_RD_REG(EMACx, EMAC_MIIRX_DATA);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write PHY register\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param phyReg: PHY register\n+ * @param regValue: PHY register value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Phy_Write(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t regValue)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Set Register Address */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);\n+ BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal);\n+\n+ /* Set Write data */\n+ BL_WR_REG(EMACx, EMAC_MIITX_DATA, regValue);\n+\n+ /* Trigger write */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA);\n+ BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal);\n+\n+ BL_DRV_DUMMY;\n+\n+ do {\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS);\n+ } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group EMAC_Private_Functions */\n+\n+/** @defgroup EMAC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Initialize EMAC module\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param cfg: EMAC configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Init(EMAC_ID_Type emacId, EMAC_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Disable clock gate */\n+ //GLB_AHB_Slave2_Clock_Gate(DISABLE, BL_AHB_SLAVE2_EXT_EMAC);\n+\n+ /* Set MAC config */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE);\n+ //tmpVal |= (1 << 7); /* local loopback in emac */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+\n+ /* Set inter frame gap value */\n+ BL_WR_REG(EMACx, EMAC_IPGT, cfg->interFrameGapValue);\n+\n+ /* Set MII interface */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MIIMODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv);\n+ BL_WR_REG(EMACx, EMAC_MIIMODE, tmpVal);\n+\n+ /* Set collision */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_COLLCONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid);\n+ BL_WR_REG(EMACx, EMAC_COLLCONFIG, tmpVal);\n+\n+ /* Set frame length */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_PACKETLEN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen);\n+ BL_WR_REG(EMACx, EMAC_PACKETLEN, tmpVal);\n+\n+ EMAC_SetMACAddress(emacId, cfg->macAddr);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(EMAC_IRQn, EMAC0_IRQHandler);\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+\n+ * @brief DeInitialize EMAC module\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_DeInit(EMAC_ID_Type emacId)\n+{\n+ EMAC_Disable(emacId);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Initialize EMAC TX RX MDA buffer\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param handle: EMAC handle pointer\n+ * @param txBuff: TX buffer\n+ * @param txBuffCount: TX buffer count\n+ * @param rxBuff: RX buffer\n+ * @param rxBuffCount: RX buffer count\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_DMADescListInit(EMAC_ID_Type emacId, EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount)\n+{\n+ uint32_t i = 0;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Set the Ethernet handler env */\n+ handle->bd = (EMAC_BD_Desc_Type *)(uintptr_t)(EMACx + EMAC_DMA_DESC_OFFSET);\n+ handle->txIndexEMAC = 0;\n+ handle->txIndexCPU = 0;\n+ handle->txBuffLimit = txBuffCount - 1;\n+ /* The receive descriptors' address starts right after the last transmit BD. */\n+ handle->rxIndexEMAC = txBuffCount;\n+ handle->rxIndexCPU = txBuffCount;\n+ handle->rxBuffLimit = txBuffCount + rxBuffCount - 1;\n+\n+ /* Fill each DMARxDesc descriptor with the right values */\n+ for (i = 0; i < txBuffCount; i++) {\n+ /* Get the pointer on the ith member of the Tx Desc list */\n+ handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(uintptr_t)(txBuff + (ETH_MAX_PACKET_SIZE * i));\n+ handle->bd[i].C_S_L = 0;\n+ }\n+\n+ /* For the last TX DMA Descriptor, it should be wrap back */\n+ handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR);\n+\n+ for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) {\n+ /* Get the pointer on the ith member of the Rx Desc list */\n+ handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(uintptr_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount)));\n+ handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) |\n+ EMAC_BD_FIELD_MSK(RX_IRQ) |\n+ EMAC_BD_FIELD_MSK(RX_E);\n+ }\n+\n+ /* For the last RX DMA Descriptor, it should be wrap back */\n+ handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR);\n+\n+ /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/\n+ BL_WR_REG(EMACx, EMAC_TX_BD_NUM, txBuffCount);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get TX MDA buffer descripter for data to send\n+ *\n+ * @param handle: EMAC handle pointer\n+ * @param txDMADesc: TX DMA descriptor pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc)\n+{\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Start TX\n+ *\n+ * @param handle: EMAC handle pointer\n+ * @param txDMADesc: TX DMA descriptor pointer\n+ * @param len: len\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len)\n+{\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable EMAC module\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Enable(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Enable EMAC */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_Enable_TX\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Enable_TX(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Enable EMAC */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_Disable_TX\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Disable_TX(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Enable EMAC */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_Enable_RX\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Enable_RX(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpval;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Enable EMAC TX*/\n+ tmpval = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpval);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_Disable_RX\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Disable_RX(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpval;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Disable EMAC RX*/\n+ tmpval = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpval);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable EMAC module\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_Disable(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Enable EMAC */\n+ tmpVal = BL_RD_REG(EMACx, EMAC_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN);\n+ BL_WR_REG(EMACx, EMAC_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC mask or unmask certain or all interrupt\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param intType: EMAC interrupt type\n+ * @param intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_IntMask(EMAC_ID_Type emacId, EMAC_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK);\n+\n+ /* Mask or unmask certain or all interrupt */\n+ if (MASK == intMask) {\n+ tmpVal |= intType;\n+ } else {\n+ tmpVal &= (~intType);\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(EMACx, EMAC_INT_MASK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get EMAC interrupt status\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param intType: EMAC interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Sts_Type EMAC_GetIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_EMAC_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE);\n+\n+ return (tmpVal & intType) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear EMAC interrupt\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param intType: EMAC interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_ClrIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_EMAC_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE);\n+\n+ BL_WR_REG(EMACx, EMAC_INT_SOURCE, tmpVal | intType);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_Int_Callback_Install\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param intIdx: EMAC_INT_Index\n+ * @param cbFun: call back\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type EMAC_Int_Callback_Install(EMAC_ID_Type emacId, EMAC_INT_Index intIdx, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+\n+ emacIntCbfArra[emacId][intIdx] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC_IRQHandler\n+ *\n+ * @param emacId: EMAC ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void EMAC_IRQHandler(EMAC_ID_Type emacId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK);\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_TX_DONE);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_TX_ERROR);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_RX_DONE);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_RX_ERROR);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_RX_BUSY);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_TX_CTRL);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX]();\n+ }\n+ }\n+\n+ if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) {\n+ EMAC_ClrIntStatus(emacId, EMAC_INT_RX_CTRL);\n+\n+ if (emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX]) {\n+ emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief EMAC0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void EMAC0_IRQHandler(void)\n+{\n+ EMAC_IRQHandler(EMAC0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Request to pause TX\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param timeCount: Pause time count\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_TxPauseReq(EMAC_ID_Type emacId, uint16_t timeCount)\n+{\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ BL_WR_REG(EMACx, EMAC_TXCTRL, (1 << 16) | timeCount);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set hash value\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param hash0: Hash value one\n+ * @param hash1: Hash value two\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_SetHash(EMAC_ID_Type emacId, uint32_t hash0, uint32_t hash1)\n+{\n+ uint32_t EMACx = emacAddr[emacId];\n+\n+ BL_WR_REG(EMACx, EMAC_HASH0_ADDR, hash0);\n+\n+ BL_WR_REG(EMACx, EMAC_HASH1_ADDR, hash1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get fram maximum len and minimum\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param max: point to maximum fram len\n+ * @param min: point to minimum fram len\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min)\n+{\n+ uint32_t EMACx = emacAddr[emacId];\n+ uint32_t tmpval;\n+\n+ tmpval = BL_RD_REG(EMACx, EMAC_PACKETLEN);\n+ *max = BL_GET_REG_BITS_VAL(tmpval, EMAC_MAXFL);\n+ *min = BL_GET_REG_BITS_VAL(tmpval, EMAC_MINFL);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get BD numbers\n+ *\n+ * @param emacId: EMAC ID type\n+ * @param bd: point to BD num\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd)\n+{\n+ uint32_t EMACx = emacAddr[emacId];\n+ \n+ *bd = BL_RD_REG(EMACx, EMAC_TX_BD_NUM);\n+\n+ return SUCCESS;\n+}\n+/*@} end of group EMAC_Public_Functions */\n+\n+/*@} end of group EMAC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8e37e4fd406e747e55e0d8e23cf5c719481d7d09\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c\n@@ -0,0 +1,5968 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_glb_pll.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_clock.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_aon.h\"\n+#include \"bl808_hbn.h\"\n+#include \"bl808_pds.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup GLB\n+ * @{\n+ */\n+\n+/** @defgroup GLB_Private_Macros\n+ * @{\n+ */\n+#define GLB_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF)\n+#define GLB_FREQ_RC32M (32000000)\n+\n+/*@} end of group GLB_Private_Macros */\n+\n+/** @defgroup GLB_Private_Types\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };\n+#endif\n+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit);\n+\n+/*@} end of group GLB_Private_Types */\n+\n+/** @defgroup GLB_Private_Variables\n+ * @{\n+ */\n+\n+\n+\n+/* WiFi PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */\n+ { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* Audio PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */\n+};\n+\n+/* CPU PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* MIPI PLL Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &mipiPllBasicCfg_24M, 0x3E800 }, /*!< XTAL is 24M */\n+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is 32M */\n+ { &mipiPllBasicCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */\n+ { &mipiPllBasicCfg_40M, 0x38400 }, /*!< XTAL is 40M */\n+ { &mipiPllBasicCfg_26M, 0x39B13 }, /*!< XTAL is 26M */\n+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2100 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */\n+ { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */\n+ { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1400MCfg_24M, 0x3A555 }, /*!< XTAL is 24M */\n+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is 32M */\n+ { &uhsPll1400MCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1400MCfg_40M, 0x34800 }, /*!< XTAL is 40M */\n+ { &uhsPll1400MCfg_26M, 0x35D89 }, /*!< XTAL is 26M */\n+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1500 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1500MCfg_24M, 0x3E800 }, /*!< XTAL is 24M */\n+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is 32M */\n+ { &uhsPll1500MCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1500MCfg_40M, 0x38400 }, /*!< XTAL is 40M */\n+ { &uhsPll1500MCfg_26M, 0x39B13 }, /*!< XTAL is 26M */\n+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1600 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */\n+ { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */\n+ { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */\n+ { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */\n+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */\n+ { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */\n+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 667 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */\n+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */\n+ { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */\n+ { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */\n+ { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */\n+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 800 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */\n+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */\n+ { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */\n+ { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */\n+ { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */\n+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1066 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */\n+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */\n+ { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1066BasicCfg_40M, 0x27F99 }, /*!< XTAL is 40M */\n+ { &uhsPll1066BasicCfg_26M, 0x29000 }, /*!< XTAL is 26M */\n+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2000 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */\n+ { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */\n+ { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */\n+};\n+\n+/*@} end of group GLB_Private_Variables */\n+\n+/** @defgroup GLB_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Global_Variables */\n+\n+/** @defgroup GLB_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Fun_Declaration */\n+\n+/** @defgroup GLB_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Functions */\n+\n+/** @defgroup GLB_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief set mcu muxpll 160M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu muxpll 160M selection\n+ *\n+ * @param None\n+ *\n+ * @return 160M mux select value\n+ *\n+*******************************************************************************/\n+GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set top muxpll 80M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu muxpll 80M selection\n+ *\n+ * @param None\n+ *\n+ * @return 80M mux select value\n+ *\n+*******************************************************************************/\n+GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 320M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 320M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 320M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_320M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_320M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_320M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 240M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 240M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 240M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_240M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_240M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_240M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 160M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 160M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 160M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_160M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power on all PLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllType: only power on xtal\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType)\n+{\n+ uint32_t tmpVal;\n+ GLB_CORE_ID_Type coreType;\n+ HBN_MCU_XCLK_Type mcuXclkSel;\n+ HBN_MCU_ROOT_CLK_Type mcuRootClkSel;\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;\n+ volatile GLB_PLL_REF_CLK_Type refClk;\n+\n+ CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType));\n+ CHECK_PARAM((pllType < (GLB_PLL_UHSPLL * 2)));\n+\n+ if (xtalType == GLB_XTAL_NONE) {\n+ return ERROR;\n+ }\n+\n+ if (xtalType != GLB_XTAL_RC32M) {\n+ /* power on xtal first */\n+ AON_Power_On_XTAL();\n+ }\n+\n+ coreType = GLB_Get_Core_Type();\n+ if ((GLB_CORE_ID_D0 == coreType)) {\n+ /* D0 */\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();\n+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ }\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ } else {\n+ /* M0 or LP or invalid(use M0 instead) */\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();\n+ mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel();\n+ if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ }\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ }\n+\n+ HBN_Set_Xtal_Type(xtalType);\n+\n+ if (GLB_PLL_NONE == pllType) {\n+ GLB_CLK_SET_DUMMY_WAIT;\n+ return SUCCESS;\n+ }\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ /* power on wifipll */\n+ if (pllType & GLB_PLL_WIFIPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &wifiPllCfg_960M[xtalType], 0);\n+ }\n+\n+ /* power on aupll */\n+ if (pllType & GLB_PLL_AUPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &audioPllCfg_442P368M[xtalType], 0);\n+ }\n+\n+ /* power on cpupll */\n+ if (pllType & GLB_PLL_CPUPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &cpuPllCfg_380M[xtalType], 0);\n+ }\n+\n+ /* power on mipipll */\n+ if (pllType & GLB_PLL_MIPIPLL) {\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &mipiPllCfg_1500M[xtalType], 0);\n+ }\n+\n+ /* power on uhspll */\n+ if (pllType & GLB_PLL_UHSPLL) {\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &uhsPllCfg_2100M[xtalType], 0);\n+ }\n+\n+ arch_delay_us(75);\n+\n+ if (xtalType != GLB_XTAL_RC32M) {\n+ /* if power on xtal, always set xclk from xtal */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ }\n+\n+ /* enable all PLL clock output */\n+ /* GLB reg_pll_en = 1, cannot be zero */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+ /* MM_GLB reg_pll_en = 1, cannot be zero */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_PLL_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power off wifi audio cpu PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* cfg0 : pu_aupll=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* cfg0 : pu_aupll_sfreg=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB wifi audio cpu PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) {\n+ /* wifipll_refclk_sel different from other's pll, 1 means xtal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power on PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param cfg: GLB PLL configuration\n+ * @param waitStable: wait PLL clock stable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ /* unknown */\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* Step1:config parameter */\n+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);\n+\n+ /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);\n+\n+ /* cfg4:Set aupll_sel_sample_clk */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);\n+\n+ /* cfg5:Set aupll_vco_speed */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+\n+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);\n+\n+ /* Step2:config pu */\n+ /* cfg0 : pu_aupll_sfreg=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* cfg0 : pu_wifipll=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */\n+ if (GLB_WAC_PLL_AUPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) {\n+ /* 451.548 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14);\n+ } else {\n+ /* 442.368 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ }\n+\n+ /* Step4:enable output clock */\n+ /* wifipll : cfg5, wifipll_vco_div3_en=1 */\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+ }\n+ /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1);\n+ }\n+ /* cfg8 : wifipll/aupll/cpupll clock enable */\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6);\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);\n+\n+ if (waitStable) {\n+ /* Wait 1.5*30us */\n+ arch_delay_us(45);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB enable or disable USB clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* pu_usbpll_mmdiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+\n+ /* toggle usbpll_rstb */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power off mipi uhs PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* cfg0 : pu_aupll=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* cfg0 : pu_aupll_sfreg=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB mipi uhs PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power on PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param cfg: GLB PLL configuration\n+ * @param waitStable: wait PLL stable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ /* unknown */\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* Step1:config parameter */\n+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ /* cfg4:Set aupll_sel_sample_clk */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);\n+\n+ /* cfg5:Set aupll_vco_speed */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+\n+ /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */\n+ if (GLB_MU_PLL_UHSPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ }\n+\n+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);\n+\n+ /* Step2:config pu */\n+ /* cfg0 : pu_aupll_sfreg=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* cfg0 : pu_wifipll=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ if (waitStable) {\n+ /* Wait 1.5*30us */\n+ arch_delay_us(45);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB set display clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param srcClk: source clock type\n+ * @param evenDiv: divider in even number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t evenNum = 0;\n+\n+ CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk));\n+ CHECK_PARAM((evenDiv <= 0x7F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ if ((evenDiv >= 8) && (evenDiv <= 126)) {\n+ evenNum = evenDiv & ~(1 << 0);\n+ } else {\n+ evenNum = evenDiv;\n+ }\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ if(enable){\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ }else{\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB enable or disable ethernet clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* uhspll_even_div_en */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_UHS_PLL_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB output ethernet MAC clock via GPIO\n+ *\n+ * @param gpio: gpio number,which can be 6/14/22/30\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio)\n+{\n+ uint32_t regAddr=GLB_BASE+GLB_GPIO_CFG0_OFFSET+(gpio<<2);\n+ uint32_t regVal=0x00040F03;\n+\n+ if( ( gpio != GLB_GPIO_PIN_6 ) && \\\n+ ( gpio != GLB_GPIO_PIN_14 ) && \\\n+ ( gpio != GLB_GPIO_PIN_12 ) && \\\n+ ( gpio != GLB_GPIO_PIN_30 ) ){\n+ return ERROR;\n+ }\n+ /* set gpio in debug function */\n+ BL_WR_WORD(regAddr,regVal);\n+\n+ /* select signal */\n+ BL_WR_WORD(0x200002E0+((gpio-6)/8)*4,0x80000010);\n+\n+ /* output */\n+ BL_WR_WORD(0x200002F0,0x01);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set System clock divider\n+ *\n+ * @param mcuClkDiv: HCLK divider\n+ * @param mcuPBclkDiv: BCLK divider\n+ * @param lpClkDiv: LP clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeout = 1024;\n+ HBN_MCU_XCLK_Type xclkSel;\n+ HBN_MCU_ROOT_CLK_Type rootClkSel;\n+\n+ /* get root clock */\n+ xclkSel = HBN_Get_MCU_XCLK_Sel();\n+ rootClkSel = HBN_Get_MCU_Root_CLK_Sel();\n+\n+ if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ }\n+\n+ /* config hclk_div=mcuClkDiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+\n+ /* config bclk_div=mcuPBclkDiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+ /* bclk act pulse */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);\n+\n+ timeout = 1024;\n+ do {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* config lp clock div=lpClkDiv */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, lpClkDiv);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);\n+ /* bclk act pulse */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PICO_CLK_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);\n+\n+ timeout = 1024;\n+ do {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* recover root clock */\n+ HBN_Set_MCU_XCLK_Sel(xclkSel);\n+ HBN_Set_MCU_Root_CLK_Sel(rootClkSel);\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get System clock divider\n+ *\n+ * @param mcuClkDiv: HCLK divider\n+ * @param mcuPBclkDiv: BCLK divider\n+ * @param lpClkDiv: LP clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv)\n+{\n+ *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV);\n+ *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);\n+ *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set mcu System clock\n+ *\n+ * @param clkFreq: mcu system clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq)\n+{\n+ uint32_t tmpVal;\n+ HBN_MCU_XCLK_Type mcuXclkSel;\n+\n+ CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq));\n+\n+ /* get xclk&&rootclk clock */\n+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();\n+\n+ /* change root clock to rc32m */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* select pll output clock before select root clock */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);\n+ switch (clkFreq) {\n+ case GLB_MCU_SYS_CLK_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);\n+\n+ /* select root clock */\n+ switch (clkFreq) {\n+ case GLB_MCU_SYS_CLK_RC32M:\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_MCU_SYS_CLK_XTAL:\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_MCU_SYS_CLK_CPUPLL_400M:\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(1, 2, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ /* unuseful for mcu, useful for dsp, just for safe */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(0, 2, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ /* unuseful for mcu, useful for dsp, just for safe */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:\n+ /* overclock, not recommended */\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(0, 3, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP0 DSP1 clock div\n+ *\n+ * @param dspClkDiv: mm glb cpu div\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeout = 1024;\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;\n+\n+ /* get root clock */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();\n+\n+ /* change root clock to rc32m */\n+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ }\n+\n+ /* set div */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV, dspBclkDiv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV, dspClkDiv);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ do {\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_STS_BCLK2X_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* recover root clock */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ GLB_Set_DSP_ROOT_CLK_Sel(dspRootClkSel);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP0 DSP1 clock div\n+ *\n+ * @param dspClkDiv: mm glb cpu div\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);\n+ *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set dsp System clock\n+ *\n+ * @param clkFreq: dsp system clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq)\n+{\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SYS_CLK_TYPE(clkFreq));\n+\n+ /* get root clock */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* select pll output clock before select root clock */\n+ if (GLB_DSP_SYS_CLK_MM_WIFIPLL_240M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_240M);\n+ } else if (GLB_DSP_SYS_CLK_MM_WIFIPLL_320M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_320M);\n+ } else if (GLB_DSP_SYS_CLK_CPUPLL_400M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_CPUPLL_400M);\n+ }\n+\n+ /* select root clock */\n+ switch (clkFreq) {\n+ case GLB_DSP_SYS_CLK_RC32M:\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_DSP_SYS_CLK_XTAL:\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_240M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_320M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_320M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ case GLB_DSP_SYS_CLK_CPUPLL_400M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ default:\n+ break;\n+ }\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP0 pbus clock div\n+ *\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* set div */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV, dspPBclkDiv);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP0 pbus clock div\n+ *\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv)\n+{\n+ *dspPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU), MM_GLB_REG_BCLK1X_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set dsp pbus clock\n+ *\n+ * @param pbClkSel: dsp pbus clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel)\n+{\n+ CHECK_PARAM(IS_GLB_DSP_SYS_PBCLK_TYPE(pbClkSel));\n+\n+ GLB_Set_DSP_PBCLK_Div(0);\n+\n+ /* select pbroot clock */\n+ switch (pbClkSel) {\n+ case GLB_DSP_SYS_PBCLK_RC32M:\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_XTAL:\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M:\n+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_160M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_CPUPLL_160M:\n+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_CPUPLL_160M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M:\n+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);\n+ GLB_Set_DSP_PBCLK_Div(1);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M);\n+ break;\n+ default:\n+ break;\n+ }\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP0 clock enable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP0 clock disable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get xclk clock source Select\n+ *\n+ * @param None\n+ *\n+ * @return xclk clock type selection\n+ *\n+*******************************************************************************/\n+GLB_DSP_XCLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_XCLK_Sel(void)\n+{\n+ return (GLB_DSP_XCLK_Type)(BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU), MM_GLB_REG_XCLK_CLK_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select xclk clock source\n+ *\n+ * @param xclk: xclk clock type selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_XCLK_TYPE(xclk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP root clock\n+ *\n+ * @param None\n+ *\n+ * @return mm glb root clock type\n+ *\n+*******************************************************************************/\n+GLB_DSP_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_ROOT_CLK_Sel(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t rootclk = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);\n+ if (0 == rootclk) {\n+ /* xclk */\n+ return GLB_DSP_ROOT_CLK_XCLK;\n+ } else {\n+ /* pll */\n+ return GLB_DSP_ROOT_CLK_PLL;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP root clock\n+ *\n+ * @param rootClk: mm glb root clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ROOT_CLK_TYPE(rootClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (rootClk) {\n+ case GLB_DSP_ROOT_CLK_XCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 0);\n+ break;\n+ case GLB_DSP_ROOT_CLK_PLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 1);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP muxpll clock\n+ *\n+ * @param pllClk: mm glb pll clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PLL_CLK_TYPE(pllClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (pllClk) {\n+ case GLB_DSP_PLL_CLK_MUXPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 0);\n+ break;\n+ case GLB_DSP_PLL_CLK_MUXPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 1);\n+ break;\n+ case GLB_DSP_PLL_CLK_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 2);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP pbroot clock\n+ *\n+ * @param None\n+ *\n+ * @return mm DSP pbroot clock type\n+ *\n+*******************************************************************************/\n+GLB_DSP_PBROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBROOT_CLK_Sel(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t pbrootclk = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);\n+ switch (pbrootclk) {\n+ case 0:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ case 1:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ case 2:\n+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M;\n+ case 3:\n+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M;\n+ default:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP pbroot clock\n+ *\n+ * @param pbrootClk: mm DSP pbroot clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PBROOT_CLK_TYPE(pbrootClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (pbrootClk) {\n+ case GLB_DSP_PBROOT_CLK_MM_XCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 0);\n+ break;\n+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 2);\n+ break;\n+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get core type\n+ *\n+ * @param None\n+ *\n+ * @return core type\n+ *\n+*******************************************************************************/\n+GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_WORD(CORE_ID_ADDRESS);\n+\n+ switch (tmpVal) {\n+ case CORE_ID_M0:\n+ return GLB_CORE_ID_M0;\n+ case CORE_ID_D0:\n+ return GLB_CORE_ID_D0;\n+ case CORE_ID_LP:\n+ return GLB_CORE_ID_LP;\n+ default:\n+ return GLB_CORE_ID_INVALID;\n+ }\n+\n+ return GLB_CORE_ID_INVALID;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief hold cpu\n+ *\n+ * @param coreID: core type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Halt_CPU(GLB_CORE_ID_Type coreID)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ PDS_Set_MCU0_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ GLB_DSP0_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ PDS_Set_LP_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief release cpu\n+ *\n+ * @param coreID: core type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Release_CPU(GLB_CORE_ID_Type coreID)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ PDS_Set_MCU0_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ GLB_DSP0_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ PDS_Set_LP_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set CPU reset address\n+ *\n+ * @param coreID: core type\n+ * @param addr: reset address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr)\n+{\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU0_BOOT, addr);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP get MCU interrupt status\n+ *\n+ * @param intType: MCU interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG16) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG17) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP set MCU interrupt mask\n+ *\n+ * @param intType: MCU interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG18);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG18, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG19);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG19, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP clear MCU interrupt status\n+ *\n+ * @param intType: MCU interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG20);\n+ tmpVal |= (1 << intType);\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG20, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG21);\n+ tmpVal |= (1 << (intType - 32));\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG21, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP set LP interrupt enable\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param intType: LP interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG22);\n+ if (enable) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG22, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG23);\n+ if (enable) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG23, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP get LP interrupt status\n+ *\n+ * @param intType: LP interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG24) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG25) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU get DSP interrupt status\n+ *\n+ * @param intType: DSP interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA0) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA1) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU set DSP interrupt mask\n+ *\n+ * @param intType: DSP interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU clear DSP interrupt status\n+ *\n+ * @param intType: DSP interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0);\n+ tmpVal |= (1 << intType);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1);\n+ tmpVal |= (1 << (intType - 32));\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_EMI_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ /* disable EMI clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ switch (clkSel) {\n+ case GLB_EMI_CLK_MCU_PBCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 0);\n+ break;\n+ case GLB_EMI_CLK_CPUPLL_200M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 4);\n+ break;\n+ case GLB_EMI_CLK_WIFIPLL_320M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 2);\n+ break;\n+ case GLB_EMI_CLK_CPUPLL_400M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* clear EMI swrst bit */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal);\n+\n+ /* set EMI cgen bit */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable MTimer clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ /* disable MTimer clock first */\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ }\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable MTimer clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ /* disable MTimer clock first */\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_C906_RTC_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set ADC clock\n+ *\n+ * @param enable: enable frequency divider or not\n+ * @param clkSel: ADC clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ /* disable ADC clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DMA clock\n+ *\n+ * @param enable: Enable or disable\n+ * @param clk: DMA clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk));\n+\n+ if (clk >= GLB_DMA1_CLK_CH0) {\n+ /* DMA1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG1);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN);\n+ if (enable) {\n+ tmpVal2 |= (1 << (clk - GLB_DMA1_CLK_CH0));\n+ } else {\n+ tmpVal2 &= (~(1 << (clk - GLB_DMA1_CLK_CH0)));\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG1, tmpVal);\n+ } else {\n+ /* DMA0 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);\n+ if (enable) {\n+ tmpVal2 |= (1 << clk);\n+ } else {\n+ tmpVal2 &= (~(1 << clk));\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set peripheral DMA cn\n+ *\n+ * @param peri: peripheral\n+ * @param cn: cn\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri));\n+ CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2);\n+ switch (cn) {\n+ case GLB_PERI_DMA_CN_SEL_DMA0:\n+ tmpVal &= ~(1 << peri);\n+ break;\n+ case GLB_PERI_DMA_CN_SEL_DMA1:\n+ tmpVal |= (1 << peri);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set IR clock divider\n+ *\n+ * @param enable: enable or disable IR clock\n+ * @param clkSel: IR clock type\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select ir rx gpio (gpio11~gpio13)\n+ *\n+ * @param gpio: IR gpio selected\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Select gpio between gpio9 and gpio23 */\n+ if (gpio > 8 && gpio < 24) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+ }\n+\n+ /* Close ir rx */\n+ if (gpio == 0) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable ir led driver\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_LED_Driver_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Enable led driver */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable ir led driver\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_LED_Driver_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Disable led driver */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set UART2 IO selection\n+ *\n+ * @param ioType: UART2 IO selection type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART2_IO_SEL_TYPE(ioType));\n+\n+ /* Set uart2 io selection */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART2_IO_SEL, ioType);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set UART clock\n+ *\n+ * @param enable: Enable or disable UART clock\n+ * @param clkSel: UART clock type\n+ * @param div: UART clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x7));\n+ CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));\n+\n+ /* disable UART clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ /* Set div */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ /* Select clock source for uart */\n+ HBN_Set_UART_CLK_Sel(clkSel);\n+\n+ /* Set enable or disable */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select UART signal function\n+ *\n+ * @param sig: UART signal\n+ * @param fun: UART function\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)\n+{\n+ uint32_t sig_pos = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));\n+ CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));\n+\n+ if (sig < GLB_UART_SIG_8) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1);\n+ sig_pos = (sig * 4);\n+ /* Clear original val */\n+ tmpVal &= (~(0xf << sig_pos));\n+ /* Set new value */\n+ tmpVal |= (fun << sig_pos);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2);\n+ sig_pos = ((sig - 8) * 4);\n+ /* Clear original val */\n+ tmpVal &= (~(0xf << sig_pos));\n+ /* Set new value */\n+ tmpVal |= (fun << sig_pos);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sflash clock\n+ *\n+ * @param enable: enable or disable sflash clock\n+ * @param clkSel: sflash clock type\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ /* disable SFLASH clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ if (clkSel == GLB_SFLASH_CLK_100M_CPUPLL) {\n+ GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_CPUPLL_100M);\n+ }\n+\n+ /* clock divider */\n+ /* Select flash clock, all Flash CLKs are divied by PLL_480M */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);\n+ switch (clkSel) {\n+ case GLB_SFLASH_CLK_120M_WIFIPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);\n+ break;\n+ case GLB_SFLASH_CLK_XTAL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);\n+ break;\n+ case GLB_SFLASH_CLK_100M_CPUPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);\n+ break;\n+ case GLB_SFLASH_CLK_80M_MUXPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);\n+ break;\n+ case GLB_SFLASH_CLK_BCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);\n+ break;\n+ case GLB_SFLASH_CLK_96M_WIFIPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ /* enable or disable flash clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set I2C clock\n+ *\n+ * @param enable: Enable or disable I2C clock\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set I2S clock\n+ *\n+ * @param refClkEn: ref clock ENABLE or DISABLE\n+ * @param refClkDiv: divider\n+ * @param inRef: di ref clock\n+ * @param outRef: do ref clock\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((refClkDiv <= 0x3F));\n+ CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef));\n+ CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef);\n+ if (refClkEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set SPI clock\n+ *\n+ * @param enable: Enable or disable SPI clock\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x1F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PWM1 clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PWM2 clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PWM2_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM2_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PDM clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DIG clock source\n+ *\n+ * @param clkSel: DIG clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dig512kEn;\n+ uint32_t dig32kEn;\n+\n+ CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel));\n+\n+ /* disable DIG512K and DIG32K clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);\n+ dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ /* repristinate DIG512K and DIG32K clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DIG 512K clock\n+ *\n+ * @param enable: enable or disable DIG 512K clock\n+ * @param compensationEn: enable or disable DIG 512K clock compensation\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x7F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (compensationEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DIG 32K clock\n+ *\n+ * @param enable: enable or disable DIG 32K clock\n+ * @param compensationEn: enable or disable DIG 32K clock compensation\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x7FF));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (compensationEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief platform wakeup becomes one of pds_wakeup source\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu gpio timer clock select\n+ *\n+ * @param gpioPin: gpio pin number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ switch (gpioPin & 0x3) {\n+ case 0: /* inout_sig_0 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0);\n+ break;\n+ case 1: /* inout_sig_1 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1);\n+ break;\n+ case 2: /* inout_sig_2 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2);\n+ break;\n+ case 3: /* inout_sig_3 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief dsp gpio timer clock select\n+ *\n+ * @param gpioPin: gpio pin number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ switch (gpioPin & 0x3) {\n+ case 0: /* inout_sig_0 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 0);\n+ break;\n+ case 1: /* inout_sig_1 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 1);\n+ break;\n+ case 2: /* inout_sig_2 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 2);\n+ break;\n+ case 3: /* inout_sig_3 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out0 select\n+ *\n+ * @param clkOutType: chip clock out0 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out0 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out1 select\n+ *\n+ * @param clkOutType: chip clock out1 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out1 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out2 select\n+ *\n+ * @param clkOutType: chip clock out2 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out2 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out3 select\n+ *\n+ * @param clkOutType: chip clock out3 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out3 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief csi dsi clock select\n+ *\n+ * @param csiClkSel: csi clock select\n+ * @param dsiClkSel: dsi clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CSI_TXCLKESC_SEL, csiClkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DSI_TXCLKESC_SEL, dsiClkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief BMX init\n+ *\n+ * @param BmxCfg: BMX config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((BmxCfg->timeoutEn) <= 0x1F);\n+ CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get BMX TO status\n+ *\n+ * @param None\n+ *\n+ * @return BMX TO status\n+ *\n+*******************************************************************************/\n+uint8_t GLB_Get_BMX_TO_Status(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear BMX TO status\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Clr_BMX_TO_Status(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief BMX timeout interrupt callback install\n+ *\n+ * @param intType: BMX timeout interrupt type\n+ * @param cbFun: callback\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));\n+\n+ glbBmxToIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief BMX Time Out interrupt IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void BMX_TO_IRQHandler(void)\n+{\n+ BMX_TO_INT_Type intType;\n+\n+ for (intType = 0; intType < BMX_TO_INT_ALL; intType++) {\n+ if (glbBmxToIntCbfArra[intType] != NULL) {\n+ glbBmxToIntCbfArra[intType]();\n+ }\n+ }\n+ GLB_Clr_BMX_TO_Status();\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief set audio auto clock\n+ *\n+ * @param divEn: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio ADC clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio DAC clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio PDM clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio PDM clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PADC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth rx clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth tx clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth ref clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set eth ref clock select\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set CAM clock\n+ *\n+ * @param enable: Enable or disable CAM clock\n+ * @param clkSel: CAM clock type\n+ * @param div: clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set SDH clock\n+ *\n+ * @param enable: Enable or disable\n+ * @param clkSel: SDH clock type\n+ * @param div: clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief swap UART gpio pins sig function\n+ *\n+ * @param group: UART swap set group\n+ * @param swap: swap or no swap\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET);\n+ if (swap) {\n+ tmpVal2 |= (1 << group);\n+ } else {\n+ tmpVal2 &= ~(1 << group);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief swap DSP SPI0 MOSI with MISO\n+ *\n+ * @param newState: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_SWAP, newState);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DSP SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_MASTER_MODE, mod);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set L2SRAM\n+ *\n+ * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable\n+ * @param vramSramRel: make l2_vram writable\n+ * @param dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable\n+ * @param blaiSramRel: make blai_64k0,blai_64k1 writable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ /* Make the above settings effective */\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DSP SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash io parameter\n+ *\n+ * @param selEmbedded: Select embedded flash pin\n+ * @param swap: Select embedded flash swap io0 with io3\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ if (selEmbedded) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);\n+ if (swap) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ }\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ if (selEmbedded) {\n+ GLB_Embedded_Flash_Pad_Enable();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief software reset\n+ *\n+ * @param swrst: reset num\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t bit = 0;\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst));\n+\n+ if (swrst < 32) {\n+ bit = swrst;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET;\n+ } else if (swrst < 64) {\n+ bit = swrst - 32;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET;\n+ } else if (swrst < 96) {\n+ bit = swrst - 64;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal |= (1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief software reset\n+ *\n+ * @param swrst: reset num\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t bit = 0;\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_GLB_AHB_DSP_SW_TYPE(swrst));\n+\n+ if (swrst < 32) {\n+ bit = swrst;\n+ regAddr = MM_GLB_BASE + MM_GLB_MM_SW_SYS_RESET_OFFSET;\n+ } else if (swrst < 64) {\n+ bit = swrst - 32;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET;\n+ } else if (swrst < 96) {\n+ bit = swrst - 64;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_DSP2_SUB_OFFSET;\n+ } else if (swrst < 128) {\n+ bit = swrst - 96;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET;\n+ } else if (swrst < 160) {\n+ bit = swrst - 128;\n+ regAddr = MM_GLB_BASE + MM_GLB_IMAGE_SENSOR_CTRL_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal |= (1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief dis reset\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param disrst: disrst macro\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DISRST_TYPE(disrst));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG3);\n+ if (enable) {\n+ tmpVal |= (1 << disrst);\n+ } else {\n+ tmpVal &= ~(1 << disrst);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get first 1 from u64, then clear it\n+ *\n+ * @param val: target value\n+ * @param bit: first 1 in bit\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)\n+{\n+ if (!*val) {\n+ return ERROR;\n+ }\n+\n+ for (uint8_t i = 0; i < 64; i++) {\n+ if ((*val) & ((uint64_t)1 << i)) {\n+ *bit = i;\n+ (*val) &= ~((uint64_t)1 << i);\n+ break;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief hold IPs clock\n+ *\n+ * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)\n+{\n+ /* api request from cjy */\n+\n+ uint32_t tmpValCfg0 = 0;\n+ uint32_t tmpValCfg1 = 0;\n+ uint32_t tmpValCfg2 = 0;\n+ uint32_t bitfield = 0;\n+\n+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);\n+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ while (ips) {\n+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {\n+ switch (bitfield) {\n+ case GLB_AHB_CLOCK_IP_CPU:\n+ tmpValCfg0 &= ~(1 << 0);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDU:\n+ tmpValCfg0 &= ~(1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SEC:\n+ tmpValCfg0 &= ~(1 << 2);\n+ tmpValCfg1 &= ~(1 << 3);\n+ tmpValCfg1 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_0:\n+ tmpValCfg0 &= ~(1 << 3);\n+ tmpValCfg1 &= ~(1 << 12);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_1:\n+ tmpValCfg0 &= ~(1 << 3);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_2:\n+ tmpValCfg0 &= ~(1 << 3);\n+ tmpValCfg2 &= ~(1 << 24);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CCI:\n+ tmpValCfg0 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_RF_TOP:\n+ tmpValCfg1 &= ~(1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GPIP:\n+ tmpValCfg1 &= ~(1 << 2);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TZC:\n+ tmpValCfg1 &= ~(1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EF_CTRL:\n+ tmpValCfg1 &= ~(1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SF_CTRL:\n+ tmpValCfg1 &= ~(1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMAC:\n+ tmpValCfg2 &= ~(1 << 19);\n+ tmpValCfg2 &= ~(1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART0:\n+ tmpValCfg1 &= ~(1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART1:\n+ tmpValCfg1 &= ~(1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART2:\n+ tmpValCfg1 &= ~(1 << 26);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART3:\n+ break;\n+ case GLB_AHB_CLOCK_IP_SPI:\n+ tmpValCfg1 &= ~(1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C:\n+ tmpValCfg1 &= ~(1 << 19);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PWM:\n+ tmpValCfg1 &= ~(1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TIMER:\n+ tmpValCfg1 &= ~(1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_IR:\n+ tmpValCfg1 &= ~(1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CHECKSUM:\n+ tmpValCfg1 &= ~(1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_QDEC:\n+ break;\n+ case GLB_AHB_CLOCK_IP_KYS:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2S:\n+ tmpValCfg1 &= ~(1 << 27);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB11:\n+ break;\n+ case GLB_AHB_CLOCK_IP_CAM:\n+ break;\n+ case GLB_AHB_CLOCK_IP_MJPEG:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:\n+ tmpValCfg2 &= ~(1 << 8);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:\n+ tmpValCfg2 &= ~(1 << 9);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:\n+ tmpValCfg2 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:\n+ tmpValCfg2 &= ~(1 << 10);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMI_MISC:\n+ tmpValCfg2 &= ~(1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:\n+ tmpValCfg2 &= ~(1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:\n+ tmpValCfg2 &= ~(1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB20:\n+ tmpValCfg1 &= ~(1 << 13);\n+ break;\n+ case GLB_AHB_CLOCK_IP_MIX2:\n+ tmpValCfg2 &= ~(1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUDIO:\n+ tmpValCfg2 &= ~(1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDH:\n+ tmpValCfg2 &= ~(1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:\n+ tmpValCfg2 &= ~(1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C1:\n+ tmpValCfg1 &= ~(1 << 25);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PHY:\n+ tmpValCfg0 &= ~(1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:\n+ tmpValCfg0 &= ~(1 << 6);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:\n+ tmpValCfg0 &= ~(1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_LZ4:\n+ tmpValCfg1 &= ~(1 << 29);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUPDM:\n+ tmpValCfg1 &= ~(1 << 28);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GAUGE:\n+ tmpValCfg1 &= ~(1 << 0);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief release IPs clock\n+ *\n+ * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... (not GLB_AHB_CLOCK_IP_xxx)\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)\n+{\n+ /* api request from cjy */\n+\n+ uint32_t tmpValCfg0 = 0;\n+ uint32_t tmpValCfg1 = 0;\n+ uint32_t tmpValCfg2 = 0;\n+ uint32_t bitfield = 0;\n+\n+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);\n+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ while (ips) {\n+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {\n+ switch (bitfield) {\n+ case GLB_AHB_CLOCK_IP_CPU:\n+ tmpValCfg0 |= (1 << 0);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDU:\n+ tmpValCfg0 |= (1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SEC:\n+ tmpValCfg0 |= (1 << 2);\n+ tmpValCfg1 |= (1 << 3);\n+ tmpValCfg1 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_0:\n+ tmpValCfg0 |= (1 << 3);\n+ tmpValCfg1 |= (1 << 12);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_1:\n+ tmpValCfg0 |= (1 << 3);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_2:\n+ tmpValCfg0 |= (1 << 3);\n+ tmpValCfg2 |= (1 << 24);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CCI:\n+ tmpValCfg0 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_RF_TOP:\n+ tmpValCfg1 |= (1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GPIP:\n+ tmpValCfg1 |= (1 << 2);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TZC:\n+ tmpValCfg1 |= (1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EF_CTRL:\n+ tmpValCfg1 |= (1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SF_CTRL:\n+ tmpValCfg1 |= (1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMAC:\n+ tmpValCfg2 |= (1 << 19);\n+ tmpValCfg2 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART0:\n+ tmpValCfg1 |= (1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART1:\n+ tmpValCfg1 |= (1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART2:\n+ tmpValCfg1 |= (1 << 26);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART3:\n+ break;\n+ case GLB_AHB_CLOCK_IP_SPI:\n+ tmpValCfg1 |= (1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C:\n+ tmpValCfg1 |= (1 << 19);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PWM:\n+ tmpValCfg1 |= (1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TIMER:\n+ tmpValCfg1 |= (1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_IR:\n+ tmpValCfg1 |= (1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CHECKSUM:\n+ tmpValCfg1 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_QDEC:\n+ break;\n+ case GLB_AHB_CLOCK_IP_KYS:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2S:\n+ tmpValCfg1 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB11:\n+ break;\n+ case GLB_AHB_CLOCK_IP_CAM:\n+ break;\n+ case GLB_AHB_CLOCK_IP_MJPEG:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:\n+ tmpValCfg2 |= (1 << 8);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:\n+ tmpValCfg2 |= (1 << 9);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:\n+ tmpValCfg2 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:\n+ tmpValCfg2 |= (1 << 10);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMI_MISC:\n+ tmpValCfg2 |= (1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:\n+ tmpValCfg2 |= (1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:\n+ tmpValCfg2 |= (1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB20:\n+ tmpValCfg1 |= (1 << 13);\n+ break;\n+ case GLB_AHB_CLOCK_IP_MIX2:\n+ tmpValCfg2 |= (1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUDIO:\n+ tmpValCfg2 |= (1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDH:\n+ tmpValCfg2 |= (1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:\n+ tmpValCfg2 |= (1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C1:\n+ tmpValCfg1 |= (1 << 25);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PHY:\n+ tmpValCfg0 |= (1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:\n+ tmpValCfg0 |= (1 << 6);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:\n+ tmpValCfg0 |= (1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_LZ4:\n+ tmpValCfg1 |= (1 << 29);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUPDM:\n+ tmpValCfg1 |= (1 << 28);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GAUGE:\n+ tmpValCfg1 |= (1 << 0);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief gate pll clock cgen\n+ *\n+ * @param clk: pll clock cgen\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ tmpVal &= (~(1 << clk));\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief gate pll clock cgen\n+ *\n+ * @param clk: pll clock cgen\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ tmpVal |= (1 << clk);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select PKA clock source\n+ *\n+ * @param clkSel: PKA clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu system part reset\n+ *\n+ * @param sysPart: mcu reset part\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart));\n+\n+ /* reset=0 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ BL_DRV_DUMMY;\n+ /* reset=1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal |= (1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ BL_DRV_DUMMY;\n+ /* reset=1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software system reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* reset M0/M1/LP/SYS(bus+...+D0+D1) */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software CPU reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;\n+\n+ /* Do reset */\n+ core = GLB_Get_Core_Type();\n+\n+ switch (core) {\n+ case GLB_CORE_ID_M0:\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software power on reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* Do reset */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set auto calc xtal type value\n+ *\n+ * @param calcXtalType: auto calc xtal type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);\n+ tmpVal = tmpVal & 0xffff0000;\n+ tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE;\n+ tmpVal |= calcXtalType;\n+ BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set auto calc xtal type value\n+ *\n+ * @param calcXtalType: auto calc xtal type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);\n+ if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) {\n+ *calcXtalType = (tmpVal & 0xff);\n+ return SUCCESS;\n+ } else {\n+ *calcXtalType = 0;\n+ return ERROR;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash id value\n+ *\n+ * @param idValue: flash id value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue|BFLB_FLASH_ID_VALID_FLAG));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get flash id value\n+ *\n+ * @param None\n+ *\n+ * @return flash id\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_Flash_Id_Value(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1);\n+ if ((tmpVal&BFLB_FLASH_ID_VALID_FLAG) != 0) {\n+ return (tmpVal&BFLB_FLASH_ID_VALID_MASK);\n+ }\n+\n+ return 0x00000000;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_ret value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_ret value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_RET(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_slp value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_slp value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_SLP(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_param value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_parm value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_PARM(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select EM type\n+ *\n+ * @param emType: EM type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_EM_TYPE(emType));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3);\n+ switch (emType) {\n+ case GLB_WRAM160KB_EM0KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00);\n+ break;\n+ case GLB_WRAM144KB_EM16KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);\n+ break;\n+ case GLB_WRAM128KB_EM32KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F);\n+ break;\n+ case GLB_WRAM112KB_EM48KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x3F);\n+ break;\n+ case GLB_WRAM96KB_EM64KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0xFF);\n+ break;\n+ default:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set psram clock\n+ *\n+ * @param id: psram id\n+ * @param enable: enable or disable psram clock\n+ * @param pll: psram pll clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t en = 0;\n+\n+ CHECK_PARAM(IS_GLB_PSRAM_PLL_TYPE(pll));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ en = enable ? 1 : 0;\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ switch (pll) {\n+ case GLB_PSRAM_EMI_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_CPUPLL_400M, en);\n+ break;\n+ case GLB_PSRAM_EMI_WIFIPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_WIFIPLL_320M, en);\n+ break;\n+ case GLB_PSRAM_EMI_AUPLL_DIV1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_AUPLL_DIV1, en);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);\n+ if (id == 1) {\n+ /* psram B */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_EN, en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, pll);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim ldo18io vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18IO_Vout(void)\n+{\n+ Efuse_Ana_LDO18IO_VOUT_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_LDO18IO_Vout_Trim(&trim);\n+ if (trim.trimLdo18ioVoutEn) {\n+ if (trim.trimLdo18ioVoutParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18ioVoutVal, 4)) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_TRIM_AON, trim.trimLdo18ioVoutVal);\n+ BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim ldo18flash vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18FLASH_Vout(void)\n+{\n+ Efuse_Ana_LDO18FLASH_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_LDO18FLASH_Trim(&trim);\n+ if (trim.trimLdo18flashVoutAonEn) {\n+ if (trim.trimLdo18flashVoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18flashVoutAon, 4)) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.trimLdo18flashVoutAon);\n+ BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set cnn clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: cnn clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_CNN_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set display clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: display clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0xF));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp2 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: dsp2 clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DSP2_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set h264 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: h264 clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_H264_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set spi clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SPI_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set uart0 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param uartClk: mm glb uart clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set uart1 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param uartClk: mm glb uart clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set i2c0 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param divEn: div enable\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ }\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set i2c1 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param divEn: div enable\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ }\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief sw sys reset\n+ *\n+ * @param sysPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SW_SYSTEM_TYPE(sysPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal |= (1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief peripheral reset\n+ *\n+ * @param periPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PERIPHERAL_TYPE(periPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal &= ~(1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal |= (1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal &= ~(1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief dsp2 sub reset\n+ *\n+ * @param dsp2Part: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DSP2_SUB_TYPE(dsp2Part));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal &= ~(1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal |= (1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal &= ~(1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief codec sub reset\n+ *\n+ * @param codecPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_CODEC_SUB_TYPE(codecPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal &= ~(1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal |= (1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal &= ~(1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief image sensor reset\n+ *\n+ * @param imageSensorPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_IMAGE_SENSOR_TYPE(imageSensorPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal &= ~(1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal |= (1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal &= ~(1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure WIFIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure AUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure CPUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock div\n+ *\n+ * @param divEn: div enable\n+ * @param divRatio: div ratio\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+ \n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ \n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure UHSPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+/*@} end of group GLB_Public_Functions */\n+\n+/*@} end of group GLB */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..07ff32518724cb32585d95cc32954bcb9b107d03\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c\n@@ -0,0 +1,955 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_glb_gpio.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_clock.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_hbn.h\"\n+#include \"bl808_pds.h\"\n+#include \"bl808_glb_gpio.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup GLB_GPIO\n+ * @{\n+ */\n+\n+/** @defgroup GLB_GPIO_Private_Macros\n+ * @{\n+ */\n+#define GLB_GPIO_INT0_NUM (GLB_GPIO_PIN_MAX)\n+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)\n+\n+/*@} end of group GLB_GPIO_Private_Macros */\n+#define GLB_GPIO_TIMEOUT_COUNT (320 * 1000)\n+/** @defgroup GLB_GPIO_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group GLB_GPIO_Private_Types */\n+\n+/** @defgroup GLB_GPIO_Private_Variables\n+ * @{\n+ */\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL };\n+\n+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group GLB_GPIO_Private_Variables */\n+\n+/** @defgroup GLB_GPIO_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group GLB_GPIO_Global_Variables */\n+\n+/** @defgroup GLB_GPIO_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group GLB_GPIO_Private_Fun_Declaration */\n+\n+/** @defgroup GLB_GPIO_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group GLB_GPIO_Private_Functions */\n+\n+/** @defgroup GLB_GPIO_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO initialization\n+ *\n+ * @param cfg: GPIO configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)\n+{\n+ uint8_t gpioPin = cfg->gpioPin;\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */\n+ /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */\n+ /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */\n+ /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ /* Disable output anyway*/\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ /* input/output, pull up/down, drive, smt, function */\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+\n+ if (cfg->gpioMode != GPIO_MODE_ANALOG) {\n+ /* not analog mode */\n+\n+ if (cfg->gpioMode == GPIO_MODE_OUTPUT) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ }\n+\n+ if (cfg->pullType == GPIO_PULL_UP) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);\n+ } else if (cfg->pullType == GPIO_PULL_DOWN) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);\n+ }\n+ if (gpioPin == GLB_GPIO_PIN_40) {\n+ *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 27);\n+ } else if (gpioPin == GLB_GPIO_PIN_41) {\n+ *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 28);\n+ }\n+ } else {\n+ /* analog mode */\n+\n+ /* clear ie && oe */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+\n+ /* clear pu && pd */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, cfg->outputMode);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief init GPIO function in pin list\n+ *\n+ * @param gpioFun: GPIO pin function\n+ * @param pinList: GPIO pin list\n+ * @param cnt: GPIO pin count\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)\n+{\n+ GLB_GPIO_Cfg_Type gpioCfg = {\n+ .gpioPin = GLB_GPIO_PIN_0,\n+ .gpioFun = (uint8_t)gpioFun,\n+ .gpioMode = GPIO_MODE_AF,\n+ .pullType = GPIO_PULL_UP,\n+ .drive = 1,\n+ .smtCtrl = 1\n+ };\n+\n+ if (gpioFun == GPIO_FUN_ANALOG) {\n+ gpioCfg.gpioMode = GPIO_MODE_ANALOG;\n+ }\n+\n+ for (uint8_t i = 0; i < cnt; i++) {\n+ gpioCfg.gpioPin = pinList[i];\n+ GLB_GPIO_Init(&gpioCfg);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO set input function enable\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Embedded flash set input function enable\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_Embedded_Flash_Pad_Enable(void)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+ uint32_t gpioPin;\n+\n+ for (gpioPin = 48; gpioPin < 52; gpioPin++) {\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO set input function disable\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO set output function enable\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO set output function disable\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO set High-Z\n+ *\n+ * @param gpioPin: GPIO pin\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ /* Disable output anyway*/\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ /* ie=0, oe=0, drive=0, smt=0, pu=1 (pull up), pd=0, func=swgpio */\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, 0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); /* pull up */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, 0xB);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get GPIO function\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return GPIO function\n+ *\n+*******************************************************************************/\n+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read GPIO\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return GPIO value\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_TCM_SECTION GLB_GPIO_Read(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write GPIO\n+ *\n+ * @param gpioPin: GPIO type\n+ * @param val: GPIO value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+\n+ if (val) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);\n+ }\n+\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief turn GPIO output high\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin)\n+{\n+ if (gpioPin < GLB_GPIO_PIN_32) {\n+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG138_OFFSET, 1 << gpioPin);\n+ } else {\n+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG139_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief turn GPIO output low\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)\n+{\n+ if (gpioPin < GLB_GPIO_PIN_32) {\n+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG140_OFFSET, 1 << gpioPin);\n+ } else {\n+ BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG141_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO interrupt initialization\n+ *\n+ * @param intCfg: GPIO interrupt configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+ uint32_t gpioPin = intCfg->gpioPin;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MODE_SET, intCfg->trig);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intCfg->intMask);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set GLB GPIO interrupt mask\n+ *\n+ * @param gpioPin: GPIO type\n+ * @param intMask: GPIO interrupt MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intMask);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get GLB GPIO interrupt status\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear GLB GPIO interrupt status\n+ *\n+ * @param gpioPin: GPIO type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t gpioCfgAddress;\n+ uint32_t tmpVal;\n+\n+ gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);\n+\n+ /* clr=1 */\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ /* clr=0 */\n+ tmpVal = BL_RD_WORD(gpioCfgAddress);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);\n+ BL_WR_WORD(gpioCfgAddress, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+void GPIO_FIFO_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_END_MASK)) {\n+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END] != NULL) {\n+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FER_MASK)) {\n+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER] != NULL) {\n+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK)) {\n+ if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO] != NULL) {\n+ glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO INT0 IRQHandler install\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)\n+{\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+BL_Err_Type GLB_GPIO_FIFO_IRQHandler_Install(void)\n+{\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(GPIO_DMA_IRQn, GPIO_FIFO_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO interrupt IRQ handler callback install\n+ *\n+ * @param gpioPin: GPIO pin type\n+ * @param cbFun: callback function\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)\n+{\n+ if (gpioPin < GLB_GPIO_PIN_MAX) {\n+ glbGpioInt0CbfArra[gpioPin] = cbFun;\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));\n+\n+ glbGpioFifoCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO interrupt IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void GPIO_INT0_IRQHandler(void)\n+{\n+ GLB_GPIO_Type gpioPin;\n+ uint32_t timeOut = 0;\n+\n+ for (gpioPin = GLB_GPIO_PIN_0; gpioPin < GLB_GPIO_PIN_MAX; gpioPin++) {\n+ if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {\n+ GLB_Clr_GPIO_IntStatus(gpioPin);\n+\n+ /* timeout check */\n+ timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;\n+\n+ do {\n+ timeOut--;\n+ } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);\n+\n+ if (!timeOut) {\n+ //MSG(\"WARNING: Clear GPIO interrupt status fail.\\r\\n\");\n+ }\n+\n+ if (glbGpioInt0CbfArra[gpioPin] != NULL) {\n+ /* Call the callback function */\n+ glbGpioInt0CbfArra[gpioPin]();\n+ }\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief GPIO fifo function initialization\n+ *\n+ * @param cfg: GPIO fifo configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code0Phase));\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code1Phase));\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->latch));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_TX_EN, cfg->fifoDmaEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_TX_FIFO_TH, cfg->fifoDmaThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_OUT_SEL_LATCH, cfg->latch);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_PARK_VALUE, cfg->idle);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE0_HIGH_TIME, cfg->code0FirstTime);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE1_HIGH_TIME, cfg->code1FirstTime);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE_TOTAL_TIME, cfg->codeTotalTime);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE0_HIGH, cfg->code0Phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE1_HIGH, cfg->code1Phase);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);\n+\n+ GLB_GPIO_FIFO_IRQHandler_Install();\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Push data to GPIO fifo\n+ *\n+ * @param data: the pointer of data buffer\n+ * @param len: the len of data buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len)\n+{\n+ uint32_t txLen = 0;\n+ uint32_t timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;\n+\n+ while (txLen < len) {\n+ if (GLB_GPIO_Fifo_GetCount() > 0) {\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG144, data[txLen++]);\n+ timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;\n+ } else {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get GPIO fifo available count\n+ *\n+ * @param None\n+ *\n+ * @return The count of available count\n+ *\n+*******************************************************************************/\n+uint32_t GLB_GPIO_Fifo_GetCount(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear GPIO fifo\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Fifo_Clear(void)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask or Unmask GPIO FIFO Interrupt\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);\n+\n+ /* Mask or unmask certain or all interrupt */\n+ if (MASK == intMask) {\n+ switch (intType) {\n+ case GLB_GPIO_FIFO_INT_FER:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_FIFO:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_END:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_ALL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ } else {\n+ switch (intType) {\n+ case GLB_GPIO_FIFO_INT_FER:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_FIFO:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_END:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_ALL:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear GPIO fifo interrupt\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);\n+\n+ /* Clear certain or all interrupt */\n+ switch (intType) {\n+ case GLB_GPIO_FIFO_INT_FER:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_FIFO:\n+ //tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_END:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);\n+ break;\n+\n+ case GLB_GPIO_FIFO_INT_ALL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get GPIO fifo interrupt status\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));\n+\n+ /* Get certain or all interrupt status */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);\n+\n+ if (GLB_GPIO_FIFO_INT_ALL == intType) {\n+ if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) ||\n+ BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) ||\n+ BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ switch (intType) {\n+ case GLB_GPIO_FIFO_INT_FER:\n+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT);\n+\n+ case GLB_GPIO_FIFO_INT_FIFO:\n+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT);\n+\n+ case GLB_GPIO_FIFO_INT_END:\n+ return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT);\n+\n+ default:\n+ return RESET;\n+ }\n+ }\n+}\n+BL_Sts_Type GLB_GPIO_Fifo_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);\n+\n+ return SUCCESS;\n+}\n+BL_Sts_Type GLB_GPIO_Fifo_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);\n+ BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group GLB_GPIO_Public_Functions */\n+\n+/*@} end of group GLB_GPIO */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..55140d817446e20e21ca593a9a8c8806df88f31b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c\n@@ -0,0 +1,2959 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_glb_misc.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_clock.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_aon.h\"\n+#include \"bl808_hbn.h\"\n+#include \"bl808_pds.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup GLB\n+ * @{\n+ */\n+\n+/** @defgroup GLB_Private_Macros\n+ * @{\n+ */\n+\n+\n+\n+/*@} end of group GLB_Private_Macros */\n+\n+/** @defgroup GLB_Private_Types\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };\n+#endif\n+\n+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit);\n+\n+/*@} end of group GLB_Private_Types */\n+\n+/** @defgroup GLB_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Variables */\n+\n+/** @defgroup GLB_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Global_Variables */\n+\n+/** @defgroup GLB_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Fun_Declaration */\n+\n+/** @defgroup GLB_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Functions */\n+\n+/** @defgroup GLB_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief GLB set display clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param srcClk: source clock type\n+ * @param evenDiv: divider in even number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t evenNum = 0;\n+\n+ CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk));\n+ CHECK_PARAM((evenDiv <= 0x7F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ if ((evenDiv >= 8) && (evenDiv <= 126)) {\n+ evenNum = evenDiv & ~(1 << 0);\n+ } else {\n+ evenNum = evenDiv;\n+ }\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ if(enable){\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ }else{\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB enable or disable ethernet clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Ethernet_CLK_From_UHSPLL(uint8_t enable)\n+\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* uhspll_even_div_en */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_UHS_PLL_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+\n+\n+/****************************************************************************/ /**\n+ * @brief DSP get MCU interrupt status\n+ *\n+ * @param intType: MCU interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG16) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG17) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP set MCU interrupt mask\n+ *\n+ * @param intType: MCU interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG18);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG18, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG19);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG19, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP clear MCU interrupt status\n+ *\n+ * @param intType: MCU interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG20);\n+ tmpVal |= (1 << intType);\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG20, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG21);\n+ tmpVal |= (1 << (intType - 32));\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG21, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP set LP interrupt enable\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param intType: LP interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG22);\n+ if (enable) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG22, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG23);\n+ if (enable) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CORE_CFG23, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP get LP interrupt status\n+ *\n+ * @param intType: LP interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG24) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG25) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU get DSP interrupt status\n+ *\n+ * @param intType: DSP interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA0) & (1 << intType)) ? SET : RESET;\n+ } else {\n+ return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA1) & (1 << (intType - 32))) ? SET : RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU set DSP interrupt mask\n+ *\n+ * @param intType: DSP interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << intType);\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1);\n+ if (UNMASK != intMask) {\n+ tmpVal |= (1 << (intType - 32));\n+ } else {\n+ tmpVal &= ~(1 << (intType - 32));\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MCU clear DSP interrupt status\n+ *\n+ * @param intType: DSP interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType));\n+\n+ if (intType < 32) {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0);\n+ tmpVal |= (1 << intType);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1);\n+ tmpVal |= (1 << (intType - 32));\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable MTimer clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ /* disable MTimer clock first */\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);\n+ }\n+ BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable MTimer clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ /* disable MTimer clock first */\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_C906_RTC_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN);\n+ }\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set ADC clock\n+ *\n+ * @param enable: enable frequency divider or not\n+ * @param clkSel: ADC clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ /* disable ADC clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DMA clock\n+ *\n+ * @param enable: Enable or disable\n+ * @param clk: DMA clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk));\n+\n+ if (clk >= GLB_DMA1_CLK_CH0) {\n+ /* DMA1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG1);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN);\n+ if (enable) {\n+ tmpVal2 |= (1 << (clk - GLB_DMA1_CLK_CH0));\n+ } else {\n+ tmpVal2 &= (~(1 << (clk - GLB_DMA1_CLK_CH0)));\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG1, tmpVal);\n+ } else {\n+ /* DMA0 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);\n+ if (enable) {\n+ tmpVal2 |= (1 << clk);\n+ } else {\n+ tmpVal2 &= (~(1 << clk));\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set peripheral DMA cn\n+ *\n+ * @param peri: peripheral\n+ * @param cn: cn\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri));\n+ CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2);\n+ switch (cn) {\n+ case GLB_PERI_DMA_CN_SEL_DMA0:\n+ tmpVal &= ~(1 << peri);\n+ break;\n+ case GLB_PERI_DMA_CN_SEL_DMA1:\n+ tmpVal |= (1 << peri);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set IR clock divider\n+ *\n+ * @param enable: enable or disable IR clock\n+ * @param clkSel: IR clock type\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select ir rx gpio (gpio11~gpio13)\n+ *\n+ * @param gpio: IR gpio selected\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Select gpio between gpio9 and gpio23 */\n+ if (gpio > 8 && gpio < 24) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+ }\n+\n+ /* Close ir rx */\n+ if (gpio == 0) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable ir led driver\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_LED_Driver_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Enable led driver */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable ir led driver\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_IR_LED_Driver_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Disable led driver */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);\n+ BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set UART2 IO selection\n+ *\n+ * @param ioType: UART2 IO selection type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART2_IO_SEL_TYPE(ioType));\n+\n+ /* Set uart2 io selection */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART2_IO_SEL, ioType);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set UART clock\n+ *\n+ * @param enable: Enable or disable UART clock\n+ * @param clkSel: UART clock type\n+ * @param div: UART clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x7));\n+ CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));\n+\n+ /* disable UART clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ /* Set div */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ /* Select clock source for uart */\n+ HBN_Set_UART_CLK_Sel(clkSel);\n+\n+ /* Set enable or disable */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select UART signal function\n+ *\n+ * @param sig: UART signal\n+ * @param fun: UART function\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)\n+{\n+ uint32_t sig_pos = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));\n+ CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));\n+\n+ if (sig < GLB_UART_SIG_8) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1);\n+ sig_pos = (sig * 4);\n+ /* Clear original val */\n+ tmpVal &= (~(0xf << sig_pos));\n+ /* Set new value */\n+ tmpVal |= (fun << sig_pos);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal);\n+ } else {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2);\n+ sig_pos = ((sig - 8) * 4);\n+ /* Clear original val */\n+ tmpVal &= (~(0xf << sig_pos));\n+ /* Set new value */\n+ tmpVal |= (fun << sig_pos);\n+ BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sflash clock\n+ *\n+ * @param enable: enable or disable sflash clock\n+ * @param clkSel: sflash clock type\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ /* disable SFLASH clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ if (clkSel == GLB_SFLASH_CLK_100M_CPUPLL) {\n+ GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_CPUPLL_100M);\n+ }\n+\n+ /* clock divider */\n+ /* Select flash clock, all Flash CLKs are divied by PLL_480M */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);\n+ switch (clkSel) {\n+ case GLB_SFLASH_CLK_120M_WIFIPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);\n+ break;\n+ case GLB_SFLASH_CLK_XTAL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);\n+ break;\n+ case GLB_SFLASH_CLK_100M_CPUPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);\n+ break;\n+ case GLB_SFLASH_CLK_80M_MUXPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);\n+ break;\n+ case GLB_SFLASH_CLK_BCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);\n+ break;\n+ case GLB_SFLASH_CLK_96M_WIFIPLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ /* enable or disable flash clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set I2C clock\n+ *\n+ * @param enable: Enable or disable I2C clock\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set I2S clock\n+ *\n+ * @param refClkEn: ref clock ENABLE or DISABLE\n+ * @param refClkDiv: divider\n+ * @param inRef: di ref clock\n+ * @param outRef: do ref clock\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((refClkDiv <= 0x3F));\n+ CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef));\n+ CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef);\n+ if (refClkEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set SPI clock\n+ *\n+ * @param enable: Enable or disable SPI clock\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x1F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PWM1 clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PWM2 clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PWM2_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM2_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set PDM clock\n+ *\n+ * @param ioSel: io select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel);\n+ BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DIG clock source\n+ *\n+ * @param clkSel: DIG clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+ uint32_t dig512kEn;\n+ uint32_t dig32kEn;\n+\n+ CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel));\n+\n+ /* disable DIG512K and DIG32K clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);\n+ dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ /* repristinate DIG512K and DIG32K clock */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DIG 512K clock\n+ *\n+ * @param enable: enable or disable DIG 512K clock\n+ * @param compensationEn: enable or disable DIG 512K clock compensation\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x7F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (compensationEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set DIG 32K clock\n+ *\n+ * @param enable: enable or disable DIG 32K clock\n+ * @param compensationEn: enable or disable DIG 32K clock compensation\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((div <= 0x7FF));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (compensationEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief platform wakeup becomes one of pds_wakeup source\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu gpio timer clock select\n+ *\n+ * @param gpioPin: gpio pin number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ switch (gpioPin & 0x3) {\n+ case 0: /* inout_sig_0 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0);\n+ break;\n+ case 1: /* inout_sig_1 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1);\n+ break;\n+ case 2: /* inout_sig_2 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2);\n+ break;\n+ case 3: /* inout_sig_3 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief dsp gpio timer clock select\n+ *\n+ * @param gpioPin: gpio pin number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ switch (gpioPin & 0x3) {\n+ case 0: /* inout_sig_0 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 0);\n+ break;\n+ case 1: /* inout_sig_1 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 1);\n+ break;\n+ case 2: /* inout_sig_2 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 2);\n+ break;\n+ case 3: /* inout_sig_3 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out0 select\n+ *\n+ * @param clkOutType: chip clock out0 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out0 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out1 select\n+ *\n+ * @param clkOutType: chip clock out1 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out1 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out2 select\n+ *\n+ * @param clkOutType: chip clock out2 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out2 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out3 select\n+ *\n+ * @param clkOutType: chip clock out3 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out3 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief csi dsi clock select\n+ *\n+ * @param csiClkSel: csi clock select\n+ * @param dsiClkSel: dsi clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CSI_TXCLKESC_SEL, csiClkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DSI_TXCLKESC_SEL, dsiClkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief BMX init\n+ *\n+ * @param BmxCfg: BMX config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((BmxCfg->timeoutEn) <= 0x1F);\n+ CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get BMX TO status\n+ *\n+ * @param None\n+ *\n+ * @return BMX TO status\n+ *\n+*******************************************************************************/\n+uint8_t GLB_Get_BMX_TO_Status(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear BMX TO status\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Clr_BMX_TO_Status(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);\n+ BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief BMX timeout interrupt callback install\n+ *\n+ * @param intType: BMX timeout interrupt type\n+ * @param cbFun: callback\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));\n+\n+ glbBmxToIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief BMX Time Out interrupt IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void BMX_TO_IRQHandler(void)\n+{\n+ BMX_TO_INT_Type intType;\n+\n+ for (intType = 0; intType < BMX_TO_INT_ALL; intType++) {\n+ if (glbBmxToIntCbfArra[intType] != NULL) {\n+ glbBmxToIntCbfArra[intType]();\n+ }\n+ }\n+ GLB_Clr_BMX_TO_Status();\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief set audio auto clock\n+ *\n+ * @param divEn: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio ADC clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio DAC clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio PDM clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set audio PDM clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PADC_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth rx clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth tx clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief invert eth ref clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set eth ref clock select\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set CAM clock\n+ *\n+ * @param enable: Enable or disable CAM clock\n+ * @param clkSel: CAM clock type\n+ * @param div: clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set SDH clock\n+ *\n+ * @param enable: Enable or disable\n+ * @param clkSel: SDH clock type\n+ * @param div: clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief swap UART gpio pins sig function\n+ *\n+ * @param group: UART swap set group\n+ * @param swap: swap or no swap\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+\n+ CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET);\n+ if (swap) {\n+ tmpVal2 |= (1 << group);\n+ } else {\n+ tmpVal2 &= ~(1 << group);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief swap DSP SPI0 MOSI with MISO\n+ *\n+ * @param newState: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_SWAP, newState);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DSP SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_MASTER_MODE, mod);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set L2SRAM\n+ *\n+ * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable\n+ * @param vramSramRel: make l2_vram writable\n+ * @param dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable\n+ * @param blaiSramRel: make blai_64k0,blai_64k1 writable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel);\n+ BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ /* Make the above settings effective */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1);\n+ BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select DSP SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select SPI_0 act mode\n+ *\n+ * @param mod: SPI work mode\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash io parameter\n+ *\n+ * @param selEmbedded: Select embedded flash pin\n+ * @param swap: Select embedded flash swap io0 with io3\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ if (selEmbedded) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);\n+ if (swap) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ }\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ if (selEmbedded) {\n+ GLB_Embedded_Flash_Pad_Enable();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief gate pll clock cgen\n+ *\n+ * @param clk: pll clock cgen\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ tmpVal &= (~(1 << clk));\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief gate pll clock cgen\n+ *\n+ * @param clk: pll clock cgen\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ tmpVal |= (1 << clk);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select PKA clock source\n+ *\n+ * @param clkSel: PKA clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief mcu system part reset\n+ *\n+ * @param sysPart: mcu reset part\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart));\n+\n+ /* reset=0 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ BL_DRV_DUMMY;\n+ /* reset=1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal |= (1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ BL_DRV_DUMMY;\n+ /* reset=1 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software system reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* reset M0/M1/LP/SYS(bus+...+D0+D1) */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software CPU reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;\n+\n+ /* Do reset */\n+ core = GLB_Get_Core_Type();\n+\n+ switch (core) {\n+ case GLB_CORE_ID_M0:\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Software power on reset\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Swicth DSP clock to RC32M, no divider */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* Swicth MCU clock to RC32M, no divider */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* Do reset */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+\n+ /* waiting for reset */\n+ while (1) {\n+ arch_delay_us(10);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set auto calc xtal type value\n+ *\n+ * @param calcXtalType: auto calc xtal type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);\n+ tmpVal = tmpVal & 0xffff0000;\n+ tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE;\n+ tmpVal |= calcXtalType;\n+ BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set auto calc xtal type value\n+ *\n+ * @param calcXtalType: auto calc xtal type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);\n+ if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) {\n+ *calcXtalType = (tmpVal & 0xff);\n+ return SUCCESS;\n+ } else {\n+ *calcXtalType = 0;\n+ return ERROR;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash id value\n+ *\n+ * @param idValue: flash id value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_HW_RSV1, idValue);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get flash id value\n+ *\n+ * @param None\n+ *\n+ * @return flash id\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_Flash_Id_Value(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_HW_RSV1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_ret value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_ret value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_RET(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_slp value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_slp value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_SLP(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set sram_param value\n+ *\n+ * @param value: value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)\n+{\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get sram_parm value\n+ *\n+ * @param None\n+ *\n+ * @return value\n+ *\n+*******************************************************************************/\n+uint32_t GLB_Get_SRAM_PARM(void)\n+{\n+ return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select EM type\n+ *\n+ * @param emType: EM type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_EM_TYPE(emType));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3);\n+ switch (emType) {\n+ case GLB_WRAM160KB_EM0KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00);\n+ break;\n+ case GLB_WRAM144KB_EM16KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);\n+ break;\n+ case GLB_WRAM128KB_EM32KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F);\n+ break;\n+ case GLB_WRAM112KB_EM48KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x3F);\n+ break;\n+ case GLB_WRAM96KB_EM64KB:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0xFF);\n+ break;\n+ default:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set psram clock\n+ *\n+ * @param id: psram id\n+ * @param enable: enable or disable psram clock\n+ * @param pll: psram pll clock\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t en = 0;\n+\n+ CHECK_PARAM(IS_GLB_PSRAM_PLL_TYPE(pll));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ en = enable ? 1 : 0;\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);\n+ switch (pll) {\n+ case GLB_PSRAM_EMI_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_CPUPLL_400M, en);\n+ break;\n+ case GLB_PSRAM_EMI_WIFIPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_WIFIPLL_320M, en);\n+ break;\n+ case GLB_PSRAM_EMI_AUPLL_DIV1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_AUPLL_DIV1, en);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);\n+ if (id == 1) {\n+ /* psram B */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_EN, en);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, pll);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim ldo18io vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18IO_Vout(void)\n+{\n+ Efuse_Ana_LDO18IO_VOUT_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_LDO18IO_Vout_Trim(&trim);\n+ if (trim.trimLdo18ioVoutEn) {\n+ if (trim.trimLdo18ioVoutParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18ioVoutVal, 4)) {\n+ tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_TRIM_AON, trim.trimLdo18ioVoutVal);\n+ BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief trim ldo18flash vout\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18FLASH_Vout(void)\n+{\n+ Efuse_Ana_LDO18FLASH_Trim_Type trim;\n+ uint32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_LDO18FLASH_Trim(&trim);\n+ if (trim.trimLdo18flashVoutAonEn) {\n+ if (trim.trimLdo18flashVoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18flashVoutAon, 4)) {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.trimLdo18flashVoutAon);\n+ BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set cnn clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: cnn clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_CNN_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set display clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: display clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0xF));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp2 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: dsp2 clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DSP2_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set h264 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param clkSel: h264 clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_H264_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV, div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL, clkSel);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set spi clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SPI_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set uart0 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param uartClk: mm glb uart clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set uart1 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param uartClk: mm glb uart clock type\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk));\n+ CHECK_PARAM((div <= 0x7));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set i2c0 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param divEn: div enable\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN);\n+ }\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set i2c1 clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param divEn: div enable\n+ * @param div: div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV, div);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN);\n+ }\n+ if (divEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN);\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief sw sys reset\n+ *\n+ * @param sysPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SW_SYSTEM_TYPE(sysPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal |= (1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal &= ~(1 << sysPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief peripheral reset\n+ *\n+ * @param periPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PERIPHERAL_TYPE(periPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal &= ~(1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal |= (1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI);\n+ tmpVal &= ~(1 << periPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief dsp2 sub reset\n+ *\n+ * @param dsp2Part: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_DSP2_SUB_TYPE(dsp2Part));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal &= ~(1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal |= (1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);\n+ tmpVal &= ~(1 << dsp2Part);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief codec sub reset\n+ *\n+ * @param codecPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_CODEC_SUB_TYPE(codecPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal &= ~(1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal |= (1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB);\n+ tmpVal &= ~(1 << codecPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief image sensor reset\n+ *\n+ * @param imageSensorPart: reset type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_IMAGE_SENSOR_TYPE(imageSensorPart));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal &= ~(1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal |= (1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL);\n+ tmpVal &= ~(1 << imageSensorPart);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group GLB_Public_Functions */\n+\n+/*@} end of group GLB */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5294bc8c04ce16ab7650dd51cda44655e7f61940\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c\n@@ -0,0 +1,3050 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_glb_pll.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_clock.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_aon.h\"\n+#include \"bl808_hbn.h\"\n+#include \"bl808_pds.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup GLB\n+ * @{\n+ */\n+\n+/** @defgroup GLB_Private_Macros\n+ * @{\n+ */\n+#define GLB_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF)\n+#define GLB_FREQ_RC32M (32000000)\n+\n+/*@} end of group GLB_Private_Macros */\n+\n+/** @defgroup GLB_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Types */\n+\n+/** @defgroup GLB_Private_Variables\n+ * @{\n+ */\n+\n+\n+\n+/* WiFi PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */\n+ { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* Audio PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */\n+};\n+\n+/* CPU PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* MIPI PLL Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &mipiPllBasicCfg_24M, 0x1F400 }, /*!< XTAL is 24M */\n+ { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */\n+ { &mipiPllBasicCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */\n+ { &mipiPllBasicCfg_40M, 0x25800 }, /*!< XTAL is 40M */\n+ { &mipiPllBasicCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */\n+ { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2100 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */\n+ { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */\n+ { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1400MCfg_24M, 0x1D2AA }, /*!< XTAL is 24M */\n+ { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is 32M */\n+ { &uhsPll1400MCfg_38P4M, 0x24755 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1400MCfg_40M, 0x23000 }, /*!< XTAL is 40M */\n+ { &uhsPll1400MCfg_26M, 0x1AEC4 }, /*!< XTAL is 26M */\n+ { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1500 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1500MCfg_24M, 0x1F400 }, /*!< XTAL is 24M */\n+ { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */\n+ { &uhsPll1500MCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1500MCfg_40M, 0x25800 }, /*!< XTAL is 40M */\n+ { &uhsPll1500MCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */\n+ { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1600 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */\n+ { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */\n+ { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */\n+ { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll400BasicCfg_24M, 0x8555 }, /*!< XTAL is 24M */\n+ { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is 32M */\n+ { &uhsPll400BasicCfg_38P4M, 0xA6AA }, /*!< XTAL is 38.4M */\n+ { &uhsPll400BasicCfg_40M, 0xA000 }, /*!< XTAL is 40M */\n+ { &uhsPll400BasicCfg_26M, 0x7B13 }, /*!< XTAL is 26M */\n+ { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 667 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll667BasicCfg_24M, 0xDE55 }, /*!< XTAL is 24M */\n+ { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is 32M */\n+ { &uhsPll667BasicCfg_38P4M, 0x115EA }, /*!< XTAL is 38.4M */\n+ { &uhsPll667BasicCfg_40M, 0x10ACC }, /*!< XTAL is 40M */\n+ { &uhsPll667BasicCfg_26M, 0xCD3B }, /*!< XTAL is 26M */\n+ { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 800 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll800BasicCfg_24M, 0x10AAA }, /*!< XTAL is 24M */\n+ { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */\n+ { &uhsPll800BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &uhsPll800BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &uhsPll800BasicCfg_26M, 0xF627 }, /*!< XTAL is 26M */\n+ { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1066 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1066BasicCfg_24M, 0x16355 }, /*!< XTAL is 24M */\n+ { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is 32M */\n+ { &uhsPll1066BasicCfg_38P4M, 0x1BC2A }, /*!< XTAL is 38.4M */\n+ { &uhsPll1066BasicCfg_40M, 0x1AA66 }, /*!< XTAL is 40M */\n+ { &uhsPll1066BasicCfg_26M, 0x14800 }, /*!< XTAL is 26M */\n+ { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2000 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */\n+ { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */\n+ { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */\n+};\n+\n+/*@} end of group GLB_Private_Variables */\n+\n+/** @defgroup GLB_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Global_Variables */\n+\n+/** @defgroup GLB_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Fun_Declaration */\n+\n+/** @defgroup GLB_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group GLB_Private_Functions */\n+\n+/** @defgroup GLB_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief set mcu muxpll 160M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu muxpll 160M selection\n+ *\n+ * @param None\n+ *\n+ * @return 160M mux select value\n+ *\n+*******************************************************************************/\n+GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set top muxpll 80M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mcu muxpll 80M selection\n+ *\n+ * @param None\n+ *\n+ * @return 80M mux select value\n+ *\n+*******************************************************************************/\n+GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 320M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 320M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 320M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_320M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_320M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_320M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 240M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 240M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 240M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_240M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_240M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_240M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set dsp muxpll 160M selection\n+ *\n+ * @param clkSel: clock selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL, clkSel);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get dsp muxpll 160M selection\n+ *\n+ * @param None\n+ *\n+ * @return dsp 160M mux select value\n+ *\n+*******************************************************************************/\n+GLB_DSP_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_160M_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);\n+ return (GLB_DSP_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power on all PLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllType: only power on xtal\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType)\n+{\n+ uint32_t tmpVal;\n+ GLB_CORE_ID_Type coreType;\n+ HBN_MCU_XCLK_Type mcuXclkSel;\n+ HBN_MCU_ROOT_CLK_Type mcuRootClkSel;\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;\n+ volatile GLB_PLL_REF_CLK_Type refClk;\n+\n+ CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType));\n+ CHECK_PARAM((pllType < (GLB_PLL_UHSPLL * 2)));\n+\n+ if (xtalType == GLB_XTAL_NONE) {\n+ return ERROR;\n+ }\n+\n+ if (xtalType != GLB_XTAL_RC32M) {\n+ /* power on xtal first */\n+ AON_Power_On_XTAL();\n+ }\n+\n+ coreType = GLB_Get_Core_Type();\n+ if ((GLB_CORE_ID_D0 == coreType)) {\n+ /* D0 */\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();\n+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ }\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ } else {\n+ /* M0 or LP or invalid(use M0 instead) */\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();\n+ mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel();\n+ if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ }\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ }\n+\n+ HBN_Set_Xtal_Type(xtalType);\n+\n+ if (GLB_PLL_NONE == pllType) {\n+ GLB_CLK_SET_DUMMY_WAIT;\n+ return SUCCESS;\n+ }\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ /* power on wifipll */\n+ if (pllType & GLB_PLL_WIFIPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &wifiPllCfg_960M[xtalType], 0);\n+ }\n+\n+ /* power on aupll */\n+ if (pllType & GLB_PLL_AUPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &audioPllCfg_442P368M[xtalType], 0);\n+ }\n+\n+ /* power on cpupll */\n+ if (pllType & GLB_PLL_CPUPLL) {\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &cpuPllCfg_380M[xtalType], 0);\n+ }\n+\n+ /* power on mipipll */\n+ if (pllType & GLB_PLL_MIPIPLL) {\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &mipiPllCfg_1500M[xtalType], 0);\n+ }\n+\n+ /* power on uhspll */\n+ if (pllType & GLB_PLL_UHSPLL) {\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &uhsPllCfg_2100M[xtalType], 0);\n+ }\n+\n+ arch_delay_us(75);\n+\n+ if (xtalType != GLB_XTAL_RC32M) {\n+ /* if power on xtal, always set xclk from xtal */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ }\n+\n+ /* enable all PLL clock output */\n+ /* GLB reg_pll_en = 1, cannot be zero */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+ /* MM_GLB reg_pll_en = 1, cannot be zero */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_PLL_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power off wifi audio cpu PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* cfg0 : pu_aupll=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* cfg0 : pu_aupll_sfreg=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB wifi audio cpu PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) {\n+ /* wifipll_refclk_sel different from other's pll, 1 means xtal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power on PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param cfg: GLB PLL configuration\n+ * @param waitStable: wait PLL clock stable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ /* unknown */\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* Step1:config parameter */\n+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);\n+\n+ /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);\n+\n+ /* cfg4:Set aupll_sel_sample_clk */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);\n+\n+ /* cfg5:Set aupll_vco_speed */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+\n+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);\n+\n+ /* Step2:config pu */\n+ /* cfg0 : pu_aupll_sfreg=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* cfg0 : pu_wifipll=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */\n+ if (GLB_WAC_PLL_AUPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) {\n+ /* 451.548 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14);\n+ } else {\n+ /* 442.368 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ }\n+\n+ /* Step4:enable output clock */\n+ /* wifipll : cfg5, wifipll_vco_div3_en=1 */\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+ }\n+ /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1);\n+ }\n+ /* cfg8 : wifipll/aupll/cpupll clock enable */\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6);\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);\n+\n+ if (waitStable) {\n+ /* Wait 1.5*30us */\n+ arch_delay_us(45);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB enable or disable USB clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* pu_usbpll_mmdiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+\n+ /* toggle usbpll_rstb */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);\n+ BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power off mipi uhs PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* cfg0 : pu_aupll=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* cfg0 : pu_aupll_sfreg=0 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB mipi uhs PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power on PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param cfg: GLB PLL configuration\n+ * @param waitStable: wait PLL stable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ /* unknown */\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* Step1:config parameter */\n+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ /* cfg4:Set aupll_sel_sample_clk */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);\n+\n+ /* cfg5:Set aupll_vco_speed */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+\n+ /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */\n+ if (GLB_MU_PLL_UHSPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ }\n+\n+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);\n+\n+ /* Step2:config pu */\n+ /* cfg0 : pu_aupll_sfreg=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* cfg0 : pu_wifipll=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ if (waitStable) {\n+ /* Wait 1.5*30us */\n+ arch_delay_us(45);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set System clock divider\n+ *\n+ * @param mcuClkDiv: HCLK divider\n+ * @param mcuPBclkDiv: BCLK divider\n+ * @param lpClkDiv: LP clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeout = 1024;\n+ HBN_MCU_XCLK_Type xclkSel;\n+ HBN_MCU_ROOT_CLK_Type rootClkSel;\n+\n+ /* get root clock */\n+ xclkSel = HBN_Get_MCU_XCLK_Sel();\n+ rootClkSel = HBN_Get_MCU_Root_CLK_Sel();\n+\n+ if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ }\n+\n+ /* config hclk_div=mcuClkDiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+\n+ /* config bclk_div=mcuPBclkDiv */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);\n+ /* bclk act pulse */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);\n+\n+ timeout = 1024;\n+ do {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* config lp clock div=lpClkDiv */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, lpClkDiv);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);\n+ /* bclk act pulse */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PICO_CLK_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);\n+\n+ timeout = 1024;\n+ do {\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* recover root clock */\n+ HBN_Set_MCU_XCLK_Sel(xclkSel);\n+ HBN_Set_MCU_Root_CLK_Sel(rootClkSel);\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get System clock divider\n+ *\n+ * @param mcuClkDiv: HCLK divider\n+ * @param mcuPBclkDiv: BCLK divider\n+ * @param lpClkDiv: LP clock divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv)\n+{\n+ *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV);\n+ *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);\n+ *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set mcu System clock\n+ *\n+ * @param clkFreq: mcu system clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq)\n+{\n+ uint32_t tmpVal;\n+ HBN_MCU_XCLK_Type mcuXclkSel;\n+\n+ CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq));\n+\n+ /* get xclk&&rootclk clock */\n+ mcuXclkSel = HBN_Get_MCU_XCLK_Sel();\n+\n+ /* change root clock to rc32m */\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+\n+ /* select pll output clock before select root clock */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);\n+ switch (clkFreq) {\n+ case GLB_MCU_SYS_CLK_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);\n+\n+ /* select root clock */\n+ switch (clkFreq) {\n+ case GLB_MCU_SYS_CLK_RC32M:\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_MCU_SYS_CLK_XTAL:\n+ GLB_Set_MCU_System_CLK_Div(0, 0, 0);\n+ HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_MCU_SYS_CLK_CPUPLL_400M:\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(1, 2, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ /* unuseful for mcu, useful for dsp, just for safe */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_240M:\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(0, 2, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ /* unuseful for mcu, useful for dsp, just for safe */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ case GLB_MCU_SYS_CLK_WIFIPLL_320M:\n+ /* overclock, not recommended */\n+ /* For high speed, set DIV first */\n+ GLB_Set_MCU_System_CLK_Div(0, 3, 1);\n+ /* Set IROM 2T Access 0 since we use RC32M, unuseful now */\n+ /* MCU_MISC_IROM_2T_Access_Set(0); */\n+ HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ HBN_Set_MCU_XCLK_Sel(mcuXclkSel);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP0 DSP1 clock div\n+ *\n+ * @param dspClkDiv: mm glb cpu div\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeout = 1024;\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+ GLB_DSP_ROOT_CLK_Type dspRootClkSel;\n+\n+ /* get root clock */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+ dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel();\n+\n+ /* change root clock to rc32m */\n+ if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) {\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ }\n+\n+ /* set div */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV, dspBclkDiv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV, dspClkDiv);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV_ACT_PULSE, 1);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ do {\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_STS_BCLK2X_PROT_DONE);\n+ } while ((--timeout) && (!tmpVal));\n+ if (!timeout) {\n+ return ERROR;\n+ }\n+\n+ /* recover root clock */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ GLB_Set_DSP_ROOT_CLK_Sel(dspRootClkSel);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP0 DSP1 clock div\n+ *\n+ * @param dspClkDiv: mm glb cpu div\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);\n+ *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set dsp System clock\n+ *\n+ * @param clkFreq: dsp system clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq)\n+{\n+ GLB_DSP_XCLK_Type dspXclkSel;\n+\n+ CHECK_PARAM(IS_GLB_DSP_SYS_CLK_TYPE(clkFreq));\n+\n+ /* get root clock */\n+ dspXclkSel = GLB_Get_DSP_XCLK_Sel();\n+\n+ /* Before config XTAL and PLL ,make sure root clk is from RC32M */\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+\n+ /* select pll output clock before select root clock */\n+ if (GLB_DSP_SYS_CLK_MM_WIFIPLL_240M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_240M);\n+ } else if (GLB_DSP_SYS_CLK_MM_WIFIPLL_320M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_320M);\n+ } else if (GLB_DSP_SYS_CLK_CPUPLL_400M == clkFreq) {\n+ GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_CPUPLL_400M);\n+ }\n+\n+ /* select root clock */\n+ switch (clkFreq) {\n+ case GLB_DSP_SYS_CLK_RC32M:\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_DSP_SYS_CLK_XTAL:\n+ GLB_Set_DSP_System_CLK_Div(0, 0);\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK);\n+ break;\n+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_240M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ case GLB_DSP_SYS_CLK_MM_WIFIPLL_320M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_320M);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ case GLB_DSP_SYS_CLK_CPUPLL_400M:\n+ GLB_Set_DSP_System_CLK_Div(0, 1);\n+ GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL);\n+ /* recover xclk */\n+ GLB_Set_DSP_XCLK_Sel(dspXclkSel);\n+ break;\n+ default:\n+ break;\n+ }\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP0 pbus clock div\n+ *\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* set div */\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV, dspPBclkDiv);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP0 pbus clock div\n+ *\n+ * @param dspBclkDiv: mm glb bclk2x div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv)\n+{\n+ *dspPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU), MM_GLB_REG_BCLK1X_DIV);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set dsp pbus clock\n+ *\n+ * @param pbClkSel: dsp pbus clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel)\n+{\n+ CHECK_PARAM(IS_GLB_DSP_SYS_PBCLK_TYPE(pbClkSel));\n+\n+ GLB_Set_DSP_PBCLK_Div(0);\n+\n+ /* select pbroot clock */\n+ switch (pbClkSel) {\n+ case GLB_DSP_SYS_PBCLK_RC32M:\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_XTAL:\n+ GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M:\n+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_160M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_CPUPLL_160M:\n+ GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_CPUPLL_160M);\n+ GLB_Set_DSP_PBCLK_Div(0);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M);\n+ break;\n+ case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M:\n+ GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M);\n+ GLB_Set_DSP_PBCLK_Div(1);\n+ GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M);\n+ break;\n+ default:\n+ break;\n+ }\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP0 clock enable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief DSP0 clock disable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get xclk clock source Select\n+ *\n+ * @param None\n+ *\n+ * @return xclk clock type selection\n+ *\n+*******************************************************************************/\n+GLB_DSP_XCLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_XCLK_Sel(void)\n+{\n+ return (GLB_DSP_XCLK_Type)(BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU), MM_GLB_REG_XCLK_CLK_SEL));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select xclk clock source\n+ *\n+ * @param xclk: xclk clock type selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_XCLK_TYPE(xclk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP root clock\n+ *\n+ * @param None\n+ *\n+ * @return mm glb root clock type\n+ *\n+*******************************************************************************/\n+GLB_DSP_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_ROOT_CLK_Sel(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t rootclk = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);\n+ if (0 == rootclk) {\n+ /* xclk */\n+ return GLB_DSP_ROOT_CLK_XCLK;\n+ } else {\n+ /* pll */\n+ return GLB_DSP_ROOT_CLK_PLL;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP root clock\n+ *\n+ * @param rootClk: mm glb root clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_ROOT_CLK_TYPE(rootClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (rootClk) {\n+ case GLB_DSP_ROOT_CLK_XCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 0);\n+ break;\n+ case GLB_DSP_ROOT_CLK_PLL:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 1);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP muxpll clock\n+ *\n+ * @param pllClk: mm glb pll clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PLL_CLK_TYPE(pllClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (pllClk) {\n+ case GLB_DSP_PLL_CLK_MUXPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 0);\n+ break;\n+ case GLB_DSP_PLL_CLK_MUXPLL_320M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 1);\n+ break;\n+ case GLB_DSP_PLL_CLK_CPUPLL_400M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 2);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get DSP pbroot clock\n+ *\n+ * @param None\n+ *\n+ * @return mm DSP pbroot clock type\n+ *\n+*******************************************************************************/\n+GLB_DSP_PBROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBROOT_CLK_Sel(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t pbrootclk = 0;\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);\n+ switch (pbrootclk) {\n+ case 0:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ case 1:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ case 2:\n+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M;\n+ case 3:\n+ return GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M;\n+ default:\n+ return GLB_DSP_PBROOT_CLK_MM_XCLK;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief select DSP pbroot clock\n+ *\n+ * @param pbrootClk: mm DSP pbroot clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_DSP_PBROOT_CLK_TYPE(pbrootClk));\n+\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU);\n+ switch (pbrootClk) {\n+ case GLB_DSP_PBROOT_CLK_MM_XCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 0);\n+ break;\n+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 2);\n+ break;\n+ case GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal);\n+ GLB_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set CPU reset address\n+ *\n+ * @param coreID: core type\n+ * @param addr: reset address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr)\n+{\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU0_BOOT, addr);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief hold cpu\n+ *\n+ * @param coreID: core type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Halt_CPU(GLB_CORE_ID_Type coreID)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ PDS_Set_MCU0_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ GLB_DSP0_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ PDS_Set_LP_Clock_Disable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief release cpu\n+ *\n+ * @param coreID: core type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Release_CPU(GLB_CORE_ID_Type coreID)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));\n+\n+ switch (coreID) {\n+ case GLB_CORE_ID_M0:\n+ PDS_Set_MCU0_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ GLB_DSP0_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET);\n+ BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ PDS_Set_LP_Clock_Enable();\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);\n+ break;\n+ default:\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MTimer clock\n+ *\n+ * @param enable: enable or disable\n+ * @param clkSel: clock selection\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_GLB_EMI_CLK_TYPE(clkSel));\n+ CHECK_PARAM((div <= 0x3));\n+\n+ /* disable EMI clock first */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ switch (clkSel) {\n+ case GLB_EMI_CLK_MCU_PBCLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 0);\n+ break;\n+ case GLB_EMI_CLK_CPUPLL_200M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 4);\n+ break;\n+ case GLB_EMI_CLK_WIFIPLL_320M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 2);\n+ break;\n+ case GLB_EMI_CLK_CPUPLL_400M_CLK:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV, div);\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN);\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* clear EMI swrst bit */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC);\n+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal);\n+\n+ /* set EMI cgen bit */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure WIFIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 0);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure AUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 0);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure CPUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 0);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 0);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock div\n+ *\n+ * @param divEn: div enable\n+ * @param divRatio: div ratio\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+ \n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ \n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure UHSPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 0);\n+ \n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get core type\n+ *\n+ * @param None\n+ *\n+ * @return core type\n+ *\n+*******************************************************************************/\n+GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_WORD(CORE_ID_ADDRESS);\n+\n+ switch (tmpVal) {\n+ case CORE_ID_M0:\n+ return GLB_CORE_ID_M0;\n+ case CORE_ID_D0:\n+ return GLB_CORE_ID_D0;\n+ case CORE_ID_LP:\n+ return GLB_CORE_ID_LP;\n+ default:\n+ return GLB_CORE_ID_INVALID;\n+ }\n+\n+ return GLB_CORE_ID_INVALID;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get first 1 from u64, then clear it\n+ *\n+ * @param val: target value\n+ * @param bit: first 1 in bit\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)\n+{\n+ if (!*val) {\n+ return ERROR;\n+ }\n+\n+ for (uint8_t i = 0; i < 64; i++) {\n+ if ((*val) & ((uint64_t)1 << i)) {\n+ *bit = i;\n+ (*val) &= ~((uint64_t)1 << i);\n+ break;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief hold IPs clock\n+ *\n+ * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)\n+{\n+ /* api request from cjy */\n+\n+ uint32_t tmpValCfg0 = 0;\n+ uint32_t tmpValCfg1 = 0;\n+ uint32_t tmpValCfg2 = 0;\n+ uint32_t bitfield = 0;\n+\n+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);\n+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ while (ips) {\n+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {\n+ switch (bitfield) {\n+ case GLB_AHB_CLOCK_IP_CPU:\n+ tmpValCfg0 &= ~(1 << 0);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDU:\n+ tmpValCfg0 &= ~(1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SEC:\n+ tmpValCfg0 &= ~(1 << 2);\n+ tmpValCfg1 &= ~(1 << 3);\n+ tmpValCfg1 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_0:\n+ tmpValCfg0 &= ~(1 << 3);\n+ tmpValCfg1 &= ~(1 << 12);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_1:\n+ tmpValCfg0 &= ~(1 << 3);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_2:\n+ tmpValCfg0 &= ~(1 << 3);\n+ tmpValCfg2 &= ~(1 << 24);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CCI:\n+ tmpValCfg0 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_RF_TOP:\n+ tmpValCfg1 &= ~(1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GPIP:\n+ tmpValCfg1 &= ~(1 << 2);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TZC:\n+ tmpValCfg1 &= ~(1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EF_CTRL:\n+ tmpValCfg1 &= ~(1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SF_CTRL:\n+ tmpValCfg1 &= ~(1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMAC:\n+ tmpValCfg2 &= ~(1 << 19);\n+ tmpValCfg2 &= ~(1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART0:\n+ tmpValCfg1 &= ~(1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART1:\n+ tmpValCfg1 &= ~(1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART2:\n+ tmpValCfg1 &= ~(1 << 26);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART3:\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART4:\n+ break;\n+ case GLB_AHB_CLOCK_IP_SPI:\n+ tmpValCfg1 &= ~(1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C:\n+ tmpValCfg1 &= ~(1 << 19);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PWM:\n+ tmpValCfg1 &= ~(1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TIMER:\n+ tmpValCfg1 &= ~(1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_IR:\n+ tmpValCfg1 &= ~(1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CHECKSUM:\n+ tmpValCfg1 &= ~(1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_QDEC:\n+ break;\n+ case GLB_AHB_CLOCK_IP_KYS:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2S:\n+ tmpValCfg1 &= ~(1 << 27);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB11:\n+ break;\n+ case GLB_AHB_CLOCK_IP_CAM:\n+ break;\n+ case GLB_AHB_CLOCK_IP_MJPEG:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:\n+ tmpValCfg2 &= ~(1 << 8);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:\n+ tmpValCfg2 &= ~(1 << 9);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:\n+ tmpValCfg2 &= ~(1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:\n+ tmpValCfg2 &= ~(1 << 10);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMI_MISC:\n+ tmpValCfg2 &= ~(1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:\n+ tmpValCfg2 &= ~(1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:\n+ tmpValCfg2 &= ~(1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB20:\n+ tmpValCfg1 &= ~(1 << 13);\n+ break;\n+ case GLB_AHB_CLOCK_IP_MIX2:\n+ tmpValCfg2 &= ~(1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUDIO:\n+ tmpValCfg2 &= ~(1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDH:\n+ tmpValCfg2 &= ~(1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:\n+ tmpValCfg2 &= ~(1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C1:\n+ tmpValCfg1 &= ~(1 << 25);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PHY:\n+ tmpValCfg0 &= ~(1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:\n+ tmpValCfg0 &= ~(1 << 6);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:\n+ tmpValCfg0 &= ~(1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_LZ4:\n+ tmpValCfg1 &= ~(1 << 29);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUPDM:\n+ tmpValCfg1 &= ~(1 << 28);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GAUGE:\n+ tmpValCfg1 &= ~(1 << 0);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief release IPs clock\n+ *\n+ * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... (not GLB_AHB_CLOCK_IP_xxx)\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)\n+{\n+ /* api request from cjy */\n+\n+ uint32_t tmpValCfg0 = 0;\n+ uint32_t tmpValCfg1 = 0;\n+ uint32_t tmpValCfg2 = 0;\n+ uint32_t bitfield = 0;\n+\n+ tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);\n+ tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);\n+ tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);\n+ while (ips) {\n+ if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {\n+ switch (bitfield) {\n+ case GLB_AHB_CLOCK_IP_CPU:\n+ tmpValCfg0 |= (1 << 0);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDU:\n+ tmpValCfg0 |= (1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SEC:\n+ tmpValCfg0 |= (1 << 2);\n+ tmpValCfg1 |= (1 << 3);\n+ tmpValCfg1 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_0:\n+ tmpValCfg0 |= (1 << 3);\n+ tmpValCfg1 |= (1 << 12);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_1:\n+ tmpValCfg0 |= (1 << 3);\n+ break;\n+ case GLB_AHB_CLOCK_IP_DMA_2:\n+ tmpValCfg0 |= (1 << 3);\n+ tmpValCfg2 |= (1 << 24);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CCI:\n+ tmpValCfg0 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_RF_TOP:\n+ tmpValCfg1 |= (1 << 1);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GPIP:\n+ tmpValCfg1 |= (1 << 2);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TZC:\n+ tmpValCfg1 |= (1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EF_CTRL:\n+ tmpValCfg1 |= (1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SF_CTRL:\n+ tmpValCfg1 |= (1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMAC:\n+ tmpValCfg2 |= (1 << 19);\n+ tmpValCfg2 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART0:\n+ tmpValCfg1 |= (1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART1:\n+ tmpValCfg1 |= (1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART2:\n+ tmpValCfg1 |= (1 << 26);\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART3:\n+ break;\n+ case GLB_AHB_CLOCK_IP_UART4:\n+ break;\n+ case GLB_AHB_CLOCK_IP_SPI:\n+ tmpValCfg1 |= (1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C:\n+ tmpValCfg1 |= (1 << 19);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PWM:\n+ tmpValCfg1 |= (1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_TIMER:\n+ tmpValCfg1 |= (1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_IR:\n+ tmpValCfg1 |= (1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_CHECKSUM:\n+ tmpValCfg1 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_QDEC:\n+ break;\n+ case GLB_AHB_CLOCK_IP_KYS:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2S:\n+ tmpValCfg1 |= (1 << 23);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB11:\n+ break;\n+ case GLB_AHB_CLOCK_IP_CAM:\n+ break;\n+ case GLB_AHB_CLOCK_IP_MJPEG:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:\n+ tmpValCfg2 |= (1 << 8);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_NORMAL:\n+ tmpValCfg2 |= (1 << 9);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_NORMAL:\n+ tmpValCfg2 |= (1 << 4);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:\n+ tmpValCfg2 |= (1 << 10);\n+ break;\n+ case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_EMI_MISC:\n+ tmpValCfg2 |= (1 << 16);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:\n+ tmpValCfg2 |= (1 << 17);\n+ break;\n+ case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:\n+ tmpValCfg2 |= (1 << 18);\n+ break;\n+ case GLB_AHB_CLOCK_IP_USB20:\n+ tmpValCfg1 |= (1 << 13);\n+ break;\n+ case GLB_AHB_CLOCK_IP_MIX2:\n+ tmpValCfg2 |= (1 << 20);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUDIO:\n+ tmpValCfg2 |= (1 << 21);\n+ break;\n+ case GLB_AHB_CLOCK_IP_SDH:\n+ tmpValCfg2 |= (1 << 22);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_NORMAL:\n+ tmpValCfg2 |= (1 << 11);\n+ break;\n+ case GLB_AHB_CLOCK_IP_ZB2_LP:\n+ break;\n+ case GLB_AHB_CLOCK_IP_I2C1:\n+ tmpValCfg1 |= (1 << 25);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PHY:\n+ tmpValCfg0 |= (1 << 7);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:\n+ tmpValCfg0 |= (1 << 6);\n+ break;\n+ case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:\n+ tmpValCfg0 |= (1 << 5);\n+ break;\n+ case GLB_AHB_CLOCK_IP_LZ4:\n+ tmpValCfg1 |= (1 << 29);\n+ break;\n+ case GLB_AHB_CLOCK_IP_AUPDM:\n+ tmpValCfg1 |= (1 << 28);\n+ break;\n+ case GLB_AHB_CLOCK_IP_GAUGE:\n+ tmpValCfg1 |= (1 << 0);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ }\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);\n+ BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief software reset\n+ *\n+ * @param swrst: reset num\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t bit = 0;\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst));\n+\n+ if (swrst < 32) {\n+ bit = swrst;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET;\n+ } else if (swrst < 64) {\n+ bit = swrst - 32;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET;\n+ } else if (swrst < 96) {\n+ bit = swrst - 64;\n+ regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal |= (1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief software reset\n+ *\n+ * @param swrst: reset num\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t bit = 0;\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_GLB_AHB_DSP_SW_TYPE(swrst));\n+\n+ if (swrst < 32) {\n+ bit = swrst;\n+ regAddr = MM_GLB_BASE + MM_GLB_MM_SW_SYS_RESET_OFFSET;\n+ } else if (swrst < 64) {\n+ bit = swrst - 32;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET;\n+ } else if (swrst < 96) {\n+ bit = swrst - 64;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_DSP2_SUB_OFFSET;\n+ } else if (swrst < 128) {\n+ bit = swrst - 96;\n+ regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET;\n+ } else if (swrst < 160) {\n+ bit = swrst - 128;\n+ regAddr = MM_GLB_BASE + MM_GLB_IMAGE_SENSOR_CTRL_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal |= (1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+ BL_DRV_DUMMY;\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal &= ~(1 << bit);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group GLB_Public_Functions */\n+\n+/*@} end of group GLB */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f77cf0b4e44b73119b97d1721673e225be8be633\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c\n@@ -0,0 +1,2136 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_hbn.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_hbn.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_xip_sflash.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup HBN\n+ * @{\n+ */\n+\n+/** @defgroup HBN_Private_Macros\n+ * @{\n+ */\n+#define HBN_CLK_SET_DUMMY_WAIT \\\n+ { \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ __NOP(); \\\n+ }\n+\n+/*@} end of group HBN_Private_Macros */\n+\n+/** @defgroup HBN_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group HBN_Private_Types */\n+\n+/** @defgroup HBN_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_INT_MAX] = { NULL };\n+static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_INT_MAX] = { NULL };\n+#endif\n+\n+/*@} end of group HBN_Private_Variables */\n+\n+/** @defgroup HBN_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group HBN_Global_Variables */\n+\n+/** @defgroup HBN_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group HBN_Private_Fun_Declaration */\n+\n+/** @defgroup HBN_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group HBN_Private_Functions */\n+\n+/** @defgroup HBN_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Enter HBN\n+ *\n+ * @param cfg: HBN APP Config\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)\n+{\n+ uint32_t valLow = 0, valHigh = 0;\n+ uint64_t val;\n+\n+ if (cfg->useXtal32k) {\n+ HBN_32K_Sel(HBN_32K_XTAL);\n+ } else {\n+ HBN_32K_Sel(HBN_32K_RC);\n+ HBN_Power_Off_Xtal_32K();\n+ }\n+\n+ /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */\n+ HBN_Hw_Pu_Pd_Cfg(DISABLE);\n+\n+ HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));\n+ if (cfg->gpioWakeupSrc != 0) {\n+ HBN_GPIO_INT_Enable(cfg->gpioTrigType);\n+ }\n+\n+ /* HBN RTC config and enable */\n+ HBN_Clear_RTC_Counter();\n+ if (cfg->sleepTime != 0) {\n+ HBN_Get_RTC_Timer_Val(&valLow, &valHigh);\n+ val = valLow + ((uint64_t)valHigh << 32);\n+ val += cfg->sleepTime;\n+ HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);\n+ HBN_Enable_RTC_Counter();\n+ }\n+\n+ HBN_Power_Down_Flash(cfg->flashCfg);\n+ //HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */\n+\n+ GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);\n+ GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_RC32M);\n+ GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_RC32M);\n+\n+ HBN_Enable(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel, cfg->dcdcPuSeq);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power down and switch clock\n+ *\n+ * @param flashCfg: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ SPI_Flash_Cfg_Type bhFlashCfg;\n+\n+ if (flashCfg == NULL) {\n+ L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));\n+ XIP_SFlash_Read_Via_Cache_Need_Lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg),\n+ sizeof(SPI_Flash_Cfg_Type), 0, 0);\n+ L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));\n+\n+ SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);\n+ SFlash_Reset_Continue_Read(&bhFlashCfg);\n+ } else {\n+ SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);\n+ SFlash_Reset_Continue_Read(flashCfg);\n+ }\n+\n+ SFlash_Powerdown();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable HBN mode\n+ *\n+ * @param aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to\n+ * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.\n+ * @param ldoLevel: LDO volatge level\n+ * @param hbnLevel: HBN work level\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_TCM_SECTION HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+ CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));\n+\n+ /* Setting from guide */\n+ /* HBN_SRAM Retion */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);\n+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);\n+\n+ /* AON GPIO IE */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ /* HBN mode LDO level */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ /* power on dcdc11&&dcdc18 sequence */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ if (dcdcPuSeq) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC_AON);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC_AON);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);\n+ }\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ /* Select RC32M */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+\n+ /* Set HBN flag */\n+ BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */\n+ switch (hbnLevel) {\n+ case HBN_LEVEL_0:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);\n+ break;\n+\n+ case HBN_LEVEL_1:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ /* Set power on option:0 for por reset twice for robust 1 for reset only once*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ /* Enable HBN mode */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ while (1) {\n+ arch_delay_ms(1000);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Reset HBN mode\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Reset HBN mode */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable HBN PIR\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_PIR_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable HBN PIR\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_PIR_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Config HBN PIR interrupt\n+ *\n+ * @param pirIntCfg: HBN PIR interrupt configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t bit4 = 0;\n+ uint32_t bit5 = 0;\n+ uint32_t bitVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+\n+ /* low trigger interrupt */\n+ if (pirIntCfg->lowIntEn == ENABLE) {\n+ bit5 = 0;\n+ } else {\n+ bit5 = 1;\n+ }\n+\n+ /* high trigger interrupt */\n+ if (pirIntCfg->highIntEn == ENABLE) {\n+ bit4 = 0;\n+ } else {\n+ bit4 = 1;\n+ }\n+\n+ bitVal = bit4 | (bit5 << 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select HBN PIR low pass filter\n+ *\n+ * @param lpf: HBN PIR low pass filter selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select HBN PIR high pass filter\n+ *\n+ * @param hpf: HBN PIR high pass filter selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set HBN PIR threshold value\n+ *\n+ * @param threshold: HBN PIR threshold value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((threshold <= 0x3FFF));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get HBN PIR threshold value\n+ *\n+ * @param None\n+ *\n+ * @return HBN PIR threshold value\n+ *\n+*******************************************************************************/\n+uint16_t HBN_Get_PIR_Threshold(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set HBN PIR interval value\n+ *\n+ * @param interval: HBN PIR interval value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((interval <= 0xFFF));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);\n+ BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get HBN PIR interval value\n+ *\n+ * @param None\n+ *\n+ * @return HBN PIR interval value\n+ *\n+*******************************************************************************/\n+uint16_t HBN_Get_PIR_Interval(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get HBN bod out state\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type HBN_Get_BOD_OUT_State(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOD_OUT) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set HBN bod config\n+ *\n+ * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset\n+ * @param threshold: bod threshold\n+ * @param mode: bod work mode with por\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_BOD_THRES_TYPE(threshold));\n+ CHECK_PARAM(IS_HBN_BOD_MODE_TYPE(mode));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 0);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, threshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_SEL, mode);\n+ BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN set ldo11aon voltage out\n+ *\n+ * @param ldoLevel: LDO volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN set ldo11rt voltage out\n+ *\n+ * @param ldoLevel: LDO volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************\n+ * @brief HBN set ldo11_Rtc voltage out\n+ *\n+ * @param ldoLevel: LDO11_Rtc volatge level\n+ * 0:0.60V 1:0.65V 2:0.70V 3:0.75V\n+ * 4:0.80V 5:0.85V 6:0.9V 7:0.95V\n+ * 8:1.0V 9:1.05V 10:1.1V 11:1.15V,\n+ * 12:1.2V 13:1.25V 14:1.3V 15:1.35V\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+ *******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ HBN_RTC_MISC_Type rtcMiscCfg;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);\n+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;\n+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN set ldo11 all voltage out, not include dcdc11\n+ *\n+ * @param ldoLevel: LDO volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+ * @note not support LDO11_Rtc 0.65v & 0.6v\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ uint32_t tmpVal;\n+ HBN_RTC_MISC_Type rtcMiscCfg;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);\n+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;\n+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN select 32K\n+ *\n+ * @param clkType: HBN 32k clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));\n+\n+ HBN_Trim_RC32K();\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select uart clock source\n+ *\n+ * @param clkSel: uart clock type selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ if ((HBN_UART_CLK_MCU_PBCLK == clkSel) || (HBN_UART_CLK_160M == clkSel)) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);\n+ } else {\n+ /* mcu_bclk as default */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, 0);\n+ }\n+\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get xclk clock source Select\n+ *\n+ * @param None\n+ *\n+ * @return xclk clock type selection\n+ *\n+*******************************************************************************/\n+HBN_MCU_XCLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_XCLK_Sel(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);\n+\n+ return (HBN_MCU_XCLK_Type)(tmpVal & 0x1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select xclk clock source\n+ *\n+ * @param xclk: xclk clock type selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_MCU_XCLK_TYPE(xclk));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);\n+ switch (xclk) {\n+ case HBN_MCU_XCLK_RC32M:\n+ tmpVal2 &= (~(1 << 0));\n+ break;\n+ case HBN_MCU_XCLK_XTAL:\n+ tmpVal2 |= (1 << 0);\n+ break;\n+ default:\n+ break;\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+ HBN_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get root clock selection\n+ *\n+ * @param None\n+ *\n+ * @return root clock selection\n+ *\n+*******************************************************************************/\n+HBN_MCU_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_Root_CLK_Sel(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t rootClkSel = 0;\n+\n+ /* root_clock_select = hbn_root_clk_sel[1] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ rootClkSel = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL) >> 1;\n+ if (0 == rootClkSel) {\n+ return HBN_MCU_ROOT_CLK_XCLK;\n+ } else {\n+ return HBN_MCU_ROOT_CLK_PLL;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Select root clk source\n+ *\n+ * @param rootClk: root clock type selection\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_MCU_ROOT_CLK_TYPE(rootClk));\n+\n+ /* root_clock_select = hbn_root_clk_sel[1] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);\n+ switch (rootClk) {\n+ case HBN_MCU_ROOT_CLK_XCLK:\n+ tmpVal2 &= 0x1; //[1]=0\n+ break;\n+ case HBN_MCU_ROOT_CLK_PLL:\n+ tmpVal2 |= 0x2; //[1]=1\n+ break;\n+ default:\n+ break;\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+ HBN_CLK_SET_DUMMY_WAIT;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set HBN_RAM sleep mode\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_slp(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);\n+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set HBN_RAM retension mode\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_Ret(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);\n+ BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on XTAL 32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);\n+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);\n+\n+ /* Delay >1s */\n+ arch_delay_us(1100);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off XTAL 32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);\n+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power on RC32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);\n+\n+ /* Delay >800us */\n+ arch_delay_us(880);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off RC3K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Trim RC32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)\n+{\n+ Efuse_Ana_RC32K_Trim_Type trim;\n+ int32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_RC32K_Trim(&trim);\n+ if (trim.trimRc32kExtCodeEn) {\n+ if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);\n+ BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);\n+ arch_delay_us(2);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/**\n+ * @brief Power Off RC32K in all state\n+ *\n+ * @return BL_Err_Type\n+ */\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_All_State(void)\n+{\n+ int32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);\n+ HBN_Power_Off_RC32K();\n+ return SUCCESS;\n+}\n+\n+/**\n+ * @brief Power Off RC32K In power off state\n+ *\n+ * @return BL_Err_Type\n+ */\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_In_Poff(void)\n+{\n+ int32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);\n+ HBN_Power_Off_RC32K();\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get HBN status flag\n+ *\n+ * @param None\n+ *\n+ * @return HBN status flag value\n+ *\n+*******************************************************************************/\n+uint32_t HBN_Get_Status_Flag(void)\n+{\n+ return BL_RD_REG(HBN_BASE, HBN_RSV0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set HBN status flag\n+ *\n+ * @param flag: Status Flag\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)\n+{\n+ BL_WR_REG(HBN_BASE, HBN_RSV0, flag);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get HBN wakeup address\n+ *\n+ * @param None\n+ *\n+ * @return HBN wakeup address\n+ *\n+*******************************************************************************/\n+uint32_t HBN_Get_Wakeup_Addr(void)\n+{\n+ return BL_RD_REG(HBN_BASE, HBN_RSV1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set HBN wakeup address\n+ *\n+ * @param addr: HBN wakeup address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)\n+{\n+ BL_WR_REG(HBN_BASE, HBN_RSV1, addr);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get core reboot flag\n+ *\n+ * @param None\n+ *\n+ * @return repower flag\n+ *\n+*******************************************************************************/\n+uint8_t ATTR_TCM_SECTION HBN_Get_Core_Unhalt_Config(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);\n+ }\n+\n+ return 0x00;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set core reboot flag\n+ *\n+ * @param core: core ID\n+ * @param hcfg: reboot cfg\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t unhalt = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);\n+ unhalt = BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);\n+ if (hcfg) {\n+ unhalt |= (1 << core);\n+ } else {\n+ unhalt &= ~(1 << core);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT, unhalt);\n+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get MM power flag\n+ *\n+ * @param None\n+ *\n+ * @return repower flag\n+ *\n+*******************************************************************************/\n+uint8_t ATTR_TCM_SECTION HBN_Get_MM_Power_Config(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_POWER_ON_MM);\n+ }\n+\n+ return 0x00;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set MM power flag\n+ *\n+ * @param pcfg: power cfg\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_MM_Power_Config(uint8_t pcfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);\n+ if (pcfg) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_POWER_ON_MM);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_POWER_ON_MM);\n+ }\n+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get hand off config\n+ *\n+ * @param None\n+ *\n+ * @return hand off config\n+ *\n+*******************************************************************************/\n+uint8_t HBN_Get_Hand_Off_Config(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {\n+ return BL_GET_REG_BITS_VAL(tmpVal, HBN_HAND_OFF_SEL);\n+ }\n+\n+ return 0x00;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set hand off config\n+ *\n+ * @param dcfg: hand off config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_Hand_Off_Config(uint8_t dcfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_HAND_OFF_SEL, dcfg);\n+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get ldo18flash repower flag\n+ *\n+ * @param None\n+ *\n+ * @return repower flag\n+ *\n+*******************************************************************************/\n+uint16_t ATTR_TCM_SECTION HBN_Get_Ldo18flash_Repower_Config(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ if (HBN_REPOWER_LDO18FLASH_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH)) {\n+ return (uint16_t)tmpVal;\n+ }\n+\n+ return 0x0000;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set ldo18flash repower flag\n+ *\n+ * @param delay: repower delay time\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo18flash_Repower_Delay(uint8_t delay)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH, HBN_REPOWER_LDO18FLASH_FLAG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REPOWER_LDO18FLASH_DLY, delay);\n+ BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set Xtal type\n+ *\n+ * @param xtalType:Xtal type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Xtal_Type(uint8_t xtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);\n+\n+ tmpVal = tmpVal & 0xffff0000;\n+ tmpVal |= HBN_XTAL_FLAG_VALUE;\n+ tmpVal |= xtalType;\n+\n+ BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Xtal type\n+ *\n+ * @param None\n+ *\n+ * @return Xtal type\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Type(uint8_t *xtalType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);\n+\n+ if ((tmpVal & HBN_XTAL_FLAG_MASK) == HBN_XTAL_FLAG_VALUE) {\n+ *xtalType = (tmpVal & 0xff);\n+ return SUCCESS;\n+ } else {\n+ *xtalType = 0;\n+ return ERROR;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Xtal value\n+ *\n+ * @param xtalVal:Xtal value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Value(uint32_t *xtalVal)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t xtalType = 0;\n+\n+ if (NULL == xtalVal) {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);\n+ if ((tmpVal & HBN_XTAL_FLAG_MASK) == HBN_XTAL_FLAG_VALUE) {\n+ xtalType = (tmpVal & 0xff);\n+ switch(xtalType){\n+ case GLB_XTAL_NONE:\n+ *xtalVal = 0;\n+ break;\n+ case GLB_XTAL_24M:\n+ *xtalVal = 24000000;\n+ break;\n+ case GLB_XTAL_32M:\n+ *xtalVal = 32000000;\n+ break;\n+ case GLB_XTAL_38P4M:\n+ *xtalVal = 38400000;\n+ break;\n+ case GLB_XTAL_40M:\n+ *xtalVal = 40000000;\n+ break;\n+ case GLB_XTAL_26M:\n+ *xtalVal = 26000000;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ *xtalVal = 32000000;\n+ break;\n+ default :\n+ *xtalVal = 0;\n+ break;\n+ }\n+ return SUCCESS;\n+ }\n+\n+ *xtalVal = 0;\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN clear RTC timer counter\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_RTC_Counter(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Clear RTC control bit0 */\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN clear RTC timer counter\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Enable_RTC_Counter(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Set RTC control bit0 */\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN set RTC timer configuration\n+ *\n+ * @param delay: RTC interrupt delay 32 clocks\n+ * @param compValLow: RTC interrupt commpare value low 32 bits\n+ * @param compValHigh: RTC interrupt commpare value high 32 bits\n+ * @param compMode: RTC interrupt commpare\n+ * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));\n+\n+ BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);\n+ BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Set interrupt delay option */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);\n+ /* Set RTC compare mode */\n+ tmpVal |= (compMode << 1);\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN get RTC timer count value\n+ *\n+ * @param valLow: RTC count value pointer for low 32 bits\n+ * @param valHigh: RTC count value pointer for high 8 bits\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Tigger RTC val read */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);\n+\n+ /* Read RTC val */\n+ *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);\n+ *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Clear_RTC_INT(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);\n+ /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */\n+ BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable GPIO interrupt\n+ *\n+ * @param gpioIntTrigType: HBN GPIO interrupt trigger type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable GPIO interrupt\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_GPIO_INT_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN get interrupt status\n+ *\n+ * @param irqType: HBN interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ATTR_TCM_SECTION HBN_Get_INT_State(HBN_INT_Type irqType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);\n+\n+ if (tmpVal & (1 << irqType)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN get pin wakeup mode value\n+ *\n+ * @param None\n+ *\n+ * @return HBN pin wakeup mode value\n+ *\n+*******************************************************************************/\n+uint8_t HBN_Get_Pin_Wakeup_Mode(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN clear interrupt status\n+ *\n+ * @param irqType: HBN interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_IRQ(HBN_INT_Type irqType)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_HBN_INT_TYPE(irqType));\n+\n+ /* set clear bit */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);\n+ tmpVal |= (1 << irqType);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);\n+\n+ /* unset clear bit */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);\n+ tmpVal &= (~(1 << irqType));\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN hardware pullup or pulldown configuration\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);\n+ }\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN wakeup pin mask configuration\n+ *\n+ * @param maskVal: mask value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN aon pad ctrl configuration\n+ *\n+ * @param aonPadCtl1: ctrl value 1\n+ * @param aonpadCtl2: ctrl value 2\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2)\n+{\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, aonPadCtl1);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, aonPadCtl2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN aon pad cfg configuration\n+ *\n+ * @param aonPadHwCtrlEn: HW Keep GPIO at PDS or HBN Mode\n+ * @param aonGpio: aon pad number\n+ * @param aonPadCfg: aon pad configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg)\n+{\n+ uint32_t tmpVal0;\n+ uint32_t tmpVal1;\n+ uint32_t enAonCtrlGpio;\n+ uint32_t aonPadIeSmt;\n+ uint32_t aonPadPu;\n+ uint32_t aonPadPd;\n+ uint32_t aonPadOe;\n+ uint8_t pu;\n+ uint8_t pd;\n+\n+ CHECK_PARAM(IS_HBN_AON_PAD_TYPE(aonGpio));\n+\n+ if (NULL == aonPadCfg) {\n+ return ERROR;\n+ }\n+\n+ /* hbn_pad_ctrl_0 */\n+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);\n+ enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO);\n+ if (aonPadCfg->ctrlEn) {\n+ enAonCtrlGpio |= (1 << aonGpio);\n+ } else {\n+ enAonCtrlGpio &= ~(1 << aonGpio);\n+ }\n+ tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio);\n+ aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT);\n+ if (aonPadCfg->inputEn) {\n+ aonPadIeSmt |= (1 << aonGpio);\n+ } else {\n+ aonPadIeSmt &= ~(1 << aonGpio);\n+ }\n+ tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);\n+\n+ /* calc pu/pd */\n+ switch (aonPadCfg->pullCfg) {\n+ case HBN_GPIO_PAD_PULL_NONE:\n+ pu = 0;\n+ pd = 0;\n+ break;\n+ case HBN_GPIO_PAD_PULL_DOWN:\n+ pu = 0;\n+ pd = 1;\n+ break;\n+ case HBN_GPIO_PAD_PULL_UP:\n+ pu = 1;\n+ pd = 0;\n+ break;\n+ case HBN_GPIO_PAD_ACTIVE_IE:\n+ pu = 1;\n+ pd = 1;\n+ break;\n+ default:\n+ pu = 0;\n+ pd = 0;\n+ break;\n+ }\n+\n+ /* hbn_pad_ctrl_1 */\n+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);\n+ aonPadPu = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU);\n+ if (pu) {\n+ aonPadPu |= (1 << aonGpio);\n+ } else {\n+ aonPadPu &= ~(1 << aonGpio);\n+ }\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU, aonPadPu);\n+ aonPadPd = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD);\n+ if (pd) {\n+ aonPadPd |= (1 << aonGpio);\n+ } else {\n+ aonPadPd &= ~(1 << aonGpio);\n+ }\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD, aonPadPd);\n+ aonPadOe = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE);\n+ if (aonPadCfg->outputEn) {\n+ aonPadOe |= (1 << aonGpio);\n+ } else {\n+ aonPadOe &= ~(1 << aonGpio);\n+ }\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE, aonPadOe);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);\n+\n+ /* hw ctrl enable/disable */\n+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);\n+ if (aonPadHwCtrlEn) {\n+ tmpVal0 = BL_SET_REG_BIT(tmpVal0, HBN_REG_AON_GPIO_ISO_MODE);\n+ } else {\n+ tmpVal0 = BL_CLR_REG_BIT(tmpVal0, HBN_REG_AON_GPIO_ISO_MODE);\n+ }\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN Set IO40&41 As Xtal_32K's IO\n+ *\n+ * @param xtal32kIoEn: Enable or disable IO40&41 As Xtal_32K's IO\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_IO4041_As_Xtal_32K_IO(uint8_t xtal32kIoEn)\n+{\n+ uint32_t tmpVal0;\n+ uint32_t tmpVal1;\n+\n+ if (xtal32kIoEn) {\n+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);\n+ tmpVal0 |= ((uint32_t)0x3 << 27);\n+ tmpVal0 &= ~((uint32_t)0x3 << 7);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);\n+\n+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);\n+ tmpVal1 &= ~((uint32_t)0x3 << 7);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);\n+ } else {\n+ tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);\n+ tmpVal0 &= ~((uint32_t)0x3 << 27);\n+ tmpVal0 &= ~((uint32_t)0x3 << 7);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);\n+\n+ tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);\n+ tmpVal1 |= ((uint32_t)0x3 << 7);\n+ BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable ACOMP0 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);\n+ tmpVal2 = tmpVal2 | (1 << edge);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable ACOMP0 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);\n+ tmpVal2 = tmpVal2 & (~(1 << edge));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable ACOMP1 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);\n+ tmpVal2 = tmpVal2 | (1 << edge);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable ACOMP1 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);\n+ tmpVal2 = tmpVal2 & (~(1 << edge));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable BOD interrupt\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Enable_BOD_IRQ(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable BOD interrupt\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Disable_BOD_IRQ(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN out0 install interrupt callback\n+ *\n+ * @param intType: HBN out0 interrupt type\n+ * @param cbFun: HBN out0 interrupt callback\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);\n+#endif\n+\n+ hbnInt0CbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief HBN out1 install interrupt callback\n+ *\n+ * @param intType: HBN out1 interrupt type\n+ * @param cbFun: HBN out1 interrupt callback\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);\n+#endif\n+\n+ hbnInt1CbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief HBN aon pad debbug pull config\n+ *\n+ * @param puPdEn: Enable or disable aon pad pull down and pull up\n+ * @param ieSmtEn: Enable or disable aon pad IE and SMT\n+ * @param trigMode: trigger mode\n+ * @param maskVal: int mask\n+ * @param dlyEn: Enable or disable aon pad wakeup delay function\n+ * @param dlySec: aon pad wakeup delay sec 1 to 7\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));\n+ CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(trigMode));\n+ CHECK_PARAM((maskVal <= 0x3FF));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, puPdEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, trigMode);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get RTC misc config\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t *pCfg = (uint32_t *)cfg;\n+\n+ if (!cfg) {\n+ return ERROR;\n+ }\n+\n+ /* read [31:19] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC);\n+\n+ /* use [30:19] */\n+ *pCfg = tmpVal;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set RTC misc config\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (!cfg) {\n+ return ERROR;\n+ }\n+\n+ /* read [31:19] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC, ((*(uint32_t *)cfg)<<1));\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set Embedded Flash Pullup enabe or disable\n+ *\n+ * @param cfg: Enable or disable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (cfg->enableBodInt) {\n+ HBN_Enable_BOD_IRQ();\n+ } else {\n+ HBN_Disable_BOD_IRQ();\n+ }\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, cfg->bodThreshold);\n+ if (cfg->enablePorInBod) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOD_SEL);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOD_SEL);\n+ }\n+\n+ if (cfg->enableBod) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOD);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOD);\n+ }\n+\n+ BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN OUT0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void HBN_OUT0_IRQHandler(void)\n+{\n+ HBN_OUT0_INT_Type out0Int = HBN_OUT0_INT_GPIO9;\n+\n+ /* GPIO and RTC */\n+ for (HBN_INT_Type gpioInt = HBN_INT_GPIO9; gpioInt <= HBN_INT_GPIO41; gpioInt++) {\n+ if (SET == HBN_Get_INT_State(gpioInt)) {\n+ HBN_Clear_IRQ(gpioInt);\n+ switch (gpioInt) {\n+ case HBN_INT_GPIO9:\n+ out0Int = HBN_OUT0_INT_GPIO9;\n+ break;\n+ case HBN_INT_GPIO10:\n+ out0Int = HBN_OUT0_INT_GPIO10;\n+ break;\n+ case HBN_INT_GPIO11:\n+ out0Int = HBN_OUT0_INT_GPIO11;\n+ break;\n+ case HBN_INT_GPIO12:\n+ out0Int = HBN_OUT0_INT_GPIO12;\n+ break;\n+ case HBN_INT_GPIO13:\n+ out0Int = HBN_OUT0_INT_GPIO13;\n+ break;\n+ case HBN_INT_GPIO14:\n+ out0Int = HBN_OUT0_INT_GPIO14;\n+ break;\n+ case HBN_INT_GPIO15:\n+ out0Int = HBN_OUT0_INT_GPIO15;\n+ break;\n+ case HBN_INT_GPIO40:\n+ out0Int = HBN_OUT0_INT_GPIO40;\n+ break;\n+ case HBN_INT_GPIO41:\n+ out0Int = HBN_OUT0_INT_GPIO41;\n+ break;\n+ default:\n+ break;\n+ }\n+ if (hbnInt0CbfArra[out0Int] != NULL) {\n+ hbnInt0CbfArra[out0Int]();\n+ }\n+ }\n+ }\n+ if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {\n+ HBN_Clear_IRQ(HBN_INT_RTC);\n+ if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {\n+ hbnInt0CbfArra[HBN_OUT0_INT_RTC]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief HBN OUT1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void HBN_OUT1_IRQHandler(void)\n+{\n+ /* PIR */\n+ if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {\n+ HBN_Clear_IRQ(HBN_INT_PIR);\n+ if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {\n+ hbnInt1CbfArra[HBN_OUT1_INT_PIR]();\n+ }\n+ }\n+ /* BOD */\n+ if (SET == HBN_Get_INT_State(HBN_INT_BOD)) {\n+ HBN_Clear_IRQ(HBN_INT_BOD);\n+ if (hbnInt1CbfArra[HBN_OUT1_INT_BOD] != NULL) {\n+ hbnInt1CbfArra[HBN_OUT1_INT_BOD]();\n+ }\n+ }\n+ /* ACOMP0 */\n+ if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {\n+ HBN_Clear_IRQ(HBN_INT_ACOMP0);\n+ if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {\n+ hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();\n+ }\n+ }\n+ /* ACOMP1 */\n+ if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {\n+ HBN_Clear_IRQ(HBN_INT_ACOMP1);\n+ if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {\n+ hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group HBN_Public_Functions */\n+\n+/*@} end of group HBN */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3f9c293e502f2f25d0b75ca3e73b6d3d1bc4a303\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c\n@@ -0,0 +1,964 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_i2c.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_i2c.h\"\n+#include \"bl808_glb.h\"\n+#include \"bl808_clock.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup I2C\n+ * @{\n+ */\n+\n+/** @defgroup I2C_Private_Macros\n+ * @{\n+ */\n+#define I2C_FIFO_STATUS_TIMEOUT (320 * 1000 * 2)\n+#define PUT_UINT32_LE(n, b, i) \\\n+ { \\\n+ (b)[(i)] = (uint8_t)((n)); \\\n+ (b)[(i) + 1] = (uint8_t)((n) >> 8); \\\n+ (b)[(i) + 2] = (uint8_t)((n) >> 16); \\\n+ (b)[(i) + 3] = (uint8_t)((n) >> 24); \\\n+ }\n+\n+/*@} end of group I2C_Private_Macros */\n+\n+/** @defgroup I2C_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group I2C_Private_Types */\n+\n+/** @defgroup I2C_Private_Variables\n+ * @{\n+ */\n+static const uint32_t i2cAddr[4] = { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = { { NULL } };\n+#endif\n+\n+/*@} end of group I2C_Private_Variables */\n+\n+/** @defgroup I2C_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group I2C_Global_Variables */\n+\n+/** @defgroup I2C_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group I2C_Private_Fun_Declaration */\n+\n+/** @defgroup I2C_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief I2C interrupt handler\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void I2C_IntHandler(I2C_ID_Type i2cNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) {\n+ if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) {\n+ /* Call the callback function */\n+ i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group I2C_Private_Functions */\n+\n+/** @defgroup I2C_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief I2C write word data\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param data: Data word\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data)\n+{\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+ uint32_t timeOut = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {\n+ timeOut--;\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C read word data\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return word data\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_RecieveWord(I2C_ID_Type i2cNo, uint32_t *recvBuff)\n+{\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+ uint32_t timeOut = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ *recvBuff = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C enable\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_Enable(I2C_ID_Type i2cNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);\n+ BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C disable\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_Disable(I2C_ID_Type i2cNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);\n+ BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);\n+\n+ /* Clear I2C fifo */\n+ tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);\n+ BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);\n+\n+ /* Clear I2C interrupt status */\n+ tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR);\n+ BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C set global reset function\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_DeInit(I2C_ID_Type i2cNo)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) {\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_I2C);\n+ } else if (i2cNo == I2C0_MM_ID) {\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C0);\n+ } else if (i2cNo == I2C1_MM_ID) {\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C1);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C init function\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param direct: I2C read or write direct\n+ * @param cfg: I2C transfer config struct\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ /* set i2c clk,default is 400000,max support clk is 400000 */\n+ if (cfg->clk == 0 || cfg->clk > 400000){\n+ I2C_ClockSet(i2cNo, 400000);\n+ } else {\n+ I2C_ClockSet(i2cNo, cfg->clk);\n+ }\n+\n+ /* Disable clock gate when use I2C0 */\n+ if (I2C0_ID == i2cNo) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C);\n+ } else if (I2C1_ID == i2cNo) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C1);\n+ } \n+\n+ /* I2C write config */\n+ tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);\n+\n+ if (direct == I2C_WRITE) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_10B_ADDR_EN, cfg->slaveAddr10Bit);\n+\n+ if (cfg->subAddrSize > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);\n+ }\n+\n+ /* align clock when 1 master*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SCL_SYNC_EN, DISABLE);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1);\n+ BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);\n+\n+ /* Set sub address */\n+ BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(I2C0_IRQn, I2C0_IRQHandler);\n+ Interrupt_Handler_Register(I2C1_IRQn, I2C1_IRQHandler);\n+ Interrupt_Handler_Register(I2C2_IRQn, I2C2_IRQHandler);\n+ Interrupt_Handler_Register(I2C3_IRQn, I2C2_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set de-glitch function cycle count value\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param cnt: De-glitch function cycle count\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);\n+\n+ if (cnt > 0) {\n+ /* enable de-glitch function */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);\n+ } else if (cnt == 0) {\n+ /* disable de-glitch function */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);\n+ } else {\n+ return ERROR;\n+ }\n+\n+ /* Set count value */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt);\n+ BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set i2c prd\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param phase: I2C phase value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ //phase_cycles = (32000000 / phase / 4) - 1;\n+ tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase);\n+ BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal);\n+ tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase);\n+ BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal);\n+ tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase);\n+ BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C set scl output clock\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param clk: Clock set\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk)\n+{\n+ uint32_t bclk = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) {\n+ bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);\n+\n+ if (clk >= 100000) {\n+ GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 0);\n+ I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1);\n+ } else if (clk >= 8000) {\n+ GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 9);\n+ I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1);\n+ } else if (clk >= 800) {\n+ GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 99);\n+ I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1);\n+ } else {\n+ GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 255);\n+ I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1);\n+ }\n+ } else if (i2cNo == I2C0_MM_ID) {\n+ bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);\n+\n+ if (clk >= 100000) {\n+ GLB_Set_DSP_I2C0_CLK(1, 1, 1, 0);\n+ I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1);\n+ } else if (clk >= 8000) {\n+ GLB_Set_DSP_I2C0_CLK(1, 1, 1, 9);\n+ I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1);\n+ } else if (clk >= 800) {\n+ GLB_Set_DSP_I2C0_CLK(1, 1, 1, 99);\n+ I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1);\n+ } else {\n+ GLB_Set_DSP_I2C0_CLK(1, 1, 1, 255);\n+ I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1);\n+ }\n+ } else if (i2cNo == I2C1_MM_ID) {\n+ bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK);\n+\n+ if (clk >= 100000) {\n+ GLB_Set_DSP_I2C1_CLK(1, 1, 1, 0);\n+ I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1);\n+ } else if (clk >= 8000) {\n+ GLB_Set_DSP_I2C1_CLK(1, 1, 1, 9);\n+ I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1);\n+ } else if (clk >= 800) {\n+ GLB_Set_DSP_I2C1_CLK(1, 1, 1, 99);\n+ I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1);\n+ } else {\n+ GLB_Set_DSP_I2C1_CLK(1, 1, 1, 255);\n+ I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1);\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C set scl sync\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param enable: Enable or disable I2C scl sync\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);\n+ }\n+\n+ BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get i2c busy state\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return RESET or SET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY);\n+ return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get i2c transfer end state\n+ *\n+ * @param i2cNo: I2C ID type\n+ *\n+ * @return RESET or SET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);\n+ return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C master write block data\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param cfg: I2C transfer config struct\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg)\n+{\n+ uint8_t i;\n+ uint32_t timeOut = 0;\n+ uint32_t temp = 0;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ I2C_Disable(i2cNo);\n+ I2C_Init(i2cNo, I2C_WRITE, cfg);\n+\n+ /* Set I2C write data */\n+ for (i = 0; i < cfg->dataSize; i++) {\n+ temp += (cfg->data[i] << ((i % 4) * 8));\n+\n+ if ((i + 1) % 4 == 0) {\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);\n+ if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) {\n+ I2C_Enable(i2cNo);\n+ }\n+ temp = 0;\n+ }\n+ }\n+\n+ if ((cfg->dataSize % 4) != 0) {\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);\n+ if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) {\n+ I2C_Enable(i2cNo);\n+ }\n+ }\n+\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ I2C_Disable(i2cNo);\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2C master read block data\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param cfg: I2C transfer config struct\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg)\n+{\n+ uint8_t i = 0;\n+ uint32_t timeOut = 0;\n+ uint32_t temp = 0;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+\n+ I2C_Disable(i2cNo);\n+ I2C_Init(i2cNo, I2C_READ, cfg);\n+ I2C_Enable(i2cNo);\n+\n+ /* Read I2C data */\n+ while (cfg->dataSize - i >= 4) {\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);\n+ PUT_UINT32_LE(temp, cfg->data, i);\n+ i += 4;\n+ }\n+\n+ if (i < cfg->dataSize) {\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);\n+\n+ while (i < cfg->dataSize) {\n+ cfg->data[i] = (temp & 0xff);\n+ temp = (temp >> 8);\n+ i++;\n+ }\n+ }\n+\n+ timeOut = I2C_FIFO_STATUS_TIMEOUT;\n+\n+ while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ I2C_Disable(i2cNo);\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ I2C_Disable(i2cNo);\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask the I2C interrupt\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param intType: Specifies the interrupt type\n+ * @param intMask: Enable/Disable Specified interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Cx = i2cAddr[i2cNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+ CHECK_PARAM(IS_I2C_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);\n+\n+ switch (intType) {\n+ case I2C_TRANS_END_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_TX_FIFO_READY_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_RX_FIFO_READY_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_NACK_RECV_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_ARB_LOST_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_FIFO_ERR_INT:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);\n+ }\n+\n+ break;\n+\n+ case I2C_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install I2C interrupt callback function\n+ *\n+ * @param i2cNo: I2C ID type\n+ * @param intType: Specifies the interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));\n+ CHECK_PARAM(IS_I2C_INT_TYPE(intType));\n+\n+ i2cIntCbfArra[i2cNo][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief I2C0 IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void I2C0_IRQHandler(void)\n+{\n+ I2C_IntHandler(I2C0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief I2C1 IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void I2C1_IRQHandler(void)\n+{\n+ I2C_IntHandler(I2C1_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief I2C2 IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void I2C2_IRQHandler(void)\n+{\n+ I2C_IntHandler(I2C0_MM_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief I2C3 IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void I2C3_IRQHandler(void)\n+{\n+ I2C_IntHandler(I2C1_MM_ID);\n+}\n+#endif\n+\n+/*@} end of group I2C_Public_Functions */\n+\n+/*@} end of group I2C */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5e8fb3595921526cccd2b71c1e378014e1e614f3\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c\n@@ -0,0 +1,508 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_i2s.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_i2s.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup I2S\n+ * @{\n+ */\n+\n+/** @defgroup I2S_Private_Macros\n+ * @{\n+ */\n+\n+static const uint32_t i2sAddr[I2S_ID_MAX] = { I2S_BASE };\n+#define I2S_USE_ID I2S0_ID\n+\n+/*@} end of group I2S_Private_Macros */\n+\n+/** @defgroup I2S_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group I2S_Private_Types */\n+\n+/** @defgroup I2S_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group I2S_Private_Variables */\n+\n+/** @defgroup I2S_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group I2S_Global_Variables */\n+\n+/** @defgroup I2S_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group I2S_Private_Fun_Declaration */\n+\n+/** @defgroup I2S_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group I2S_Private_Functions */\n+\n+/** @defgroup I2S_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief I2S BCLK config\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param i2sCfg: I2S configuration pointer\n+ *\n+ * @return NONE\n+ *\n+*******************************************************************************/\n+void I2S_SetBclkPeriod(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg)\n+{\n+ uint32_t overSampleRate;\n+ uint32_t bclkDivCnt;\n+ uint32_t tmpVal;\n+ uint8_t enumOffset = 2;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));\n+\n+ if (i2sCfg->fsChannel == I2S_FS_CHANNELS_6) {\n+ enumOffset = 3;\n+ }\n+ overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz;\n+\n+ switch (i2sCfg->frameSize) {\n+ case I2S_SIZE_FRAME_8:\n+ bclkDivCnt = overSampleRate / (8 * (i2sCfg->fsChannel + enumOffset));\n+ break;\n+\n+ case I2S_SIZE_FRAME_16:\n+ bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset));\n+ break;\n+\n+ case I2S_SIZE_FRAME_24:\n+ bclkDivCnt = overSampleRate / (24 * (i2sCfg->fsChannel + enumOffset));\n+ break;\n+\n+ case I2S_SIZE_FRAME_32:\n+ bclkDivCnt = overSampleRate / (32 * (i2sCfg->fsChannel + enumOffset));\n+ break;\n+\n+ default:\n+ bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset));\n+ break;\n+ }\n+\n+ bclkDivCnt = (bclkDivCnt / 2) - 1;\n+\n+ tmpVal = (bclkDivCnt << 16) | bclkDivCnt;\n+ BL_WR_REG(I2Sx, I2S_BCLK_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S configuration\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param i2sCfg: I2S configuration pointer\n+ *\n+ * @return NONE\n+ *\n+*******************************************************************************/\n+void I2S_Init(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType));\n+ CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType));\n+ CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));\n+ CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode));\n+ CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel));\n+ CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize));\n+ CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel));\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2S);\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG);\n+\n+ /* Set data endian*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType);\n+\n+ /* Set I2S mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType);\n+\n+ /* Set BCLK invert */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert);\n+\n+ /* Set FS size */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize);\n+\n+ /* Set FS invert */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert);\n+\n+ /* Set FS mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode);\n+\n+ /* Set FS channel mode */\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_CH_CNT, i2sCfg->fsChannel);\n+\n+ /* Set Data size */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize);\n+\n+ /* Set Data offset */\n+ if (i2sCfg->dataOffset != 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN);\n+ }\n+\n+ /* Set mono mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode);\n+\n+ /* Set rx mono mode channel left or right */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel);\n+\n+ /* Clear mute mode */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);\n+\n+ BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal);\n+\n+ I2S_SetBclkPeriod(I2S_USE_ID, i2sCfg);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S configure FIFO function\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param fifoCfg: FIFO configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_FifoConfig(I2S_ID_Type i2sId, I2S_FifoCfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0);\n+ /* Set packed mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange);\n+ /* Clear tx and rx FIFO signal */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);\n+\n+ /* Set DMA config */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable);\n+\n+ BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal);\n+\n+ /* Set CLR signal to 0*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);\n+ BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1);\n+ /* Set TX and RX FIFO threshold */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel);\n+\n+ BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S configure IO function\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param ioCfg: IO configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_IOConfig(I2S_ID_Type i2sId, I2S_IOCfg_Type *ioCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_IO_CONFIG);\n+ /* Enable or disable deglitch */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn);\n+\n+ /* Set deglitch cycle count */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt);\n+\n+ /* Enable or disable inverse BCLK signal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK);\n+\n+ /* Enable or disable inverse FS signal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS);\n+\n+ /* Enable or disable inverse RX signal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX);\n+\n+ /* Enable or disable inverse TX signal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX);\n+\n+ BL_WR_REG(I2Sx, I2S_IO_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable I2S\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param roleType: I2S master or slave\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Enable(I2S_ID_Type i2sId, I2S_Role_Type roleType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType));\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);\n+\n+ /* Set role type */\n+ if (I2S_ROLE_MASTER == roleType) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);\n+ } else if (I2S_ROLE_SLAVE == roleType) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);\n+ }\n+\n+ BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable I2S\n+ *\n+ * @param i2sId: I2S ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Disable(I2S_ID_Type i2sId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);\n+ BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S read data\n+ *\n+ * @param i2sId: I2S ID type\n+ *\n+ * @return Data read\n+ *\n+*******************************************************************************/\n+uint32_t I2S_Read(I2S_ID_Type i2sId)\n+{\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) {\n+ };\n+\n+ return BL_RD_REG(I2Sx, I2S_FIFO_RDATA);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S write data\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param data: write data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Write(I2S_ID_Type i2sId, uint32_t data)\n+{\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) {\n+ };\n+\n+ BL_WR_REG(I2Sx, I2S_FIFO_WDATA, data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S set mute\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param enabled: mute enabled or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Mute(I2S_ID_Type i2sId, BL_Fun_Type enabled)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG);\n+\n+ if (enabled ? 1 : 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);\n+ }\n+\n+ BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S set 24-bit data align mode in fifo\n+ *\n+ * @param i2sId: I2S ID type\n+ * @param justType: Align mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_SetFifoJustified(I2S_ID_Type i2sId, I2S_FIFO_24_Justified_Type justType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType));\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType);\n+ BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S flush\n+ *\n+ * @param i2sId: I2S ID type\n+ *\n+ * @return data count in TX FIFO\n+ *\n+*******************************************************************************/\n+uint32_t I2S_GetTxFIFO_AvlCnt(I2S_ID_Type i2sId)\n+{\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S flush\n+ *\n+* @param i2sId: I2S ID type\n+ *\n+ * @return data count in RX FIFO\n+ *\n+*******************************************************************************/\n+uint32_t I2S_GetRxFIFO_AvlCnt(I2S_ID_Type i2sId)\n+{\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S flush\n+ *\n+ * @param i2sId: I2S ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Tx_FIFO_Flush(I2S_ID_Type i2sId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);\n+\n+ BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief I2S flush\n+ *\n+ * @param i2sId: I2S ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void I2S_Rx_FIFO_Flush(I2S_ID_Type i2sId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t I2Sx = i2sAddr[i2sId];\n+\n+ tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);\n+\n+ BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal);\n+}\n+\n+/*@} end of group I2S_Public_Functions */\n+\n+/*@} end of group I2S */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0290919738f42dc34f42c6b38147840dee0edbc5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c\n@@ -0,0 +1,737 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_ipc.c\n+ * @version V1.2\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2018 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_ipc.h\"\n+\n+/** @addtogroup BL606P_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup IPC\n+ * @{\n+ */\n+\n+/** @defgroup IPC_Private_Macros\n+ * @{\n+ */\n+#define IPC_LP_OFFSET_IN_M0 0\n+#define IPC_D0_OFFSET_IN_M0 16\n+\n+#define IPC_M0_OFFSET_IN_LP 0\n+#define IPC_D0_OFFSET_IN_LP 16\n+\n+#define IPC_M0_OFFSET_IN_D0 0\n+#define IPC_LP_OFFSET_IN_D0 16\n+\n+/*@} end of group IPC_Private_Macros */\n+\n+/** @defgroup IPC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group IPC_Private_Types */\n+\n+/** @defgroup IPC_Private_Variables\n+ * @{\n+ */\n+\n+ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };\n+ipcIntCallback *lpIpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };\n+ipcIntCallback *d0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };\n+\n+/*@} end of group IPC_Private_Variables */\n+\n+/** @defgroup IPC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group IPC_Global_Variables */\n+\n+/** @defgroup IPC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group IPC_Private_Fun_Declaration */\n+\n+/** @defgroup IPC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group IPC_Private_Functions */\n+\n+/** @defgroup IPC_Public_Functions\n+ * @{\n+ */\n+#if defined(CPU_M0) || defined(CPU_LP)\n+/****************************************************************************/ /**\n+ * @brief M0 IPC interrupt init\n+ *\n+ * @param onLPTriggerCallBack: Callback when LP trigger\n+ *\n+ * @param onD0TriggerCallBack: Callback when D0 trigger\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack,\n+ ipcIntCallback *onD0TriggerCallBack)\n+{\n+ m0IpcIntCbfArra[0] = onLPTriggerCallBack;\n+ m0IpcIntCbfArra[1] = onD0TriggerCallBack;\n+\n+ IPC_M0_Int_Unmask_By_Word(0xffffffff);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(IPC_M0_IRQn, IPC_M0_IRQHandler);\n+#endif\n+ CPU_Interrupt_Enable(IPC_M0_IRQn);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief M0 unmask IPC interrupt\n+ *\n+ * @param src: M0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Int_Unmask(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 unmask IPC interrupt by word\n+ *\n+ * @param src: IPC interrupt source in word,every bit is interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Int_Unmask_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 get IPC interrupt raw status\n+ *\n+ * @param None\n+ *\n+ * @return IPC interrupt raw status\n+ *\n+*******************************************************************************/\n+uint32_t IPC_M0_Get_Int_Raw_Status(void)\n+{\n+ return BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 clear IPC interrupt\n+ *\n+ * @param src: M0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Clear_Int(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 clear IPC interrupt by word\n+ *\n+ * @param src: IPC interrupt source in word,every bit is interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Clear_Int_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CPUx trigger IPC interrupt to M0\n+ *\n+ * @param src: IPC interrupt source\n+ * \n+ * @param cpuxOffset: CPU interrupt offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_CPUx_Trigger_M0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));\n+\n+ tmpVal = (1 << (src + cpuxOffset));\n+\n+ BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP trigger IPC interrupt to M0\n+ *\n+ * @param src: LP IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_M0(src, IPC_LP_OFFSET_IN_M0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 trigger IPC interrupt to M0\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_M0(src, IPC_D0_OFFSET_IN_M0);\n+}\n+\n+#if defined(CPU_M0) || defined(CPU_LP)\n+/****************************************************************************/ /**\n+ * @brief LP IPC interrupt init\n+ *\n+ * @param onM0TriggerCallBack: Callback when M0 trigger\n+ *\n+ * @param onD0TriggerCallBack: Callback when D0 trigger\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack,\n+ ipcIntCallback *onD0TriggerCallBack)\n+{\n+ lpIpcIntCbfArra[0] = onM0TriggerCallBack;\n+ lpIpcIntCbfArra[1] = onD0TriggerCallBack;\n+\n+ IPC_LP_Int_Unmask_By_Word(0xffffffff);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(IPC_LP_IRQn, IPC_LP_IRQHandler);\n+#endif\n+ CPU_Interrupt_Enable(IPC_LP_IRQn);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief LP unmask IPC interrupt\n+ *\n+ * @param src: LP IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Int_Unmask(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP unmask IPC interrupt by word\n+ *\n+ * @param src: IPC interrupt source in word,every bit is interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Int_Unmask_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP get IPC interrupt raw status\n+ *\n+ * @param None\n+ *\n+ * @return IPC interrupt raw status\n+ *\n+*******************************************************************************/\n+uint32_t IPC_LP_Get_Int_Raw_Status(void)\n+{\n+ return BL_RD_REG(IPC1_BASE, IPC_CPU0_IPC_IRSRR);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP clear IPC interrupt\n+ *\n+ * @param src: LP IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Clear_Int(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP clear IPC interrupt by word\n+ *\n+ * @param src: IPC interrupt source in word,every bit is interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Clear_Int_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CPUx trigger IPC interrupt to LP\n+ *\n+ * @param src: IPC interrupt source\n+ *\n+ * @param cpuxOffset: CPU interrupt offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_CPUx_Trigger_LP(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));\n+\n+ tmpVal = (1 << (src + cpuxOffset));\n+\n+ BL_WR_REG(IPC1_BASE, IPC_CPU1_IPC_ISWR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 trigger IPC interrupt to LP\n+ *\n+ * @param src: M0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Trigger_LP(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_LP(src, IPC_M0_OFFSET_IN_LP);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 trigger IPC interrupt to LP\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_LP(src, IPC_D0_OFFSET_IN_LP);\n+}\n+\n+#if defined(CPU_D0) || defined(CPU_D1)\n+/****************************************************************************/ /**\n+ * @brief D0 IPC interrupt init\n+ *\n+ * @param onM0TriggerCallBack: Callback when M0 trigger\n+ *\n+ * @param onLPTriggerCallBack: Callback when LP trigger\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack,\n+ ipcIntCallback *onLPTriggerCallBack)\n+{\n+ d0IpcIntCbfArra[0] = onM0TriggerCallBack;\n+ d0IpcIntCbfArra[1] = onLPTriggerCallBack;\n+\n+ IPC_D0_Int_Unmask_By_Word(0xffffffff);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(IPC_D0_IRQn, IPC_D0_IRQHandler);\n+#endif\n+ CPU_Interrupt_Enable(IPC_D0_IRQn);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief D0 unmask IPC interrupt\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Int_Unmask(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 unmask IPC interrupt by word\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Int_Unmask_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 get IPC interrupt raw status\n+ *\n+ * @param None\n+ *\n+ * @return IPC interrupt raw status\n+ *\n+*******************************************************************************/\n+uint32_t IPC_D0_Get_Int_Raw_Status(void)\n+{\n+ return BL_RD_REG(IPC2_BASE, IPC_CPU0_IPC_IRSRR);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 clear IPC interrupt\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Clear_Int(IPC_Int_Src_Type src)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));\n+\n+ tmpVal = (1 << src);\n+\n+ BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 clear IPC interrupt by word\n+ *\n+ * @param src: IPC interrupt source in word,every bit is interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Clear_Int_By_Word(uint32_t src)\n+{\n+ BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, src);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CPUx trigger IPC interrupt to D0\n+ *\n+ * @param src: IPC interrupt source\n+ *\n+ * @param cpuxOffset: CPU interrupt offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_CPUx_Trigger_D0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));\n+\n+ tmpVal = (1 << (src + cpuxOffset));\n+\n+ BL_WR_REG(IPC2_BASE, IPC_CPU1_IPC_ISWR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 trigger IPC interrupt to D0\n+ *\n+ * @param src: M0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_D0(src, IPC_M0_OFFSET_IN_D0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP trigger IPC interrupt to D0\n+ *\n+ * @param src: LP IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src)\n+{\n+ IPC_CPUx_Trigger_D0(src, IPC_LP_OFFSET_IN_D0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 trigger IPC interrupt to CPUx\n+ *\n+ * @param tgtCPU: Target CPU\n+ *\n+ * @param src: IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)\n+{\n+ switch (tgtCPU) {\n+ case GLB_CORE_ID_LP:\n+ IPC_M0_Trigger_LP(src);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ IPC_M0_Trigger_D0(src);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief LP trigger IPC interrupt to CPUx\n+ *\n+ * @param tgtCPU: Target CPU\n+ *\n+ * @param src: IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)\n+{\n+ switch (tgtCPU) {\n+ case GLB_CORE_ID_M0:\n+ IPC_LP_Trigger_M0(src);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ IPC_LP_Trigger_D0(src);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 trigger IPC interrupt to CPUx\n+ *\n+ * @param tgtCPU: Target CPU\n+ *\n+ * @param src: IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)\n+{\n+ switch (tgtCPU) {\n+ case GLB_CORE_ID_M0:\n+ IPC_D0_Trigger_M0(src);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ IPC_D0_Trigger_LP(src);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 trigger IPC interrupt to D1\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)\n+{\n+ GLB_CORE_ID_Type localCPU = GLB_Get_Core_Type();\n+\n+ switch (localCPU) {\n+ case GLB_CORE_ID_M0:\n+ IPC_M0_Trigger_CPUx(tgtCPU, src);\n+ break;\n+ case GLB_CORE_ID_LP:\n+ IPC_LP_Trigger_CPUx(tgtCPU, src);\n+ break;\n+ case GLB_CORE_ID_D0:\n+ IPC_D0_Trigger_CPUx(tgtCPU, src);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief D0 trigger IPC interrupt to D1\n+ *\n+ * @param src: D0 IPC interrupt source\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX - 1])\n+{\n+ uint32_t tmp;\n+ uint32_t grp = 0;\n+\n+ for (grp = 0; grp < GLB_CORE_ID_MAX - 1; grp++) {\n+ tmp = (irqStatus >> (16 * grp)) & 0xffff;\n+ if (tmp != 0) {\n+ if (callBack[grp] != NULL) {\n+ callBack[grp](tmp);\n+ }\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief M0 IPC IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void IPC_M0_IRQHandler(void)\n+{\n+ uint32_t irqStatus;\n+ irqStatus = IPC_M0_Get_Int_Raw_Status();\n+ IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra);\n+ IPC_M0_Clear_Int_By_Word(irqStatus);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief LP IPC IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void IPC_LP_IRQHandler(void)\n+{\n+ uint32_t irqStatus;\n+ irqStatus = IPC_LP_Get_Int_Raw_Status();\n+ IPC_Common_Interrupt_Handler(irqStatus, lpIpcIntCbfArra);\n+ IPC_LP_Clear_Int_By_Word(irqStatus);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief D0 IPC IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void IPC_D0_IRQHandler(void)\n+{\n+ uint32_t irqStatus;\n+ irqStatus = IPC_D0_Get_Int_Raw_Status();\n+ IPC_Common_Interrupt_Handler(irqStatus, d0IpcIntCbfArra);\n+ IPC_D0_Clear_Int_By_Word(irqStatus);\n+}\n+#endif\n+\n+/*@} end of group IPC_Public_Functions */\n+\n+/*@} end of group IPC */\n+\n+/*@} end of group BL606P_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1fb74e6277484c903ff72d821095325f3fd317cb\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c\n@@ -0,0 +1,1269 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_ir.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_ir.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup IR\n+ * @{\n+ */\n+\n+/** @defgroup IR_Private_Macros\n+ * @{\n+ */\n+#define NEC_HEAD_H_MIN 17000\n+#define NEC_HEAD_H_MAX 19000\n+#define NEC_HEAD_L_MIN 8400\n+#define NEC_HEAD_L_MAX 9600\n+#define NEC_BIT0_H_MIN 525\n+#define NEC_BIT0_H_MAX 1725\n+#define RC5_ONE_PLUSE_MIN 1175\n+#define RC5_ONE_PLUSE_MAX 2375\n+#define RC5_TWO_PLUSE_MIN 2955\n+#define RC5_TWO_PLUSE_MAX 4155\n+#define IR_TX_INT_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define IR_RX_INT_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b))\n+\n+/*@} end of group IR_Private_Macros */\n+\n+/** @defgroup IR_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group IR_Private_Types */\n+\n+/** @defgroup IR_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group IR_Private_Variables */\n+\n+/** @defgroup IR_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group IR_Global_Variables */\n+\n+/** @defgroup IR_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group IR_Private_Fun_Declaration */\n+\n+/** @defgroup IR_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group IR_Private_Functions */\n+\n+/** @defgroup IR_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief IR RX IRQ handler function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void IRRX_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) {\n+ BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));\n+\n+ if (irIntCbfArra[IR_INT_RX_END] != NULL) {\n+ irIntCbfArra[IR_INT_RX_END]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FRDY_MASK)) {\n+ if (irIntCbfArra[IR_INT_RX_FIFO_REQ] != NULL) {\n+ irIntCbfArra[IR_INT_RX_FIFO_REQ]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FER_MASK)) {\n+ if (irIntCbfArra[IR_INT_RX_FIFO_ERROR] != NULL) {\n+ irIntCbfArra[IR_INT_RX_FIFO_ERROR]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief IR TX IRQ handler function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void IRTX_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) {\n+ BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));\n+\n+ if (irIntCbfArra[IR_INT_TX_END] != NULL) {\n+ irIntCbfArra[IR_INT_TX_END]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FRDY_MASK)) {\n+ if (irIntCbfArra[IR_INT_TX_FIFO_REQ] != NULL) {\n+ irIntCbfArra[IR_INT_TX_FIFO_REQ]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FER_MASK)) {\n+ if (irIntCbfArra[IR_INT_TX_FIFO_ERROR] != NULL) {\n+ irIntCbfArra[IR_INT_TX_FIFO_ERROR]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief IR tx initialization function\n+ *\n+ * @param irTxCfg: IR tx configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR);\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);\n+ /* Set data bit */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1);\n+ /* Set tail pulse */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_HL_INV, irTxCfg->tailPulseInverse);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_EN, irTxCfg->tailPulse);\n+ /* Set head pulse */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_HL_INV, irTxCfg->headPulseInverse);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_EN, irTxCfg->headPulse);\n+ /* Enable or disable logic 1 and 0 pulse inverse */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV, irTxCfg->logic1PulseInverse);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV, irTxCfg->logic0PulseInverse);\n+ /* Enable or disable data pulse */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_EN, irTxCfg->dataPulse);\n+ /* Enable or disable output modulation */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_EN, irTxCfg->outputModulation);\n+ /* Enable or disable output inverse */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_OUT_INV, irTxCfg->outputInverse);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_EN, irTxCfg->freerunEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_CONT_EN, irTxCfg->continueEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_FRAME_SIZE, irTxCfg->frameSize);\n+\n+ /* Write back */\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler);\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR tx pulse width configure function\n+ *\n+ * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_0);\n+ /* Set logic 0 pulse phase 0 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1);\n+ /* Set logic 0 pulse phase 1 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1);\n+ /* Set logic 1 pulse phase 0 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1);\n+ /* Set logic 1 pulse phase 1 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1);\n+ BL_WR_REG(IR_BASE, IRTX_PW_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_1);\n+ /* Set head pulse phase 0 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1);\n+ /* Set head pulse phase 1 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1);\n+ /* Set tail pulse phase 0 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1);\n+ /* Set tail pulse phase 1 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1);\n+ BL_WR_REG(IR_BASE, IRTX_PW_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);\n+ /* Set modulation phase 0 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1);\n+ /* Set modulation phase 1 width */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1);\n+ /* Set pulse width unit */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1);\n+ BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR rx initialization function\n+ *\n+ * @param irRxCfg: IR rx configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode));\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR);\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+\n+ /* Set rx mode */\n+ switch (irRxCfg->rxMode) {\n+ case IR_RX_NEC:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0);\n+ break;\n+\n+ case IR_RX_RC5:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1);\n+ break;\n+\n+ case IR_RX_SWM:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Enable or disable input inverse */\n+ ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV));\n+ /* Enable or disable rx input de-glitch function */\n+ ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN));\n+ /* Set de-glitch function cycle count */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt);\n+ /* Write back */\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);\n+ /* Set pulse width threshold to trigger end condition */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1);\n+ /* Set pulse width threshold for logic0/1 detection */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1);\n+ /* Write back */\n+ BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR configure fifo function\n+ *\n+ * @param fifoCfg: FIFO configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Set fifo threshold value */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_TH, fifoCfg->txFifoThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_TH, fifoCfg->rxFifoThreshold);\n+ BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_1, tmpVal);\n+\n+ /* Enable or disable dma function */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IRTX_DMA_EN, fifoCfg->txFifoDmaEnable);\n+ BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR set default value of all registers function\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_DeInit(void)\n+{\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_IR_REMOTE);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR enable function\n+ *\n+ * @param direct: IR direction type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_Enable(IR_Direction_Type direct)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));\n+\n+ if (direct == IR_TX || direct == IR_TXRX) {\n+ /* Enable ir tx unit */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN));\n+ }\n+\n+ if (direct == IR_RX || direct == IR_TXRX) {\n+ /* Enable ir rx unit */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR disable function\n+ *\n+ * @param direct: IR direction type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_Disable(IR_Direction_Type direct)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));\n+\n+ if (direct == IR_TX || direct == IR_TXRX) {\n+ /* Disable ir tx unit */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN));\n+ }\n+\n+ if (direct == IR_RX || direct == IR_TXRX) {\n+ /* Disable ir rx unit */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR tx software mode enable or disable function\n+ *\n+ * @param txSWM: Enable or disable\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable or disable tx swm */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);\n+\n+ if (ENABLE == txSWM) {\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));\n+ } else {\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR clear rx fifo function\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_RxFifoClear(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Clear rx fifo */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0);\n+ BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR clear tx fifo function\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_TxFifoClear(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Clear rx fifo */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0);\n+ BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_TX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send data function\n+ *\n+ * @param data: data to send\n+ * @param length: Length of send buffer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_SendData(uint32_t *data, uint8_t length)\n+{\n+ uint32_t txLen = 0;\n+ uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;\n+\n+ while (txLen < length) {\n+ if (IR_GetTxFifoCount() > 0) {\n+ BL_WR_REG(IR_BASE, IR_FIFO_WDATA, data[txLen++]);\n+ timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;\n+ } else {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR software mode send pulse width data function\n+ *\n+ * @param data: data to send\n+ * @param length: Length of send buffer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length)\n+{\n+ uint8_t i = 0, j = 0;\n+ uint16_t minData = data[0];\n+ uint32_t tmpVal;\n+ uint32_t count = (length + 3) / 4;\n+ uint32_t pwVal = 0;\n+\n+ /* Search for min value */\n+ for (i = 1; i < length; i++) {\n+ if (minData > data[i] && data[i] != 0) {\n+ minData = data[i];\n+ }\n+ }\n+\n+ /* Set min value as pulse width unit */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);\n+ BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData));\n+\n+ /* Calculate tx SWM pulse width data as multiples of pulse width unit */\n+ for (i = 0; i < count; i++) {\n+ pwVal = 0;\n+\n+ if (i < count - 1) {\n+ /* Put every four pulse width together as a 32-bit value to tx fifo */\n+ for (j = 0; j < 4; j++) {\n+ /* Every pulse width divided by pulse width unit */\n+ tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff;\n+ /* Tx fifo 32-bit value: pwVal[7:0]:first pulse width, pwVal[15:8]:second pulse width... */\n+ pwVal |= tmpVal << (8 * j);\n+ }\n+ } else {\n+ /* Deal with pulse width data remained which is less than 4 */\n+ for (j = 0; j < length % 4; j++) {\n+ tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff;\n+ pwVal |= tmpVal << (8 * j);\n+ }\n+ }\n+\n+ /* Write to tx fifo */\n+ IR_SendData(&pwVal, 1);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send command function\n+ *\n+ * @param data: data to send\n+ * @param length: Length of send buffer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length)\n+{\n+ uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;\n+\n+ /* Write data */\n+ IR_SendData(data, length);\n+\n+ /* Mask tx interrupt */\n+ IR_IntMask(IR_INT_TX_END, MASK);\n+\n+ /* Clear tx interrupt */\n+ IR_ClrIntStatus(IR_INT_TX_END);\n+\n+ /* Enable ir tx */\n+ IR_Enable(IR_TX);\n+\n+ /* Wait for tx interrupt */\n+ while (SET != IR_GetIntStatus(IR_INT_TX_END)) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ IR_Disable(IR_TX);\n+\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ /* Disable ir tx */\n+ IR_Disable(IR_TX);\n+\n+ /* Clear tx interrupt */\n+ IR_ClrIntStatus(IR_INT_TX_END);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send command in software mode function\n+ *\n+ * @param data: IR fifo data to send\n+ * @param length: Length of data\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length)\n+{\n+ uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;\n+\n+ /* Mask tx interrupt */\n+ IR_IntMask(IR_INT_TX_END, MASK);\n+\n+ /* Clear tx interrupt */\n+ IR_ClrIntStatus(IR_INT_TX_END);\n+\n+ /* Enable ir tx */\n+ IR_Enable(IR_TX);\n+\n+ /* Write fifo */\n+ IR_SWMSendData(data, length);\n+\n+ /* Wait for tx interrupt */\n+ while (SET != IR_GetIntStatus(IR_INT_TX_END)) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ IR_Disable(IR_TX);\n+\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ /* Disable ir tx */\n+ IR_Disable(IR_TX);\n+\n+ /* Clear tx interrupt */\n+ IR_ClrIntStatus(IR_INT_TX_END);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send in NEC protocol\n+ *\n+ * @param address: Address\n+ * @param command: Command\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command)\n+{\n+ uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address;\n+\n+ IR_SendCommand(&tmpVal, 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR interrupt mask or unmask function\n+ *\n+ * @param intType: IR interrupt type\n+ * @param intMask: Mask or unmask\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_INT_TYPE(intType));\n+\n+ if (intType < 3) {\n+ /* Mask or unmask tx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+\n+ if (MASK == intMask) {\n+ tmpVal |= 1 << (intType + 8);\n+ } else {\n+ tmpVal &= ~(1 << (intType + 8));\n+ }\n+\n+ BL_WR_REG(IR_BASE, IRTX_INT_STS, tmpVal);\n+ } else if (intType < 6) {\n+ /* Mask or unmask rx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+\n+ if (MASK == intMask) {\n+ tmpVal |= 1 << (intType + 5);\n+ } else {\n+ tmpVal &= ~(1 << (intType + 5));\n+ }\n+\n+ BL_WR_REG(IR_BASE, IRRX_INT_STS, tmpVal);\n+ } else {\n+ if (MASK == intMask) {\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ tmpVal |= 0x700;\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ tmpVal |= 0x700;\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ } else {\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ tmpVal &= ~0x700;\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ tmpVal &= ~0x700;\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear ir interrupt function\n+ *\n+ * @param intType: IR interrupt type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_INT_TYPE(intType));\n+\n+ if (intType == IR_INT_TX_END || intType == IR_INT_ALL) {\n+ /* Clear tx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));\n+ }\n+\n+ if (intType == IR_INT_RX_END || intType == IR_INT_ALL) {\n+ /* Clear rx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR install interrupt callback function\n+ *\n+ * @param intType: IR interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_INT_TYPE(intType));\n+\n+ irIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief IR get interrupt status function\n+ *\n+ * @param intType: IR int type\n+ *\n+ * @return IR tx or rx interrupt status\n+ *\n+*******************************************************************************/\n+BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_INT_TYPE(intType));\n+\n+ /* Read tx or rx interrupt status */\n+ if (intType < 3) {\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);\n+ tmpVal &= 1 << intType;\n+ } else if (intType < 6) {\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ tmpVal &= 1 << (intType - 3);\n+ } else {\n+ }\n+\n+ if (tmpVal) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR get tx/rx fifo underflow or overflow status function\n+ *\n+ * @param fifoSts: IR fifo status type\n+ *\n+ * @return IR fifo status\n+ *\n+*******************************************************************************/\n+BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts));\n+\n+ /* Read rx fifo status */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0);\n+\n+ if ((tmpVal & (1U << (fifoSts + IR_TX_FIFO_OVERFLOW_POS))) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR receive data function\n+ *\n+ * @param irWord: IR rx data word 0 or 1\n+ *\n+ * @return Data received\n+ *\n+*******************************************************************************/\n+uint32_t IR_ReceiveData(IR_Word_Type irWord)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_WORD_TYPE(irWord));\n+\n+ /* Read word 0 or word 1 */\n+ if (IR_WORD_0 == irWord) {\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0);\n+ } else {\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1);\n+ }\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR software mode receive pulse width data function\n+ *\n+ * @param data: Data received\n+ * @param length: Max length of receive buffer\n+ *\n+ * @return Length of datas received\n+ *\n+*******************************************************************************/\n+uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length)\n+{\n+ uint8_t rxLen = 0;\n+\n+ while (rxLen < length && IR_GetRxFifoCount() > 0) {\n+ /* Read data */\n+ data[rxLen++] = BL_RD_REG(IR_BASE, IR_FIFO_RDATA) & 0xffff;\n+ }\n+\n+ return rxLen;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR receive in NEC protocol\n+ *\n+ * @param address: Address\n+ * @param command: Command\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command)\n+{\n+ uint32_t tmpVal = IR_ReceiveData(IR_WORD_0);\n+\n+ *address = tmpVal & 0xff;\n+ *command = (tmpVal >> 16) & 0xff;\n+\n+ if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) {\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR get rx data bit count function\n+ *\n+ * @param None\n+ *\n+ * @return IR rx data bit count\n+ *\n+*******************************************************************************/\n+uint8_t IR_GetRxDataBitCount(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Read rx data bit count */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR get rx fifo count function\n+ *\n+ * @param None\n+ *\n+ * @return IR rx fifo available count\n+ *\n+*******************************************************************************/\n+uint8_t IR_GetRxFifoCount(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Read rx fifo count */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR get tx fifo count function\n+ *\n+ * @param None\n+ *\n+ * @return IR tx fifo available count\n+ *\n+*******************************************************************************/\n+uint8_t IR_GetTxFifoCount(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Read tx fifo count */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_CNT);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR learning to set rx and tx mode function\n+ *\n+ * @param data: Buffer to save data\n+ * @param length: Length of data\n+ *\n+ * @return Protocol type\n+ *\n+*******************************************************************************/\n+IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR);\n+\n+ /* Disable rx,set rx in software mode and enable rx input inverse */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);\n+ /* Set pulse width threshold to trigger end condition */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999));\n+\n+ /* Clear and mask rx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK);\n+ BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));\n+\n+ /* Enable rx */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));\n+\n+ /* Wait for rx interrupt */\n+ while (SET != IR_GetIntStatus(IR_INT_RX_END)) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ IR_Disable(IR_RX);\n+\n+ return IR_RX_SWM;\n+ }\n+ }\n+\n+ /* Disable rx */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));\n+\n+ /* Clear rx interrupt */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);\n+ BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));\n+\n+ /*Receive data */\n+ *length = IR_GetRxFifoCount();\n+ *length = IR_SWMReceiveData((uint16_t *)data, *length);\n+\n+ /* Judge protocol type */\n+ if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) {\n+ /* Set rx in NEC mode */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0));\n+ /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */\n+ BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47);\n+ /* Set tx in NEC mode */\n+ /* Tx configure */\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1fc514);\n+ /* Set logic 0,logic 1,head and tail pulse width */\n+ BL_WR_REG(IR_BASE, IRTX_PW_0, 0x02000000);\n+ BL_WR_REG(IR_BASE, IRTX_PW_1, 0x0000070f);\n+ /* Set modulation phase width and pulse width unit */\n+ BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464);\n+\n+ return IR_RX_NEC;\n+ } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) &&\n+ ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) {\n+ /* Set rx in RC-5 mode */\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1));\n+ /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */\n+ BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a);\n+ /* Set tx in RC-5 mode */\n+ /* Tx configure */\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xcc134);\n+ /* Set logic 0,logic 1,head and tail pulse width */\n+ BL_WR_REG(IR_BASE, IRTX_PW_0, 0);\n+ BL_WR_REG(IR_BASE, IRTX_PW_1, 0);\n+ /* Set modulation phase width and pulse width unit */\n+ BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1);\n+\n+ return IR_RX_RC5;\n+ } else if ((data[0] >> 16) != 0) {\n+ /* Set tx in software mode */\n+ /* Tx configure */\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 16 | 0xc);\n+ /* Set modulation phase width */\n+ BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000);\n+\n+ return IR_RX_SWM;\n+ } else {\n+ tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE);\n+\n+ if (tmpVal == 0) {\n+ return IR_RX_NEC;\n+ } else if (tmpVal == 1) {\n+ return IR_RX_RC5;\n+ } else {\n+ return IR_RX_SWM;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR receive data according to mode which is learned function\n+ *\n+ * @param mode: Protocol type\n+ * @param data: Buffer to save data\n+ *\n+ * @return Length of data\n+ *\n+*******************************************************************************/\n+uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data)\n+{\n+ uint8_t length = 0;\n+ uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));\n+\n+ /* Disable ir rx */\n+ IR_Disable(IR_RX);\n+\n+ /* Clear and mask rx interrupt */\n+ IR_ClrIntStatus(IR_INT_RX_END);\n+ IR_IntMask(IR_INT_RX_END, MASK);\n+\n+ /* Enable ir rx */\n+ IR_Enable(IR_RX);\n+\n+ /* Wait for rx interrupt */\n+ while (SET != IR_GetIntStatus(IR_INT_RX_END)) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ IR_Disable(IR_RX);\n+\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ /* Disable ir rx */\n+ IR_Disable(IR_RX);\n+\n+ /* Clear rx interrupt */\n+ IR_ClrIntStatus(IR_INT_RX_END);\n+\n+ /* Receive data according to mode */\n+ if (mode == IR_RX_NEC || mode == IR_RX_RC5) {\n+ /* Get data bit count */\n+ length = IR_GetRxDataBitCount();\n+ data[0] = IR_ReceiveData(IR_WORD_0);\n+ } else {\n+ /* Get fifo count */\n+ length = IR_GetRxFifoCount();\n+ length = IR_SWMReceiveData((uint16_t *)data, length);\n+ }\n+\n+ return length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send data according to mode which is learned function\n+ *\n+ * @param mode: Protocol type\n+ * @param data: Buffer of data to send\n+ * @param length: Length of data\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));\n+\n+ /* Set send length */\n+ tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1);\n+ BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);\n+\n+ if (mode == IR_RX_NEC || mode == IR_RX_RC5) {\n+ IR_SendCommand(data, 1);\n+ } else {\n+ IR_SWMSendCommand((uint16_t *)data, length);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR init to control led function\n+ *\n+ * @param clk: Clock source\n+ * @param div: Clock division(1~64)\n+ * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096)\n+ * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16)\n+ * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16)\n+ * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16)\n+ * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_LEDInit(HBN_MCU_XCLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L)\n+{\n+ IR_TxCfg_Type txCfg = {\n+ 24, /* 24-bit data */\n+ DISABLE, /* Disable signal of tail pulse inverse */\n+ DISABLE, /* Disable signal of tail pulse */\n+ DISABLE, /* Disable signal of head pulse inverse */\n+ DISABLE, /* Disable signal of head pulse */\n+ DISABLE, /* Disable signal of logic 1 pulse inverse */\n+ DISABLE, /* Disable signal of logic 0 pulse inverse */\n+ ENABLE, /* Enable signal of data pulse */\n+ DISABLE, /* Disable signal of output modulation */\n+ ENABLE, /* Enable signal of output inverse */\n+ DISABLE, /* Disable tx freerun mode */\n+ DISABLE, /* Disable tx freerun continuous mode */\n+ IR_FRAME_SIZE_32 /* Frame size */\n+ };\n+\n+ IR_TxPulseWidthCfg_Type txPWCfg = {\n+ code0L, /* Pulse width of logic 0 pulse phase 1 */\n+ code0H, /* Pulse width of logic 0 pulse phase 0 */\n+ code1L, /* Pulse width of logic 1 pulse phase 1 */\n+ code1H, /* Pulse width of logic 1 pulse phase 0 */\n+ 1, /* Pulse width of head pulse phase 1 */\n+ 1, /* Pulse width of head pulse phase 0 */\n+ 1, /* Pulse width of tail pulse phase 1 */\n+ 1, /* Pulse width of tail pulse phase 0 */\n+ 1, /* Modulation phase 1 width */\n+ 1, /* Modulation phase 0 width */\n+ unit /* Pulse width unit */\n+ };\n+\n+ HBN_Set_MCU_XCLK_Sel(clk);\n+ GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1);\n+\n+ /* Disable ir before config */\n+ IR_Disable(IR_TXRX);\n+\n+ /* IR tx init */\n+ IR_TxInit(&txCfg);\n+ IR_TxPulseWidthConfig(&txPWCfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief IR send 24-bit data to control led function\n+ *\n+ * @param data: Data to send(24-bit)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type IR_LEDSend(uint32_t data)\n+{\n+ /* Change MSB_first to LSB_first */\n+ data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa);\n+ data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc);\n+ data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0);\n+ data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000);\n+ IR_SendCommand(&data, 1);\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group IR_Public_Functions */\n+\n+/*@} end of group IR */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4b6653c84d9cde7613760bd1ac1de9ed2b810bfe\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c\n@@ -0,0 +1,671 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_iso11898.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_glb.h\"\n+#include \"bl808_iso11898.h\"\n+#include \"bflb_platform.h\"\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type * iso11898IntCbfArra[ISO11898_INT_ALL] = { NULL };\n+static void ISO11898_IntHandler(void);\n+static void ISO11898_IRQHandler(void);\n+#endif\n+\n+void ISO11898_Init(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable ISO11898 clock witch share with UART2 */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2);\n+\n+ /* Enable UART clock*/\n+ tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0);\n+ tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN);\n+ BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal);\n+\n+ /* UART2 and ISO11898 can not work together */\n+ GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_ISO11898);\n+\n+ /* Need to enter reset mode before operating */\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET);\n+\n+ /* Force using Peli not Basic ISO11898 */\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_MODE);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER, tmpVal);\n+\n+ /* Disable all interrupts */\n+ BL_WR_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE, 0);\n+\n+ /* Set clock and sample point */\n+ ISO11898_Clock_Div_Set(0);\n+ ISO11898_Synchronization_Jump_Width_Set(3);\n+ ISO11898_Sample_Parameter_Set(1, 8, 5);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(UART2_IRQn, ISO11898_IRQHandler);\n+#endif\n+}\n+\n+void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_MODE_TYPE(type));\n+ CHECK_PARAM(IS_ISO11898_MODE_VALUE_TYPE(value));\n+\n+ /* Set mode value */\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE);\n+ tmpVal &= ~(1 << type);\n+ tmpVal |= (value << type); \n+\n+ /* Write back */\n+ BL_WR_REG(ISO11898_BASE, ISO11898_MODE, tmpVal);\n+}\n+\n+ISO11898_MODE_VALUE_Type ISO11898_Mode_Get(ISO11898_MODE_Type type)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_MODE_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE);\n+ tmpVal &= (1 << type);\n+ tmpVal >>= type;\n+ return (ISO11898_MODE_VALUE_Type)tmpVal;\n+}\n+\n+void ISO11898_Int_Enable(ISO11898_INT_Type intType, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE);\n+ /* Enable or Disable certain or all interrupt */\n+ if(ISO11898_INT_ALL == intType){\n+ if(ENABLE == enable){\n+ tmpVal |= 0xFF;\n+ }else{\n+ tmpVal &= 0;\n+ }\n+ }else{\n+ if(ENABLE == enable){\n+ tmpVal |= 1<<intType;\n+ }else{\n+ tmpVal &= ~(1<<intType);\n+ }\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE, tmpVal);\n+}\n+\n+void ISO11898_Cmd_Request_Transmit(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_TRANSMIT_REQUEST);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_COMMAND, tmpVal);\n+}\n+void ISO11898_Cmd_Abort_Transmit(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_ABORT_TRANSMISSION);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_COMMAND, tmpVal);\n+}\n+void ISO11898_Cmd_Release_Recv_Buff(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_RELEASE_RECEIVE_BUFFER);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_COMMAND, tmpVal);\n+}\n+void ISO11898_Cmd_Clear_Data_Overrun(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_CLEAR_DATA_OVERRUN);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_COMMAND, tmpVal);\n+}\n+void ISO11898_Cmd_Request_Self_Reception(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_COMMAND);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_SELF_REQUEST);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_COMMAND, tmpVal);\n+}\n+\n+ISO11898_STATUS_VALUE_Type ISO11898_Status_Get(ISO11898_STATUS_Type type)\n+{\n+ volatile uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_STATUS_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_STATUS);\n+ tmpVal &= (1 << type);\n+ tmpVal >>= type;\n+ return (ISO11898_STATUS_VALUE_Type)tmpVal;\n+}\n+\n+uint8_t ISO11898_Arbitration_Lost_Position_Get(void)\n+{\n+ uint8_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ARB_LOST_CAPTURE);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ALC4_0);\n+ return tmpVal;\n+}\n+\n+void ISO11898_Error_Get(ISO11898_ERROR_Type *const type)\n+{\n+ uint8_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(type));\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_CODE_CAPTURE);\n+ type->code = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ERR_CODE);\n+ type->dir = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_DIR);\n+ type->location = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SEGMENT4_0);\n+}\n+\n+BL_Err_Type ISO11898_Error_Warning_Limit_Set(uint8_t limit)\n+{\n+ if(ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+ BL_WR_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT, limit);\n+ return SUCCESS;\n+}\n+\n+uint8_t ISO11898_Error_Warning_Limit_Get(void)\n+{\n+ return BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT);\n+}\n+\n+uint8_t ISO11898_Error_Rx_Counter_Get(void)\n+{\n+ return BL_RD_REG(ISO11898_BASE, ISO11898_RX_ERR_COUNT);\n+}\n+\n+uint8_t ISO11898_Error_Tx_Counter_Get(void)\n+{\n+ return BL_RD_REG(ISO11898_BASE, ISO11898_TX_ERR_COUNT);\n+}\n+\n+BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg)\n+{\n+ uint32_t timeOut;\n+ uint32_t tmpVal;\n+ uint32_t i;\n+ volatile uint32_t *pData;\n+ \n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr));\n+ CHECK_PARAM(IS_ISO11898_FRAME_TYPE(cfg->frameType));\n+ CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->frameFormat));\n+\n+ timeOut = cfg->timeout;\n+\n+ /* Chcek Timeout type */\n+ while(ISO11898_STATUS_TRANSMIT_BUFFER_LOCKED == ISO11898_Status_Get(ISO11898_STATUS_TRANSMIT_BUFFER))\n+ {\n+ /* Wait no time */\n+ if (cfg->timeout == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ /* Wait until transmit buffer accessible */\n+ if (cfg->timeout >= ISO11898_TIMEOUT_MAX)\n+ {\n+\n+ }\n+ /* Wait time = cfg->timeOut */\n+ else\n+ {\n+ if(timeOut == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ timeOut--;\n+ }\n+ }\n+\n+ /* Config information register */\n+ tmpVal = cfg->dataLen;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF, cfg->frameFormat);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR, cfg->frameType);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_INFORMATION, tmpVal);\n+\n+ tmpVal = cfg->id;\n+ /* Transmit format with 11 bits ID, SFF */\n+ if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat)\n+ {\n+ /* Config identifier registers */\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 3) & 0xFF);\n+ tmpVal <<= 5;\n+ tmpVal |= (cfg->frameType << 4);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, tmpVal & 0xFF);\n+ /* Config SFF data registers start address */\n+ pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET);\n+ }\n+ /* Transmit format with 29 bits ID, EFF */\n+ else\n+ {\n+ /* Config identifier registers */\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 21) & 0xFF);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, (tmpVal >> 13) & 0xFF);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3, (tmpVal >> 5) & 0xFF);\n+ tmpVal <<= 3;\n+ tmpVal |= (cfg->frameType << 2);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4, tmpVal & 0xFF);\n+ /* Config EFF data registers start address */\n+ pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET);\n+ }\n+ /* Move data from user buff to registers */\n+ for (i = 0; i < cfg->dataLen; i++)\n+ {\n+ *(pData + i) = (uint32_t)(*(cfg->dataAddr + i));\n+ }\n+\n+ /* Trig a request for transmit */\n+ if(ISO11898_MODE_VALUE_RESET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+ else if(ISO11898_MODE_VALUE_LISTEN_ONLY == ISO11898_Mode_Get(ISO11898_MODE_TYPE_LISTEN_ONLY))\n+ {\n+ return ERROR;\n+ }\n+ else if(ISO11898_MODE_VALUE_SELF_TSET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_SELF_TSET))\n+ {\n+ ISO11898_Cmd_Request_Self_Reception();\n+ }\n+ else\n+ {\n+ ISO11898_Cmd_Request_Transmit();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+BL_Err_Type ISO11898_Receive(ISO11898_CFG_Type *cfg)\n+{\n+ uint32_t timeOut;\n+ uint32_t tmpVal;\n+ uint32_t i;\n+ uint32_t id;\n+ volatile uint32_t *pData;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr));\n+\n+ timeOut = cfg->timeout;\n+\n+ /* Chcek Timeout type */\n+ while(ISO11898_STATUS_RECEIVE_BUFFER_EMPTY == ISO11898_Status_Get(ISO11898_STATUS_RECEIVE_BUFFER))\n+ {\n+ /* Wait no time */\n+ if (cfg->timeout == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ /* Wait until transmit buffer accessible */\n+ if (cfg->timeout >= ISO11898_TIMEOUT_MAX)\n+ {\n+\n+ }\n+ /* Wait time = cfg->timeOut */\n+ else\n+ {\n+ if(timeOut == 0)\n+ {\n+ return TIMEOUT;\n+ }\n+ timeOut--;\n+ }\n+ }\n+\n+ /* Read information register */\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INFORMATION);\n+ cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF);\n+ cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR);\n+ cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_DLC);\n+\n+ /* Receive with 11 bits ID */\n+ if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat)\n+ {\n+ /* Read identifier registers */\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1);\n+ id = ((tmpVal & 0xFF) << 3);\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2);\n+ id |= (tmpVal & 0xFF) >> 5;\n+ /* Config SFF data registers start address */\n+ pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET);\n+ }\n+ /* Receive with 29 bits ID */\n+ else\n+ {\n+ /* Read identifier registers */\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1);\n+ id = ((tmpVal & 0xFF) << 21);\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2);\n+ id |= (tmpVal & 0xFF) << 13;\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3);\n+ id |= (tmpVal & 0xFF) << 5;\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4);\n+ id |= (tmpVal & 0xFF) >> 3;\n+ /* Config EFF data registers start address */\n+ pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET);\n+ }\n+ cfg->id = id;\n+\n+ /* Move data from registers to user buff */\n+ for (i = 0; i < cfg->dataLen; i++)\n+ {\n+ *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF);\n+ }\n+\n+ ISO11898_Cmd_Release_Recv_Buff();\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t ISO11898_Receive_Buff_Frame_Count_Get(void)\n+{\n+ volatile uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_RX_MESSAGE_COUNT);\n+ return (uint8_t)(tmpVal & 0xFF);\n+}\n+\n+BL_Err_Type ISO11898_Clock_Div_Set(uint8_t div)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Must be operated in reset mode */\n+ if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER, div);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t ISO11898_Clock_Div_Get(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0);\n+ return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER);\n+}\n+\n+BL_Err_Type ISO11898_Synchronization_Jump_Width_Set(uint8_t width)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Must be operated in reset mode */\n+ if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH, width);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+uint8_t ISO11898_Synchronization_Jump_Width_Get(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0);\n+ return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH);\n+}\n+\n+BL_Err_Type ISO11898_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Must be operated in reset mode */\n+ if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET))\n+ {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1, head);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2, tail);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING, num);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1, tmpVal & 0xFF);\n+\n+ return SUCCESS;\n+}\n+\n+void ISO11898_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1);\n+ *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1);\n+ *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2);\n+ *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING);\n+}\n+\n+void ISO11898_Filter_Set(const ISO11898_FILTER_CFG_Type *cfg)\n+{\n+ uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask\n+\n+ /* Config filter must be in reset mode */\n+ ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET);\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET);\n+\n+\n+ /* Single filter mode */\n+ if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode)\n+ {\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE);\n+ /* Filter: ID10~0 + RTR + Data1 + Data2 */\n+ if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 << 5);\n+ tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4);\n+ tmpVal[2] = cfg->matchData1;\n+ tmpVal[3] = cfg->matchData2;\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 << 5);\n+ tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4);\n+ tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0\n+ tmpVal[6] = cfg->maskData1;\n+ tmpVal[7] = cfg->maskData2;\n+ }\n+ /* Filter: ID28~0 + RTR */\n+ else if(ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13);\n+ tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5);\n+ tmpVal[3] = (uint8_t)(cfg->matchId1 << 3);\n+ tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13);\n+ tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5);\n+ tmpVal[7] = (uint8_t)(cfg->maskId1 << 3);\n+ tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2);\n+ tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0\n+ }\n+ }\n+ /* Dual filter mode */\n+ else if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode)\n+ {\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL);\n+ /* Filter1: ID10~0 + RTR + Data1 */\n+ /* Filter2: ID10~0 + RTR */\n+ if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 << 5);\n+ tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4);\n+ tmpVal[1] |= (cfg->matchData1 >> 4);\n+ tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3);\n+ tmpVal[3] = (uint8_t)(cfg->matchId2 << 5);\n+ tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4);\n+ tmpVal[3] |= (cfg->matchData1 & 0xF);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 << 5);\n+ tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4);\n+ tmpVal[5] |= (cfg->maskData1 >> 4);\n+ tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3);\n+ tmpVal[7] = (uint8_t)(cfg->maskId2 << 5);\n+ tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4);\n+ tmpVal[7] |= (cfg->maskData1 & 0xF);\n+ }\n+ /* Filter1: ID28~13 */\n+ /* Filter2: ID28~13 */\n+ else if (ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType)\n+ {\n+ tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21);\n+ tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13);\n+ tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21);\n+ tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13);\n+ tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21);\n+ tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13);\n+ tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21);\n+ tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13);\n+ }\n+ }\n+ /* Write configuration to Registers*/\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)tmpVal[4]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)tmpVal[5]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)tmpVal[6]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)tmpVal[7]);\n+\n+ /* Recovery reset mode value */\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset);\n+}\n+\n+void ISO11898_Filter_Register_Set(ISO11898_FILTER_REGISTER_Type reg, uint8_t value)\n+{\n+ /* Config filter must be in reset mode */\n+ ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET);\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET);\n+\n+ /* Write configuration to Register*/\n+ BL_WR_WORD(ISO11898_BASE + ISO11898_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value);\n+\n+ /* Recovery reset mode value */\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset);\n+}\n+\n+void ISO11898_Filter_Registers_Set(uint8_t *valueArr)\n+{\n+ /* Config filter must be in reset mode */\n+ ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET);\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET);\n+\n+ /* Write configuration to Registers*/\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)valueArr[4]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)valueArr[5]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)valueArr[6]);\n+ BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)valueArr[7]);\n+\n+ /* Recovery reset mode value */\n+ ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset);\n+}\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type ISO11898_Int_Callback_Install(ISO11898_INT_Type intType,intCallback_Type* cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cbFun));\n+ CHECK_PARAM(IS_ISO11898_INT_TYPE(intType));\n+\n+ iso11898IntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+\n+static void ISO11898_IntHandler(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t i = 0;\n+\n+ tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT);\n+\n+ for(i=0; i<ISO11898_INT_ALL; i++)\n+ {\n+ if(tmpVal & (1 << i))\n+ {\n+ if (iso11898IntCbfArra[i])\n+ {\n+ iso11898IntCbfArra[i]();\n+ }\n+ }\n+ }\n+}\n+\n+void ISO11898_IRQHandler(void)\n+{\n+ ISO11898_IntHandler();\n+}\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9f72604763423b474b7c5a7d3fa00d8e4a2b669b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c\n@@ -0,0 +1,408 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_l1c.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_l1c.h\"\n+#include \"bl808_common.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup L1C\n+ * @{\n+ */\n+\n+/** @defgroup L1C_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Private_Macros */\n+\n+/** @defgroup L1C_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Private_Types */\n+\n+/** @defgroup L1C_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Private_Variables */\n+\n+/** @defgroup L1C_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Global_Variables */\n+\n+/** @defgroup L1C_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Private_Fun_Declaration */\n+\n+/** @defgroup L1C_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group L1C_Private_Functions */\n+\n+/** @defgroup L1C_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Enable I-Cache\n+ *\n+ * @param wayDsiable: cache way disable config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Enable(uint8_t wayDsiable)\n+{\n+#ifndef __riscv_32e\n+ csi_icache_enable();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable D-Cache\n+ *\n+ * @param wayDsiable: cache way disable config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Enable(uint8_t wayDsiable)\n+{\n+#ifndef __riscv_32e\n+ csi_dcache_enable();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable I-Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Disable(void)\n+{\n+#ifndef __riscv_32e\n+ csi_icache_disable();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable D-Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Disable(void)\n+{\n+#ifndef __riscv_32e\n+ csi_dcache_disable();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief L1C D-Cache write set\n+ *\n+ * @param wtEn: L1C write through enable\n+ * @param wbEn: L1C write back enable\n+ * @param waEn: L1C write allocate enable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+__WEAK\n+void ATTR_TCM_SECTION L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)\n+{\n+ return;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clean all D_Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_All(void)\n+{\n+#ifndef __riscv_32e\n+ csi_dcache_clean();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clean and invalid all D_Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_All(void)\n+{\n+#ifndef __riscv_32e\n+ csi_dcache_clean_invalid();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Invalid all I-Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_All(void)\n+{\n+#ifndef __riscv_32e\n+ csi_icache_invalid();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Invalid all D_Cache\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_All(void)\n+{\n+#ifndef __riscv_32e\n+ csi_dcache_invalid();\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clean D-Cache according to address\n+ *\n+ * @param addr: Address to clean\n+ * @param len: Length to clean\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len)\n+{\n+#ifndef __riscv_32e\n+#ifdef CPU_D0\n+ csi_dcache_clean_range((uintptr_t *)addr, len);\n+#else\n+ csi_dcache_clean_range((uint32_t *)(uintptr_t *)addr, len);\n+#endif\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clean and invalid D-Cache according to address\n+ *\n+ * @param addr: Address to clean\n+ * @param len: Length to clean\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len)\n+{\n+#ifndef __riscv_32e\n+#ifdef CPU_D0\n+ csi_dcache_clean_invalid_range((uintptr_t *)addr, len);\n+#else\n+ csi_dcache_clean_invalid_range((uint32_t *)(uintptr_t *)addr, len);\n+#endif\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Invalid I-Cache according to address\n+ *\n+ * @param addr: Address to clean\n+ * @param len: Length to clean\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len)\n+{\n+ L1C_ICache_Invalid_All();\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Invalid D-Cache according to address\n+ *\n+ * @param addr: Address to clean\n+ * @param len: Length to clean\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len)\n+{\n+#ifndef __riscv_32e\n+#ifdef CPU_D0\n+ csi_dcache_invalid_range((uintptr_t *)addr, len);\n+#else\n+ csi_dcache_invalid_range((uint32_t *)(uintptr_t *)addr, len);\n+#endif\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief cache wrap\n+ *\n+ * @param en: wrap enable or disable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(uint8_t en)\n+{\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief cache wrap\n+ *\n+ * @param core: cpu core\n+ * @param cacheSetting: cache setting\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting)\n+{\n+ (void)core;\n+ (void)cacheSetting;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Judge addr is in cache range\n+ *\n+ * @param addr: phyical addr\n+ *\n+ * @return 1 for addr is in cache range and 0 for not in cache range\n+ *\n+*******************************************************************************/\n+int ATTR_TCM_SECTION L1C_Is_DCache_Range(uintptr_t addr)\n+{\n+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;\n+\n+ /* Get core type */\n+ core = GLB_Get_Core_Type();\n+ if(core==GLB_CORE_ID_D0){\n+ if(((addr>>16)&0xffff)>=0x3ef8){\n+ return 1;\n+ }else{\n+ return 0;\n+ }\n+ }else{\n+ if(((addr>>16)&0xffff)>=0x4000){\n+ return 1;\n+ }else{\n+ return 0;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get None Cache address according to Cache address\n+ *\n+ * @param addr: cache addr\n+ *\n+ * @return none cache addr\n+ *\n+*******************************************************************************/\n+int ATTR_TCM_SECTION L1C_Get_None_Cache_Addr(uintptr_t addr)\n+{\n+ GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;\n+\n+ /* Get core type */\n+ core = GLB_Get_Core_Type();\n+ if(core==GLB_CORE_ID_D0){\n+ return addr;\n+ }else{\n+ return (addr&0x0FFFFFFF)|0x20000000;\n+ }\n+}\n+\n+/*@} end of group L1C_Public_Functions */\n+\n+/*@} end of group L1C */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_lz4d.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_lz4d.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_lz4d.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4c4875e1a5589c709853896cc3c1423236c1e625\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_lz4d.c\n@@ -0,0 +1,286 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_lz4d.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_common.h\"\n+#include \"bl808_lz4d.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup LZ4D\n+ * @{\n+ */\n+\n+/** @defgroup LZ4D_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group LZ4D_Private_Macros */\n+\n+/** @defgroup LZ4D_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group LZ4D_Private_Types */\n+\n+/** @defgroup LZ4D_Private_Variables\n+ * @{\n+ */\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *lz4dIntCbfArra[LZ4D_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group LZ4D_Private_Variables */\n+\n+/** @defgroup LZ4D_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group LZ4D_Global_Variables */\n+\n+/** @defgroup LZ4D_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group LZ4D_Private_Fun_Declaration */\n+\n+/** @defgroup LZ4D_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group LZ4D_Private_Functions */\n+\n+/** @defgroup LZ4D_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief None\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void LZ4D_Stop(void)\n+{\n+ LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0;\n+}\n+\n+void LZ4D_Start(void)\n+{\n+ LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1;\n+}\n+\n+uint32_t LZ4D_GetAddrReg(LZ4D_ADDR_REG_Type addr)\n+{\n+ uint32_t res = -1;\n+\n+ switch (addr) {\n+ case LZ4D_ADDR_END_SRC:\n+ res = LZ4DECOMPRESSOR->lz4_src_end.WORD & LZ4D_ADDR_END_MAX;\n+ break;\n+\n+ case LZ4D_ADDR_END_DST:\n+ res = LZ4DECOMPRESSOR->lz4_dst_end.WORD & LZ4D_ADDR_END_MAX;\n+ break;\n+\n+ case LZ4D_ADDR_BASE_SRC:\n+ res = LZ4DECOMPRESSOR->lz4_src_start.WORD;\n+ break;\n+\n+ case LZ4D_ADDR_BASE_DST:\n+ res = LZ4DECOMPRESSOR->lz4_dst_start.WORD;\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return res;\n+}\n+\n+uint32_t LZ4D_GetDecompressLen(void)\n+{\n+ uint32_t len = 0;\n+\n+ len = LZ4D_GetAddrReg(LZ4D_ADDR_END_DST) -\n+ (LZ4D_GetAddrReg(LZ4D_ADDR_BASE_DST) & LZ4D_ADDR_END_MAX);\n+\n+ return len;\n+}\n+\n+uint32_t LZ4D_GetStatus(LZ4D_STATUS_Type sts)\n+{\n+ uint32_t res = 0;\n+\n+ switch (sts) {\n+ case LZ4D_STATUS_DONE ... LZ4D_STATUS_ERROR:\n+ res = LZ4DECOMPRESSOR->lz4_int_sta.WORD & sts;\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return res;\n+}\n+\n+void LZ4D_Decompress(const void *in, void *out)\n+{\n+ LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0;\n+\n+ LZ4DECOMPRESSOR->lz4_src_start.WORD = (uint32_t)(uintptr_t)in;\n+ /* TODO: the out region length must be 4-byte aligned:\n+ * e.g.: the decompressed length is 33, you have to allocate 36 bytes for it.\n+ * or, the HW will overwrite the RAM space from offset 34 to 36. \n+ */\n+ LZ4DECOMPRESSOR->lz4_dst_start.WORD = (uint32_t)(uintptr_t)out;\n+\n+ /* flush the CPU D$ in case of data bas been cached,\n+ * e.g., the compressed data is copied by CPU.\n+ */\n+ //L1C_DCache_Clean_Invalid_All();\n+\n+ LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1;\n+\n+ /* after LZ4D doing it's job, CPU has to invalid the cache line for *out */\n+}\n+\n+/*******************************************************************************\n+ * @brief LZ4D mask or unmask certain or all interrupt\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: mask or unmask\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void LZ4D_IntMask(LZ4D_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ switch (intType) {\n+ case LZ4D_INT_DONE:\n+ if (UNMASK == intMask) {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1;\n+ } else {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0;\n+ }\n+ break;\n+\n+ case LZ4D_INT_ERROR:\n+ if (UNMASK == intMask) {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1;\n+ } else {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0;\n+ }\n+ break;\n+\n+ case LZ4D_INT_ALL:\n+ if (UNMASK == intMask) {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1;\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1;\n+ } else {\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0;\n+ LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0;\n+ }\n+ break;\n+\n+ default:\n+ /* invalid param */\n+ break;\n+ }\n+}\n+\n+/*******************************************************************************\n+ * @brief ADC install interrupt callback\n+ *\n+ * @param intType: ADC interrupt type\n+ * @param cbFun: ADC interrupt callback\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void LZ4D_Int_Callback_Install(LZ4D_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ if (intType < LZ4D_INT_ALL)\n+ lz4dIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/*******************************************************************************\n+ * @brief LZ4D interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void LZ4D_IRQHandler(void)\n+{\n+ if (LZ4D_GetStatus(LZ4D_STATUS_DONE)) {\n+ if (lz4dIntCbfArra[LZ4D_INT_DONE] != NULL) {\n+ lz4dIntCbfArra[LZ4D_INT_DONE]();\n+ }\n+ }\n+\n+ if (LZ4D_GetStatus(LZ4D_STATUS_ERROR)) {\n+ if (lz4dIntCbfArra[LZ4D_INT_ERROR] != NULL) {\n+ lz4dIntCbfArra[LZ4D_INT_ERROR]();\n+ }\n+ }\n+}\n+#endif\n+\n+void LZ4D_Init(void)\n+{\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(LZ4D_IRQn, LZ4D_IRQHandler);\n+#endif\n+}\n+\n+/*@} end of group LZ4D_Public_Functions */\n+\n+/*@} end of group LZ4D */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d3cbdd8822b2b900d7e2662f954ffbac35d027d8\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c\n@@ -0,0 +1,105 @@\n+#include \"bl808_glb.h\"\n+#include \"bl808_mfg_efuse.h\"\n+#include \"bl808_ef_ctrl.h\"\n+#include \"bl808_ef_cfg.h\"\n+\n+static uint8_t rf_cal_slots=3;\n+extern void main(void);\n+#define RF_CAL_SLOT_CFG_OFFSET (4*13)\n+#ifdef BFLB_MCU_SDK\n+#include \"bflb_platform.h\"\n+#define mfg_print MSG\n+#else\n+#define mfg_print printf\n+#endif\n+\n+uint8_t mfg_efuse_get_rf_cal_slots(void)\n+{\n+ return rf_cal_slots;\n+}\n+\n+void mfg_efuse_set_rf_cal_slots(uint8_t slots)\n+{\n+ rf_cal_slots=slots;\n+}\n+\n+uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload)\n+{\n+ uint8_t empty=0; \n+ \n+ \n+ if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload)){\n+ empty=1;\n+ }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload)){\n+ empty=1;\n+ }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload)){\n+ empty=1;\n+ }else{ \n+ }\n+ \n+ \n+ return empty;\n+}\n+\n+int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program)\n+{\n+ BL_Err_Type ret=SUCCESS;\n+ uint8_t slot=0xff; \n+ \n+ if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,1)){\n+ slot=0;\n+ }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,1)){\n+ slot=1;\n+ }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,1)){\n+ slot=2;\n+ }else{\n+ mfg_print(\"No empty slot found\\r\\n\");\n+ }\n+ \n+ if(slot!=0xff){\n+ ret=EF_Ctrl_Write_MAC_Address_Opt(slot,mac,program);\n+ mfg_print(\"Write slot:%d\\r\\n\",slot);\n+ }\n+ \n+ \n+ if(ret==SUCCESS){\n+ return 0;\n+ }else{\n+ return -1;\n+ }\n+}\n+\n+void mfg_efuse_write_macaddr(void)\n+{ \n+ EF_Ctrl_Program_Direct_R0(0,NULL,0);\n+ while(SET==EF_Ctrl_Busy());\n+}\n+\n+int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload)\n+{\n+ uint8_t slot=0xff;\n+ BL_Err_Type ret=ERROR;\n+ \n+ \n+ if(rf_cal_slots>=3&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload))){\n+ slot=2;\n+ }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload))){\n+ slot=1;\n+ }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload))){\n+ slot=0;\n+ }\n+ \n+ if(slot!=0xff){\n+ mfg_print(\"Read slot:%d\\r\\n\",slot);\n+ ret=EF_Ctrl_Read_MAC_Address_Opt(slot,mac,reload);\n+ }else{\n+ mfg_print(\"No written slot found\\r\\n\");\n+ }\n+ \n+ \n+ if(ret==SUCCESS){\n+ return 0;\n+ }else{\n+ return -1;\n+ }\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..600b71ac134d2febd15961889fb7c98b94559117\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c\n@@ -0,0 +1,241 @@\n+#include \"bl808_mfg_flash.h\"\n+#include \"softcrc.h\"\n+\n+static rf_para_flash_t rf_para;\n+static uint32_t rf_para_addr=0;\n+static SPI_Flash_Cfg_Type *pFlashCfg;\n+\n+//#define RF_PARA_MAGIC_FLAG 0x41504652\n+#define RF_PARA_MAGIC_FLAG 0x41\n+#define RF_PARA_VALID_FLAG 0x5A\n+#define RF_PARA_PART_NAME \"rf_para\"\n+\n+\n+//PtTable_Stuff_Config ptTableStuff[2];\n+//PtTable_Entry_Config ptEntry={0};\n+\n+\n+static BL_Err_Type PtTable_Flash_Read (uint32_t addr,uint8_t *data, uint32_t len)\n+{\n+ //XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,addr,data,len);\n+ return SUCCESS;\n+}\n+\n+int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg)\n+{\n+#if 0\n+ PtTable_ID_Type activeID;\n+ PtTable_Error_Type ret;\n+\n+ pFlashCfg=flashCfg;\n+ if(pFlashCfg!=NULL){\n+ PtTable_Set_Flash_Operation(NULL,NULL,PtTable_Flash_Read);\n+ activeID=PtTable_Get_Active_Partition_Need_Lock(ptTableStuff);\n+ if(PT_TABLE_ID_INVALID==activeID){\n+ //mfg_print(\"No valid PT\\r\\n\");\n+ return -1;\n+ }\n+ ret=PtTable_Get_Active_Entries_By_Name(&ptTableStuff[activeID],(uint8_t*)RF_PARA_PART_NAME,&ptEntry);\n+ if(PT_ERROR_SUCCESS==ret){\n+ rf_para_addr=ptEntry.Address[0];\n+ //mfg_print(\"RF para flash address=%08x\\r\\n\",(unsigned int)rf_para_addr);\n+ return 0;\n+ }else{\n+ //mfg_print(\"Not found \"RF_PARA_PART_NAME\"\\r\\n\");\n+ return -1;\n+ }\n+ }\n+#endif \n+ return -1;\n+}\n+\n+static int8_t mfg_flash_program(void)\n+{\n+#if 0\n+ BL_Err_Type ret;\n+\n+ //mfg_print(\"mfg_flash_write\\r\\n\");\n+\n+ ret=XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg,rf_para_addr,rf_para_addr+15);\n+ if(ret!=SUCCESS){\n+ //mfg_print(\"Flash erase error\\r\\n\");\n+ return -1;\n+ }\n+\n+ ret=XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para));\n+ if(ret!=SUCCESS){\n+ //mfg_print(\"Flash write error\\r\\n\");\n+ return -1;\n+ }\n+#endif\n+ return 0;\n+}\n+\n+static int8_t mfg_flash_read(void)\n+{\n+#if 0\n+ BL_Err_Type ret;\n+\n+ //mfg_print(\"mfg_flash_read\\r\\n\");\n+\n+ ret=XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para));\n+ if(ret!=SUCCESS){\n+ //mfg_print(\"Flash write error\\r\\n\");\n+ return -1;\n+ }\n+#endif\n+ return 0;\n+}\n+\n+int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program)\n+{\n+#if 0\n+ rf_para.magic=RF_PARA_MAGIC_FLAG;\n+ rf_para.capcode_valid=RF_PARA_VALID_FLAG;\n+ rf_para.capcode=capcode;\n+ rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8);\n+\n+ if(program){\n+ return mfg_flash_program();\n+ }else{\n+ return 0;\n+ }\n+#endif\n+ return 0;\n+}\n+\n+void mfg_flash_write_xtal_capcode(void)\n+{\n+ //mfg_flash_program();\n+}\n+\n+int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload)\n+{ \n+#if 0\n+ if((reload!=0)&&(mfg_flash_read()!=0)){\n+ return -1;\n+ }\n+ if(rf_para.magic==RF_PARA_MAGIC_FLAG){\n+ if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){\n+ if(rf_para.capcode_valid==RF_PARA_VALID_FLAG){\n+ *capcode=rf_para.capcode;\n+ return 0;\n+ }\n+ }\n+ }\n+#endif \n+ return -1;\n+}\n+\n+int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program)\n+{\n+#if 0\n+ rf_para.magic=RF_PARA_MAGIC_FLAG;\n+ rf_para.poweroffset_valid=RF_PARA_VALID_FLAG;\n+ rf_para.poweroffset[0]=pwrOffset[0];\n+ rf_para.poweroffset[1]=pwrOffset[6];\n+ rf_para.poweroffset[2]=pwrOffset[12];\n+ rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8);\n+\n+ if(program){\n+ return mfg_flash_program();\n+ }else{\n+ return 0;\n+ }\n+#endif \n+ return 0;\n+}\n+\n+void mfg_flash_write_poweroffset(void)\n+{\n+ //mfg_flash_program();\n+}\n+\n+int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload)\n+{\n+#if 0\n+ int8_t pwrOffsetTmp[3];\n+ int32_t step=0;\n+\n+ if((reload!=0)&&(mfg_flash_read()!=0)){\n+ return -1;\n+ }\n+ if(rf_para.magic==RF_PARA_MAGIC_FLAG){\n+ if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){\n+ if(rf_para.poweroffset_valid==RF_PARA_VALID_FLAG){\n+ memset(pwrOffset,0,14);\n+ pwrOffsetTmp[0]=rf_para.poweroffset[0];\n+ pwrOffsetTmp[1]=rf_para.poweroffset[1];\n+ pwrOffsetTmp[2]=rf_para.poweroffset[2];\n+\n+ pwrOffset[0]=pwrOffsetTmp[0];\n+\n+ step=(pwrOffsetTmp[1]-pwrOffsetTmp[0])*100/6;\n+ pwrOffset[1]=(step+50)/100+pwrOffsetTmp[0];\n+ pwrOffset[2]=(step*2+50)/100+pwrOffsetTmp[0];\n+ pwrOffset[3]=(step*3+50)/100+pwrOffsetTmp[0];\n+ pwrOffset[4]=(step*4+50)/100+pwrOffsetTmp[0];\n+ pwrOffset[5]=(step*5+50)/100+pwrOffsetTmp[0];\n+\n+ pwrOffset[6]=pwrOffsetTmp[1];\n+\n+ step=(pwrOffsetTmp[2]-pwrOffsetTmp[1])*100/6;\n+ pwrOffset[7]=(step+50)/100+pwrOffsetTmp[1];\n+ pwrOffset[8]=(step*2+50)/100+pwrOffsetTmp[1];\n+ pwrOffset[9]=(step*3+50)/100+pwrOffsetTmp[1];\n+ pwrOffset[10]=(step*4+50)/100+pwrOffsetTmp[1];\n+ pwrOffset[11]=(step*5+50)/100+pwrOffsetTmp[1];\n+\n+ pwrOffset[12]=pwrOffsetTmp[2];\n+\n+ pwrOffset[13]=(step*7+50)/100+pwrOffsetTmp[1];\n+ return 0;\n+ }\n+ }\n+ }\n+#endif \n+ return -1;\n+ \n+}\n+\n+int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program)\n+{\n+#if 0\n+ rf_para.magic=RF_PARA_MAGIC_FLAG;\n+ rf_para.mac_valid=RF_PARA_VALID_FLAG;\n+ memcpy(rf_para.mac,mac,6);\n+ rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8);\n+\n+ if(program){\n+ return mfg_flash_program();\n+ }else{\n+ return 0;\n+ }\n+#endif\n+ return 0;\n+}\n+\n+void mfg_flash_write_macaddr(void)\n+{\n+ //mfg_flash_program();\n+}\n+\n+int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload)\n+{\n+#if 0\n+ if((reload!=0)&&(mfg_flash_read()!=0)){\n+ //mfg_print(\"mfg_flash_read fail\\r\\n\");\n+ return -1;\n+ }\n+ if(rf_para.magic==RF_PARA_MAGIC_FLAG){\n+ if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){\n+ if(rf_para.mac_valid==RF_PARA_VALID_FLAG){\n+ memcpy(mac,rf_para.mac,6);\n+ return 0;\n+ }\n+ }\n+ }\n+#endif \n+ return -1;\n+}\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..78f34a436284f363c466e0f61ea665e82fdd1921\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c\n@@ -0,0 +1,237 @@\n+#include \"bl808_mfg_media.h\"\n+\n+static uint8_t rf_para_on_flash=0;\n+\n+#if 0\n+int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ if(0==mfg_flash_init(flashCfg)){\n+ rf_para_on_flash=1;\n+ }else{\n+ rf_para_on_flash=0;\n+ }\n+ return 0;\n+}\n+\n+int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ int8_t ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_init_need_lock(flashCfg);\n+ __enable_irq();\n+\n+ return ret;\n+}\n+\n+uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return 1;\n+ }else{\n+ return mfg_efuse_is_xtal_capcode_slot_empty(reload);\n+ }\n+}\n+\n+int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_xtal_capcode_pre(capcode,program);\n+ }else{\n+ return mfg_efuse_write_xtal_capcode_pre(capcode,program);\n+ }\n+}\n+\n+int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program)\n+{\n+ int8_t ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_write_xtal_capcode_pre_need_lock(capcode,program);\n+ __enable_irq();\n+\n+ return ret;\n+}\n+\n+void mfg_media_write_xtal_capcode_need_lock(void)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_xtal_capcode();\n+ }else{\n+ return mfg_efuse_write_xtal_capcode();\n+ }\n+}\n+\n+void mfg_media_write_xtal_capcode_with_lock(void)\n+{\n+ __disable_irq();\n+ mfg_media_write_xtal_capcode_need_lock();\n+ __enable_irq();\n+}\n+\n+int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_read_xtal_capcode(capcode,reload);\n+ }else{\n+ return mfg_efuse_read_xtal_capcode(capcode,reload);\n+ }\n+}\n+\n+int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload)\n+{\n+ int8_t ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_read_xtal_capcode_need_lock(capcode,reload);\n+ __enable_irq();\n+\n+ return ret;\n+}\n+\n+int8_t mfg_media_read_xtal_capcode(uint8_t *capcode,uint8_t reload)\n+{\n+ return mfg_media_read_xtal_capcode_need_lock(capcode,reload);\n+}\n+\n+uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return 1;\n+ }else{\n+ return mfg_efuse_is_poweroffset_slot_empty(reload);\n+ }\n+}\n+\n+int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_poweroffset_pre(pwrOffset,program);\n+ }else{\n+ return mfg_efuse_write_poweroffset_pre(pwrOffset,program);\n+ }\n+}\n+\n+int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program)\n+{\n+ int ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_write_poweroffset_pre_need_lock(pwrOffset,program);\n+ __enable_irq();\n+\n+ return ret;\n+}\n+\n+void mfg_media_write_poweroffset_need_lock(void)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_poweroffset();\n+ }else{\n+ return mfg_efuse_write_poweroffset();\n+ }\n+}\n+\n+void mfg_media_write_poweroffset_with_lock(void)\n+{\n+ __disable_irq();\n+ mfg_media_write_poweroffset_need_lock();\n+ __enable_irq();\n+}\n+\n+int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_read_poweroffset(pwrOffset,reload);\n+ }else{\n+ return mfg_efuse_read_poweroffset(pwrOffset,reload);\n+ }\n+}\n+\n+int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload)\n+{\n+ int ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_read_poweroffset_need_lock(pwrOffset,reload);\n+ __enable_irq();\n+ \n+ return ret;\n+}\n+\n+int8_t mfg_media_read_poweroffset(int8_t pwrOffset[14],uint8_t reload)\n+{\n+ return mfg_media_read_poweroffset_need_lock(pwrOffset,reload);\n+}\n+#endif\n+uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return 1;\n+ }else{\n+ return mfg_efuse_is_macaddr_slot_empty(reload);\n+ }\n+}\n+\n+int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_macaddr_pre(mac,program);\n+ }else{\n+ return mfg_efuse_write_macaddr_pre(mac,program);\n+ }\n+}\n+\n+int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program)\n+{\n+ int ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_write_macaddr_pre_need_lock(mac,program); \n+ __enable_irq();\n+ \n+ return ret;\n+}\n+\n+void mfg_media_write_macaddr_need_lock(void)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_write_macaddr();\n+ }else{\n+ return mfg_efuse_write_macaddr();\n+ }\n+}\n+\n+void mfg_media_write_macaddr_with_lock(void)\n+{\n+ __disable_irq();\n+ mfg_media_write_macaddr_need_lock(); \n+ __enable_irq();\n+}\n+\n+int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload)\n+{\n+ if(rf_para_on_flash){\n+ return mfg_flash_read_macaddr(mac,reload);\n+ }else{\n+ return mfg_efuse_read_macaddr(mac,reload);\n+ }\n+}\n+\n+int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload)\n+{\n+ int ret;\n+\n+ __disable_irq();\n+ ret=mfg_media_read_macaddr_need_lock(mac,reload); \n+ __enable_irq();\n+\n+ return ret;\n+}\n+\n+int8_t mfg_media_read_macaddr(uint8_t mac[6],uint8_t reload)\n+{\n+\n+ return mfg_media_read_macaddr_need_lock(mac,reload);\n+}\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..825a3ec617ca7f047ff4710ad495992758fe1b77\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c\n@@ -0,0 +1,467 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_mjdec.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_mjdec.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup MJDEC\n+ * @{\n+ */\n+\n+/** @defgroup MJDEC_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group MJDEC_Private_Macros */\n+\n+/** @defgroup MJDEC_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group MJDEC_Private_Types */\n+\n+/** @defgroup MJDEC_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type * mjdecIntCbfArra[MJDEC_INT_ALL] = {NULL};\n+#endif\n+\n+/*@} end of group MJDEC_Private_Variables */\n+\n+/** @defgroup MJDEC_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group MJDEC_Global_Variables */\n+\n+/** @defgroup MJDEC_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group MJDEC_Private_Fun_Declaration */\n+\n+/** @defgroup MJDEC_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group MJDEC_Private_Functions */\n+\n+/** @defgroup MJDEC_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************//**\n+ * @brief Mjdec module init\n+ *\n+ * @param cfg: Mjdec configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Init(MJDEC_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t q;\n+\n+ /* disable mjdec */\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal);\n+\n+ if(cfg->picQuality < 1) {\n+ q = 1;\n+ } else if(cfg->picQuality > 75) {\n+ q = 100;\n+ } else {\n+ q = cfg->picQuality;\n+ }\n+\n+ /* basic configure */\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_YUV_MODE, cfg->yuv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_W_XLEN, cfg->burstWrite);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_R_XLEN, cfg->burstRead);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_U_EVEN, cfg->evenOrderEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_BLK_DMY, cfg->dmyBlock);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_HBLK_DMY, cfg->dmyVertical);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_WBLK_DMY, cfg->dmyHorizational);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_SWAP_MODE, cfg->swapMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,cfg->intCnt);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3,tmpVal);\n+\n+ /* align buffer to 16 bytes boundary */\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_YY_FRAME_ADDR, (cfg->bufferFrameYY + 0xF) & (~0xF));\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_UV_FRAME_ADDR, (cfg->bufferFrameUV + 0xF) & (~0xF));\n+ \n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_FRAME_SIZE);\n+ switch(cfg->yuv)\n+ {\n+ case MJDEC_YUV422_PLANAR:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3);\n+ break;\n+ case MJDEC_YUV420:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+15)>>4);\n+ break;\n+ case MJDEC_YUV400:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+7)>>3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_FRAME_SIZE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_HEADER_SKIP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP, cfg->headSkip);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP_BYTE, cfg->headByte);\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_HEADER_SKIP, tmpVal);\n+\n+ /* Clear interrupt */\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 0x1);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(MJDEC_IRQn, MJDEC_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************//**\n+ * @brief Deinit mjdec module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Deinit(void)\n+{\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG_DEC);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Enable mjdec module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable mjdec module */\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Disable mjdec module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable mjdec module */\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get one mjdec frame\n+ *\n+ * @param info: Mjdec frame infomation pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Get_Frame_Info(MJDEC_Frame_Info *info)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3);\n+ info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJDEC_FRAME_VALID_CNT);\n+ info->curFrameAddr = BL_RD_REG(MJDEC_BASE, MJDEC_JP_ADDR0);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Get available count of frames\n+ *\n+ * @param None\n+ *\n+ * @return Frames count\n+ *\n+*******************************************************************************/\n+uint8_t MJDEC_Get_Frame_Count(void)\n+{\n+ return (uint8_t)BL_GET_REG_BITS_VAL(BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3), MJDEC_FRAME_VALID_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Push one jpeg picture frame\n+ *\n+ * @param bufferMjpeg: jpeg picture frame buffer pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+BL_Err_Type MJDEC_Push_Frame(uint32_t bufferJpeg)\n+{\n+ /* because of AXI 64bits, bufferJpeg address bit [0:2] must be 0 */\n+ if((bufferJpeg & 0x07) != 0)\n+ {\n+ return INVALID;\n+ }\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_FRAM_PUSH, bufferJpeg | 0x1);\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************//**\n+ * @brief Pop one mjdec frame\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Pop_Frame(void)\n+{\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 1 << 1);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Set frame threshold to issue normal interrupt\n+ *\n+ * @param count: Frame threshold\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Set_Frame_Threshold(uint8_t count)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,count);\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Set Q value\n+ *\n+ * @param q: Q value, must be in 1-75 or 100\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_Set_Q_Value(uint8_t q)\n+{\n+ uint32_t tmpVal;\n+\n+ if(q < 1) {\n+ q = 1;\n+ } else if(q > 75) {\n+ q = 100;\n+ }\n+ tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q);\n+ BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief MJDEC Enable Disable Interrupt\n+ *\n+ * @param intType: MJDEC Interrupt Type\n+ * @param intMask: Enable or Disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_IntMask(MJDEC_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_MJDEC_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3);\n+ switch(intType)\n+ {\n+ case MJDEC_INT_NORMAL:\n+ if(intMask == UNMASK){\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN);\n+ }else{\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN);\n+ }\n+ break;\n+\n+ case MJDEC_INT_BACK_IDLE:\n+ if(intMask == UNMASK){\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN);\n+ }else{\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN);\n+ }\n+ break;\n+\n+ case MJDEC_INT_ALL:\n+ if(intMask == UNMASK){\n+ /* Enable all interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN);\n+ }else{\n+ /* Disable all interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN);\n+ }\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief MJDEC Interrupt Clear\n+ *\n+ * @param intType: MJDEC Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJDEC_IntClr(MJDEC_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ \n+ CHECK_PARAM(IS_MJDEC_INT_TYPE(intType));\n+ \n+ tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR);\n+ switch(intType)\n+ {\n+ case MJDEC_INT_NORMAL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR);\n+ break;\n+ case MJDEC_INT_BACK_IDLE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR);\n+ break;\n+ case MJDEC_INT_ALL:\n+ tmpVal = 0x1;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR,tmpVal);\n+}\n+\n+/****************************************************************************//**\n+ * @brief Install mjdec interrupt callback function\n+ *\n+ * @param intType: MJDEC interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void MJDEC_Int_Callback_Install(MJDEC_INT_Type intType,intCallback_Type* cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_MJDEC_INT_TYPE(intType));\n+\n+ mjdecIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************//**\n+ * @brief Mjdec interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void MJDEC_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+ \n+ tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3);\n+ BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1);\n+ if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_NORMAL_INT) ){\n+ // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1);\n+ if(mjdecIntCbfArra[MJDEC_INT_NORMAL] != NULL) {\n+ /* call the callback function */\n+ mjdecIntCbfArra[MJDEC_INT_NORMAL]();\n+ }\n+ }\n+ if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_IDLE_INT) ){\n+ // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1);\n+ if(mjdecIntCbfArra[MJDEC_INT_BACK_IDLE] != NULL) {\n+ /* call the callback function */\n+ mjdecIntCbfArra[MJDEC_INT_BACK_IDLE]();\n+ }\n+ }\n+}\n+#endif\n+\n+\n+/*@} end of group MJDEC_Public_Functions */\n+\n+/*@} end of group MJDEC */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b41bc29a7810d6ab316ba0f496cb3fdc79028bfc\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c\n@@ -0,0 +1,1006 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_mjpeg.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_mjpeg.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup MJPEG\n+ * @{\n+ */\n+\n+/** @defgroup MJPEG_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group MJPEG_Private_Macros */\n+\n+/** @defgroup MJPEG_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group MJPEG_Private_Types */\n+\n+/** @defgroup MJPEG_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group MJPEG_Private_Variables */\n+\n+/** @defgroup MJPEG_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group MJPEG_Global_Variables */\n+\n+/** @defgroup MJPEG_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group MJPEG_Private_Fun_Declaration */\n+\n+/** @defgroup MJPEG_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group MJPEG_Private_Functions */\n+\n+/** @defgroup MJPEG_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Mjpeg module init\n+ *\n+ * @param cfg: Mjpeg configuration structure pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Init(MJPEG_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_MJPEG);\n+\n+ /* disable mjpeg */\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);\n+\n+ /* basic configure */\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_HW_FRAME, cfg->frameCount);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_XLEN, cfg->burst);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_READ_FWRAP, cfg->readStartEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE);\n+\n+ switch (cfg->yuv) {\n+ case MJPEG_YUV422_INTERLEAVE:\n+ case MJPEG_YUV422_PLANAR:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);\n+ break;\n+\n+ case MJPEG_YUV420:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4);\n+ break;\n+\n+ case MJPEG_YUV400:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal);\n+\n+ /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/\n+ BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0));\n+ BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0));\n+ BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY);\n+\n+ /*align buffer to 16 bytes boundary*/\n+ BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0));\n+\n+ /*Set memory brust size */\n+ if (cfg->burst == MJPEG_BURST_SINGLE) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 8);\n+ } else if (cfg->burst == MJPEG_BURST_INCR4) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 32);\n+ } else if (cfg->burst == MJPEG_BURST_INCR8) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 64);\n+ } else if (cfg->burst == MJPEG_BURST_INCR16) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 128);\n+ }\n+\n+ /* Clear interrupt */\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mjpeg set YUYV order, only work in interleave mode\n+ *\n+ * @param y0: Y0 order\n+ * @param u0: U0 order\n+ * @param y1: Y1 order\n+ * @param v0: V0 order\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mjpeg set Y/UV input cam id, only work in planar mode\n+ *\n+ * @param yCamId: Cam id of Y used\n+ * @param uvCamId: Cam id of UV used\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Planar_Y_UV_Input(uint8_t yCamId, uint8_t uvCamId)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AXI_SEL, yCamId);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AXI_SEL, uvCamId);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Deinit mjpeg module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Deinit(void)\n+{\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable mjpeg module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable mjpeg module */\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable mjpeg module\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable mjpeg module */\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable&disable mjpeg software mode and set frame count\n+ *\n+ * @param swType: SW mode type\n+ * @param count: Frame count\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_SW_Enable(MJPEG_SW_Mode_Type swType, uint8_t count)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_MODE, swType);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MJPEG software mode run, software mode enable first\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_SW_Run(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set memory to store block line for frame on SW kick\n+ *\n+ * @param count: Block line count\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_SW_Set_Kick_Block(uint16_t count)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_HBLK, count);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MJPEG SW mode kick once\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_SW_Kick(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_SW_KICK);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get one mjpeg frame\n+ *\n+ * @param info: Mjpeg frame infomation pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);\n+\n+ info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT);\n+ info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_ID_10), MJPEG_FRAME_ID_0);\n+ info->curFrameAddr = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0);\n+ info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3;\n+ info->status = tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get available count of frames\n+ *\n+ * @param None\n+ *\n+ * @return Frames count\n+ *\n+*******************************************************************************/\n+uint8_t MJPEG_Get_Frame_Count(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Pop one mjpeg frame\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Pop_Frame(void)\n+{\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Free current read memory block\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Current_Block_Clear(void)\n+{\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Current read memory block index\n+ *\n+ * @param None\n+ *\n+ * @return Block number\n+ *\n+*******************************************************************************/\n+MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void)\n+{\n+ return (MJPEG_Swap_Block_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get block status, full or not full\n+ *\n+ * @param block: Block number\n+ *\n+ * @return Block status\n+ *\n+*******************************************************************************/\n+BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block)\n+{\n+ CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block));\n+\n+ if (MJPEG_BLOCK_0 == block) {\n+ return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL);\n+ } else {\n+ return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Current read memory block is frame start\n+ *\n+ * @param None\n+ *\n+ * @return Set or reset\n+ *\n+*******************************************************************************/\n+BL_Sts_Type MJPEG_Current_Block_Is_Start(void)\n+{\n+ return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Current read memory block is frame end\n+ *\n+ * @param None\n+ *\n+ * @return Set or reset\n+ *\n+*******************************************************************************/\n+BL_Sts_Type MJPEG_Current_Block_Is_End(void)\n+{\n+ return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get frame remain bit count in last block, only valid when current read memory block is\n+ * frame end\n+ *\n+ * @param None\n+ *\n+ * @return Bit count\n+ *\n+*******************************************************************************/\n+uint32_t MJPEG_Get_Remain_Bit(void)\n+{\n+ return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set frame threshold to issue normal interrupt\n+ *\n+ * @param count: Frame threshold\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Frame_Threshold(uint8_t count)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set bytes of frame head to preserve\n+ *\n+ * @param size: Bytes of head\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Frame_Head_Set_Size(uint16_t size)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, size);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable or disable auto fill frame tail with 0xff and 0xd9\n+ *\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Frame_Tail_Auto_Fill(BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, enable);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set parameter in Y quantize table according to index\n+ *\n+ * @param index: Q parameter index\n+ * @param qParameter: Q parameter value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Quantize_Parameter_Y(uint8_t index, uint16_t qParameter)\n+{\n+ uint32_t tmpVal;\n+\n+ if (index > 63) {\n+ return;\n+ }\n+\n+ index = index % 8 * 8 + index / 8;\n+\n+ tmpVal = 2048 / qParameter;\n+\n+ if (20480 / qParameter % 10 > 4) {\n+ tmpVal++;\n+ }\n+\n+ qParameter = tmpVal & 0xffff;\n+\n+ tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4);\n+ BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set parameter in UV quantize table according to index\n+ *\n+ * @param index: Q parameter index\n+ * @param qParameter: Q parameter value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Quantize_Parameter_UV(uint8_t index, uint16_t qParameter)\n+{\n+ uint32_t tmpVal;\n+\n+ if (index > 63) {\n+ return;\n+ }\n+\n+ index = index % 8 * 8 + index / 8;\n+\n+ tmpVal = 2048 / qParameter;\n+\n+ if (20480 / qParameter % 10 > 4) {\n+ tmpVal++;\n+ }\n+\n+ qParameter = tmpVal & 0xffff;\n+\n+ tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4);\n+ BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set Y quantize table\n+ *\n+ * @param qTable: Y table\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Quantize_Table_Y(uint16_t *qTable)\n+{\n+ uint8_t i, j;\n+ uint16_t tmpVal1;\n+ uint16_t tmpVal2;\n+\n+ for (i = 0; i < 8; i++) {\n+ for (j = 0; j < 4; j++) {\n+ tmpVal1 = 2048 / qTable[16 * j + i];\n+ tmpVal2 = 2048 / qTable[16 * j + i + 8];\n+\n+ if (20480 / qTable[16 * j + i] % 10 > 4) {\n+ tmpVal1++;\n+ }\n+\n+ if (20480 / qTable[16 * j + i + 8] % 10 > 4) {\n+ tmpVal2++;\n+ }\n+\n+ BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16);\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set UV quantize table\n+ *\n+ * @param qTable: UV table\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Set_Quantize_Table_UV(uint16_t *qTable)\n+{\n+ uint8_t i, j;\n+ uint16_t tmpVal1;\n+ uint16_t tmpVal2;\n+\n+ for (i = 0; i < 8; i++) {\n+ for (j = 0; j < 4; j++) {\n+ tmpVal1 = 2048 / qTable[16 * j + i];\n+ tmpVal2 = 2048 / qTable[16 * j + i + 8];\n+\n+ if (20480 / qTable[16 * j + i] % 10 > 4) {\n+ tmpVal1++;\n+ }\n+\n+ if (20480 / qTable[16 * j + i + 8] % 10 > 4) {\n+ tmpVal2++;\n+ }\n+\n+ BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16);\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Calculate quantize table according to input table and quality factor\n+ *\n+ * @param inputTable: Pointer of input table\n+ * @param outputTable: Pointer of output table\n+ * @param quality: Quality factor\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Calculate_Quantize_Table(uint16_t *inputTable, uint16_t *outputTable, uint8_t quality)\n+{\n+ uint32_t scaleFactor, i;\n+\n+ if (quality == 0) {\n+ quality = 1;\n+ } else if (quality > 100) {\n+ quality = 100;\n+ }\n+\n+ if (quality < 50) {\n+ scaleFactor = 5000000 / quality;\n+ } else {\n+ scaleFactor = 200000 - quality * 2000;\n+ }\n+\n+ for (i = 0; i < 64; i++) {\n+ outputTable[i] = (inputTable[i] * scaleFactor + 50000) / 100000;\n+\n+ if (outputTable[i] == 0) {\n+ outputTable[i] = 1;\n+ } else if (outputTable[i] > 0xff) {\n+ outputTable[i] = 0xff;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Quantize SRAM switch\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_Quantize_SRAM_Switch(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_Q_SRAM_SW);\n+ BL_WR_REG(MJPEG_BASE, MJPEG_Q_ENC, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get current quantize SRAM selection for encode\n+ *\n+ * @param None\n+ *\n+ * @return Current quantize SRAM\n+ *\n+*******************************************************************************/\n+uint8_t MJPEG_Get_Current_Quantize_SRAM(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC);\n+ return BL_GET_REG_BITS_VAL(tmpVal, MJPEG_STS_Q_SRAM_ENC);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get frame0~3 quantize SRAM selection\n+ *\n+ * @param frameId: Frame id\n+ *\n+ * @return Quantize SRAM\n+ *\n+*******************************************************************************/\n+uint8_t MJPEG_Get_Frame_Quantize_SRAM(MJPEG_Frame_ID_Type frameId)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC);\n+ return (tmpVal >> frameId & 1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MJPEG Enable Disable Interrupt\n+ *\n+ * @param intType: MJPEG Interrupt Type\n+ * @param intMask: Enable or Disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);\n+\n+ switch (intType) {\n+ case MJPEG_INT_NORMAL:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_CAM_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_MEM_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_FRAME_OVERWRITE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_BACK_IDLE:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_SWAP:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);\n+ } else {\n+ /* Disable this interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);\n+ }\n+\n+ break;\n+\n+ case MJPEG_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* Enable all interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);\n+ } else {\n+ /* Disable all interrupt */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MJPEG Interrupt Clear\n+ *\n+ * @param intType: MJPEG Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void MJPEG_IntClr(MJPEG_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP);\n+\n+ switch (intType) {\n+ case MJPEG_INT_NORMAL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR);\n+ break;\n+\n+ case MJPEG_INT_CAM_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR);\n+ break;\n+\n+ case MJPEG_INT_MEM_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR);\n+ break;\n+\n+ case MJPEG_INT_FRAME_OVERWRITE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR);\n+ break;\n+\n+ case MJPEG_INT_BACK_IDLE:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR);\n+ break;\n+\n+ case MJPEG_INT_SWAP:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR);\n+ break;\n+\n+ case MJPEG_INT_ALL:\n+ tmpVal = 0x3F00;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install mjpeg interrupt callback function\n+ *\n+ * @param intType: MJPEG interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));\n+\n+ mjpegIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Mjpeg interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void MJPEG_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_NORMAL]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_BACK_IDLE]();\n+ }\n+ }\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) {\n+ BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000);\n+\n+ if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) {\n+ /* call the callback function */\n+ mjpegIntCbfArra[MJPEG_INT_SWAP]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group MJPEG_Public_Functions */\n+\n+/*@} end of group MJPEG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e7cab7b558338324b62f2b7be00653bc6a3bd766\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c\n@@ -0,0 +1,480 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_osd_blend.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2021 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_osd_blend.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup OSD_BLEND\n+ * @{\n+ */\n+\n+/** @defgroup OSD_BLEND_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Private_Macros */\n+\n+/** @defgroup OSD_BLEND_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Private_Types */\n+\n+/** @defgroup OSD_BLEND_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Private_Variables */\n+\n+/** @defgroup OSD_BLEND_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Global_Variables */\n+\n+/** @defgroup OSD_BLEND_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Private_Fun_Declaration */\n+\n+/** @defgroup OSD_BLEND_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group OSD_BLEND_Private_Functions */\n+\n+/** @defgroup OSD_BLEND_Public_Functions\n+ * @{\n+ */\n+\n+/******************************************************************************\n+ * @brief OSD blend layer configuration\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param xstart: OSD layer start point: x-axis, better to be even.\n+ * @param ystart: OSD layer start point: y-axis, better to be even.\n+ * @param xend: OSD layer end point: x-axis, better to be odd.\n+ * @param yend: OSD layer end point: y-axis, better to be odd.\n+ * @param data: OSD layer data buffer pointer.\n+ * @param dat_len: data length in dword size(8bytes).\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_config_layer(osd_blend_reg_t *pblend,\n+ uint32_t xstart, uint32_t ystart,\n+ uint32_t xend, uint32_t yend,\n+ uintptr_t *data, uint32_t dat_len)\n+{\n+ pblend->obnd_layer_xconfig.WORD = (xstart & OSD_BLEND_OBND_X_MIN_MSK) |\n+ ((xend << OSD_BLEND_OBND_X_MAX_POS) & OSD_BLEND_OBND_X_MAX_MSK);\n+ pblend->obnd_layer_yconfig.WORD = (ystart & OSD_BLEND_OBND_Y_MIN_MSK) |\n+ ((yend << OSD_BLEND_OBND_Y_MAX_POS) & OSD_BLEND_OBND_Y_MAX_MSK);\n+\n+ pblend->obnd_mem_config1.WORD = (uint32_t)(uintptr_t)data;\n+ pblend->obnd_mem_config2.WORD = dat_len;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer mem access timing configuration\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param req_hlen: memory access timing setting in H-SYNC cycles after V-SYNC.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_mem_access_line(osd_blend_reg_t *pblend, uint32_t req_hlen)\n+{\n+ pblend->obnd_sh.BF.obnd_layer_mem_req_cnt = req_hlen;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer force shadow control:\n+ * call this API before DSP2 streaming on to ensure the OSD layer \n+ * is activated even in frame 0.\n+ * After calling this API, this OSD blending layer has to be enabled.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_layer_early_commit(osd_blend_reg_t *pblend)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_mem_config0.WORD;\n+ /* disable this layer */\n+ val &= OSD_BLEND_OBND_LAYER_EN_UMSK;\n+ /* set OSD blend force shadow bit, so that the settings will be loaded\n+ * immediately and mem access will be started after layer is enabled.\n+ */\n+ val |= OSD_BLEND_OBND_FORCE_SH_MSK;\n+ pblend->obnd_mem_config0.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer enable/disable control\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: requested state of this blend layer.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_ctrl_layer(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_mem_config0.WORD;\n+ val &= OSD_BLEND_OBND_LAYER_EN_UMSK;\n+ val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_LAYER_EN_MSK : 0;\n+ pblend->obnd_mem_config0.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer color format configuration\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param fmt: color format.\n+ * @param order_alpha: order of the alpha.\n+ * @param order_r_v: order of the red(RGB) or v(YUV).\n+ * @param order_g_y: order of the green(RGB) or y(YUV).\n+ * @param order_b_u: order of the blue(RGB) or u(YUV).\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_set_color_format(osd_blend_reg_t *pblend, OSD_BLEND_COLOR_FMT_e fmt,\n+ OSD_BLEND_COLOR_ORDER_e order_alpha,\n+ OSD_BLEND_COLOR_ORDER_e order_r_v,\n+ OSD_BLEND_COLOR_ORDER_e order_g_y,\n+ OSD_BLEND_COLOR_ORDER_e order_b_u)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_layer_config0.WORD;\n+ val &= ~(OSD_BLEND_OBND_COLOR_FORMAT_MSK |\n+ OSD_BLEND_OBND_ORDER_A_MSK |\n+ OSD_BLEND_OBND_ORDER_RV_MSK |\n+ OSD_BLEND_OBND_ORDER_GY_MSK |\n+ OSD_BLEND_OBND_ORDER_BU_MSK);\n+\n+ val |= fmt << OSD_BLEND_OBND_COLOR_FORMAT_POS;\n+ val |= order_alpha << OSD_BLEND_OBND_ORDER_A_POS;\n+ val |= order_r_v << OSD_BLEND_OBND_ORDER_RV_POS;\n+ val |= order_g_y << OSD_BLEND_OBND_ORDER_GY_POS;\n+ val |= order_b_u << OSD_BLEND_OBND_ORDER_BU_POS;\n+\n+ pblend->obnd_layer_config0.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer global alpha configuration\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: enable or disable the global alpha for this layer.\n+ * @param alpha: value of the alpha.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_set_global_alpha(osd_blend_reg_t *pblend, uint32_t enable,\n+ uint8_t alpha)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_layer_config0.WORD;\n+ val &= OSD_BLEND_OBND_GLOBAL_A_UMSK;\n+ val &= OSD_BLEND_OBND_GLOBAL_A_EN_UMSK;\n+ val |= (alpha << OSD_BLEND_OBND_GLOBAL_A_POS) & OSD_BLEND_OBND_GLOBAL_A_MSK;\n+ val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_A_EN_MSK : 0;\n+ pblend->obnd_layer_config0.WORD = val;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer global color configuration\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: enable or disable the global color for this layer.\n+ * @param r_v: value of the red(RGB) or v(YUV).\n+ * @param g_y: value of the green(RGB) or y(YUV).\n+ * @param b_u: value of the blue(RGB) or u(YUV).\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_set_global_color(osd_blend_reg_t *pblend, uint32_t enable,\n+ uint8_t r_v, uint8_t g_y, uint8_t b_u)\n+{\n+ uint32_t val = 0;\n+\n+ val = (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_COLOR_EN_MSK : 0;\n+ val |= (r_v << OSD_BLEND_OBND_GLOBAL_RV_POS) & OSD_BLEND_OBND_GLOBAL_RV_MSK;\n+ val |= (g_y << OSD_BLEND_OBND_GLOBAL_GY_POS) & OSD_BLEND_OBND_GLOBAL_GY_MSK;\n+ val |= (b_u << OSD_BLEND_OBND_GLOBAL_BU_POS) & OSD_BLEND_OBND_GLOBAL_BU_MSK;\n+ pblend->obnd_layer_config1.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer update palette value according to the index.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param color: palette color, can be format ARGB8888 or AYUV8888.\n+ * @param index: the palette index for updating.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_update_palette(osd_blend_reg_t *pblend, uint32_t color, uint8_t index)\n+{\n+ uint32_t val = 0;\n+\n+ /* palette should be updated when blend is disabled. */\n+\n+ pblend->obnd_layer_config7.WORD = color;\n+ val = pblend->obnd_layer_config6.WORD;\n+ val &= OSD_BLEND_OBND_UPDATE_INDEX_UMSK;\n+ val |= index << OSD_BLEND_OBND_UPDATE_INDEX_POS;\n+\n+ /* trigger update */\n+ val |= OSD_BLEND_OBND_UPDATE_TRIGGER_MSK;\n+ pblend->obnd_layer_config6.WORD = val;\n+ arch_delay_us(1);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer palette keying control.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: enable or disable the palette keying for this layer.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_palette_keying_ctrl(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_layer_config2.WORD;\n+ val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK;\n+\n+ val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0;\n+\n+ pblend->obnd_layer_config2.WORD = val;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer palette keying configuration.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: enable or disable the palette keying for this layer.\n+ * @param mode: palette keying mode: within or out of the min/max range.\n+ * @param replace_index: the palette index that will be used as the replace color.\n+ * @param min_key_index: min index for the palette keying.\n+ * @param max_key_index: max index for the palette keying.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_palette_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable,\n+ OSB_BLEND_KEYING_MODE_e mode,\n+ uint8_t replace_index,\n+ uint8_t min_key_index, uint8_t max_key_index)\n+{\n+ uint32_t val = 0;\n+\n+ /* disable palette keying */\n+ val = pblend->obnd_layer_config2.WORD;\n+ val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK;\n+ pblend->obnd_layer_config2.WORD = val;\n+\n+ /* it is done if palette keying mode is disabled */\n+ if (OSD_BLEND_ST_ENABLE != enable) {\n+ return SUCCESS;\n+ }\n+\n+ val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0;\n+ val |= (OSB_BLEND_KEYING_INVERT == mode) ? OSD_BLEND_OBND_KEY_INDEX_INV_MSK : 0;\n+ val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK;\n+ val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK;\n+ val |= (replace_index << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS) &\n+ OSD_BLEND_OBND_KEY_REPLACE_INDEX_MSK;\n+\n+ pblend->obnd_layer_config2.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer palette keying min/max updating control.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param min_key_index: min index for the palette keying.\n+ * @param max_key_index: max index for the palette keying.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_palette_keying_update_range(osd_blend_reg_t *pblend,\n+ uint8_t min_key_index, uint8_t max_key_index)\n+{\n+ uint32_t val = 0;\n+\n+ val = pblend->obnd_layer_config2.WORD;\n+\n+ val &= OSD_BLEND_OBND_KEY_INDEX_MIN_UMSK;\n+ val &= OSD_BLEND_OBND_KEY_INDEX_MAX_UMSK;\n+ val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK;\n+ val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK;\n+\n+ pblend->obnd_layer_config2.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD blend layer color keying configuration.\n+ *\n+ * @param pblend: pointer to a specific OSD blend layer\n+ * @param enable: enable or disable the color keying for this layer.\n+ * @param pset: point to the color keying setting.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_blend_color_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable,\n+ osd_blend_color_keying_set_t *pset)\n+{\n+ uint32_t val = 0;\n+\n+ CHECK_PARAM(NULL != pset);\n+\n+ /* disable color keying */\n+ val = pblend->obnd_layer_config6.WORD;\n+ val &= OSD_BLEND_OBND_KEY_COLOR_EN_UMSK;\n+ pblend->obnd_layer_config6.WORD = val;\n+\n+ /* it is done if color keying mode is disabled */\n+ if (OSD_BLEND_ST_ENABLE != enable) {\n+ return SUCCESS;\n+ }\n+\n+ /* layer_config3: min & max for alpha and rv */\n+ val = pset->min_key_alpha << OSD_BLEND_OBND_KEY_A_MIN_POS;\n+ val |= pset->max_key_alpha << OSD_BLEND_OBND_KEY_A_MAX_POS;\n+ val |= pset->min_key_rv << OSD_BLEND_OBND_KEY_RV_MIN_POS;\n+ val |= pset->max_key_rv << OSD_BLEND_OBND_KEY_RV_MAX_POS;\n+ pblend->obnd_layer_config3.WORD = val;\n+\n+ /* layer_config4: min & max for gy and bu */\n+ val = pset->min_key_gy << OSD_BLEND_OBND_KEY_GY_MIN_POS;\n+ val |= pset->max_key_gy << OSD_BLEND_OBND_KEY_GY_MAX_POS;\n+ val |= pset->min_key_bu << OSD_BLEND_OBND_KEY_BU_MIN_POS;\n+ val |= pset->max_key_bu << OSD_BLEND_OBND_KEY_BU_MAX_POS;\n+ pblend->obnd_layer_config4.WORD = val;\n+\n+ /* layer_config5: replace color */\n+ val = pset->replace_alpha << OSD_BLEND_OBND_KEY_REPLACE_A_POS;\n+ val |= pset->replace_rv << OSD_BLEND_OBND_KEY_REPLACE_RV_POS;\n+ val |= pset->replace_gy << OSD_BLEND_OBND_KEY_REPLACE_GY_POS;\n+ val |= pset->replace_bu << OSD_BLEND_OBND_KEY_REPLACE_BU_POS;\n+ pblend->obnd_layer_config5.WORD = val;\n+\n+ /* color range inverted? */\n+ val = pblend->obnd_layer_config6.WORD;\n+ val &= ~(OSD_BLEND_OBND_KEY_A_INV_MSK |\n+ OSD_BLEND_OBND_KEY_RV_INV_MSK |\n+ OSD_BLEND_OBND_KEY_GY_INV_MSK |\n+ OSD_BLEND_OBND_KEY_BU_INV_MSK);\n+ val |= (OSB_BLEND_KEYING_INVERT == pset->mode_alpha) ?\n+ OSD_BLEND_OBND_KEY_A_INV_MSK :\n+ 0;\n+ val |= (OSB_BLEND_KEYING_INVERT == pset->mode_rv) ?\n+ OSD_BLEND_OBND_KEY_RV_INV_MSK :\n+ 0;\n+ val |= (OSB_BLEND_KEYING_INVERT == pset->mode_gy) ?\n+ OSD_BLEND_OBND_KEY_GY_INV_MSK :\n+ 0;\n+ val |= (OSB_BLEND_KEYING_INVERT == pset->mode_bu) ?\n+ OSD_BLEND_OBND_KEY_BU_INV_MSK :\n+ 0;\n+\n+ /* enable color keying */\n+ val |= OSD_BLEND_OBND_KEY_COLOR_EN_MSK;\n+ pblend->obnd_layer_config6.WORD = val;\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group OSD_BLEND_Public_Functions */\n+\n+/*@} end of group OSD_BLEND */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9e0e42c9691380e6b362f6e6b198ee4b78f68534\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c\n@@ -0,0 +1,335 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_osd_blend.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2021 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_osd_draw.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup OSD_DRAW\n+ * @{\n+ */\n+\n+/** @defgroup OSD_DRAW_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Private_Macros */\n+\n+/** @defgroup OSD_DRAW_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Private_Types */\n+\n+/** @defgroup OSD_DRAW_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Private_Variables */\n+\n+/** @defgroup OSD_DRAW_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Global_Variables */\n+\n+/** @defgroup OSD_DRAW_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Private_Fun_Declaration */\n+\n+/** @defgroup OSD_DRAW_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group OSD_DRAW_Private_Functions */\n+\n+/** @defgroup OSD_DRAW_Public_Functions\n+ * @{\n+ */\n+\n+/******************************************************************************\n+ * @brief OSD draw layer state control\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param layer: draw layer.\n+ * @param state: enable or disable the layer in this draw HW IP.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_set_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer);\n+\n+ tmpval = odraw->osd_draw_config.WORD;\n+\n+ if (state == OSD_RECT_STATE_ENABLE) {\n+ tmpval |= layer_mask;\n+ } else {\n+ tmpval &= ~layer_mask;\n+ }\n+\n+ odraw->osd_draw_config.WORD = tmpval;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD draw layer state get\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param layer: draw layer.\n+ * @param state: pointer to return the state value.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_get_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type *state)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer);\n+\n+ CHECK_PARAM(NULL != odraw);\n+ CHECK_PARAM(NULL != state);\n+\n+ tmpval = odraw->osd_draw_config.WORD;\n+ tmpval &= layer_mask;\n+ *state = (!!tmpval) ? OSD_RECT_STATE_ENABLE : OSD_RECT_STATE_DISABLE;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD draw layer style set\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param layer: draw layer.\n+ * @param style: solid or hollow style.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_set_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type style)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer);\n+\n+ if (style == OSD_RECT_STYLE_SOLID) {\n+ tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS;\n+ } else {\n+ tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS);\n+ }\n+\n+ odraw->osd_draw_config.WORD = tmpval;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD draw layer style get\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param layer: draw layer.\n+ * @param style: pointer to return the solid or hollow style.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_get_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type *style)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer);\n+\n+ CHECK_PARAM(NULL != odraw);\n+ CHECK_PARAM(NULL != style);\n+\n+ tmpval = odraw->osd_draw_config.WORD;\n+ tmpval &= layer_mask << OSD_REG_DRAW_TYPE_L_POS;\n+ *style = (!!tmpval) ? OSD_RECT_STYLE_SOLID : OSD_RECT_STYLE_HOLLOW;\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD draw layer control\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param layer: draw layer.\n+ * @param state: enable or disable this draw layer.\n+ * @param style: solid or hollow style for this layer.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_config_rect_layer(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state, OSD_RECT_STYLE_Type style)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer);\n+\n+ tmpval = odraw->osd_draw_config.WORD;\n+\n+ if (state == OSD_RECT_STATE_ENABLE) {\n+ tmpval |= layer_mask;\n+ } else {\n+ tmpval &= ~layer_mask;\n+ }\n+\n+ if (style == OSD_RECT_STYLE_SOLID) {\n+ tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS;\n+ } else {\n+ tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS);\n+ }\n+\n+ odraw->osd_draw_config.WORD = tmpval;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief Draw a specific rectangle with OSD draw HW IP.\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param rect: pointer to a rectangle setting structure.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_rectangle(osd_draw_reg_t *odraw, osd_rectangle_t *rect)\n+{\n+ osd_rectangle_desc_t *desc = OSD_RECT_DESC((odraw), OSD_VALID_LAYER(rect->layer));\n+\n+ CHECK_PARAM(NULL != odraw);\n+ CHECK_PARAM(NULL != rect);\n+\n+ osd_draw_set_layer_state(odraw, rect->layer, OSD_RECT_STATE_DISABLE);\n+ desc->attr = rect->desc.attr;\n+\n+ /* EVEN and ODD */\n+ rect->desc.pos.x.start &= -2;\n+ rect->desc.pos.x.end |= 1;\n+ rect->desc.pos.y.start &= -2;\n+ rect->desc.pos.y.end |= 1;\n+ rect->desc.attr.yuvt.thinkness += (rect->desc.attr.yuvt.thinkness & 1) ? 1 : 0;\n+\n+ desc->pos.x = rect->desc.pos.x;\n+ desc->pos.y = rect->desc.pos.y;\n+ osd_draw_config_rect_layer(odraw, rect->layer, OSD_RECT_STATE_ENABLE, rect->style);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief Draw a specific rectangle with OSD draw HW IP on the top if possible.\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ * @param rect: pointer to a rectangle setting structure.\n+ * @param layer: pointer to return the current drawing layer.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_rectangle_onTop(osd_draw_reg_t *odraw, osd_rectangle_t *rect, uint32_t *layer)\n+{\n+ uint32_t tmpval = 0;\n+ uint32_t draw_layer = 0;\n+\n+ CHECK_PARAM(NULL != layer);\n+ CHECK_PARAM(NULL != rect);\n+\n+ tmpval = odraw->osd_draw_config.WORD;\n+ tmpval &= 0x0000FFFF;\n+\n+ tmpval = __CLZ(tmpval);\n+\n+ if (OSD_MAX_LAYER == tmpval) {\n+ /* no available TOP layer since all layers used */\n+ *layer = (uint32_t)-1;\n+ return NORESC;\n+ }\n+\n+ draw_layer = sizeof(uintptr_t) * 8 - tmpval;\n+\n+ rect->layer = draw_layer;\n+ *layer = draw_layer;\n+ osd_draw_rectangle(odraw, rect);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief Init the OSD draw HW IP.\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_init(osd_draw_reg_t *odraw)\n+{\n+ odraw->osd_draw_config.WORD = 0;\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief DeInit the OSD draw HW IP.\n+ *\n+ * @param odraw: pointer to a specific OSD draw HW IP.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_draw_deinit(osd_draw_reg_t *odraw)\n+{\n+ odraw->osd_draw_config.WORD = 0;\n+ return SUCCESS;\n+}\n+\n+/*@} end of group OSD_DRAW_Public_Functions */\n+\n+/*@} end of group OSD_DRAW */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ecf59a9814fbc504c8b417b3193c74f6ec985bfa\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c\n@@ -0,0 +1,245 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_osd_probe.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2021 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_osd_probe.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup OSD_PROBE\n+ * @{\n+ */\n+\n+/** @defgroup OSD_PROBE_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Private_Macros */\n+\n+/** @defgroup OSD_PROBE_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Private_Types */\n+\n+/** @defgroup OSD_PROBE_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Private_Variables */\n+\n+/** @defgroup OSD_PROBE_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Global_Variables */\n+\n+/** @defgroup OSD_PROBE_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Private_Fun_Declaration */\n+\n+/** @defgroup OSD_PROBE_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group OSD_PROBE_Private_Functions */\n+\n+/** @defgroup OSD_PROBE_Public_Functions\n+ * @{\n+ */\n+\n+/******************************************************************************\n+ * @brief OSD probe setup one detect point\n+ *\n+ * @param index: point index in probe.\n+ * @param x: point x-axis.\n+ * @param y: point y-axis.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_set_addr(uintptr_t index, uintptr_t x, uintptr_t y)\n+{\n+ uint32_t addr = 0;\n+\n+ addr = ((y << OSD_PB_REG_OSD_PB_Y_00_POS) & OSD_PB_REG_OSD_PB_Y_00_MSK) | (x & OSD_PB_REG_OSD_PB_X_00_MSK);\n+\n+ if (index < OSD_PROBE_ADDR_MAX_INDEX) {\n+ BL_WR_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t), addr);\n+ return SUCCESS;\n+ } else {\n+ return INVALID;\n+ }\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe get info of one detect point\n+ *\n+ * @param index: point index in probe.\n+ * @param x: return the value of point x-axis.\n+ * @param y: return the value of point y-axis.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_get_addr(uintptr_t index, uintptr_t *x, uintptr_t *y)\n+{\n+ uint32_t addr = 0;\n+ BL_Err_Type err = INVALID;\n+\n+ CHECK_PARAM(NULL != x);\n+ CHECK_PARAM(NULL != y);\n+\n+ if (index < OSD_PROBE_ADDR_MAX_INDEX) {\n+ addr = BL_RD_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t));\n+ *x = addr & OSD_PB_REG_OSD_PB_X_00_MSK;\n+ *y = (addr & OSD_PB_REG_OSD_PB_Y_00_MSK) >> OSD_PB_REG_OSD_PB_Y_00_POS;\n+ err = SUCCESS;\n+ }\n+\n+ return err;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe get result count info\n+ *\n+ * @param cnt: return the count info of the probe result.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_get_count(uintptr_t *cnt)\n+{\n+ CHECK_PARAM(NULL != cnt);\n+\n+ *cnt = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_W_CNT_R);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe get result\n+ *\n+ * @param res: return the probe result.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_get_result(uintptr_t *res)\n+{\n+ uint32_t ctrl = 0;\n+\n+ CHECK_PARAM(NULL != res);\n+\n+ ctrl = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_IDX_R);\n+\n+ *res = ctrl ? BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT0) : BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT1);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe get ctrl reg\n+ *\n+ * @param ctrl: return the value of the ctrl reg.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_get_ctrl(uintptr_t *ctrl)\n+{\n+ CHECK_PARAM(NULL != ctrl);\n+\n+ *ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe set Y channel threshold.\n+ *\n+ * @param luma: value of the Y threshold.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_set_threshold(uintptr_t luma)\n+{\n+ uint32_t ctrl = 0;\n+\n+ ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG);\n+ ctrl &= ~OSD_PB_REG_OSD_PB_LUMA_TH_MSK;\n+ ctrl |= (luma & OSD_PB_REG_OSD_PB_LUMA_TH_MSK);\n+ BL_WR_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG, ctrl);\n+\n+ return SUCCESS;\n+}\n+\n+/******************************************************************************\n+ * @brief OSD probe get Y channel threshold.\n+ *\n+ * @param luma: return value of the Y threshold in reg.\n+ *\n+ * @return Result of the operation.\n+ *\n+*******************************************************************************/\n+\n+BL_Err_Type osd_probe_get_threshold(uintptr_t *luma)\n+{\n+ uint32_t ctrl = 0;\n+\n+ CHECK_PARAM(NULL != luma);\n+\n+ ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG);\n+ *luma = ctrl & OSD_PB_REG_OSD_PB_LUMA_TH_MSK;\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group OSD_PROBE_Public_Functions */\n+\n+/*@} end of group OSD_PROBE */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4a8f3d859207d5589618b9810672c041689fa1af\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c\n@@ -0,0 +1,1058 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_pds.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"bl808_pds.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PDS\n+ * @{\n+ */\n+\n+/** @defgroup PDS_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group PDS_Private_Macros */\n+\n+/** @defgroup PDS_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group PDS_Private_Types */\n+\n+/** @defgroup PDS_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX] = { NULL };\n+#endif\n+\n+/*@} end of group PDS_Private_Variables */\n+\n+/** @defgroup PDS_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PDS_Global_Variables */\n+\n+/** @defgroup PDS_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group PDS_Private_Fun_Declaration */\n+\n+/** @defgroup PDS_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group PDS_Private_Functions */\n+\n+/** @defgroup PDS_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief set gpio pad pull type in pds\n+ *\n+ * @param pad: gpio type\n+ * @param pu: power up\n+ * @param pd: power down\n+ * @param ie: Active IE (interrupt)\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpValPu;\n+ uint32_t tmpValPd;\n+ uint32_t tmpValIe;\n+ uint32_t pos;\n+\n+ CHECK_PARAM(IS_GLB_GPIO_TYPE(pad));\n+\n+ /* [0] : GPIO0~8 */\n+ /* [1] : GPIO16~23 */\n+ /* [2] : GPIO24~38 */\n+ if (pad <= GLB_GPIO_PIN_8) {\n+ pos = 0;\n+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_23)) {\n+ pos = 1;\n+ } else if ((pad >= GLB_GPIO_PIN_24) && (pad <= GLB_GPIO_PIN_38)) {\n+ pos = 2;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ /* pu/pd/ie config */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);\n+ tmpValPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET);\n+ if (pu) {\n+ tmpValPu |= (1 << pos);\n+ } else {\n+ tmpValPu &= ~(1 << pos);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET, tmpValPu);\n+ tmpValPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET);\n+ if (pd) {\n+ tmpValPd |= (1 << pos);\n+ } else {\n+ tmpValPd &= ~(1 << pos);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET, tmpValPd);\n+ tmpValIe = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET);\n+ if (ie) {\n+ tmpValIe |= (1 << pos);\n+ } else {\n+ tmpValIe &= ~(1 << pos);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET, tmpValIe);\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set gpio pad int mask type in pds\n+ *\n+ * @param pad: gpio type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t pos = 0;\n+\n+ /* [8:0] : GPIO0~8 */\n+ /* [31:9] : GPIO16~38 */\n+ if (pad <= GLB_GPIO_PIN_8) {\n+ pos = pad;\n+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_38)) {\n+ pos = pad - 7;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET);\n+ if (UNMASK != intMask) {\n+ /* MASK */\n+ tmpVal |= (1 << pos);\n+ } else {\n+ /* UNMASK */\n+ tmpVal &= ~(1 << pos);\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_PD_SET, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set gpio pad trig type in pds\n+ *\n+ * @param set: set type\n+ * @param trig: trig type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));\n+ CHECK_PARAM(IS_PDS_GPIO_INT_TRIG_TYPE(trig));\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);\n+ switch (set) {\n+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET1_INT_MODE, trig);\n+ break;\n+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET2_INT_MODE, trig);\n+ break;\n+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET3_INT_MODE, trig);\n+ break;\n+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET4_INT_MODE, trig);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set gpio pad int clear in pds\n+ *\n+ * @param set: set type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));\n+\n+ /* pds_gpio_setx_int_clr = 0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);\n+ switch (set) {\n+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);\n+\n+ /* pds_gpio_setx_int_clr = 1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);\n+ switch (set) {\n+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);\n+\n+ /* pds_gpio_setx_int_clr = 0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);\n+ switch (set) {\n+ case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_3_GPIO23_GPIO30:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);\n+ break;\n+ case PDS_GPIO_INT_SET_4_GPIO31_GPIO38:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get gpio pad int status\n+ *\n+ * @param pad: gpio type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad)\n+{\n+ uint32_t pos = 0;\n+\n+ /* [8:0] : GPIO0~8 */\n+ /* [31:9] : GPIO16~38 */\n+ if (pad <= GLB_GPIO_PIN_8) {\n+ pos = pad;\n+ } else if ((pad >= GLB_GPIO_PIN_16) && (pad <= GLB_GPIO_PIN_38)) {\n+ pos = pad - 7;\n+ } else {\n+ return RESET;\n+ }\n+\n+ return (BL_RD_REG(PDS_BASE, PDS_GPIO_STAT) & (1 << pos)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash pad pull none\n+ *\n+ * @param pinCfg: flash pin type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg)\n+{\n+ switch (pinCfg) {\n+ case SF_IO_EXT_SF2:\n+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_34, 0, 0, 0);\n+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_35, 0, 0, 0);\n+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_36, 0, 0, 0);\n+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_37, 0, 0, 0);\n+ PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_PIN_38, 0, 0, 0);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set flash pad pull none\n+ *\n+ * @param pinCfg: flash pin type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ switch (pinCfg) {\n+ case SF_IO_EXT_SF2:\n+ /* pu/pd/ie config */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);\n+ /* GPIO24~38 [8][5][2] = 0 */\n+ tmpVal &= ~(0x124);\n+ BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MCU0 clock enable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MCU0 clock disable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set MCU0 reset address\n+ *\n+ * @param addr: address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Reset_Address(uint32_t addr)\n+{\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief enable LP clock\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Clock_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief disable LP clock\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Clock_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set LP clock divider\n+ *\n+ * @param div: divider\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_System_CLK_Div(uint8_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, 1);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, div);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set LP clock\n+ *\n+ * @param clkFreq: clock type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Set_LP_System_CLK(PDS_LP_SYS_CLK_Type clkFreq)\n+{\n+ CHECK_PARAM(IS_PDS_LP_SYS_CLK_TYPE(clkFreq));\n+\n+ /* do nothing */\n+ (void)clkFreq;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reset LP rtc\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Reset_LP_RTC(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* lp rtc_rst=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ /* lp rtc_rst=1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_RST);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ /* lp rtc_rst=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set LP rtc clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param div: clock div\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_RTC_CLK(uint8_t enable, uint16_t div)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((div <= 0x3FF));\n+\n+ /* lp rtc_en=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ /* lp rtc_div=div */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_E902_RTC_DIV, div);\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ /* lp rtc_en=0/1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG8);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN);\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG8, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set LP reset address\n+ *\n+ * @param addr: address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_LP_Reset_Address(uint32_t addr)\n+{\n+ BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get mm system power state\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type ATTR_CLOCK_SECTION PDS_Get_MM_System_Power_On_State(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t pwrOff = 0;\n+ uint32_t isoEn = 0;\n+ uint32_t gateClk = 0;\n+ uint32_t memStby = 0;\n+ uint32_t pdsRst = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ pwrOff = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PWR_OFF);\n+ isoEn = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_ISO_EN);\n+ gateClk = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_GATE_CLK);\n+ memStby = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_MEM_STBY);\n+ pdsRst = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_FORCE_MM_PDS_RST);\n+\n+ if (pwrOff || isoEn || gateClk || memStby || pdsRst) {\n+ /* mm system power off */\n+ return RESET;\n+ }\n+\n+ /* mm system power on */\n+ return SET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power on mm system\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_MM_System(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* mm_pwr_off=0, [1]=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_PWR_OFF);\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);\n+\n+ /* wait > 30us */\n+ arch_delay_us(45);\n+\n+ /* mm_iso_en=0, [5]=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_ISO_EN);\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);\n+\n+ /* mm_gate_clk=0, [17]=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_GATE_CLK);\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);\n+\n+ /* mm_stby=0, [13]=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_MEM_STBY);\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);\n+\n+ /* mm_reset=0, [9]=0 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_FORCE_MM_PDS_RST);\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable power down sleep\n+ *\n+ * @param cfg: power down sleep configuration 1\n+ * @param cfg4: power down sleep configuration 2\n+ * @param pdsSleepCnt: power down sleep count cycle\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)\n+{\n+ uint32_t tmpVal = 0;\n+ /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */\n+ /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */\n+ if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {\n+ return ERROR;\n+ } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {\n+ BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);\n+ } else {\n+ /* PDS sleep time 0 ,means mask pds_timer wakeup */\n+ }\n+\n+ /* PDS_CTL4 config */\n+ BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);\n+\n+ /* PDS_CTL config */\n+ if (cfg->pdsStart) {\n+ /* clear pds int */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));\n+ BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));\n+ } else {\n+ BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power down sleep force configure\n+ *\n+ * @param cfg2: power down sleep force configuration 1\n+ * @param cfg3: power down sleep force configuration 2\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5)\n+{\n+ /* PDS_CTL2 config */\n+ BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);\n+\n+ /* PDS_CTL3 config */\n+ BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);\n+\n+ /* PDS_CTL5 config */\n+ BL_WR_REG(PDS_BASE, PDS_CTL5, *(uint32_t *)cfg5);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power down sleep ram configure\n+ *\n+ * @param ocramCfg: power down sleep force ocram configuration\n+ * @param wramCfg: power down sleep force wram configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg)\n+{\n+ if ((NULL == ram1Cfg) || (NULL == ram2Cfg)) {\n+ return ERROR;\n+ }\n+\n+ BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ram1Cfg);\n+ BL_WR_REG(PDS_BASE, PDS_RAM2, *(uint32_t *)ram2Cfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power down sleep force configure\n+ *\n+ * @param defaultLvCfg: power down sleep default level configuration\n+ * @param ramCfg: ram configuration\n+ * @param pdsSleepCnt: power down sleep time count\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,\n+ PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg,\n+ uint32_t pdsSleepCnt)\n+{\n+ /* RAM config need fix after ECO */\n+ PDS_RAM_Config(ram1Cfg, ram2Cfg);\n+ PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3), (PDS_CTL5_Type *)&(defaultLvCfg->pdsCtl5));\n+ PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief power down sleep int mask\n+ *\n+ * @param intType: PDS int type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ if (intMask != UNMASK) {\n+ tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET));\n+ } else {\n+ tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET));\n+ }\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get power down sleep int status\n+ *\n+ * @param intType: PDS int type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)\n+{\n+ return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear power down sleep int status\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION PDS_IntClear(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);\n+ BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install PDS interrupt callback function\n+ *\n+ * @param intType: PDS int type\n+ * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)\n+{\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);\n+#endif\n+\n+ pdsIntCbfArra[intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Trim RC32M\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)\n+{\n+ Efuse_Ana_RC32M_Trim_Type trim;\n+ int32_t tmpVal = 0;\n+\n+ EF_Ctrl_Read_RC32M_Trim(&trim);\n+ if (trim.trimRc32mExtCodeEn) {\n+ if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);\n+ BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);\n+ arch_delay_us(2);\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PDS turn on USB\n+ *\n+ * @param waitReady : wait turn on usb finish\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */\n+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */\n+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */\n+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */\n+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */\n+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */\n+ /* #1.2ms; wait UCLK */\n+ /* wait(soc616_b0.usb_uclk); */\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ /* greater than 5T */\n+ arch_delay_us(1);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ /* greater than 5T */\n+ arch_delay_us(1);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ /* wait UCLK 1.2ms */\n+ arch_delay_ms(3);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ if (waitReady) {\n+ arch_delay_ms(2);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PDS turn off USB\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Turn_Off_USB(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */\n+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */\n+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */\n+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */\n+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */\n+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */\n+ /* #1.2ms; wait UCLK */\n+ /* wait(soc616_b0.usb_uclk); */\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB phy suspend\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Set_USB_Suspend(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB phy resume\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Set_USB_Resume(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power down sleep wake up interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void PDS_WAKEUP_IRQHandler(void)\n+{\n+ for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {\n+ if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType] != NULL)) {\n+ pdsIntCbfArra[intType]();\n+ }\n+ }\n+\n+ PDS_IntClear();\n+}\n+#endif\n+\n+/*@} end of group PDS_Public_Functions */\n+\n+/*@} end of group PDS */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8d693866393a26bf9f2121f2ebc144ef1c89109e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c\n@@ -0,0 +1,537 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808p_psram_ctrl.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#include \"bl808_glb.h\"\n+#include \"bl808_psram.h\"\n+#include \"psram_reg.h\"\n+\n+/** @addtogroup BL808P_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PSRAM_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_CTRL_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Private_Macros */\n+\n+/** @defgroup PSRAM_CTRL_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Private_Types */\n+\n+/** @defgroup PSRAM_CTRL_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Private_Variables */\n+\n+/** @defgroup PSRAM_CTRL_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Global_Variables */\n+\n+/** @defgroup PSRAM_CTRL_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Private_Fun_Declaration */\n+\n+/** @defgroup PSRAM_CTRL_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_CTRL_Private_Functions */\n+\n+/** @defgroup PSRAM_CTRL_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Init PSRAM controller\n+ *\n+ * @param PSRAM_ID: PSRAM vendor\n+ * @param psramCtrlCfg: PSRAM controller IO type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg)\n+{\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+ CHECK_PARAM(IS_PSRAM_CTRL_CFG_TYPE(psramCtrlCfg));\n+\n+ //PSRAM initial sequence\n+ arch_delay_us(150);\n+ /* set psram ctrl x8 */\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SEL_PSRAM0_X16, 0x0);\n+ BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);\n+\n+ /* set psram dqs delay 0xfff0 */\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ROUGH_SEL_I_DQS0, 0xfff0);\n+ BL_WR_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5, tmpVal);\n+\n+ /* Set vendor and mode for psram controller */\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ //\ttmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_PCK_S_DIV, 0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_VENDOR_SEL, psramCtrlCfg->vendor);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_X16_MODE, psramCtrlCfg->ioMode);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ADDR_MASK, psramCtrlCfg->size);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_DQS_REL_VAL, 0x1f);\n+ BL_WR_REG(psram_base, PSRAM_MANUAL_CONTROL2, tmpVal);\n+\n+ if (psramCtrlCfg->vendor == PSRAM_CTRL_VENDOR_WINBOND && psramCtrlCfg->ioMode == PSRAM_CTRL_X16_MODE && psramCtrlCfg->size == PSRAM_SIZE_16MB) {\n+ //If using W957D6NKR, must set reg_wb_hyper3 bit to 1\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_HYPER3);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PSRAM Ctrl request access\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ //start configure request\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_REQ, 1);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //Waiting for the authorization\n+ do {\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_REG_CONFIG_GNT));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PSRAM Ctrl release access\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void PSram_Ctrl_Release(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ //clear start configure request\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_REQ, 0);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read register for winbond PSRAM\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param reg_addr: PSRAM Register ID CR0 or CR1\n+ * @param regVal: read Reister value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));\n+ CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ PSram_Ctrl_Request(PSRAM_ID);\n+\n+ //configure pSRAM register,select reg_addr CR0 or CR1\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //start psram configure\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_R_PUSLE, 1);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //waiting confiure complete\n+ do {\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));\n+\n+ //read reg data form sts_config_read\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL);\n+ *regVal = (uint16_t)(tmpVal >> 16);\n+\n+ PSram_Ctrl_Release(PSRAM_ID);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief write register for winbond PSRAM\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param reg_addr: PSRAM Register ID CR0 or CR1\n+ * @param reg_cfg: winbond configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+ PSRAM_Ctrl_Size_Type psramDensity;\n+\n+ CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));\n+ CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ PSram_Ctrl_Request(PSRAM_ID);\n+\n+ //configure Winbond register\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_LATENCY, reg_cfg->latency);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_DRIVE_ST, reg_cfg->driveStrength);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_HYBRID_EN, reg_cfg->brustType);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_BURST_LENGTH, reg_cfg->brustLen);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_FIX_LATENCY, reg_cfg->fixedLatency);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_DPD_DIS, reg_cfg->disDeepPowerDownMode);\n+\n+ psramDensity = BL_GET_REG_BITS_VAL(BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL2), PSRAM_REG_ADDR_MASK);\n+\n+ if (psramDensity == PSRAM_SIZE_4MB) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_PASR, reg_cfg->PASR);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_PASR, reg_cfg->PASR << 2);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_HYBRID_SLP, reg_cfg->hybridSleepMode);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_IPD, reg_cfg->inputPowerDownMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_MCLK_TYPE, reg_cfg->clockType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_LINEAR_DIS, reg_cfg->linear_dis);\n+ /* W955D8MKY don't support sw rst */\n+ /* tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_SW_RST, reg_cfg->rst); */\n+\n+ BL_WR_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE, tmpVal);\n+\n+ //configure pSRAM register,select reg_addr CR0 or CR1\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //start psram configure\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_W_PUSLE, 1);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //waiting confiure complete\n+ do {\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));\n+\n+ PSram_Ctrl_Release(PSRAM_ID);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read register for APmemory PSRAM\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param reg_addr: PSRAM Register ID CR0 or CR1\n+ * @param regVal: read Reister value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));\n+ CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ PSram_Ctrl_Request(PSRAM_ID);\n+\n+ //configure pSRAM register,select reg_addr CR0 or CR1\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //start psram configure\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_R_PUSLE, 1);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //waiting confiure complete\n+ do {\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));\n+\n+ //read reg data form sts_config_read\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL);\n+ *regVal = (uint16_t)(tmpVal >> 16);\n+\n+ PSram_Ctrl_Release(PSRAM_ID);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief write register for Apmemory PSRAM\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param reg_addr: PSRAM Register ID\n+ * @param reg_cfg: winbond configuration\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));\n+ CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ PSram_Ctrl_Request(PSRAM_ID);\n+\n+ //configure Winbond register\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_R_LATENCY_TYPE, reg_cfg->fixedLatency);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_R_LATENCY_CODE, reg_cfg->readLatency);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_RF, reg_cfg->refreshFreq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_DRIVE_ST, reg_cfg->driveStrength);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_W_LATENCY_CODE, reg_cfg->writeLatency);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_PASR, reg_cfg->PASR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_SLEEP, reg_cfg->halfSleepModeEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_DPD, reg_cfg->deepPowerDownModeEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_RBX, reg_cfg->crossBoundaryEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_BURST_TYPE, reg_cfg->brustType);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_BURST_LENGTH, reg_cfg->brustLen);\n+\n+ BL_WR_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE, tmpVal);\n+\n+ //configure pSRAM register,select reg_addr CR0 or CR1\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //start psram configure\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_W_PUSLE, 1);\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+\n+ //waiting confiure complete\n+ do {\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));\n+\n+ PSram_Ctrl_Release(PSRAM_ID);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief write register for apmemory PSRAM\n+ *\n+ * @param PSRAM_ID: apmemory configuration register type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_GLB_RESET_PULSE);\n+ BL_WR_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief write register for Winbond PSRAM\n+ *\n+ * @param PSRAM_ID: Winbond configuration register type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_SW_RST);\n+ BL_WR_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set clk type diff/single\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param clkSel: Clock Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);\n+\n+ if (clkSel == PSRAM_CLOCK_DIFF) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE);\n+ }\n+\n+ BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get timeout status\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ *\n+ * @return FLAG\n+ *\n+*******************************************************************************/\n+uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);\n+\n+ return BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_TIMEOUT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PSram_Ctrl_Clear_Timout_Flag\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR);\n+ BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR);\n+ BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set clk type diff/single\n+ *\n+ * @param PSRAM_ID: PSRAM ID\n+ * @param enable: Enable or not\n+ * @param timeoutThr: timeoutThr\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);\n+\n+ CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));\n+\n+ tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_EN);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_TIMEOUT_CNT, timeoutThr);\n+\n+ BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);\n+}\n+\n+/*@} end of group PSRAM_CTRL_Public_Functions */\n+\n+/*@} end of group PSRAM_CTRL */\n+\n+/*@} end of group BL808P_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..838c9b8565dcb163ddef5d99948da815dac2ee95\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c\n@@ -0,0 +1,827 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_psram_uhs.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_psram_uhs.h\"\n+#include \"bl808_common.h\"\n+#include \"bl808_glb.h\"\n+#include \"psram_uhs_reg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PSRAM_UHS\n+ * @{\n+ */\n+\n+/** @defgroup PSRAM_UHS_Private_Macros\n+ * @{\n+ */\n+#define PSRAM_UHS_RW_TIMEOUT 0xffffffff\n+/*@} end of group PSRAM_UHS_Private_Macros */\n+\n+/** @defgroup PSRAM_UHS_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Private_Types */\n+\n+/** @defgroup PSRAM_UHS_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Private_Variables */\n+\n+/** @defgroup PSRAM_UHS_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Global_Variables */\n+\n+/** @defgroup PSRAM_UHS_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Private_Fun_Declaration */\n+\n+/** @defgroup PSRAM_UHS_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group PSRAM_UHS_Private_Functions */\n+\n+/** @defgroup PSRAM_UHS_Public_Functions\n+ * @{\n+ */\n+int config_uhs_phy(uint32_t datarate)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (datarate > 1866) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA0A1323);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0b030404);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x050e0419);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x0a6a1c1c);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0711070e);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ } else if (datarate > 1600) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA283203);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x091e1818);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0710070d);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 3);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ } else if (datarate > 1066) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA270212);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x09020303);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040c0313);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x07d11515);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x060f060c);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ } else if (datarate > 800) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA270212);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x06010202);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0309020d);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x05360e0e);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x050c0509);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ } else if (datarate > 666) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA041020);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0208010a);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03e90b0b);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ } else if (datarate > 400) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA130010);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02080108);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03420909);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ } else {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA020010);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x04000101);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02070106);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x01f50606);\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040a0407);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ }\n+ return 0;\n+}\n+\n+static void power_up_ldo12uhs(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);\n+\n+#ifdef BL808D_REWORK\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN_SEL, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 0);\n+#else\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 1);\n+ BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);\n+ arch_delay_us(300);\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 6);\n+#endif\n+ BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);\n+ arch_delay_us(1);\n+}\n+\n+static void set_cen_ck_ckn(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ arch_delay_us(1);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);\n+ tmpVal &= 0xFFFCFFFF;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);\n+ arch_delay_us(1);\n+}\n+\n+static int set_or_uhs(uint32_t datarate)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t *uhs_phy_cfg_base_addr = (uint32_t *)(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_00_OFFSET);\n+ // clang-format off\n+ const static uint32_t uhs_phy_cfg_data[] ={\n+ 0x802b0200, 0x60206020, 0x70027002, 0x70027002,\n+ 0x70027002, 0x70027002, 0x70027002, 0x70027002,\n+ 0x70027002, 0x70027002, 0x26000000, 0x26000006,\n+ };\n+ // clang-format on\n+\n+ for (uint32_t i = 0; i < 12; i++) {\n+ uhs_phy_cfg_base_addr[i] = uhs_phy_cfg_data[i];\n+ }\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30);\n+ tmpVal &= 0x08ffffff;\n+ tmpVal |= 0x07000000;\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48);\n+ tmpVal &= 0xfffffcff;\n+ tmpVal |= 0x00000200;\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C);\n+ tmpVal &= 0xffe0ffff;\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal &= 0xff88ff88;\n+ tmpVal |= 0x00330033;\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ arch_delay_us(1);\n+\n+ return 0;\n+}\n+static void switch_to_ldo12uhs(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);\n+ tmpVal &= 0xFFCFFFFF;\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);\n+ arch_delay_us(1);\n+}\n+\n+static void release_cen_ck_ckn(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);\n+ tmpVal &= 0xFFFCFEFF;\n+#ifdef BL808D_REWORK\n+ tmpVal |= 0x10000;\n+#else\n+ tmpVal |= 0x30000;\n+#endif\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);\n+ arch_delay_us(1);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 3);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+ arch_delay_us(1);\n+}\n+\n+static void Psram_analog_init(uint32_t pck_freq)\n+{\n+ /* power on ldo12 */\n+ power_up_ldo12uhs();\n+\n+ /* set cen ck ckn */\n+ set_cen_ck_ckn();\n+\n+ /*\n+ * overwrite default register content\n+ * only support 2000M and 1500MHZ\n+ */\n+ set_or_uhs(pck_freq);\n+\n+ /* switch to ldo12 */\n+ switch_to_ldo12uhs();\n+\n+ /* release cen ck */\n+ release_cen_ck_ckn();\n+\n+ /* config phy paramater */\n+ config_uhs_phy(pck_freq);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Init Psram UHS ,set auto refresh cycle\n+ *\n+ * @param cfg: pck frequency unit is MHZ\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_PSRAM_UHS_MEM_SIZE_TYPE(cfg->psramMemSize));\n+ CHECK_PARAM(IS_PSRAM_UHS_PAGE_SIZE_TYPE(cfg->psramPageSize));\n+\n+ if (cfg->pck_freq > 2300) {\n+ /* max support 2300MHZ */\n+ while (1)\n+ ;\n+ } else if (cfg->pck_freq > 1600) {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1a03000f);\n+ } else {\n+ BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1202000b);\n+ }\n+\n+ Psram_analog_init(cfg->pck_freq);\n+\n+ /* Wait 150 us */\n+ arch_delay_us(150);\n+\n+ /* set refresh paramater */\n+ /* 1. auto refresh clock source is pck_t, Adjust pck_t_div so that the frequency is around ~50Mhz */\n+/* tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);\n+ tmpVal &= 0x00ffffff;\n+\n+ if (cfg->pck_freq >= 2200) {\n+ tmpVal |= 0x05000000;\n+ } else if (cfg->pck_freq >= 2000) {\n+ tmpVal |= 0x04000000;\n+ } else if (cfg->pck_freq >= 1500) {\n+ tmpVal |= 0x03000000;\n+ } else if (cfg->pck_freq >= 1400) {\n+ tmpVal |= 0x02000000;\n+ } else if (cfg->pck_freq >= 666) {\n+ tmpVal |= 0x01000000;\n+ }\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal); */\n+\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);\n+ tmpVal &= 0x00ffffff;\n+\n+ if (cfg->pck_freq >= 2200) {\n+ tmpVal |= 0x05000000;\n+ } else if (cfg->pck_freq >= 1800) {\n+ tmpVal |= 0x04000000;\n+ } else if (cfg->pck_freq >= 1500) {\n+ tmpVal |= 0x03000000;\n+ } else if (cfg->pck_freq >= 1400) {\n+ tmpVal |= 0x02000000;\n+ } else if (cfg->pck_freq >= 666) {\n+ tmpVal |= 0x01000000;\n+ }\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal);\n+\n+ /* 2. setting refresh windows cycle count\n+ * reg_win_cycle = refresh_window / Tpck_y\n+ *\n+ * refresh_window unit is ms\n+ * when refresh tempotory > 85\n+ * refresh_window = 16\n+ * elsee\n+ * refresh_window = 32\n+ */\n+ if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0x16e360);\n+ } else {\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0xB71B0);\n+ }\n+ /* 3 & 4. setting refresh count in a windows fixed value 4096 in v0.2\n+ * calculate Average cycle between two auto-refresh\n+ * reg_refi_cycle = reg_win_cycle / reg_win_ref_cnt\n+ * */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_WIN_REF_CNT, 0x1000);\n+ if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (370));\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (190));\n+ }\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2, tmpVal);\n+\n+ /* 5 setting single auto refresh time */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, (uint32_t)(90 / T_pck_t));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, 5);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4, tmpVal);\n+\n+ /* 6 auto-refesh enable */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_AF_EN);\n+\n+ /* 7&8 . set psram memory size and page size */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_ADDRMB_MSK, cfg->psramMemSize);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_LINEAR_BND_B, cfg->psramPageSize);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 9. psram enable initial */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_INIT_EN);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read register for uhs\n+ *\n+ * @param reg_addr: read addr\n+ * @param regVal: regVal\n+ *\n+ * @return success or not\n+ *\n+*******************************************************************************/\n+int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t cnt = 0;\n+\n+ /* 1 generate requeset and wait authorization*/\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ return -1;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));\n+\n+ /* 2 set mode reg */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, reg_addr);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 3 enable controller Rx*/\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGR_PULSE);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* 4 wait read done */\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ return -1;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGR_DONE));\n+\n+ /* 5 steup up read data */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+\n+ *regVal = (uint8_t)(BL_GET_REG_BITS_VAL(tmpVal, PSRAM_UHS_STS_CONFIG_READ));\n+\n+ /* 6 cancel requeset singnal */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ return 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief write register for winbond PSRAM\n+ *\n+ * @param regCfg: wirte reg data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t cnt = 0;\n+ uint8_t regWriteList[] = { 0, 2 };\n+ uint8_t i = 0;\n+\n+ CHECK_PARAM(IS_PSRAM_UHS_DRIVER_ST_TYPE(regCfg->driver_st));\n+ CHECK_PARAM(IS_PSRAM_UHS_WARP_BURST_TYPE(regCfg->burst_size));\n+ CHECK_PARAM(IS_PSRAM_UHS_LATENCY_TYPE(regCfg->lentency));\n+\n+ /* 1 congfi write reg*/\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE);\n+\n+ switch (regCfg->burst_size) {\n+ case PSRAM_UHS_WARP_BURST_64:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);\n+ break;\n+ case PSRAM_UHS_WARP_BURST_32:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);\n+ break;\n+ case PSRAM_UHS_WARP_BURST_16:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);\n+ break;\n+ case PSRAM_UHS_WARP_BURST_NONE:\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);\n+ break;\n+ default:\n+ return -1;\n+ }\n+ if (regCfg->driver_st != PSRAM_UHS_DRIVER_ST_NO_CHANGE) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DRIVE_ST, regCfg->driver_st);\n+ }\n+ if (regCfg->lentency != PSRAM_UHS_LATENCY_NO_CHANGE) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_LATENCY, regCfg->lentency);\n+ }\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE, tmpVal);\n+\n+ /* 2 generate requeset and wait authorization */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ return -1;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));\n+\n+ for (i = 0; i < sizeof(regWriteList) / sizeof(uint8_t); i++) {\n+ /* 3 set mode reg */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, regWriteList[i]);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 4 enable controller */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* 5 wait write done */\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ return -1;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));\n+ }\n+\n+ /* 6 cancel requeset singnal */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ return 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Timing Reset\n+ *\n+ * @param reg_addr: reg_addr\n+ * @param regCfg: wirte reg data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+int PSram_UHS_Timing_Reset(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ arch_delay_us(1000);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 0);\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 4);\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);\n+\n+ return 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief construct cmd wave for psram\n+ *\n+ * @param reg_addr: reg_addr\n+ * @param regCfg: wirte reg data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t cnt = 0;\n+\n+ CHECK_PARAM(IS_PSRAM_UHS_CMD_TYPE(cmd));\n+\n+ /* generate requeset and wait authorization*/\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));\n+\n+ /* enable cmd generate */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+\n+ switch (cmd) {\n+ case PSRAM_UHS_CMD_SELF_REFRESH_IN:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFI_PULSE);\n+ break;\n+ case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFO_PULSE);\n+ break;\n+ case PSRAM_UHS_CMD_GLOBAL_RESET:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_GLBR_PULSE);\n+ /* Wait 15 us for reset */\n+ arch_delay_us(15);\n+ break;\n+ case PSRAM_UHS_CMD_ZQ_CAL_LONG:\n+\n+ /* 3 set mode reg */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 5);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 4 enable controller */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* 5 wait write done */\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));\n+\n+ break;\n+ case PSRAM_UHS_CMD_ZQ_CAL_SHORT:\n+\n+ /* 3 set mode reg */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 6);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 4 enable controller */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* 5 wait write done */\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));\n+ break;\n+ case PSRAM_UHS_CMD_ZQ_CAL_RESET:\n+\n+ /* 3 set mode reg */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 7);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ /* 4 enable controller */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* 5 wait write done */\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));\n+ break;\n+ default:\n+ goto exit;\n+ break;\n+ }\n+\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);\n+\n+ cnt = 0;\n+\n+ /* wait write done */\n+ switch (cmd) {\n+ case PSRAM_UHS_CMD_SELF_REFRESH_IN:\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFI_DONE));\n+ break;\n+ case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFO_DONE));\n+ break;\n+ case PSRAM_UHS_CMD_GLOBAL_RESET:\n+ do {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);\n+ cnt++;\n+ if (cnt > PSRAM_UHS_RW_TIMEOUT)\n+ goto exit;\n+\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_GLBR_DONE));\n+ break;\n+ default:\n+ goto exit;\n+ }\n+\n+ /* 6 cancel requeset singnal */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ return 0;\n+\n+exit:\n+ /* 6 cancel requeset singnal */\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);\n+ BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);\n+\n+ return -1;\n+}\n+\n+/**\n+ * @brief defualt init for 64MB x16 UHS PSRAM\n+ * user should enable UHS PSRAM PLL before call this function\n+ * @param uhs_pll_clk The uhs pll frequency used\n+ */\n+void Psram_UHS_x16_Init(uint32_t uhs_pll_clk)\n+{\n+ PSRAM_UHS_Cfg_Type psramDefaultCfg = {\n+ 2000,\n+ PSRAM_MEM_SIZE_64MB,\n+ PSRAM_PAGE_SIZE_2KB,\n+ PSRAM_UHS_NORMAL_TEMP,\n+ };\n+\n+ PSRAM_UHS_Write_Reg_Cfg_Type writeReg = {\n+ PSRAM_UHS_DRIVER_ST_40_PDPU,\n+ PSRAM_UHS_WARP_BURST_NONE,\n+ PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ,\n+ };\n+\n+ psramDefaultCfg.pck_freq = uhs_pll_clk;\n+\n+ if ((uhs_pll_clk >= 2000) && (uhs_pll_clk <= 2300)) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ;\n+ } else if ((uhs_pll_clk <= 1600) && (uhs_pll_clk > 1066)) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ;\n+ } else if ((uhs_pll_clk < 1067) && (uhs_pll_clk > 800)) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ;\n+ } else if ((uhs_pll_clk <= 800) && (uhs_pll_clk > 667)) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ;\n+ } else if ((uhs_pll_clk < 667) && (uhs_pll_clk > 400)) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ;\n+ } else if (uhs_pll_clk <= 400) {\n+ writeReg.lentency = PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ;\n+ }\n+\n+ /* first initial psram controller*/\n+ Psram_UHS_Init(&psramDefaultCfg);\n+\n+ /* reset psram device*/\n+ PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_GLOBAL_RESET);\n+\n+ arch_delay_us(100);\n+\n+ /* write 1GHZ configuration to psram device */\n+ PSram_UHS_Write_Reg(&writeReg);\n+}\n+\n+/*@} end of group PSRAM_UHS_Public_Functions */\n+\n+/*@} end of group PSRAM_UHS */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fd9451c627068963551a4a3eb818402ec512cc5b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c\n@@ -0,0 +1,1247 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_pwm.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_pwm.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PWM\n+ * @{\n+ */\n+\n+/** @defgroup PWM_Private_Macros\n+ * @{\n+ */\n+#define PWMx_Get_Reg_Addr(id) (PWM_BASE + PWM_CHANNEL_OFFSET + (id)*0x40)\n+#define PWM_INT_TIMEOUT_COUNT (320 * 1000)\n+#define PWM_STOP_TIMEOUT_COUNT (320 * 1000)\n+\n+/*@} end of group PWM_Private_Macros */\n+\n+/** @defgroup PWM_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group PWM_Private_Types */\n+\n+/** @defgroup PWM_Private_Variables\n+ * @{\n+ */\n+\n+/**\n+ * @brief PWM interrupt callback function address array\n+*/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *PWMIntCbfArra[PWMx_ID_MAX][PWM_INT_ALL] = { { NULL } };\n+#endif\n+/*@} end of group PWM_Private_Variables */\n+\n+/** @defgroup PWM_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group PWM_Global_Variables */\n+\n+/** @defgroup PWM_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph);\n+#endif\n+\n+/*@} end of group PWM_Private_Fun_Declaration */\n+\n+/** @defgroup PWM_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief PWM interrupt handle\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t maskVal = 0;\n+ uint32_t PWMx;\n+ uint16_t intIndex;\n+ PWMx_ID_Type id;\n+\n+ for (id = PWM0_ID; id < PWMx_ID_MAX; id++) {\n+ /* Get PWMx start register address */\n+ PWMx = PWMx_Get_Reg_Addr(id);\n+ tmpVal = BL_RD_REG(PWMx, PWM_INT_STS);\n+ maskVal = BL_RD_REG(PWMx, PWM_INT_MASK);\n+ for (intIndex = 0; intIndex < PWM_INT_ALL; intIndex++) {\n+ if (((1 << intIndex) & tmpVal) && (((1 << intIndex) & maskVal) == 0)) {\n+ if (intIndex == PWM_INT_REPT) {\n+ if (BL_GET_REG_BITS_VAL(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STOP_ON_REPT) == 1) {\n+ PWMx_Disable(id);\n+ }\n+ }\n+ BL_WR_REG(PWMx, PWM_INT_CLEAR, 1 << intIndex);\n+ if (PWMIntCbfArra[id][intIndex] != NULL) {\n+ PWMIntCbfArra[id][intIndex]();\n+ }\n+ }\n+ }\n+ }\n+ return SUCCESS;\n+}\n+\n+#endif\n+\n+/*@} end of group PWM_Private_Functions */\n+\n+/** @defgroup PWM_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx init\n+ *\n+ * @param id: PWM ID\n+ * @param chCfg: PWMx configuration\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type PWMx_Init(PWMx_ID_Type id, PWMx_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CLK_TYPE(cfg->clk));\n+ CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(cfg->stopMode));\n+ CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(cfg->extPol));\n+ CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(cfg->adcSrc));\n+\n+ /* Ungate pwm clock gate */\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_PWM);\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));\n+ while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STS_STOP)) {\n+ timeoutCnt--;\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, cfg->clk);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, cfg->stopMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, cfg->extPol);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, cfg->adcSrc);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_ON_REPT, cfg->stpRept);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, cfg->clkDiv);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+\n+ /* Config pwm period and rept count */\n+ tmpVal = BL_RD_REG(PWMx, PWM_PERIOD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, cfg->period);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, cfg->intPulseCnt);\n+ BL_WR_REG(PWMx, PWM_PERIOD, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(PWM_IRQn, PWM_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx update clock divider\n+ *\n+ * @param id: PWM ID\n+ * @param div: Clock divider\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div)\n+{\n+ uint32_t tmpVal;\n+ //* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, div);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx update period\n+ *\n+ * @param id: PWM ID\n+ * @param period: period\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Config pwm period and duty */\n+ tmpVal = BL_RD_REG(PWMx, PWM_PERIOD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, period);\n+ BL_WR_REG(PWMx, PWM_PERIOD, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx get configuration\n+ *\n+ * @param id: PWM ID\n+ * @param period: period pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* get pwm period */\n+ tmpVal = BL_RD_REG(PWMx, PWM_PERIOD);\n+ *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx enable\n+ *\n+ * @param id: PWMx ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWMx_Enable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Config pwm clock to enable pwm */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PWMx disable\n+ *\n+ * @param id: PWMx ID\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWMx_Disable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+\n+ /* Config pwm clock to disable pwm */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));\n+}\n+\n+void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modP));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modN));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polP));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polN));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlP));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlN));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkP));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkN));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, cfg->modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, cfg->modN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, cfg->polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, cfg->polN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, cfg->idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, cfg->idlN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, cfg->brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, cfg->brkN);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, cfg->modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, cfg->modN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, cfg->polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, cfg->polN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, cfg->idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, cfg->idlN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, cfg->brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, cfg->brkN);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, cfg->modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, cfg->modN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, cfg->polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, cfg->polN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, cfg->idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, cfg->idlN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, cfg->brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, cfg->brkN);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, cfg->modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, cfg->modN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, cfg->polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, cfg->polN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, cfg->idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, cfg->idlN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, cfg->brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, cfg->brkN);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+\n+ /* Config pwm thresholdL and thresholdH */\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, cfg->thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, cfg->thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, cfg->thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, cfg->thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, cfg->thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, cfg->thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, cfg->thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, cfg->thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ /* Config pwm dead time */\n+ tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, cfg->dtg);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, cfg->dtg);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, cfg->dtg);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, cfg->dtg);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal);\n+}\n+\n+void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL);\n+ BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL);\n+ BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL);\n+ BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL);\n+ BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH);\n+ BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+\n+ /* get pwm thresholdL and thresholdH */\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE);\n+ *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL);\n+ *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE);\n+ *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL);\n+ *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE);\n+ *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL);\n+ *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE);\n+ *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL);\n+ *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n+void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(modP));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(modN));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, modN);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, modN);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, modN);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, modP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, modN);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(mod));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, mod);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, mod);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, mod);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, mod);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_MODE_TYPE(mod));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, mod);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, mod);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, mod);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, mod);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(polP));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(polN));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, polN);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, polN);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, polN);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, polP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, polN);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, pol);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, pol);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, pol);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, pol);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, pol);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, pol);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, pol);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, pol);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlP));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlN));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idlN);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idlN);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idlN);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idlP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idlN);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idl);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idl);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idl);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idl);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idl);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idl);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idl);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idl);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkP));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkN));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brkN);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brkN);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brkN);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brkP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brkN);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brk);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brk);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brk);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brk);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+ CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brk);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brk);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brk);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brk);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal);\n+}\n+\n+void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg)\n+{\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Config pwm config1 */\n+ BL_WR_REG(PWMx, PWM_CONFIG1, cfg);\n+}\n+\n+void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg)\n+{\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Get pwm config1 value */\n+ *cfg = BL_RD_REG(PWMx, PWM_CONFIG1);\n+}\n+\n+void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_CHx_TYPE(ch));\n+\n+ /* Config pwm config1 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME);\n+ switch (ch) {\n+ case PWM_CH0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, dtg);\n+ break;\n+ case PWM_CH1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, dtg);\n+ break;\n+ case PWM_CH2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, dtg);\n+ break;\n+ case PWM_CH3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, dtg);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal);\n+}\n+\n+void PWM_SW_Break_Enable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PWM_SW_BREAK_EN);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+void PWM_SW_Break_Disable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_SW_BREAK_EN);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+void PWM_EXT_Break_Enable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PWM_EXT_BREAK_EN);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+void PWM_EXT_Break_Disable(PWMx_ID_Type id)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_EXT_BREAK_EN);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(pol));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, pol);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(src));\n+\n+ /* Config pwm config0 */\n+ tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, src);\n+ BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Mask/Unmask the PWM interrupt\n+ *\n+ * @param id: PWM ID\n+ * @param intType: Specifies the interrupt type\n+ * @param intMask: Enable/Disable Specified interrupt type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(PWMx, PWM_INT_MASK);\n+ if (intType == PWM_INT_ALL) {\n+ if (intMask == UNMASK) {\n+ tmpVal &= ~((1U << PWM_INT_ALL) - 1);\n+ } else {\n+ tmpVal |= ((1U << PWM_INT_ALL) - 1);\n+ }\n+ } else {\n+ if (intMask == UNMASK) {\n+ tmpVal &= ~(1U << intType);\n+ } else {\n+ tmpVal |= (1U << intType);\n+ }\n+ }\n+ BL_WR_REG(PWMx, PWM_INT_MASK, tmpVal);\n+}\n+\n+void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWMx_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(PWMx, PWM_INT_CLEAR);\n+\n+ if (intType == PWM_INT_ALL) {\n+ tmpVal = ((1U << PWM_INT_ALL) - 1);\n+ } else {\n+ tmpVal = (1U << intType);\n+ }\n+ BL_WR_REG(PWMx, PWM_INT_CLEAR, tmpVal);\n+}\n+\n+BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ /* Get PWMx start register address */\n+ uint32_t PWMx = PWMx_Get_Reg_Addr(id);\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_PWM_CH_ID_TYPE(id));\n+ CHECK_PARAM(IS_PWM_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(PWMx, PWM_INT_STS);\n+\n+ if (intType == PWM_INT_ALL) {\n+ if (tmpVal & ((1 << PWM_CHx_MAX) - 1)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ if (tmpVal & (1 << intType)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install PWM interrupt callback function\n+ *\n+ * @param id: PWM ID\n+ * @param intType: PWM interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun)\n+{\n+ PWMIntCbfArra[id][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief PWM interrupt function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void PWM_IRQHandler(void)\n+{\n+ PWM_IntHandler(PWM_IRQn);\n+}\n+#endif\n+\n+/*@} end of group PWM_Public_Functions */\n+\n+/*@} end of group PWM */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c72d6ab20e374fc561ac447b599a1a7565863068\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c\n@@ -0,0 +1,2536 @@\n+#include \"bl808_romdriver_e907.h\"\n+\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_LowPower_Enter_PDS0(void){\n+ return RomDriver_AON_LowPower_Enter_PDS0();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_LowPower_Exit_PDS0(void){\n+ return RomDriver_AON_LowPower_Exit_PDS0();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_Off_BG(void){\n+ return RomDriver_AON_Power_Off_BG();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_Off_LDO15_RF(void){\n+ return RomDriver_AON_Power_Off_LDO15_RF();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_Off_MBG(void){\n+ return RomDriver_AON_Power_Off_MBG();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_Off_SFReg(void){\n+ return RomDriver_AON_Power_Off_SFReg();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_Off_XTAL(void){\n+ return RomDriver_AON_Power_Off_XTAL();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_On_BG(void){\n+ return RomDriver_AON_Power_On_BG();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_On_LDO15_RF(void){\n+ return RomDriver_AON_Power_On_LDO15_RF();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_On_MBG(void){\n+ return RomDriver_AON_Power_On_MBG();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_On_SFReg(void){\n+ return RomDriver_AON_Power_On_SFReg();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Power_On_XTAL(void){\n+ return RomDriver_AON_Power_On_XTAL();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel){\n+ return RomDriver_AON_Set_DCDC11_Top_Vout(dcdcLevel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut){\n+ return RomDriver_AON_Set_Xtal_CapCode(capIn,capOut);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Trim_DCDC11_Vout(void){\n+ return RomDriver_AON_Trim_DCDC11_Vout();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Trim_DCDC18_Vout(void){\n+ return RomDriver_AON_Trim_DCDC18_Vout();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type AON_Trim_USB20_RCAL(void){\n+ return RomDriver_AON_Trim_USB20_RCAL();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t AON_Get_Xtal_CapCode(void){\n+ return RomDriver_AON_Get_Xtal_CapCode();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT){\n+ return RomDriver_ASM_Delay_Us(core,cnt,loopT);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void arch_delay_ms(uint32_t cnt){\n+ return RomDriver_arch_delay_ms(cnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void arch_delay_us(uint32_t cnt){\n+ return RomDriver_arch_delay_us(cnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type EF_Ctrl_Crc_Result(void){\n+ return RomDriver_EF_Ctrl_Crc_Result();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]){\n+ return RomDriver_EF_Ctrl_Get_Customer_PIDVID(pid,vid);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]){\n+ return RomDriver_EF_Ctrl_Read_Chip_ID(chipID);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]){\n+ return RomDriver_EF_Ctrl_Read_MAC_Address(mac);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]){\n+ return RomDriver_EF_Ctrl_Read_MAC_Address_Raw(mac);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void){\n+ return RomDriver_EF_Ctrl_AutoLoad_Done();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type EF_Ctrl_Busy(void){\n+ return RomDriver_EF_Ctrl_Busy();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void){\n+ return RomDriver_EF_Ctrl_Crc_Is_Busy();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len){\n+ return RomDriver_EF_Ctrl_Get_Trim_Parity(val,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len){\n+ return RomDriver_EF_Ctrl_Is_All_Bits_Zero(val,start,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len){\n+ return RomDriver_EF_Ctrl_Clear(region,index,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Crc_Enable(void){\n+ return RomDriver_EF_Ctrl_Crc_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue){\n+ return RomDriver_EF_Ctrl_Crc_Set_Golden(goldenValue);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Load_Efuse_R0(void){\n+ return RomDriver_EF_Ctrl_Load_Efuse_R0();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Load_Efuse_R1(void){\n+ return RomDriver_EF_Ctrl_Load_Efuse_R1();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Program_Direct(region,index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Program_Direct_R0(index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Program_Direct_R1(index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Program_Efuse_0(void){\n+ return RomDriver_EF_Ctrl_Program_Efuse_0();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Program_Efuse_1(void){\n+ return RomDriver_EF_Ctrl_Program_Efuse_1();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_ADC_Gain_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len){\n+ return RomDriver_EF_Ctrl_Read_AES_Key(index,keyData,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_DCDC11_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_DCDC18_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh){\n+ return RomDriver_EF_Ctrl_Read_Dbg_Pwd(slot,passWdLow,passWdHigh);\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo){\n+ return RomDriver_EF_Ctrl_Read_Device_Info(deviceInfo);\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Read_Direct(region,index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Read_Direct_R0(index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len){\n+ return RomDriver_EF_Ctrl_Read_Direct_R1(index,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_LDO18FLASH_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_LDO18IO_Vout_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_RC32K_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_RC32M_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]){\n+ return RomDriver_EF_Ctrl_Read_Secure_Boot(aes);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg){\n+ return RomDriver_EF_Ctrl_Read_Secure_Cfg(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage){\n+ return RomDriver_EF_Ctrl_Read_Sw_Usage(index,usage);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_TSEN_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim){\n+ return RomDriver_EF_Ctrl_Read_USB20RCAL_Trim(trim);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal){\n+ return RomDriver_EF_Ctrl_Read_Xtal_Trim_RC32M(forceNoTrim,noXtal);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program){\n+ return RomDriver_EF_Ctrl_Readlock_AES_Key(index,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program){\n+ return RomDriver_EF_Ctrl_Readlock_Dbg_Pwd(program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel){\n+ return RomDriver_EF_Ctrl_Set_sf_key_re_sel(ef_sf_key_re_sel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Sw_AHB_Clk_0(void){\n+ return RomDriver_EF_Ctrl_Sw_AHB_Clk_0();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Sw_AHB_Clk_1(void){\n+ return RomDriver_EF_Ctrl_Sw_AHB_Clk_1();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_AES_Key(index,keyData,len,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_Dbg_Pwd(slot,passWdLow,passWdHigh,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_MAC_Address(mac,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_Secure_Boot(sign,aes,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_Secure_Cfg(cfg,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program){\n+ return RomDriver_EF_Ctrl_Write_Sw_Usage(index,usage,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program){\n+ return RomDriver_EF_Ctrl_Writelock_AES_Key(index,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program){\n+ return RomDriver_EF_Ctrl_Writelock_Dbg_Pwd(program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Writelock_MAC_Address(uint8_t program){\n+ return RomDriver_EF_Ctrl_Writelock_MAC_Address(program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program){\n+ return RomDriver_EF_Ctrl_Writelock_Sw_Usage(index,program);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst){\n+ return RomDriver_GLB_AHB_DSP_Software_Reset(swrst);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst){\n+ return RomDriver_GLB_AHB_MCU_Software_Reset(swrst);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg){\n+ return RomDriver_GLB_BMX_TO_Init(BmxCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Clr_BMX_TO_Status(void){\n+ return RomDriver_GLB_Clr_BMX_TO_Status();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Clr_EMI_Reset_Gate(void){\n+ return RomDriver_GLB_Clr_EMI_Reset_Gate();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){\n+ return RomDriver_GLB_Config_AUDIO_PLL(xtalType,pllCfgList);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){\n+ return RomDriver_GLB_Config_CPU_PLL(xtalType,pllCfgList);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList){\n+ return RomDriver_GLB_Config_MIPI_PLL(xtalType,pllCfgList);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio){\n+ return RomDriver_GLB_Config_MIPI_PLL_Div(divEn,divRatio);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList){\n+ return RomDriver_GLB_Config_UHS_PLL(xtalType,pllCfgList);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){\n+ return RomDriver_GLB_Config_WIFI_PLL(xtalType,pllCfgList);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP0_Clock_Disable(void){\n+ return RomDriver_GLB_DSP0_Clock_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP0_Clock_Enable(void){\n+ return RomDriver_GLB_DSP0_Clock_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType){\n+ return RomDriver_GLB_DSP_Clr_MCU_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart){\n+ return RomDriver_GLB_DSP_Codec_Sub_Reset(codecPart);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part){\n+ return RomDriver_GLB_DSP_DSP2_Sub_Reset(dsp2Part);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart){\n+ return RomDriver_GLB_DSP_Image_Sensor_Reset(imageSensorPart);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart){\n+ return RomDriver_GLB_DSP_Peripheral_Reset(periPart);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart){\n+ return RomDriver_GLB_DSP_SW_System_Reset(sysPart);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType){\n+ return RomDriver_GLB_DSP_Set_LP_IntEn(enable,intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask){\n+ return RomDriver_GLB_DSP_Set_MCU_IntMask(intType,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType){\n+ return RomDriver_GLB_Get_Auto_Calc_Xtal_Type(calcXtalType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv){\n+ return RomDriver_GLB_Get_DSP_PBCLK_Div(dspPBclkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv){\n+ return RomDriver_GLB_Get_DSP_System_CLK_Div(dspClkDiv,dspBclkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv){\n+ return RomDriver_GLB_Get_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv,lpClkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Halt_CPU(GLB_CORE_ID_Type coreID){\n+ return RomDriver_GLB_Halt_CPU(coreID);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_IR_LED_Driver_Disable(void){\n+ return RomDriver_GLB_IR_LED_Driver_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_IR_LED_Driver_Enable(void){\n+ return RomDriver_GLB_IR_LED_Driver_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio){\n+ return RomDriver_GLB_IR_RX_GPIO_Sel(gpio);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable){\n+ return RomDriver_GLB_Invert_ETH_REF_O_CLK(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable){\n+ return RomDriver_GLB_Invert_ETH_RX_CLK(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable){\n+ return RomDriver_GLB_Invert_ETH_TX_CLK(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType){\n+ return RomDriver_GLB_MCU_Clr_DSP_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart){\n+ return RomDriver_GLB_MCU_SW_System_Reset(sysPart);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask){\n+ return RomDriver_GLB_MCU_Set_DSP_IntMask(intType,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio){\n+ return RomDriver_GLB_Output_EMAC_CLK(gpio);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips){\n+ return RomDriver_GLB_PER_Clock_Gate(ips);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips){\n+ return RomDriver_GLB_PER_Clock_UnGate(ips);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk){\n+ return RomDriver_GLB_PLL_CGEN_Clock_Gate(clk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk){\n+ return RomDriver_GLB_PLL_CGEN_Clock_UnGate(clk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable){\n+ return RomDriver_GLB_Platform_Wakeup_PDS_Enable(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType){\n+ return RomDriver_GLB_Power_Off_MU_PLL(pllType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType){\n+ return RomDriver_GLB_Power_Off_WAC_PLL(pllType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable){\n+ return RomDriver_GLB_Power_On_MU_PLL(pllType,cfg,waitStable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable){\n+ return RomDriver_GLB_Power_On_WAC_PLL(pllType,cfg,waitStable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType){\n+ return RomDriver_GLB_Power_On_XTAL_And_PLL_CLK(xtalType,pllType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Release_CPU(GLB_CORE_ID_Type coreID){\n+ return RomDriver_GLB_Release_CPU(coreID);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_SW_CPU_Reset(void){\n+ return RomDriver_GLB_SW_CPU_Reset();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_SW_POR_Reset(void){\n+ return RomDriver_GLB_SW_POR_Reset();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_SW_System_Reset(void){\n+ return RomDriver_GLB_SW_System_Reset();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_Sel_DSP_TMR_GPIO_Clock(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_Sel_MCU_TMR_GPIO_Clock(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_ADC_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div){\n+ return RomDriver_GLB_Set_Audio_ADC_CLK(enable,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn){\n+ return RomDriver_GLB_Set_Audio_AUTO_CLK(divEn);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div){\n+ return RomDriver_GLB_Set_Audio_DAC_CLK(enable,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div){\n+ return RomDriver_GLB_Set_Audio_PDM_CLK(enable,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType){\n+ return RomDriver_GLB_Set_Auto_Calc_Xtal_Type(calcXtalType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_CAM_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr){\n+ return RomDriver_GLB_Set_CPU_Reset_Address(coreID,addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel){\n+ return RomDriver_GLB_Set_CSI_DSI_CLK_Sel(csiClkSel,dsiClkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType){\n+ return RomDriver_GLB_Set_Chip_Clock_Out0_Sel(clkOutType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType){\n+ return RomDriver_GLB_Set_Chip_Clock_Out1_Sel(clkOutType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType){\n+ return RomDriver_GLB_Set_Chip_Clock_Out2_Sel(clkOutType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType){\n+ return RomDriver_GLB_Set_Chip_Clock_Out3_Sel(clkOutType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div){\n+ return RomDriver_GLB_Set_DIG_32K_CLK(enable,compensationEn,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div){\n+ return RomDriver_GLB_Set_DIG_512K_CLK(enable,compensationEn,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel){\n+ return RomDriver_GLB_Set_DIG_CLK_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk){\n+ return RomDriver_GLB_Set_DMA_CLK(enable,clk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_CNN_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_DP_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_H264_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_I2C0_CLK(enable,clkSel,divEn,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_I2C1_CLK(enable,clkSel,divEn,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_DSP2_CLK(enable,clkSel,div);\n+}\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel){\n+ return RomDriver_GLB_Set_DSP_L2SRAM_Available_Size(h2pfSramRel,vramSramRel,dspl2SramRel,blaiSramRel);\n+}\n+#endif\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst){\n+ return RomDriver_GLB_Set_DSP_MTimer_CLK(enable,div,rst);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk){\n+ return RomDriver_GLB_Set_DSP_MUXPLL_CLK_Sel(pllClk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel){\n+ return RomDriver_GLB_Set_DSP_Muxpll_160M_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel){\n+ return RomDriver_GLB_Set_DSP_Muxpll_240M_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel){\n+ return RomDriver_GLB_Set_DSP_Muxpll_320M_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel){\n+ return RomDriver_GLB_Set_DSP_PBCLK(pbClkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv){\n+ return RomDriver_GLB_Set_DSP_PBCLK_Div(dspPBclkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk){\n+ return RomDriver_GLB_Set_DSP_PBROOT_CLK_Sel(pbrootClk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk){\n+ return RomDriver_GLB_Set_DSP_ROOT_CLK_Sel(rootClk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod){\n+ return RomDriver_GLB_Set_DSP_SPI_0_ACT_MOD_Sel(mod);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_SPI_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq){\n+ return RomDriver_GLB_Set_DSP_System_CLK(clkFreq);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv){\n+ return RomDriver_GLB_Set_DSP_System_CLK_Div(dspClkDiv,dspBclkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_UART0_CLK(enable,uartClk,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div){\n+ return RomDriver_GLB_Set_DSP_UART1_CLK(enable,uartClk,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk){\n+ return RomDriver_GLB_Set_DSP_XCLK_Sel(xclk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv){\n+ return RomDriver_GLB_Set_Display_CLK(enable,srcClk,evenDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable){\n+ return RomDriver_GLB_Set_EMAC_CLK(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div){\n+ return RomDriver_GLB_Set_EMI_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType){\n+ return RomDriver_GLB_Set_EM_Sel(emType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel){\n+ return RomDriver_GLB_Set_ETH_REF_O_CLK_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap){\n+ return RomDriver_GLB_Set_Flash_IO_PARM(selEmbedded,swap);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue){\n+ return RomDriver_GLB_Set_Flash_Id_Value(idValue);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_I2C_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef){\n+ return RomDriver_GLB_Set_I2S_CLK(refClkEn,refClkDiv,inRef,outRef);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_IR_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst){\n+ return RomDriver_GLB_Set_MCU_MTimer_CLK(enable,div,rst);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel){\n+ return RomDriver_GLB_Set_MCU_Muxpll_160M_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel){\n+ return RomDriver_GLB_Set_MCU_Muxpll_80M_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod){\n+ return RomDriver_GLB_Set_MCU_SPI_0_ACT_MOD_Sel(mod);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq){\n+ return RomDriver_GLB_Set_MCU_System_CLK(clkFreq);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv){\n+ return RomDriver_GLB_Set_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv,lpClkDiv);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div){\n+ return RomDriver_GLB_Set_PADC_CLK(enable,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel){\n+ return RomDriver_GLB_Set_PDM_IO_Sel(ioSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel){\n+ return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div){\n+ return RomDriver_GLB_Set_PSram_CLK(id,enable,pll,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel){\n+ return RomDriver_GLB_Set_PWM1_IO_Sel(ioSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel){\n+ return RomDriver_GLB_Set_PWM2_IO_Sel(ioSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn){\n+ return RomDriver_GLB_Set_Peripheral_DMA_CN(peri,cn);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_SDH_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_SF_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_SPI_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value){\n+ return RomDriver_GLB_Set_SRAM_PARM(value);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value){\n+ return RomDriver_GLB_Set_SRAM_RET(value);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value){\n+ return RomDriver_GLB_Set_SRAM_SLP(value);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType){\n+ return RomDriver_GLB_Set_UART2_IO_Sel(ioType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div){\n+ return RomDriver_GLB_Set_UART_CLK(enable,clkSel,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable){\n+ return RomDriver_GLB_Set_USB_CLK_From_WIFIPLL(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState){\n+ return RomDriver_GLB_Swap_DSP_SPI_0_MOSI_With_MISO(newState);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState){\n+ return RomDriver_GLB_Swap_MCU_SPI_0_MOSI_With_MISO(newState);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Trim_LDO18FLASH_Vout(void){\n+ return RomDriver_GLB_Trim_LDO18FLASH_Vout();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Trim_LDO18IO_Vout(void){\n+ return RomDriver_GLB_Trim_LDO18IO_Vout();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun){\n+ return RomDriver_GLB_UART_Fun_Sel(sig,fun);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap){\n+ return RomDriver_GLB_UART_Sig_Swap_Set(group,swap);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType){\n+ return RomDriver_GLB_DSP_Get_LP_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType){\n+ return RomDriver_GLB_DSP_Get_MCU_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType){\n+ return RomDriver_GLB_MCU_Get_DSP_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_CORE_ID_Type GLB_Get_Core_Type(void){\n+ return RomDriver_GLB_Get_Core_Type();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_MUXPLL_160M_CLK_SEL_Type GLB_Get_DSP_Muxpll_160M_Sel(void){\n+ return RomDriver_GLB_Get_DSP_Muxpll_160M_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_MUXPLL_240M_CLK_SEL_Type GLB_Get_DSP_Muxpll_240M_Sel(void){\n+ return RomDriver_GLB_Get_DSP_Muxpll_240M_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_MUXPLL_320M_CLK_SEL_Type GLB_Get_DSP_Muxpll_320M_Sel(void){\n+ return RomDriver_GLB_Get_DSP_Muxpll_320M_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_PBROOT_CLK_Type GLB_Get_DSP_PBROOT_CLK_Sel(void){\n+ return RomDriver_GLB_Get_DSP_PBROOT_CLK_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_ROOT_CLK_Type GLB_Get_DSP_ROOT_CLK_Sel(void){\n+ return RomDriver_GLB_Get_DSP_ROOT_CLK_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_DSP_XCLK_Type GLB_Get_DSP_XCLK_Sel(void){\n+ return RomDriver_GLB_Get_DSP_XCLK_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_MCU_MUXPLL_160M_CLK_SEL_Type GLB_Get_MCU_Muxpll_160M_Sel(void){\n+ return RomDriver_GLB_Get_MCU_Muxpll_160M_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+GLB_MCU_MUXPLL_80M_CLK_SEL_Type GLB_Get_MCU_Muxpll_80M_Sel(void){\n+ return RomDriver_GLB_Get_MCU_Muxpll_80M_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_Get_Flash_Id_Value(void){\n+ return RomDriver_GLB_Get_Flash_Id_Value();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_Get_SRAM_PARM(void){\n+ return RomDriver_GLB_Get_SRAM_PARM();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_Get_SRAM_RET(void){\n+ return RomDriver_GLB_Get_SRAM_RET();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_Get_SRAM_SLP(void){\n+ return RomDriver_GLB_Get_SRAM_SLP();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t GLB_Get_BMX_TO_Status(void){\n+ return RomDriver_GLB_Get_BMX_TO_Status();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_Clr_GPIO_IntStatus(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_Embedded_Flash_Pad_Enable(void){\n+ return RomDriver_GLB_Embedded_Flash_Pad_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Clr(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Fifo_Clear(void){\n+ return RomDriver_GLB_GPIO_Fifo_Clear();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg){\n+ return RomDriver_GLB_GPIO_Fifo_Init(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType){\n+ return RomDriver_GLB_GPIO_Fifo_IntClear(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask){\n+ return RomDriver_GLB_GPIO_Fifo_IntMask(intType,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len){\n+ return RomDriver_GLB_GPIO_Fifo_Push(data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt){\n+ return RomDriver_GLB_GPIO_Func_Init(gpioFun,pinList,cnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg){\n+ return RomDriver_GLB_GPIO_Init(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Input_Disable(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Input_Enable(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask){\n+ return RomDriver_GLB_GPIO_IntMask(gpioPin,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg){\n+ return RomDriver_GLB_GPIO_Int_Init(intCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Output_Disable(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Output_Enable(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Set(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Set_HZ(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val){\n+ return RomDriver_GLB_GPIO_Write(gpioPin,val);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_GPIO_Fifo_Disable(void){\n+ return RomDriver_GLB_GPIO_Fifo_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_GPIO_Fifo_Enable(void){\n+ return RomDriver_GLB_GPIO_Fifo_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType){\n+ return RomDriver_GLB_GPIO_Fifo_GetIntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_Get_GPIO_IntStatus(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_GPIO_Fifo_GetCount(void){\n+ return RomDriver_GLB_GPIO_Fifo_GetCount();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Read(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin){\n+ return RomDriver_GLB_GPIO_Get_Fun(gpioPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType){\n+ return RomDriver_HBN_32K_Sel(clkType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg){\n+ return RomDriver_HBN_Aon_Pad_Cfg(aonPadHwCtrlEn,aonGpio,aonPadCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2){\n+ return RomDriver_HBN_Aon_Pad_Ctrl(aonPadCtl1,aonPadCtl2);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec){\n+ return RomDriver_HBN_Aon_Pad_WakeUpCfg(puPdEn,trigMode,maskVal,dlyEn,dlySec);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType){\n+ return RomDriver_HBN_Clear_IRQ(irqType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Clear_RTC_Counter(void){\n+ return RomDriver_HBN_Clear_RTC_Counter();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Clear_RTC_INT(void){\n+ return RomDriver_HBN_Clear_RTC_INT();\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Disable_AComp0_IRQ(void){\n+ return RomDriver_HBN_Disable_AComp0_IRQ();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Disable_AComp1_IRQ(void){\n+ return RomDriver_HBN_Disable_AComp1_IRQ();\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Disable_BOD_IRQ(void){\n+ return RomDriver_HBN_Disable_BOD_IRQ();\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Enable_AComp0_IRQ(void){\n+ return RomDriver_HBN_Enable_AComp0_IRQ();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Enable_AComp1_IRQ(void){\n+ return RomDriver_HBN_Enable_AComp1_IRQ();\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Enable_BOD_IRQ(void){\n+ return RomDriver_HBN_Enable_BOD_IRQ();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Enable_RTC_Counter(void){\n+ return RomDriver_HBN_Enable_RTC_Counter();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_GPIO_INT_Disable(void){\n+ return RomDriver_HBN_GPIO_INT_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType){\n+ return RomDriver_HBN_GPIO_INT_Enable(gpioIntTrigType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg){\n+ return RomDriver_HBN_Get_RTC_Misc_Cfg(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh){\n+ return RomDriver_HBN_Get_RTC_Timer_Val(valLow,valHigh);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Get_Xtal_Type(uint8_t *xtalType){\n+ return RomDriver_HBN_Get_Xtal_Type(xtalType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable){\n+ return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PD_RC32K_All_State(void){\n+ return RomDriver_HBN_PD_RC32K_All_State();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PD_RC32K_In_Poff(void){\n+ return RomDriver_HBN_PD_RC32K_In_Poff();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PIR_Disable(void){\n+ return RomDriver_HBN_PIR_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PIR_Enable(void){\n+ return RomDriver_HBN_PIR_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf){\n+ return RomDriver_HBN_PIR_HPF_Sel(hpf);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg){\n+ return RomDriver_HBN_PIR_INT_Config(pirIntCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf){\n+ return RomDriver_HBN_PIR_LPF_Sel(lpf);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal){\n+ return RomDriver_HBN_Pin_WakeUp_Mask(maskVal);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Power_Off_RC32K(void){\n+ return RomDriver_HBN_Power_Off_RC32K();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Power_Off_Xtal_32K(void){\n+ return RomDriver_HBN_Power_Off_Xtal_32K();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Power_On_RC32K(void){\n+ return RomDriver_HBN_Power_On_RC32K();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Power_On_Xtal_32K(void){\n+ return RomDriver_HBN_Power_On_Xtal_32K();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Reset(void){\n+ return RomDriver_HBN_Reset();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg){\n+ return RomDriver_HBN_Set_BOD_Cfg(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode){\n+ return RomDriver_HBN_Set_BOD_Config(enable,threshold,mode);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg){\n+ return RomDriver_HBN_Set_Core_Reboot_Config(core,hcfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_HRAM_Ret(void){\n+ return RomDriver_HBN_Set_HRAM_Ret();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_HRAM_slp(void){\n+ return RomDriver_HBN_Set_HRAM_slp();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Hand_Off_Config(uint8_t dcfg){\n+ return RomDriver_HBN_Set_Hand_Off_Config(dcfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_IO4041_As_Xtal_32K_IO(uint8_t xtal32kIoEn){\n+ return RomDriver_HBN_Set_IO4041_As_Xtal_32K_IO(xtal32kIoEn);\n+}\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel){\n+ return RomDriver_HBN_Set_Ldo11_All_Vout(ldoLevel);\n+}\n+#endif\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel){\n+ return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel){\n+ return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel);\n+}\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel){\n+ return RomDriver_HBN_Set_Ldo11_Rtc_Vout(ldoLevel);\n+}\n+#endif\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Ldo18flash_Repower_Delay(uint8_t delay){\n+ return RomDriver_HBN_Set_Ldo18flash_Repower_Delay(delay);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk){\n+ return RomDriver_HBN_Set_MCU_Root_CLK_Sel(rootClk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk){\n+ return RomDriver_HBN_Set_MCU_XCLK_Sel(xclk);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_MM_Power_Config(uint8_t pcfg){\n+ return RomDriver_HBN_Set_MM_Power_Config(pcfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval){\n+ return RomDriver_HBN_Set_PIR_Interval(interval);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold){\n+ return RomDriver_HBN_Set_PIR_Threshold(threshold);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg){\n+ return RomDriver_HBN_Set_RTC_Misc_Cfg(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode){\n+ return RomDriver_HBN_Set_RTC_Timer(delay,compValLow,compValHigh,compMode);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag){\n+ return RomDriver_HBN_Set_Status_Flag(flag);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel){\n+ return RomDriver_HBN_Set_UART_CLK_Sel(clkSel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr){\n+ return RomDriver_HBN_Set_Wakeup_Addr(addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Set_Xtal_Type(uint8_t xtalType){\n+ return RomDriver_HBN_Set_Xtal_Type(xtalType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type HBN_Trim_RC32K(void){\n+ return RomDriver_HBN_Trim_RC32K();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type HBN_Get_BOD_OUT_State(void){\n+ return RomDriver_HBN_Get_BOD_OUT_State();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType){\n+ return RomDriver_HBN_Get_INT_State(irqType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+HBN_MCU_ROOT_CLK_Type HBN_Get_MCU_Root_CLK_Sel(void){\n+ return RomDriver_HBN_Get_MCU_Root_CLK_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+HBN_MCU_XCLK_Type HBN_Get_MCU_XCLK_Sel(void){\n+ return RomDriver_HBN_Get_MCU_XCLK_Sel();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint16_t HBN_Get_Ldo18flash_Repower_Config(void){\n+ return RomDriver_HBN_Get_Ldo18flash_Repower_Config();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint16_t HBN_Get_PIR_Interval(void){\n+ return RomDriver_HBN_Get_PIR_Interval();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint16_t HBN_Get_PIR_Threshold(void){\n+ return RomDriver_HBN_Get_PIR_Threshold();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t HBN_Get_Status_Flag(void){\n+ return RomDriver_HBN_Get_Status_Flag();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t HBN_Get_Wakeup_Addr(void){\n+ return RomDriver_HBN_Get_Wakeup_Addr();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t HBN_Get_Core_Unhalt_Config(void){\n+ return RomDriver_HBN_Get_Core_Unhalt_Config();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t HBN_Get_Hand_Off_Config(void){\n+ return RomDriver_HBN_Get_Hand_Off_Config();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t HBN_Get_MM_Power_Config(void){\n+ return RomDriver_HBN_Get_MM_Power_Config();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t HBN_Get_Pin_Wakeup_Mode(void){\n+ return RomDriver_HBN_Get_Pin_Wakeup_Mode();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq){\n+ return RomDriver_HBN_Enable(aGPIOIeCfg,ldoLevel,hbnLevel,dcdcPuSeq);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg){\n+ return RomDriver_HBN_Mode_Enter(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_HBN_Power_Down_Flash(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Clean_All(void){\n+ return RomDriver_L1C_DCache_Clean_All();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len){\n+ return RomDriver_L1C_DCache_Clean_By_Addr(addr,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Clean_Invalid_All(void){\n+ return RomDriver_L1C_DCache_Clean_Invalid_All();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len){\n+ return RomDriver_L1C_DCache_Clean_Invalid_By_Addr(addr,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Disable(void){\n+ return RomDriver_L1C_DCache_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Enable(uint8_t wayDsiable){\n+ return RomDriver_L1C_DCache_Enable(wayDsiable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Invalid_All(void){\n+ return RomDriver_L1C_DCache_Invalid_All();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len){\n+ return RomDriver_L1C_DCache_Invalid_By_Addr(addr,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_ICache_Disable(void){\n+ return RomDriver_L1C_ICache_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_ICache_Enable(uint8_t wayDsiable){\n+ return RomDriver_L1C_ICache_Enable(wayDsiable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_ICache_Invalid_All(void){\n+ return RomDriver_L1C_ICache_Invalid_All();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len){\n+ return RomDriver_L1C_ICache_Invalid_By_Addr(addr,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting){\n+ return RomDriver_L1C_Set_Cache_Setting_By_ID(core,cacheSetting);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type L1C_Set_Wrap(uint8_t en){\n+ return RomDriver_L1C_Set_Wrap(en);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+int L1C_Get_None_Cache_Addr(uintptr_t addr){\n+ return RomDriver_L1C_Get_None_Cache_Addr(addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+int L1C_Is_DCache_Range(uintptr_t addr){\n+ return RomDriver_L1C_Is_DCache_Range(addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn){\n+ return RomDriver_L1C_DCache_Write_Set(wtEn,wbEn,waEn);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, uint32_t pdsSleepCnt){\n+ return RomDriver_PDS_Default_Level_Config(defaultLvCfg,ram1Cfg,ram2Cfg,pdsSleepCnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt){\n+ return RomDriver_PDS_Enable(cfg,cfg4,pdsSleepCnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5){\n+ return RomDriver_PDS_Force_Config(cfg2,cfg3,cfg5);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_IntClear(void){\n+ return RomDriver_PDS_IntClear();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask){\n+ return RomDriver_PDS_IntMask(intType,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Power_On_MM_System(void){\n+ return RomDriver_PDS_Power_On_MM_System();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg){\n+ return RomDriver_PDS_RAM_Config(ram1Cfg,ram2Cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Reset_LP_RTC(void){\n+ return RomDriver_PDS_Reset_LP_RTC();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg){\n+ return RomDriver_PDS_Set_Flash_Pad_Pull_None(pinCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg){\n+ return RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast(pinCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set){\n+ return RomDriver_PDS_Set_GPIO_Pad_IntClr(set);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask){\n+ return RomDriver_PDS_Set_GPIO_Pad_IntMask(pad,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig){\n+ return RomDriver_PDS_Set_GPIO_Pad_IntMode(set,trig);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie){\n+ return RomDriver_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(pad,pu,pd,ie);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_Clock_Disable(void){\n+ return RomDriver_PDS_Set_LP_Clock_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_Clock_Enable(void){\n+ return RomDriver_PDS_Set_LP_Clock_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_RTC_CLK(uint8_t enable, uint16_t div){\n+ return RomDriver_PDS_Set_LP_RTC_CLK(enable,div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_Reset_Address(uint32_t addr){\n+ return RomDriver_PDS_Set_LP_Reset_Address(addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_System_CLK(PDS_LP_SYS_CLK_Type clkFreq){\n+ return RomDriver_PDS_Set_LP_System_CLK(clkFreq);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_LP_System_CLK_Div(uint8_t div){\n+ return RomDriver_PDS_Set_LP_System_CLK_Div(div);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_MCU0_Clock_Disable(void){\n+ return RomDriver_PDS_Set_MCU0_Clock_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_MCU0_Clock_Enable(void){\n+ return RomDriver_PDS_Set_MCU0_Clock_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_MCU0_Reset_Address(uint32_t addr){\n+ return RomDriver_PDS_Set_MCU0_Reset_Address(addr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_USB_Resume(void){\n+ return RomDriver_PDS_Set_USB_Resume();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Set_USB_Suspend(void){\n+ return RomDriver_PDS_Set_USB_Suspend();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Trim_RC32M(void){\n+ return RomDriver_PDS_Trim_RC32M();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Turn_Off_USB(void){\n+ return RomDriver_PDS_Turn_Off_USB();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady){\n+ return RomDriver_PDS_Turn_On_USB(waitReady);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad){\n+ return RomDriver_PDS_Get_GPIO_Pad_IntStatus(pad);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType){\n+ return RomDriver_PDS_Get_IntStatus(intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type PDS_Get_MM_System_Power_On_State(void){\n+ return RomDriver_PDS_Get_MM_System_Power_On_State();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin){\n+ return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){\n+ return RomDriver_SF_Cfg_Flash_Init(sel,pSfCtrlCfg,pBank2Cfg);\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID,pFlashCfg,group,bank);\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(flashID,pFlashCfg,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin){\n+ return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault){\n+ return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){\n+ return RomDriver_SF_Cfg_Sbus2_Flash_Init(sel,pBank2Cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Cfg_Flash_Identify(callFromFlash,flashPinCfg,restoreDefault,pFlashCfg,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Cfg_Flash_Identify_Ext(callFromFlash,flashPinCfg,restoreDefault,pFlashCfg,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type SF_Ctrl_GetBusyState(void){\n+ return RomDriver_SF_Ctrl_GetBusyState();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type SF_Ctrl_Is_AES_Enable(void){\n+ return RomDriver_SF_Ctrl_Is_AES_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void){\n+ return RomDriver_SF_Ctrl_Is_Sbus2_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t SF_Ctrl_Get_Clock_Delay(void){\n+ return RomDriver_SF_Ctrl_Get_Clock_Delay();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void){\n+ return RomDriver_SF_Ctrl_Get_Wrap_Queue_Value();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr){\n+ return RomDriver_SF_Ctrl_32bits_Addr_En(en32BitsAddr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Disable(void){\n+ return RomDriver_SF_Ctrl_AES_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Enable(void){\n+ return RomDriver_SF_Ctrl_AES_Enable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Enable_BE(void){\n+ return RomDriver_SF_Ctrl_AES_Enable_BE();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Enable_LE(void){\n+ return RomDriver_SF_Ctrl_AES_Enable_LE();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){\n+ return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addrOffset);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){\n+ return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addrOffset);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){\n+ return RomDriver_SF_Ctrl_AES_Set_Key(region,key,keyType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){\n+ return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,keyType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode){\n+ return RomDriver_SF_Ctrl_AES_Set_Mode(mode);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked){\n+ return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,startAddr,endAddr,locked);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){\n+ return RomDriver_SF_Ctrl_AES_XTS_Set_IV(region,iv,addrOffset);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){\n+ return RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE(region,iv,addrOffset);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){\n+ return RomDriver_SF_Ctrl_AES_XTS_Set_Key(region,key,keyType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){\n+ return RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE(region,key,keyType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg){\n+ return RomDriver_SF_Ctrl_Bank2_Enable(bank2Cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Disable(void){\n+ return RomDriver_SF_Ctrl_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Disable_Wrap_Access(uint8_t disable){\n+ return RomDriver_SF_Ctrl_Disable_Wrap_Access(disable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg){\n+ return RomDriver_SF_Ctrl_Enable(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){\n+ return RomDriver_SF_Ctrl_Flash2_Read_Icache_Set(cfg,cmdValid);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){\n+ return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmdValid);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock){\n+ return RomDriver_SF_Ctrl_Lock_Flash_Image_Offset(lock);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock){\n+ return RomDriver_SF_Ctrl_Remap_Set(remap,lock);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus2_Hold_Sram(void){\n+ return RomDriver_SF_Ctrl_Sbus2_Hold_Sram();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus2_Release_Sram(void){\n+ return RomDriver_SF_Ctrl_Sbus2_Release_Sram();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad){\n+ return RomDriver_SF_Ctrl_Sbus2_Replace(pad);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus2_Revoke_replace(void){\n+ return RomDriver_SF_Ctrl_Sbus2_Revoke_replace();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert){\n+ return RomDriver_SF_Ctrl_Sbus2_Set_Delay(clkDelay,rxClkInvert);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Ctrl_Sbus_Select_Bank(bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel){\n+ return RomDriver_SF_Ctrl_Select_Pad(sel);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg){\n+ return RomDriver_SF_Ctrl_SendCmd(cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Set_Clock_Delay(uint8_t delay){\n+ return RomDriver_SF_Ctrl_Set_Clock_Delay(delay);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay){\n+ return RomDriver_SF_Ctrl_Set_IO_Delay(pad,doDelay,diDelay,oeDelay);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner){\n+ return RomDriver_SF_Ctrl_Set_Owner(owner);\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){\n+ return RomDriver_SFlash_Blk32_Erase(flashCfg,blkNum);\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){\n+ return RomDriver_SFlash_Blk64_Erase(flashCfg,blkNum);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Chip_Erase(flashCfg);\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr){\n+ return RomDriver_SFlash_Erase(flashCfg,startaddr,endaddr);\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){\n+ return RomDriver_SFlash_Erase_Security_Register(pFlashCfg,pSecRegCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SFlash_IDbus_Read_Enable(flashCfg,ioMode,contRead,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len){\n+ return RomDriver_SFlash_Program(flashCfg,ioMode,addr,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){\n+ return RomDriver_SFlash_Program_Security_Register(pFlashCfg,pSecRegCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Qspi_Disable(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Qspi_Enable(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos){\n+ return RomDriver_SFlash_RCV_Enable(pFlashCfg,rCmd,wCmd,bitPos);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len){\n+ return RomDriver_SFlash_Read(flashCfg,ioMode,contRead,addr,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){\n+ return RomDriver_SFlash_Read_Reg(flashCfg,regIndex,regValue,regLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen){\n+ return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg,readRegCmd,regValue,regLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg){\n+ return RomDriver_SFlash_Read_Security_Register(pSecRegCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg,flashContRead,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum){\n+ return RomDriver_SFlash_Sector_Erase(flashCfg,secNum);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr){\n+ return RomDriver_SFlash_Set32BitsAddrMode(flashCfg,en32BitsAddr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode){\n+ return RomDriver_SFlash_SetSPIMode(mode);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,addr,len,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Software_Reset(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Write_Enable(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){\n+ return RomDriver_SFlash_Write_Reg(flashCfg,regIndex,regValue,regLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen){\n+ return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg,writeRegCmd,regValue,regLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Busy(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_DisableBurstWrap(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr){\n+ return RomDriver_SFlash_GetDeviceId(data,is32BitsAddr);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data){\n+ return RomDriver_SFlash_GetJedecId(flashCfg,data);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen){\n+ return RomDriver_SFlash_GetUniqueId(data,idLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_IDbus_Read_Disable(void){\n+ return RomDriver_SFlash_IDbus_Read_Disable();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){\n+ return RomDriver_SFlash_Init(pSfCtrlCfg,pBank2Cfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_Powerdown(void){\n+ return RomDriver_SFlash_Powerdown();\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Release_Powerdown(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Reset_Continue_Read(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_SetBurstWrap(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){\n+ return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){\n+ return RomDriver_UART_ApplyAbrResult(uartId,autoBaudDet);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud){\n+ return RomDriver_UART_AutoBaudDetection(uartId,autoBaud);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId){\n+ return RomDriver_UART_ClrRtsValue(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId){\n+ return RomDriver_UART_ClrTxValue(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_DeInit(UART_ID_Type uartId){\n+ return RomDriver_UART_DeInit(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct){\n+ return RomDriver_UART_Disable(uartId,direct);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct){\n+ return RomDriver_UART_Enable(uartId,direct);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg){\n+ return RomDriver_UART_FifoConfig(uartId,fifoCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width){\n+ return RomDriver_UART_GetBitWidth0X55(uartId,width);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg){\n+ return RomDriver_UART_Init(uartId,uartCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType){\n+ return RomDriver_UART_IntClear(uartId,intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask){\n+ return RomDriver_UART_IntMask(uartId,intType,intMask);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg){\n+ return RomDriver_UART_IrConfig(uartId,irCfg);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId){\n+ return RomDriver_UART_RxFifoClear(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len){\n+ return RomDriver_UART_SendData(uartId,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len){\n+ return RomDriver_UART_SendDataBlock(uartId,data,len);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError){\n+ return RomDriver_UART_SetAllowableError0X55(uartId,allowableError);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate){\n+ return RomDriver_UART_SetBaudRate(uartId,baudRate);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt){\n+ return RomDriver_UART_SetDeglitchCount(uartId,deglitchCnt);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity){\n+ return RomDriver_UART_SetRS485(uartId,enable,polarity);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId){\n+ return RomDriver_UART_SetRtsValue(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count){\n+ return RomDriver_UART_SetRxByteCount(uartId,count);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length){\n+ return RomDriver_UART_SetRxDataLength(uartId,length);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time){\n+ return RomDriver_UART_SetRxTimeoutValue(uartId,time);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length){\n+ return RomDriver_UART_SetTxDataLength(uartId,length);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_SetTxValue(UART_ID_Type uartId){\n+ return RomDriver_UART_SetTxValue(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId){\n+ return RomDriver_UART_TxFifoClear(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun){\n+ return RomDriver_UART_TxFreeRun(uartId,txFreeRun);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType){\n+ return RomDriver_UART_GetIntStatus(uartId,intType);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow){\n+ return RomDriver_UART_GetOverflowStatus(uartId,overflow);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId){\n+ return RomDriver_UART_GetRxBusBusyStatus(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId){\n+ return RomDriver_UART_GetTxBusBusyStatus(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){\n+ return RomDriver_UART_GetAutoBaudCount(uartId,autoBaudDet);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint16_t UART_GetRxByteCount(UART_ID_Type uartId){\n+ return RomDriver_UART_GetRxByteCount(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen){\n+ return RomDriver_UART_ReceiveData(uartId,data,maxLen);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t UART_GetRxFifoCount(UART_ID_Type uartId){\n+ return RomDriver_UART_GetRxFifoCount(uartId);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+uint8_t UART_GetTxFifoCount(UART_ID_Type uartId){\n+ return RomDriver_UART_GetTxFifoCount(uartId);\n+}\n+\n+#if 0\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg,startaddr,len,group,bank);\n+}\n+#endif\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg,is32BitsAddr,data,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg,data,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg,data,idLen,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg,addr,data,len,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_State_Restore(pFlashCfg,offset,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_State_Save(pFlashCfg,offset,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){\n+ return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg,addr,data,len,group,bank);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void XIP_SFlash_Opt_Enter(uint8_t *aesEnable){\n+ return RomDriver_XIP_SFlash_Opt_Enter(aesEnable);\n+}\n+\n+__ALWAYS_INLINE ATTR_TCM_SECTION\n+void XIP_SFlash_Opt_Exit(uint8_t aesEnable){\n+ return RomDriver_XIP_SFlash_Opt_Exit(aesEnable);\n+}\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..84af0f57ec7045a21b75e2afad0eb66a9db065e7\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c\n@@ -0,0 +1,3092 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_romapi_patch.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2021 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_romapi_patch.h\"\n+#include \"bl808_romdriver_e907.h\"\n+#error \"Not using romndriver now\"\n+\n+/* WiFi PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 0, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 2, /*!< pll_icp_5u */\n+ .clkpllRz = 3, /*!< pll_rz */\n+ .clkpllCz = 1, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 1, /*!< pll_r4_short */\n+ .clkpllC4En = 0, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */\n+ { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */\n+ { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* Audio PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */\n+ { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */\n+ { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */\n+};\n+\n+/* CPU PLL Config*/\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */\n+ .clkpllIcp1u = 1, /*!< pll_icp_1u */\n+ .clkpllIcp5u = 0, /*!< pll_icp_5u */\n+ .clkpllRz = 5, /*!< pll_rz */\n+ .clkpllCz = 2, /*!< pll_cz */\n+ .clkpllC3 = 2, /*!< pll_c3 */\n+ .clkpllR4Short = 0, /*!< pll_r4_short */\n+ .clkpllC4En = 1, /*!< pll_r4_en */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */\n+ .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */\n+ { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */\n+ { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* MIPI PLL Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 0, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &mipiPllBasicCfg_24M, 0x3E800 }, /*!< XTAL is 24M */\n+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is 32M */\n+ { &mipiPllBasicCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */\n+ { &mipiPllBasicCfg_40M, 0x38400 }, /*!< XTAL is 40M */\n+ { &mipiPllBasicCfg_26M, 0x39B13 }, /*!< XTAL is 26M */\n+ { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2100 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */\n+ { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */\n+ { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */\n+ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 4, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1400MCfg_24M, 0x3A555 }, /*!< XTAL is 24M */\n+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is 32M */\n+ { &uhsPll1400MCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1400MCfg_40M, 0x34800 }, /*!< XTAL is 40M */\n+ { &uhsPll1400MCfg_26M, 0x35D89 }, /*!< XTAL is 26M */\n+ { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1500 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1500MCfg_24M, 0x3E800 }, /*!< XTAL is 24M */\n+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is 32M */\n+ { &uhsPll1500MCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1500MCfg_40M, 0x38400 }, /*!< XTAL is 40M */\n+ { &uhsPll1500MCfg_26M, 0x39B13 }, /*!< XTAL is 26M */\n+ { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1600 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 5, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */\n+ { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */\n+ { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */\n+ { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */\n+ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 400 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */\n+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */\n+ { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */\n+ { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */\n+ { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */\n+ { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 667 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = {\n+ .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 1, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */\n+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */\n+ { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */\n+ { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */\n+ { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */\n+ { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 800 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 2, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */\n+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */\n+ { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */\n+ { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */\n+ { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */\n+ { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 1066 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = {\n+ .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 3, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */\n+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */\n+ { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */\n+ { &uhsPll1066BasicCfg_40M, 0x27F99 }, /*!< XTAL is 40M */\n+ { &uhsPll1066BasicCfg_26M, 0x29000 }, /*!< XTAL is 26M */\n+ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */\n+};\n+\n+/* uhs PLL 2000 Config*/\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = {\n+ .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */\n+};\n+const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */\n+ { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */\n+ { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */\n+ { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */\n+ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */\n+};\n+\n+static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = {\n+ { NULL }\n+};\n+#ifndef BFLB_USE_HAL_DRIVER\n+static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE };\n+\n+typedef struct\n+{\n+ uint32_t jedecID;\n+ char *name;\n+ const SPI_Flash_Cfg_Type *cfg;\n+} Flash_Info_t;\n+#endif\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3d,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 500,\n+ .timeE32k = 2000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 0,\n+ .cReadMode = 0xf0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={\n+ .resetCreadCmd=0xff,\n+ .resetCreadCmdSize=3,\n+ .mid=0x20,\n+\n+ .deBurstWrapCmd=0x77,\n+ .deBurstWrapCmdDmyClk=0x3,\n+ .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData=0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd=0x06,\n+ .wrEnableIndex=0x00,\n+ .wrEnableBit=0x01,\n+ .wrEnableReadRegLen=0x01,\n+\n+ .qeIndex=1,\n+ .qeBit=0x01,\n+ .qeWriteRegLen=0x01,\n+ .qeReadRegLen=0x1,\n+\n+ .busyIndex=0,\n+ .busyBit=0x00,\n+ .busyReadRegLen=0x1,\n+ .releasePowerDown=0xab,\n+\n+ .readRegCmd[0]=0x05,\n+ .readRegCmd[1]=0x35,\n+ .writeRegCmd[0]=0x01,\n+ .writeRegCmd[1]=0x31,\n+\n+ .fastReadQioCmd=0xeb,\n+ .frQioDmyClk=16/8,\n+ .cReadSupport=1,\n+ .cReadMode=0x20,\n+\n+ .burstWrapCmd=0x77,\n+ .burstWrapCmdDmyClk=0x3,\n+ .burstWrapDataMode=SF_CTRL_DATA_4_LINES,\n+ .burstWrapData=0x40,\n+ /*erase*/\n+ .chipEraseCmd=0xc7,\n+ .sectorEraseCmd=0x20,\n+ .blk32EraseCmd=0x52,\n+ .blk64EraseCmd=0xd8,\n+ /*write*/\n+ .pageProgramCmd=0x02,\n+ .qpageProgramCmd=0x32,\n+ .qppAddrMode=SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode=SF_CTRL_QIO_MODE,\n+ .clkDelay=1,\n+ .clkInvert=0x01,\n+\n+ .resetEnCmd=0x66,\n+ .resetCmd=0x99,\n+ .cRExit=0xff,\n+ .wrEnableWriteRegLen=0x00,\n+\n+ /*id*/\n+ .jedecIdCmd=0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd=0x0b,\n+ .frDmyClk=8/8,\n+ .qpiFastReadCmd =0x0b,\n+ .qpiFrDmyClk=8/8,\n+ .fastReadDoCmd=0x3b,\n+ .frDoDmyClk=8/8,\n+ .fastReadDioCmd=0xbb,\n+ .frDioDmyClk=0,\n+ .fastReadQoCmd=0x6b,\n+ .frQoDmyClk=8/8,\n+\n+ .qpiFastReadQioCmd=0xeb,\n+ .qpiFrQioDmyClk=16/8,\n+ .qpiPageProgramCmd=0x02,\n+ .writeVregEnableCmd=0x50,\n+\n+ /* qpi mode */\n+ .enterQpi=0x38,\n+ .exitQpi=0xff,\n+\n+ /*AC*/\n+ .timeEsector=400,\n+ .timeE32k=1600,\n+ .timeE64k=2000,\n+ .timePagePgm=5,\n+ .timeCe=33000,\n+ .pdDelay=3,\n+ .qeData=0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0x20,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = 0x24,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0x20,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 300,\n+ .timeE32k = 1200,\n+ .timeE64k = 1200,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 500,\n+ .timeE32k = 2000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc2,\n+\n+ .deBurstWrapCmd = 0xC0,\n+ .deBurstWrapCmdDmyClk = 0x00,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .deBurstWrapData = 0x10,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 0,\n+ .qeBit = 0x06,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x15,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xA5,\n+\n+ .burstWrapCmd = 0xC0,\n+ .burstWrapCmdDmyClk = 0x00,\n+ .burstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .burstWrapData = 0x02,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x38,\n+ .qppAddrMode = SF_CTRL_ADDR_4_LINES,\n+\n+ .ioMode = (SF_CTRL_QIO_MODE | 0x20),\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {\n+ {\n+ .jedecID = 0x1760c8,\n+ //.name=\"GD_LQ64E_64_18\",\n+ .cfg = &flashCfg_GD_LQ64E,\n+ },\n+ {\n+ .jedecID = 0x1760ef,\n+ //.name=\"WB_64JW_64_18\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID=0x144020,\n+ //.name=\"XM_25QH80_80_33\",\n+ .cfg=&flashCfg_XM25QH16,\n+ },\n+ {\n+ .jedecID=0x154020,\n+ //.name=\"XM_25QH16_16_33\",\n+ .cfg=&flashCfg_XM25QH16,\n+ },\n+ {\n+ .jedecID=0x164020,\n+ //.name=\"XM_25QH32_32_33\",\n+ .cfg=&flashCfg_XM25QH16,\n+ },\n+ {\n+ .jedecID=0x174020,\n+ //.name=\"XM_25QH64_64_33\",\n+ .cfg=&flashCfg_XM25QH16,\n+ },\n+ {\n+ .jedecID = 0x17400B,\n+ //.name=\"XT_25F64B_32_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1570ef,\n+ //.name=\"Winb_16JV_16_33\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1940ef,\n+ //.name=\"Winb_256FV_128_33\",\n+ .cfg = &flashCfg_Winb_256FV,\n+ },\n+ {\n+ .jedecID = 0x1860c8,\n+ //.name=\"GD_LQ128E_64_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x15345e,\n+ //.name=\"ZB_WQ16A_16_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x15405e,\n+ //.name=\"ZB_Q16B_16_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x16405e,\n+ //.name=\"ZB_Q32B_32_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x17405e,\n+ //.name=\"ZB_Q64B_64_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x15605E,\n+ //.name=\"ZB_VQ16\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x3925C2,\n+ //.name=\"MX_25U256_256_33\",\n+ .cfg = &flashCfg_Mxic_25L256,\n+ },\n+ {\n+ .jedecID = 0x1740c8,\n+ //.name=\"GD_Q64E_64_18\",\n+ .cfg = &flashCfg_XM25QH16,\n+ }\n+};\n+\n+static void UART_IntHandler(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t maskVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_INT_STS);\n+ maskVal = BL_RD_REG(UARTx, UART_INT_MASK);\n+\n+ /* Length of uart tx data transfer arrived interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_END]();\n+ }\n+ }\n+\n+ /* Length of uart rx data transfer arrived interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_END]();\n+ }\n+ }\n+\n+ /* Tx fifo ready interrupt,auto-cleared when data is pushed */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* Rx fifo ready interrupt,auto-cleared when data is popped */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* Rx time-out interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RTO]();\n+ }\n+ }\n+\n+ /* Rx parity check error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_PCE]();\n+ }\n+ }\n+\n+ /* Tx fifo overflow/underflow error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_FER]();\n+ }\n+ }\n+\n+ /* Rx fifo overflow/underflow error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_FER]();\n+ }\n+ }\n+\n+ /* Rx lin mode sync field error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_LSE]();\n+ }\n+ }\n+\n+ /* Rx byte count reached interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_BCR]();\n+ }\n+ }\n+\n+ /* Rx auto baud rate detection finish interrupt using start bit */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_STARTBIT]();\n+ }\n+ }\n+\n+ /* Rx auto baud rate detection finish interrupt using codeword 0x55 */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_0X55]();\n+ }\n+ }\n+}\n+\n+void UART1_IRQHandler(void)\n+{\n+ UART_IntHandler(UART1_ID);\n+}\n+\n+void UART0_IRQHandler(void)\n+{\n+ UART_IntHandler(UART0_ID);\n+}\n+\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Install uart interrupt callback function\n+ *\n+ * @param uartId: UART ID type\n+ * @param intType: UART interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_INT_TYPE(intType));\n+\n+ uartIntCbfArra[uartId][intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+//CLOCK\n+//EFUSE\n+//PDS\n+/****************************************************************************/ /**\n+ * @brief PDS turn on USB\n+ *\n+ * @param waitReady : wait turn on usb finish\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */\n+ /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */\n+ /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */\n+ /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */\n+ /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */\n+ /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */\n+ /* #1.2ms; wait UCLK */\n+ /* wait(soc616_b0.usb_uclk); */\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);\n+ BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);\n+\n+ /* greater than 5T */\n+ arch_delay_us(1);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ /* greater than 5T */\n+ arch_delay_us(1);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ /* wait UCLK 1.2ms */\n+ arch_delay_ms(3);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);\n+ BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);\n+\n+ if (waitReady) {\n+ arch_delay_ms(2);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+//HBN\n+\n+/****************************************************************************/ /**\n+ * @brief Power on XTAL 32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);\n+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);\n+\n+ /* Delay >1s */\n+ arch_delay_us(1100);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Power off XTAL 32K\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);\n+ BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/**\n+ * @brief Power Off RC32K in all state\n+ *\n+ * @return BL_Err_Type\n+ */\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_All_State(void)\n+{\n+ int32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);\n+ HBN_Power_Off_RC32K();\n+ return SUCCESS;\n+}\n+\n+/**\n+ * @brief Power Off RC32K In power off state\n+ *\n+ * @return BL_Err_Type\n+ */\n+BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_In_Poff(void)\n+{\n+ int32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K);\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal);\n+ HBN_Power_Off_RC32K();\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************\n+ * @brief HBN set ldo11_Rtc voltage out\n+ *\n+ * @param ldoLevel: LDO11_Rtc volatge level\n+ * 0:0.60V 1:0.65V 2:0.70V 3:0.75V\n+ * 4:0.80V 5:0.85V 6:0.9V 7:0.95V\n+ * 8:1.0V 9:1.05V 10:1.1V 11:1.15V,\n+ * 12:1.2V 13:1.25V 14:1.3V 15:1.35V\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+ *******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ HBN_RTC_MISC_Type rtcMiscCfg;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);\n+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;\n+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN set ldo11 all voltage out, not include dcdc11\n+ *\n+ * @param ldoLevel: LDO volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+ * @note not support LDO11_Rtc 0.65v & 0.6v\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)\n+{\n+ uint32_t tmpVal;\n+ HBN_RTC_MISC_Type rtcMiscCfg;\n+\n+ CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);\n+ BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);\n+\n+ HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg);\n+ rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel;\n+ HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get RTC misc config\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t *pCfg = (uint32_t *)cfg;\n+\n+ if (!cfg) {\n+ return ERROR;\n+ }\n+\n+ /* read [31:19] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC);\n+\n+ /* use [30:19] */\n+ *pCfg = tmpVal;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set RTC misc config\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (!cfg) {\n+ return ERROR;\n+ }\n+\n+ /* read [31:19] */\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC, ((*(uint32_t *)cfg)<<1));\n+ BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable ACOMP0 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);\n+ tmpVal2 = tmpVal2 | (1 << edge);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable ACOMP0 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);\n+ tmpVal2 = tmpVal2 & (~(1 << edge));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN enable ACOMP1 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);\n+ tmpVal2 = tmpVal2 | (1 << edge);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief HBN disable ACOMP1 interrupt\n+ *\n+ * @param edge: HBN acomp interrupt edge type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+ tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);\n+ tmpVal2 = tmpVal2 & (~(1 << edge));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);\n+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+//AON\n+/****************************************************************************/ /**\n+ * @brief AON set DCDC11_Top voltage out\n+ *\n+ * @param dcdcLevel: DCDC11_Top volatge level\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel));\n+\n+ tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel);\n+ BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+/****************************************************************************/ /**\n+ * @brief delay us\n+ *\n+ * @param[in] core: systemcoreclock\n+ *\n+ * @param[in] cnt: delay cnt us\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)\n+{\n+ volatile uint32_t divVal = loopT;\n+ volatile uint32_t speed = 0;\n+ volatile uint32_t cycNum = 0;\n+\n+ /* 1M=100K*10, so multiple is 10 */\n+ /* loop function take 4 instructions, so instructionNum is 4 */\n+ /* divVal = multiple*instructionNum */\n+\n+ if (core >= 1 * 1000 * 1000) {\n+ /* CPU clock >= 1MHz */\n+ speed = core / (100 * 1000);\n+ cycNum = speed * cnt;\n+ cycNum = cycNum / 10;\n+ cycNum = cycNum / divVal;\n+ /* cycNum >= 0 */\n+ } else {\n+ /* CPU clock < 1MHz */\n+ speed = core / 1000;\n+ cycNum = speed * cnt;\n+ cycNum = cycNum / 1000;\n+ cycNum = cycNum / divVal;\n+ /* cycNum >= 0 */\n+ }\n+\n+ if (!cycNum) {\n+ return;\n+ }\n+\n+ __asm__ __volatile__(\n+ \"mv a4,%0\\n\\t\"\n+ \"li a5,0x0\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \".align 4\\n\\t\"\n+ \"1 :\\n\"\n+ \"beq a5,a4,2f\\n\\t\"\n+ \"addi a5,a5,0x1\\n\\t\"\n+ \"lui a3,0xF0000\\n\\t\"\n+ \"lw a3,0(a3)\\n\\t\"\n+ \"j 1b\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"nop\\n\\t\"\n+ \"2 :\\n\\t\"\n+ \"nop\\n\"\n+ : /* output */\n+ : \"r\"(cycNum) /* input */\n+ : \"a3\", \"a4\", \"a5\" /* destruct description */\n+ );\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief delay us\n+ *\n+ * @param[in] cnt: delay cnt us\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)\n+{\n+ GLB_CORE_ID_Type coreID;\n+ uint32_t coreFreq;\n+ uint32_t loopTick = 5;\n+ uint32_t m0Cyc00[] = { 46, 46, 77, 85 };\n+ uint32_t m0Cyc10[] = { 10, 10, 77, 85 };\n+ uint32_t m0Cyc11[] = { 10, 10, 77, 85 };\n+ uint32_t d0Cyc00[] = { 5, 5, 62, 34 };\n+ uint32_t d0Cyc11[] = { 5, 5, 13, 13 };\n+ uint32_t lpCyc00[] = { 6, 6, 55, 85 };\n+ uint32_t *pCyc = NULL;\n+ uint32_t iCacheEn = 1;\n+ uint32_t dCacheEn = 1;\n+\n+ /* requirement: icache enable && dcache enable */\n+ /* otherwise the latency depends on the code address */\n+\n+ coreID = GLB_Get_Core_Type();\n+\n+ if (GLB_CORE_ID_M0 == coreID) {\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);\n+#ifdef __RV32\n+ iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos;\n+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;\n+#endif\n+ if (iCacheEn && dCacheEn) {\n+ pCyc = m0Cyc11;\n+ } else if (iCacheEn && !dCacheEn) {\n+ pCyc = m0Cyc10;\n+ } else if (!iCacheEn && !dCacheEn) {\n+ pCyc = m0Cyc00;\n+ } else {\n+ pCyc = m0Cyc11;\n+ }\n+ } else if (GLB_CORE_ID_D0 == coreID) {\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK);\n+#ifdef __RV64\n+ iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos;\n+ dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;\n+#endif\n+ if (iCacheEn && dCacheEn) {\n+ pCyc = d0Cyc11;\n+ } else if (!iCacheEn && !dCacheEn) {\n+ pCyc = d0Cyc00;\n+ } else {\n+ pCyc = d0Cyc11;\n+ }\n+ } else if (GLB_CORE_ID_LP == coreID) {\n+ coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK);\n+ pCyc = lpCyc00;\n+ } else {\n+ coreFreq = 32 * 1000 * 1000;\n+ pCyc = lpCyc00;\n+ }\n+\n+ switch (((uint32_t)&ASM_Delay_Us) >> 24) {\n+ case 0x22:\n+ loopTick = pCyc[0];\n+ break;\n+ case 0x62:\n+ loopTick = pCyc[0];\n+ break;\n+ case 0x3F:\n+ loopTick = pCyc[2];\n+ break;\n+ case 0x3E:\n+ loopTick = pCyc[3];\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);\n+\n+ ASM_Delay_Us(coreFreq, cnt, loopTick);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief delay ms\n+ *\n+ * @param[in] cnt: delay cnt ms\n+ *\n+ * @return none\n+ *\n+ *******************************************************************************/\n+void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)\n+{\n+ uint32_t i = 0;\n+ uint32_t count = 0;\n+\n+ if (cnt >= 1024) {\n+ /* delay (n*1024) ms */\n+ for (i = 0; i < (cnt / 1024); i++) {\n+ arch_delay_us(1024 * 1000);\n+ }\n+ }\n+\n+ count = cnt & 0x3FF;\n+\n+ if (count) {\n+ /* delay (1-1023)ms */\n+ arch_delay_us(count * 1000);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out0 select\n+ *\n+ * @param clkOutType: chip clock out0 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out0 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out1 select\n+ *\n+ * @param clkOutType: chip clock out1 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out1 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out2 select\n+ *\n+ * @param clkOutType: chip clock out2 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out2 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief chip clock out3 select\n+ *\n+ * @param clkOutType: chip clock out3 output type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);\n+ /* set clk out3 output enable */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);\n+ BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+//FLASH\n+\n+/****************************************************************************/ /**\n+ * @brief GLB power on PLL\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param cfg: GLB PLL configuration\n+ * @param waitStable: wait PLL clock stable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ /* unknown */\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* Step1:config parameter */\n+ /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);\n+\n+ /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);\n+\n+ /* cfg4:Set aupll_sel_sample_clk */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);\n+\n+ /* cfg5:Set aupll_vco_speed */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+\n+ /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);\n+\n+ /* Step2:config pu */\n+ /* cfg0 : pu_aupll_sfreg=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* cfg0 : pu_wifipll=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* delay > 2us */\n+ arch_delay_us(3);\n+\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);\n+\n+ /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */\n+ if (GLB_WAC_PLL_AUPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) {\n+ /* 451.548 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14);\n+ } else {\n+ /* 442.368 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+ }\n+\n+ /* Step4:enable output clock */\n+ /* wifipll : cfg5, wifipll_vco_div3_en=1 */\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);\n+ }\n+ /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);\n+ if (GLB_WAC_PLL_WIFIPLL == pllType) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1);\n+ }\n+ /* cfg8 : wifipll/aupll/cpupll clock enable */\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6);\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);\n+\n+ if (waitStable) {\n+ /* Wait 1.5*30us */\n+ arch_delay_us(45);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB wifi audio cpu PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_WAC_PLL_WIFIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_AUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_WAC_PLL_CPUPLL:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) {\n+ /* wifipll_refclk_sel different from other's pll, 1 means xtal */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ }\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB mipi uhs PLL ref clock select\n+ *\n+ * @param pllType: PLL XTAL type\n+ * @param refClk: PLL ref clock select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType));\n+ CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));\n+\n+ switch (pllType) {\n+ case GLB_MU_PLL_MIPIPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ case GLB_MU_PLL_UHSPLL:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET;\n+ break;\n+ default:\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+ break;\n+ }\n+\n+ /* xxxpll_refclk_sel */\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure WIFIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure AUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure CPUPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL);\n+ GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk);\n+ GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure MIPIPLL clock div\n+ *\n+ * @param divEn: div enable\n+ * @param divRatio: div ratio\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio)\n+{\n+ uint32_t REG_PLL_BASE_ADDRESS = 0;\n+ uint32_t tmpVal = 0;\n+\n+ REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET;\n+\n+ tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio);\n+ BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reconfigure UHSPLL clock\n+ *\n+ * @param xtalType: XTAL frequency type\n+ * @param pllCfg: PLL configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)\n+{\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+\n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GLB set display clock\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ * @param srcClk: source clock type\n+ * @param evenDiv: divider in even number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t evenNum = 0;\n+\n+ CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk));\n+ CHECK_PARAM((evenDiv <= 0x7F));\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ if ((evenDiv >= 8) && (evenDiv <= 126)) {\n+ evenNum = evenDiv & ~(1 << 0);\n+ } else {\n+ evenNum = evenDiv;\n+ }\n+\n+ tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);\n+ }\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum);\n+ BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one 32K block\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param blkNum: flash 32K block number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)\n+{\n+ uint32_t cnt = 0;\n+ uint8_t is32BitsAddr = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ BL_Err_Type stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8);\n+ flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum);\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > flashCfg->timeE32k * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one region\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param startaddr: start address to erase\n+ * @param endaddr: end address(include this address) to erase\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr)\n+{\n+ uint32_t len = 0;\n+ uint32_t eraseLen = 0;\n+ BL_Err_Type ret = SUCCESS;\n+\n+ if (startaddr > endaddr) {\n+ return ERROR;\n+ }\n+\n+ while (startaddr <= endaddr) {\n+ len = endaddr - startaddr + 1;\n+\n+ if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID &&\n+ (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 &&\n+ len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) {\n+ /* 64K margin address,and length > 64K-sector size, erase one first */\n+ ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE);\n+ eraseLen = BFLB_SPIFLASH_BLK64K_SIZE;\n+ } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID &&\n+ (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&\n+ len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) {\n+ /* 32K margin address,and length > 32K-sector size, erase one first */\n+ ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE);\n+ eraseLen = BFLB_SPIFLASH_BLK32K_SIZE;\n+ } else {\n+ /* Sector erase */\n+ startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1)));\n+ ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024);\n+ eraseLen = flashCfg->sectorSize * 1024;\n+ }\n+\n+ startaddr += eraseLen;\n+\n+ if (ret != SUCCESS) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one region\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param startaddr: start address to erase\n+ * @param len: data length to erase\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return stat;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash config according to flash ID patch\n+ *\n+ * @param flashID: Flash ID\n+ * @param pFlashCfg: Flash config pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t i;\n+ uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];\n+ uint32_t crc, *pCrc;\n+ uint32_t xipOffset;\n+ char flashCfgMagic[] = \"FCFG\";\n+\n+ if (flashID == 0) {\n+ xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(0, group, bank);\n+ XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank);\n+\n+ if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) {\n+ crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));\n+\n+ if (*pCrc == crc) {\n+ ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ } else {\n+ if(RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank) == SUCCESS){\n+ return SUCCESS;\n+ }\n+ for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {\n+ if (flashInfos[i].jedecID == flashID) {\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Identify one flash patch\n+ *\n+ * @param callFromFlash: code run at flash or ram\n+ * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config\n+ * @param restoreDefault: Wether restore default flash GPIO config\n+ * @param pFlashCfg: Flash config pointer\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return Flash ID\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg,\n+ uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t jdecId = 0;\n+ uint32_t i = 0;\n+ uint32_t ret = 0;\n+\n+ ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank);\n+ if(callFromFlash){\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank);\n+ }\n+ if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){\n+ return ret;\n+ }\n+\n+ jdecId = (ret&0xffffff);\n+ for(i=0; i<sizeof(flashInfos)/sizeof(flashInfos[0]); i++){\n+ if(flashInfos[i].jedecID == jdecId){\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg,sizeof(SPI_Flash_Cfg_Type));\n+ break;\n+ }\n+ }\n+ if(i == sizeof(flashInfos)/sizeof(flashInfos[0])){\n+ return jdecId;\n+ }else{\n+ return (jdecId|BFLB_FLASH_ID_VALID_FLAG);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get Xtal value\n+ *\n+ * @param xtalVal:Xtal value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Value(uint32_t *xtalVal)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t xtalType = 0;\n+\n+ if (NULL == xtalVal) {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);\n+ if ((tmpVal & HBN_XTAL_FLAG_MASK) == HBN_XTAL_FLAG_VALUE) {\n+ xtalType = (tmpVal & 0xff);\n+ switch(xtalType){\n+ case GLB_XTAL_NONE:\n+ *xtalVal = 0;\n+ break;\n+ case GLB_XTAL_24M:\n+ *xtalVal = 24000000;\n+ break;\n+ case GLB_XTAL_32M:\n+ *xtalVal = 32000000;\n+ break;\n+ case GLB_XTAL_38P4M:\n+ *xtalVal = 38400000;\n+ break;\n+ case GLB_XTAL_40M:\n+ *xtalVal = 40000000;\n+ break;\n+ case GLB_XTAL_26M:\n+ *xtalVal = 26000000;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ *xtalVal = 32000000;\n+ break;\n+ default :\n+ *xtalVal = 0;\n+ break;\n+ }\n+ return SUCCESS;\n+ }\n+\n+ *xtalVal = 0;\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set L2SRAM\n+ *\n+ * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable\n+ * @param vramSramRel: make l2_vram writable\n+ * @param dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable\n+ * @param blaiSramRel: make blai_64k0,blai_64k1 writable\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ /* Make the above settings effective */\n+ tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1);\n+ BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..174b77ac7dbe9a446c542a9ce5a0d1ecff9d0aa9\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c\n@@ -0,0 +1,623 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_romdriver_e907.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2021 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+ \n+#include \"bl808_romdriver_e907.h\"\n+#include <string.h>\n+\n+/** @addtogroup BL808_Periph_Driver\n+ * @{\n+ */\n+\n+/** @defgroup ROMDRIVER\n+ * @brief ROMDRIVER common functions\n+ * @{\n+ */\n+\n+/** @defgroup ROMDRIVER_Private_Type\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Private_Type*/\n+\n+/** @defgroup ROMDRIVER_Private_Defines\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Private_Defines */\n+\n+/** @defgroup ROMDRIVER_Private_Variables\n+ * @{\n+ */ \n+\n+/*@} end of group ROMDRIVER_Private_Variables */\n+\n+/** @defgroup ROMDRIVER_Global_Variables\n+ * @{\n+ */ \n+ \n+\n+uint32_t const romDriverTable[]={\n+ 0x08080001,\n+ 0x00000000,\n+ 0x00000000,\n+ 0x00000000,\n+\n+\n+ [ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0,\n+ [ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0,\n+ [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG,\n+ [ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF,\n+ [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG,\n+ [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg,\n+ [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL,\n+ [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG,\n+ [ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF,\n+ [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG,\n+ [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg,\n+ [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL,\n+ [ROM_API_INDEX_AON_Set_DCDC11_Top_Vout] = (uint32_t)AON_Set_DCDC11_Top_Vout,\n+ [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,\n+ [ROM_API_INDEX_AON_Trim_DCDC11_Vout] = (uint32_t)AON_Trim_DCDC11_Vout,\n+ [ROM_API_INDEX_AON_Trim_DCDC18_Vout] = (uint32_t)AON_Trim_DCDC18_Vout,\n+ [ROM_API_INDEX_AON_Trim_USB20_RCAL] = (uint32_t)AON_Trim_USB20_RCAL,\n+ [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode,\n+\n+ [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us,\n+\n+ [ROM_API_INDEX_arch_delay_ms] = (uint32_t)arch_delay_ms,\n+ [ROM_API_INDEX_arch_delay_us] = (uint32_t)arch_delay_us,\n+\n+ [ROM_API_INDEX_EF_Ctrl_Crc_Result] = (uint32_t)EF_Ctrl_Crc_Result,\n+ [ROM_API_INDEX_EF_Ctrl_Get_Customer_PIDVID] = (uint32_t)EF_Ctrl_Get_Customer_PIDVID,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Chip_ID] = (uint32_t)EF_Ctrl_Read_Chip_ID,\n+ [ROM_API_INDEX_EF_Ctrl_Read_MAC_Address] = (uint32_t)EF_Ctrl_Read_MAC_Address,\n+ [ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Raw] = (uint32_t)EF_Ctrl_Read_MAC_Address_Raw,\n+ [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done,\n+ [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy,\n+ [ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy] = (uint32_t)EF_Ctrl_Crc_Is_Busy,\n+ [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,\n+ [ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero] = (uint32_t)EF_Ctrl_Is_All_Bits_Zero,\n+ [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear,\n+ [ROM_API_INDEX_EF_Ctrl_Crc_Enable] = (uint32_t)EF_Ctrl_Crc_Enable,\n+ [ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden] = (uint32_t)EF_Ctrl_Crc_Set_Golden,\n+ [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0,\n+ [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1] = (uint32_t)EF_Ctrl_Load_Efuse_R1,\n+ [ROM_API_INDEX_EF_Ctrl_Program_Direct] = (uint32_t)EF_Ctrl_Program_Direct,\n+ [ROM_API_INDEX_EF_Ctrl_Program_Direct_R0] = (uint32_t)EF_Ctrl_Program_Direct_R0,\n+ [ROM_API_INDEX_EF_Ctrl_Program_Direct_R1] = (uint32_t)EF_Ctrl_Program_Direct_R1,\n+ [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0,\n+ [ROM_API_INDEX_EF_Ctrl_Program_Efuse_1] = (uint32_t)EF_Ctrl_Program_Efuse_1,\n+ [ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim] = (uint32_t)EF_Ctrl_Read_ADC_Gain_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_AES_Key] = (uint32_t)EF_Ctrl_Read_AES_Key,\n+ [ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim] = (uint32_t)EF_Ctrl_Read_DCDC11_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim] = (uint32_t)EF_Ctrl_Read_DCDC18_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd] = (uint32_t)EF_Ctrl_Read_Dbg_Pwd,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Device_Info] = (uint32_t)EF_Ctrl_Read_Device_Info,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Direct] = (uint32_t)EF_Ctrl_Read_Direct,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Direct_R0] = (uint32_t)EF_Ctrl_Read_Direct_R0,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Direct_R1] = (uint32_t)EF_Ctrl_Read_Direct_R1,\n+ [ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim] = (uint32_t)EF_Ctrl_Read_LDO18FLASH_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim] = (uint32_t)EF_Ctrl_Read_LDO18IO_Vout_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot] = (uint32_t)EF_Ctrl_Read_Secure_Boot,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg] = (uint32_t)EF_Ctrl_Read_Secure_Cfg,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage] = (uint32_t)EF_Ctrl_Read_Sw_Usage,\n+ [ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim] = (uint32_t)EF_Ctrl_Read_TSEN_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim] = (uint32_t)EF_Ctrl_Read_USB20RCAL_Trim,\n+ [ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M] = (uint32_t)EF_Ctrl_Read_Xtal_Trim_RC32M,\n+ [ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key] = (uint32_t)EF_Ctrl_Readlock_AES_Key,\n+ [ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd] = (uint32_t)EF_Ctrl_Readlock_Dbg_Pwd,\n+ [ROM_API_INDEX_EF_Ctrl_Set_sf_key_re_sel] = (uint32_t)EF_Ctrl_Set_sf_key_re_sel,\n+ [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,\n+ [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_1,\n+ [ROM_API_INDEX_EF_Ctrl_Write_AES_Key] = (uint32_t)EF_Ctrl_Write_AES_Key,\n+ [ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd] = (uint32_t)EF_Ctrl_Write_Dbg_Pwd,\n+ [ROM_API_INDEX_EF_Ctrl_Write_MAC_Address] = (uint32_t)EF_Ctrl_Write_MAC_Address,\n+ [ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot] = (uint32_t)EF_Ctrl_Write_Secure_Boot,\n+ [ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg] = (uint32_t)EF_Ctrl_Write_Secure_Cfg,\n+ [ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage] = (uint32_t)EF_Ctrl_Write_Sw_Usage,\n+ [ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key] = (uint32_t)EF_Ctrl_Writelock_AES_Key,\n+ [ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd] = (uint32_t)EF_Ctrl_Writelock_Dbg_Pwd,\n+ [ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address] = (uint32_t)EF_Ctrl_Writelock_MAC_Address,\n+ [ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage] = (uint32_t)EF_Ctrl_Writelock_Sw_Usage,\n+\n+ [ROM_API_INDEX_GLB_AHB_DSP_Software_Reset] = (uint32_t)GLB_AHB_DSP_Software_Reset,\n+ [ROM_API_INDEX_GLB_AHB_MCU_Software_Reset] = (uint32_t)GLB_AHB_MCU_Software_Reset,\n+ [ROM_API_INDEX_GLB_BMX_TO_Init] = (uint32_t)GLB_BMX_TO_Init,\n+ [ROM_API_INDEX_GLB_Clr_BMX_TO_Status] = (uint32_t)GLB_Clr_BMX_TO_Status,\n+ [ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate] = (uint32_t)GLB_Clr_EMI_Reset_Gate,\n+ [ROM_API_INDEX_GLB_Config_AUDIO_PLL] = (uint32_t)GLB_Config_AUDIO_PLL,\n+ [ROM_API_INDEX_GLB_Config_CPU_PLL] = (uint32_t)GLB_Config_CPU_PLL,\n+ [ROM_API_INDEX_GLB_Config_MIPI_PLL] = (uint32_t)GLB_Config_MIPI_PLL,\n+ [ROM_API_INDEX_GLB_Config_MIPI_PLL_Div] = (uint32_t)GLB_Config_MIPI_PLL_Div,\n+ [ROM_API_INDEX_GLB_Config_UHS_PLL] = (uint32_t)GLB_Config_UHS_PLL,\n+ [ROM_API_INDEX_GLB_Config_WIFI_PLL] = (uint32_t)GLB_Config_WIFI_PLL,\n+ [ROM_API_INDEX_GLB_DSP0_Clock_Disable] = (uint32_t)GLB_DSP0_Clock_Disable,\n+ [ROM_API_INDEX_GLB_DSP0_Clock_Enable] = (uint32_t)GLB_DSP0_Clock_Enable,\n+ [ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus] = (uint32_t)GLB_DSP_Clr_MCU_IntStatus,\n+ [ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset] = (uint32_t)GLB_DSP_Codec_Sub_Reset,\n+ [ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset] = (uint32_t)GLB_DSP_DSP2_Sub_Reset,\n+ [ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset] = (uint32_t)GLB_DSP_Image_Sensor_Reset,\n+ [ROM_API_INDEX_GLB_DSP_Peripheral_Reset] = (uint32_t)GLB_DSP_Peripheral_Reset,\n+ [ROM_API_INDEX_GLB_DSP_SW_System_Reset] = (uint32_t)GLB_DSP_SW_System_Reset,\n+ [ROM_API_INDEX_GLB_DSP_Set_LP_IntEn] = (uint32_t)GLB_DSP_Set_LP_IntEn,\n+ [ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask] = (uint32_t)GLB_DSP_Set_MCU_IntMask,\n+ [ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type] = (uint32_t)GLB_Get_Auto_Calc_Xtal_Type,\n+ [ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div] = (uint32_t)GLB_Get_DSP_PBCLK_Div,\n+ [ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div] = (uint32_t)GLB_Get_DSP_System_CLK_Div,\n+ [ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div] = (uint32_t)GLB_Get_MCU_System_CLK_Div,\n+ [ROM_API_INDEX_GLB_Halt_CPU] = (uint32_t)GLB_Halt_CPU,\n+ [ROM_API_INDEX_GLB_IR_LED_Driver_Disable] = (uint32_t)GLB_IR_LED_Driver_Disable,\n+ [ROM_API_INDEX_GLB_IR_LED_Driver_Enable] = (uint32_t)GLB_IR_LED_Driver_Enable,\n+ [ROM_API_INDEX_GLB_IR_RX_GPIO_Sel] = (uint32_t)GLB_IR_RX_GPIO_Sel,\n+ [ROM_API_INDEX_GLB_Invert_ETH_REF_O_CLK] = (uint32_t)GLB_Invert_ETH_REF_O_CLK,\n+ [ROM_API_INDEX_GLB_Invert_ETH_RX_CLK] = (uint32_t)GLB_Invert_ETH_RX_CLK,\n+ [ROM_API_INDEX_GLB_Invert_ETH_TX_CLK] = (uint32_t)GLB_Invert_ETH_TX_CLK,\n+ [ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus] = (uint32_t)GLB_MCU_Clr_DSP_IntStatus,\n+ [ROM_API_INDEX_GLB_MCU_SW_System_Reset] = (uint32_t)GLB_MCU_SW_System_Reset,\n+ [ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask] = (uint32_t)GLB_MCU_Set_DSP_IntMask,\n+ [ROM_API_INDEX_GLB_Output_EMAC_CLK] = (uint32_t)GLB_Output_EMAC_CLK,\n+ [ROM_API_INDEX_GLB_PER_Clock_Gate] = (uint32_t)GLB_PER_Clock_Gate,\n+ [ROM_API_INDEX_GLB_PER_Clock_UnGate] = (uint32_t)GLB_PER_Clock_UnGate,\n+ [ROM_API_INDEX_GLB_PLL_CGEN_Clock_Gate] = (uint32_t)GLB_PLL_CGEN_Clock_Gate,\n+ [ROM_API_INDEX_GLB_PLL_CGEN_Clock_UnGate] = (uint32_t)GLB_PLL_CGEN_Clock_UnGate,\n+ [ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable] = (uint32_t)GLB_Platform_Wakeup_PDS_Enable,\n+ [ROM_API_INDEX_GLB_Power_Off_MU_PLL] = (uint32_t)GLB_Power_Off_MU_PLL,\n+ [ROM_API_INDEX_GLB_Power_Off_WAC_PLL] = (uint32_t)GLB_Power_Off_WAC_PLL,\n+ [ROM_API_INDEX_GLB_Power_On_MU_PLL] = (uint32_t)GLB_Power_On_MU_PLL,\n+ [ROM_API_INDEX_GLB_Power_On_WAC_PLL] = (uint32_t)GLB_Power_On_WAC_PLL,\n+ [ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK] = (uint32_t)GLB_Power_On_XTAL_And_PLL_CLK,\n+ [ROM_API_INDEX_GLB_Release_CPU] = (uint32_t)GLB_Release_CPU,\n+ [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset,\n+ [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset,\n+ [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset,\n+ [ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock] = (uint32_t)GLB_Sel_DSP_TMR_GPIO_Clock,\n+ [ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock] = (uint32_t)GLB_Sel_MCU_TMR_GPIO_Clock,\n+ [ROM_API_INDEX_GLB_Set_ADC_CLK] = (uint32_t)GLB_Set_ADC_CLK,\n+ [ROM_API_INDEX_GLB_Set_Audio_ADC_CLK] = (uint32_t)GLB_Set_Audio_ADC_CLK,\n+ [ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK] = (uint32_t)GLB_Set_Audio_AUTO_CLK,\n+ [ROM_API_INDEX_GLB_Set_Audio_DAC_CLK] = (uint32_t)GLB_Set_Audio_DAC_CLK,\n+ [ROM_API_INDEX_GLB_Set_Audio_PDM_CLK] = (uint32_t)GLB_Set_Audio_PDM_CLK,\n+ [ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type] = (uint32_t)GLB_Set_Auto_Calc_Xtal_Type,\n+ [ROM_API_INDEX_GLB_Set_CAM_CLK] = (uint32_t)GLB_Set_CAM_CLK,\n+ [ROM_API_INDEX_GLB_Set_CPU_Reset_Address] = (uint32_t)GLB_Set_CPU_Reset_Address,\n+ [ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel] = (uint32_t)GLB_Set_CSI_DSI_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel] = (uint32_t)GLB_Set_Chip_Clock_Out0_Sel,\n+ [ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel] = (uint32_t)GLB_Set_Chip_Clock_Out1_Sel,\n+ [ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel] = (uint32_t)GLB_Set_Chip_Clock_Out2_Sel,\n+ [ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel] = (uint32_t)GLB_Set_Chip_Clock_Out3_Sel,\n+ [ROM_API_INDEX_GLB_Set_DIG_32K_CLK] = (uint32_t)GLB_Set_DIG_32K_CLK,\n+ [ROM_API_INDEX_GLB_Set_DIG_512K_CLK] = (uint32_t)GLB_Set_DIG_512K_CLK,\n+ [ROM_API_INDEX_GLB_Set_DIG_CLK_Sel] = (uint32_t)GLB_Set_DIG_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_DMA_CLK] = (uint32_t)GLB_Set_DMA_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_CNN_CLK] = (uint32_t)GLB_Set_DSP_CNN_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_DP_CLK] = (uint32_t)GLB_Set_DSP_DP_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_H264_CLK] = (uint32_t)GLB_Set_DSP_H264_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK] = (uint32_t)GLB_Set_DSP_I2C0_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK] = (uint32_t)GLB_Set_DSP_I2C1_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK] = (uint32_t)GLB_Set_DSP_DSP2_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size] = (uint32_t)GLB_Set_DSP_L2SRAM_Available_Size,\n+ [ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK] = (uint32_t)GLB_Set_DSP_MTimer_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel] = (uint32_t)GLB_Set_DSP_MUXPLL_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel] = (uint32_t)GLB_Set_DSP_Muxpll_160M_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel] = (uint32_t)GLB_Set_DSP_Muxpll_240M_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel] = (uint32_t)GLB_Set_DSP_Muxpll_320M_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_PBCLK] = (uint32_t)GLB_Set_DSP_PBCLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div] = (uint32_t)GLB_Set_DSP_PBCLK_Div,\n+ [ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel] = (uint32_t)GLB_Set_DSP_PBROOT_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel] = (uint32_t)GLB_Set_DSP_ROOT_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel] = (uint32_t)GLB_Set_DSP_SPI_0_ACT_MOD_Sel,\n+ [ROM_API_INDEX_GLB_Set_DSP_SPI_CLK] = (uint32_t)GLB_Set_DSP_SPI_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_System_CLK] = (uint32_t)GLB_Set_DSP_System_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div] = (uint32_t)GLB_Set_DSP_System_CLK_Div,\n+ [ROM_API_INDEX_GLB_Set_DSP_UART0_CLK] = (uint32_t)GLB_Set_DSP_UART0_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_UART1_CLK] = (uint32_t)GLB_Set_DSP_UART1_CLK,\n+ [ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel] = (uint32_t)GLB_Set_DSP_XCLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_Display_CLK] = (uint32_t)GLB_Set_Display_CLK,\n+ [ROM_API_INDEX_GLB_Set_EMAC_CLK] = (uint32_t)GLB_Set_EMAC_CLK,\n+ [ROM_API_INDEX_GLB_Set_EMI_CLK] = (uint32_t)GLB_Set_EMI_CLK,\n+ [ROM_API_INDEX_GLB_Set_EM_Sel] = (uint32_t)GLB_Set_EM_Sel,\n+ [ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel] = (uint32_t)GLB_Set_ETH_REF_O_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_Flash_IO_PARM] = (uint32_t)GLB_Set_Flash_IO_PARM,\n+ [ROM_API_INDEX_GLB_Set_Flash_Id_Value] = (uint32_t)GLB_Set_Flash_Id_Value,\n+ [ROM_API_INDEX_GLB_Set_I2C_CLK] = (uint32_t)GLB_Set_I2C_CLK,\n+ [ROM_API_INDEX_GLB_Set_I2S_CLK] = (uint32_t)GLB_Set_I2S_CLK,\n+ [ROM_API_INDEX_GLB_Set_IR_CLK] = (uint32_t)GLB_Set_IR_CLK,\n+ [ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK] = (uint32_t)GLB_Set_MCU_MTimer_CLK,\n+ [ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel] = (uint32_t)GLB_Set_MCU_Muxpll_160M_Sel,\n+ [ROM_API_INDEX_GLB_Set_MCU_Muxpll_80M_Sel] = (uint32_t)GLB_Set_MCU_Muxpll_80M_Sel,\n+ [ROM_API_INDEX_GLB_Set_MCU_SPI_0_ACT_MOD_Sel] = (uint32_t)GLB_Set_MCU_SPI_0_ACT_MOD_Sel,\n+ [ROM_API_INDEX_GLB_Set_MCU_System_CLK] = (uint32_t)GLB_Set_MCU_System_CLK,\n+ [ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div] = (uint32_t)GLB_Set_MCU_System_CLK_Div,\n+ [ROM_API_INDEX_GLB_Set_PADC_CLK] = (uint32_t)GLB_Set_PADC_CLK,\n+ [ROM_API_INDEX_GLB_Set_PDM_IO_Sel] = (uint32_t)GLB_Set_PDM_IO_Sel,\n+ [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Set_PSram_CLK] = (uint32_t)GLB_Set_PSram_CLK,\n+ [ROM_API_INDEX_GLB_Set_PWM1_IO_Sel] = (uint32_t)GLB_Set_PWM1_IO_Sel,\n+ [ROM_API_INDEX_GLB_Set_PWM2_IO_Sel] = (uint32_t)GLB_Set_PWM2_IO_Sel,\n+ [ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN] = (uint32_t)GLB_Set_Peripheral_DMA_CN,\n+ [ROM_API_INDEX_GLB_Set_SDH_CLK] = (uint32_t)GLB_Set_SDH_CLK,\n+ [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK,\n+ [ROM_API_INDEX_GLB_Set_SPI_CLK] = (uint32_t)GLB_Set_SPI_CLK,\n+ [ROM_API_INDEX_GLB_Set_SRAM_PARM] = (uint32_t)GLB_Set_SRAM_PARM,\n+ [ROM_API_INDEX_GLB_Set_SRAM_RET] = (uint32_t)GLB_Set_SRAM_RET,\n+ [ROM_API_INDEX_GLB_Set_SRAM_SLP] = (uint32_t)GLB_Set_SRAM_SLP,\n+ [ROM_API_INDEX_GLB_Set_UART2_IO_Sel] = (uint32_t)GLB_Set_UART2_IO_Sel,\n+ [ROM_API_INDEX_GLB_Set_UART_CLK] = (uint32_t)GLB_Set_UART_CLK,\n+ [ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL] = (uint32_t)GLB_Set_USB_CLK_From_WIFIPLL,\n+ [ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO] = (uint32_t)GLB_Swap_DSP_SPI_0_MOSI_With_MISO,\n+ [ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO] = (uint32_t)GLB_Swap_MCU_SPI_0_MOSI_With_MISO,\n+ [ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout] = (uint32_t)GLB_Trim_LDO18FLASH_Vout,\n+ [ROM_API_INDEX_GLB_Trim_LDO18IO_Vout] = (uint32_t)GLB_Trim_LDO18IO_Vout,\n+ [ROM_API_INDEX_GLB_UART_Fun_Sel] = (uint32_t)GLB_UART_Fun_Sel,\n+ [ROM_API_INDEX_GLB_UART_Sig_Swap_Set] = (uint32_t)GLB_UART_Sig_Swap_Set,\n+ [ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus] = (uint32_t)GLB_DSP_Get_LP_IntStatus,\n+ [ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus] = (uint32_t)GLB_DSP_Get_MCU_IntStatus,\n+ [ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus] = (uint32_t)GLB_MCU_Get_DSP_IntStatus,\n+ [ROM_API_INDEX_GLB_Get_Core_Type] = (uint32_t)GLB_Get_Core_Type,\n+ [ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel] = (uint32_t)GLB_Get_DSP_Muxpll_160M_Sel,\n+ [ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel] = (uint32_t)GLB_Get_DSP_Muxpll_240M_Sel,\n+ [ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel] = (uint32_t)GLB_Get_DSP_Muxpll_320M_Sel,\n+ [ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel] = (uint32_t)GLB_Get_DSP_PBROOT_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel] = (uint32_t)GLB_Get_DSP_ROOT_CLK_Sel,\n+ [ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel] = (uint32_t)GLB_Get_DSP_XCLK_Sel,\n+ [ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel] = (uint32_t)GLB_Get_MCU_Muxpll_160M_Sel,\n+ [ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel] = (uint32_t)GLB_Get_MCU_Muxpll_80M_Sel,\n+ [ROM_API_INDEX_GLB_Get_Flash_Id_Value] = (uint32_t)GLB_Get_Flash_Id_Value,\n+ [ROM_API_INDEX_GLB_Get_SRAM_PARM] = (uint32_t)GLB_Get_SRAM_PARM,\n+ [ROM_API_INDEX_GLB_Get_SRAM_RET] = (uint32_t)GLB_Get_SRAM_RET,\n+ [ROM_API_INDEX_GLB_Get_SRAM_SLP] = (uint32_t)GLB_Get_SRAM_SLP,\n+ [ROM_API_INDEX_GLB_Get_BMX_TO_Status] = (uint32_t)GLB_Get_BMX_TO_Status,\n+ [ROM_API_INDEX_GLB_Clr_GPIO_IntStatus] = (uint32_t)GLB_Clr_GPIO_IntStatus,\n+ [ROM_API_INDEX_GLB_Embedded_Flash_Pad_Enable] = (uint32_t)GLB_Embedded_Flash_Pad_Enable,\n+ [ROM_API_INDEX_GLB_GPIO_Clr] = (uint32_t)GLB_GPIO_Clr,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_Clear] = (uint32_t)GLB_GPIO_Fifo_Clear,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_Init] = (uint32_t)GLB_GPIO_Fifo_Init,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_IntClear] = (uint32_t)GLB_GPIO_Fifo_IntClear,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_IntMask] = (uint32_t)GLB_GPIO_Fifo_IntMask,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_Push] = (uint32_t)GLB_GPIO_Fifo_Push,\n+ [ROM_API_INDEX_GLB_GPIO_Func_Init] = (uint32_t)GLB_GPIO_Func_Init,\n+ [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init,\n+ [ROM_API_INDEX_GLB_GPIO_Input_Disable] = (uint32_t)GLB_GPIO_Input_Disable,\n+ [ROM_API_INDEX_GLB_GPIO_Input_Enable] = (uint32_t)GLB_GPIO_Input_Enable,\n+ [ROM_API_INDEX_GLB_GPIO_IntMask] = (uint32_t)GLB_GPIO_IntMask,\n+ [ROM_API_INDEX_GLB_GPIO_Int_Init] = (uint32_t)GLB_GPIO_Int_Init,\n+ [ROM_API_INDEX_GLB_GPIO_Output_Disable] = (uint32_t)GLB_GPIO_Output_Disable,\n+ [ROM_API_INDEX_GLB_GPIO_Output_Enable] = (uint32_t)GLB_GPIO_Output_Enable,\n+ [ROM_API_INDEX_GLB_GPIO_Set] = (uint32_t)GLB_GPIO_Set,\n+ [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ,\n+ [ROM_API_INDEX_GLB_GPIO_Write] = (uint32_t)GLB_GPIO_Write,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_Disable] = (uint32_t)GLB_GPIO_Fifo_Disable,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_Enable] = (uint32_t)GLB_GPIO_Fifo_Enable,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_GetIntStatus] = (uint32_t)GLB_GPIO_Fifo_GetIntStatus,\n+ [ROM_API_INDEX_GLB_Get_GPIO_IntStatus] = (uint32_t)GLB_Get_GPIO_IntStatus,\n+ [ROM_API_INDEX_GLB_GPIO_Fifo_GetCount] = (uint32_t)GLB_GPIO_Fifo_GetCount,\n+ [ROM_API_INDEX_GLB_GPIO_Read] = (uint32_t)GLB_GPIO_Read,\n+ [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun,\n+\n+ [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel,\n+ [ROM_API_INDEX_HBN_Aon_Pad_Cfg] = (uint32_t)HBN_Aon_Pad_Cfg,\n+ [ROM_API_INDEX_HBN_Aon_Pad_Ctrl] = (uint32_t)HBN_Aon_Pad_Ctrl,\n+ [ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg] = (uint32_t)HBN_Aon_Pad_WakeUpCfg,\n+ [ROM_API_INDEX_HBN_Clear_IRQ] = (uint32_t)HBN_Clear_IRQ,\n+ [ROM_API_INDEX_HBN_Clear_RTC_Counter] = (uint32_t)HBN_Clear_RTC_Counter,\n+ [ROM_API_INDEX_HBN_Clear_RTC_INT] = (uint32_t)HBN_Clear_RTC_INT,\n+ [ROM_API_INDEX_HBN_Disable_AComp0_IRQ] = (uint32_t)HBN_Disable_AComp0_IRQ,\n+ [ROM_API_INDEX_HBN_Disable_AComp1_IRQ] = (uint32_t)HBN_Disable_AComp1_IRQ,\n+ [ROM_API_INDEX_HBN_Disable_BOD_IRQ] = (uint32_t)HBN_Disable_BOD_IRQ,\n+ [ROM_API_INDEX_HBN_Enable_AComp0_IRQ] = (uint32_t)HBN_Enable_AComp0_IRQ,\n+ [ROM_API_INDEX_HBN_Enable_AComp1_IRQ] = (uint32_t)HBN_Enable_AComp1_IRQ,\n+ [ROM_API_INDEX_HBN_Enable_BOD_IRQ] = (uint32_t)HBN_Enable_BOD_IRQ,\n+ [ROM_API_INDEX_HBN_Enable_RTC_Counter] = (uint32_t)HBN_Enable_RTC_Counter,\n+ [ROM_API_INDEX_HBN_GPIO_INT_Disable] = (uint32_t)HBN_GPIO_INT_Disable,\n+ [ROM_API_INDEX_HBN_GPIO_INT_Enable] = (uint32_t)HBN_GPIO_INT_Enable,\n+ [ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg] = (uint32_t)HBN_Get_RTC_Misc_Cfg,\n+ [ROM_API_INDEX_HBN_Get_RTC_Timer_Val] = (uint32_t)HBN_Get_RTC_Timer_Val,\n+ [ROM_API_INDEX_HBN_Get_Xtal_Type] = (uint32_t)HBN_Get_Xtal_Type,\n+ [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg,\n+ [ROM_API_INDEX_HBN_PD_RC32K_All_State] = (uint32_t)HBN_PD_RC32K_All_State,\n+ [ROM_API_INDEX_HBN_PD_RC32K_In_Poff] = (uint32_t)HBN_PD_RC32K_In_Poff,\n+ [ROM_API_INDEX_HBN_PIR_Disable] = (uint32_t)HBN_PIR_Disable,\n+ [ROM_API_INDEX_HBN_PIR_Enable] = (uint32_t)HBN_PIR_Enable,\n+ [ROM_API_INDEX_HBN_PIR_HPF_Sel] = (uint32_t)HBN_PIR_HPF_Sel,\n+ [ROM_API_INDEX_HBN_PIR_INT_Config] = (uint32_t)HBN_PIR_INT_Config,\n+ [ROM_API_INDEX_HBN_PIR_LPF_Sel] = (uint32_t)HBN_PIR_LPF_Sel,\n+ [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask,\n+ [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K,\n+ [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K,\n+ [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K,\n+ [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K,\n+ [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset,\n+ [ROM_API_INDEX_HBN_Set_BOD_Cfg] = (uint32_t)HBN_Set_BOD_Cfg,\n+ [ROM_API_INDEX_HBN_Set_BOD_Config] = (uint32_t)HBN_Set_BOD_Config,\n+ [ROM_API_INDEX_HBN_Set_Core_Reboot_Config] = (uint32_t)HBN_Set_Core_Reboot_Config,\n+ [ROM_API_INDEX_HBN_Set_HRAM_Ret] = (uint32_t)HBN_Set_HRAM_Ret,\n+ [ROM_API_INDEX_HBN_Set_HRAM_slp] = (uint32_t)HBN_Set_HRAM_slp,\n+ [ROM_API_INDEX_HBN_Set_Hand_Off_Config] = (uint32_t)HBN_Set_Hand_Off_Config,\n+ [ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO] = (uint32_t)HBN_Set_IO4041_As_Xtal_32K_IO,\n+ [ROM_API_INDEX_HBN_Set_Ldo11_All_Vout] = (uint32_t)HBN_Set_Ldo11_All_Vout,\n+ [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout,\n+ [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout,\n+ [ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout] = (uint32_t)HBN_Set_Ldo11_Rtc_Vout,\n+ [ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay] = (uint32_t)HBN_Set_Ldo18flash_Repower_Delay,\n+ [ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel] = (uint32_t)HBN_Set_MCU_Root_CLK_Sel,\n+ [ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel] = (uint32_t)HBN_Set_MCU_XCLK_Sel,\n+ [ROM_API_INDEX_HBN_Set_MM_Power_Config] = (uint32_t)HBN_Set_MM_Power_Config,\n+ [ROM_API_INDEX_HBN_Set_PIR_Interval] = (uint32_t)HBN_Set_PIR_Interval,\n+ [ROM_API_INDEX_HBN_Set_PIR_Threshold] = (uint32_t)HBN_Set_PIR_Threshold,\n+ [ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg] = (uint32_t)HBN_Set_RTC_Misc_Cfg,\n+ [ROM_API_INDEX_HBN_Set_RTC_Timer] = (uint32_t)HBN_Set_RTC_Timer,\n+ [ROM_API_INDEX_HBN_Set_Status_Flag] = (uint32_t)HBN_Set_Status_Flag,\n+ [ROM_API_INDEX_HBN_Set_UART_CLK_Sel] = (uint32_t)HBN_Set_UART_CLK_Sel,\n+ [ROM_API_INDEX_HBN_Set_Wakeup_Addr] = (uint32_t)HBN_Set_Wakeup_Addr,\n+ [ROM_API_INDEX_HBN_Set_Xtal_Type] = (uint32_t)HBN_Set_Xtal_Type,\n+ [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K,\n+ [ROM_API_INDEX_HBN_Get_BOD_OUT_State] = (uint32_t)HBN_Get_BOD_OUT_State,\n+ [ROM_API_INDEX_HBN_Get_INT_State] = (uint32_t)HBN_Get_INT_State,\n+ [ROM_API_INDEX_HBN_Get_MCU_Root_CLK_Sel] = (uint32_t)HBN_Get_MCU_Root_CLK_Sel,\n+ [ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel] = (uint32_t)HBN_Get_MCU_XCLK_Sel,\n+ [ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config] = (uint32_t)HBN_Get_Ldo18flash_Repower_Config,\n+ [ROM_API_INDEX_HBN_Get_PIR_Interval] = (uint32_t)HBN_Get_PIR_Interval,\n+ [ROM_API_INDEX_HBN_Get_PIR_Threshold] = (uint32_t)HBN_Get_PIR_Threshold,\n+ [ROM_API_INDEX_HBN_Get_Status_Flag] = (uint32_t)HBN_Get_Status_Flag,\n+ [ROM_API_INDEX_HBN_Get_Wakeup_Addr] = (uint32_t)HBN_Get_Wakeup_Addr,\n+ [ROM_API_INDEX_HBN_Get_Core_Unhalt_Config] = (uint32_t)HBN_Get_Core_Unhalt_Config,\n+ [ROM_API_INDEX_HBN_Get_Hand_Off_Config] = (uint32_t)HBN_Get_Hand_Off_Config,\n+ [ROM_API_INDEX_HBN_Get_MM_Power_Config] = (uint32_t)HBN_Get_MM_Power_Config,\n+ [ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode] = (uint32_t)HBN_Get_Pin_Wakeup_Mode,\n+ [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable,\n+ [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter,\n+ [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash,\n+\n+ [ROM_API_INDEX_L1C_DCache_Clean_All] = (uint32_t)L1C_DCache_Clean_All,\n+ [ROM_API_INDEX_L1C_DCache_Clean_By_Addr] = (uint32_t)L1C_DCache_Clean_By_Addr,\n+ [ROM_API_INDEX_L1C_DCache_Clean_Invalid_All] = (uint32_t)L1C_DCache_Clean_Invalid_All,\n+ [ROM_API_INDEX_L1C_DCache_Clean_Invalid_By_Addr] = (uint32_t)L1C_DCache_Clean_Invalid_By_Addr,\n+ [ROM_API_INDEX_L1C_DCache_Disable] = (uint32_t)L1C_DCache_Disable,\n+ [ROM_API_INDEX_L1C_DCache_Enable] = (uint32_t)L1C_DCache_Enable,\n+ [ROM_API_INDEX_L1C_DCache_Invalid_All] = (uint32_t)L1C_DCache_Invalid_All,\n+ [ROM_API_INDEX_L1C_DCache_Invalid_By_Addr] = (uint32_t)L1C_DCache_Invalid_By_Addr,\n+ [ROM_API_INDEX_L1C_ICache_Disable] = (uint32_t)L1C_ICache_Disable,\n+ [ROM_API_INDEX_L1C_ICache_Enable] = (uint32_t)L1C_ICache_Enable,\n+ [ROM_API_INDEX_L1C_ICache_Invalid_All] = (uint32_t)L1C_ICache_Invalid_All,\n+ [ROM_API_INDEX_L1C_ICache_Invalid_By_Addr] = (uint32_t)L1C_ICache_Invalid_By_Addr,\n+ [ROM_API_INDEX_L1C_Set_Cache_Setting_By_ID] = (uint32_t)L1C_Set_Cache_Setting_By_ID,\n+ [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap,\n+ [ROM_API_INDEX_L1C_Get_None_Cache_Addr] = (uint32_t)L1C_Get_None_Cache_Addr,\n+ [ROM_API_INDEX_L1C_Is_DCache_Range] = (uint32_t)L1C_Is_DCache_Range,\n+ [ROM_API_INDEX_L1C_DCache_Write_Set] = (uint32_t)L1C_DCache_Write_Set,\n+\n+ [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config,\n+ [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable,\n+ [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config,\n+ [ROM_API_INDEX_PDS_IntClear] = (uint32_t)PDS_IntClear,\n+ [ROM_API_INDEX_PDS_IntMask] = (uint32_t)PDS_IntMask,\n+ [ROM_API_INDEX_PDS_Power_On_MM_System] = (uint32_t)PDS_Power_On_MM_System,\n+ [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config,\n+ [ROM_API_INDEX_PDS_Reset_LP_RTC] = (uint32_t)PDS_Reset_LP_RTC,\n+ [ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None] = (uint32_t)PDS_Set_Flash_Pad_Pull_None,\n+ [ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast] = (uint32_t)PDS_Set_Flash_Pad_Pull_None_Fast,\n+ [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr] = (uint32_t)PDS_Set_GPIO_Pad_IntClr,\n+ [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask] = (uint32_t)PDS_Set_GPIO_Pad_IntMask,\n+ [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode] = (uint32_t)PDS_Set_GPIO_Pad_IntMode,\n+ [ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie] = (uint32_t)PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie,\n+ [ROM_API_INDEX_PDS_Set_LP_Clock_Disable] = (uint32_t)PDS_Set_LP_Clock_Disable,\n+ [ROM_API_INDEX_PDS_Set_LP_Clock_Enable] = (uint32_t)PDS_Set_LP_Clock_Enable,\n+ [ROM_API_INDEX_PDS_Set_LP_RTC_CLK] = (uint32_t)PDS_Set_LP_RTC_CLK,\n+ [ROM_API_INDEX_PDS_Set_LP_Reset_Address] = (uint32_t)PDS_Set_LP_Reset_Address,\n+ [ROM_API_INDEX_PDS_Set_LP_System_CLK] = (uint32_t)PDS_Set_LP_System_CLK,\n+ [ROM_API_INDEX_PDS_Set_LP_System_CLK_Div] = (uint32_t)PDS_Set_LP_System_CLK_Div,\n+ [ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable] = (uint32_t)PDS_Set_MCU0_Clock_Disable,\n+ [ROM_API_INDEX_PDS_Set_MCU0_Clock_Enable] = (uint32_t)PDS_Set_MCU0_Clock_Enable,\n+ [ROM_API_INDEX_PDS_Set_MCU0_Reset_Address] = (uint32_t)PDS_Set_MCU0_Reset_Address,\n+ [ROM_API_INDEX_PDS_Set_USB_Resume] = (uint32_t)PDS_Set_USB_Resume,\n+ [ROM_API_INDEX_PDS_Set_USB_Suspend] = (uint32_t)PDS_Set_USB_Suspend,\n+ [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M,\n+ [ROM_API_INDEX_PDS_Turn_Off_USB] = (uint32_t)PDS_Turn_Off_USB,\n+ [ROM_API_INDEX_PDS_Turn_On_USB] = (uint32_t)PDS_Turn_On_USB,\n+ [ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus] = (uint32_t)PDS_Get_GPIO_Pad_IntStatus,\n+ [ROM_API_INDEX_PDS_Get_IntStatus] = (uint32_t)PDS_Get_IntStatus,\n+ [ROM_API_INDEX_PDS_Get_MM_System_Power_On_State] = (uint32_t)PDS_Get_MM_System_Power_On_State,\n+\n+ [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,\n+ [ROM_API_INDEX_SF_Cfg_Flash_Init] = (uint32_t)SF_Cfg_Flash_Init,\n+ [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,\n+ [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext,\n+ [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,\n+ [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio,\n+ [ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init] = (uint32_t)SF_Cfg_Sbus2_Flash_Init,\n+ [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify,\n+ [ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext] = (uint32_t)SF_Cfg_Flash_Identify_Ext,\n+ [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState,\n+ [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable,\n+ [ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable] = (uint32_t)SF_Ctrl_Is_Sbus2_Enable,\n+ [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,\n+ [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay,\n+ [ROM_API_INDEX_SF_Ctrl_Get_Wrap_Queue_Value] = (uint32_t)SF_Ctrl_Get_Wrap_Queue_Value,\n+ [ROM_API_INDEX_SF_Ctrl_32bits_Addr_En] = (uint32_t)SF_Ctrl_32bits_Addr_En,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_Mode] = (uint32_t)SF_Ctrl_AES_Set_Mode,\n+ [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region,\n+ [ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV] = (uint32_t)SF_Ctrl_AES_XTS_Set_IV,\n+ [ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_XTS_Set_IV_BE,\n+ [ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key] = (uint32_t)SF_Ctrl_AES_XTS_Set_Key,\n+ [ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_XTS_Set_Key_BE,\n+ [ROM_API_INDEX_SF_Ctrl_Bank2_Enable] = (uint32_t)SF_Ctrl_Bank2_Enable,\n+ [ROM_API_INDEX_SF_Ctrl_Cmds_Set] = (uint32_t)SF_Ctrl_Cmds_Set,\n+ [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable,\n+ [ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access] = (uint32_t)SF_Ctrl_Disable_Wrap_Access,\n+ [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable,\n+ [ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set] = (uint32_t)SF_Ctrl_Flash2_Read_Icache_Set,\n+ [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set] = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set,\n+ [ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Lock_Flash_Image_Offset,\n+ [ROM_API_INDEX_SF_Ctrl_Remap_Set] = (uint32_t)SF_Ctrl_Remap_Set,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram] = (uint32_t)SF_Ctrl_Sbus2_Hold_Sram,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram] = (uint32_t)SF_Ctrl_Sbus2_Release_Sram,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus2_Replace] = (uint32_t)SF_Ctrl_Sbus2_Replace,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace] = (uint32_t)SF_Ctrl_Sbus2_Revoke_replace,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay] = (uint32_t)SF_Ctrl_Sbus2_Set_Delay,\n+ [ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank] = (uint32_t)SF_Ctrl_Sbus_Select_Bank,\n+ [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad,\n+ [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd,\n+ [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay,\n+ [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,\n+ [ROM_API_INDEX_SF_Ctrl_Set_IO_Delay] = (uint32_t)SF_Ctrl_Set_IO_Delay,\n+ [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner,\n+\n+ [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase,\n+ [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase,\n+ [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase,\n+ [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase,\n+ [ROM_API_INDEX_SFlash_Erase_Security_Register] = (uint32_t)SFlash_Erase_Security_Register,\n+ [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable,\n+ [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program,\n+ [ROM_API_INDEX_SFlash_Program_Security_Register] = (uint32_t)SFlash_Program_Security_Register,\n+ [ROM_API_INDEX_SFlash_Qspi_Disable] = (uint32_t)SFlash_Qspi_Disable,\n+ [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable,\n+ [ROM_API_INDEX_SFlash_RCV_Enable] = (uint32_t)SFlash_RCV_Enable,\n+ [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read,\n+ [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg,\n+ [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd,\n+ [ROM_API_INDEX_SFlash_Read_Security_Register] = (uint32_t)SFlash_Read_Security_Register,\n+ [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown,\n+ [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase,\n+ [ROM_API_INDEX_SFlash_Set32BitsAddrMode] = (uint32_t)SFlash_Set32BitsAddrMode,\n+ [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode,\n+ [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg,\n+ [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset,\n+ [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable,\n+ [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg,\n+ [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd,\n+ [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy,\n+ [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap,\n+ [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId,\n+ [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId,\n+ [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId,\n+ [ROM_API_INDEX_SFlash_IDbus_Read_Disable] = (uint32_t)SFlash_IDbus_Read_Disable,\n+ [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init,\n+ [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown,\n+ [ROM_API_INDEX_SFlash_Release_Powerdown] = (uint32_t)SFlash_Release_Powerdown,\n+ [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read,\n+ [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap,\n+ [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,\n+\n+ [ROM_API_INDEX_UART_ApplyAbrResult] = (uint32_t)UART_ApplyAbrResult,\n+ [ROM_API_INDEX_UART_AutoBaudDetection] = (uint32_t)UART_AutoBaudDetection,\n+ [ROM_API_INDEX_UART_ClrRtsValue] = (uint32_t)UART_ClrRtsValue,\n+ [ROM_API_INDEX_UART_ClrTxValue] = (uint32_t)UART_ClrTxValue,\n+ [ROM_API_INDEX_UART_DeInit] = (uint32_t)UART_DeInit,\n+ [ROM_API_INDEX_UART_Disable] = (uint32_t)UART_Disable,\n+ [ROM_API_INDEX_UART_Enable] = (uint32_t)UART_Enable,\n+ [ROM_API_INDEX_UART_FifoConfig] = (uint32_t)UART_FifoConfig,\n+ [ROM_API_INDEX_UART_GetBitWidth0X55] = (uint32_t)UART_GetBitWidth0X55,\n+ [ROM_API_INDEX_UART_Init] = (uint32_t)UART_Init,\n+ [ROM_API_INDEX_UART_IntClear] = (uint32_t)UART_IntClear,\n+ [ROM_API_INDEX_UART_IntMask] = (uint32_t)UART_IntMask,\n+ [ROM_API_INDEX_UART_IrConfig] = (uint32_t)UART_IrConfig,\n+ [ROM_API_INDEX_UART_RxFifoClear] = (uint32_t)UART_RxFifoClear,\n+ [ROM_API_INDEX_UART_SendData] = (uint32_t)UART_SendData,\n+ [ROM_API_INDEX_UART_SendDataBlock] = (uint32_t)UART_SendDataBlock,\n+ [ROM_API_INDEX_UART_SetAllowableError0X55] = (uint32_t)UART_SetAllowableError0X55,\n+ [ROM_API_INDEX_UART_SetBaudRate] = (uint32_t)UART_SetBaudRate,\n+ [ROM_API_INDEX_UART_SetDeglitchCount] = (uint32_t)UART_SetDeglitchCount,\n+ [ROM_API_INDEX_UART_SetRS485] = (uint32_t)UART_SetRS485,\n+ [ROM_API_INDEX_UART_SetRtsValue] = (uint32_t)UART_SetRtsValue,\n+ [ROM_API_INDEX_UART_SetRxByteCount] = (uint32_t)UART_SetRxByteCount,\n+ [ROM_API_INDEX_UART_SetRxDataLength] = (uint32_t)UART_SetRxDataLength,\n+ [ROM_API_INDEX_UART_SetRxTimeoutValue] = (uint32_t)UART_SetRxTimeoutValue,\n+ [ROM_API_INDEX_UART_SetTxDataLength] = (uint32_t)UART_SetTxDataLength,\n+ [ROM_API_INDEX_UART_SetTxValue] = (uint32_t)UART_SetTxValue,\n+ [ROM_API_INDEX_UART_TxFifoClear] = (uint32_t)UART_TxFifoClear,\n+ [ROM_API_INDEX_UART_TxFreeRun] = (uint32_t)UART_TxFreeRun,\n+ [ROM_API_INDEX_UART_GetIntStatus] = (uint32_t)UART_GetIntStatus,\n+ [ROM_API_INDEX_UART_GetOverflowStatus] = (uint32_t)UART_GetOverflowStatus,\n+ [ROM_API_INDEX_UART_GetRxBusBusyStatus] = (uint32_t)UART_GetRxBusBusyStatus,\n+ [ROM_API_INDEX_UART_GetTxBusBusyStatus] = (uint32_t)UART_GetTxBusBusyStatus,\n+ [ROM_API_INDEX_UART_GetAutoBaudCount] = (uint32_t)UART_GetAutoBaudCount,\n+ [ROM_API_INDEX_UART_GetRxByteCount] = (uint32_t)UART_GetRxByteCount,\n+ [ROM_API_INDEX_UART_ReceiveData] = (uint32_t)UART_ReceiveData,\n+ [ROM_API_INDEX_UART_GetRxFifoCount] = (uint32_t)UART_GetRxFifoCount,\n+ [ROM_API_INDEX_UART_GetTxFifoCount] = (uint32_t)UART_GetTxFifoCount,\n+\n+ [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore,\n+ [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save,\n+ [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock,\n+ [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter,\n+ [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit,\n+\n+ [ROM_API_INDEX_FUNC_EMPTY_START ... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef,\n+};\n+\n+\n+/*@} end of group ROMDRIVER_Global_Variables */\n+\n+/** @defgroup ROMDRIVER_Private_FunctionDeclaration\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Private_FunctionDeclaration */\n+\n+/** @defgroup ROMDRIVER_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Private_Functions */\n+\n+/** @defgroup ROMDRIVER_Public_Functions\n+ * @{\n+ */\n+\n+/*@} end of group ROMDRIVER_Public_Functions */\n+\n+/*@} end of group ROMDRIVER_COMMON */\n+\n+/*@} end of group BL808_Periph_Driver */\n+\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8db34aef44d2464e46176991c573cda561d0cac5\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c\n@@ -0,0 +1,1367 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sdh.c\n+ * @version V1.2\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2018 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808.h\"\n+#include \"string.h\"\n+#include \"bl808_sdh.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SDH\n+ * @{\n+ */\n+\n+/** @defgroup SDH_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SDH_Private_Macros */\n+\n+/** @defgroup SDH_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SDH_Private_Types */\n+\n+/** @defgroup SDH_Private_Variables\n+ * @{\n+ */\n+static uint32_t bootDummy = 0;\n+static SDH_Handle_Cfg_Type *sdhHandle = NULL;\n+\n+/*@} end of group SDH_Private_Variables */\n+\n+/** @defgroup SDH_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SDH_Global_Variables */\n+\n+/** @defgroup SDH_Private_Fun_Declaration\n+ * @{\n+ */\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle);\n+#endif\n+\n+/*@} end of group SDH_Private_Fun_Declaration */\n+\n+/** @defgroup SDH_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group SDH_Private_Functions */\n+\n+/** @defgroup SDH_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Enable SDH DMA\n+ *\n+ * @param dmaMode: DMA mode select\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode)\n+{\n+ uint16_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SDH_DMA_MODE_TYPE(dmaMode));\n+\n+ /* Select DMA type */\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SEL, dmaMode);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_DMA_EN);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable SDH DMA\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_DisableDMA(void)\n+{\n+ uint16_t tmpVal;\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_DMA_EN);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);\n+}\n+/****************************************************************************/ /**\n+ * @brief SDH enable interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState)\n+{\n+ if (NewState != DISABLE) {\n+ /* Enable the SDH interrupts */\n+ SDH_EnableIntSource(SDH_IT_FLAG);\n+ } else {\n+ /* Disable the SDH interrupts */\n+ SDH_DisableIntSource(SDH_IT_FLAG);\n+ }\n+}\n+/****************************************************************************/ /**\n+ * @brief SDH enable interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_EnableStatus(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable all interrupts */\n+ SDH_DisableIntStatus(SDH_INT_ALL);\n+\n+ tmpVal = (SDH_INT_CMD_TIMEOUT | SDH_INT_CMD_CRC_ERROR | SDH_INT_CMD_ENDBIT_ERROR |\n+ SDH_INT_CMD_INDEX_ERROR | SDH_INT_CMD_COMPLETED |\n+ SDH_INT_CARD_INSERT | SDH_INT_CARD_REMOVE |\n+ SDH_INT_DATA_COMPLETED | SDH_INT_DMA_COMPLETED |\n+ SDH_INT_BUFFER_WRITE_READY | SDH_INT_BUFFER_READ_READY |\n+ SDH_INT_DATA_TIMEOUT | SDH_INT_DATA_CRC_ERROR | SDH_INT_DATA_ENDBIT_ERROR |\n+ SDH_INT_AUTO_CMD12_ERROR | SDH_INT_DMA_ERROR | SDH_INT_BLK_GAP_EVENT |\n+ SDH_INT_RETUNE_EVENT | SDH_INT_TUNE_ERROR);\n+\n+ SDH_EnableIntStatus(tmpVal);\n+}\n+/****************************************************************************/ /**\n+ * @brief SDH enable interrupt\n+ *\n+ * @param dataCfg: Transfer data config pointer\n+ *\n+ * @return SDH status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg)\n+{\n+ uint16_t tmpVal;\n+\n+ if (dataCfg != NULL) {\n+ /* For transfer boot continous, only need to set the CREQ bit */\n+ if (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL);\n+ /* Clear stop at block gap request */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_STOP_AT_BLOCK_GAP_REQ);\n+ /* Continous transfer data */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_CONT_REQ);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL, tmpVal);\n+\n+ return SDH_STAT_SUCCESS;\n+ }\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);\n+\n+ /* Check data inhibit flag */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_DAT)) {\n+ return SDH_STAT_BUSY;\n+ }\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+\n+ /* Check transfer block count */\n+ if ((dataCfg->blockCount > SDH_MAX_BLOCK_COUNT) || ((dataCfg->txData == NULL) && (dataCfg->rxData == NULL))) {\n+ return SDH_STAT_INVLAID_PARA;\n+ }\n+\n+ if (dataCfg->rxData) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TO_HOST_DIR);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_TO_HOST_DIR);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);\n+\n+ /* auto command 23, auto send set block count cmd before multiple read/write */\n+ if (dataCfg->enableAutoCommand23) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x02);\n+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, dataCfg->blockCount);\n+ } else if (dataCfg->enableAutoCommand12) {\n+ /* auto command 12 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x01);\n+ }\n+\n+ if (dataCfg->blockCount > 1U) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);\n+ }\n+\n+ /* Enable block count */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_BLK_CNT_EN);\n+\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);\n+\n+ /* if transfer boot data, leave the block count to SDH_SetMmcBootConfig function */\n+ if (dataCfg->dataType != SDH_TRANS_DATA_BOOT) {\n+ /* config data block size/block count */\n+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_SIZE, dataCfg->blockSize);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_COUNT, dataCfg->blockCount);\n+ }\n+ } else {\n+ /* clear data flags */\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);\n+\n+ /* Check data inhibit flag */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_CMD)) {\n+ return SDH_STAT_BUSY;\n+ }\n+ }\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH enable interrupt\n+ *\n+ * @param cmd: Transfer data config pointer\n+ *\n+ * @return SDH status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd)\n+{\n+ if (cmd->respType != SDH_RESP_NONE) {\n+ cmd->response[0U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_0);\n+ cmd->response[1U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_2);\n+ cmd->response[2U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_4);\n+ cmd->response[3U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_6);\n+ }\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH read data port\n+ *\n+ * @param dataCfg: Transfer data config pointer\n+ *\n+ * @return Read length\n+ *\n+*******************************************************************************/\n+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t totalLen, recvLen = 0;\n+\n+ totalLen = (dataCfg->blockCount * dataCfg->blockSize);\n+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+\n+ if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {\n+ do {\n+ dataCfg->rxData[dataCfg->rxDataLen++] = BL_RD_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0);\n+ recvLen += 4;\n+ } while (recvLen < totalLen);\n+ }\n+\n+ return recvLen;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH read data port\n+ *\n+ * @param dataCfg: Transfer data config pointer\n+ *\n+ * @return Read length\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg)\n+{\n+ uint32_t intStatus = 0U;\n+ SDH_Stat_Type error = SDH_STAT_SUCCESS;\n+\n+ /* Make sure the buffer size is 4 byte aligned */\n+ if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {\n+ dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));\n+ }\n+\n+ while (!(intStatus & (SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {\n+ intStatus = SDH_GetIntStatus();\n+ }\n+\n+ /* during std tuning process, software do not need to read data, but wait BRR is enough */\n+ if ((dataCfg->dataType == SDH_TRANS_DATA_TUNING) && (intStatus & SDH_INT_BUFFER_READ_READY)) {\n+ SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);\n+ return SDH_STAT_SUCCESS;\n+ } else if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {\n+ SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);\n+ /* if tuning error occur ,return directly */\n+ error = SDH_STAT_TUNE_ERROR;\n+ } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {\n+ if (!(dataCfg->enableIgnoreError)) {\n+ error = SDH_STAT_RECV_DATA_FAIL;\n+ }\n+\n+ /* clear data error flag */\n+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);\n+ }\n+\n+ if (error == SDH_STAT_SUCCESS) {\n+ SDH_ReadDataPort(dataCfg);\n+ /* clear buffer read ready */\n+ SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);\n+ intStatus = 0U;\n+ }\n+\n+ /* Clear data complete flag after the last read operation. */\n+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);\n+\n+ return error;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH write data port\n+ *\n+ * @param dataCfg: Transfer data config pointer\n+ *\n+ * @return write length\n+ *\n+*******************************************************************************/\n+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);\n+\n+ if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {\n+ BL_WR_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0, dataCfg->txData[dataCfg->txDataLen++]);\n+ }\n+\n+ return 4;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH write data port\n+ *\n+ * @param dataCfg: Transfer data config pointer\n+ *\n+ * @return Write length\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg)\n+{\n+ uint32_t totalLen;\n+ uint32_t txLen = 0U, intStatus = 0U;\n+ SDH_Stat_Type error = SDH_STAT_SUCCESS;\n+\n+ /* Make sure the buffer size is 4 byte aligned */\n+ if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {\n+ dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));\n+ }\n+\n+ totalLen = (dataCfg->blockCount * dataCfg->blockSize);\n+\n+ while ((error == SDH_STAT_SUCCESS) && (txLen < totalLen)) {\n+ while (!(intStatus & (SDH_INT_BUFFER_WRITE_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {\n+ intStatus = SDH_GetIntStatus();\n+ }\n+\n+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {\n+ SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);\n+ /* if tuning error occur ,return directly */\n+ error = SDH_STAT_TUNE_ERROR;\n+ } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {\n+ if (!(dataCfg->enableIgnoreError)) {\n+ error = SDH_STAT_RECV_DATA_FAIL;\n+ }\n+\n+ /* clear data error flag */\n+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);\n+ }\n+\n+ if (error == SDH_STAT_SUCCESS) {\n+ txLen += SDH_WriteDataPort(dataCfg);\n+ /* clear buffer read ready */\n+ SDH_ClearIntStatus(SDH_INT_BUFFER_WRITE_READY);\n+ intStatus = 0U;\n+ }\n+ }\n+\n+ while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS))) {\n+ intStatus = SDH_GetIntStatus();\n+ }\n+\n+ if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {\n+ if (!(dataCfg->enableIgnoreError)) {\n+ error = SDH_STAT_RECV_DATA_FAIL;\n+ }\n+\n+ /* clear data error flag */\n+ SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);\n+ }\n+\n+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);\n+\n+ return error;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH send command\n+ *\n+ * @param cmd: command config pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd)\n+{\n+ uint32_t tmpVal;\n+ uint32_t flag = cmd->flag;\n+ //uint32_t flag = 0;\n+\n+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);\n+\n+ if (((tmpVal & SDH_PRESENT_FLAG_CMD_INHBIT) == 0U) && (cmd->type != SDH_CMD_EMPTY)) {\n+ /* Define the flag corresponding to each response type. */\n+ switch (cmd->respType) {\n+ case SDH_RESP_NONE:\n+ break;\n+\n+ case SDH_RESP_R1: /* Response 1 */\n+ case SDH_RESP_R5: /* Response 5 */\n+ case SDH_RESP_R6: /* Response 6 */\n+ case SDH_RESP_R7: /* Response 7 */\n+ flag |= (SDH_TRANS_FLAG_RESP_48BITS | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);\n+ break;\n+\n+ case SDH_RESP_R1B: /* Response 1 with busy */\n+ case SDH_RESP_R5B: /* Response 5 with busy */\n+ flag |= (SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);\n+ break;\n+\n+ case SDH_RESP_R2: /* Response 2 */\n+ flag |= (SDH_TRANS_FLAG_RESP_136BITS | SDH_TRANS_FLAG_EN_CRC_CHECK);\n+ break;\n+\n+ case SDH_RESP_R3: /* Response 3 */\n+ case SDH_RESP_R4: /* Response 4 */\n+ flag |= (SDH_TRANS_FLAG_RESP_48BITS);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Config command index */\n+ tmpVal = flag >> 16;\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_TYPE, cmd->type);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_INDEX, cmd->index);\n+\n+ /* Config command argument */\n+ BL_WR_REG(SDH_BASE, SDH_SD_ARG_LOW, cmd->argument);\n+\n+ /* Config command index */\n+ BL_WR_REG16(SDH_BASE, SDH_SD_CMD, tmpVal);\n+ }\n+\n+ /* FIXME:how to enable again */\n+ if (cmd->type == SDH_CMD_EMPTY) {\n+ SDH_DisableIntSource(SDH_INT_CMD_COMPLETED);\n+ }\n+}\n+/****************************************************************************/ /**\n+ * @brief SDH wait command send done\n+ *\n+ * @param cmd: Command config pointer\n+ *\n+ * @return Command deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd)\n+{\n+ uint32_t intStatus = 0U;\n+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;\n+\n+ /* Wait command complete or encounters error. */\n+ while (!(intStatus & (SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR))) {\n+ intStatus = SDH_GetIntStatus();\n+ }\n+\n+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {\n+ stat = SDH_STAT_TUNE_ERROR;\n+ } else if ((intStatus & SDH_INT_CMD_ERRORS) != 0U) {\n+ stat = SDH_STAT_SEND_CMD_FAIL;\n+ }\n+\n+ /* Receive response when command completes successfully. */\n+ if (stat == SDH_STAT_SUCCESS) {\n+ stat = SDH_GetCmdResp(cmd);\n+ }\n+\n+ SDH_ClearIntStatus(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR);\n+\n+ return stat;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH transfer data\n+ *\n+ * @param dataCfg: Data config pointer\n+ * @param enDMA: Whether enable DMA\n+ *\n+ * @return command deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA)\n+{\n+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;\n+ uint32_t intStatus = 0U;\n+\n+ if (enDMA) {\n+ /* Wait dataCfg complete or encounters error. */\n+ while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |\n+ SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR))) {\n+ intStatus = SDH_GetIntStatus();\n+ }\n+\n+ if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {\n+ stat = SDH_STAT_TUNE_ERROR;\n+ } else if ((intStatus & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) != 0U) {\n+ if ((!(dataCfg->enableIgnoreError)) || (intStatus & SDH_INT_DATA_TIMEOUT)) {\n+ stat = SDH_STAT_SEND_DATA_FAIL;\n+ }\n+ }\n+\n+ /* load dummy data */\n+ if ((dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) && (stat == SDH_STAT_SUCCESS)) {\n+ *(dataCfg->rxData) = bootDummy;\n+ }\n+\n+ SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |\n+ SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR);\n+ } else {\n+ if (dataCfg->rxData) {\n+ stat = SDH_ReadDataPortBlock(dataCfg);\n+ } else {\n+ stat = SDH_WriteDataPortBlock(dataCfg);\n+ }\n+ }\n+\n+ return stat;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH set clock\n+ *\n+ * @param srcClock: Source clock frequency in Hz\n+ * @param busClock: SDH clock frequency in Hz\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock)\n+{\n+ uint16_t tmpVal;\n+ uint16_t div = srcClock / busClock / 2;\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);\n+\n+ /* Disable internal clock*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);\n+\n+ /* Set divdier */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_LO, div & 0xff);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_HI, (div >> 8) & 0x3);\n+ /* 0x1 = Programmable Clock Mode,0x0 = Divided Clock mode */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CLK_GEN_SEL, 0);\n+\n+ /* Enable internal clock*/\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_INT_CLK_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_CLK_EN);\n+\n+ BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);\n+\n+ /* Wait for clock stable */\n+ do {\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, SDH_INT_CLK_STABLE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH disable clock\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_DisableSdClock(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_CLOCK_CTRL);\n+\n+ /* Disable internal clock*/\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);\n+\n+ BL_WR_REG(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);\n+}\n+/****************************************************************************\n+ * @brief SDH init function\n+ *\n+ * @param cfg: SDH config pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_Powon(void)\n+{\n+ uint32_t tmpVal;\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_BUS_POWER);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);\n+}\n+/****************************************************************************\n+ * @brief SDH init function\n+ *\n+ * @param cfg: SDH config pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal;\n+\n+ SDH_SetSdClock(cfg->srcClock, cfg->busClock);\n+ SDH_DisableDMA();\n+\n+ /* Set SDH config */\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);\n+\n+ if (cfg->dataWidth == SDH_DATA_BUS_WIDTH_8BITS) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DATA_WIDTH, cfg->dataWidth);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_HI_SPEED_EN, cfg->highSpeed);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_BUS_VLT, cfg->volt);\n+\n+ BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);\n+\n+ if (cfg->vlot18Enable) {\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_HOST_CTRL_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_UHS_MODE_SEL, cfg->speed);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SDH_V18_EN, cfg->vlot18Enable);\n+ BL_WR_REG16(SDH_BASE, SDH_HOST_CTRL_2, tmpVal);\n+ }\n+\n+ tmpVal = BL_RD_REG(SDH_BASE, SDH_TX_CFG_REG);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TX_INT_CLK_SEL);\n+ BL_WR_REG(SDH_BASE, SDH_TX_CFG_REG, tmpVal);\n+\n+ SDH_EnableStatus();\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SDH_IRQn, SDH_MMC1_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH deinit function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_Deinit(void)\n+{\n+ SDH_DisableDMA();\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH reset function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_Reset(void)\n+{\n+ uint16_t tmpVal;\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SW_RST_ALL);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);\n+\n+ /* Wait for reset done */\n+ do {\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SDH_SW_RST_ALL));\n+}\n+/****************************************************************************/ /**\n+ * @brief SDH set timeout function\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_Set_Timeout(uint8_t tmo)\n+{\n+ uint16_t tmpVal;\n+\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_TIMEOUT_VALUE, tmo);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH get capability\n+ *\n+ * @param capability: None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability)\n+{\n+ /* Get the capability */\n+ capability->maxBlockLength = 512;\n+ capability->maxBlockCount = 65536;\n+ capability->flags = (SDH_CAP_SUPPORT_8BITS |\n+ SDH_CAP_SUPPORT_ADMA2 |\n+ SDH_CAP_SUPPORT_ADMA1 |\n+ SDH_CAP_SUPPORT_HIGHSPEED |\n+ SDH_CAP_SUPPORT_SDMA |\n+ SDH_CAP_SUPPORT_SUS_RES |\n+ SDH_CAP_SUPPORT_VLT33 |\n+ SDH_CAP_SUPPORT_VLT18 |\n+ SDH_CAP_SUPPORT_SBUS_64BITS |\n+ SDH_CAP_SUPPORT_ASYNC_INT |\n+ SDH_CAP_SUPPORT_DDR50 |\n+ SDH_CAP_SUPPORT_SDR104 |\n+ SDH_CAP_SUPPORT_SDR50 |\n+ SDH_CAP_SUPPORT_DRV_TYPE_A |\n+ SDH_CAP_SUPPORT_DRV_TYPE_C |\n+ SDH_CAP_SUPPORT_DRV_TYPE_D |\n+ SDH_CAP_SUPPORT_SDR50_TUNE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH create ADMA1 descriptor\n+ *\n+ * @param adma1Entries: ADMA1 entries pointer\n+ * @param maxEntries: ADMA1 entries size\n+ * @param data: Data buffer to deal with\n+ * @param dataLen: Data length\n+ * @param flag: ADMA setting flag\n+ *\n+ * @return SDH deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,\n+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)\n+{\n+ uint32_t miniEntries, startEntries = 0U;\n+ uint32_t i, dmaBufferLen = 0U;\n+\n+ if (((uintptr_t)data % SDH_ADMA1_ADDRESS_ALIGN) != 0U) {\n+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;\n+ }\n+\n+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {\n+ return SDH_STAT_NOT_SUPPORT;\n+ }\n+\n+ /* TODO:align */\n+ /* Make sure the buffer size is 4 byte aligned */\n+ if (dataLen % sizeof(uint32_t) != 0U) {\n+ /* make the data length as word-aligned */\n+ dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));\n+ }\n+\n+ /* Check if ADMA descriptor's number is enough. */\n+ if ((dataLen % SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {\n+ miniEntries = dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;\n+ } else {\n+ miniEntries = ((dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);\n+ }\n+\n+ /* ADMA1 needs two descriptors to finish a transfer */\n+ miniEntries <<= 1U;\n+\n+ if (miniEntries + startEntries > maxEntries) {\n+ return SDH_STAT_OUTOF_RANGE;\n+ }\n+\n+ for (i = startEntries; i < (miniEntries + startEntries); i += 2U) {\n+ if (dataLen > SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {\n+ dmaBufferLen = SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;\n+ } else {\n+ dmaBufferLen = dataLen;\n+ }\n+\n+ adma1Entries[i] = (dmaBufferLen << SDH_ADMA1_DESCRIPTOR_LENGTH_POS);\n+ adma1Entries[i] |= SDH_ADMA1_DESC_FLAG_SETLEN;\n+ adma1Entries[i + 1U] = (uintptr_t)(data);\n+ adma1Entries[i + 1U] |= SDH_ADMA1_DESC_FLAG_TRANSFER;\n+ data += (dmaBufferLen / sizeof(uint32_t));\n+ dataLen -= dmaBufferLen;\n+ }\n+\n+ /* Set end of the descriptor */\n+ adma1Entries[i - 1U] |= SDH_ADMA1_DESC_FLAG_END;\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH create ADMA2 descriptor\n+ *\n+ * @param adma2Entries: ADMA2 entries pointer\n+ * @param maxEntries: ADMA2 entries size\n+ * @param data: Data buffer to deal with\n+ * @param dataLen: Data length\n+ * @param flag: ADMA setting flag\n+ *\n+ * @return SDH deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,\n+ const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)\n+{\n+ uint32_t miniEntries, startEntries = 0U;\n+ uint32_t i, dmaBufferLen = 0U;\n+\n+ if (((uintptr_t)data % SDH_ADMA2_ADDRESS_ALIGN) != 0U) {\n+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;\n+ }\n+\n+ /* TODO:align */\n+ /* Make sure the buffer size is 4 byte aligned */\n+ if (dataLen % sizeof(uint32_t) != 0U) {\n+ /* make the data length as word-aligned */\n+ dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));\n+ }\n+\n+ /* Check if ADMA descriptor's number is enough. */\n+ if ((dataLen % SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {\n+ miniEntries = dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;\n+ } else {\n+ miniEntries = ((dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);\n+ }\n+\n+ /* Calculate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor\n+\tdata address and data size is enough */\n+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {\n+ for (i = 0U; i < maxEntries; i++) {\n+ if ((adma2Entries[i].attribute & SDH_ADMA2_DESC_FLAG_VALID) == 0U) {\n+ break;\n+ }\n+ }\n+\n+ startEntries = i;\n+ /* Add one entry for dummy entry */\n+ miniEntries += 1U;\n+ }\n+\n+ if (miniEntries + startEntries > maxEntries) {\n+ return SDH_STAT_OUTOF_RANGE;\n+ }\n+\n+ for (i = startEntries; i < (miniEntries + startEntries); i++) {\n+ if (dataLen > SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {\n+ dmaBufferLen = SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;\n+ } else {\n+ /* TODO:align */\n+ /* Adma don't support 0 data length transfer descriptor */\n+ dmaBufferLen = (dataLen == 0U ? sizeof(uint32_t) : dataLen);\n+ }\n+\n+ /* Each descriptor for ADMA2 is 64-bit in length */\n+ adma2Entries[i].address = (dataLen == 0U) ? (uint32_t)(uintptr_t)&bootDummy : (uint32_t)(uintptr_t)data;\n+ adma2Entries[i].attribute = (dmaBufferLen << SDH_ADMA2_DESCRIPTOR_LENGTH_POS);\n+ adma2Entries[i].attribute |= (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER);\n+ // (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER | SDH_ADMA2_DESC_FLAG_INT);\n+ /* TODO:align */\n+ data += (dmaBufferLen / sizeof(uint32_t));\n+\n+ if (dataLen != 0U) {\n+ dataLen -= dmaBufferLen;\n+ }\n+ }\n+\n+ /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA\n+\tengine will not stop at block gap */\n+ if (flag == SDH_ADMA_FLAG_MULTI_DESC) {\n+ //adma2Entries[startEntries + 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;\n+ adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;\n+ } else {\n+ /* Set the end bit */\n+ adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_END;\n+ }\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH set DMA config\n+ *\n+ * @param dmaCfg: DMA config pointer\n+ * @param data: Data pointer for sending\n+ * @param enAutoCmd23: Whether enable auto command 23\n+ *\n+ * @return DMA config deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23)\n+{\n+ uint16_t tmpVal;\n+\n+ if (dmaCfg->dmaMode == SDH_DMA_MODE_SIMPLE) {\n+ /* Check DMA data buffer address align or not */\n+ if (((uintptr_t)data % SDH_SDMA_LENGTH_ALIGN) != 0U) {\n+ return SDH_STAT_DMA_ADDR_NOT_ALIGN;\n+ }\n+\n+ /* In simple DMA mode if use auto CMD23, address should load to ADMA addr,\n+\t\t and block count should load to DS_ADDR*/\n+ if (enAutoCmd23) {\n+ BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)data);\n+ } else {\n+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uintptr_t)data);\n+ }\n+ } else {\n+ /* When use ADMA, disable simple DMA */\n+ BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uint32_t)0);\n+ BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)(dmaCfg->admaEntries));\n+ }\n+\n+ /* Select DMA mode and config the burst length */\n+ SDH_EnableDMA(dmaCfg->dmaMode);\n+\n+ /* Set DMA burst size and FIFO threshold */\n+ tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SIZE, dmaCfg->fifoThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_BRST_SIZE, dmaCfg->burstSize);\n+ BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP, tmpVal);\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH create DMA entries according to DMA config\n+ *\n+ * @param dmaCfg: DMA config pointer\n+ * @param dataCfg: Data config pointer\n+ * @param flag: ADMA create entries flag\n+ *\n+ * @return Create entries result\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag)\n+{\n+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;\n+\n+ /* TODO:align */\n+ uint32_t bootDummyOffset = (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT ? sizeof(uint32_t) : 0);\n+ const uint32_t *data = (const uint32_t *)((dataCfg->rxData == NULL) ? dataCfg->txData : dataCfg->rxData);\n+ uint32_t dataLen = dataCfg->blockSize * dataCfg->blockCount;\n+\n+ data += bootDummyOffset;\n+ dataLen -= bootDummyOffset;\n+\n+ switch (dmaCfg->dmaMode) {\n+ case SDH_DMA_MODE_SIMPLE:\n+ stat = SDH_STAT_SUCCESS;\n+ break;\n+\n+ case SDH_DMA_MODE_ADMA1:\n+ stat = SDH_CreateADMA1Descriptor(dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);\n+ break;\n+\n+ case SDH_DMA_MODE_ADMA2:\n+ stat = SDH_CreateADMA2Descriptor((SDH_ADMA2_Desc_Type *)dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);\n+ break;\n+\n+ default:\n+ return SDH_STAT_SEND_DATA_FAIL;\n+ }\n+\n+ /* For internal dma, internal DMA configurations should not update the configurations when continous transfer the\n+\t * boot data, only the DMA descriptor need update */\n+ if ((stat == SDH_STAT_SUCCESS) && (dataCfg->dataType != SDH_TRANS_DATA_BOOT_CONT)) {\n+ stat = SDH_SetInternalDmaConfig(dmaCfg, data, dataCfg->enableAutoCommand23);\n+ }\n+\n+ return stat;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH transfer data in blocking way\n+ *\n+ * @param dmaCfg: DMA config pointer\n+ * @param transfer: Transfer config pointer\n+ *\n+ * @return Transfer deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)\n+{\n+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;\n+ SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;\n+ SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;\n+ uint32_t intStatus;\n+ uint8_t enDMA = 1;\n+ uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);\n+ //volatile uint32_t tmp;\n+ /* Check re-tuning request */\n+ intStatus = SDH_GetIntStatus();\n+\n+ if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {\n+ SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);\n+ return SDH_STAT_RETUNE_REQ;\n+ }\n+\n+ /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/\n+ if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {\n+ stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);\n+ }\n+\n+ /* If the DMA desciptor configure fail or not needed , disable it */\n+ if ((stat != SDH_STAT_SUCCESS) || (dmaCfg == NULL)) {\n+ enDMA = 0;\n+ /* Disable DMA, using polling mode in this situation */\n+ SDH_DisableDMA();\n+ }\n+\n+ /* Config the data transfer parameter */\n+ stat = SDH_ConfigDataTranfer(dataCfg);\n+\n+ if (SDH_STAT_SUCCESS != stat) {\n+ return stat;\n+ }\n+\n+ /* Send command first */\n+ if (dataCfg != NULL) {\n+ cmdCfg->flag = SDH_TRANS_FLAG_DATA_PRESENT;\n+ } else {\n+ cmdCfg->flag = 0;\n+ }\n+\n+ SDH_SendCommand(cmdCfg);\n+\n+ /* Wait command done */\n+ if ((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL)) {\n+ stat = SDH_WaitCommandDone(cmdCfg);\n+ }\n+\n+ /*\n+\ttmp = BL_RD_REG16(SDH_BASE,SDH_SD_ADMA_ERROR_STATUS);\n+\tbflb_platform_printf(\"SDH_SD_ADMA_ERROR_STATUS->0x%x!\\r\\n\",tmp);\n+\ttmp = BL_RD_REG16(SDH_BASE,SDH_SD_AUTO_CMD12_ERROR_STATUS);\n+\t*/\n+\n+ /* Wait for transferring data finish */\n+ if ((dataCfg != NULL) && (stat == SDH_STAT_SUCCESS)) {\n+ stat = SDH_TransferDataBlocking(dataCfg, enDMA);\n+ }\n+\n+ return stat;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH transfer data in blocking way\n+ *\n+ * @param handle: SDH handler\n+ * @param dmaCfg: DMA config pointer\n+ * @param transfer: Transfer config pointer\n+ *\n+ * @return Transfer deal status\n+ *\n+*******************************************************************************/\n+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)\n+{\n+ SDH_Stat_Type stat = SDH_STAT_SUCCESS;\n+ SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;\n+ SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;\n+ uint32_t intStatus;\n+ uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);\n+\n+ /* Check re-tuning request */\n+ intStatus = SDH_GetIntStatus();\n+\n+ if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {\n+ SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);\n+ return SDH_STAT_RETUNE_REQ;\n+ }\n+\n+ /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/\n+ if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {\n+ stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);\n+ }\n+\n+ /* If the DMA desciptor configure fail or not needed , disable it */\n+ if (stat != SDH_STAT_SUCCESS) {\n+ /* Disable DMA, using polling mode in this situation */\n+ //SDH_DisableDMA();\n+ return stat;\n+ }\n+\n+ /* Config the data transfer parameter */\n+ stat = SDH_ConfigDataTranfer(dataCfg);\n+\n+ if (SDH_STAT_SUCCESS != stat) {\n+ return stat;\n+ }\n+\n+ /* Send command first */\n+ if (dataCfg != NULL) {\n+ cmdCfg->flag |= SDH_TRANS_FLAG_DATA_PRESENT;\n+ }\n+\n+#if 0\n+\tSDH_SendCommand(cmdCfg);\n+\n+\n+\t/* Wait command done */\n+\tif((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL))\n+\t{\n+\t\tstat = SDH_WaitCommandDone(cmdCfg);\n+\t}\n+\n+#endif\n+\n+ return SDH_STAT_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH install callback function for handler\n+ *\n+ * @param handle: SDH handler\n+ * @param callBack: SDH callBack function\n+ * @param userData: User private data for SDH handler\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle,\n+ const SDH_Trans_Callback_Cfg_Type *callBack, void *userData)\n+{\n+ /* Zero the handle. */\n+ ARCH_MemSet(handle, 0, sizeof(SDH_Handle_Cfg_Type));\n+\n+ /* Set the callback. */\n+ handle->callBack.SDH_CallBack_CardInserted = callBack->SDH_CallBack_CardInserted;\n+ handle->callBack.SDH_CallBack_CardRemoved = callBack->SDH_CallBack_CardRemoved;\n+ handle->callBack.SDH_CallBack_SdioInterrupt = callBack->SDH_CallBack_SdioInterrupt;\n+ handle->callBack.SDH_CallBack_BlockGap = callBack->SDH_CallBack_BlockGap;\n+ handle->callBack.SDH_CallBack_TransferFinished = callBack->SDH_CallBack_TransferFinished;\n+ handle->callBack.SDH_CMDCallBack_TransferFinished = callBack->SDH_CMDCallBack_TransferFinished;\n+ handle->callBack.SDH_CallBack_ReTuning = callBack->SDH_CallBack_ReTuning;\n+ handle->callBack.SDH_CallBack_Vendor = callBack->SDH_CallBack_ReTuning;\n+ handle->userData = userData;\n+\n+ /* Save the handle in global variables */\n+ sdhHandle = handle;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SDH interrupt handle\n+ *\n+ * @param intPeriph: Select the peripheral\n+ * @param handle: SDH handler\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)\n+{\n+ uint32_t intFlag, intMask;\n+\n+ intFlag = SDH_GetIntStatus();\n+ intMask = SDH_GetIntEnableStatus();\n+ intFlag &= intMask;\n+\n+ if (NULL == handle) {\n+ SDH_ClearIntStatus(intFlag);\n+ return;\n+ }\n+\n+ handle->intFlag = intFlag;\n+\n+ /* Card insert interrupt */\n+ if (intFlag & SDH_INT_CARD_INSERT) {\n+ if (NULL != handle->callBack.SDH_CallBack_CardInserted) {\n+ handle->callBack.SDH_CallBack_CardInserted(handle->userData);\n+ }\n+ }\n+\n+ /* Card remove interrupt */\n+ if (intFlag & SDH_INT_CARD_REMOVE) {\n+ if (NULL != handle->callBack.SDH_CallBack_CardRemoved) {\n+ handle->callBack.SDH_CallBack_CardRemoved(handle->userData);\n+ }\n+ }\n+\n+ /* Command error interrupt */\n+ if (intFlag & (SDH_INT_CMD_ERRORS)) {\n+ if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished) {\n+ handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SEND_CMD_FAIL, handle->userData);\n+ }\n+ }\n+\n+ /* Command success interrupt */\n+ if (intFlag & SDH_INT_CMD_COMPLETED) {\n+ if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished &&\n+ NULL == handle->dataCfg) {\n+ /* Only deal with pure command, user need check response to make sure in SDH_CallBack_TransferFinished */\n+ handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);\n+ }\n+ }\n+\n+ /* Data error interrupt */\n+ if (intFlag & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) {\n+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {\n+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SEND_DATA_FAIL, handle->userData);\n+ }\n+ }\n+\n+ /* Data success interrupt*/\n+ if (intFlag & SDH_INT_DATA_COMPLETED) {\n+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {\n+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);\n+ }\n+ }\n+\n+ /* Card interrupt */\n+ if (intFlag & SDH_INT_CARD) {\n+ if (handle->callBack.SDH_CallBack_SdioInterrupt) {\n+ handle->callBack.SDH_CallBack_SdioInterrupt(handle->userData);\n+ }\n+ }\n+\n+ /* Buffer read ready interrupt*/\n+ if (intFlag & SDH_INT_BUFFER_READ_READY) {\n+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {\n+ handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);\n+ } else {\n+ handle->dataCfg->rxDataLen += SDH_ReadDataPort(handle->dataCfg);\n+ }\n+ }\n+\n+ /* Buffer write ready interrupt */\n+ if (intFlag & SDH_INT_BUFFER_WRITE_READY) {\n+ if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {\n+ handle->dataCfg->txDataLen += SDH_WriteDataPort(handle->dataCfg);\n+ }\n+ }\n+\n+ /* DMA success interrupt*/\n+ if (intFlag & SDH_INT_DMA_COMPLETED) {\n+ if (handle->dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {\n+ *(handle->dataCfg->rxData) = bootDummy;\n+ }\n+ }\n+\n+ /* Block gap event interrupt */\n+ if (intFlag & SDH_INT_BLK_GAP_EVENT) {\n+ if (handle->callBack.SDH_CallBack_BlockGap) {\n+ handle->callBack.SDH_CallBack_BlockGap(handle->userData);\n+ }\n+ }\n+\n+ /* Re-tuning event interrupt */\n+ if (intFlag & SDH_INT_RETUNE_EVENT) {\n+ if (handle->callBack.SDH_CallBack_ReTuning) {\n+ handle->callBack.SDH_CallBack_ReTuning(handle->userData);\n+ }\n+ }\n+\n+ /* Vendor specified interrupt */\n+ if (intFlag & (SDH_INT_SPI_ERROR |\n+ SDH_INT_AXI_RESP_ERROR |\n+ SDH_INT_CPL_TIMEOUT_ERROR |\n+ SDH_INT_CRC_STAT_ERROR)) {\n+ if (handle->callBack.SDH_CallBack_Vendor) {\n+ handle->callBack.SDH_CallBack_Vendor(handle->userData);\n+ }\n+ }\n+\n+ SDH_ClearIntStatus(intFlag);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SDH interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+void SDH_MMC1_IRQHandler(void)\n+{\n+ SDH_IntHandler(SDH_IRQn, sdhHandle);\n+}\n+#endif\n+\n+/*@} end of group SDH_Public_Functions */\n+\n+/*@} end of group SDH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_dbg.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_dbg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_dbg.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a5496837e46794d82f0da2f887be02ca7e518ad1\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_dbg.c\n@@ -0,0 +1,163 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sec_dbg.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_sec_dbg.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_DBG\n+ * @{\n+ */\n+\n+/** @defgroup SEC_DBG_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Private_Macros */\n+\n+/** @defgroup SEC_DBG_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Private_Types */\n+\n+/** @defgroup SEC_DBG_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Private_Variables */\n+\n+/** @defgroup SEC_DBG_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Global_Variables */\n+\n+/** @defgroup SEC_DBG_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SEC_DBG_Private_Fun_Declaration */\n+\n+/** @defgroup SEC_DBG_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Dbg read chip ID\n+ *\n+ * @param id[8]: chip ID buffer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Dbg_Read_Chip_ID(uint8_t id[8])\n+{\n+ uint32_t idLow, idHigh;\n+\n+ idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW);\n+ BL_WRWD_TO_BYTEP(id, idLow);\n+\n+ idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH);\n+ BL_WRWD_TO_BYTEP((id + 4), idHigh);\n+}\n+\n+/***************************************************************************** /\n+ * @brief Sec Dbg set PWD\n+ *\n+ * @param pwd: PWD buffer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Dbg_Set_Dbg_Pwd(const uint32_t pwd[4])\n+{\n+ BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_LOW, pwd[0]);\n+ BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_HIGH, pwd[1]);\n+ BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_LOW, pwd[2]);\n+ BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_HIGH, pwd[3]);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Dbg read debug mode\n+ *\n+ * @param None\n+ *\n+ * @return debug mode status\n+ *\n+*******************************************************************************/\n+uint32_t Sec_Dbg_Read_Dbg_Mode(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Dbg read debug enable status\n+ *\n+ * @param None\n+ *\n+ * @return enable status\n+ *\n+*******************************************************************************/\n+uint32_t Sec_Dbg_Read_Dbg_Enable(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Dbg Set debug trigger status\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Dbg_Set_Dbg_Trigger(void)\n+{\n+ uint32_t tmpVal=0;\n+ tmpVal=BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS);\n+ tmpVal=BL_SET_REG_BIT(tmpVal,SEC_DBG_SD_DBG_PWD_TRIG);\n+ BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS,tmpVal);\n+}\n+\n+/*@} end of group SEC_DBG_Public_Functions */\n+\n+/*@} end of group SEC_DBG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8e12b99b168d75d51fad252ab0352618128908b0\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c\n@@ -0,0 +1,5135 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sec_eng.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_sec_eng.h\"\n+#include \"bl808_tzc_sec.h\"\n+#include \"bl808_l1c.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SEC_ENG\n+ * @{\n+ */\n+\n+/** @defgroup SEC_ENG_Private_Macros\n+ * @{\n+ */\n+#define PUT_UINT32_BE(n, b, i) \\\n+ { \\\n+ (b)[(i)] = (uint8_t)((n) >> 24); \\\n+ (b)[(i) + 1] = (uint8_t)((n) >> 16); \\\n+ (b)[(i) + 2] = (uint8_t)((n) >> 8); \\\n+ (b)[(i) + 3] = (uint8_t)((n)); \\\n+ }\n+#define PUT_UINT32(n, b, i) \\\n+ { \\\n+ (b)[(i) + 3] = (uint8_t)((n) >> 24); \\\n+ (b)[(i) + 2] = (uint8_t)((n) >> 16); \\\n+ (b)[(i) + 1] = (uint8_t)((n) >> 8); \\\n+ (b)[(i) + 0] = (uint8_t)((n)); \\\n+ }\n+#define PUT_UINT64_BE(n, b, i) \\\n+ { \\\n+ (b)[(i)] = (uint8_t)((n) >> 56); \\\n+ (b)[(i) + 1] = (uint8_t)((n) >> 48); \\\n+ (b)[(i) + 2] = (uint8_t)((n) >> 40); \\\n+ (b)[(i) + 3] = (uint8_t)((n) >> 32); \\\n+ (b)[(i) + 4] = (uint8_t)((n) >> 24); \\\n+ (b)[(i) + 5] = (uint8_t)((n) >> 16); \\\n+ (b)[(i) + 6] = (uint8_t)((n) >> 8); \\\n+ (b)[(i) + 7] = (uint8_t)((n)); \\\n+ }\n+#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100 * 320 * 1000)\n+#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 320 * 1000)\n+\n+/*@} end of group SEC_ENG_Private_Macros */\n+\n+/** @defgroup SEC_ENG_Private_Types\n+ * @{\n+ */\n+struct pka0_pld_cfg {\n+ union {\n+ struct\n+ {\n+ uint32_t size : 12; /*[11: 0], r/w, 0x0 */\n+ uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */\n+ uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */\n+ uint32_t op : 7; /*[30:24], r/w, 0x0 */\n+ uint32_t last_op : 1; /*[31:31], r/w, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_pldi_cfg {\n+ union {\n+ struct\n+ {\n+ uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */\n+ uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */\n+ uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */\n+ uint32_t op : 7; /*[30:24], r/w, 0x0 */\n+ uint32_t last_op : 1; /*[31:31], r/w, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_common_op_first_cfg {\n+ union {\n+ struct\n+ {\n+ uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */\n+ uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */\n+ uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */\n+ uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */\n+ uint32_t op : 7; /*[30:24], r/w, 0x0 */\n+ uint32_t last_op : 1; /*[31:31], r/w, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_common_op_snd_cfg_S1_only {\n+ union {\n+ struct\n+ {\n+ uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */\n+ uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */\n+ uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */\n+ uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_common_op_snd_cfg_S2_only {\n+ union {\n+ struct\n+ {\n+ uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */\n+ uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */\n+ uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_common_op_snd_cfg_S1_S2 {\n+ union {\n+ struct\n+ {\n+ uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */\n+ uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */\n+ uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */\n+ uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */\n+ uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+struct pka0_bit_shift_op_cfg {\n+ union {\n+ struct\n+ {\n+ uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */\n+ uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */\n+ } BF;\n+ uint32_t WORD;\n+ } value;\n+};\n+\n+/*@} end of group SEC_ENG_Private_Types */\n+\n+/** @defgroup SEC_ENG_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group SEC_ENG_Private_Variables */\n+\n+/** @defgroup SEC_ENG_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SEC_ENG_Global_Variables */\n+\n+/** @defgroup SEC_ENG_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SEC_ENG_Private_Fun_Declaration */\n+\n+/** @defgroup SEC_ENG_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 initialization function\n+ *\n+ * @param shaCtx: SHA256 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param shaType: SHA type\n+ * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes\n+ * @param padding[16]: SHA padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16])\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+ CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType));\n+\n+ /* Deal SHA control register to set SHA mode */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (shaType < 8) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7);\n+ }\n+\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ /* Clear context */\n+ ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx));\n+\n+ /* Init temp buffer and padding buffer */\n+ shaCtx->shaBuf = shaTmpBuf;\n+ shaCtx->shaPadding = padding;\n+ ARCH_MemSet(shaCtx->shaPadding, 0, 64);\n+ ARCH_MemSet(shaCtx->shaPadding, 0x80, 1);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 initialization function\n+ *\n+ * @param shaCtx: SHA512 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param shaType: SHA type\n+ * @param shaTmpBuf[16]: SHA temp buffer for store data that is less that 128 bytes\n+ * @param padding[16]: SHA padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint64_t shaTmpBuf[16], uint64_t padding[16])\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+ CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType));\n+\n+ /* Deal SHA control register to set SHA mode */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (shaType < 8) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7);\n+ }\n+\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ /* Clear context */\n+ ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Ctx));\n+\n+ /* Init temp buffer and padding buffer */\n+ shaCtx->shaBuf = shaTmpBuf;\n+ shaCtx->shaPadding = padding;\n+ ARCH_MemSet(shaCtx->shaPadding, 0, 128);\n+ ARCH_MemSet(shaCtx->shaPadding, 0x80, 1);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 initialization function\n+ *\n+ * @param md5Ctx: MD5 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param shaType: SHA type\n+ * @param md5TmpBuf[16]: MD5 temp buffer for store data that is less that 64 bytes\n+ * @param padding[16]: MD5 padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t md5TmpBuf[16], uint32_t padding[16])\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+ CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType));\n+\n+ /* Deal SHA control register to set SHA mode */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (shaType < 8) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7);\n+ }\n+\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ /* Clear context */\n+ ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Ctx));\n+\n+ /* Init temp buffer and padding buffer */\n+ md5Ctx->md5Buf = md5TmpBuf;\n+ md5Ctx->md5Padding = padding;\n+ ARCH_MemSet(md5Ctx->md5Padding, 0, 64);\n+ ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA start function\n+ *\n+ * @param shaNo: SHA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Set SHA enable */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ /* Hash sel 0 for new start */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL);\n+\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 update input data function\n+ *\n+ * @param shaCtx: SHA256 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: SHA input data pointer, and the address should be word align\n+ * @param len: SHA input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last SHA state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed);\n+\n+ left = shaCtx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ shaCtx->total[0] += (uint32_t)len;\n+ shaCtx->total[0] &= 0xFFFFFFFF;\n+\n+ if (shaCtx->total[0] < (uint32_t)len) {\n+ shaCtx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);\n+ /* Set data source address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf);\n+\n+ /* Set data length */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ shaCtx->shaFeed = 1;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 64;\n+ len = len % 64;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last sha state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed);\n+\n+ /* Fill data */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ input += (fill * 64);\n+ shaCtx->shaFeed = 1;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 update input data function\n+ *\n+ * @param shaCtx: SHA512 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: SHA input data pointer, and the address should be word align\n+ * @param len: SHA input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ if ((((uintptr_t)input) & 0x07) != 0) {\n+ return ERROR;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last SHA state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed);\n+\n+ left = shaCtx->total[0] & 0x7F;\n+ fill = 128 - left;\n+\n+ shaCtx->total[0] += (uint64_t)len;\n+\n+ if (shaCtx->total[0] < (uint64_t)len) {\n+ shaCtx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);\n+ /* Set data source address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf);\n+\n+ /* Set data length */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1);\n+\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ shaCtx->shaFeed = 1;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 128;\n+ len = len % 128;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last sha state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed);\n+\n+ /* Fill data */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ input += (fill * 128);\n+ shaCtx->shaFeed = 1;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 update input data function\n+ *\n+ * @param md5Ctx: MD5 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: SHA input data pointer, and the address should be word align\n+ * @param len: SHA input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last SHA state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed);\n+\n+ left = md5Ctx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ md5Ctx->total[0] += (uint32_t)len;\n+ md5Ctx->total[0] &= 0xFFFFFFFF;\n+\n+ if (md5Ctx->total[0] < (uint32_t)len) {\n+ md5Ctx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill);\n+\n+ /* Set data source address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)md5Ctx->md5Buf);\n+\n+ /* Set data length */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ md5Ctx->md5Feed = 1;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 64;\n+ len = len % 64;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* SHA need set se_sha_sel to 1 to keep the last sha state */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed);\n+\n+ /* Fill data */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ input += (fill * 64);\n+ md5Ctx->md5Feed = 1;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 finish to get output function\n+ *\n+ * @param shaCtx: SHA256 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: SHA output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ uint8_t shaMode;\n+ uint8_t msgLen[8];\n+ uint8_t *p = (uint8_t *)hash;\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);\n+ low = (shaCtx->total[0] << 3);\n+\n+ PUT_UINT32_BE(high, msgLen, 0);\n+ PUT_UINT32_BE(low, msgLen, 4);\n+\n+ last = shaCtx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8);\n+ Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE);\n+ /* Copy SHA value */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ if (shaMode == SEC_ENG_SHA256) {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ }\n+ }\n+\n+ /* Disable SHA engine*/\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 finish to get output function\n+ *\n+ * @param shaCtx: SHA512 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: SHA output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint64_t last, padn;\n+ uint64_t high, low;\n+ uint8_t shaMode;\n+ uint8_t msgLen[16];\n+ uint8_t *p = (uint8_t *)hash;\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3);\n+ low = (shaCtx->total[0] << 3);\n+\n+ PUT_UINT64_BE(high, msgLen, 0);\n+ PUT_UINT64_BE(low, msgLen, 8);\n+\n+ last = shaCtx->total[0] & 0x7F;\n+ padn = (last < 112) ? (112 - last) : (240 - last);\n+\n+ Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 16);\n+ Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 16);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE);\n+ /* Copy SHA value */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_0);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_1);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_2);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_3);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ if (shaMode == SEC_ENG_SHA512T256 || shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ if (shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_4);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_5);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ if (shaMode == SEC_ENG_SHA512) {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_6);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_7);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ }\n+ }\n+ }\n+\n+ /* Disable SHA engine*/\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 finish to get output function\n+ *\n+ * @param md5Ctx: MD5 context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: MD5 output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ uint8_t msgLen[8];\n+ uint8_t *p = (uint8_t *)hash;\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3);\n+ low = (md5Ctx->total[0] << 3);\n+\n+ PUT_UINT32(low, msgLen, 0);\n+ PUT_UINT32(high, msgLen, 4);\n+\n+ last = md5Ctx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ ARCH_MemCpy_Fast(md5Ctx->md5Padding, msgLen, 8);\n+ Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, 8);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ /* Copy SHA value */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3);\n+ *p++ = (tmpVal & 0xff);\n+ *p++ = ((tmpVal >> 8) & 0xff);\n+ *p++ = ((tmpVal >> 16) & 0xff);\n+ *p++ = ((tmpVal >> 24) & 0xff);\n+\n+ /* Disable SHA engine*/\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA enable link mode and set link config address\n+ *\n+ * @param shaNo: SHA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Enable sha and enable link mode */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA disable link mode\n+ *\n+ * @param shaNo: SHA ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Disable sha and disable link mode */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 link mode initialization function\n+ *\n+ * @param shaCtx: SHA256 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param linkAddr: SHA link configure address\n+ * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes\n+ * @param padding[16]: SHA padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16])\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Clear context */\n+ ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx));\n+\n+ /* Init temp buffer,padding buffer and link address */\n+ shaCtx->shaBuf = shaTmpBuf;\n+ shaCtx->shaPadding = padding;\n+ ARCH_MemSet(shaCtx->shaPadding, 0, 64);\n+ ARCH_MemSet(shaCtx->shaPadding, 0x80, 1);\n+ shaCtx->linkAddr = linkAddr;\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 link mode initialization function\n+ *\n+ * @param shaCtx: SHA512 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param linkAddr: SHA link configure address\n+ * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 128 bytes\n+ * @param padding[16]: SHA padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint64_t shaTmpBuf[16], uint64_t padding[16])\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Clear context */\n+ ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Link_Ctx));\n+\n+ /* Init temp buffer,padding buffer and link address */\n+ shaCtx->shaBuf = shaTmpBuf;\n+ shaCtx->shaPadding = padding;\n+ ARCH_MemSet(shaCtx->shaPadding, 0, 128);\n+ ARCH_MemSet(shaCtx->shaPadding, 0x80, 1);\n+ shaCtx->linkAddr = linkAddr;\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 link mode initialization function\n+ *\n+ * @param shaCtx: SHA256 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param linkAddr: MD5 link configure address\n+ * @param shaTmpBuf[16]: MD5 temp buffer for store data that is less than 64 bytes\n+ * @param padding[16]: MD5 padding buffer for store padding data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t md5TmpBuf[16], uint32_t padding[16])\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Clear context */\n+ ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Link_Ctx));\n+\n+ /* Init temp buffer,padding buffer and link address */\n+ md5Ctx->md5Buf = md5TmpBuf;\n+ md5Ctx->md5Padding = padding;\n+ ARCH_MemSet(md5Ctx->md5Padding, 0, 64);\n+ ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1);\n+ md5Ctx->linkAddr = linkAddr;\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 link mode update input data function\n+ *\n+ * @param shaCtx: SHA256 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: SHA input data pointer, and the address should be word align\n+ * @param len: SHA input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);\n+\n+ left = shaCtx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ shaCtx->total[0] += (uint32_t)len;\n+ shaCtx->total[0] &= 0xFFFFFFFF;\n+\n+ if (shaCtx->total[0] < (uint32_t)len) {\n+ shaCtx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);\n+ /* Set data source address */\n+ *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf;\n+\n+ /* Set data length */\n+ *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 64;\n+ len = len % 64;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Fill data */\n+ *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input;\n+ *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ input += (fill * 64);\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 link mode update input data function\n+ *\n+ * @param shaCtx: SHA512 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: SHA input data pointer, and the address should be word align\n+ * @param len: SHA input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);\n+\n+ left = shaCtx->total[0] & 0x7F;\n+ fill = 128 - left;\n+\n+ shaCtx->total[0] += (uint64_t)len;\n+\n+ if (shaCtx->total[0] < (uint64_t)len) {\n+ shaCtx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);\n+ /* Set data source address */\n+ *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf;\n+\n+ /* Set data length */\n+ *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 128;\n+ len = len % 128;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Fill data */\n+ *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input;\n+ *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ input += (fill * 128);\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 link mode update input data function\n+ *\n+ * @param md5Ctx: MD5 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param input: MD5 input data pointer, and the address should be word align\n+ * @param len: MD5 input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t fill;\n+ uint32_t left;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ if (len == 0) {\n+ return SUCCESS;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr);\n+\n+ left = md5Ctx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ md5Ctx->total[0] += (uint32_t)len;\n+ md5Ctx->total[0] &= 0xFFFFFFFF;\n+\n+ if (md5Ctx->total[0] < (uint32_t)len) {\n+ md5Ctx->total[1]++;\n+ }\n+\n+ if (left && len >= fill) {\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill);\n+\n+ /* Set data source address */\n+ *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)md5Ctx->md5Buf;\n+\n+ /* Set data length */\n+ *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = 1;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40;\n+ input += fill;\n+ len -= fill;\n+ left = 0;\n+ }\n+\n+ fill = len / 64;\n+ len = len % 64;\n+\n+ if (fill > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Fill data */\n+ *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)input;\n+ *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = fill;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ input += (fill * 64);\n+ /* Choose accumulating last hash in the next time */\n+ *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40;\n+ }\n+\n+ if (len > 0) {\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Copy left data into temp buffer */\n+ ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len);\n+ }\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CRC16 link mode work input data function\n+ *\n+ * @param shaNo: SHA ID type\n+ * @param linkAddr: CRC16 link mode address\n+ * @param input: CRC16 input data pointer, and the address should be word align\n+ * @param len: CRC16 input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo));\n+\n+ /* Link address should word align */\n+ if ((linkAddr & 0x03) != 0) {\n+ return ERROR;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr);\n+\n+ /* Change source buffer address and destination buffer address */\n+ *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in;\n+\n+ /* Set data length, 16 bits per block */\n+ *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 16;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* CRC16 code len is 16 bits */\n+ ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief CRC32 link mode work input data function\n+ *\n+ * @param shaNo: SHA ID type\n+ * @param linkAddr: CRC32 link mode address\n+ * @param input: CRC32 input data pointer, and the address should be word align\n+ * @param len: CRC32 input data length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out)\n+{\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo));\n+\n+ /* Link address should word align */\n+ if ((linkAddr & 0x03) != 0) {\n+ return ERROR;\n+ }\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr);\n+\n+ /* Change source buffer address and destination buffer address */\n+ *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in;\n+\n+ /* Set data length , 32 bits per block*/\n+ *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 32;\n+\n+ /* Trigger */\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* CRC32 code len is 32 bits */\n+ ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 4);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA256 link mode finish to get output function\n+ *\n+ * @param shaCtx: SHA256 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: SHA output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ uint8_t msgLen[8];\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);\n+\n+ high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);\n+ low = (shaCtx->total[0] << 3);\n+\n+ PUT_UINT32_BE(high, msgLen, 0);\n+ PUT_UINT32_BE(low, msgLen, 4);\n+\n+ last = shaCtx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Get result according to SHA mode,result is placed in (link address + offset:8) */\n+ switch (shaMode) {\n+ case 0:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32);\n+ break;\n+\n+ case 1:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28);\n+ break;\n+\n+ case 2:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20);\n+ break;\n+\n+ case 3:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Choose new hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SHA512 link mode finish to get output function\n+ *\n+ * @param shaCtx: SHA512 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: SHA output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint64_t last, padn;\n+ uint64_t high, low;\n+ uint8_t msgLen[16];\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);\n+\n+ high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3);\n+ low = (shaCtx->total[0] << 3);\n+\n+ PUT_UINT64_BE(high, msgLen, 0);\n+ PUT_UINT64_BE(low, msgLen, 8);\n+\n+ last = shaCtx->total[0] & 0x7F;\n+ padn = (last < 112) ? (112 - last) : (240 - last);\n+\n+ Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, msgLen, 16);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Get result according to SHA mode,result is placed in (link address + offset:8) */\n+ switch (shaMode) {\n+ case 4:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 64);\n+ break;\n+\n+ case 5:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 48);\n+ break;\n+\n+ case 6:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28);\n+ break;\n+\n+ case 7:\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Choose new hash in the next time */\n+ *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief MD5 link mode finish to get output function\n+ *\n+ * @param md5Ctx: MD5 link mode context pointer\n+ * @param shaNo: SHA ID type\n+ * @param hash: MD5 output data of SHA result\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash)\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ uint8_t msgLen[8];\n+ uint32_t SHAx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr);\n+\n+ high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3);\n+ low = (md5Ctx->total[0] << 3);\n+\n+ PUT_UINT32(low, msgLen, 0);\n+ PUT_UINT32(high, msgLen, 4);\n+\n+ last = md5Ctx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn);\n+\n+ /* Wait for shaPadding idle */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, msgLen, 8);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));\n+\n+ ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(md5Ctx->linkAddr + 8), 16);\n+\n+ /* Choose new hash in the next time */\n+ *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) &= ~0x40;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 request SHA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if ((tmpVal & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x02);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if ((tmpVal & 0x03) == 0x01) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 release SHA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 request SHA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if ((tmpVal & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x04);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if ((tmpVal & 0x03) == 0x02) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 release SHA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES initialization function\n+ *\n+ * @param aesCtx: AES context pointer\n+ * @param aesNo: AES ID type\n+ * @param aesType: AES type:ECB,CTR,CBC\n+ * @param keyType: AES key type:128,256,192\n+ * @param enDecType: AES encryption or decryption\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+ CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType));\n+ CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType));\n+ CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType));\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ /* Set AES mode type*/\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE, aesType);\n+\n+ /* Set AES key type */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE, keyType);\n+\n+ /* Set AES encryption or decryption */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_DEC_EN, enDecType);\n+\n+ /* Clear dec_key_sel to select new key */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL);\n+\n+ /* Clear aes iv sel to select new iv */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL);\n+\n+ /* Clear AES interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T);\n+\n+ /* Enable AES */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN);\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ /* Clear AES context */\n+ memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx));\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES enable function,set AES bigendian\n+ *\n+ * @param aesNo: AES ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ /* set 0x0f to 0x1f for xts mode */\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x1f);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES enable function,set AES littleendian\n+ *\n+ * @param aesNo: AES ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ /* set 0x00 to 0x0f for xts mode */\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x10);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES enable link mode\n+ *\n+ * @param aesNo: AES ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ /* Enable aes link mode */\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES disable link mode\n+ *\n+ * @param aesNo: AES ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ /* Disable aes link mode */\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES work in link mode\n+ *\n+ * @param aesNo: AES ID type\n+ * @param linkAddr: Address of config structure in link mode\n+ * @param in: AES input data buffer to deal with\n+ * @param len: AES input data length\n+ * @param out: AES output data buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ /* Link address should word align */\n+ if ((linkAddr & 0x03) != 0 || len % 16 != 0) {\n+ return ERROR;\n+ }\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr);\n+\n+ /* Change source buffer address and destination buffer address */\n+ *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in;\n+ *(uint32_t *)(uintptr_t)(linkAddr + 8) = (uint32_t)(uintptr_t)out;\n+\n+ /* Set data length */\n+ *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16;\n+\n+ /* Enable aes */\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));\n+\n+ /* Start aes engine and wait finishing */\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T));\n+\n+ __NOP();\n+ __NOP();\n+ timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ /* Disable aes */\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1\n+ *\n+ * @param aesNo: AES ID type\n+ * @param src: AES key source type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_SBOOT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_SBOOT_KEY_SEL, src);\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_SBOOT, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES set KEY and IV\n+ *\n+ * @param aesNo: AES ID type\n+ * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW\n+ * @param key: AES KEY pointer\n+ * @param iv: AES IV pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t keyType;\n+ uint32_t aesType;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+ CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE);\n+\n+ /* Set IV, XTS mode and other mode are different */\n+ if (aesType == (uint32_t)SEC_ENG_AES_XTS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ } else {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ }\n+\n+ /* Select hardware key */\n+ if (keySrc == SEC_ENG_AES_KEY_HW) {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal);\n+\n+ return;\n+ }\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE);\n+\n+ if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ }\n+\n+ /* Select software key */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW);\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES set KEY and IV with bigendian\n+ *\n+ * @param aesNo: AES ID type\n+ * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW\n+ * @param key: AES KEY pointer\n+ * @param iv: AES IV pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t keyType;\n+ uint32_t aesType;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+ CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE);\n+\n+ /* Set IV, XTS mode and other mode are different */\n+ if (aesType == (uint32_t)SEC_ENG_AES_XTS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ } else {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ }\n+\n+ /* Select hardware key */\n+ if (keySrc == SEC_ENG_AES_KEY_HW) {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal);\n+\n+ return;\n+ }\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE);\n+\n+ if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) {\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ }\n+\n+ /* Select software key */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW);\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES set counter byte type in CTR mode\n+ *\n+ * @param aesNo: AES ID type\n+ * @param counterType: AES counter type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));\n+ CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType));\n+\n+ /* Set counter type */\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES encrypt or decrypt input data\n+ *\n+ * @param aesCtx: AES context pointer\n+ * @param aesNo: AES ID type\n+ * @param in: AES input data buffer to deal with\n+ * @param len: AES input data length\n+ * @param out: AES output data buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ if (len % 16 != 0) {\n+ return ERROR;\n+ }\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ /* Clear trigger */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ /* Set input and output address */\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MSA, (uintptr_t)in);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MDA, (uintptr_t)out);\n+\n+ /* Set message length */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MSG_LEN, len / 16);\n+\n+ if (aesCtx->mode == SEC_ENG_AES_CTR) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL);\n+ }\n+\n+ /* Set IV sel:0 for new, 1 for last */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_IV_SEL, aesCtx->aesFeed);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ /* Trigger AES Engine */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T);\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ /* Wait finished */\n+ timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ aesCtx->aesFeed = 1;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief AES finish function, clean register\n+ *\n+ * @param aesNo: AES ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo)\n+{\n+ uint32_t AESx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL);\n+\n+ BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 request access for AES\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 2) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x02);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 2) & 0x03) == 0x01) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 release AES Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void)\n+{\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 request AES Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 2) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x04);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 2) & 0x03) == 0x02) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 release AES Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG enable TRNG interrupt\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Trng_Enable(void)\n+{\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */\n+ //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N,0x1ff);\n+\n+ /* No interrupt as default */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ /* busy will be set to 1 after trigger, the gap is 1T */\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+\n+ do {\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY));\n+\n+ /* Clear trng interrupt */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler);\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG enable TRNG interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_Trng_Int_Enable(void)\n+{\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK);\n+\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG disable TRNG interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_Trng_Int_Disable(void)\n+{\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK);\n+\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG get random data out\n+ *\n+ * @param data[32]: TRNG output data\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32])\n+{\n+ uint8_t *p = (uint8_t *)data;\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ /* busy will be set to 1 after trigger, the gap is 1T */\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+ __NOP();\n+\n+ do {\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY));\n+\n+ /* copy trng value */\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7));\n+ p += 4;\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ /* Clear data */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG get random data out\n+ *\n+ * @param data: TRNG output data buffer\n+ *\n+ * @param len: total length to get in bytes\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len)\n+{\n+ uint8_t tmpBuf[32];\n+ uint32_t readLen = 0;\n+ uint32_t i = 0, cnt = 0;\n+\n+ while (readLen < len) {\n+ if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) {\n+ return -1;\n+ }\n+\n+ cnt = len - readLen;\n+\n+ if (cnt > sizeof(tmpBuf)) {\n+ cnt = sizeof(tmpBuf);\n+ }\n+\n+ for (i = 0; i < cnt; i++) {\n+ data[readLen + i] = tmpBuf[i];\n+ }\n+\n+ readLen += cnt;\n+ }\n+\n+ return 0;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG Interrupt Read Trigger\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_Trng_Int_Read_Trigger(void)\n+{\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ Sec_Eng_Trng_Int_Enable();\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TRNG get random data out with Interrupt\n+ *\n+ * @param data[32]: TRNG output data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_Trng_Int_Read(uint8_t data[32])\n+{\n+ uint8_t *p = (uint8_t *)data;\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ /* copy trng value */\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6));\n+ p += 4;\n+ BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7));\n+ p += 4;\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ /* Clear data */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T);\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable TRNG\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_Trng_Disable(void)\n+{\n+ uint32_t TRNGx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN);\n+ //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T);\n+\n+ BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 request TRNG Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 4) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x02);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 4) & 0x03) == 0x01) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 release TRNG Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 request TRNG Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 4) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x04);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 4) & 0x03) == 0x02) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 release TRNG Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA Reset\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Reset(void)\n+{\n+ uint8_t val;\n+\n+ //Disable sec engine\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0);\n+\n+ //Enable sec engine\n+ val = 1 << 3;\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA Enable big endian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_BigEndian_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA Enable little endian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LittleEndian_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA get status function\n+ *\n+ * @param status: Structure pointer of PKA status type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA clear interrupt\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Clear_Int(void)\n+{\n+ uint32_t ctrl;\n+\n+ ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);\n+\n+ ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA get Register size according to Register type\n+ *\n+ * @param reg_type: PKA Register type\n+ *\n+ * @return Register size\n+ *\n+*******************************************************************************/\n+static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type)\n+{\n+ switch (reg_type) {\n+ case SEC_ENG_PKA_REG_SIZE_8:\n+ return 8;\n+\n+ case SEC_ENG_PKA_REG_SIZE_16:\n+ return 16;\n+\n+ case SEC_ENG_PKA_REG_SIZE_32:\n+ return 32;\n+\n+ case SEC_ENG_PKA_REG_SIZE_64:\n+ return 64;\n+\n+ case SEC_ENG_PKA_REG_SIZE_96:\n+ return 96;\n+\n+ case SEC_ENG_PKA_REG_SIZE_128:\n+ return 128;\n+\n+ case SEC_ENG_PKA_REG_SIZE_192:\n+ return 192;\n+\n+ case SEC_ENG_PKA_REG_SIZE_256:\n+ return 256;\n+\n+ case SEC_ENG_PKA_REG_SIZE_384:\n+ return 384;\n+\n+ case SEC_ENG_PKA_REG_SIZE_512:\n+ return 512;\n+\n+ default:\n+ return 0;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA set pre-load register configuration\n+ *\n+ * @param size: Data size in word to write\n+ * @param regIndex: Register index\n+ * @param regType: Register type\n+ * @param op: PKA operation\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp)\n+{\n+ struct pka0_pld_cfg cfg;\n+\n+ cfg.value.BF.size = size;\n+ cfg.value.BF.d_reg_index = regIndex;\n+ cfg.value.BF.d_reg_type = regType;\n+ cfg.value.BF.op = op;\n+ cfg.value.BF.last_op = lastOp;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA write common operation first configuration\n+ *\n+ * @param s0RegIndex: Register index\n+ * @param s0RegType: Register type\n+ * @param dRegIndex: Result Register index\n+ * @param dRegType: Result Register type\n+ * @param op: PKA operation\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType,\n+ uint8_t op, uint8_t lastOp)\n+{\n+ struct pka0_common_op_first_cfg cfg;\n+\n+ cfg.value.BF.s0_reg_idx = s0RegIndex;\n+ cfg.value.BF.s0_reg_type = s0RegType;\n+\n+ if (op != SEC_ENG_PKA_OP_LCMP) {\n+ cfg.value.BF.d_reg_idx = dRegIndex;\n+ cfg.value.BF.d_reg_type = dRegType;\n+ }\n+\n+ cfg.value.BF.op = op;\n+ cfg.value.BF.last_op = lastOp;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA write common operation second configuration1\n+ *\n+ * @param s1RegIndex: Register index\n+ * @param s1RegType: Register type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType)\n+{\n+ struct pka0_common_op_snd_cfg_S1_only cfg;\n+\n+ cfg.value.BF.s1_reg_idx = s1RegIndex;\n+ cfg.value.BF.s1_reg_type = s1RegType;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA write common operation second configuration2\n+ *\n+ * @param s2RegIndex: Register index\n+ * @param s2RegType: Register type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType)\n+{\n+ struct pka0_common_op_snd_cfg_S2_only cfg;\n+\n+ cfg.value.BF.s2_reg_idx = s2RegIndex;\n+ cfg.value.BF.s2_reg_type = s2RegType;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA write common operation second configuration1 and configuration 2\n+ *\n+ * @param s1RegIndex: Configuration 1 Register index\n+ * @param s1RegType: Configuration 1 Register type\n+ * @param s2RegIndex: Configuration 2 Register index\n+ * @param s2RegType: Configuration 3 Register type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType)\n+{\n+ struct pka0_common_op_snd_cfg_S1_S2 cfg;\n+\n+ cfg.value.BF.s1_reg_idx = s1RegIndex;\n+ cfg.value.BF.s1_reg_type = s1RegType;\n+ cfg.value.BF.s2_reg_idx = s2RegIndex;\n+ cfg.value.BF.s2_reg_type = s2RegType;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA wait for complete interrupt\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void)\n+{\n+ uint32_t pka0_ctrl;\n+ uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT;\n+\n+ do {\n+ pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA read block data from register\n+ *\n+ * @param dest: Pointer to buffer address\n+ * @param src: Pointer to register address\n+ * @param len: Data len in word\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifdef ARCH_ARM\n+#ifndef __GNUC__\n+__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ PUSH{ R3 - R6, LR } Start0\n+ CMP R2,\n+# 4 BLT Finish0\n+ LDR R3,\n+ [R1] LDR R4, [R1] LDR R5, [R1] LDR R6, [R1] STMIA R0 !, { R3 - R6 } SUBS R2, R2, #4 B Start0 Finish0 POP\n+ {\n+ R3 - R6, PC\n+ }\n+}\n+#else\n+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ __asm__ __volatile__(\"push {r3-r6,lr}\\n\\t\"\n+ \"Start0 :\"\n+ \"cmp r2,#4\\n\\t\"\n+ \"blt Finish0\\n\\t\"\n+ \"ldr r3,[r1]\\n\\t\"\n+ \"ldr r4,[r1]\\n\\t\"\n+ \"ldr r5,[r1]\\n\\t\"\n+ \"ldr r6,[r1]\\n\\t\"\n+ \"stmia r0!,{r3-r6}\\n\\t\"\n+ \"sub r2,r2,#4\\n\\t\"\n+ \"b Start0\\n\\t\"\n+ \"Finish0 :\"\n+ \"pop {r3-r6,pc}\\n\\t\");\n+}\n+#endif\n+#endif\n+#ifdef ARCH_RISCV\n+void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ uint32_t wrLen = len - len % 4;\n+ uint32_t i;\n+\n+ for (i = 0; i < wrLen; i++) {\n+ dest[i] = *src;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief PKA Write block data to register\n+ *\n+ * @param dest: Pointer to register address\n+ * @param src: Pointer to buffer address\n+ * @param len: Data len in word\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifdef ARCH_ARM\n+#ifndef __GNUC__\n+__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ PUSH{ R3 - R6, LR } Start1\n+ CMP R2,\n+# 4 BLT Finish1\n+ LDMIA R1 !,\n+ { R3 - R6 } STR R3, [R0] STR R4, [R0] STR R5, [R0] STR R6, [R0] SUBS R2, R2, #4 B Start1 Finish1 POP\n+ {\n+ R3 - R6, PC\n+ }\n+}\n+#else\n+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ __asm__ __volatile__(\"push {r3-r6,lr}\\n\\t\"\n+ \"Start1 :\"\n+ \"cmp r2,#4\\n\\t\"\n+ \"blt Finish1\\n\\t\"\n+ \"ldmia r1!,{r3-r6}\\n\\t\"\n+ \"str r3,[r0]\\n\\t\"\n+ \"str r4,[r0]\\n\\t\"\n+ \"str r5,[r0]\\n\\t\"\n+ \"str r6,[r0]\\n\\t\"\n+ \"sub r2,r2,#4\\n\\t\"\n+ \"b Start1\\n\\t\"\n+ \"Finish1 :\"\n+ \"pop {r3-r6,pc}\\n\\t\");\n+}\n+#endif\n+#endif\n+#ifdef ARCH_RISCV\n+void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len)\n+{\n+ uint32_t wrLen = len - len % 4;\n+ uint32_t i;\n+\n+ for (i = 0; i < wrLen; i++) {\n+ *dest = src[i];\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief PKA get result\n+ *\n+ * @param result: Pointer to store result\n+ * @param retSize: Result length in word\n+ * @param regLen: register length in byte\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen)\n+{\n+ uint32_t ret_data = 0x00;\n+ int index = 0x00;\n+\n+ /* Wait for the result */\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize);\n+ index = retSize - (retSize % 4);\n+\n+ while (index < retSize) {\n+ ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW);\n+ result[index] = ret_data;\n+ index++;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA load data to register\n+ *\n+ * @param regType: Register type\n+ * @param regIndex: Register index\n+ * @param data: Data buffer\n+ * @param size: Data length in word\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp)\n+{\n+ int index = 0x00;\n+ uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType);\n+\n+ Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp);\n+\n+ if (size > regLen / 4) {\n+ size = regLen / 4;\n+ }\n+\n+ Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size);\n+ index = size - (size % 4);\n+\n+ while (index < size) {\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]);\n+ index++;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA read data from register\n+ *\n+ * @param regType: Register type\n+ * @param regIdx: Register index\n+ * @param result: Data buffer\n+ * @param retSize: Data length in word\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize)\n+{\n+ uint16_t regSize;\n+ uint32_t dummyData = 0;\n+\n+ regSize = Sec_Eng_PKA_Get_Reg_Size(regType);\n+\n+ if (retSize > regSize / 4) {\n+ result = NULL;\n+ return;\n+ }\n+\n+ Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1);\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ Sec_Eng_PKA_Get_Result(result, retSize, regSize);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA clear register\n+ *\n+ * @param dRegType: Register type\n+ * @param dRegIdx: Register index\n+ * @param size: Data length in word\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp)\n+{\n+ uint32_t dummyData = 0;\n+\n+ Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA load data to register\n+ *\n+ * @param regType: regType: Register type\n+ * @param regIndex: regIndex: Register index\n+ * @param data: data: Data buffer\n+ * @param lastOp: size: Data length in word\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp)\n+{\n+ struct pka0_pldi_cfg cfg;\n+\n+ cfg.value.BF.rsvd = 0;\n+ cfg.value.BF.d_reg_index = regIndex;\n+ cfg.value.BF.d_reg_type = regType;\n+ cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR;\n+ cfg.value.BF.last_op = lastOp;\n+\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA negative source data:D = (1 << SIZE{S0})-S0\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source Register type\n+ * @param s0RegIdx: Source Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)\n+{\n+ uint32_t dummyData = 0;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA move data:D = S0\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source Register type\n+ * @param s0RegIdx: Source Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)\n+{\n+ uint32_t dummyData = 0;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA resize data:D = S0, D.Size = S0.Size\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source Register type\n+ * @param s0RegIdx: Source Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)\n+{\n+ uint32_t dummyData = 0;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod add:D = (S0 + S1) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod sub:D = (S0 - S1) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod :D = S0 mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod mul:D = (S0 * S1) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod sqr:D = (S0 ^ 2) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod exp:D = (S0 ^ S1) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA Report COUT to 1 when S0 < S1\n+ *\n+ * @param cout: Compare result\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx)\n+{\n+ uint32_t pka0_ctrl = 0x00;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);\n+\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+\n+ *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA add:D = S0 + S1\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA sub:D = S0 - S1\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mul:D = S0 * S1\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s1RegType: Source 1 Register type\n+ * @param s1RegIdx: Source 1 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA sqr:D = S0^2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp)\n+{\n+ uint32_t dummyData = 0;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA div:D = S0 / S2\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param s2RegType: Source 2 Register type\n+ * @param s2RegIdx: Source 2 Register index\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp)\n+{\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp);\n+ Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA shift:D = S0 << BIT SHIFT\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param bit_shift: Bits to shift\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift, uint8_t lastOp)\n+{\n+ struct pka0_bit_shift_op_cfg cfg;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0);\n+\n+ cfg.value.BF.bit_shift = bit_shift;\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA shift:D = S0 >> BIT SHIFT\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param bit_shift: Bits to shift\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift, uint8_t lastOp)\n+{\n+ struct pka0_bit_shift_op_cfg cfg;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0);\n+\n+ cfg.value.BF.bit_shift = bit_shift;\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1)\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param s0RegType: Source 0 Register type\n+ * @param s0RegIdx: Source 0 Register index\n+ * @param bit_shift: Bits to shift\n+ * @param lastOp: Last operation\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,\n+ uint16_t bit_shift, uint8_t lastOp)\n+{\n+ struct pka0_bit_shift_op_cfg cfg;\n+\n+ Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp);\n+\n+ cfg.value.BF.bit_shift = bit_shift;\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);\n+\n+ if (lastOp) {\n+ Sec_Eng_PKA_Wait_ISR();\n+ Sec_Eng_PKA_Clear_Int();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA GF to Mont filed 2N:d = (a<<size) % p\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param sRegType: Source Register type\n+ * @param sRegIdx: Source Register index\n+ * @param size: Bits to shift\n+ * @param tRegType: Temp Register type\n+ * @param tRegIdx: Temp Register index\n+ * @param pRegType: Mod P Register type\n+ * @param pRegIdx: Mod P Register index\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size,\n+ uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx)\n+{\n+ Sec_Eng_PKA_LMUL2N(tRegType, tRegIdx, sRegType, sRegIdx, size, 0);\n+ Sec_Eng_PKA_MREM(dRegType, dRegIdx, tRegType, tRegIdx, pRegType, pRegIdx, 1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief PKA GF to Mont filed 2N:d = (a * inv_r) % p\n+ *\n+ * @param dRegType: Destination Register type\n+ * @param dRegIdx: Destination Register index\n+ * @param aRegType: Source Register type\n+ * @param aRegIdx: Source Register index\n+ * @param invrRegType: Invert R Register type\n+ * @param invrRegIdx: Invert R Register index\n+ * @param tRegType: Temp Register type\n+ * @param tRegIdx: Temp Register index\n+ * @param pRegType: Mod P Register type\n+ * @param pRegIdx: Mod P Register index\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, uint8_t invrRegIdx,\n+ uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx)\n+{\n+ Sec_Eng_PKA_LMUL(tRegType, tRegIdx, aRegType, aRegIdx, invrRegType, invrRegIdx, 0);\n+ Sec_Eng_PKA_MREM(dRegType, dRegIdx, tRegType, tRegIdx, pRegType, pRegIdx, 1);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 request PKA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Request_PKA_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 6) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x02);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 6) & 0x03) == 0x01) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 release PKA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 request PKA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 6) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x04);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 6) & 0x03) == 0x02) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 release PKA Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set gmac little endian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_GMAC_Enable_LE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set gmac big endian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_GMAC_Enable_BE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler);\n+ Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler);\n+#endif\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GMAC enable link mode\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_GMAC_Enable_Link(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Enable gmac link mode */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GMAC disable link mode\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Sec_Eng_GMAC_Disable_Link(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Disable gmac link mode */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief GMAC work in link mode\n+ *\n+ * @param linkAddr: Address of config structure in link mode\n+ * @param in: GMAC input data buffer to deal with\n+ * @param len: GMAC input data length\n+ * @param out: GMAC output data buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out)\n+{\n+ uint32_t GMACx = SEC_ENG_BASE;\n+ uint32_t tmpVal;\n+ uint32_t timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT;\n+\n+ /* Link address should word align */\n+ if ((linkAddr & 0x03) != 0 || len % 16 != 0) {\n+ return ERROR;\n+ }\n+\n+ /* Wait finished */\n+ do {\n+ tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY));\n+\n+ /* Set link address */\n+ BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_LCA, linkAddr);\n+\n+ /* Change source buffer address */\n+ *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in;\n+\n+ /* Set data length */\n+ *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16;\n+\n+ /* Start gmac engine and wait finishing */\n+ tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_TRIG_1T));\n+ timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT;\n+\n+ do {\n+ tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY));\n+\n+ /* Get result */\n+ ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x18), 16);\n+\n+ return SUCCESS;\n+}\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Interrupt Handler\n+ *\n+ * @param intType: IRQ Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void SEC_Eng_IntHandler(SEC_ENG_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case SEC_ENG_INT_TRNG:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) {\n+ /* Clear interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T));\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_TRNG] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_TRNG]();\n+ }\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_AES:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) {\n+ /* Clear interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T));\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_AES] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_AES]();\n+ }\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_SHA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) {\n+ /* Clear interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T));\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_SHA] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_SHA]();\n+ }\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_PKA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) {\n+ /* Clear interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T));\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_PKA] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_PKA]();\n+ }\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_CDET:\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_CDET] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_CDET]();\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_GMAC:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) {\n+ /* Clear interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T));\n+\n+ /* Call the callback function */\n+ if (secEngIntCbfArra[SEC_ENG_INT_GMAC] != NULL) {\n+ secEngIntCbfArra[SEC_ENG_INT_GMAC]();\n+ }\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 request GMAC Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 10) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x02);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 10) & 0x03) == 0x01) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group0 release GMAC Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 request GMAC Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 10) & 0x03) == 0x03) {\n+ /* SHA control idle, write to request*/\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x04);\n+\n+ /* Check request result */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD);\n+\n+ if (((tmpVal >> 10) & 0x03) == 0x02) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Group1 release GMAC Access\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void)\n+{\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Interrupt Mask or Unmask\n+ *\n+ * @param intType: Sec Eng Interrupt Type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case SEC_ENG_INT_TRNG:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_AES:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_SHA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_PKA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_CDET:\n+ break;\n+\n+ case SEC_ENG_INT_GMAC:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* UNMASK(Enable) this interrupt */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK));\n+ } else {\n+ /* MASK(Disable) this interrupt */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK));\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK));\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Interrupt clear\n+ *\n+ * @param intType: Sec Eng Interrupt Type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case SEC_ENG_INT_AES:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T));\n+ break;\n+\n+ case SEC_ENG_INT_SHA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T));\n+ break;\n+\n+ case SEC_ENG_INT_TRNG:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T));\n+ break;\n+\n+ case SEC_ENG_INT_PKA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T));\n+ break;\n+\n+ case SEC_ENG_INT_CDET:\n+ break;\n+\n+ case SEC_ENG_INT_GMAC:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T));\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Interrupt callback function install\n+ *\n+ * @param intType: Sec Eng Interrupt Type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType));\n+\n+ secEngIntCbfArra[intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng get interrupt status\n+ *\n+ * @param intType: Sec Eng Interrupt Type\n+ *\n+ * @return status of interrupt\n+ *\n+*******************************************************************************/\n+BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ BL_Sts_Type status = RESET;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType));\n+\n+ switch (intType) {\n+ case SEC_ENG_INT_AES:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) {\n+ status = SET;\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_SHA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) {\n+ status = SET;\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_TRNG:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) {\n+ status = SET;\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_PKA:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) {\n+ status = SET;\n+ }\n+\n+ break;\n+\n+ case SEC_ENG_INT_CDET:\n+ break;\n+\n+ case SEC_ENG_INT_GMAC:\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) {\n+ status = SET;\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return status;\n+}\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Trng IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_TRNG_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_TRNG);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Pka IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_PKA_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_PKA);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Aes IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_AES_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_AES);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Sha IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_SHA_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_SHA);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Cdet IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_CDET_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_CDET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Sec Eng Gmac IRQ Handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void SEC_GMAC_IRQHandler(void)\n+{\n+ SEC_Eng_IntHandler(SEC_ENG_INT_GMAC);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief turn on sec ring\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Turn-on Sec Ring Oscillation */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief turn off sec ring\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Turn-off Sec Ring Oscillation */\n+ tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN);\n+ BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal);\n+}\n+\n+/*@} end of group SEC_ENG_Public_Functions */\n+\n+/*@} end of group SEC_ENG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3d0745eb74c0f30be51fbbe3b621480b3e8a315a\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c\n@@ -0,0 +1,1673 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_cfg.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_sf_cfg.h\"\n+#include \"softcrc.h\"\n+#include \"bl808_xip_sflash.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CFG\n+ * @{\n+ */\n+\n+/** @defgroup SF_CFG_Private_Macros\n+ * @{\n+ */\n+#define BFLB_FLASH_CFG_MAGIC \"FCFG\"\n+\n+/*@} end of group SF_CFG_Private_Macros */\n+\n+/** @defgroup SF_CFG_Private_Types\n+ * @{\n+ */\n+#ifndef BFLB_USE_ROM_DRIVER\n+typedef struct\n+{\n+ uint32_t jedecID;\n+ char *name;\n+ const SPI_Flash_Cfg_Type *cfg;\n+} Flash_Info_t;\n+#endif\n+\n+/*@} end of group SF_CFG_Private_Types */\n+\n+/** @defgroup SF_CFG_Private_Variables\n+ * @{\n+ */\n+#ifndef BFLB_USE_ROM_DRIVER\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 0,\n+ .cReadMode = 0xFF,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3d,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 300,\n+ .timeE32k = 1200,\n+ .timeE64k = 1200,\n+ .timePagePgm = 5,\n+ .timeCe = 20 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0x20,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 0,\n+ .cReadMode = 0xf0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xef,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0x20,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = 0x24,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1600,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 500,\n+ .timeE32k = 2000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 32 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 8 / 8,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 300,\n+ .timeE32k = 1200,\n+ .timeE64k = 1200,\n+ .timePagePgm = 5,\n+ .timeCe = 20 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0x12,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x31,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 300,\n+ .timeE32k = 1200,\n+ .timeE64k = 1200,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_128 = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xC2,\n+\n+ .deBurstWrapCmd = 0xC0,\n+ .deBurstWrapCmdDmyClk = 0x00,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .deBurstWrapData = 0x10,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 0,\n+ .qeBit = 0x06,\n+ .qeWriteRegLen = 0x01,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xA5,\n+\n+ .burstWrapCmd = 0xC0,\n+ .burstWrapCmdDmyClk = 0x00,\n+ .burstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .burstWrapData = 0x02,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x38,\n+ .qppAddrMode = SF_CTRL_ADDR_4_LINES,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 300,\n+ .timeE32k = 1200,\n+ .timeE64k = 1200,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 45,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc2,\n+\n+ .deBurstWrapCmd = 0xC0,\n+ .deBurstWrapCmdDmyClk = 0x00,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .deBurstWrapData = 0x10,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 0,\n+ .qeBit = 0x06,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x15,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xA5,\n+\n+ .burstWrapCmd = 0xC0,\n+ .burstWrapCmdDmyClk = 0x00,\n+ .burstWrapDataMode = SF_CTRL_DATA_1_LINE,\n+ .burstWrapData = 0x02,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x38,\n+ .qppAddrMode = SF_CTRL_ADDR_4_LINES,\n+\n+ .ioMode = (SF_CTRL_QIO_MODE | 0x20),\n+ .clkDelay = 1,\n+ .clkInvert = 0x3f,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 400,\n+ .timeE32k = 1000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 20,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {\n+ {\n+ .jedecID = 0x1440ef,\n+ //.name=\"Winb_80DV_08_33\",\n+ .cfg = &flashCfg_Winb_80DV,\n+ },\n+ {\n+ .jedecID = 0x1540ef,\n+ //.name=\"Winb_16JV_16_33\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1640ef,\n+ //.name=\"Winb_32FV_32_33\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1840ef,\n+ //.name=\"Winb_128JV_128_33\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID = 0x1940ef,\n+ //.name=\"Winb_256FV_128_33\",\n+ .cfg = &flashCfg_Winb_256FV,\n+ },\n+ {\n+ .jedecID = 0x1460ef,\n+ //.name=\"Winb_80EW_08_18\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1560ef,\n+ //.name=\"Winb_16FW_16_18\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1660ef,\n+ //.name=\"Winb_32FW_32_18\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1760ef,\n+ //.name=\"WB_64JW_64_18\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID = 0x1860ef,\n+ //.name=\"Winb_128JW_128_18\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID = 0x1570ef,\n+ //.name=\"Winb_16JV_16_33\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1870ef,\n+ //.name=\"Winb_128JV_128_33\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID = 0x1680ef,\n+ //.name=\"Winb_32JW_32_18\",\n+ .cfg = &flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x1880ef,\n+ //.name=\"Winb_128JW_128_18\",\n+ .cfg = &flashCfg_Winb_64JW,\n+ },\n+ {\n+ .jedecID = 0x1440C8,\n+ //.name=\"GD_Q08E_08_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1540C8,\n+ //.name=\"GD_Q16E_16_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1640C8,\n+ //.name=\"GD_Q32C_32_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x1740C8,\n+ //.name=\"GD_Q64E_64_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x1840C8,\n+ //.name=\"GD_Q128E_128_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x1460C8,\n+ //.name=\"GD_LQ08C_08_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1560C8,\n+ //.name=\"GD_LE16C_16_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1660C8,\n+ //.name=\"GD_LQ32D_32_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1760c8,\n+ //.name=\"GD_LQ64E_64_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1860c8,\n+ //.name=\"GD_LQ128E_64_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x1465C8,\n+ //.name=\"GD_WQ80E_80_33\",\n+ .cfg = &flashCfg_Gd_WQ80E_WQ16E,\n+ },\n+ {\n+ .jedecID = 0x1565C8,\n+ //.name=\"GD_WQ16E_16_33\",\n+ .cfg = &flashCfg_Gd_WQ80E_WQ16E,\n+ },\n+ {\n+ .jedecID = 0x1665C8,\n+ //.name=\"GD_WQ32E_32_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x15345e,\n+ //.name=\"ZB_WQ16A_16_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x15405e,\n+ //.name=\"ZB_Q16B_16_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x16405e,\n+ //.name=\"ZB_Q32B_32_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x17405e,\n+ //.name=\"ZB_Q64B_64_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x14605E,\n+ //.name=\"ZB_VQ80\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x15605E,\n+ //.name=\"ZB_VQ16\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x1820C2,\n+ //.name=\"MX_25L128_128_33\",\n+ .cfg = &flashCfg_Mxic_128,\n+ },\n+ {\n+ .jedecID = 0x1920C2,\n+ //.name=\"MX_25L256_256_33\",\n+ .cfg = &flashCfg_Mxic_25L256,\n+ },\n+ {\n+ .jedecID = 0x3925C2,\n+ //.name=\"MX_25U256_256_33\",\n+ .cfg = &flashCfg_Mxic_25L256,\n+ },\n+ {\n+ .jedecID=0x144020,\n+ //.name=\"XM_25QH80_80_33\",\n+ .cfg=&flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID=0x154020,\n+ //.name=\"XM_25QH16_16_33\",\n+ .cfg=&flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID=0x164020,\n+ //.name=\"XM_25QH32_32_33\",\n+ .cfg=&flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID=0x174020,\n+ //.name=\"XM_25QH64_64_33\",\n+ .cfg=&flashCfg_Winb_16JV,\n+ },\n+ {\n+ .jedecID = 0x15400B,\n+ //.name=\"XT_25F16B_16_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x16400B,\n+ //.name=\"XT_25F32B_32_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x17400B,\n+ //.name=\"XT_25F64B_32_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x18400B,\n+ //.name=\"XT_25F128B_128_33\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x14600B,\n+ //.name=\"XT_25Q80B_08_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x16600B,\n+ //.name=\"XT_25Q32B_32_18\",\n+ .cfg = &flashCfg_Gd_Q80E_Q16E,\n+ },\n+ {\n+ .jedecID = 0x144068,\n+ //.name=\"Boya_Q08B_08_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x154068,\n+ //.name=\"Boya_Q16B_16_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x164068,\n+ //.name=\"Boya_Q32B_32_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x174068,\n+ //.name=\"Boya_Q64A_64_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ },\n+ {\n+ .jedecID = 0x184068,\n+ //.name=\"Boya_Q128A_128_33\",\n+ .cfg = &flashCfg_Gd_Q32E_Q128E,\n+ }\n+};\n+#endif\n+\n+/*@} end of group SF_CFG_Private_Variables */\n+\n+/** @defgroup SF_CFG_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_Global_Variables */\n+\n+/** @defgroup SF_CFG_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_Private_Fun_Declaration */\n+\n+/** @defgroup SF_CFG_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Init external flash GPIO according to flash GPIO config\n+ *\n+ * @param extFlashPin: Flash GPIO config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin)\n+{\n+ GLB_GPIO_Cfg_Type cfg;\n+ uint8_t gpiopins[6];\n+ uint8_t i = 0;\n+\n+ cfg.gpioMode = GPIO_MODE_AF;\n+ cfg.pullType = GPIO_PULL_UP;\n+ cfg.drive = 2;\n+ cfg.smtCtrl = 1;\n+ cfg.gpioFun = GPIO_FUN_FLASH;\n+\n+ if (extFlashPin == 0) {\n+ gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;\n+ gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;\n+ gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;\n+ gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;\n+ gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;\n+ gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ for (i = 0; i < sizeof(gpiopins); i++) {\n+ cfg.gpioPin = gpiopins[i];\n+\n+ if (i == 0 || i == 1) {\n+ /* flash clk and cs is output */\n+ cfg.gpioMode = GPIO_MODE_OUTPUT;\n+ } else {\n+ /* data are bidir */\n+ cfg.gpioMode = GPIO_MODE_AF;\n+ }\n+\n+ GLB_GPIO_Init(&cfg);\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Deinit external flash GPIO according to flash GPIO config\n+ *\n+ * @param extFlashPin: Flash GPIO config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin)\n+{\n+ GLB_GPIO_Cfg_Type cfg;\n+ uint8_t gpiopins[6];\n+ uint8_t i = 0;\n+\n+ cfg.gpioMode = GPIO_MODE_INPUT;\n+ cfg.pullType = GPIO_PULL_UP;\n+ cfg.drive = 1;\n+ cfg.smtCtrl = 1;\n+ cfg.gpioFun = GPIO_FUN_GPIO;\n+\n+ if (extFlashPin == 0) {\n+ gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;\n+ gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;\n+ gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;\n+ gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;\n+ gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;\n+ gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ for (i = 0; i < sizeof(gpiopins); i++) {\n+ cfg.gpioPin = gpiopins[i];\n+ GLB_GPIO_Init(&cfg);\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/*@} end of group SF_CFG_Private_Functions */\n+\n+/** @defgroup SF_CFG_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash config according to flash ID\n+ *\n+ * @param flashID: Flash ID\n+ * @param pFlashCfg: Flash config pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t i;\n+ uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];\n+ uint32_t crc, *pCrc;\n+ uint32_t xipOffset;\n+\n+ if (flashID == 0) {\n+ xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(0, group, bank);\n+ XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank);\n+\n+ if (ARCH_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) {\n+ crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));\n+\n+ if (*pCrc == crc) {\n+ ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ } else {\n+ for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {\n+ if (flashInfos[i].jedecID == flashID) {\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash config according to flash ID patch\n+ *\n+ * @param flashID: Flash ID\n+ * @param pFlashCfg: Flash config pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ return SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Init flash GPIO according to flash Pin config\n+ *\n+ * @param flashPinCfg: Specify flash Pin config\n+ * @param restoreDefault: Wether to restore default setting\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault)\n+{\n+ uint8_t selEmbedded = 0;\n+ uint8_t swap = 0;\n+\n+ if ((flashPinCfg&(1<<3)) > 0) {\n+ return ERROR;\n+ }\n+\n+ if (restoreDefault) {\n+ /* Set Default first */\n+ GLB_Set_Flash_IO_PARM(1, 1);\n+ SF_Ctrl_Select_Pad(SF_IO_EMB_SWAP_IO0_IO3);\n+\n+ /* Default is set, so return */\n+ if (flashPinCfg == SF_IO_EMB_SWAP_IO0_IO3) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ if (flashPinCfg & (1 << 2)) {\n+ /* Init sf2 gpio */\n+ SF_Cfg_Init_Ext_Flash_Gpio(0);\n+ selEmbedded = 0;\n+ } else {\n+ selEmbedded = 1;\n+ }\n+ /* if pin select dual flash, embedded is default */\n+ if ((flashPinCfg & (1 << 4))) {\n+ selEmbedded = 1;\n+ }\n+\n+ swap = ((flashPinCfg >> 1) & 1);\n+ swap = (!swap);\n+ GLB_Set_Flash_IO_PARM(selEmbedded, swap);\n+ SF_Ctrl_Select_Pad(flashPinCfg);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Identify one flash\n+ *\n+ * @param callFromFlash: code run at flash or ram\n+ * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config\n+ * @param restoreDefault: Wether restore default flash GPIO config\n+ * @param pFlashCfg: Flash config pointer\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return Flash ID\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg,\n+ uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint8_t autoScan = 0;\n+ uint8_t flashPin = 0;\n+ uint32_t jdecId = 0;\n+ uint32_t i = 0;\n+ uint32_t offset;\n+ BL_Err_Type stat;\n+\n+ autoScan = ((flashPinCfg >> 7) & 1);\n+ flashPin = (flashPinCfg & 0x7F);\n+\n+ ARCH_MemCpy_Fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type));\n+\n+ if (callFromFlash == 1) {\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);\n+ return 0;\n+ }\n+ }\n+\n+ if (autoScan) {\n+ flashPin = 0;\n+\n+ do {\n+ if (flashPin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {\n+ jdecId = 0;\n+ break;\n+ }\n+\n+ if (!IS_SF_CTRL_PIN_SELECT(flashPin) || (flashPin&(1<<3)) > 0) {\n+ flashPin++;\n+ continue;\n+ }\n+\n+ SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault);\n+ SFlash_Release_Powerdown(pFlashCfg);\n+ SFlash_Reset_Continue_Read(pFlashCfg);\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+ jdecId = 0;\n+ SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+ jdecId = jdecId & 0xffffff;\n+ flashPin++;\n+ } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);\n+ } else {\n+ /* select media gpio */\n+ SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault);\n+ SFlash_Release_Powerdown(pFlashCfg);\n+ SFlash_Reset_Continue_Read(pFlashCfg);\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+ SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+ jdecId = jdecId & 0xffffff;\n+ }\n+\n+ for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {\n+ if (flashInfos[i].jedecID == jdecId) {\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));\n+ break;\n+ }\n+ }\n+\n+ if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) {\n+ if (callFromFlash == 1) {\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ return jdecId;\n+ } else {\n+ if (callFromFlash == 1) {\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ return (jdecId | BFLB_FLASH_ID_VALID_FLAG);\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Identify one flash patch\n+ *\n+ * @param callFromFlash: code run at flash or ram\n+ * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config\n+ * @param restoreDefault: Wether restore default flash GPIO config\n+ * @param pFlashCfg: Flash config pointer\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return Flash ID\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg,\n+ uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ return SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Cfg flash init\n+ *\n+ * @param sel: SF pin select\n+ * @param pSfCtrlCfg: Serial flash controller configuration pointer\n+ * @param pBank2Cfg: Serial flash2 controller configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg)\n+{\n+ uint8_t selEmbedded = 0;\n+ uint8_t swap = 0;\n+\n+ if ((sel&(1<<3)) > 0) {\n+ return ERROR;\n+ }\n+\n+ if (sel & (1 << 2)) {\n+ SF_Cfg_Init_Ext_Flash_Gpio(0);\n+ selEmbedded = 0;\n+ } else {\n+ selEmbedded = 1;\n+ }\n+ /* If pin select dual flash, embedded is default */\n+ if ((sel & (1 << 4))) {\n+ selEmbedded = 1;\n+ }\n+\n+ swap = ((sel >> 1) & 1);\n+ swap = (!swap);\n+ GLB_Set_Flash_IO_PARM(selEmbedded, swap);\n+ SF_Ctrl_Select_Pad(sel);\n+\n+ if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {\n+ /* Embedded pad1 io delay set */\n+ SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay);\n+ } else if (sel <= SF_IO_EXT_SF2) {\n+ /* Pad2 or pad3 io delay set */\n+ SF_Ctrl_Set_IO_Delay((sel >> 2), pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay);\n+ } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {\n+ /* Dual flash mode, embedded pad1 and pad2 io delay set */\n+ SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay);\n+ SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay);\n+ }\n+\n+ if (pBank2Cfg != NULL) {\n+ if (pBank2Cfg->sbus2Select) {\n+ if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {\n+ /* Default sbus2 replace opt flash2 */\n+ SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);\n+ }\n+ }\n+ }\n+\n+ SFlash_Init(pSfCtrlCfg, pBank2Cfg);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Cfg system bus 2 flash init\n+ *\n+ * @param sel: SF pin select\n+ * @param pBank2Cfg: Serial flash2 controller configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg)\n+{\n+ if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {\n+ return ERROR;\n+ }\n+\n+ /* Init flash2 gpio */\n+ if (sel & (1 << 2)) {\n+ SF_Cfg_Init_Ext_Flash_Gpio(0);\n+ }\n+\n+ /* Set remap for flash2 xip mode */\n+ SF_Ctrl_Remap_Set(pBank2Cfg->remap, pBank2Cfg->remapLock);\n+\n+ /* Dual flash mode, pad2 io delay set */\n+ SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay);\n+\n+ if (pBank2Cfg->sbus2Select) {\n+ /* Default sbus2 replace opt flash2 */\n+ SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);\n+ }\n+\n+ SFlash_Init(NULL, pBank2Cfg);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/*@} end of group SF_CFG_Public_Functions */\n+\n+/*@} end of group SF_CFG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9dd2683e6dc238b3f068daad12ee998bf6c5932d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c\n@@ -0,0 +1,295 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_cfg_ext.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"softcrc.h\"\n+#include \"bl808_sf_cfg.h\"\n+#include \"bl808_sf_cfg_ext.h\"\n+#include \"bl808_xip_sflash.h\"\n+#include \"bl808_romdriver_e907.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CFG_EXT\n+ * @{\n+ */\n+\n+/** @defgroup SF_CFG_EXT_Private_Macros\n+ * @{\n+ */\n+#define BFLB_FLASH_CFG_MAGIC \"FCFG\"\n+\n+/*@} end of group SF_CFG_EXT_Private_Macros */\n+\n+/** @defgroup SF_CFG_EXT_Private_Types\n+ * @{\n+ */\n+typedef struct\n+{\n+ uint32_t jedecID;\n+ char *name;\n+ const SPI_Flash_Cfg_Type *cfg;\n+} Flash_Info_t;\n+\n+/*@} end of group SF_CFG_EXT_Private_Types */\n+\n+/** @defgroup SF_CFG_EXT_Private_Variables\n+ * @{\n+ */\n+static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = {\n+ .resetCreadCmd = 0xff,\n+ .resetCreadCmdSize = 3,\n+ .mid = 0xc8,\n+\n+ .deBurstWrapCmd = 0x77,\n+ .deBurstWrapCmdDmyClk = 0x3,\n+ .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .deBurstWrapData = 0xF0,\n+\n+ /*reg*/\n+ .writeEnableCmd = 0x06,\n+ .wrEnableIndex = 0x00,\n+ .wrEnableBit = 0x01,\n+ .wrEnableReadRegLen = 0x01,\n+\n+ .qeIndex = 1,\n+ .qeBit = 0x01,\n+ .qeWriteRegLen = 0x02,\n+ .qeReadRegLen = 0x1,\n+\n+ .busyIndex = 0,\n+ .busyBit = 0x00,\n+ .busyReadRegLen = 0x1,\n+ .releasePowerDown = 0xab,\n+\n+ .readRegCmd[0] = 0x05,\n+ .readRegCmd[1] = 0x35,\n+ .writeRegCmd[0] = 0x01,\n+ .writeRegCmd[1] = 0x01,\n+\n+ .fastReadQioCmd = 0xeb,\n+ .frQioDmyClk = 16 / 8,\n+ .cReadSupport = 1,\n+ .cReadMode = 0xa0,\n+\n+ .burstWrapCmd = 0x77,\n+ .burstWrapCmdDmyClk = 0x3,\n+ .burstWrapDataMode = SF_CTRL_DATA_4_LINES,\n+ .burstWrapData = 0x40,\n+ /*erase*/\n+ .chipEraseCmd = 0xc7,\n+ .sectorEraseCmd = 0x20,\n+ .blk32EraseCmd = 0x52,\n+ .blk64EraseCmd = 0xd8,\n+ /*write*/\n+ .pageProgramCmd = 0x02,\n+ .qpageProgramCmd = 0x32,\n+ .qppAddrMode = SF_CTRL_ADDR_1_LINE,\n+\n+ .ioMode = SF_CTRL_QIO_MODE,\n+ .clkDelay = 1,\n+ .clkInvert = 0x3d,\n+\n+ .resetEnCmd = 0x66,\n+ .resetCmd = 0x99,\n+ .cRExit = 0xff,\n+ .wrEnableWriteRegLen = 0x00,\n+\n+ /*id*/\n+ .jedecIdCmd = 0x9f,\n+ .jedecIdCmdDmyClk = 0,\n+ .enter32BitsAddrCmd = 0xb7,\n+ .exit32BitsAddrCmd = 0xe9,\n+ .sectorSize = 4,\n+ .pageSize = 256,\n+\n+ /*read*/\n+ .fastReadCmd = 0x0b,\n+ .frDmyClk = 8 / 8,\n+ .qpiFastReadCmd = 0x0b,\n+ .qpiFrDmyClk = 8 / 8,\n+ .fastReadDoCmd = 0x3b,\n+ .frDoDmyClk = 8 / 8,\n+ .fastReadDioCmd = 0xbb,\n+ .frDioDmyClk = 0,\n+ .fastReadQoCmd = 0x6b,\n+ .frQoDmyClk = 8 / 8,\n+\n+ .qpiFastReadQioCmd = 0xeb,\n+ .qpiFrQioDmyClk = 16 / 8,\n+ .qpiPageProgramCmd = 0x02,\n+ .writeVregEnableCmd = 0x50,\n+\n+ /* qpi mode */\n+ .enterQpi = 0x38,\n+ .exitQpi = 0xff,\n+\n+ /*AC*/\n+ .timeEsector = 500,\n+ .timeE32k = 2000,\n+ .timeE64k = 2000,\n+ .timePagePgm = 5,\n+ .timeCe = 33 * 1000,\n+ .pdDelay = 3,\n+ .qeData = 0,\n+};\n+\n+static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {\n+ {\n+ .jedecID = 0x1760c8,\n+ //.name=\"GD_LQ64E_64_18\",\n+ .cfg = &flashCfg_GD_LQ64E,\n+ },\n+};\n+\n+/*@} end of group SF_CFG_EXT_Private_Variables */\n+\n+/** @defgroup SF_CFG_EXT_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_EXT_Global_Variables */\n+\n+/** @defgroup SF_CFG_EXT_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */\n+\n+/** @defgroup SF_CFG_EXT_Private_Functions\n+ * @{\n+ */\n+\n+\n+\n+/*@} end of group SF_CFG_EXT_Private_Functions */\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash config according to flash ID patch\n+ *\n+ * @param flashID: Flash ID\n+ * @param pFlashCfg: Flash config pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)\n+{\n+ uint32_t i;\n+ uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];\n+ uint32_t crc, *pCrc;\n+ uint32_t xipOffset;\n+ char flashCfgMagic[] = \"FCFG\";\n+\n+ if (flashID == 0) {\n+ xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);\n+ SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0);\n+ XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);\n+ SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0);\n+\n+ if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) {\n+ crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));\n+\n+ if (*pCrc == crc) {\n+ ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ } else {\n+ if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){\n+ return SUCCESS;\n+ }\n+ for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {\n+ if (flashInfos[i].jedecID == flashID) {\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));\n+ return SUCCESS;\n+ }\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+\n+\n+/****************************************************************************/ /**\n+ * @brief Identify one flash patch\n+ *\n+ * @param callFromFlash: code run at flash or ram\n+ * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config\n+ * @param restoreDefault: Wether restore default flash GPIO config\n+ * @param pFlashCfg: Flash config pointer\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return Flash ID\n+ *\n+*******************************************************************************/\n+uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg,\n+ uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t jdecId = 0;\n+ uint32_t i = 0;\n+ uint32_t ret = 0;\n+\n+ ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank);\n+ if(callFromFlash){\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank);\n+ }\n+ if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){\n+ return ret;\n+ }\n+\n+ jdecId = (ret&0xffffff);\n+ for(i=0; i<sizeof(flashInfos)/sizeof(flashInfos[0]); i++){\n+ if(flashInfos[i].jedecID == jdecId){\n+ ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg,sizeof(SPI_Flash_Cfg_Type));\n+ break;\n+ }\n+ }\n+ if(i == sizeof(flashInfos)/sizeof(flashInfos[0])){\n+ return jdecId;\n+ }else{\n+ return (jdecId|BFLB_FLASH_ID_VALID_FLAG);\n+ }\n+}\n+\n+/*@} end of group SF_CFG_EXT_Public_Functions */\n+\n+/*@} end of group SF_CFG_EXT_EXT */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4b2c19429e26f11c9b0d473b5296d070012f1e3d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c\n@@ -0,0 +1,1870 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sf_ctrl.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_sf_ctrl.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SF_CTRL\n+ * @{\n+ */\n+\n+/** @defgroup SF_CTRL_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SF_CTRL_Private_Macros */\n+\n+/** @defgroup SF_CTRL_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SF_CTRL_Private_Types */\n+\n+/** @defgroup SF_CTRL_Private_Variables\n+ * @{\n+ */\n+#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000)\n+#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80)\n+\n+/*@} end of group SF_CTRL_Private_Variables */\n+\n+/** @defgroup SF_CTRL_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SF_CTRL_Global_Variables */\n+\n+/** @defgroup SF_CTRL_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SF_CTRL_Private_Fun_Declaration */\n+\n+/** @defgroup SF_CTRL_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group SF_CTRL_Private_Functions */\n+\n+/** @defgroup SF_CTRL_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Enable serail flash controller\n+ *\n+ * @param cfg: serial flash controller config\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+\n+ if (cfg == NULL) {\n+ return;\n+ }\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner));\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ if (cfg->en32bAddr) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN);\n+ }\n+\n+ if (cfg->clkDelay > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);\n+ }\n+\n+ /* Serail out inverted, so sf ctrl send on negative edge */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);\n+\n+ /* Enable AHB access sram buffer and enable sf interface */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);\n+\n+ SF_Ctrl_Set_Owner(cfg->owner);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable serail bank2 controller\n+ *\n+ * @param bank2Cfg: serial bank2 controller config\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (bank2Cfg == NULL) {\n+ return;\n+ }\n+\n+ /* Select if1 bank2 clock delay */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12);\n+\n+ if (bank2Cfg->bank2RxClkInvertSrc) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);\n+\n+ if (bank2Cfg->bank2RxClkInvertSel) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);\n+ }\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);\n+ }\n+\n+ if (bank2Cfg->bank2DelaySrc) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);\n+\n+ if (bank2Cfg->bank2ClkDelay > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);\n+ }\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal);\n+\n+ /* Select sbus2 clock delay */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0);\n+\n+ if (bank2Cfg->bank2RxClkInvertSel) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL);\n+ }\n+\n+ if (bank2Cfg->bank2ClkDelay > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal);\n+\n+ /* Dual flash mode, enable bank2, select pad1 and pad2 */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl set io delay\n+ *\n+ * @param pad: Pad select\n+ * @param doDelay: DO delay select\n+ * @param diDelay: DI delay select\n+ * @param oeDelay: OE delay select\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t offset = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad));\n+\n+ if (pad == SF_CTRL_PAD1) {\n+ offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET;\n+ } else if (pad == SF_CTRL_PAD2) {\n+ offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET;\n+ } else {\n+ offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET;\n+ }\n+\n+ /* Set do di and oe delay */\n+ tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL, doDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL, diDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL, oeDelay);\n+ BL_WR_REG(offset, SF_CTRL_IO_DLY_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DO_DLY_SEL, doDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DI_DLY_SEL, diDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_OE_DLY_SEL, oeDelay);\n+ BL_WR_REG(offset, SF_CTRL_IO_DLY_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DO_DLY_SEL, doDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DI_DLY_SEL, diDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_OE_DLY_SEL, oeDelay);\n+ BL_WR_REG(offset, SF_CTRL_IO_DLY_3, tmpVal);\n+\n+ tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DO_DLY_SEL, doDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DI_DLY_SEL, diDelay);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_OE_DLY_SEL, oeDelay);\n+ BL_WR_REG(offset, SF_CTRL_IO_DLY_4, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Flash controller sbus2 hold sram\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Hold_Sram(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Sbus2 hold sram */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Flash controller sbus2 release sram\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Release_Sram(void)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Sbus2 release sram */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash controller sbus2 status\n+ *\n+ * @param None\n+ *\n+ * @return Wether if2 is enable\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_Sbus2_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_EN)) {\n+ if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_FN_SEL)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+\n+ return RESET;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl set sbus2 repalce\n+ *\n+ * @param pad: SF pad to replace\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad));\n+\n+ /* Sbus2 enable */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal);\n+\n+ SF_Ctrl_Sbus2_Hold_Sram();\n+\n+ /* Sbus2 repalce pad */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3);\n+\n+ if (pad == SF_CTRL_PAD1) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1);\n+ } else if (pad == SF_CTRL_PAD2) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_PAD_SEL, pad);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl sbus2 revoke replace\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Revoke_replace(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ SF_Ctrl_Sbus2_Release_Sram();\n+\n+ /* Sbus2 clear repalce pad */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal);\n+\n+ /* Sbus2 disable */\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl set sbus2 clock delay\n+ *\n+ * @param clkDelay: Sbus2 clock delay\n+ * @param rxClkInvert: Sbus2 rx clock invert\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0);\n+\n+ if (clkDelay > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, clkDelay - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL, rxClkInvert);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash controller clock delay value\n+ *\n+ * @param en32BitsAddr: Serial flash enable or disable 32-bits addr\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ if (en32BitsAddr) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN);\n+\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash controller clock delay value\n+ *\n+ * @param None\n+ *\n+ * @return Clock delay value\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) {\n+ return 0;\n+ } else {\n+ return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash controller clock delay value\n+ *\n+ * @param delay: Clock delay value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ if (delay > 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl get wrap queue value\n+ *\n+ * @param None\n+ *\n+ * @return Wrap queue value\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Wrap_Queue_Value(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3);\n+\n+ return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_Q);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl set cmds config\n+ *\n+ * @param cmdsCfg: SF Ctrl cmds config\n+ * @param bank: bank select type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_WRAP_MODE(cmdsCfg->cmdsWrapMode));\n+ CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->cmdsWrapLen));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3);\n+\n+ if (cmdsCfg->ackLatency) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT);\n+ }\n+\n+ if (cmdsCfg->cmdsCoreEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN);\n+ }\n+\n+ if (bank == SF_CTRL_FLASH_BANK1) {\n+ if (cmdsCfg->cmdsEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_MODE, cmdsCfg->cmdsWrapMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_LEN, cmdsCfg->cmdsWrapLen);\n+ } else {\n+ if (cmdsCfg->cmdsEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_MODE, cmdsCfg->cmdsWrapMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_LEN, cmdsCfg->cmdsWrapLen);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl pad select\n+ *\n+ * @param sel: Pin select type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_PIN_SELECT(sel));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+\n+ if (sel <= SF_IO_EXT_SF2) {\n+ /* Single flash mode, disable bank2 */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);\n+\n+ if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {\n+ /* Select embedded pad1 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0);\n+ } else {\n+ /* Select pad2 or pad3 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, ((sel&0xf) >> 2));\n+ }\n+ } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {\n+ /* Dual flash mode, enable bank2, select pad1 and pad2 */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl dual flash memory remap set\n+ *\n+ * @param remap: Memory remap set type\n+ * @param lock: Memory remap lock\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_REMAP_TYPE(remap));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP, remap);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+\n+ if (lock) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl select bank on system bus\n+ *\n+ * @param bank: bank select type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank)\n+{\n+ /* TODO: sf_if_bk_swap */\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash controller owner:I/D AHB or system AHB\n+ *\n+ * @param owner: owner type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner));\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ /* Set owner */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner);\n+\n+ /* Set iahb to flash interface */\n+ if (owner == SF_CTRL_OWNER_IAHB) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Disable flash controller\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable flash controller AES with big indian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable flash controller AES with little indian\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES region\n+ *\n+ * @param region: region number\n+ * @param enable: enable or not\n+ * @param hwKey: hardware key or software key\n+ * @param startAddr: region start address\n+ * @param endAddr: region end address\n+ * @param locked: lock this region or not\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable,\n+ uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked)\n+{\n+ /* Do flash key eco */\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal;\n+\n+ if (!hwKey) {\n+ regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ }\n+\n+ tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_END);\n+ /* sf_aes_end =1 means 1,11,1111,1111 */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024);\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_END, tmpVal);\n+\n+ tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_START);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked);\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_START, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES key\n+ *\n+ * @param region: region number\n+ * @param key: key data pointer\n+ * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+\n+ if (NULL != key) {\n+ if (keyType == SF_CTRL_AES_128BITS) {\n+ i = 4;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\t*/\n+ } else if (keyType == SF_CTRL_AES_256BITS) {\n+ i = 8;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\t*/\n+ } else if (keyType == SF_CTRL_AES_192BITS) {\n+ i = 6;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));\n+\t\t\tkey+=4;\n+\t\t\t*/\n+ }\n+\n+ tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ tmpVal -= 4;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES XTS mode key\n+ *\n+ * @param region: region number\n+ * @param key: key data pointer\n+ * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)\n+{\n+ /* Do flash key eco */\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+\n+ if (NULL != key) {\n+ i = 8;\n+ tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key)));\n+ key += 4;\n+ tmpVal -= 4;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES key with big endian\n+ *\n+ * @param region: region number\n+ * @param key: key data pointer\n+ * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+\n+ if (NULL != key) {\n+ if (keyType == SF_CTRL_AES_128BITS) {\n+ i = 4;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\t*/\n+ } else if (keyType == SF_CTRL_AES_256BITS) {\n+ i = 8;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\t*/\n+ } else if (keyType == SF_CTRL_AES_192BITS) {\n+ i = 6;\n+ /*\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));\n+\t\t\tkey+=4;\n+\t\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));\n+\t\t\t*/\n+ }\n+\n+ tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ tmpVal += 4;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES XTS mode key with big endian\n+ *\n+ * @param region: region number\n+ * @param key: key data pointer\n+ * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+\n+ if (NULL != key) {\n+ i = 8;\n+ tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key));\n+ key += 4;\n+ tmpVal += 4;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES iv\n+ *\n+ * @param region: region number\n+ * @param iv: iv data pointer\n+ * @param addrOffset: flash address offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 3;\n+\n+ if (iv != NULL) {\n+ tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ iv += 4;\n+ tmpVal -= 4;\n+ }\n+\n+ /*\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv)));\n+\t\tiv+=4;\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv)));\n+\t\tiv+=4;\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv)));\n+\t\tiv+=4;\n+\t\t*/\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset);\n+ iv += 4;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES XTS iv\n+ *\n+ * @param region: region number\n+ * @param iv: iv data pointer\n+ * @param addrOffset: flash address offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 3;\n+\n+ if (iv != NULL) {\n+ tmpVal = SF_CTRL_SF_AES_IV_W1_OFFSET;\n+\n+ while (i--) {\n+ iv += 4;\n+ BL_WR_WORD(regionRegBase + tmpVal, (BL_RDWD_FRM_BYTEP(iv)));\n+ tmpVal += 4;\n+ }\n+\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset);\n+ iv += 4;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES iv with big endian\n+ *\n+ * @param region: region number\n+ * @param iv: iv data pointer\n+ * @param addrOffset: flash address offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 3;\n+\n+ if (iv != NULL) {\n+ tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET;\n+\n+ while (i--) {\n+ BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv));\n+ iv += 4;\n+ tmpVal += 4;\n+ }\n+\n+ /*\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv));\n+\t\tiv+=4;\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv));\n+\t\tiv+=4;\n+\t\tBL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv));\n+\t\tiv+=4;\n+\t\t*/\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset));\n+ iv += 4;\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Serial flash controller set AES XTS iv with big endian\n+ *\n+ * @param region: region number\n+ * @param iv: iv data pointer\n+ * @param addrOffset: flash address offset\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset)\n+{\n+ /* Do flash key eco*/\n+ uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);\n+ uint32_t tmpVal, i = 3;\n+\n+ if (iv != NULL) {\n+ tmpVal = SF_CTRL_SF_AES_IV_W2_OFFSET;\n+\n+ while (i--) {\n+ iv += 4;\n+ BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv)));\n+ tmpVal -= 4;\n+ }\n+\n+ BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset));\n+ iv += 4;\n+ }\n+}\n+#endif\n+#ifndef BFLB_USE_ROM_DRIVER\n+\n+/****************************************************************************/ /**\n+ * @brief Set serial flash controller AES mode\n+ *\n+ * @param mode: AES mode select\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode)\n+{\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_AES_MODE_TYPE(mode));\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+\n+ if (mode == SF_CTRL_AES_CTR_MODE) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable serial flash controller AES\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Disable serial flash controller AES\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Check is serial flash controller AES enable\n+ *\n+ * @param None\n+ *\n+ * @return Wether AES is enable\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN)) {\n+ return SET;\n+ }\n+\n+ return RESET;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash image offset\n+ *\n+ * @param addrOffset: Address offset value\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank));\n+\n+ if (group) {\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET, addrOffset);\n+ } else {\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET, addrOffset);\n+ }\n+ } else {\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset);\n+ } else {\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET, addrOffset);\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash image offset\n+ *\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return :Address offset value\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank));\n+\n+ if (group) {\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET);\n+ } else {\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET);\n+ }\n+ } else {\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);\n+ } else {\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET);\n+ }\n+ }\n+\n+ return tmpVal;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Lock/unlock sf_id0/sf_id1/sf_bk2_id0/sf_bk2_id1 offset\n+ *\n+ * @param lock: lock or unlock\n+ *\n+ * @return :None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock)\n+{\n+ uint32_t tmpVal;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);\n+ if (lock) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF controller send one command\n+ *\n+ * @param cfg: Serial flash controller command configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+ uint32_t cmdOffset = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));\n+ CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));\n+ CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));\n+ CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ if (SF_Ctrl_Is_Sbus2_Enable() == RESET) {\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) {\n+ return;\n+ }\n+\n+ cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;\n+ } else {\n+ cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET;\n+ }\n+\n+ /* Clear trigger */\n+ tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG);\n+ BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal);\n+\n+ /* Copy command buffer */\n+ BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_1, cfg->cmdBuf[0]);\n+ BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_2, cfg->cmdBuf[1]);\n+\n+ tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0);\n+\n+ /* Configure SPI and IO mode*/\n+ if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE);\n+ }\n+\n+ if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {\n+ if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_NIO_MODE);\n+ } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DO_MODE);\n+ } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QO_MODE);\n+ }\n+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DIO_MODE);\n+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QIO_MODE);\n+ }\n+\n+ /* Configure cmd */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_CMD_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_CMD_BYTE, 0);\n+\n+ /* Configure address */\n+ if (cfg->addrSize != 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, cfg->addrSize - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, 0);\n+ }\n+\n+ /* Configure dummy */\n+ if (cfg->dummyClks != 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, cfg->dummyClks - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, 0);\n+ }\n+\n+ /* Configure data */\n+ if (cfg->nbData != 0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, cfg->nbData - 1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, 0);\n+ }\n+\n+ /* Set read write flag */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_RW, cfg->rwFlag);\n+ BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal);\n+\n+ /* Trigger */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG);\n+ BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal);\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Ctrl disable iahb to flash wrap access for XTS mode\n+ *\n+ * @param disable: Disable for 1 and enable for 0\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Disable_Wrap_Access(uint8_t disable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ if (disable) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP);\n+ }\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Config SF controller for flash I/D cache read\n+ *\n+ * @param cfg: Serial flash controller command configuration pointer\n+ * @param cmdValid: command valid or not, for continous read, cache may need no command\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));\n+ CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));\n+ CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));\n+ CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {\n+ return;\n+ }\n+\n+ /* Copy command buffer */\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]);\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0);\n+\n+ /* Configure SPI and IO mode*/\n+ if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);\n+ }\n+\n+ if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {\n+ if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);\n+ } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);\n+ } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);\n+ }\n+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);\n+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);\n+ }\n+\n+ if (cmdValid) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);\n+ }\n+\n+ /* Configure address */\n+ if (cfg->addrSize != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);\n+ }\n+\n+ /* configure dummy */\n+ if (cfg->dummyClks != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);\n+ }\n+\n+ /* Configure data */\n+ if (cfg->nbData != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);\n+ }\n+\n+ /* Set read write flag */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Config bank2 controller for flash2 I/D cache read\n+ *\n+ * @param cfg: Serial flash controller command configuration pointer\n+ * @param cmdValid: command valid or not, for continous read, cache may need no command\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t timeOut = 0;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));\n+ CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));\n+ CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));\n+ CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));\n+\n+ timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);\n+\n+ if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {\n+ return;\n+ }\n+\n+ /* Copy command buffer */\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]);\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]);\n+\n+ tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9);\n+\n+ /* Configure SPI and IO mode*/\n+ if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);\n+ }\n+\n+ if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {\n+ if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);\n+ } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);\n+ } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);\n+ }\n+ } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);\n+ } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);\n+ }\n+\n+ if (cmdValid) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);\n+ }\n+\n+ /* Configure address */\n+ if (cfg->addrSize != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);\n+ }\n+\n+ /* configure dummy */\n+ if (cfg->dummyClks != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);\n+ }\n+\n+ /* Configure data */\n+ if (cfg->nbData != 0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);\n+ }\n+\n+ /* Set read write flag */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);\n+\n+ BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get SF Ctrl busy state\n+ *\n+ * @param None\n+ *\n+ * @return SET for SF ctrl busy or RESET for SF ctrl not busy\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t cmdOffset = 0;\n+\n+ if (SF_Ctrl_Is_Sbus2_Enable() == RESET) {\n+ cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;\n+ } else {\n+ cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_IF_BUSY)) {\n+ return SET;\n+ }\n+\n+ return RESET;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SF Controller interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SF_Ctrl_IRQHandler(void)\n+{\n+ /* TODO: Not implemented */\n+}\n+#endif\n+\n+/*@} end of group SF_CTRL_Public_Functions */\n+\n+/*@} end of group SF_CTRL */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d6dfcb749ad5142a7510f03d029dd642176b6860\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c\n@@ -0,0 +1,2164 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_sflash.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_sflash.h\"\n+#include \"bl808_sf_ctrl.h\"\n+#include \"bl808_l1c.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SFLASH\n+ * @{\n+ */\n+\n+/** @defgroup SFLASH_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group SFLASH_Private_Macros */\n+\n+/** @defgroup SFLASH_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SFLASH_Private_Types */\n+\n+/** @defgroup SFLASH_Private_Variables\n+ * @{\n+ */\n+#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000)\n+\n+/*@} end of group SFLASH_Private_Variables */\n+\n+/** @defgroup SFLASH_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SFLASH_Global_Variables */\n+\n+/** @defgroup SFLASH_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group SFLASH_Private_Fun_Declaration */\n+\n+/** @defgroup SFLASH_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group SFLASH_Private_Functions */\n+\n+/** @defgroup SFLASH_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Init serial flash control interface\n+ *\n+ * @param pSfCtrlCfg: Serial flash controller configuration pointer\n+ * @param pBank2Cfg: Serial flash2 controller configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg)\n+{\n+ uint8_t clkDelay = 0;\n+ uint8_t rxClkInvert = 0;\n+\n+ if (pBank2Cfg != NULL) {\n+ if (pBank2Cfg->sbus2Select) {\n+ if (pBank2Cfg->bank2DelaySrc) {\n+ clkDelay = pBank2Cfg->bank2ClkDelay;\n+ } else {\n+ if (pSfCtrlCfg != NULL) {\n+ clkDelay = pSfCtrlCfg->clkDelay;\n+ } else {\n+ clkDelay = 1;\n+ }\n+ }\n+\n+ if (pBank2Cfg->bank2RxClkInvertSrc) {\n+ rxClkInvert = pBank2Cfg->bank2RxClkInvertSel;\n+ } else {\n+ if (pSfCtrlCfg != NULL) {\n+ rxClkInvert = pSfCtrlCfg->rxClkInvert;\n+ } else {\n+ rxClkInvert = 0;\n+ }\n+ }\n+\n+ SF_Ctrl_Sbus2_Set_Delay(clkDelay, rxClkInvert);\n+ } else {\n+ SF_Ctrl_Sbus2_Revoke_replace();\n+ }\n+\n+ SF_Ctrl_Bank2_Enable(pBank2Cfg);\n+ } else {\n+ SF_Ctrl_Sbus2_Revoke_replace();\n+ }\n+\n+ if (pSfCtrlCfg != NULL) {\n+ SF_Ctrl_Enable(pSfCtrlCfg);\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set serial flash control interface SPI or QPI mode\n+ *\n+ * @param mode: Serial flash interface mode\n+ *\n+ * @return BFLB_RET:SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode)\n+{\n+ BL_Err_Type stat = SUCCESS;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode));\n+\n+ return stat;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Read flash register\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param regIndex: register index\n+ * @param regValue: register value pointer to store data\n+ * @param regLen: register value length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint32_t cnt = 0;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24;\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.nbData = regLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ arch_delay_us(1);\n+ cnt++;\n+\n+ if (cnt > 1000) {\n+ return ERROR;\n+ }\n+ }\n+\n+ ARCH_MemCpy(regValue, flashCtrlBuf, regLen);\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Write flash register\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param regIndex: register index\n+ * @param regValue: register value pointer storing data\n+ * @param regLen: register value length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t cnt = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ ARCH_MemCpy(flashCtrlBuf, regValue, regLen);\n+\n+ flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24;\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.nbData = regLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ /* take 40ms for tw(write status register) as default */\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(100);\n+ cnt++;\n+\n+ if (cnt > 400) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Read flash register with read command\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param readRegCmd: read command\n+ * @param regValue: register value pointer to store data\n+ * @param regLen: register value length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint32_t cnt = 0;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = readRegCmd << 24;\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.nbData = regLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ arch_delay_us(1);\n+ cnt++;\n+\n+ if (cnt > 1000) {\n+ return ERROR;\n+ }\n+ }\n+\n+ ARCH_MemCpy(regValue, flashCtrlBuf, regLen);\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Write flash register with write command\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param writeRegCmd: write command\n+ * @param regValue: register value pointer storing data\n+ * @param regLen: register value length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t cnt = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ ARCH_MemCpy(flashCtrlBuf, regValue, regLen);\n+\n+ flashCmd.cmdBuf[0] = writeRegCmd << 24;\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.nbData = regLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ /* take 40ms for tw(write status register) as default */\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(100);\n+ cnt++;\n+\n+ if (cnt > 400) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Check flash busy status\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SET for busy or RESET for not busy\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint32_t stat = 0;\n+ SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen);\n+\n+ if ((stat & (1 << flashCfg->busyBit)) == 0) {\n+ return RESET;\n+ }\n+\n+ return SET;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable flash write function\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint32_t stat = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ /* Write enable*/\n+ flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24;\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen);\n+\n+ if ((stat & (1 << flashCfg->wrEnableBit)) != 0) {\n+ return SUCCESS;\n+ }\n+\n+ return ERROR;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable flash flash controller QSPI interface\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint32_t stat = 0, ret;\n+\n+ if (flashCfg->qeReadRegLen == 0) {\n+ ret = SFlash_Write_Enable(flashCfg);\n+\n+ if (SUCCESS != ret) {\n+ return ERROR;\n+ }\n+\n+ SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);\n+ return SUCCESS;\n+ }\n+\n+ SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);\n+\n+ if (flashCfg->qeData == 0) {\n+ if ((stat & (1 << flashCfg->qeBit)) != 0) {\n+ return SUCCESS;\n+ }\n+ } else {\n+ if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ if (flashCfg->qeWriteRegLen != 1) {\n+ /* This is read r0,read r1 write r0,r1 case*/\n+ SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);\n+ SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1);\n+\n+ if (flashCfg->qeData == 0) {\n+ stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex));\n+ } else {\n+ stat = stat & (~(0xff << (8 * flashCfg->qeIndex)));\n+ stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex));\n+ }\n+ } else {\n+ if (flashCfg->qeData == 0) {\n+ stat |= (1 << (flashCfg->qeBit % 8));\n+ } else {\n+ stat = flashCfg->qeData;\n+ }\n+ }\n+\n+ ret = SFlash_Write_Enable(flashCfg);\n+\n+ if (SUCCESS != ret) {\n+ return ERROR;\n+ }\n+\n+ SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);\n+ SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);\n+\n+ if (flashCfg->qeData == 0) {\n+ if ((stat & (1 << flashCfg->qeBit)) != 0) {\n+ return SUCCESS;\n+ }\n+ } else {\n+ if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {\n+ return SUCCESS;\n+ }\n+ }\n+\n+ return ERROR;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Disable flash flash controller QSPI interface\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint32_t stat = 0, ret;\n+\n+ if (flashCfg->qeReadRegLen == 0) {\n+ ret = SFlash_Write_Enable(flashCfg);\n+\n+ if (SUCCESS != ret) {\n+ return ERROR;\n+ }\n+\n+ SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);\n+ return SUCCESS;\n+ }\n+\n+ SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);\n+\n+ if ((stat & (1 << flashCfg->qeBit)) == 0) {\n+ return SUCCESS;\n+ }\n+\n+ if (flashCfg->qeWriteRegLen != 1) {\n+ /* This is read r0,read r1 write r0,r1 case*/\n+ SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);\n+ SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1);\n+ stat &= (~(1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)));\n+ } else {\n+ stat &= (~(1 << (flashCfg->qeBit % 8)));\n+ }\n+\n+ ret = SFlash_Write_Enable(flashCfg);\n+\n+ if (SUCCESS != ret) {\n+ return ERROR;\n+ }\n+\n+ SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);\n+ SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);\n+\n+ if ((stat & (1 << flashCfg->qeBit)) == 0) {\n+ return SUCCESS;\n+ }\n+\n+ return ERROR;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable flash volatile register write enable\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24;\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash whole chip\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint32_t cnt = 0;\n+ uint32_t timeout = 0;\n+ BL_Err_Type stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24;\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeout = flashCfg->timeCe;\n+\n+ if ((timeout >> 15) > 0) {\n+ timeout = (timeout & 0x7FFF) * 1000;\n+ }\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > timeout * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one sector\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param secNum: flash sector number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum)\n+{\n+ uint32_t cnt = 0;\n+ uint8_t is32BitsAddr = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ BL_Err_Type stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | ((flashCfg->sectorSize * 1024 * secNum) >> 8);\n+ flashCmd.cmdBuf[1] = ((flashCfg->sectorSize * 1024 * secNum) << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum);\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > flashCfg->timeEsector * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one 32K block\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param blkNum: flash 32K block number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)\n+{\n+ uint32_t cnt = 0;\n+ uint8_t is32BitsAddr = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ BL_Err_Type stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8);\n+ flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum);\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > flashCfg->timeE32k * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one 64K block\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param blkNum: flash 64K block number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint32_t cnt = 0;\n+ uint8_t is32BitsAddr = 0;\n+ BL_Err_Type stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) >> 8);\n+ flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum);\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > flashCfg->timeE64k * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one region\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param startaddr: start address to erase\n+ * @param endaddr: end address(include this address) to erase\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr)\n+{\n+ uint32_t len = 0;\n+ uint32_t eraseLen = 0;\n+ BL_Err_Type ret = SUCCESS;\n+\n+ if (startaddr > endaddr) {\n+ return ERROR;\n+ }\n+\n+ while (startaddr <= endaddr) {\n+ len = endaddr - startaddr + 1;\n+\n+ if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID &&\n+ (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 &&\n+ len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) {\n+ /* 64K margin address,and length > 64K-sector size, erase one first */\n+ ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE);\n+ eraseLen = BFLB_SPIFLASH_BLK64K_SIZE;\n+ } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID &&\n+ (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&\n+ len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) {\n+ /* 32K margin address,and length > 32K-sector size, erase one first */\n+ ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE);\n+ eraseLen = BFLB_SPIFLASH_BLK32K_SIZE;\n+ } else {\n+ /* Sector erase */\n+ startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1)));\n+ ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024);\n+ eraseLen = flashCfg->sectorSize * 1024;\n+ }\n+\n+ startaddr += eraseLen;\n+\n+ if (ret != SUCCESS) {\n+ return ERROR;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash unique ID\n+ *\n+ * @param data: data pointer to store read data\n+ * @param idLen: unique ID len\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint8_t cmd, dummyClks;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ dummyClks = 4;\n+ cmd = 0x4B;\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = idLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ ARCH_MemCpy(data, flashCtrlBuf, idLen);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash jedec ID\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param data: data pointer to store read data\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint8_t cmd, dummyClks;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ dummyClks = flashCfg->jedecIdCmdDmyClk;\n+ cmd = flashCfg->jedecIdCmd;\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = 3;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ ARCH_MemCpy(data, flashCtrlBuf, 3);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get flash device ID\n+ *\n+ * @param data: data pointer to store read data\n+ * @param is32BitsAddr: Is flash addr mode in 32-bits\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint8_t cmd, dummyClks;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint32_t addr = 0x00000001;\n+ uint8_t readMode = 0xFF;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ dummyClks = 2;\n+ cmd = 0x94;\n+ flashCmd.addrSize = 4;\n+\n+ if (is32BitsAddr) {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);\n+ flashCmd.cmdBuf[1] = (addr << 24) | (readMode << 16);\n+ flashCmd.addrSize++;\n+ } else {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr);\n+ flashCmd.cmdBuf[1] = (readMode << 24);\n+ }\n+\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = 2;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+\n+ ARCH_MemCpy(data, flashCtrlBuf, 2);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash power down\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_Powerdown(void)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint8_t cmd = 0;\n+ uint32_t timeOut = 0;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ cmd = 0xB9;\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Release flash power down for wake up\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint8_t cmd;\n+ uint32_t timeOut = 0;\n+\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ cmd = flashCfg->releasePowerDown;\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return;\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Sflash restore from power down\n+ *\n+ * @param pFlashCfg: Flash configuration pointer\n+ * @param flashContRead: Whether enable continuous read\n+ * @param bank: bank select type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead,\n+ SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat = SUCCESS;\n+ uint32_t jdecId = 0;\n+ uint8_t tmp[8];\n+ uint8_t ioMode = pFlashCfg->ioMode & 0xf;\n+\n+ /* Wake flash up from power down */\n+ SFlash_Release_Powerdown(pFlashCfg);\n+ arch_delay_us(120);\n+\n+ SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);\n+\n+ if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) {\n+ SFlash_Qspi_Enable(pFlashCfg);\n+ }\n+\n+ if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) {\n+ /* unwrap */\n+ L1C_Set_Wrap(DISABLE);\n+ } else {\n+ /* burst wrap */\n+ L1C_Set_Wrap(ENABLE);\n+ /* For command that is setting register instead of send command, we need write enable */\n+ SFlash_Write_Enable(pFlashCfg);\n+ SFlash_SetBurstWrap(pFlashCfg);\n+ }\n+\n+ if (flashContRead) {\n+ stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));\n+ stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32, bank);\n+ }\n+\n+ return stat;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash burst wrap config\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint8_t cmd, dummyClks;\n+ uint32_t wrapData;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((flashCfg->ioMode >> 4) & 0x01) == 1) {\n+ /* Disable burst wrap ,just return */\n+ return;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode;\n+ flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode;\n+ dummyClks = flashCfg->burstWrapCmdDmyClk;\n+ cmd = flashCfg->burstWrapCmd;\n+ wrapData = flashCfg->burstWrapData;\n+ ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = 1;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Disable flash burst wrap config\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint8_t cmd, dummyClks;\n+ uint32_t wrapData;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode;\n+ flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode;\n+ dummyClks = flashCfg->deBurstWrapCmdDmyClk;\n+ cmd = flashCfg->deBurstWrapCmd;\n+ wrapData = flashCfg->deBurstWrapData;\n+ ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = 1;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set flash 24-bits or 32-bits addr mode\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param en32BitsAddr: Serial flash enable or disable 32-bits addr\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint8_t cmd = 0;\n+\n+ if ((flashCfg->ioMode & 0x20) == 0) {\n+ return ERROR;\n+ }\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ SF_Ctrl_32bits_Addr_En(en32BitsAddr);\n+\n+ if (en32BitsAddr) {\n+ cmd = flashCfg->enter32BitsAddrCmd;\n+ } else {\n+ cmd = flashCfg->exit32BitsAddrCmd;\n+ }\n+\n+ flashCmd.cmdBuf[0] = (cmd << 24);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Software reset flash\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ uint16_t cnt = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ /* Reset enable */\n+ flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24;\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+\n+ /* Wait for write done */\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(100);\n+ cnt++;\n+\n+ if (cnt > 20) {\n+ return ERROR;\n+ }\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ /* Reset */\n+ flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24;\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ arch_delay_us(50);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Reset flash continous read mode\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg)\n+{\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ /* Reset continous read */\n+ ARCH_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = flashCfg->resetCreadCmdSize;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Set I/D bus read flash configuration in flash controller\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param ioMode: flash controller interface mode\n+ * @param contRead: Wether enable cont read mode\n+ * @param addr: address to read/write\n+ * @param len: data length to read/write\n+ * @param bank: bank select type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,\n+ uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank)\n+{\n+ uint8_t cmd, dummyClks;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint8_t cmdValid = 1;\n+ uint8_t noReadModeCfg = 0;\n+ uint8_t cReadSupport = 0;\n+ uint8_t is32BitsAddr = 0;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);\n+\n+ if (SF_CTRL_NIO_MODE == ioMode) {\n+ cmd = flashCfg->fastReadCmd;\n+ dummyClks = flashCfg->frDmyClk;\n+ } else if (SF_CTRL_DO_MODE == ioMode) {\n+ flashCmd.dataMode = SF_CTRL_DATA_2_LINES;\n+ cmd = flashCfg->fastReadDoCmd;\n+ dummyClks = flashCfg->frDoDmyClk;\n+ } else if (SF_CTRL_DIO_MODE == ioMode) {\n+ flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;\n+ flashCmd.dataMode = SF_CTRL_DATA_2_LINES;\n+ cmd = flashCfg->fastReadDioCmd;\n+ dummyClks = flashCfg->frDioDmyClk;\n+ } else if (SF_CTRL_QO_MODE == ioMode) {\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ cmd = flashCfg->fastReadQoCmd;\n+ dummyClks = flashCfg->frQoDmyClk;\n+ } else if (SF_CTRL_QIO_MODE == ioMode) {\n+ flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ cmd = flashCfg->fastReadQioCmd;\n+ dummyClks = flashCfg->frQioDmyClk;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /*prepare command**/\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);\n+ flashCmd.cmdBuf[1] = (addr << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | addr;\n+ }\n+\n+ if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {\n+ noReadModeCfg = flashCfg->cReadSupport & 0x02;\n+ cReadSupport = flashCfg->cReadSupport & 0x01;\n+\n+ if (noReadModeCfg == 0) {\n+ /* Read mode must be set*/\n+ if (cReadSupport == 0) {\n+ /* Not support cont read,but we still need set read mode(winbond 80dv)*/\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16);\n+ } else {\n+ flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);\n+ }\n+ } else {\n+ /* Flash support cont read, setting depend on user parameter */\n+ if (contRead) {\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[0] = addr;\n+ flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode;\n+ }\n+\n+ cmdValid = 0;\n+ } else {\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16);\n+ } else {\n+ flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);\n+ }\n+ }\n+ }\n+\n+ flashCmd.addrSize++;\n+ }\n+ }\n+\n+ flashCmd.dummyClks = dummyClks;\n+ flashCmd.nbData = len;\n+ if (bank == SF_CTRL_FLASH_BANK0) {\n+ SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid);\n+ } else {\n+ SF_Ctrl_Flash2_Read_Icache_Set(&flashCmd, cmdValid);\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Enable I/D bus read from flash\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param ioMode: flash controller interface mode\n+ * @param contRead: Wether enable cont read mode\n+ * @param bank: bank select type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode,\n+ uint8_t contRead, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+\n+ stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32, bank);\n+\n+ if (SUCCESS != stat) {\n+ return stat;\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Disable read from flash with IDbus\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+void ATTR_TCM_SECTION SFlash_IDbus_Read_Disable(void)\n+{\n+ //L1C_Cache_Read_Disable();\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Sflash enable RCV mode to recovery for erase while power drop\n+ *\n+ * @param pFlashCfg: Flash configuration pointer\n+ * @param rCmd: Read RCV register cmd\n+ * @param wCmd: Write RCV register cmd\n+ * @param bitPos: RCV register bit pos\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos)\n+{\n+ BL_Err_Type stat;\n+ uint32_t cnt = 0;\n+ uint32_t tempVal = 0;\n+\n+ while (SET == SFlash_Busy(pFlashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > 20000 * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1);\n+\n+ if (SUCCESS != stat) {\n+ stat = ERROR;\n+ }\n+\n+ if (((tempVal >> bitPos) & 0x01) > 0) {\n+ return SUCCESS;\n+ }\n+\n+ tempVal |= (uint32_t)(1 << bitPos);\n+ stat = SFlash_Write_Enable(pFlashCfg);\n+\n+ if (SUCCESS != stat) {\n+ stat = ERROR;\n+ }\n+\n+ stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1);\n+\n+ if (SUCCESS != stat) {\n+ return stat;\n+ }\n+\n+ while (SET == SFlash_Busy(pFlashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > 20000 * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1);\n+\n+ if (SUCCESS != stat) {\n+ stat = ERROR;\n+ }\n+\n+ if (((tempVal >> bitPos) & 0x01) <= 0) {\n+ return ERROR;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash security register one block\n+ *\n+ * @param pFlashCfg: Flash configuration pointer\n+ * @param pSecRegCfg: Security register configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg)\n+{\n+ uint32_t cnt = 0;\n+ uint8_t cmd = 0;\n+ uint8_t secOptMode = 0;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (pSecRegCfg->enterSecOptCmd != 0x00) {\n+ secOptMode = 1;\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ cmd = pSecRegCfg->eraseCmd;\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12);\n+ /* rwFlag don't care */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ while (SET == SFlash_Busy(pFlashCfg)) {\n+ arch_delay_us(500);\n+ cnt++;\n+\n+ if (cnt > pFlashCfg->timeEsector * 3) {\n+ return ERROR;\n+ }\n+ }\n+\n+ if (secOptMode > 0) {\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Program flash security register one block\n+ *\n+ * @param pFlashCfg: Flash configuration pointer\n+ * @param pSecRegCfg: Security register configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t i = 0, curLen = 0;\n+ uint32_t cnt = 0;\n+ BL_Err_Type stat;\n+ uint8_t cmd;\n+ uint8_t secOptMode = 0;\n+ uint8_t *data = pSecRegCfg->data;\n+ uint32_t addr = pSecRegCfg->addr;\n+ uint32_t len = pSecRegCfg->len;\n+ uint32_t currentAddr = 0;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (pSecRegCfg->enterSecOptCmd != 0x00) {\n+ secOptMode = 1;\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ /* Prepare command */\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.addrSize = 3;\n+ cmd = pSecRegCfg->programCmd;\n+\n+ for (i = 0; i < len;) {\n+ /* Write enable is needed for every program */\n+ stat = SFlash_Write_Enable(pFlashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ /* Get current programmed length within page size */\n+ curLen = 256 - addr % 256;\n+\n+ if (curLen > len - i) {\n+ curLen = len - i;\n+ }\n+\n+ currentAddr = (pSecRegCfg->blockNum << 12) | addr;\n+\n+ /* Prepare command */\n+ arch_memcpy_fast(flashCtrlBuf, data, curLen);\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr);\n+ flashCmd.nbData = curLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ /* Adjust address and programmed length */\n+ addr += curLen;\n+ i += curLen;\n+ data += curLen;\n+\n+ /* Wait for write done */\n+ cnt = 0;\n+\n+ while (SET == SFlash_Busy(pFlashCfg)) {\n+ arch_delay_us(100);\n+ cnt++;\n+\n+ if (cnt > pFlashCfg->timePagePgm * 20) {\n+ return ERROR;\n+ }\n+ }\n+ }\n+\n+ if (secOptMode > 0) {\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from flash security register one block\n+ *\n+ * @param pSecRegCfg: Security register configuration pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t curLen, i;\n+ uint8_t cmd;\n+ uint8_t secOptMode = 0;\n+ uint8_t *data = pSecRegCfg->data;\n+ uint32_t addr = pSecRegCfg->addr;\n+ uint32_t len = pSecRegCfg->len;\n+ uint32_t currentAddr = 0;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (pSecRegCfg->enterSecOptCmd != 0x00) {\n+ secOptMode = 1;\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ /* Prepare command */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+ flashCmd.dummyClks = 1;\n+ cmd = pSecRegCfg->readCmd;\n+\n+ /* Read data */\n+ for (i = 0; i < len;) {\n+ currentAddr = (pSecRegCfg->blockNum << 12) | addr;\n+ /* Prepare command */\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr);\n+ curLen = len - i;\n+\n+ if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) {\n+ curLen = NOR_FLASH_CTRL_BUF_SIZE;\n+ flashCmd.nbData = curLen;\n+ } else {\n+ /* Make sf_ctrl word read */\n+ flashCmd.nbData = ((curLen + 3) >> 2) << 2;\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ arch_memcpy_fast(data, flashCtrlBuf, curLen);\n+\n+ addr += curLen;\n+ i += curLen;\n+ data += curLen;\n+ }\n+\n+ if (secOptMode > 0) {\n+ if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) {\n+ arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ arch_memset(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from flash\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param ioMode: flash controller interface mode\n+ * @param contRead: Wether enable cont read mode\n+ * @param addr: flash read start address\n+ * @param data: data pointer to store data read from flash\n+ * @param len: data length to read\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,\n+ SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t curLen, i;\n+ uint8_t cmd, dummyClks;\n+ uint32_t timeOut = 0;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+ uint8_t noReadModeCfg = 0;\n+ uint8_t cReadSupport = 0;\n+ uint8_t is32BitsAddr = 0;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ if (SF_CTRL_NIO_MODE == ioMode) {\n+ cmd = flashCfg->fastReadCmd;\n+ dummyClks = flashCfg->frDmyClk;\n+ } else if (SF_CTRL_DO_MODE == ioMode) {\n+ flashCmd.dataMode = SF_CTRL_DATA_2_LINES;\n+ cmd = flashCfg->fastReadDoCmd;\n+ dummyClks = flashCfg->frDoDmyClk;\n+ } else if (SF_CTRL_DIO_MODE == ioMode) {\n+ flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;\n+ flashCmd.dataMode = SF_CTRL_DATA_2_LINES;\n+ cmd = flashCfg->fastReadDioCmd;\n+ dummyClks = flashCfg->frDioDmyClk;\n+ } else if (SF_CTRL_QO_MODE == ioMode) {\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ cmd = flashCfg->fastReadQoCmd;\n+ dummyClks = flashCfg->frQoDmyClk;\n+ } else if (SF_CTRL_QIO_MODE == ioMode) {\n+ flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ cmd = flashCfg->fastReadQioCmd;\n+ dummyClks = flashCfg->frQioDmyClk;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* Prepare command */\n+ flashCmd.rwFlag = SF_CTRL_READ;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ }\n+\n+ if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {\n+ noReadModeCfg = flashCfg->cReadSupport & 0x02;\n+ cReadSupport = flashCfg->cReadSupport & 0x01;\n+\n+ if (noReadModeCfg == 0) {\n+ /* Read mode must be set*/\n+ if (cReadSupport == 0) {\n+ /* Not support cont read,but we still need set read mode(winbond 80dv)*/\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16);\n+ } else {\n+ flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);\n+ }\n+ } else {\n+ /* Flash support cont read, setting depend on user parameter */\n+ if (contRead) {\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16);\n+ } else {\n+ flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);\n+ }\n+ } else {\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16);\n+ } else {\n+ flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);\n+ }\n+ }\n+ }\n+\n+ flashCmd.addrSize++;\n+ }\n+ }\n+\n+ flashCmd.dummyClks = dummyClks;\n+\n+ /* Read data */\n+ for (i = 0; i < len;) {\n+ /* Prepare command */\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);\n+ flashCmd.cmdBuf[1] |= (addr << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr);\n+ }\n+\n+ curLen = len - i;\n+\n+ if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) {\n+ curLen = NOR_FLASH_CTRL_BUF_SIZE;\n+ flashCmd.nbData = curLen;\n+ } else {\n+ /* Make sf_ctrl word read */\n+ flashCmd.nbData = ((curLen + 3) >> 2) << 2;\n+ }\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ timeOut = SFCTRL_BUSY_STATE_TIMEOUT;\n+\n+ while (SET == SF_Ctrl_GetBusyState()) {\n+ timeOut--;\n+\n+ if (timeOut == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ ARCH_MemCpy_Fast(data, flashCtrlBuf, curLen);\n+\n+ addr += curLen;\n+ i += curLen;\n+ data += curLen;\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Program flash one region\n+ *\n+ * @param flashCfg: Serial flash parameter configuration pointer\n+ * @param ioMode: progran mode:SPI mode or QPI mode\n+ * @param addr: start address to be programed\n+ * @param data: data pointer to be programed\n+ * @param len: data length to be programed\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,\n+ SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)\n+{\n+ uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;\n+ uint32_t i = 0, curLen = 0;\n+ uint32_t cnt = 0;\n+ uint8_t is32BitsAddr = 0;\n+ BL_Err_Type stat;\n+ uint8_t cmd;\n+ SF_Ctrl_Cmd_Cfg_Type flashCmd;\n+\n+ if (((uintptr_t)&flashCmd) % 4 == 0) {\n+ ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);\n+ } else {\n+ ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd));\n+ }\n+\n+ if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {\n+ cmd = flashCfg->pageProgramCmd;\n+ } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) {\n+ flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode;\n+ flashCmd.dataMode = SF_CTRL_DATA_4_LINES;\n+ cmd = flashCfg->qpageProgramCmd;\n+ } else {\n+ return ERROR;\n+ }\n+\n+ is32BitsAddr = (flashCfg->ioMode & 0x20);\n+ /* Prepare command */\n+ flashCmd.rwFlag = SF_CTRL_WRITE;\n+ flashCmd.addrSize = 3;\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.addrSize++;\n+ }\n+\n+ for (i = 0; i < len;) {\n+ /* Write enable is needed for every program */\n+ stat = SFlash_Write_Enable(flashCfg);\n+\n+ if (stat != SUCCESS) {\n+ return stat;\n+ }\n+\n+ /* Get current programmed length within page size */\n+ curLen = flashCfg->pageSize - addr % flashCfg->pageSize;\n+\n+ if (curLen > len - i) {\n+ curLen = len - i;\n+ }\n+\n+ /* Prepare command */\n+ ARCH_MemCpy_Fast(flashCtrlBuf, data, curLen);\n+\n+ if (is32BitsAddr > 0) {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8);\n+ flashCmd.cmdBuf[1] = (addr << 24);\n+ } else {\n+ flashCmd.cmdBuf[0] = (cmd << 24) | (addr);\n+ }\n+\n+ flashCmd.nbData = curLen;\n+\n+ SF_Ctrl_SendCmd(&flashCmd);\n+\n+ /* Adjust address and programmed length */\n+ addr += curLen;\n+ i += curLen;\n+ data += curLen;\n+\n+ /* Wait for write done */\n+ cnt = 0;\n+\n+ while (SET == SFlash_Busy(flashCfg)) {\n+ arch_delay_us(100);\n+ cnt++;\n+\n+ if (cnt > flashCfg->timePagePgm * 20) {\n+ return ERROR;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/*@} end of group SFLASH_Public_Functions */\n+\n+/*@} end of group SFLASH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4776ac4c74f7ddea1bb3d443bfbb3ab51078b373\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c\n@@ -0,0 +1,1373 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_spi.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_spi.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup SPI\n+ * @{\n+ */\n+\n+/** @defgroup SPI_Private_Macros\n+ * @{\n+ */\n+#define SPI_TX_TIMEOUT_COUNT (320 * 1000)\n+#define SPI_RX_TIMEOUT_COUNT (320 * 1000)\n+\n+/*@} end of group SPI_Private_Macros */\n+\n+/** @defgroup SPI_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group SPI_Private_Types */\n+\n+/** @defgroup SPI_Private_Variables\n+ * @{\n+ */\n+const uint32_t spiAddr[SPI_ID_MAX] = { SPI0_BASE, SPI1_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = {\n+ { NULL }\n+};\n+#endif\n+\n+/*@} end of group SPI_Private_Variables */\n+\n+/** @defgroup SPI_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group SPI_Global_Variables */\n+\n+/** @defgroup SPI_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void SPI_IntHandler(SPI_ID_Type spiNo);\n+#endif\n+\n+/*@} end of group SPI_Private_Fun_Declaration */\n+\n+/** @defgroup SPI_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief SPI interrupt common handler function\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void SPI_IntHandler(SPI_ID_Type spiNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);\n+\n+ /* Transfer end interrupt,shared by both master and slave mode */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) {\n+ BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR));\n+\n+ if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_END]();\n+ }\n+ }\n+\n+ /* TX fifo ready interrupt(fifo count > fifo threshold) */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) {\n+ if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* RX fifo ready interrupt(fifo count > fifo threshold) */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) {\n+ if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) {\n+ BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR));\n+\n+ if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT]();\n+ }\n+ }\n+\n+ /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) {\n+ BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR));\n+\n+ if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN]();\n+ }\n+ }\n+\n+ /* TX/RX fifo overflow/underflow interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) {\n+ if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) {\n+ spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group SPI_Private_Functions */\n+\n+/** @defgroup SPI_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief SPI initialization function\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param spiCfg: SPI configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(slavePin));\n+ CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod));\n+ CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence));\n+ CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence));\n+ CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv));\n+ CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity));\n+\n+ /* Disable clock gate when use SPI0 */\n+ if (SPI0_ID == spiNo) {\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SPI);\n+ }\n+\n+ /* spi config */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_S_3PIN_MODE, spiCfg->slavePin);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize);\n+ BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(SPI0_IRQn, SPI0_IRQHandler);\n+ Interrupt_Handler_Register(SPI1_IRQn, SPI1_IRQHandler);\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI set default value of all registers function\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ if (SPI0_ID == spiNo) {\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SPI);\n+ } else if (SPI0_MM_ID == spiNo) {\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_SPI);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Length of data phase1/0,start/stop condition and interval between frame initialization\n+ * function\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param clockCfg: Clock configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Configure length of data phase1/0 and start/stop condition */\n+ tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1);\n+ BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);\n+\n+ /* Configure length of interval between frame */\n+ tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);\n+ BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI configure fifo function\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param fifoCfg: FIFO configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Set fifo threshold value */\n+ tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold);\n+ BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal);\n+\n+ /* Enable or disable dma function */\n+ tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable);\n+ BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set SPI Frame Size\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param frameSize: FrameSize Type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(frameSize));\n+\n+ /* The SPI must be clear fifo first */\n+ SPI_ClrRxFifo(spiNo);\n+ SPI_ClrTxFifo(spiNo);\n+\n+ /* set framsize*/\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, frameSize);\n+ BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set SPI SCK Clcok\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param clk: Clk\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk)\n+{\n+ uint32_t glb_div = 0, spi_div = 0;\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ if (clk > 80000000) {\n+ clk = 80000000;\n+ } else if (clk < 9766) {\n+ clk = 9766;\n+ }\n+\n+ if (clk >= 312500) {\n+ glb_div = 0;\n+ spi_div = 80000000 / clk - 1;\n+ } else {\n+ glb_div = 31;\n+ spi_div = 2500000 / clk - 1;\n+ }\n+\n+ if (spiNo == SPI0_ID) {\n+ GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, glb_div);\n+ } else {\n+ GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, glb_div);\n+ }\n+\n+ /* Configure length of data phase1/0 and start/stop condition */\n+ tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div);\n+ BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);\n+ BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable spi transfer\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param modeType: Master or slave mode select\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));\n+\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+\n+ if (modeType != SPI_WORK_MODE_SLAVE) {\n+ /* master mode */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);\n+ } else {\n+ /* slave mode */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);\n+ }\n+\n+ BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable spi transfer\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param modeType: Master or slave mode select\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));\n+\n+ /* close master and slave */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);\n+ BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param value: Time value\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Set time-out value */\n+ tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE);\n+ BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Set de-glitch function cycle count value\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param cnt: De-glitch function cycle count\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Set count value */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt);\n+ BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable rx data ignore function and set start/stop point\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param startPoint: Start point\n+ * @param stopPoint: Stop point\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Enable rx ignore function */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));\n+\n+ /* Set start and stop point */\n+ tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint;\n+ BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable rx data ignore function\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Disable rx ignore function */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear tx fifo and tx fifo overflow/underflow status\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Clear tx fifo */\n+ tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);\n+ BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear rx fifo and rx fifo overflow/underflow status\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Clear rx fifo */\n+ tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);\n+ BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Clear spi interrupt status\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param intType: SPI interrupt type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Clear certain or all interrupt */\n+ tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);\n+\n+ if (SPI_INT_ALL == intType) {\n+ tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS;\n+ } else {\n+ tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS);\n+ }\n+\n+ BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI mask or unmask certain or all interrupt\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param intType: SPI interrupt type\n+ * @param intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);\n+\n+ /* Mask or unmask certain or all interrupt */\n+ if (SPI_INT_ALL == intType) {\n+ if (MASK == intMask) {\n+ tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS;\n+ } else {\n+ tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS);\n+ }\n+ } else {\n+ if (MASK == intMask) {\n+ tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS);\n+ } else {\n+ tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS));\n+ }\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install spi interrupt callback function\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param intType: SPI interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_INT_TYPE(intType));\n+\n+ spiIntCbfArra[spiNo][intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SPI send datas\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param buff: Buffer of datas\n+ * @param length: Length of buffer\n+ * @param timeoutType: Enable or disable timeout judgment\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t txLen = 0;\n+ uint32_t rData;\n+ uint32_t frameSize = 0;\n+ uint32_t SPIx = spiAddr[spiNo];\n+ uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));\n+\n+ /* Get fifo valid width */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE);\n+\n+ switch (frameSize) {\n+ case 0:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 1:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2);\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 2:\n+\n+ /* Same as case 3 */\n+ case 3:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4);\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI receive datas\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param buff: Buffer of datas\n+ * @param length: Length of buffer\n+ * @param timeoutType: Enable or disable timeout judgment\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t rxLen = 0;\n+ uint32_t frameSize = 0;\n+ uint32_t SPIx = spiAddr[spiNo];\n+ uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));\n+\n+ /* Get fifo valid width */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE);\n+\n+ switch (frameSize) {\n+ case 0:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;\n+\n+ /* Fill tx fifo with 0 */\n+ for (rxLen = 0; rxLen < tmpVal; rxLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive data and send the rest of the data 0 */\n+ for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (; rxLen < length; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 1:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2);\n+\n+ /* Fill tx fifo with 0 */\n+ for (rxLen = 0; rxLen < tmpVal; rxLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive data and send the rest of the data 0 */\n+ for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (; rxLen < length; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 2:\n+\n+ /* Same as case 3 */\n+ case 3:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4);\n+\n+ /* Fill tx fifo with 0 */\n+ for (rxLen = 0; rxLen < tmpVal; rxLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive data and send the rest of the data 0 */\n+ for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (; rxLen < length; rxLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI send and receive datas at the same time\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param sendBuff: Buffer of datas to send\n+ * @param recvBuff: Buffer of datas received\n+ * @param length: Length of buffer\n+ * @param timeoutType: Enable or disable timeout judgment\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t txLen = 0;\n+ uint32_t frameSize = 0;\n+ uint32_t SPIx = spiAddr[spiNo];\n+ uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));\n+\n+ /* Get fifo valid width */\n+ tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);\n+ frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE);\n+\n+ switch (frameSize) {\n+ case 0:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint8_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint8_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 1:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2);\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint16_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint16_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ case 2:\n+\n+ /* Same as case 3 */\n+ case 3:\n+\n+ tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4);\n+\n+ /* Fill tx fifo */\n+ for (; txLen < tmpVal; txLen++) {\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive data and send the rest of the data */\n+ for (; txLen < length; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint32_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]);\n+ }\n+\n+ /* Wait receive the rest of the data */\n+ for (txLen = 0; txLen < tmpVal; txLen++) {\n+ timeoutCnt = SPI_RX_TIMEOUT_COUNT;\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) {\n+ if (timeoutType) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ ((uint32_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get tx fifo available count value function\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return Count value\n+ *\n+*******************************************************************************/\n+uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo)\n+{\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Get count value */\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get rx fifo available count value function\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return Count value\n+ *\n+*******************************************************************************/\n+uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo)\n+{\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Get count value */\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get spi interrupt status\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param intType: SPI interrupt type\n+ *\n+ * @return Status of interrupt\n+ *\n+*******************************************************************************/\n+BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_INT_TYPE(intType));\n+\n+ /* Get certain or all interrupt status */\n+ tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);\n+\n+ if (SPI_INT_ALL == intType) {\n+ if ((tmpVal & 0x3f) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ if ((tmpVal & (1U << intType)) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get indicator of spi bus busy\n+ *\n+ * @param spiNo: SPI ID type\n+ *\n+ * @return Status of spi bus\n+ *\n+*******************************************************************************/\n+BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+\n+ /* Get bus busy status */\n+ tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get tx/rx fifo overflow or underflow status\n+ *\n+ * @param spiNo: SPI ID type\n+ * @param fifoSts: Select tx/rx overflow or underflow\n+ *\n+ * @return Status of tx/rx fifo\n+ *\n+*******************************************************************************/\n+BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts)\n+{\n+ uint32_t tmpVal;\n+ uint32_t SPIx = spiAddr[spiNo];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));\n+ CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts));\n+\n+ /* Get tx/rx fifo overflow or underflow status */\n+ tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);\n+\n+ if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief SPI0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SPI0_IRQHandler(void)\n+{\n+ SPI_IntHandler(SPI0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief SPI1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void SPI1_IRQHandler(void)\n+{\n+ SPI_IntHandler(SPI0_MM_ID);\n+}\n+#endif\n+\n+/*@} end of group SPI_Public_Functions */\n+\n+/*@} end of group SPI */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0c27913ed40a8138c77b30eb2f228066802b9c3e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c\n@@ -0,0 +1,1317 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_timer.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_timer.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TIMER\n+ * @{\n+ */\n+\n+/** @defgroup TIMER_Private_Macros\n+ * @{\n+ */\n+#define TIMER_MAX_MATCH 3\n+\n+/*@} end of group TIMER_Private_Macros */\n+\n+/** @defgroup TIMER_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group TIMER_Private_Types */\n+\n+/** @defgroup TIMER_Private_Variables\n+ * @{\n+ */\n+static const uint32_t timerAddr[TIMER_ID_MAX] = { TIMER0_BASE, TIMER1_BASE };\n+#ifndef BFLB_USE_HAL_DRIVER\n+intCallback_Type *timerIntCbfArra[TIMER_ID_MAX][TIMER_CH_MAX][TIMER_INT_ALL] = { NULL };\n+intCallback_Type *wdtIntCbfArra[WDT_ID_MAX][WDT_INT_ALL] = { NULL };\n+#endif\n+\n+/*@} end of group TIMER_Private_Variables */\n+\n+/** @defgroup TIMER_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group TIMER_Global_Variables */\n+\n+/** @defgroup TIMER_Private_Fun_Declaration\n+ * @{\n+ */\n+#ifndef BFLB_USE_HAL_DRIVER\n+static void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh);\n+#endif\n+\n+/*@} end of group TIMER_Private_Fun_Declaration */\n+\n+/** @defgroup TIMER_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER interrupt common handler function\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t intId;\n+ uint32_t tmpVal;\n+ uint32_t tmpAddr;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ intId = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh);\n+ tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh;\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+\n+ /* Comparator 0 match interrupt */\n+ if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_0)) {\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_0));\n+\n+ if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0] != NULL) {\n+ /* Call the callback function */\n+ timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0]();\n+ }\n+ }\n+\n+ /* Comparator 1 match interrupt */\n+ if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_1)) {\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_1));\n+\n+ if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1] != NULL) {\n+ /* Call the callback function */\n+ timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1]();\n+ }\n+ }\n+\n+ /* Comparator 2 match interrupt */\n+ if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_2)) {\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_2));\n+\n+ if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2] != NULL) {\n+ /* Call the callback function */\n+ timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2]();\n+ }\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get the specified channel and match comparator value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param cmpNo: TIMER comparator ID type\n+ *\n+ * @return Match comapre register value\n+ *\n+*******************************************************************************/\n+uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));\n+\n+ tmpVal = BL_RD_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo));\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set specified channel and comparator compare value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param cmpNo: TIMER comparator ID type\n+ * @param val: TIMER match compare register value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val)\n+{\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));\n+\n+ BL_WR_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER enable or disable compare value effect immediately after update\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCMR);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_ALIGN, 1 - enable);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_ALIGN, 1 - enable);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_TCMR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get the specified channel count value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return TIMER count register value\n+ *\n+*******************************************************************************/\n+uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpAddr;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpAddr = TIMERx + TIMER_TCR2_OFFSET+ 4 * timerCh;\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER reset count value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCER);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR);\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR);\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR);\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR);\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get specified channel and comparator match status\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param cmpNo: TIMER comparator ID type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)\n+{\n+ uint32_t tmpVal;\n+ BL_Sts_Type bitStatus = RESET;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));\n+\n+ tmpVal = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh);\n+\n+ switch (cmpNo) {\n+ case TIMER_COMP_ID_0:\n+ bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_0) ? SET : RESET;\n+ break;\n+\n+ case TIMER_COMP_ID_1:\n+ bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_1) ? SET : RESET;\n+ break;\n+\n+ case TIMER_COMP_ID_2:\n+ bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_2) ? SET : RESET;\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ return bitStatus;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get specified channel preload value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return Preload register value\n+ *\n+*******************************************************************************/\n+uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ return BL_RD_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set preload register low 32bits value\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param val: Preload register low 32bits value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val)\n+{\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ BL_WR_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh, val);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param plSrc: TIMER preload source type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc)\n+{\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc));\n+\n+ BL_WR_WORD(TIMERx + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set count mode:preload or free run\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode)\n+{\n+ uint32_t tmpval;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode));\n+\n+ tmpval = BL_RD_WORD(TIMERx + TIMER_TCMR_OFFSET);\n+ tmpval &= (~(1 << (timerCh + 1)));\n+ tmpval |= (countMode << (timerCh + 1));\n+\n+ BL_WR_WORD(TIMERx + TIMER_TCMR_OFFSET, tmpval);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER clear interrupt status\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param cmpNo: TIMER macth comparator ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo)\n+{\n+ uint32_t tmpAddr;\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));\n+\n+ tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh;\n+\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+ tmpVal |= (1 << cmpNo);\n+\n+ BL_WR_WORD(tmpAddr, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER initialization function\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCfg: TIMER configuration structure pointer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg)\n+{\n+ TIMER_Chan_Type timerCh = timerCfg->timerCh;\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh));\n+ CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc));\n+ CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode));\n+\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_TIMER);\n+\n+ /* Configure timer clock source */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_3, timerCfg->clkSrc);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal);\n+\n+ /* Configure timer clock division */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal);\n+\n+ /* Configure timer count mode: preload or free run */\n+ TIMER_SetCountMode(timerId, timerCh, timerCfg->countMode);\n+\n+ /* Configure timer preload trigger src */\n+ TIMER_SetPreloadTrigSrc(timerId, timerCh, timerCfg->plTrigSrc);\n+\n+ if (timerCfg->countMode == TIMER_COUNT_PRELOAD) {\n+ /* Configure timer preload value */\n+ TIMER_SetPreloadValue(timerId, timerCh, timerCfg->preLoadVal);\n+\n+ /* Configure match compare values */\n+ if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);\n+ }\n+\n+ if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);\n+ }\n+\n+ if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);\n+ }\n+ } else {\n+ /* Configure match compare values */\n+ if (timerCfg->matchVal0 > 1) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);\n+ }\n+\n+ if (timerCfg->matchVal1 > 1) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);\n+ }\n+\n+ if (timerCfg->matchVal2 > 1) {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);\n+ } else {\n+ TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);\n+ }\n+ }\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(TIMER0_CH0_IRQn, TIMER0_CH0_IRQHandler);\n+ Interrupt_Handler_Register(TIMER0_CH1_IRQn, TIMER0_CH1_IRQHandler);\n+ Interrupt_Handler_Register(TIMER1_CH0_IRQn, TIMER1_CH0_IRQHandler);\n+ Interrupt_Handler_Register(TIMER1_CH1_IRQn, TIMER1_CH1_IRQHandler);\n+\n+#endif\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set default value of all registers function\n+ *\n+ * @param timerId: TIMER ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId)\n+{\n+ if (TIMER0_ID == timerId) {\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_TIMER);\n+ } else if (TIMER1_ID == timerId) {\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_TIMER);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER enable one channel function\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCER);\n+ tmpVal |= (1 << (timerCh + 1));\n+\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER disable one channel function\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCER);\n+ tmpVal &= (~(1 << (timerCh + 1)));\n+\n+ BL_WR_REG(TIMERx, TIMER_TCER, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER mask or unmask certain or all interrupt\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param intType: TIMER interrupt type\n+ * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpAddr;\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+ CHECK_PARAM(IS_TIMER_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpAddr = TIMERx + TIMER_TIER2_OFFSET + 4 * timerCh;\n+ tmpVal = BL_RD_WORD(tmpAddr);\n+\n+ switch (intType) {\n+ case TIMER_INT_COMP_0:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0));\n+ } else {\n+ /* Disable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0));\n+ }\n+\n+ break;\n+\n+ case TIMER_INT_COMP_1:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1));\n+ } else {\n+ /* Disable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1));\n+ }\n+\n+ break;\n+\n+ case TIMER_INT_COMP_2:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2));\n+ } else {\n+ /* Disable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2));\n+ }\n+\n+ break;\n+\n+ case TIMER_INT_ALL:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0));\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1));\n+ BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2));\n+ } else {\n+ /* Disable this interrupt */\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0));\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1));\n+ BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2));\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set gpio polarity\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerCh: TIMER channel type\n+ * @param polarity: TIMER GPIO polarity\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_INV, polarity);\n+ } else {\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_GPIO_INV, polarity);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER channel 0 enable or disable measure gpio pulse width function\n+ *\n+ * @param timerId: Timer ID type\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_EN, enable);\n+ BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER channel 0 get gpio pulse width value function\n+ *\n+ * @param timerId: Timer ID type\n+ *\n+ * @return Pulse width\n+ *\n+*******************************************************************************/\n+uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+\n+ do {\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO);\n+ } while (!BL_IS_REG_BIT_SET(tmpVal, TIMER_GPIO_LAT_OK));\n+\n+ return (BL_RD_REG(TIMERx, TIMER_GPIO_LAT2) - BL_RD_REG(TIMERx, TIMER_GPIO_LAT1));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER force clock division\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerChan: TIMER channel type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[timerId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan));\n+\n+ /* write 0 after write 1 to force clock division */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR2_FORCE);\n+ } else {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR3_FORCE);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE);\n+\n+ if (timerCh == TIMER_CH0) {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR2_FORCE);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR3_FORCE);\n+ }\n+\n+ BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER install interrupt callback\n+ *\n+ * @param timerId: Timer ID type\n+ * @param timerChan: TIMER channel type\n+ * @param intType: TIMER interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_TIMER_ID_TYPE(timerId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan));\n+ CHECK_PARAM(IS_TIMER_INT_TYPE(intType));\n+\n+ timerIntCbfArra[timerId][timerChan][intType] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set watchdog clock source and clock division\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param clkSrc: Watchdog timer clock source type\n+ * @param div: Watchdog timer clock division value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+ CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc));\n+\n+ /* Configure watchdog timer clock source */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc);\n+ BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal);\n+\n+ /* Configure watchdog timer clock divison */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div);\n+ BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get watchdog match compare value\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return Watchdog match comapre register value\n+ *\n+*******************************************************************************/\n+uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ /* Get watchdog timer match register value */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMR);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_WMR);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER set watchdog match compare value\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param val: Watchdog match compare value\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ /* Set watchdog timer match register value */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WMR, val);\n+ BL_WR_REG(TIMERx, TIMER_WMR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog enable or disable compare value effect immediately after update\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param enable: Enable or disable\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_ALIGN, 1 - enable);\n+ BL_WR_REG(TIMERx, TIMER_WMR, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get watchdog count register value\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return Watchdog count register value\n+ *\n+*******************************************************************************/\n+uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ /* Get watchdog timer count register value */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WVR);\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER reset watchdog count register value\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_ResetCounterValue(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ /* Reset watchdog timer count register value */\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WCR);\n+\n+ /* Set watchdog counter reset register bit0 to 1 */\n+ BL_WR_REG(TIMERx, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER get watchdog reset status\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ /* Get watchdog status register */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WSR);\n+\n+ return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER clear watchdog reset status\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_ClearResetStatus(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WSR);\n+\n+ /* Set watchdog status register */\n+ BL_WR_REG(TIMERx, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER enable watchdog function\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_Enable(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(TIMER0_WDT_IRQn, TIMER0_WDT_IRQHandler);\n+ Interrupt_Handler_Register(TIMER1_WDT_IRQn, TIMER1_WDT_IRQHandler);\n+#endif\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMER);\n+\n+ BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog timer disable function\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_Disable(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMER);\n+\n+ BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog timer disable function\n+ *\n+ * @param wdtId: Watchdog ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_ForceClockDivision(WDT_ID_Type wdtId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+\n+ /* write 0 after write 1 to force clock division */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE);\n+\n+ tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_WCDR_FORCE);\n+\n+ BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE);\n+\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_WCDR_FORCE);\n+\n+ BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog timer mask or unmask certain or all interrupt\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param intType: Watchdog interrupt type\n+ * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+ CHECK_PARAM(IS_WDT_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ WDT_ENABLE_ACCESS(TIMERx);\n+\n+ /* Deal with watchdog match/interrupt enable register,\n+\t WRIE:watchdog reset/interrupt enable */\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_WMER);\n+\n+ switch (intType) {\n+ case WDT_INT:\n+ if (intMask == UNMASK) {\n+ /* Enable this interrupt */\n+ /* 0 means generates a watchdog interrupt,\n+\t\t\t\t a watchdog timer reset is not generated*/\n+ BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE));\n+ } else {\n+ /* Disable this interrupt */\n+ /* 1 means generates a watchdog timer reset,\n+\t\t\t\t a watchdog interrupt is not generated*/\n+ BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE));\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog install interrupt callback\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param wdtInt: Watchdog interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+ CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt));\n+\n+ wdtIntCbfArra[wdtId][wdtInt] = cbFun;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Watchdog set gpio polarity\n+ *\n+ * @param wdtId: Watchdog ID type\n+ * @param polarity: Watchdog GPIO polarity\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity)\n+{\n+ uint32_t tmpVal;\n+ uint32_t TIMERx = timerAddr[wdtId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_WDT_ID_TYPE(wdtId));\n+ CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));\n+\n+ tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_GPIO_INV, polarity);\n+ BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER0 channel 0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER0_CH0_IRQHandler(void)\n+{\n+ TIMER_IntHandler(TIMER0_ID, TIMER_CH0);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER0 channel 1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER0_CH1_IRQHandler(void)\n+{\n+ TIMER_IntHandler(TIMER0_ID, TIMER_CH1);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER0 watchdog interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER0_WDT_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ WDT_ENABLE_ACCESS(TIMER0_BASE);\n+\n+ tmpVal = BL_RD_REG(TIMER0_BASE, TIMER_WICR);\n+ BL_WR_REG(TIMER0_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR));\n+\n+ if (wdtIntCbfArra[WDT0_ID][WDT_INT] != NULL) {\n+ /* Call the callback function */\n+ wdtIntCbfArra[WDT0_ID][WDT_INT]();\n+ }\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER1 channel 0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER1_CH0_IRQHandler(void)\n+{\n+ TIMER_IntHandler(TIMER1_ID, TIMER_CH0);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER1 channel 1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER1_CH1_IRQHandler(void)\n+{\n+ TIMER_IntHandler(TIMER1_ID, TIMER_CH1);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief TIMER1 watchdog interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void TIMER1_WDT_IRQHandler(void)\n+{\n+ uint32_t tmpVal;\n+\n+ WDT_ENABLE_ACCESS(TIMER1_BASE);\n+\n+ tmpVal = BL_RD_REG(TIMER1_BASE, TIMER_WICR);\n+ BL_WR_REG(TIMER1_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR));\n+\n+ if (wdtIntCbfArra[WDT1_ID][WDT_INT] != NULL) {\n+ /* Call the callback function */\n+ wdtIntCbfArra[WDT1_ID][WDT_INT]();\n+ }\n+}\n+#endif\n+/*@} end of group TIMER_Private_Functions */\n+\n+/*@} end of group TIMER */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2cea9f2e57e4c24faa9e86e919cfcd6c1405f301\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c\n@@ -0,0 +1,906 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_touch.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_touch.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TOUCH\n+ * @{\n+ */\n+\n+/** @defgroup TOUCH_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Private_Macros */\n+\n+/** @defgroup TOUCH_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Private_Types */\n+\n+/** @defgroup TOUCH_Private_Variables\n+ * @{\n+ */\n+static intCallback_Type *touchIntCbfArra[TOUCH_INT_INTERRUPT + 1][TOUCH_CHANNEL_11 + 1] = { { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL } };\n+\n+/*@} end of group TOUCH_Private_Variables */\n+\n+/** @defgroup TOUCH_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Global_Variables */\n+\n+/** @defgroup TOUCH_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Private_Fun_Declaration */\n+\n+/** @defgroup TOUCH_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group TOUCH_Private_Functions */\n+\n+/** @defgroup TOUCH_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief touch moudle init\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCfg: touch moudle config\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CLK_SEL_TYPE(tCfg->clkSel));\n+ CHECK_PARAM(IS_TOUCH_CLK_DIV_TYPE(tCfg->clkDiv));\n+ CHECK_PARAM(IS_TOUCH_POWER_SEL_TYPE(tCfg->powerSel));\n+ CHECK_PARAM(IS_TOUCH_WORK_MODE_TYPE(tCfg->workMode));\n+ CHECK_PARAM(IS_TOUCH_RUN_MODE_TYPE(tCfg->runMode));\n+ CHECK_PARAM((tCfg->sleepTime <= 0x7FFFFF));\n+ CHECK_PARAM(IS_TOUCH_PCHARGE_LOW_TYPE(tCfg->pchargeLow));\n+ CHECK_PARAM(IS_TOUCH_PCHARGE_HIGH_TYPE(tCfg->pchargeHigh));\n+ CHECK_PARAM(IS_TOUCH_LDO_VOLTAGE_TYPE(tCfg->ldoVol));\n+ CHECK_PARAM(IS_TOUCH_VREF_VOLTAGE_TYPE(tCfg->vrefVol));\n+ CHECK_PARAM(IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(tCfg->hystersisVol));\n+ CHECK_PARAM(IS_TOUCH_COMPENSATION_CAP_TYPE(tCfg->compensationCap));\n+ CHECK_PARAM(IS_TOUCH_FILTER_ORDER_CTRL_TYPE(tCfg->filterCtrl));\n+ CHECK_PARAM(IS_TOUCH_LTA_ORDER_CTRL_TYPE(tCfg->ltaCtrl));\n+ CHECK_PARAM((tCfg->dataHysCtrl <= 0x1FF));\n+\n+ /* touch1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1);\n+\n+ if (tCfg->powerSel == TOUCH_POWER_SEL_AON) {\n+ /* power from AON bandgap */\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL);\n+ } else {\n+ /* power from internal bandgap */\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL);\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_ULP_EN, tCfg->ulpEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CYCLE_EN, tCfg->cycleEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CONT_EN, tCfg->runMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_LOW, tCfg->pchargeLow);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_HIGH, tCfg->pchargeHigh);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_DIV_RATIO, tCfg->clkDiv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_SEL, tCfg->clkSel);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_COMP_HYS_SEL, tCfg->hystersisVol);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_SEL, tCfg->ldoVol);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VREF_SEL, tCfg->vrefVol);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal);\n+\n+ /* touch3 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_CCSEL, tCfg->compensationCap);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SELF_MUTUAL_SEL, tCfg->workMode);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_ORDER, tCfg->filterCtrl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_EN, tCfg->filterEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_ORDER, tCfg->ltaCtrl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_EN, tCfg->ltaEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS_EN, tCfg->dataHystersisEn);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_CAL_EN, tCfg->calibrationEn);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH3, tmpVal);\n+\n+ /* touch_sleep_time */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SLEEP_CYCLE, tCfg->sleepTime);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME, tmpVal);\n+\n+ /* touch_data_hystersis */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS, tCfg->dataHysCtrl);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch moudle channel init\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tChCfg: touch moudle channel config\n+ * @param tChSel: touch moudle channel select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch0));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch1));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch2));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch3));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch4));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch5));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch6));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch7));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch8));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch9));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch10));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch11));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tChSel));\n+\n+ /* touch2 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL11_HIGHZ_EN, tChCfg->ch11);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL10_HIGHZ_EN, tChCfg->ch10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL9_HIGHZ_EN, tChCfg->ch9);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL8_HIGHZ_EN, tChCfg->ch8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL7_HIGHZ_EN, tChCfg->ch7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL6_HIGHZ_EN, tChCfg->ch6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL5_HIGHZ_EN, tChCfg->ch5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL4_HIGHZ_EN, tChCfg->ch4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL3_HIGHZ_EN, tChCfg->ch3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL2_HIGHZ_EN, tChCfg->ch2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL1_HIGHZ_EN, tChCfg->ch1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL0_HIGHZ_EN, tChCfg->ch0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_SEL, tChSel);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH2, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch moudle start\n+ *\n+ * @param touchId: touch moudle ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+\n+ /* touch1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_TOUCH);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch moudle stop\n+ *\n+ * @param touchId: touch moudle ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+\n+ /* touch1 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_TOUCH);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch moudle set V threshold value\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCh: touch moudle channel\n+ * @param value: vth value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ if (tCh <= TOUCH_CHANNEL_3) {\n+ /* channel 0 - channel 3 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_0:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3, value);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0, tmpVal);\n+ } else if (tCh <= TOUCH_CHANNEL_7) {\n+ /* channel 4 - channel 7 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_4:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_5:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_6:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_7:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7, value);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1, tmpVal);\n+ } else {\n+ /* channel 8 - channel 11 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_8:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_9:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_10:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10, value);\n+ break;\n+\n+ case TOUCH_CHANNEL_11:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11, value);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2, tmpVal);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch moudle vth data\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return vth data\n+ *\n+*******************************************************************************/\n+uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ if (tCh <= TOUCH_CHANNEL_3) {\n+ /* channel 0 - channel 3 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_0:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0);\n+ break;\n+\n+ case TOUCH_CHANNEL_1:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1);\n+ break;\n+\n+ case TOUCH_CHANNEL_2:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2);\n+ break;\n+\n+ case TOUCH_CHANNEL_3:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ } else if (tCh <= TOUCH_CHANNEL_7) {\n+ /* channel 4 - channel 7 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_4:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4);\n+ break;\n+\n+ case TOUCH_CHANNEL_5:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5);\n+ break;\n+\n+ case TOUCH_CHANNEL_6:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6);\n+ break;\n+\n+ case TOUCH_CHANNEL_7:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ } else {\n+ /* channel 8 - channel 11 */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2);\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_8:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8);\n+ break;\n+\n+ case TOUCH_CHANNEL_9:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9);\n+ break;\n+\n+ case TOUCH_CHANNEL_10:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10);\n+ break;\n+\n+ case TOUCH_CHANNEL_11:\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+ }\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch moudle raw data\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return raw data\n+ *\n+*******************************************************************************/\n+uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_0:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_0);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH0);\n+ break;\n+\n+ case TOUCH_CHANNEL_1:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH1);\n+ break;\n+\n+ case TOUCH_CHANNEL_2:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_2);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH2);\n+ break;\n+\n+ case TOUCH_CHANNEL_3:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_3);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH3);\n+ break;\n+\n+ case TOUCH_CHANNEL_4:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_4);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH4);\n+ break;\n+\n+ case TOUCH_CHANNEL_5:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_5);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH5);\n+ break;\n+\n+ case TOUCH_CHANNEL_6:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_6);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH6);\n+ break;\n+\n+ case TOUCH_CHANNEL_7:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_7);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH7);\n+ break;\n+\n+ case TOUCH_CHANNEL_8:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_8);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH8);\n+ break;\n+\n+ case TOUCH_CHANNEL_9:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_9);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH9);\n+ break;\n+\n+ case TOUCH_CHANNEL_10:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_10);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH10);\n+ break;\n+\n+ case TOUCH_CHANNEL_11:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_11);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH11);\n+ break;\n+ }\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch moudle LTA data\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return LTA data\n+ *\n+*******************************************************************************/\n+uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_0:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_0);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH0);\n+ break;\n+\n+ case TOUCH_CHANNEL_1:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH1);\n+ break;\n+\n+ case TOUCH_CHANNEL_2:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_2);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH2);\n+ break;\n+\n+ case TOUCH_CHANNEL_3:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_3);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH3);\n+ break;\n+\n+ case TOUCH_CHANNEL_4:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_4);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH4);\n+ break;\n+\n+ case TOUCH_CHANNEL_5:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_5);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH5);\n+ break;\n+\n+ case TOUCH_CHANNEL_6:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_6);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH6);\n+ break;\n+\n+ case TOUCH_CHANNEL_7:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_7);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH7);\n+ break;\n+\n+ case TOUCH_CHANNEL_8:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_8);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH8);\n+ break;\n+\n+ case TOUCH_CHANNEL_9:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_9);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH9);\n+ break;\n+\n+ case TOUCH_CHANNEL_10:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_10);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH10);\n+ break;\n+\n+ case TOUCH_CHANNEL_11:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_11);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH11);\n+ break;\n+ }\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch moudle FLT data\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return FLT data\n+ *\n+*******************************************************************************/\n+uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ switch (tCh) {\n+ case TOUCH_CHANNEL_0:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_0);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH0);\n+ break;\n+\n+ case TOUCH_CHANNEL_1:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_1);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH1);\n+ break;\n+\n+ case TOUCH_CHANNEL_2:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_2);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH2);\n+ break;\n+\n+ case TOUCH_CHANNEL_3:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_3);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH3);\n+ break;\n+\n+ case TOUCH_CHANNEL_4:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_4);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH4);\n+ break;\n+\n+ case TOUCH_CHANNEL_5:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_5);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH5);\n+ break;\n+\n+ case TOUCH_CHANNEL_6:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_6);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH6);\n+ break;\n+\n+ case TOUCH_CHANNEL_7:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_7);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH7);\n+ break;\n+\n+ case TOUCH_CHANNEL_8:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_8);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH8);\n+ break;\n+\n+ case TOUCH_CHANNEL_9:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_9);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH9);\n+ break;\n+\n+ case TOUCH_CHANNEL_10:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_10);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH10);\n+ break;\n+\n+ case TOUCH_CHANNEL_11:\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_11);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH11);\n+ break;\n+ }\n+\n+ return tmpVal;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch end flag\n+ *\n+ * @param touchId: touch moudle ID\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId)\n+{\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS), PDS_TOUCH_END_FLAG) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch interrupt enable\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_INT_EN);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch interrupt disable\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_INT_EN);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch interrupt mask or not\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ * @param tCh: touch moudle channel\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpMask = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ TOUCH_IntEnable(touchId, intType);\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING);\n+\n+ if (intMask == MASK) {\n+ tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK);\n+ tmpMask |= (1 << tCh);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask);\n+ } else {\n+ tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK);\n+ tmpMask &= (~(1 << tCh));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask);\n+ }\n+\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get touch interrupt status\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_STATUS);\n+\n+ if (tmpVal & (1 << tCh)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear touch interrupt status\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ * @param tCh: touch moudle channel\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpClr = 0;\n+\n+ CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId));\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+ CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh));\n+\n+ /* set */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING);\n+ tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR);\n+ tmpClr |= (1 << tCh);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal);\n+\n+ /* unset */\n+ tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING);\n+ tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR);\n+ tmpClr &= (~(1 << tCh));\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr);\n+ tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief install touch interrupt callback\n+ *\n+ * @param touchId: touch moudle ID\n+ * @param intType: touch moudle interrupt type\n+ * @param tCh: touch moudle channel\n+ * @param cbFun: callback function\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, intCallback_Type *cbFun)\n+{\n+ CHECK_PARAM(IS_TOUCH_INT_TYPE(intType));\n+\n+ touchIntCbfArra[intType][tCh] = cbFun;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief touch IRQ handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void TOUCH_IRQHandler(void)\n+{\n+ TOUCH_CHANNEL_Type tmpCh;\n+\n+ for (tmpCh = TOUCH_CHANNEL_0; tmpCh <= TOUCH_CHANNEL_11; tmpCh++) {\n+ if (SET == TOUCH_GetIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh)) {\n+ TOUCH_ClrIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh);\n+\n+ if (touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh] != NULL) {\n+ touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh]();\n+ }\n+ }\n+ }\n+}\n+\n+/*@} end of group TOUCH_Public_Functions */\n+\n+/*@} end of group TOUCH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8cdafef270866ca83186f1fb3e2702e5ed1b2dc0\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c\n@@ -0,0 +1,898 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_tzc_sec.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_tzc_sec.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup TZC_ENG\n+ * @{\n+ */\n+\n+/** @defgroup TZC_ENG_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Private_Macros */\n+\n+/** @defgroup TZC_ENG_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Private_Types */\n+\n+/** @defgroup TZC_ENG_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Private_Variables */\n+\n+/** @defgroup TZC_ENG_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Global_Variables */\n+\n+/** @defgroup TZC_ENG_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Private_Fun_Declaration */\n+\n+/** @defgroup TZC_ENG_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group TZC_ENG_Private_Functions */\n+\n+/** @defgroup TZC_ENG_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief None\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Set_Sboot_Done(void)\n+{\n+ uint32_t tmpVal;\n+ /* Set Sboot done */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);\n+}\n+\n+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ if (masterType < TZC_SEC_MASTER_D0) {\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);\n+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);\n+\n+ if (group == 0) {\n+ tmpVal &= (~(1 << masterType));\n+ } else {\n+ tmpVal |= (1 << masterType);\n+ }\n+ tmpVal |= (1 << (masterType + 16));\n+ tmpVal2 |= (1 << masterType);\n+\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);\n+ } else {\n+ masterType -= TZC_SEC_MASTER_D0;\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);\n+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);\n+\n+ if (group == 0) {\n+ tmpVal &= (~(1 << masterType));\n+ } else {\n+ tmpVal |= (1 << masterType);\n+ }\n+ tmpVal |= (1 << (masterType + 16));\n+ tmpVal2 |= (1 << masterType);\n+\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);\n+ }\n+}\n+\n+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SLAVE_MAX) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ if (slaveType >= TZC_SEC_SLAVE_MM) {\n+ slaveType -= TZC_SEC_SLAVE_MM;\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ /* set lock*/\n+ tmpVal |= (1 << (slaveType + 16));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0, tmpVal);\n+ } else if (slaveType < TZC_SEC_SLAVE_EMI_MISC) {\n+ slaveType -= TZC_SEC_SLAVE_GLB;\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);\n+ /* set lock */\n+ tmpVal |= (1 << slaveType);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);\n+ } else {\n+ slaveType -= TZC_SEC_SLAVE_EMI_MISC;\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);\n+ /* set lock */\n+ tmpVal |= (1 << (slaveType + TZC_SEC_SLAVE_EMI_MISC));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);\n+ }\n+}\n+\n+void Tzc_Sec_Set_MM_Slave_Group(TZC_SEC_MM_Slave_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_MM_SLAVE_MAX) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ if (slaveType < TZC_SEC_MM_SLAVE_DSP2_MISC) {\n+ /* set group */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0);\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0, tmpVal);\n+\n+ /* set lock */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0);\n+ tmpVal |= (1 << slaveType);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0, tmpVal);\n+\n+ } else if (slaveType < TZC_SEC_MM_SLAVE_CODEC_MISC) {\n+ slaveType -= TZC_SEC_MM_SLAVE_DSP2_MISC;\n+\n+ /* set group */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1);\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1, tmpVal);\n+\n+ /* set lock */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);\n+ tmpVal |= (1 << (slaveType + 16));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);\n+ } else {\n+ slaveType -= TZC_SEC_MM_SLAVE_CODEC_MISC;\n+\n+ /* set group */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2);\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2, tmpVal);\n+\n+ /* set lock */\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);\n+ tmpVal |= (1 << slaveType);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);\n+ }\n+}\n+\n+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (slaveType >= TZC_SEC_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2);\n+ /* set lock */\n+ tmpVal |= (1 << slaveType);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2, tmpVal);\n+}\n+\n+void Tzc_Sec_Set_MM_Glb_Ctrl_Group(TZC_SEC_MM_GLB_Ctrl_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (slaveType >= TZC_SEC_MM_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2);\n+ /* set lock */\n+ tmpVal |= (1 << slaveType);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2, tmpVal);\n+}\n+\n+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+ uint32_t tmpVal2;\n+\n+ if (cpu == GLB_CORE_ID_M0) {\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);\n+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_CPU_TZMID, group);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_CPU_TZMID_LOCK, 1);\n+\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);\n+ } else if (cpu == GLB_CORE_ID_D0) {\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);\n+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_MMCPU_TZMID, group);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_MMCPU_TZMID, 1);\n+\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);\n+\n+ } else if (cpu == GLB_CORE_ID_LP) {\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);\n+ tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_PICO_TZMID, group);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_PICO_TZMID_LOCK, 1);\n+\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set ROM region access configuration\n+ *\n+ * @param region: ROM region index 0-2\n+ * @param startAddr: ROM region start address\n+ * @param length: ROM region length\n+ * @param group: ROM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set OCRAM region access configuration\n+ *\n+ * @param region: OCRAM region index 0-2\n+ * @param startAddr: OCRAM region start address\n+ * @param length: OCRAM region length\n+ * @param group: OCRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3) {\n+ return;\n+ }\n+ group = group & 0xf;\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);\n+ tmpVal &= (~(0xf << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_OCRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 20);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set OCRAM regionx access configuration\n+ *\n+ * @param group: OCRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t region = 3;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 20);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set WRAM region access configuration\n+ *\n+ * @param region: WRAM region index 0-2\n+ * @param startAddr: WRAM region start address\n+ * @param length: WRAM region length\n+ * @param group: WRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3) {\n+ return;\n+ }\n+ group = group & 0xf;\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);\n+ tmpVal &= (~(0xf << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_WRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 20);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set WRAM regionx access configuration\n+ *\n+ * @param group: WRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t region = 3;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 20);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set Flash region access configuration\n+ *\n+ * @param region: Flash region index 0-2\n+ * @param startAddr: Flash region start address\n+ * @param length: Flash region length\n+ * @param group: Flash region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal2 = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 4 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 0xf & (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);\n+ tmpVal &= (~(0xf << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);\n+\n+ /* Set range */\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* Set range MSB */\n+ tmpVal = BL_RD_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET);\n+ tmpVal = tmpVal & (0xff << (8 * region));\n+ tmpVal2 = ((alignEnd >> 26) & 0x7) | (((startAddr >> 26) & 0x7) << 3);\n+ tmpVal2 = tmpVal2 << (8 * region);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET, tmpVal | tmpVal2);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 20);\n+ tmpVal |= 1 << (region + 25);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set Flash regionx access configuration\n+ *\n+ * @param group: Flash region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint8_t region = 4;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 4)));\n+ tmpVal |= (group << (region * 4));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 20);\n+ tmpVal |= 1 << (region + 25);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set L2SRAM region access configuration\n+ *\n+ * @param region: L2SRAM region index 0-2\n+ * @param startAddr: L2SRAM region start address\n+ * @param length: L2SRAM region length\n+ * @param group: L2SRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_L2SRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set VRAM region access configuration\n+ *\n+ * @param region: VRAM region index 0-2\n+ * @param startAddr: VRAM region start address\n+ * @param length: VRAM region length\n+ * @param group: VRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_VRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set PSRAMA region access configuration\n+ *\n+ * @param region: PSRAMA region index 0-2\n+ * @param startAddr: PSRAMA region start address\n+ * @param length: PSRAMA region length\n+ * @param group: PSRAMA region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);\n+}\n+\n+/**\n+ * @brief TrustZone Security set Release PSRAMA region access\n+ *\n+ */\n+void Tzc_Sec_PSRAMA_Access_Release(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t region = 0;\n+ /* set disable */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);\n+ tmpVal &= (~(1 << (region + 16)));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set PSRAMB region access configuration\n+ *\n+ * @param region: PSRAMB region index 0-2\n+ * @param startAddr: PSRAMB region start address\n+ * @param length: PSRAMB region length\n+ * @param group: PSRAMB region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);\n+}\n+/**\n+ * @brief TrustZone Security set Release PSRAMB region access\n+ *\n+ */\n+void Tzc_Sec_PSRAMB_Access_Release(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t region = 0;\n+ /* set disable */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);\n+ tmpVal &= (~(1 << (region + 16)));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);\n+}\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set XRAM region access configuration\n+ *\n+ * @param region: XRAM region index 0-2\n+ * @param startAddr: XRAM region start address\n+ * @param length: XRAM region length\n+ * @param group: XRAM region auth group type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;\n+\n+ /* check the parameter */\n+ CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));\n+ if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);\n+ tmpVal &= (~(3 << (region * 2)));\n+ tmpVal |= (group << (region * 2));\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);\n+\n+ tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);\n+ BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_XRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);\n+\n+ /* set enable and lock */\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);\n+ tmpVal |= 1 << (region + 16);\n+ tmpVal |= 1 << (region + 24);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set sec_eng module config\n+ *\n+ * @param mode: sec_eng control mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD, mode);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);\n+ /* set lock */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD_LOCK, 1);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set sf_ctrl module config\n+ *\n+ * @param mode: sf_ctrl control mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD, mode);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);\n+ /* set lock */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD_LOCK, 1);\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);\n+}\n+\n+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SE_CTRL_MAX) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);\n+ /* set lock */\n+ tmpVal |= (1 << (slaveType));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);\n+}\n+\n+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group)\n+{\n+ uint32_t tmpVal;\n+\n+ if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SF_CTRL_MAX) {\n+ return;\n+ }\n+ group = 1 << (group);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1);\n+ /* set group */\n+ tmpVal &= (~(3 << (slaveType * 2)));\n+ tmpVal |= (group << (slaveType * 2));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);\n+\n+ tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);\n+ /* set lock */\n+ tmpVal |= (1 << (slaveType + 16));\n+ BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief TrustZone Security set watchdog reset delay value\n+ *\n+ * @param mode: sec_eng control mode\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_WDT_DLY, delayValue);\n+ BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);\n+}\n+\n+/*@} end of group TZC_ENG_Public_Functions */\n+\n+/*@} end of group TZC_ENG */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1b228b6f01e6c6120c915229b8b31e2915b99031\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c\n@@ -0,0 +1,1471 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_uart.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_uart.h\"\n+#include \"bl808_glb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup UART\n+ * @{\n+ */\n+\n+/** @defgroup UART_Private_Macros\n+ * @{\n+ */\n+#define UART_TX_TIMEOUT_COUNT (320 * 1000)\n+\n+/*@} end of group UART_Private_Macros */\n+\n+/** @defgroup UART_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group UART_Private_Types */\n+\n+/** @defgroup UART_Private_Variables\n+ * @{\n+ */\n+static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE };\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = {\n+ { NULL }\n+};\n+#endif\n+\n+/*@} end of group UART_Private_Variables */\n+\n+/** @defgroup UART_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group UART_Global_Variables */\n+\n+/** @defgroup UART_Private_Fun_Declaration\n+ * @{\n+ */\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+static void UART_IntHandler(UART_ID_Type uartId);\n+#endif\n+\n+/*@} end of group UART_Private_Fun_Declaration */\n+\n+/** @defgroup UART_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief UART interrupt common handler function\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+static void UART_IntHandler(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t maskVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_INT_STS);\n+ maskVal = BL_RD_REG(UARTx, UART_INT_MASK);\n+\n+ /* Length of uart tx data transfer arrived interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_END]();\n+ }\n+ }\n+\n+ /* Length of uart rx data transfer arrived interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_END]();\n+ }\n+ }\n+\n+ /* Tx fifo ready interrupt,auto-cleared when data is pushed */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* Rx fifo ready interrupt,auto-cleared when data is popped */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();\n+ }\n+ }\n+\n+ /* Rx time-out interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RTO]();\n+ }\n+ }\n+\n+ /* Rx parity check error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_PCE]();\n+ }\n+ }\n+\n+ /* Tx fifo overflow/underflow error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_TX_FER]();\n+ }\n+ }\n+\n+ /* Rx fifo overflow/underflow error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {\n+ if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_RX_FER]();\n+ }\n+ }\n+\n+ /* Rx lin mode sync field error interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_LSE]();\n+ }\n+ }\n+\n+ /* Rx byte count reached interrupt */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_BCR]();\n+ }\n+ }\n+\n+ /* Rx auto baud rate detection finish interrupt using start bit */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_STARTBIT]();\n+ }\n+ }\n+\n+ /* Rx auto baud rate detection finish interrupt using codeword 0x55 */\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) {\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS);\n+\n+ if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) {\n+ uartIntCbfArra[uartId][UART_INT_0X55]();\n+ }\n+ }\n+}\n+#endif\n+\n+/*@} end of group UART_Private_Functions */\n+\n+/** @defgroup UART_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief UART set baud rate function\n+ *\n+ * @param uartId: UART ID type\n+ * @param baudRate: baudRate need to set\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate)\n+{\n+ uint32_t uartClk= 0;\n+ uint32_t fraction = 0;\n+ uint32_t baudRateDivisor = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Get uart clk */\n+ if (uartId == UART0_ID || uartId == UART1_ID || uartId == UART2_ID) {\n+ uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);\n+ } else if (uartId == UART0_MM_ID) {\n+ uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART3);\n+ } else {\n+ return ERROR;\n+ }\n+\n+ /* Cal the baud rate divisor */\n+ fraction = uartClk * 10 / baudRate % 10;\n+ baudRateDivisor = uartClk / baudRate;\n+\n+ if (fraction >= 5) {\n+ ++baudRateDivisor;\n+ }\n+\n+ /* Set the baud rate register value */\n+ BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART initialization function\n+ *\n+ * @param uartId: UART ID type\n+ * @param uartCfg: UART configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg)\n+{\n+ uint32_t tmpValTxCfg = 0;\n+ uint32_t tmpValRxCfg = 0;\n+ uint32_t fraction = 0;\n+ uint32_t baudRateDivisor = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity));\n+ CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits));\n+ CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits));\n+ CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse));\n+\n+ /* Disable clock gate when use UART2 */\n+ if(uartId == UART2_ID){\n+ GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2);\n+ }\n+\n+ /* Cal the baud rate divisor */\n+ fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10;\n+ baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate;\n+\n+ if (fraction >= 5) {\n+ ++baudRateDivisor;\n+ }\n+\n+ /* Set the baud rate register value */\n+ BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF));\n+\n+ /* Configure parity type */\n+ tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+ tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+\n+ switch (uartCfg->parity) {\n+ case UART_PARITY_NONE:\n+ tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);\n+ tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);\n+ break;\n+\n+ case UART_PARITY_ODD:\n+ tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);\n+ tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);\n+ tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);\n+ tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);\n+ break;\n+\n+ case UART_PARITY_EVEN:\n+ tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);\n+ tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);\n+ tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);\n+ tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ /* Configure data bits */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4));\n+ tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4));\n+\n+ /* Configure tx stop bits */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits);\n+\n+ /* Configure tx cts flow control function */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl);\n+\n+ /* Configure rx input de-glitch function */\n+ tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch);\n+\n+ /* Configure tx lin mode function */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode);\n+\n+ /* Configure rx lin mode function */\n+ tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode);\n+\n+ /* Set tx break bit count for lin protocol */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt);\n+\n+ /* Write back */\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg);\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg);\n+\n+ /* Configure LSB-first or MSB-first */\n+ tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG);\n+\n+ if (UART_MSB_FIRST == uartCfg->byteBitInverse) {\n+ tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);\n+ } else {\n+ tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);\n+ }\n+\n+ BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg);\n+\n+ tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE);\n+ /* Configure rx rts output SW control mode */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl);\n+ /* Configure tx output SW control mode */\n+ tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl);\n+ BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg);\n+\n+#ifndef BFLB_USE_HAL_DRIVER\n+ Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler);\n+ Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler);\n+ Interrupt_Handler_Register(UART2_IRQn, UART2_IRQHandler);\n+ Interrupt_Handler_Register(UART3_IRQn, UART3_IRQHandler);\n+#endif\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set default value of all registers function\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_DeInit(UART_ID_Type uartId)\n+{\n+ switch(uartId){\n+ case UART0_ID:\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART0);\n+ break;\n+ case UART1_ID:\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART1);\n+ break;\n+ case UART2_ID:\n+ GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART2);\n+ break;\n+ case UART0_MM_ID:\n+ GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_UART0);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART configure fifo function\n+ *\n+ * @param uartId: UART ID type\n+ * @param fifoCfg: FIFO configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Deal with uart fifo configure register */\n+ tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1);\n+ /* Configure dma tx fifo threshold */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);\n+ /* Configure dma rx fifo threshold */\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);\n+ /* Write back */\n+ BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal);\n+\n+ /* Enable or disable uart fifo dma function */\n+ tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);\n+\n+ if (ENABLE == fifoCfg->txFifoDmaEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);\n+ }\n+\n+ if (ENABLE == fifoCfg->rxFifoDmaEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);\n+ }\n+\n+ BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART configure infra function\n+ *\n+ * @param uartId: UART ID type\n+ * @param irCfg: IR configuration structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Configure tx ir mode */\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+\n+ if (ENABLE == irCfg->txIrEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);\n+ }\n+\n+ if (ENABLE == irCfg->txIrInverse) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);\n+ }\n+\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal);\n+\n+ /* Configure rx ir mode */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+\n+ if (ENABLE == irCfg->rxIrEnable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN);\n+ }\n+\n+ if (ENABLE == irCfg->rxIrInverse) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV);\n+ }\n+\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);\n+\n+ /* Configure tx ir pulse start and stop position */\n+ BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart);\n+\n+ /* Configure rx ir pulse start position */\n+ BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Enable UART\n+ *\n+ * @param uartId: UART ID type\n+ * @param direct: UART direction type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));\n+\n+ if (direct == UART_TX || direct == UART_TXRX) {\n+ /* Enable UART tx unit */\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN));\n+ }\n+\n+ if (direct == UART_RX || direct == UART_TXRX) {\n+ /* Enable UART rx unit */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Disable UART\n+ *\n+ * @param uartId: UART ID type\n+ * @param direct: UART direction type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));\n+\n+ if (direct == UART_TX || direct == UART_TXRX) {\n+ /* Disable UART tx unit */\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN));\n+ }\n+\n+ if (direct == UART_RX || direct == UART_TXRX) {\n+ /* Disable UART rx unit */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is\n+ * reached\n+ *\n+ * @param uartId: UART ID type\n+ * @param length: Length of data (unit:character/byte)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Set length */\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is\n+ * reached\n+ *\n+ * @param uartId: UART ID type\n+ * @param length: Length of data (unit:character/byte)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Set length */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set rx time-out value for triggering RTO interrupt\n+ *\n+ * @param uartId: UART ID type\n+ * @param time: Time-out value (unit:bit time)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Set time-out value */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1);\n+ BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set byte count value for bcr interrupt\n+ *\n+ * @param uartId: UART ID type\n+ * @param count: Byte count\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Set count value */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_BCR_VALUE, count);\n+ BL_WR_REG(UARTx, UART_URX_BCR_INT_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set de-glitch function cycle count value\n+ *\n+ * @param uartId: UART ID type\n+ * @param deglitchCnt: De-glitch function cycle count\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Set count value */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt);\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set tx and rx baudrate according to auto baudrate detection value\n+ *\n+ * @param uartId: UART ID type\n+ * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint16_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Get detection value */\n+ tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet);\n+\n+ /* Set tx baudrate */\n+ BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set rx rts output software control value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Rts set 1*/\n+ tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);\n+ BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART clear rx rts output software control value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Rts clear 0 */\n+ tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);\n+ BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set tx output software control value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetTxValue(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Tx set 1*/\n+ tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);\n+ BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART clear tx output software control value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t tmpVal;\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Rts clear 0 */\n+ tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);\n+ BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART configure tx free run mode function\n+ *\n+ * @param uartId: UART ID type\n+ * @param txFreeRun: Enable or disable tx free run mode\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Enable or disable tx free run mode */\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);\n+\n+ if (ENABLE == txFreeRun) {\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));\n+ } else {\n+ BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART configure auto baud rate detection function\n+ *\n+ * @param uartId: UART ID type\n+ * @param autoBaud: Enable or disable auto function\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Enable or disable auto baud rate detection function */\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);\n+\n+ if (ENABLE == autoBaud) {\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));\n+ } else {\n+ BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART auto baud rate detection pulse width allowable error for using codeword 0x55\n+ *\n+ * @param uartId: UART ID type\n+ * @param allowableError: Pulse width allowable error\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_URX_ABR_PW_TOL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_ABR_PW_TOL, allowableError);\n+ BL_WR_REG(UARTx, UART_URX_ABR_PW_TOL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART get bit width of auto baud rate detection for using codeword 0x55\n+ *\n+ * @param uartId: UART ID type\n+ * @param width: Buffer to save bit width, length:8\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width)\n+{\n+ uint32_t i;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ for (i = 0; i < 4; i++) {\n+ width[2 * i] = (uint16_t)BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i);\n+ width[2 * i + 1] = (uint16_t)(BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i) >> 16);\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART set RS-485 trans ceiver mode\n+ *\n+ * @param uartId: UART ID type\n+ * @param enable: Enable or disable RS-485 mode\n+ * @param polarity: Set DE polarity, active-low or active-high\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_UTX_RS485_CFG);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_EN, enable);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_POL, polarity);\n+ BL_WR_REG(UARTx, UART_UTX_RS485_CFG, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART tx fifo clear\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Clear tx fifo */\n+ tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);\n+ BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART rx fifo clear\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Clear rx fifo */\n+ tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);\n+ BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART mask or unmask certain or all interrupt\n+ *\n+ * @param uartId: UART ID type\n+ * @param intType: UART interrupt type\n+ * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_INT_TYPE(intType));\n+ CHECK_PARAM(IS_BL_MASK_TYPE(intMask));\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_INT_MASK);\n+\n+ /* Mask or unmask certain or all interrupt */\n+ if (UART_INT_ALL == intType) {\n+ if (MASK == intMask) {\n+ tmpVal |= 0xfff;\n+ } else {\n+ tmpVal &= 0;\n+ }\n+ } else {\n+ if (MASK == intMask) {\n+ tmpVal |= 1 << intType;\n+ } else {\n+ tmpVal &= ~(1 << intType);\n+ }\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(UARTx, UART_INT_MASK, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART clear certain or all interrupt\n+ *\n+ * @param uartId: UART ID type\n+ * @param intType: UART interrupt type\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR);\n+\n+ /* Clear certain or all interrupt */\n+ if (UART_INT_ALL == intType) {\n+ tmpVal |= 0xfff;\n+ } else {\n+ tmpVal |= 1 << intType;\n+ }\n+\n+ /* Write back */\n+ BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Install uart interrupt callback function\n+ *\n+ * @param uartId: UART ID type\n+ * @param intType: UART interrupt type\n+ * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun)\n+{\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_INT_TYPE(intType));\n+\n+ uartIntCbfArra[uartId][intType] = cbFun;\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief UART send data to tx fifo\n+ *\n+ * @param uartId: UART ID type\n+ * @param data: The data to be send\n+ * @param len: The length of the send buffer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len)\n+{\n+ uint32_t txLen = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Send data */\n+ while (txLen < len) {\n+ if (UART_GetTxFifoCount(uartId) > 0) {\n+ BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);\n+ timeoutCnt = UART_TX_TIMEOUT_COUNT;\n+ } else {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART send data to tx fifo in block mode\n+ *\n+ * @param uartId: UART ID type\n+ * @param data: The data to be send\n+ * @param len: The length of the send buffer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len)\n+{\n+ uint32_t txLen = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+ uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Send data */\n+ while (txLen < len) {\n+ if (UART_GetTxFifoCount(uartId) > 0) {\n+ BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);\n+ timeoutCnt = UART_TX_TIMEOUT_COUNT;\n+ } else {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+ }\n+\n+ timeoutCnt = UART_TX_TIMEOUT_COUNT;\n+\n+ while (UART_GetTxBusBusyStatus(uartId) == SET) {\n+ timeoutCnt--;\n+\n+ if (timeoutCnt == 0) {\n+ return TIMEOUT;\n+ }\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART receive data from rx fifo\n+ *\n+ * @param uartId: UART ID type\n+ * @param data: The receive data buffer\n+ * @param maxLen: The max length of the buffer\n+ *\n+ * @return The length of the received buffer\n+ *\n+*******************************************************************************/\n+uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen)\n+{\n+ uint32_t rxLen = 0;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Receive data */\n+ while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) {\n+ data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET);\n+ }\n+\n+ return rxLen;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART get auto baud count value\n+ *\n+ * @param uartId: UART ID type\n+ * @param autoBaudDet: Detection using codeword 0x55 or start bit\n+ *\n+ * @return Bit period of auto baudrate detection\n+ *\n+*******************************************************************************/\n+uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet));\n+\n+ /* Select 0x55 or start bit detection value */\n+ if (UART_AUTOBAUD_0X55 == autoBaudDet) {\n+ return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff;\n+ } else {\n+ return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART get rx current byte count value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return Rx byte count value\n+ *\n+*******************************************************************************/\n+uint16_t UART_GetRxByteCount(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG), UART_STS_URX_BCR_COUNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART get tx fifo unoccupied count value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return Tx fifo unoccupied count value\n+ *\n+*******************************************************************************/\n+uint8_t UART_GetTxFifoCount(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART get rx fifo occupied count value\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return Rx fifo occupied count value\n+ *\n+*******************************************************************************/\n+uint8_t UART_GetRxFifoCount(UART_ID_Type uartId)\n+{\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameter */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get uart interrupt status\n+ *\n+ * @param uartId: UART ID type\n+ * @param intType: UART interrupt type\n+ *\n+ * @return Status of interrupt\n+ *\n+*******************************************************************************/\n+BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_INT_TYPE(intType));\n+\n+ /* Get certain or all interrupt status */\n+ tmpVal = BL_RD_REG(UARTx, UART_INT_STS);\n+\n+ if (UART_INT_ALL == intType) {\n+ if ((tmpVal & 0xfff) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ } else {\n+ if ((tmpVal & (1U << intType)) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get indicator of uart tx bus busy\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return Status of tx bus\n+ *\n+*******************************************************************************/\n+BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Get tx bus busy status */\n+ tmpVal = BL_RD_REG(UARTx, UART_STATUS);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get indicator of uart rx bus busy\n+ *\n+ * @param uartId: UART ID type\n+ *\n+ * @return Status of rx bus\n+ *\n+*******************************************************************************/\n+BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+\n+ /* Get rx bus busy status */\n+ tmpVal = BL_RD_REG(UARTx, UART_STATUS);\n+\n+ if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get tx/rx fifo overflow or underflow status\n+ *\n+ * @param uartId: UART ID type\n+ * @param overflow: Select tx/rx overflow or underflow\n+ *\n+ * @return Status of tx/rx fifo\n+ *\n+*******************************************************************************/\n+BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow)\n+{\n+ uint32_t tmpVal;\n+ uint32_t UARTx = uartAddr[uartId];\n+\n+ /* Check the parameters */\n+ CHECK_PARAM(IS_UART_ID_TYPE(uartId));\n+ CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow));\n+\n+ /* Get tx/rx fifo overflow or underflow status */\n+ tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);\n+\n+ if ((tmpVal & (1U << (overflow + 4))) != 0) {\n+ return SET;\n+ } else {\n+ return RESET;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief UART0 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+void UART0_IRQHandler(void)\n+{\n+ UART_IntHandler(UART0_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief UART1 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)\n+void UART1_IRQHandler(void)\n+{\n+ UART_IntHandler(UART1_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief UART2 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void UART2_IRQHandler(void)\n+{\n+ UART_IntHandler(UART2_ID);\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief UART3 interrupt handler\n+ *\n+ * @param None\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_HAL_DRIVER\n+void UART3_IRQHandler(void)\n+{\n+ UART_IntHandler(UART0_MM_ID);\n+}\n+#endif\n+\n+/*@} end of group UART_Public_Functions */\n+\n+/*@} end of group UART */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3ac0da747e4ce8619d2734b4cc2fd6629c21b540\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c\n@@ -0,0 +1,1500 @@\n+#include \"bl808_uhs_phy.h\"\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <stdint.h>\n+#include \"psram_uhs_reg.h\"\n+#include \"glb_reg.h\"\n+#include \"pds_reg.h\"\n+#include \"bl808_common.h\"\n+#include \"bl808_psram_uhs.h\"\n+#include \"bl808_glb.h\"\n+\n+#define bl808_DBG_RF (0)\n+#if bl808_DBG_RF\n+#define uhs_phy_printf_debug printf // debug mode\n+#define uhs_phy_printf printf \n+#else\n+#define uhs_phy_printf_debug(...)\n+// #define uhs_phy_printf printf // commit it out in release version\n+#define uhs_phy_printf(...) // useed in release version\n+#endif\n+\n+uint8_t uhs_latency_code = 1;\n+int32_t dqs_dq_delta = 0;\n+uint32_t dcache_original = 0;\n+uint32_t dcache_current = 0;\n+uint32_t dcache_end = 0;\n+\n+\n+void uhs_phy_delay_us(uint32_t us)\n+{\n+ arch_delay_us(us);\n+}\n+\n+void power_up_mm(void)\n+{\n+ // power up MM domain\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,0x0);\n+ BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); \n+}\n+\n+void power_up_uhspll(void)\n+{\n+ // power_up_uhspll\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); \n+}\n+\n+void power_up_ldo12uhs(void)\n+{\n+ // use internal LDO \n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5);\n+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);\n+ uhs_phy_delay_us(1);\n+ // use external LDO\n+ // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1);\n+ // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);\n+ // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);\n+}\n+\n+void set_cen_ck_ckn(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);\n+ uhs_phy_delay_us(1);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);\n+ uhs_phy_delay_us(1);\n+}\n+\n+void set_or_uhs(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0); \n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0); \n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);\n+ uhs_phy_delay_us(300);\n+}\n+\n+void switch_to_ldo12uhs(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);\n+ uhs_phy_delay_us(150);\n+}\n+\n+void release_cen_ck_ckn(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);\n+ uhs_phy_delay_us(1);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);\n+ uhs_phy_delay_us(1);\n+}\n+\n+void uhs_phy_pwr_down(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0);\n+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);\n+ uhs_phy_delay_us(1);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);\n+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);\n+ uhs_phy_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0);\n+ BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);\n+ uhs_phy_delay_us(1); \n+}\n+\n+void psram_init(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+ uhs_phy_delay_us(1);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); \n+ uhs_phy_delay_us(10); // wait for reg_config_gnt\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+\n+ // psram auto refresh at 2000Mbps\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+\n+ // psram cmd timing < 2000Mbps\n+ BL_WR_WORD(0x3000F030,0x18090610);\n+}\n+\n+void set_uhspll_freq(uint32_t datarate)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t uhspll_sdmin = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SEL_SAMPLE_CLK,0x1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG4,tmpVal);\n+ uhspll_sdmin = (datarate/(40/2))<<11;\n+ if(datarate > 1000)\n+ {\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x0);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal);\n+ }\n+ else if(datarate > 500)\n+ {\n+ uhspll_sdmin = uhspll_sdmin<<1;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal);\n+ }\n+ else\n+ {\n+ uhspll_sdmin = uhspll_sdmin<<2;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x2);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal);\n+ }\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG6);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDMIN,uhspll_sdmin);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG6,tmpVal);\n+ uhs_phy_delay_us(30);\n+\n+ //reset PLL\n+ /* toggle sdm_reset (pulse 0 > 1us) */\n+ /* cfg0 : aupll_sdm_reset */\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 0);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+\n+ /* Step3:reset pll */\n+ /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 0);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+ arch_delay_us(2);\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1);\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);\n+ \n+ uhs_phy_delay_us(30);\n+}\n+\n+void set_uhs_phy_init(void)\n+{\n+ // set phy & controller\n+ uint32_t tmpVal = 0;\n+ // default latency(800MHz)\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); \n+} \n+\n+void set_uhs_phy(void)\n+{\n+ // set phy & controller\n+ // latency code=3 (1066MHz)\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323); // if fail than use 0x0f391323 \n+ // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); //for 400Mbps\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333); \n+} \n+\n+void uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32)\n+{\n+ uint32_t tmpVal = 0;\n+ if(ma == 0)\n+ {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive); \n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);\n+ }\n+ else if(ma == 2)\n+ {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); \n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,BL_32);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);\n+ }\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+ while (1)\n+ {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);\n+ if (tmpVal == 1)\n+ break;\n+ }\n+ \n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);\n+ while (1)\n+ {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE);\n+ if (tmpVal == 1)\n+ break;\n+ }\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+}\n+\n+void uhs_reg_r(uint32_t ma)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpInd = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+\n+ // uhs_phy_delay_us(10);\n+ while (1)\n+ {\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);\n+ if (tmpVal == 1)\n+ break;\n+ }\n+ \n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1); //reg_regw_pulse\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);\n+ // uhs_phy_delay_us(1);\n+ tmpInd = 0;\n+ while (1)\n+ {\n+ tmpInd++;\n+ uhs_phy_delay_us(1);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+ tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE);\n+ if (tmpVal == 1 || tmpInd == 2){\n+ //debug\n+\t\t\tif (tmpInd == 2){\n+ uhs_phy_printf_debug(\"tmpInd = %ld\\r\\n\",tmpInd);\n+ }\n+ break;\n+ } \n+ }\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);\n+}\n+\n+\n+void cfg_dq_rx(uint8_t dq){\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); \n+}\n+\n+void cfg_dqs_rx(uint8_t dqs){\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); \n+}\n+\n+void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);\n+}\n+\n+void uhs_reset(uint32_t datarate)\n+{\n+\tuint32_t tmpVal = 0;\n+\t\n+\ttmpVal = BL_RD_WORD(0x30007044);\n+\ttmpVal = tmpVal | 0x00008000;\n+\tBL_WR_WORD(0x30007044,tmpVal);\n+\tuhs_phy_delay_us(10);\n+\ttmpVal = tmpVal & 0xFFFF7FFF;\n+\tBL_WR_WORD(0x30007044,tmpVal);\n+\t\n+\tBL_WR_WORD(0x3000F030,0x18090610);\n+\t\n+\tPSRAM_UHS_Cfg_Type psramCfg = {\n+\t\tdatarate,\n+\t\tPSRAM_MEM_SIZE_64MB,\n+\t\tPSRAM_PAGE_SIZE_2KB,\n+\t\t0,\n+ };\n+\tPsram_UHS_Init(&psramCfg); //controller init\n+\t\n+ set_or_uhs();\n+\tset_uhs_phy();\n+}\n+\n+void reg_read_cal(uint32_t datarate)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal_1 = 0;\n+ uint32_t uhs_latency = 42;\n+ int32_t i = 0;\n+ uint8_t dqs_dq_flag = 0;\n+ uint32_t reg_dqs = 0;\n+ uint32_t reg_dq = 0;\n+\n+ for(uhs_latency = 41; uhs_latency > 0; uhs_latency --)\n+ {\n+ if(uhs_latency == 34)\n+ {\n+ uhs_phy_printf(\"reg read cal error\\r\\n\");\n+ while(1){\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ // break;\n+ }\n+\n+ uhs_phy_printf_debug(\"reg read cal by latency=%ld\\r\\n\",uhs_latency);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ \n+ // sweep dqs\n+ cfg_dq_rx(0);\n+ for(i = 15; i >= 0; i --)\n+ {\n+ cfg_dqs_rx(i);\n+\n+ uhs_reg_r(0); \n+\t\t\ttmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf_debug(\"reg read pass by dqs=%ld\\r\\n\",i); \n+ reg_dqs = i;\n+ dqs_dq_flag = 1;\n+ break;\n+ } \n+ else\n+ {\n+ uhs_phy_printf_debug(\"reg read fail by dqs=%ld\\r\\n\",i);\n+ }\n+\t\t\t\n+\t\t\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+\t\t\ttmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE);\n+\t\t\tif(tmpVal == 0)\n+\t\t\t{\n+\t\t\t\tuhs_phy_printf_debug(\"read done not found!!!\");\n+\t\t\t\tuhs_reset(datarate);\n+\t\t\t\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+\t\t\t\ttmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+\t\t\t\ttmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+\t\t\t\tBL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+\t\t\t\tcfg_dq_rx(0);\n+\t\t\t}\n+ \n+ }\n+\n+ // sweep dq \n+ cfg_dqs_rx(0);\n+ for(i = 15; i >=0; i --)\n+ {\n+ cfg_dq_rx(i);\n+\n+ uhs_reg_r(0);\n+ tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf_debug(\"reg read pass by dq=%ld\\r\\n\",i);\n+ reg_dq = i;\n+ dqs_dq_flag = 1;\n+ break; \n+ } \n+ else\n+ {\n+ uhs_phy_printf_debug(\"reg read fail by dq=%ld\\r\\n\",i);\n+ }\n+ \n+\t\t\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);\n+\t\t\ttmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE);\n+\t\t\tif(tmpVal == 0)\n+\t\t\t{\n+\t\t\t\tuhs_phy_printf_debug(\"read done not found!!!\");\n+\t\t\t\tuhs_reset(datarate);\n+\t\t\t\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+\t\t\t\ttmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+\t\t\t\ttmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+\t\t\t\tBL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+\t\t\t\tcfg_dqs_rx(0);\n+\t\t\t}\n+\t\t\t\n+ } \n+\n+ if (dqs_dq_flag == 1){\n+ uhs_latency = uhs_latency - 2;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ //sweep dqs\n+ cfg_dq_rx(0);\n+ for(i = 15; i >= 0; i --)\n+ {\n+ cfg_dqs_rx(i);\n+ uhs_reg_r(0); \n+ tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf_debug(\"reg read pass by dqs=%ld\\r\\n\",i); \n+ reg_dqs = i;\n+ dqs_dq_flag = 1;\n+ break; \n+ } \n+ else{\n+ uhs_phy_printf_debug(\"reg read fail by dqs=%ld\\r\\n\",i);\n+ }\n+ }\n+ // sweep dq \n+ cfg_dqs_rx(0);\n+ for(i = 15; i >=0; i --)\n+ {\n+ cfg_dq_rx(i);\n+\n+ uhs_reg_r(0);\n+ tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf_debug(\"reg read pass by dq=%ld\\r\\n\",i);\n+ reg_dq = i;\n+ dqs_dq_flag = 1;\n+ break;\n+ } \n+ else{\n+ uhs_phy_printf_debug(\"reg read fail by dq=%ld\\r\\n\",i);\n+ }\n+ }\n+ \n+ if(reg_dqs > reg_dq)\n+ {\n+ reg_dqs = (reg_dqs-reg_dq)/2;\n+ reg_dq = 0;\n+ } \n+ else\n+ {\n+ reg_dq = (reg_dq-reg_dqs)/2;\n+ reg_dqs = 0;\n+ } \n+ \n+ // set dqs & dq by register read calibration result \n+ cfg_dqs_rx(reg_dqs);\n+ cfg_dq_rx(reg_dq); \n+ uhs_reg_r(0);\n+ uhs_phy_printf(\"reg read cal pass, latency=%ld, dqs=%ld, dq=%ld\\r\\n\",uhs_latency,reg_dqs,reg_dq);\n+\n+ break;\n+ }\n+ }\n+}\n+\n+void cfg_dq_drv(uint32_t dq){\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);\n+}\n+\n+void cfg_dqs_drv(uint32_t dqs){\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);\n+}\n+\n+void reg_write_cal(void) //only need sweep dqs\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t tmpVal_1 = 0;\n+ int32_t i = 0;\n+ uint32_t reg_dqs;\n+ uint32_t reg_dq = 0;\n+ uint32_t reg_dqs1 = 0;\n+ uint32_t reg_dqs2 = 0;\n+ uint8_t dqs_dq_flag = 0;\n+\n+ // sweep1 dqs\n+ for(i = 15; i >=0; i --)\n+ {\n+ cfg_dqs_drv(i); \n+ uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1\n+ uhs_reg_r(2);\n+ tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if((tmpVal == 16) && (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf(\"reg write pass by -- dqs1=%ld\\r\\n\",i); \n+ reg_dqs1 = i;\n+ dqs_dq_flag = 1;\n+ break; \n+ } \n+ else{\n+ uhs_phy_printf_debug(\"reg write fail by -- dqs1=%ld\\r\\n\",i);\n+ }\n+ } \n+ // sweep2 dqs \n+ for(i = 0; i <=15; i ++)\n+ {\n+ cfg_dqs_drv(i);\n+ uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1\n+ uhs_reg_r(2);\n+ tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround \n+ tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if((tmpVal == 16) && (tmpVal_1 == 1))\n+ {\n+ uhs_phy_printf(\"reg write pass by ++ dqs2=%ld\\r\\n\",i);\n+ reg_dqs2 = i;\n+ dqs_dq_flag = 1;\n+ break; \n+ } \n+ else{\n+ uhs_phy_printf_debug(\"reg write fail by ++ dqs2=%ld\\r\\n\",i);\n+ }\n+ } \n+\n+ if(dqs_dq_flag == 0)\n+ {\n+ uhs_phy_printf(\"reg write cal error 0\\r\\n\");\n+ while(1){\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ // break;\n+ }\n+ \n+ reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ;\n+ // set dqs by register write cal result \n+ cfg_dqs_drv(reg_dqs);\n+ uhs_reg_w(uhs_latency_code,2,2,0); //BL_32 == 0\n+ uhs_reg_r(2);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == 0)\n+ {\n+ uhs_phy_printf(\"reg write cal pass dqs=%ld, dq=%ld\\r\\n\",reg_dqs,reg_dq);\n+ } \n+ else{\n+ uhs_phy_printf(\"reg write cal error 1\\r\\n\");\n+ while(1){\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ // break;\n+ }\n+ \n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);\n+ reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV);\n+ dqs_dq_delta = 16 + reg_dqs - reg_dq;\n+ uhs_phy_printf(\"reg_write_cal return dqs_dq_delta=%ld\\r\\n\",dqs_dq_delta);\n+ // return dqs_dq_delta;\n+}\n+\n+void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)\n+{\n+ uint32_t addr_tmp = addr;\n+ uint32_t data = data0;\n+ int32_t i = 0;\n+ for(i = 0; i < (len>>2); i ++)\n+ {\n+ addr_tmp = (i << 2) + addr;\n+ if(i % 2 == 0)\n+ data = data0 + i;\n+ else\n+ data = data1 + i;\n+ BL_WR_WORD(addr_tmp,data); \n+ }\n+}\n+uint32_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)\n+{\n+ uint32_t array_read_pass = 1;\n+ uint32_t addr_tmp = addr;\n+ uint32_t data = data0;\n+ uint32_t data_read = 0;\n+ int32_t i = 0;\n+ \n+ for(i = 0; i < (len>>2); i ++)\n+ {\n+ addr_tmp = (i << 2) + addr;\n+ data_read = BL_RD_WORD(addr_tmp);\n+ if(i % 2 == 0)\n+ data = data0 + i;\n+ else\n+ data = data1 + i;\n+ if(data_read != data){\n+ array_read_pass = 0;\n+ break;\n+ }\n+ }\n+ return array_read_pass;\n+}\n+\n+void set_ck_dly_drv(uint32_t array_ck_dly_drv)\n+{\n+ uint32_t array_dqx_dly_drv = 0;\n+ uint32_t array_dqsx_dly_drv = 0;\n+ uint32_t array_cen_dly_drv = 0;\n+\n+ arch_delay_us(1); // ck modify need time\n+\n+ array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0;\n+ array_cen_dly_drv = array_dqx_dly_drv + 1;\n+ // array_dqsx_dly_drv = ((int32_t)((int32_t)(dqs_dq_delta)+(int32_t)(array_dqx_dly_drv))<0)?0:(array_dqx_dly_drv + dqs_dq_delta);\n+ array_dqsx_dly_drv = (dqs_dq_delta + array_dqx_dly_drv >= 16) ? (dqs_dq_delta + array_dqx_dly_drv - 16) : 0;\n+\n+ // array_dqsx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqsx_dly_drv;\n+ array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv;\n+ array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv;\n+ array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv;\n+\n+ cfg_dq_drv(array_dqx_dly_drv);\n+ cfg_dqs_drv(array_dqsx_dly_drv);\n+ cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv);\n+\n+ arch_delay_us(10); // ck modify need time\n+}\n+\n+void array_read_latency_cal(void)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t uhs_latency = 42;\n+ uint32_t array_ck_dly_drv = 0;\n+ uint32_t flag = 0;\n+\n+ uint32_t dig = 0;\n+ uint32_t ana = 0;\n+ uint32_t latency = 0;\n+\n+ array_write_fix(0x50000000,128,0x12345678,0x87654321);\n+\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ dig = (tmpVal >> 16) & 0xF;\n+ ana = (tmpVal >> 20) & 0x7;\n+ latency = (dig<<2) + ana;\n+\n+ for(uhs_latency = latency; uhs_latency > 0; uhs_latency --)\n+ {\n+ if(uhs_latency == 34)\n+ {\n+ uhs_phy_printf(\"array read latency cal error\\r\\n\");\n+ while(1){\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ // break;\n+ }\n+\n+ uhs_phy_printf_debug(\"array read cal by latency=%ld\\r\\n\",uhs_latency);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+\n+ array_ck_dly_drv = 11;\n+ set_ck_dly_drv(array_ck_dly_drv);\n+\n+ flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+\n+ if(flag == 1)\n+ {\n+ uhs_phy_printf_debug(\"array read pass by ck == 11\\r\\n\"); \n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ uhs_phy_printf(\"array read latency cal pass, latency=%ld, ck=%ld\\r\\n\",uhs_latency,array_ck_dly_drv);\n+ break;\n+ } \n+ else\n+ {\n+ uhs_phy_printf_debug(\"array read fail by ck == 11\\r\\n\");\n+ array_ck_dly_drv = 4;\n+ set_ck_dly_drv(array_ck_dly_drv);\n+ flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+ if(flag == 1)\n+ {\n+ uhs_phy_printf_debug(\"array read pass by ck == 4\\r\\n\"); \n+ // uhs_latency = uhs_latency - 2;\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);\n+ BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);\n+ uhs_phy_printf(\"array read latency cal pass, latency=%ld, ck=%ld\\r\\n\",uhs_latency,array_ck_dly_drv);\n+ break;\n+ } \n+ else{\n+ uhs_phy_printf_debug(\"array read fail by ck == 4\\r\\n\");\n+ }\n+ } \n+ }\n+}\n+\n+void array_write_ck_cal(void) \n+{\n+ uint32_t array_ck_dly_drv = 0;\n+ uint32_t array_ck_dly_drv1 = 0;\n+ uint32_t array_ck_dly_drv2 = 0;\n+ uint32_t flag = 0;\n+\n+ array_write_fix(0x50000000,1024,0x12345678,0x87654321);\n+\n+ for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --)\n+ {\n+ set_ck_dly_drv(array_ck_dly_drv);\n+ \n+ flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321);\n+ if(flag == 0){\n+ uhs_phy_printf_debug(\"array write ck cal fail by ck=%ld\\r\\n\",array_ck_dly_drv);\n+ array_ck_dly_drv1 = array_ck_dly_drv;\n+ break;\n+ }\n+ }\n+\n+ if(flag == 1){\n+ array_ck_dly_drv = (15 + 4) / 2;\n+ set_ck_dly_drv(array_ck_dly_drv);\n+\n+ uhs_phy_printf(\"array write ck cal pass, ck=%ld\\r\\n\",array_ck_dly_drv);\n+ return;\n+ }\n+\n+ for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++)\n+ {\n+ set_ck_dly_drv(array_ck_dly_drv);\n+ \n+ flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321);\n+ if(flag == 0){\n+ uhs_phy_printf_debug(\"array write ck cal fail by ck=%ld\\r\\n\",array_ck_dly_drv);\n+ array_ck_dly_drv2 = array_ck_dly_drv;\n+ break;\n+ }\n+ }\n+\n+ if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4)\n+ {\n+ uhs_phy_printf_debug(\"array write ck cal error\\r\\n\");\n+ while(1){\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ // break;\n+ }\n+ if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4))\n+ {\n+ array_ck_dly_drv = 15;\n+ }\n+ else\n+ {\n+ array_ck_dly_drv = 4;\n+ } \n+ \n+ set_ck_dly_drv(array_ck_dly_drv);\n+ \n+ uhs_phy_printf(\"array write ck cal pass, ck=%ld\\r\\n\",array_ck_dly_drv);\n+\n+}\n+\n+void array_read_dqs_dq_cal(void)\n+{\n+ // uint32_t tmpVal = 0;\n+ int32_t i = 0;\n+ uint32_t array_dqs = 0;\n+ uint32_t array_dq = 0;\n+ uint32_t dqs_flag;\n+ uint32_t dq_flag;\n+ array_write_fix(0x50000000,128,0x12345678,0x87654321);\n+ // sweep dqs\n+ cfg_dq_rx(0);\n+\n+ for(i = 15; i >= 0; i --)\n+ {\n+ cfg_dqs_rx(i);\n+ dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+ if(dqs_flag == 1)\n+ {\n+ uhs_phy_printf_debug(\"array_read_dqs_dq_cal pass by dqs%ld\\r\\n\",i); \n+ array_dqs = i;\n+ break; \n+ }\n+ }\n+ // sweep dq \n+ cfg_dqs_rx(0);\n+ for(i = 15; i >=0; i --)\n+ {\n+ cfg_dq_rx(i);\n+ dq_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+ if(dq_flag == 1)\n+ {\n+ uhs_phy_printf_debug(\"array_read_dqs_dq_cal pass by dq%ld\\r\\n\",i); \n+ array_dq = i;\n+ break; \n+ } \n+ }\n+ if(dqs_flag == 0 && dq_flag == 0)\n+ {\n+ uhs_phy_printf(\"array_read_dqs_dq_cal error\\r\\n\");\n+ while(1)\n+ {\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ }\n+ if(array_dqs > array_dq)\n+ {\n+ array_dqs = (array_dqs-array_dq)/2;\n+ array_dq = 0;\n+ }\n+ else\n+ {\n+ array_dq = (array_dq-array_dqs)/2;\n+ array_dqs = 0;\n+ }\n+ cfg_dq_rx(array_dq);\n+ cfg_dqs_rx(array_dqs);\n+ uhs_phy_printf(\"array_read_dqs_dq_cal pass by array_dqs=%ld, array_dq=%ld\\r\\n\",array_dqs,array_dq);\n+}\n+\n+void array_write_dqs_dq_cal(void)\n+{\n+ uint32_t tmpVal = 0;\n+ int32_t i = 0;\n+ uint32_t dqs_flag = 0;\n+ uint32_t array_dqs_dly_drv = 0;\n+ uint32_t array_dqs_dly_drv1 = 0;\n+ uint32_t array_dqs_dly_drv2 = 0;\n+\n+ for(i = 15; i >= 0; i --)\n+ { \n+ cfg_dqs_drv(i); \n+ array_write_fix(0x50000000,128,0x12345678,0x87654321);\n+ dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+ if(dqs_flag == 1)\n+ {\n+ uhs_phy_printf(\"array_write_dqs_dq_cal pass by -- dqs1=%ld\\r\\n\",i);\n+ array_dqs_dly_drv1 = i;\n+ break; \n+ } \n+ else\n+ {\n+ uhs_phy_printf_debug(\"array_write_dqs_dq_cal fail by -- dqs1=%ld\\r\\n\",i);\n+ }\n+ }\n+ for(i = 0; i <= 15; i ++)\n+ {\n+ cfg_dqs_drv(i);\n+ array_write_fix(0x50000000,128,0x12345678,0x87654321);\n+ dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321);\n+ if(dqs_flag == 1)\n+ {\n+ uhs_phy_printf(\"array_write_dqs_dq_cal pass by ++ dqs2=%ld\\r\\n\",i);\n+ array_dqs_dly_drv2 = i;\n+ break;\n+ } \n+ else\n+ {\n+ uhs_phy_printf_debug(\"array_write_dqs_dq_cal fail by ++ dqs2=%ld\\r\\n\",i);\n+ }\n+ }\n+ if(dqs_flag == 0)\n+ {\n+ uhs_phy_printf(\"array_write_dqs_dq_cal error\\r\\n\");\n+ while(1)\n+ {\n+ uhs_phy_printf(\".\");\n+ uhs_phy_delay_us(100000);\n+ };\n+ }\n+ array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ;\n+ // if ck_dly_drv = 4, fix dqsx_dly_drv to 0\n+\ttmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);\n+\ttmpVal = (tmpVal >> 16) & 0xF;\n+\tif(tmpVal == 4)\n+\t{\n+\t\tarray_dqs_dly_drv = 0;\n+\t}\n+ uhs_phy_printf(\"array_write_dqs_dq_cal pass by array_dqs_dly_drv=%ld\\r\\n\",array_dqs_dly_drv);\n+ // set dqs by register write cal result \n+ cfg_dqs_drv(array_dqs_dly_drv);\n+}\n+\n+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq)\n+{\n+ uint32_t xtalFreq = 0;\n+ uint32_t factor = 0;\n+ GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = {\n+ .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */\n+ .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */\n+ .clkpllVcoSpeed = 7, /*!< pll_vco_speed */\n+ .clkpllEvenDivEn = 1, /*!< pll_even_div_en */\n+ .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */\n+ };\n+ GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = {\n+ { NULL, 0x0 }, /*!< XTAL is None */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 24M */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 32M */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 38.4M */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 40M */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is 26M */\n+ { &uhsPllMCfg, 0x0 }, /*!< XTAL is RC32M */\n+ };\n+ GLB_PLL_REF_CLK_Type refClk;\n+\n+ /* calc clkpllRefdivRatio */\n+ switch(xtalType){\n+ case GLB_XTAL_NONE:\n+ return ERROR;\n+ case GLB_XTAL_24M:\n+ xtalFreq = 240;\n+ uhsPllMCfg.clkpllRefdivRatio = 1;\n+ break;\n+ case GLB_XTAL_32M:\n+ xtalFreq = 320;\n+ uhsPllMCfg.clkpllRefdivRatio = 2;\n+ break;\n+ case GLB_XTAL_38P4M:\n+ xtalFreq = 384;\n+ uhsPllMCfg.clkpllRefdivRatio = 2;\n+ break;\n+ case GLB_XTAL_40M:\n+ xtalFreq = 400;\n+ uhsPllMCfg.clkpllRefdivRatio = 2;\n+ break;\n+ case GLB_XTAL_26M:\n+ xtalFreq = 260;\n+ uhsPllMCfg.clkpllRefdivRatio = 1;\n+ break;\n+ case GLB_XTAL_RC32M:\n+ xtalFreq = 320;\n+ uhsPllMCfg.clkpllRefdivRatio = 2;\n+ break;\n+ default :\n+ break;\n+ }\n+ /* calc clkpllSelSampleClk */\n+ factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio);\n+ if(factor<32*2048){\n+ uhsPllMCfg.clkpllSelSampleClk = 0;\n+ }else if(factor<64*2048){\n+ uhsPllMCfg.clkpllSelSampleClk = 1;\n+ }else if(factor<128*2048){\n+ uhsPllMCfg.clkpllSelSampleClk = 2;\n+ }else{\n+ uhsPllMCfg.clkpllSelSampleClk = 2;\n+ }\n+ /* calc clkpllVcoSpeed */\n+ if(pllFreq<800){\n+ uhsPllMCfg.clkpllVcoSpeed = 1;\n+ }else if(pllFreq<1000){\n+ uhsPllMCfg.clkpllVcoSpeed = 2;\n+ }else if(pllFreq<1200){\n+ uhsPllMCfg.clkpllVcoSpeed = 3;\n+ }else if(pllFreq<1500){\n+ uhsPllMCfg.clkpllVcoSpeed = 4;\n+ }else if(pllFreq<1700){\n+ uhsPllMCfg.clkpllVcoSpeed = 5;\n+ }else if(pllFreq<1900){\n+ uhsPllMCfg.clkpllVcoSpeed = 6;\n+ }else if(pllFreq<2200){\n+ uhsPllMCfg.clkpllVcoSpeed = 7;\n+ }else{\n+ uhsPllMCfg.clkpllVcoSpeed = 8;\n+ }\n+ /* calc clkpllEvenDivRatio */\n+ uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50;\n+ /* calc clkpllSdmin */\n+ uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor;\n+ uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor;\n+ uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor;\n+ uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor;\n+ uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor;\n+ uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor;\n+ \n+ if (xtalType == GLB_XTAL_RC32M) {\n+ refClk = GLB_PLL_REFCLK_RC32M;\n+ } else {\n+ refClk = GLB_PLL_REFCLK_XTAL;\n+ }\n+ \n+ GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);\n+ GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);\n+ GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1);\n+ \n+ return SUCCESS;\n+}\n+\n+void self_cal(uint32_t datarate)\n+{ \n+ // int32_t P1= 0;\n+ uint32_t tmpVal = 0;\n+ // uint32_t uhs_latency = 0;\n+\n+ if (datarate >= 933*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_1066;\n+ }else if(datarate >= 800*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_933;\n+ }else if(datarate >= 533*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_800;\n+ }else if(datarate >= 400*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_533;\n+ }else if(datarate >= 333*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_400;\n+ }else if(datarate >= 200*2){\n+ uhs_latency_code = UHS_LATENCY_CODE_333;\n+ }else{\n+ uhs_latency_code = UHS_LATENCY_CODE_200;\n+ }\n+\n+ PSRAM_UHS_Cfg_Type psramCfg = {\n+ datarate,\n+ PSRAM_MEM_SIZE_64MB,\n+ PSRAM_PAGE_SIZE_2KB,\n+ 0,\n+ };\n+\n+\t// set to 2000Mbps\n+ uhs_reg_w(uhs_latency_code,2,0,0); // BL_32 == 0\n+ // set_uhspll_freq(datarate); // use SW function later\n+ GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate); //stuck\n+ Psram_UHS_Init(&psramCfg); //controller init\n+ set_uhs_phy();\n+\t\n+ // check reg read \n+ uhs_reg_r(0);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+uhs_latency_code)){\n+ uhs_phy_printf(\"register write pass at 1400Mbps and read pass at %ldMbps\\r\\n\",datarate);\n+ } \n+ else{\n+ uhs_phy_printf(\"register write fail at 1400Mbps or read fail at %ldMbps\\r\\n\",datarate);\n+ }\n+\n+ // register read latency & dqs & dq calibration\n+ reg_read_cal(datarate);\n+ // register write dqs & dq calibration\n+ reg_write_cal();\n+ uhs_reg_w(uhs_latency_code,2,2,0); // BL_32 == 0\n+ uhs_reg_r(2);\n+ // array read latency calibration \n+ array_read_latency_cal();\n+ // array write ck calibration\n+ array_write_ck_cal();\n+ // array read dqs & dq calibration\n+ array_read_dqs_dq_cal();\n+ // array write dqs & dq calibration\n+ array_write_dqs_dq_cal();\n+}\n+\n+void soft_reset(void)\n+{\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset\n+ BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal);\n+}\n+\n+void uhs_phy_init(uint32_t datarate)\n+{\n+ uhs_phy_printf_debug(\"uhs phy init\\r\\n\");\n+ power_up_mm();\n+ power_up_uhspll();\n+ \n+ power_up_ldo12uhs();\n+ set_cen_ck_ckn();\n+\n+ set_or_uhs();\n+ switch_to_ldo12uhs();\n+ release_cen_ck_ckn();\n+\n+ uint32_t tmpVal = 0;\n+ tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en\n+ BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal);\n+\n+ PSRAM_UHS_Cfg_Type psramCfg = {\n+ 1400,\n+ PSRAM_MEM_SIZE_64MB,\n+ PSRAM_PAGE_SIZE_2KB,\n+ 0,\n+ };\n+\n+ // set_uhspll_freq(1400); // 700MHz is prefer , use SW function later\n+ GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400); //stuck\n+ Psram_UHS_Init(&psramCfg); // controller init\n+ set_uhs_phy_init(); // phy init\n+ psram_init(); // psram init after set freq & set_phy\n+\n+ uhs_reg_r(0);\n+ tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;\n+ if(tmpVal == ((2<<3)+1)) // 1400M --> default uhs_latency_code == 1\n+ {\n+ uhs_phy_printf_debug(\"register read pass at datarate at 1400Mbps\\r\\n\");\n+ } \n+ else{\n+ uhs_phy_printf_debug(\"register read fail at datarate at 1400Mbps\\r\\n\");\n+ } \n+ \n+ //get dcache original state\n+ __DSB();\n+ __ISB();\n+ dcache_original = __get_MHCR();\n+ dcache_original &= (0x1<<1);\n+ __DSB();\n+ __ISB();\n+ uhs_phy_printf(\"dcache_original=%lx\\r\\n\",dcache_original);\n+\n+ csi_dcache_disable();\n+\n+ //get dcache current state\n+ __DSB();\n+ __ISB();\n+ dcache_current = __get_MHCR();\n+ dcache_current &= (0x1<<1);\n+ __DSB();\n+ __ISB();\n+ uhs_phy_printf(\"dcache_current=%lx\\r\\n\",dcache_current);\n+\n+ if(dcache_current == 0x0)\n+ {\n+ self_cal(datarate);\n+ }\n+ else\n+ {\n+ uhs_phy_printf(\"dcache disable fail\\r\\n\");\n+ }\n+ \n+ if (dcache_original == (0x1<<1))\n+ { \n+ csi_dcache_enable(); \n+ }\n+\n+ //get dcache end state\n+ __DSB();\n+ __ISB();\n+ dcache_end = __get_MHCR();\n+ dcache_end &= (0x1<<1);\n+ __DSB();\n+ __ISB();\n+ if(dcache_end == dcache_original)\n+ {\n+ uhs_phy_printf(\"dcache state right , dcache_state=%lx\\r\\n\",dcache_end);\n+ }\n+ else\n+ {\n+ uhs_phy_printf(\"dcache state error\\r\\n\");\n+ }\n+\n+ uhs_phy_delay_us(1000);\n+\n+}\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..aa0d23b852c0a56df7cd47333a815ed3ece8d927\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c\n@@ -0,0 +1,1939 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_usb.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"bl808_usb.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup USB\n+ * @{\n+ */\n+\n+/** @defgroup USB_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group USB_Private_Macros */\n+\n+/** @defgroup USB_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group USB_Private_Types */\n+\n+/** @defgroup USB_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group USB_Private_Variables */\n+\n+/** @defgroup USB_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group USB_Global_Variables */\n+\n+/** @defgroup USB_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group USB_Private_Fun_Declaration */\n+\n+/** @defgroup USB_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group USB_Private_Functions */\n+\n+/** @defgroup USB_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief USB global interrupt enable or disable\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Global_IntEnable(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_GLINT_EN_HOV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GLINT_EN_HOV);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB global interrupt mask or unmask\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_GLB_INT);\n+\n+ if (intMask == MASK) {\n+ tmpVal = tmpVal | (1 << intType);\n+ } else {\n+ tmpVal = tmpVal & ~(1 << intType);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_GLB_INT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB global interrupt status\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType));\n+\n+ return (BL_RD_REG(USB_BASE, USB_GLB_ISR) & (1 << intType)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB normal configuration\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t to = 0;\n+\n+ if (cfg->swRst) {\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_SFRST_HOV);\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_SFRST_HOV)) {\n+ if (to >= cfg->rstTimeOut) {\n+ return ERROR;\n+ }\n+\n+ to++;\n+ }\n+ }\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+\n+ if (cfg->forceFullSpeed) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_FORCE_FS);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_FORCE_FS);\n+ }\n+\n+ if (cfg->remoteWakeupEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+\n+ if (cfg->chipEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_CHIP_EN_HOV);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CHIP_EN_HOV);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB device speed\n+ *\n+ * @param None\n+ *\n+ * @return high speed or full speed\n+ *\n+*******************************************************************************/\n+USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void)\n+{\n+ return (USB_DEVICE_SPEED_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_HS_EN_HOV);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB go suspend\n+ *\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Go_Suspend(uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_GOSUSP);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GOSUSP);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB device address\n+ *\n+ * @param addr: address\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Device_Address(uint8_t addr)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM((addr <= 127));\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DEVADR, addr);\n+ BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB device address\n+ *\n+ * @param None\n+ *\n+ * @return address\n+ *\n+*******************************************************************************/\n+uint8_t USB_Get_Device_Address(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_ADR), USB_DEVADR);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB non-control transfer enable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_AFT_CONF);\n+ BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB non-control transfer disable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_AFT_CONF);\n+ BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB FIFO counters and location counters clear\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Clear_FIFO(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_TST);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_CLRFF_HOV);\n+ BL_WR_REG(USB_BASE, USB_DEV_TST, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB SOF mask timer in high speed\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_HS);\n+ BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB SOF mask timer in full speed\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_FS);\n+ BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB SOF mask timer in full speed\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_SoftDetach_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_UNPLUG);\n+ BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB SOF mask timer in full speed\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_SoftDetach_Disable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_UNPLUG);\n+ BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB FIFOn empty\n+ *\n+ * @param fifoNum: FIFO number\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum)\n+{\n+ CHECK_PARAM(IS_USB_FIFO_EMPTY_TYPE(fifoNum));\n+\n+ return (BL_RD_REG(USB_BASE, USB_DEV_CXCFE) & (1 << fifoNum)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB control FIFO empty\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_EMP) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB control FIFO full\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Is_CTRL_FIFO_Full(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FUL) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB control FIFO full\n+ *\n+ * @param None\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Clear_CTRL_FIFO(void)\n+{\n+ BL_WR_REG(USB_BASE, USB_DEV_CXCFE, BL_SET_REG_BIT(0, USB_CX_CLR));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB control endpoint stall once\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_STL);\n+ BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB control endpoint data transfer done\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_DONE);\n+ BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB endpoint receive 0 length data packet\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID)\n+{\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ return (BL_RD_REG(USB_BASE, USB_DEV_RXZ) & (1 << (epID - 1))) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB endpoint receive 0 length data packet\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID)\n+{\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_RXZ, 1 << (epID - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reset USB in endpoint data_toggle_sequence\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ /* calc reg address */\n+ regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + (epID - 1) * 4;\n+\n+ /* clear RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ /* set RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_IEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ /* clear RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reset USB out endpoint data_toggle_sequence\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ /* calc reg address */\n+ regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + (epID - 1) * 4;\n+\n+ /* clear RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ /* set RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_OEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ /* clear RSTG_IEPn bit */\n+ BL_RD_WORD(regAddr);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB endpoint transmit 0 length data packet\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1);\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal |= (1 << USB_TX0BYTE_IEP1_POS);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief is USB endpoint receive 0 length data packet\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID)\n+{\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ return (BL_RD_REG(USB_BASE, USB_DEV_TXZ) & (1 << (epID - 1))) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB endpoint transfer 0 length data packet status\n+ *\n+ * @param epID: endpoint number\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID)\n+{\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_TXZ, 1 << (epID - 1));\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB IN endpoint stall\n+ *\n+ * @param epID: endpoint number\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1);\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_IEP1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_IEP1);\n+ }\n+\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB IN endpoint max packet size\n+ *\n+ * @param epID: endpoint number\n+ * @param max: max packet size\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+ CHECK_PARAM((max <= 0x7FF));\n+\n+ regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1);\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_IEP1, max);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB OUT endpoint stall\n+ *\n+ * @param epID: endpoint number\n+ * @param enable: ENABLE or DISABLE\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+\n+ regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1);\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+\n+ if (enable) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_OEP1);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_OEP1);\n+ }\n+\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB OUT endpoint max packet size\n+ *\n+ * @param epID: endpoint number\n+ * @param max: max packet size\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+ CHECK_PARAM((max <= 0x7FF));\n+\n+ regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1);\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_OEP1, max);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB FIFO ID of IN endpoint\n+ *\n+ * @param epID: endpoint number\n+ * @param fifoID: FIFO ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+ CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID));\n+\n+ if (epID <= USB_Endpoint_4) {\n+ regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET;\n+ } else {\n+ regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+\n+ switch (epID) {\n+ case USB_Endpoint_1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP1, fifoID);\n+ break;\n+\n+ case USB_Endpoint_2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP2, fifoID);\n+ break;\n+\n+ case USB_Endpoint_3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP3, fifoID);\n+ break;\n+\n+ case USB_Endpoint_4:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP4, fifoID);\n+ break;\n+\n+ case USB_Endpoint_5:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP5, fifoID);\n+ break;\n+\n+ case USB_Endpoint_6:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP6, fifoID);\n+ break;\n+\n+ case USB_Endpoint_7:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP7, fifoID);\n+ break;\n+\n+ case USB_Endpoint_8:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP8, fifoID);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB FIFO ID of IN endpoint\n+ *\n+ * @param epID: endpoint number\n+ * @param fifoID: FIFO ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ /* cannot be USB_Endpoint_0 */\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID));\n+ CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID));\n+\n+ if (epID <= USB_Endpoint_4) {\n+ regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET;\n+ } else {\n+ regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET;\n+ }\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+\n+ switch (epID) {\n+ case USB_Endpoint_1:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP1, fifoID);\n+ break;\n+\n+ case USB_Endpoint_2:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP2, fifoID);\n+ break;\n+\n+ case USB_Endpoint_3:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP3, fifoID);\n+ break;\n+\n+ case USB_Endpoint_4:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP4, fifoID);\n+ break;\n+\n+ case USB_Endpoint_5:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP5, fifoID);\n+ break;\n+\n+ case USB_Endpoint_6:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP6, fifoID);\n+ break;\n+\n+ case USB_Endpoint_7:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP7, fifoID);\n+ break;\n+\n+ case USB_Endpoint_8:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP8, fifoID);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB FIFO configuration\n+ *\n+ * @param fifoID: FIFO ID\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal1 = 0;\n+ uint32_t tmpVal2 = 0;\n+ uint32_t en = 0;\n+\n+ CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID));\n+ CHECK_PARAM(IS_USB_FIFO_DIR_TYPE(cfg->dir));\n+ CHECK_PARAM(IS_USB_ENDPOINT_TYPE(cfg->epID));\n+ CHECK_PARAM(IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(cfg->blockSize));\n+ CHECK_PARAM(IS_USB_FIFO_BLOCK_CNT_TYPE(cfg->blockType));\n+ CHECK_PARAM(IS_USB_FIFO_TRANSFER_TYPE(cfg->fifoType));\n+\n+ tmpVal1 = BL_RD_REG(USB_BASE, USB_DEV_FMAP);\n+ tmpVal2 = BL_RD_REG(USB_BASE, USB_DEV_FCFG);\n+\n+ if (cfg->enable) {\n+ en = 1;\n+ }\n+\n+ switch (fifoID) {\n+ case USB_FIFO_0:\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO0, cfg->dir);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO0, cfg->epID);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F0, en);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F0, cfg->blockSize);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F0, cfg->blockType);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F0, cfg->fifoType);\n+ break;\n+\n+ case USB_FIFO_1:\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO1, cfg->dir);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO1, cfg->epID);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F1, en);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F1, cfg->blockSize);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F1, cfg->blockType);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F1, cfg->fifoType);\n+ break;\n+\n+ case USB_FIFO_2:\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO2, cfg->dir);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO2, cfg->epID);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F2, en);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F2, cfg->blockSize);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F2, cfg->blockType);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F2, cfg->fifoType);\n+ break;\n+\n+ case USB_FIFO_3:\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO3, cfg->dir);\n+ tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO3, cfg->epID);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F3, en);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F3, cfg->blockSize);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F3, cfg->blockType);\n+ tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F3, cfg->fifoType);\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_FMAP, tmpVal1);\n+ BL_WR_REG(USB_BASE, USB_DEV_FCFG, tmpVal2);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief reset USB FIFO\n+ *\n+ * @param fifoID: FIFO ID\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID));\n+\n+ regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID;\n+\n+ tmpVal = BL_RD_WORD(regAddr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_FFRST0_HOV);\n+ BL_WR_WORD(regAddr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB out FIFO count\n+ *\n+ * @param fifoID: FIFO ID\n+ *\n+ * @return FIFO count\n+ *\n+*******************************************************************************/\n+uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID)\n+{\n+ uint32_t regAddr = 0;\n+\n+ CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID));\n+\n+ regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID;\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_WORD(regAddr), USB_BC_F0);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB dma configuration\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_USB_DMA_TRANS_DIR_TYPE(cfg->dir));\n+ CHECK_PARAM(IS_USB_DMA_TARGET_FIFO_TYPE(fifoN));\n+ CHECK_PARAM(((cfg->length) <= 0x1FFFF));\n+\n+ switch (fifoN) {\n+ case USB_DMA_TARGET_FIFO_CTRL:\n+ tmpVal = (1 << 4);\n+ break;\n+ case USB_DMA_TARGET_FIFO_0:\n+ tmpVal = (1 << 0);\n+ break;\n+ case USB_DMA_TARGET_FIFO_1:\n+ tmpVal = (1 << 1);\n+ break;\n+ case USB_DMA_TARGET_FIFO_2:\n+ tmpVal = (1 << 2);\n+ break;\n+ case USB_DMA_TARGET_FIFO_3:\n+ tmpVal = (1 << 3);\n+ break;\n+ default:\n+ break;\n+ }\n+ BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal);\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1);\n+\n+ switch (cfg->dir) {\n+ case USB_DMA_TRANS_DIR_FIFO_2_MEM:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0);\n+ break;\n+\n+ case USB_DMA_TRANS_DIR_MEM_2_FIFO:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 1);\n+ break;\n+\n+ case USB_DMA_TRANS_DIR_FIFO_2_FIFO:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0);\n+\n+ if ((cfg->length) & 0x3) {\n+ return ERROR;\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, cfg->length);\n+ BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal);\n+\n+ BL_WR_REG(USB_BASE, USB_DMA_CPS2, cfg->memAddr);\n+\n+ return SUCCESS;\n+}\n+/****************************************************************************/ /**\n+ * @brief reset usb dma accessing fifo\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+void USB_Reset_DMA_Accessing_Fifo(void)\n+{\n+ BL_WR_REG(USB_BASE, USB_DMA_TFN, 0);\n+}\n+/****************************************************************************/ /**\n+ * @brief update USB dma transmit configuration\n+ *\n+ * @param memAddr: memory address\n+ * @param length: transmit length\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, length);\n+ BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal);\n+\n+ BL_WR_REG(USB_BASE, USB_DMA_CPS2, memAddr);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB dma transmit start\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_DMA_Start(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_DMA_START_HOV);\n+ BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB setup command\n+ *\n+ * @param setup[2]: buffer\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2])\n+{\n+ uint32_t tmpVal = 0;\n+\n+ if (NULL == setup) {\n+ return ERROR;\n+ }\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_ACC_CXF_HOV);\n+ BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal);\n+\n+ setup[0] = BL_RD_REG(USB_BASE, USB_DMA_CPS3);\n+ setup[1] = BL_RD_REG(USB_BASE, USB_DMA_CPS3);\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN);\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_ACC_CXF_HOV);\n+ BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB vdma configuration\n+ *\n+ * @param fifoN: target FIFO\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t setting1Addr = 0;\n+ uint32_t setting2Addr = 0;\n+\n+ CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN));\n+ CHECK_PARAM(IS_USB_VDMA_TRANS_DIR_TYPE(cfg->dir));\n+ CHECK_PARAM(((cfg->length) <= 0x1FFFF));\n+\n+ setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN);\n+ setting2Addr = USB_BASE + USB_VDMA_CXFPS2_OFFSET + 0x08 * (fifoN);\n+ tmpVal = BL_RD_WORD(setting1Addr);\n+\n+ switch (cfg->dir) {\n+ case USB_VDMA_TRANS_DIR_FIFO_2_MEM:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0);\n+ break;\n+\n+ case USB_VDMA_TRANS_DIR_MEM_2_FIFO:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 1);\n+ break;\n+\n+ case USB_VDMA_TRANS_DIR_FIFO_2_FIFO:\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 1);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0);\n+\n+ if ((cfg->length) & 0x3) {\n+ return ERROR;\n+ }\n+\n+ break;\n+\n+ default:\n+ break;\n+ }\n+\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_LEN_CXF, cfg->length);\n+ BL_WR_WORD(setting1Addr, tmpVal);\n+\n+ BL_WR_WORD(setting2Addr, cfg->memAddr);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB vdma transmit start\n+ *\n+ * @param fifoN: target FIFO\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN)\n+{\n+ uint32_t tmpVal = 0;\n+ uint32_t setting1Addr = 0;\n+\n+ CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN));\n+\n+ setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN);\n+\n+ tmpVal = BL_RD_WORD(setting1Addr);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_START_CXF);\n+ BL_WR_WORD(setting1Addr, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB vdma transmit start status\n+ *\n+ * @param fifoN: target FIFO\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN)\n+{\n+ uint32_t setting1Addr = 0;\n+\n+ CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN));\n+\n+ setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 8 * (fifoN);\n+\n+ return BL_GET_REG_BITS_VAL(BL_RD_WORD(setting1Addr), USB_VDMA_START_CXF) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB vdma multi channel function enable\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_VDMA_Enable(void)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_VDMA_CTRL);\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_EN);\n+ BL_WR_REG(USB_BASE, USB_VDMA_CTRL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB LPM configuration\n+ *\n+ * @param cfg: configuration\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_USB_LPM_RESP_TYPE(cfg->resp));\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CAP);\n+\n+ if (cfg->lpmWakeUpEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_LPM_CAP, tmpVal);\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_ACCEPT, cfg->resp);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MIN, cfg->minBesl);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MAX, cfg->maxBesl);\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL);\n+\n+ if (cfg->lpmEn) {\n+ tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_EN);\n+ } else {\n+ tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_EN);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set USB LPM configuration\n+ *\n+ * @param None\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+uint8_t USB_Get_LPM_BESL(void)\n+{\n+ return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_LPM_BESL);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief set suspend delay\n+ *\n+ * @param ms: delay ms count\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms)\n+{\n+ uint32_t tmpVal;\n+\n+ CHECK_PARAM((ms <= 7));\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ICR);\n+ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_IDLE_CNT, ms);\n+ BL_WR_REG(USB_BASE, USB_DEV_ICR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB group interrupt mask or unmask\n+ *\n+ * @param intType: interrupt type\n+ * @param intMask: MASK or UNMASK\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask)\n+{\n+ uint32_t tmpVal = 0;\n+\n+ CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType));\n+\n+ tmpVal = BL_RD_REG(USB_BASE, USB_DEV_MIGR);\n+\n+ if (intMask == MASK) {\n+ tmpVal = tmpVal | (1 << intType);\n+ } else {\n+ tmpVal = tmpVal & ~(1 << intType);\n+ }\n+\n+ BL_WR_REG(USB_BASE, USB_DEV_MIGR, tmpVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB group interrupt status\n+ *\n+ * @param intType: interrupt type\n+ *\n+ * @return SET or RESET\n+ *\n+*******************************************************************************/\n+BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType)\n+{\n+ CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType));\n+\n+ return (BL_RD_REG(USB_BASE, USB_DEV_IGR) & (1 << intType)) ? SET : RESET;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB mask sub group interrupt\n+ *\n+ * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ...\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType)\n+{\n+ uint64_t val = intType;\n+ uint32_t bit = 0;\n+ uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET);\n+ uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET);\n+ uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET);\n+ uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET);\n+ uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET);\n+\n+ while (0 == arch_ctzll(&val, &bit)) {\n+ val &= ~(((uint64_t)1) << bit);\n+ switch (bit) {\n+ case USB_SUB_GRP0_INT_CX_SETUP:\n+ tmpValG0 |= (1 << USB_MCX_SETUP_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_IN:\n+ tmpValG0 |= (1 << USB_MCX_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_OUT:\n+ tmpValG0 |= (1 << USB_MCX_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_COMFAIL:\n+ tmpValG0 |= (1 << USB_MCX_COMFAIL_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_COMABORT:\n+ tmpValG0 |= (1 << USB_MCX_COMABORT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_OUT:\n+ tmpValG1 |= (1 << USB_MF0_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_SPK:\n+ tmpValG1 |= (1 << USB_MF0_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_OUT:\n+ tmpValG1 |= (1 << USB_MF1_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_SPK:\n+ tmpValG1 |= (1 << USB_MF1_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_OUT:\n+ tmpValG1 |= (1 << USB_MF2_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_SPK:\n+ tmpValG1 |= (1 << USB_MF2_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_OUT:\n+ tmpValG1 |= (1 << USB_MF3_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_SPK:\n+ tmpValG1 |= (1 << USB_MF3_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_IN:\n+ tmpValG1 |= (1 << USB_MF0_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_IN:\n+ tmpValG1 |= (1 << USB_MF1_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_IN:\n+ tmpValG1 |= (1 << USB_MF2_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_IN:\n+ tmpValG1 |= (1 << USB_MF3_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RESET:\n+ tmpValG2 |= (1 << USB_MUSBRST_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_SUSPEND:\n+ tmpValG2 |= (1 << USB_MSUSP_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RESUME:\n+ tmpValG2 |= (1 << USB_MRESM_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_TX0BYTE:\n+ tmpValG2 |= (1 << USB_MTX0BYTE_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RX0BYTE:\n+ tmpValG2 |= (1 << USB_MRX0BYTE_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_DMA_CMPLT:\n+ tmpValG2 |= (1 << USB_MDMA_CMPLT_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_DMA_ERROR:\n+ tmpValG2 |= (1 << USB_MDMA_ERROR_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_IDLE:\n+ tmpValG2 |= (1 << USB_MDEV_IDLE_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS:\n+ tmpValG2 |= (1 << USB_MDEV_WAKEUP_BYVBUS_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF:\n+ tmpValG3 |= (1 << USB_MVDMA_CMPLT_CXF_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F0:\n+ tmpValG3 |= (1 << USB_MVDMA_CMPLT_F0_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F1:\n+ tmpValG3 |= (1 << USB_MVDMA_CMPLT_F1_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F2:\n+ tmpValG3 |= (1 << USB_MVDMA_CMPLT_F2_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F3:\n+ tmpValG3 |= (1 << USB_MVDMA_CMPLT_F3_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_CXF:\n+ tmpValG3 |= (1 << USB_MVDMA_ERROR_CXF_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F0:\n+ tmpValG3 |= (1 << USB_MVDMA_ERROR_F0_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F1:\n+ tmpValG3 |= (1 << USB_MVDMA_ERROR_F1_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F2:\n+ tmpValG3 |= (1 << USB_MVDMA_ERROR_F2_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F3:\n+ tmpValG3 |= (1 << USB_MVDMA_ERROR_F3_POS);\n+ break;\n+ case USB_SUB_GRP4_INT_L1:\n+ tmpValG4 |= (1 << USB_ML1_INT_POS);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4);\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief USB unmask sub group interrupt\n+ *\n+ * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ...\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType)\n+{\n+ uint64_t val = intType;\n+ uint32_t bit = 0;\n+ uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET);\n+ uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET);\n+ uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET);\n+ uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET);\n+ uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET);\n+\n+ while (0 == arch_ctzll(&val, &bit)) {\n+ val &= ~(((uint64_t)1) << bit);\n+ switch (bit) {\n+ case USB_SUB_GRP0_INT_CX_SETUP:\n+ tmpValG0 &= ~(1 << USB_MCX_SETUP_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_IN:\n+ tmpValG0 &= ~(1 << USB_MCX_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_OUT:\n+ tmpValG0 &= ~(1 << USB_MCX_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_COMFAIL:\n+ tmpValG0 &= ~(1 << USB_MCX_COMFAIL_INT_POS);\n+ break;\n+ case USB_SUB_GRP0_INT_CX_COMABORT:\n+ tmpValG0 &= ~(1 << USB_MCX_COMABORT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_OUT:\n+ tmpValG1 &= ~(1 << USB_MF0_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_SPK:\n+ tmpValG1 &= ~(1 << USB_MF0_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_OUT:\n+ tmpValG1 &= ~(1 << USB_MF1_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_SPK:\n+ tmpValG1 &= ~(1 << USB_MF1_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_OUT:\n+ tmpValG1 &= ~(1 << USB_MF2_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_SPK:\n+ tmpValG1 &= ~(1 << USB_MF2_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_OUT:\n+ tmpValG1 &= ~(1 << USB_MF3_OUT_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_SPK:\n+ tmpValG1 &= ~(1 << USB_MF3_SPK_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F0_IN:\n+ tmpValG1 &= ~(1 << USB_MF0_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F1_IN:\n+ tmpValG1 &= ~(1 << USB_MF1_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F2_IN:\n+ tmpValG1 &= ~(1 << USB_MF2_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP1_INT_F3_IN:\n+ tmpValG1 &= ~(1 << USB_MF3_IN_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RESET:\n+ tmpValG2 &= ~(1 << USB_MUSBRST_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_SUSPEND:\n+ tmpValG2 &= ~(1 << USB_MSUSP_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RESUME:\n+ tmpValG2 &= ~(1 << USB_MRESM_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_TX0BYTE:\n+ tmpValG2 &= ~(1 << USB_MTX0BYTE_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_RX0BYTE:\n+ tmpValG2 &= ~(1 << USB_MRX0BYTE_INT_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_DMA_CMPLT:\n+ tmpValG2 &= ~(1 << USB_MDMA_CMPLT_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_DMA_ERROR:\n+ tmpValG2 &= ~(1 << USB_MDMA_ERROR_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_IDLE:\n+ tmpValG2 &= ~(1 << USB_MDEV_IDLE_HOV_POS);\n+ break;\n+ case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS:\n+ tmpValG2 &= ~(1 << USB_MDEV_WAKEUP_BYVBUS_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF:\n+ tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_CXF_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F0:\n+ tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F0_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F1:\n+ tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F1_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F2:\n+ tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F2_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_CMPLT_F3:\n+ tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F3_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_CXF:\n+ tmpValG3 &= ~(1 << USB_MVDMA_ERROR_CXF_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F0:\n+ tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F0_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F1:\n+ tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F1_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F2:\n+ tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F2_POS);\n+ break;\n+ case USB_SUB_GRP3_INT_VDMA_ERROR_F3:\n+ tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F3_POS);\n+ break;\n+ case USB_SUB_GRP4_INT_L1:\n+ tmpValG4 &= ~(1 << USB_ML1_INT_POS);\n+ break;\n+ default:\n+ break;\n+ }\n+ }\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3);\n+ BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4);\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 0 interrupt status\n+ *\n+ * @param None\n+ *\n+ * @return interrupt status\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_0_IntStatus(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_ISG0_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 1 interrupt status\n+ *\n+ * @param None\n+ *\n+ * @return interrupt status\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_1_IntStatus(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_ISG1_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 2 interrupt status\n+ *\n+ * @param None\n+ *\n+ * @return interrupt status\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_2_IntStatus(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_ISG2_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 3 interrupt status\n+ *\n+ * @param None\n+ *\n+ * @return interrupt status\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_3_IntStatus(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_ISG3_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 4 interrupt status\n+ *\n+ * @param None\n+ *\n+ * @return interrupt status\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_4_IntStatus(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_ISG4_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 0 interrupt mask\n+ *\n+ * @param None\n+ *\n+ * @return interrupt mask\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_0_IntMask(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 1 interrupt mask\n+ *\n+ * @param None\n+ *\n+ * @return interrupt mask\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_1_IntMask(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 2 interrupt mask\n+ *\n+ * @param None\n+ *\n+ * @return interrupt mask\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_2_IntMask(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 3 interrupt mask\n+ *\n+ * @param None\n+ *\n+ * @return interrupt mask\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_3_IntMask(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get USB sub group 4 interrupt mask\n+ *\n+ * @param None\n+ *\n+ * @return interrupt mask\n+ *\n+*******************************************************************************/\n+uint32_t USB_Get_Sub_Group_4_IntMask(void)\n+{\n+ return BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB sub group 0 interrupt status\n+ *\n+ * @param clrVal: clear value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal)\n+{\n+ BL_WR_WORD(USB_BASE + USB_DEV_ISG0_OFFSET, clrVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB sub group 1 interrupt status\n+ *\n+ * @param clrVal: clear value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal)\n+{\n+ BL_WR_WORD(USB_BASE + USB_DEV_ISG1_OFFSET, clrVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB sub group 2 interrupt status\n+ *\n+ * @param clrVal: clear value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal)\n+{\n+ BL_WR_WORD(USB_BASE + USB_DEV_ISG2_OFFSET, clrVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB sub group 3 interrupt status\n+ *\n+ * @param clrVal: clear value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal)\n+{\n+ BL_WR_WORD(USB_BASE + USB_DEV_ISG3_OFFSET, clrVal);\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief clear USB sub group 4 interrupt status\n+ *\n+ * @param clrVal: clear value\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal)\n+{\n+ BL_WR_WORD(USB_BASE + USB_DEV_ISG4_OFFSET, clrVal);\n+\n+ return SUCCESS;\n+}\n+\n+/*@} end of group USB_Public_Functions */\n+\n+/*@} end of group USB */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b6c7b11c9850cce42ad5f22228cacee9c31bba01\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c\n@@ -0,0 +1,469 @@\n+/**\n+ ******************************************************************************\n+ * @file bl808_xip_sflash.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"string.h\"\n+#include \"bl808_xip_sflash.h\"\n+\n+/** @addtogroup BL808_Peripheral_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup XIP_SFLASH\n+ * @{\n+ */\n+\n+/** @defgroup XIP_SFLASH_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Private_Macros */\n+\n+/** @defgroup XIP_SFLASH_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Private_Types */\n+\n+/** @defgroup XIP_SFLASH_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Private_Variables */\n+\n+/** @defgroup XIP_SFLASH_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Global_Variables */\n+\n+/** @defgroup XIP_SFLASH_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group XIP_SFLASH_Private_Fun_Declaration */\n+\n+/** @defgroup XIP_SFLASH_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Save flash controller state\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param offset: CPU XIP flash offset pointer\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ /* XIP_SFlash_Delay */\n+ volatile uint32_t i = 32 * 2;\n+\n+ while (i--)\n+ ;\n+\n+ if (bank == SF_CTRL_FLASH_BANK1) {\n+ SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);\n+ }\n+ SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);\n+ /* Exit form continous read for accepting command */\n+ SFlash_Reset_Continue_Read(pFlashCfg);\n+ /* For disable command that is setting register instaed of send command, we need write enable */\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+ /* Enable 32Bits addr mode again in case reset command make it reset */\n+ SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE);\n+ if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {\n+ /* Enable QE again in case reset command make it reset */\n+ SFlash_Qspi_Enable(pFlashCfg);\n+ }\n+ /* Deburst again to make sure */\n+ SFlash_DisableBurstWrap(pFlashCfg);\n+\n+ /* Clear offset setting*/\n+ *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(0, group, bank);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Restore flash controller state\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param offset: CPU XIP flash offset\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t tmp[1];\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank);\n+\n+ if(((pFlashCfg->ioMode>>4)&0x01) == 0) {\n+ if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) {\n+ SFlash_SetBurstWrap(pFlashCfg);\n+ }\n+ }\n+ SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE);\n+ SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ if (bank == SF_CTRL_FLASH_BANK1) {\n+ SF_Ctrl_Sbus2_Revoke_replace();\n+ }\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/*@} end of group XIP_SFLASH_Private_Functions */\n+\n+/** @defgroup XIP_SFLASH_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Erase flash one region\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param startaddr: start address to erase\n+ * @param len: data length to erase\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return stat;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Program flash one region\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param addr: start address to be programed\n+ * @param data: data pointer to be programed\n+ * @param len: data length to be programed\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return stat;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from flash\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param addr: flash read start address\n+ * @param data: data pointer to store data read from flash\n+ * @param len: data length to read\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return stat;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get Flash Jedec ID\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param data: data pointer to store Jedec ID Read from flash\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ SFlash_GetJedecId(pFlashCfg, data);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get Flash Device ID\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param is32BitsAddr: Is flash addr mode in 32-bits\n+ * @param data: data pointer to store Device ID Read from flash\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ SFlash_GetDeviceId(data, is32BitsAddr);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Get Flash Unique ID\n+ *\n+ * @param pFlashCfg: Flash config pointer\n+ * @param data: data pointer to store Device ID Read from flash\n+ * @param idLen: Unique id len\n+ * @param group: CPU group id 0 or 1\n+ * @param bank: Flash bank select\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ BL_Err_Type stat;\n+ uint32_t offset;\n+ uint8_t aesEnable = 0;\n+ SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;\n+\n+ XIP_SFlash_Opt_Enter(&aesEnable);\n+ stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);\n+\n+ if (stat != SUCCESS) {\n+ SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);\n+ } else {\n+ SFlash_GetUniqueId(data, idLen);\n+ XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);\n+ }\n+\n+ XIP_SFlash_Opt_Exit(aesEnable);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief Read data from flash via XIP\n+ *\n+ * @param addr: flash read start address\n+ * @param data: data pointer to store data read from flash\n+ * @param len: data length to read\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK\n+BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len,\n+ uint8_t group, SF_Ctrl_Bank_Select bank)\n+{\n+ uint32_t offset;\n+\n+ addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1);\n+ addr |= BL808_FLASH_XIP_BASE;\n+\n+ offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank);\n+ SF_Ctrl_Set_Flash_Image_Offset(0, group, bank);\n+ /* Flash read */\n+ ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr), len);\n+ SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank);\n+\n+ return SUCCESS;\n+}\n+#endif\n+\n+/****************************************************************************/ /**\n+ * @brief XIP SFlash option save\n+ *\n+ * @param aesEnable: AES enable status pointer\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+__WEAK\n+void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable)\n+{\n+ *aesEnable = SF_Ctrl_Is_AES_Enable();\n+\n+ if (*aesEnable) {\n+ SF_Ctrl_AES_Disable();\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief XIP SFlash option restore\n+ *\n+ * @param aesEnable: AES enable status\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+__WEAK\n+void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable)\n+{\n+ if (aesEnable) {\n+ SF_Ctrl_AES_Enable();\n+ }\n+}\n+\n+/*@} end of group XIP_SFLASH_Public_Functions */\n+\n+/*@} end of group XIP_SFLASH */\n+\n+/*@} end of group BL808_Peripheral_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..05c627927f6f09a72e87e82d0af726a4334613f8\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c\n@@ -0,0 +1,50 @@\n+/**\n+ * @file arm_dsp_wrapper.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#include \"arm_dsp_wrapper.h\"\n+\n+void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize)\n+{\n+ uint32_t blkCnt = blockSize >> 2u;\n+\n+ float32_t in1 = value;\n+ float32_t in2 = value;\n+ float32_t in3 = value;\n+ float32_t in4 = value;\n+\n+ while (blkCnt > 0u) {\n+ *pDst++ = in1;\n+ *pDst++ = in2;\n+ *pDst++ = in3;\n+ *pDst++ = in4;\n+\n+ blkCnt--;\n+ }\n+\n+ blkCnt = blockSize % 0x4u;\n+\n+ while (blkCnt > 0u) {\n+ *pDst++ = value;\n+ blkCnt--;\n+ }\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..445b22a2c43439c7fe6b4ed1b87c19e4ff015d0c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h\n@@ -0,0 +1,44 @@\n+/**\n+ * @file arm_dsp_wrapper.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#ifndef __MY_MATH_F_H__\n+#define __MY_MATH_F_H__\n+\n+#include \"misc.h\"\n+#include \"math.h\"\n+\n+typedef float float32_t;\n+\n+__INLINE__ float32_t arm_sqrt_f32(float32_t x)\n+{\n+ return sqrtf(x);\n+}\n+\n+__INLINE__ float32_t arm_cos_f32(float32_t x)\n+{\n+ return cosf(x);\n+}\n+\n+void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize);\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9842d6ba928ebf673f97b364dc1a0732eb6c4d8d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c\n@@ -0,0 +1,294 @@\n+/**\n+ * @file drv_device.c\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#include \"drv_device.h\"\n+\n+#define DEVICE_CHECK_PARAM\n+\n+#define dev_open (dev->open)\n+#define dev_close (dev->close)\n+#define dev_read (dev->read)\n+#define dev_write (dev->write)\n+#define dev_control (dev->control)\n+\n+dlist_t device_head = DLIST_OBJECT_INIT(device_head);\n+\n+/**\n+ * This function get device list header\n+ *\n+ * @param None\n+ *\n+ * @return device header\n+ */\n+dlist_t *device_get_list_header(void)\n+{\n+ return &device_head;\n+}\n+\n+/**\n+ * This function registers a device driver with specified name.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param name the device driver's name\n+ * @param flags the capabilities flag of device\n+ *\n+ * @return the error code, DEVICE_EOK on initialization successfully.\n+ */\n+int device_register(struct device *dev, const char *name)\n+{\n+ dlist_t *node;\n+\n+ dlist_for_each(node, &device_head)\n+ {\n+ struct device *dev_obj;\n+ dev_obj = dlist_entry(node, struct device, list);\n+\n+ if (dev_obj == dev) {\n+ return -DEVICE_EEXIST;\n+ }\n+ }\n+\n+ strcpy(dev->name, name);\n+\n+ dlist_insert_after(&device_head, &(dev->list));\n+ dev->status = DEVICE_REGISTERED;\n+ return DEVICE_EOK;\n+}\n+\n+/**\n+ * This function unregisters a device driver with specified name.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param name the device driver's name\n+ * @param flags the capabilities flag of device\n+ *\n+ * @return the error code, DEVICE_EOK on initialization successfully.\n+ */\n+int device_unregister(const char *name)\n+{\n+ struct device *dev = device_find(name);\n+\n+ if (!dev) {\n+ return -DEVICE_ENODEV;\n+ }\n+ dev->status = DEVICE_UNREGISTER;\n+ /* remove from old list */\n+ dlist_remove(&(dev->list));\n+ return DEVICE_EOK;\n+}\n+\n+/**\n+ * This function finds a device driver by specified name.\n+ *\n+ * @param name the device driver's name\n+ *\n+ * @return the registered device driver on successful, or NULL on failure.\n+ */\n+struct device *device_find(const char *name)\n+{\n+ struct device *dev;\n+ dlist_t *node;\n+\n+ dlist_for_each(node, &device_head)\n+ {\n+ dev = dlist_entry(node, struct device, list);\n+\n+ if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) {\n+ return dev;\n+ }\n+ }\n+ return NULL;\n+}\n+\n+/**\n+ * This function will open a device\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param oflag the flags for device open\n+ *\n+ * @return the result\n+ */\n+int device_open(struct device *dev, uint16_t oflag)\n+{\n+#ifdef DEVICE_CHECK_PARAM\n+ int retval = DEVICE_EOK;\n+\n+ if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) {\n+ if (dev_open != NULL) {\n+ retval = dev_open(dev, oflag);\n+ dev->status = DEVICE_OPENED;\n+ dev->oflag |= oflag;\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+#else\n+ return dev_open(dev, oflag);\n+#endif\n+}\n+/**\n+ * This function will close a device\n+ *\n+ * @param dev the pointer of device driver structure\n+ *\n+ * @return the result\n+ */\n+int device_close(struct device *dev)\n+{\n+#ifdef DEVICE_CHECK_PARAM\n+ int retval = DEVICE_EOK;\n+\n+ if (dev->status == DEVICE_OPENED) {\n+ if (dev_close != NULL) {\n+ retval = dev_close(dev);\n+ dev->status = DEVICE_CLOSED;\n+ dev->oflag = 0;\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+#else\n+ return dev_close(dev);\n+#endif\n+}\n+/**\n+ * This function will perform a variety of control functions on devices.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param cmd the command sent to device\n+ * @param arg the argument of command\n+ *\n+ * @return the result\n+ */\n+int device_control(struct device *dev, int cmd, void *args)\n+{\n+#ifdef DEVICE_CHECK_PARAM\n+ int retval = DEVICE_EOK;\n+\n+ if (dev->status > DEVICE_UNREGISTER) {\n+ if (dev_control != NULL) {\n+ retval = dev_control(dev, cmd, args);\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+#else\n+ return dev_control(dev, cmd, args);\n+#endif\n+}\n+/**\n+ * This function will write some data to a device.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param pos the position of written\n+ * @param buffer the data buffer to be written to device\n+ * @param size the size of buffer\n+ *\n+ * @return the actually written size on successful, otherwise negative returned.\n+ */\n+int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)\n+{\n+#ifdef DEVICE_CHECK_PARAM\n+ int retval = DEVICE_EOK;\n+\n+ if (dev->status == DEVICE_OPENED) {\n+ if (dev_write != NULL) {\n+ retval = dev_write(dev, pos, buffer, size);\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+#else\n+ return dev_write(dev, pos, buffer, size);\n+#endif\n+}\n+/**\n+ * This function will read some data from a device.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param pos the position of reading\n+ * @param buffer the data buffer to save read data\n+ * @param size the size of buffer\n+ *\n+ * @return the actually read size on successful, otherwise negative returned.\n+ */\n+int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)\n+{\n+#ifdef DEVICE_CHECK_PARAM\n+ int retval = DEVICE_EOK;\n+\n+ if (dev->status == DEVICE_OPENED) {\n+ if (dev_read != NULL) {\n+ retval = dev_read(dev, pos, buffer, size);\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+#else\n+ return dev_read(dev, pos, buffer, size);\n+#endif\n+}\n+/**\n+ * This function will read some data from a device.\n+ *\n+ * @param dev the pointer of device driver structure\n+ * @param pos the position of reading\n+ * @param buffer the data buffer to save read data\n+ * @param size the size of buffer\n+ *\n+ * @return the actually read size on successful, otherwise negative returned.\n+ */\n+int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event))\n+{\n+ int retval = DEVICE_EOK;\n+\n+ if (dev->status > DEVICE_UNREGISTER) {\n+ if (callback != NULL) {\n+ dev->callback = callback;\n+ } else {\n+ retval = -DEVICE_EFAULT;\n+ }\n+ } else {\n+ retval = -DEVICE_EINVAL;\n+ }\n+\n+ return retval;\n+}\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a7a820f0b15fc4f5397a7d09a660a2b9600ffe36\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h\n@@ -0,0 +1,135 @@\n+/**\n+ * @file drv_device.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef __DRV_DEVICE_H__\n+#define __DRV_DEVICE_H__\n+\n+#include \"drv_list.h\"\n+#include \"stdio.h\"\n+\n+#define DEVICE_NAME_MAX 20 /* max device name*/\n+\n+#define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */\n+#define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */\n+#define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */\n+#define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */\n+#define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */\n+#define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */\n+#define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */\n+\n+#define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */\n+#define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */\n+#define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/\n+#define DEVICE_CTRL_RESUME 0x04 /* resume device */\n+#define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */\n+#define DEVICE_CTRL_CONFIG 0x06 /* config device */\n+#define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */\n+#define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */\n+#define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */\n+#define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */\n+#define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */\n+#define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */\n+#define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */\n+#define DEVICE_CTRL_RESVD1 0x0E\n+#define DEVICE_CTRL_RESVD2 0x0F\n+\n+/*\n+ * POSIX Error codes\n+ */\n+\n+#define DEVICE_EOK 0\n+#define DEVICE_EFAULT 14 /* Bad address */\n+#define DEVICE_EEXIST 17 /* device exists */\n+#define DEVICE_ENODEV 19 /* No such device */\n+#define DEVICE_EINVAL 22 /* Invalid argument */\n+#define DEVICE_ENOSPACE 23 /* No more Device for Allocate */\n+\n+#define __ASSERT_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)\n+\n+#define __ASSERT_LOC(test) \\\n+ __ASSERT_PRINT(\"ASSERTION FAIL [%s] @ %s:%d\\n\", \\\n+ #test, \\\n+ __FILE__, __LINE__)\n+\n+#define DEVICE_ASSERT(test, fmt, ...) \\\n+ do { \\\n+ if (!(test)) { \\\n+ __ASSERT_LOC(test); \\\n+ __ASSERT_PRINT(fmt, ##__VA_ARGS__); \\\n+ } \\\n+ } while (0)\n+\n+enum device_class_type {\n+ DEVICE_CLASS_NONE = 0,\n+ DEVICE_CLASS_GPIO,\n+ DEVICE_CLASS_UART,\n+ DEVICE_CLASS_SPI,\n+ DEVICE_CLASS_I2C,\n+ DEVICE_CLASS_ADC,\n+ DEVICE_CLASS_DAC,\n+ DEVICE_CLASS_DMA,\n+ DEVICE_CLASS_TIMER,\n+ DEVICE_CLASS_PWM,\n+ DEVICE_CLASS_QDEC,\n+ DEVICE_CLASS_SDIO,\n+ DEVICE_CLASS_USB,\n+ DEVICE_CLASS_RMII,\n+ DEVICE_CLASS_I2S,\n+ DEVICE_CLASS_CAMERA,\n+ DEVICE_CLASS_SEC_HASH,\n+ DEVICE_CLASS_KEYSCAN,\n+};\n+\n+enum device_status_type {\n+ DEVICE_UNREGISTER = 0,\n+ DEVICE_REGISTERED,\n+ DEVICE_OPENED,\n+ DEVICE_CLOSED\n+};\n+\n+struct device {\n+ char name[DEVICE_NAME_MAX]; /*name of device */\n+ dlist_t list; /*list node of device */\n+ enum device_status_type status; /*status of device */\n+ enum device_class_type type; /*type of device */\n+ uint16_t oflag; /*oflag of device */\n+\n+ int (*open)(struct device *dev, uint16_t oflag);\n+ int (*close)(struct device *dev);\n+ int (*control)(struct device *dev, int cmd, void *args);\n+ int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);\n+ int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size);\n+ void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event);\n+ void *handle;\n+};\n+\n+int device_register(struct device *dev, const char *name);\n+int device_unregister(const char *name);\n+struct device *device_find(const char *name);\n+int device_open(struct device *dev, uint16_t oflag);\n+int device_close(struct device *dev);\n+int device_control(struct device *dev, int cmd, void *args);\n+int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);\n+int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size);\n+int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event));\n+dlist_t *device_get_list_header(void);\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c84c8a3f6c338f3aa7ea8e59655810382075e4fd\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h\n@@ -0,0 +1,472 @@\n+/**\n+ * @file drv_list.h\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef __DRV_LIST_H__\n+#define __DRV_LIST_H__\n+\n+#include \"string.h\"\n+#include \"stdint.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * container_of - return the member address of ptr, if the type of ptr is the\n+ * struct type.\n+ */\n+#define container_of(ptr, type, member) \\\n+ ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))\n+\n+/**\n+ * Double List structure\n+ */\n+struct dlist_node {\n+ struct dlist_node *next; /**< point to next node. */\n+ struct dlist_node *prev; /**< point to prev node. */\n+};\n+typedef struct dlist_node dlist_t; /**< Type for lists. */\n+\n+/**\n+ * @brief initialize a list\n+ *\n+ * @param l list to be initialized\n+ */\n+static inline void dlist_init(dlist_t *l)\n+{\n+ l->next = l->prev = l;\n+}\n+\n+/**\n+ * @brief insert a node after a list\n+ *\n+ * @param l list to insert it\n+ * @param n new node to be inserted\n+ */\n+static inline void dlist_insert_after(dlist_t *l, dlist_t *n)\n+{\n+ l->next->prev = n;\n+ n->next = l->next;\n+\n+ l->next = n;\n+ n->prev = l;\n+}\n+\n+/**\n+ * @brief insert a node before a list\n+ *\n+ * @param n new node to be inserted\n+ * @param l list to insert it\n+ */\n+static inline void dlist_insert_before(dlist_t *l, dlist_t *n)\n+{\n+ l->prev->next = n;\n+ n->prev = l->prev;\n+\n+ l->prev = n;\n+ n->next = l;\n+}\n+\n+/**\n+ * @brief remove node from list.\n+ * @param n the node to remove from the list.\n+ */\n+static inline void dlist_remove(dlist_t *n)\n+{\n+ n->next->prev = n->prev;\n+ n->prev->next = n->next;\n+\n+ n->next = n->prev = n;\n+}\n+\n+/**\n+ * @brief move node from list.\n+ * @param n the node to remove from the list.\n+ */\n+static inline void dlist_move_head(dlist_t *l, dlist_t *n)\n+{\n+ dlist_remove(n);\n+ dlist_insert_after(l, n);\n+}\n+\n+/**\n+ * @brief move node from list.\n+ * @param n the node to remove from the list.\n+ */\n+static inline void dlist_move_tail(dlist_t *l, dlist_t *n)\n+{\n+ dlist_remove(n);\n+ dlist_insert_before(l, n);\n+}\n+\n+/**\n+ * @brief tests whether a list is empty\n+ * @param l the list to test.\n+ */\n+static inline int dlist_isempty(const dlist_t *l)\n+{\n+ return l->next == l;\n+}\n+\n+/**\n+ * @brief get the list length\n+ * @param l the list to get.\n+ */\n+static inline unsigned int dlist_len(const dlist_t *l)\n+{\n+ unsigned int len = 0;\n+ const dlist_t *p = l;\n+\n+ while (p->next != l) {\n+ p = p->next;\n+ len++;\n+ }\n+\n+ return len;\n+}\n+\n+/**\n+ * @brief initialize a dlist object\n+ */\n+#define DLIST_OBJECT_INIT(object) \\\n+ { \\\n+ &(object), &(object) \\\n+ }\n+/**\n+ * @brief initialize a dlist object\n+ */\n+#define DLIST_DEFINE(list) \\\n+ dlist_t list = { &(list), &(list) }\n+\n+/**\n+ * dlist_first_entry - get the first element from a list\n+ * @ptr: the list head to take the element from.\n+ * @type: the type of the struct this is embedded in.\n+ * @member: the name of the list_struct within the struct.\n+ *\n+ * Note, that list is expected to be not empty.\n+ */\n+#define dlist_first_entry(ptr, type, member) \\\n+ dlist_entry((ptr)->next, type, member)\n+/**\n+ * dlist_first_entry_or_null - get the first element from a list\n+ * @ptr: the list head to take the element from.\n+ * @type: the type of the struct this is embedded in.\n+ * @member: the name of the list_struct within the struct.\n+ *\n+ * Note, that list is expected to be not empty.\n+ */\n+#define dlist_first_entry_or_null(ptr, type, member) \\\n+ (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member))\n+\n+/**\n+ * @brief get the struct for this entry\n+ * @param node the entry point\n+ * @param type the type of structure\n+ * @param member the name of list in structure\n+ */\n+#define dlist_entry(node, type, member) \\\n+ container_of(node, type, member)\n+\n+/**\n+ * dlist_for_each - iterate over a list\n+ * @pos: the dlist_t * to use as a loop cursor.\n+ * @head: the head for your list.\n+ */\n+#define dlist_for_each(pos, head) \\\n+ for (pos = (head)->next; pos != (head); pos = pos->next)\n+\n+/**\n+ * dlist_for_each_prev - iterate over a list\n+ * @pos: the dlist_t * to use as a loop cursor.\n+ * @head: the head for your list.\n+ */\n+#define dlist_for_each_prev(pos, head) \\\n+ for (pos = (head)->prev; pos != (head); pos = pos->prev)\n+\n+/**\n+ * dlist_for_each_safe - iterate over a list safe against removal of list entry\n+ * @pos: the dlist_t * to use as a loop cursor.\n+ * @n: another dlist_t * to use as temporary storage\n+ * @head: the head for your list.\n+ */\n+#define dlist_for_each_safe(pos, n, head) \\\n+ for (pos = (head)->next, n = pos->next; pos != (head); \\\n+ pos = n, n = pos->next)\n+\n+#define dlist_for_each_prev_safe(pos, n, head) \\\n+ for (pos = (head)->prev, n = pos->prev; pos != (head); \\\n+ pos = n, n = pos->prev)\n+/**\n+ * dlist_for_each_entry - iterate over list of given type\n+ * @pos: the type * to use as a loop cursor.\n+ * @head: the head for your list.\n+ * @member: the name of the list_struct within the struct.\n+ */\n+#define dlist_for_each_entry(pos, head, member) \\\n+ for (pos = dlist_entry((head)->next, typeof(*pos), member); \\\n+ &pos->member != (head); \\\n+ pos = dlist_entry(pos->member.next, typeof(*pos), member))\n+\n+/**\n+ * dlist_for_each_entry_reverse - iterate over list of given type\n+ * @pos: the type * to use as a loop cursor.\n+ * @head: the head for your list.\n+ * @member: the name of the list_struct within the struct.\n+ */\n+#define dlist_for_each_entry_reverse(pos, head, member) \\\n+ for (pos = dlist_entry((head)->prev, typeof(*pos), member); \\\n+ &pos->member != (head); \\\n+ pos = dlist_entry(pos->member.prev, typeof(*pos), member))\n+\n+/**\n+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry\n+ * @pos: the type * to use as a loop cursor.\n+ * @n: another type * to use as temporary storage\n+ * @head: the head for your list.\n+ * @member: the name of the list_struct within the struct.\n+ */\n+#define dlist_for_each_entry_safe(pos, n, head, member) \\\n+ for (pos = dlist_entry((head)->next, typeof(*pos), member), \\\n+ n = dlist_entry(pos->member.next, typeof(*pos), member); \\\n+ &pos->member != (head); \\\n+ pos = n, n = dlist_entry(n->member.next, typeof(*n), member))\n+\n+/**\n+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry\n+ * @pos: the type * to use as a loop cursor.\n+ * @n: another type * to use as temporary storage\n+ * @head: the head for your list.\n+ * @member: the name of the list_struct within the struct.\n+ */\n+#define dlist_for_each_entry_safe_reverse(pos, n, head, member) \\\n+ for (pos = dlist_entry((head)->prev, typeof(*pos), field), \\\n+ n = dlist_entry(pos->member.prev, typeof(*pos), member); \\\n+ &pos->member != (head); \\\n+ pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member))\n+\n+/**\n+ * Single List structure\n+ */\n+struct slist_node {\n+ struct slist_node *next; /**< point to next node. */\n+};\n+typedef struct slist_node slist_t; /**< Type for single list. */\n+\n+/**\n+ * @brief initialize a single list\n+ *\n+ * @param l the single list to be initialized\n+ */\n+static inline void slist_init(slist_t *l)\n+{\n+ l->next = NULL;\n+}\n+\n+static inline void slist_add_head(slist_t *l, slist_t *n)\n+{\n+ n->next = l->next;\n+ l->next = n;\n+}\n+\n+static inline void slist_add_tail(slist_t *l, slist_t *n)\n+{\n+ while (l->next) {\n+ l = l->next;\n+ }\n+\n+ /* append the node to the tail */\n+ l->next = n;\n+ n->next = NULL;\n+}\n+\n+static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n)\n+{\n+ if (!next) {\n+ slist_add_tail(next, l);\n+ return;\n+ }\n+\n+ while (l->next) {\n+ if (l->next == next) {\n+ l->next = n;\n+ n->next = next;\n+ }\n+\n+ l = l->next;\n+ }\n+}\n+\n+static inline slist_t *slist_remove(slist_t *l, slist_t *n)\n+{\n+ /* remove slist head */\n+ while (l->next && l->next != n) {\n+ l = l->next;\n+ }\n+\n+ /* remove node */\n+ if (l->next != (slist_t *)0) {\n+ l->next = l->next->next;\n+ }\n+\n+ return l;\n+}\n+\n+static inline unsigned int slist_len(const slist_t *l)\n+{\n+ unsigned int len = 0;\n+ const slist_t *list = l->next;\n+\n+ while (list != NULL) {\n+ list = list->next;\n+ len++;\n+ }\n+\n+ return len;\n+}\n+\n+static inline unsigned int slist_contains(slist_t *l, slist_t *n)\n+{\n+ while (l->next) {\n+ if (l->next == n) {\n+ return 0;\n+ }\n+\n+ l = l->next;\n+ }\n+\n+ return 1;\n+}\n+\n+static inline slist_t *slist_head(slist_t *l)\n+{\n+ return l->next;\n+}\n+\n+static inline slist_t *slist_tail(slist_t *l)\n+{\n+ while (l->next) {\n+ l = l->next;\n+ }\n+\n+ return l;\n+}\n+\n+static inline slist_t *slist_next(slist_t *n)\n+{\n+ return n->next;\n+}\n+\n+static inline int slist_isempty(slist_t *l)\n+{\n+ return l->next == NULL;\n+}\n+\n+/**\n+ * @brief initialize a slist object\n+ */\n+#define SLIST_OBJECT_INIT(object) \\\n+ { \\\n+ NULL \\\n+ }\n+\n+/**\n+ * @brief initialize a slist object\n+ */\n+#define SLIST_DEFINE(slist) \\\n+ slist_t slist = { NULL }\n+\n+/**\n+ * @brief get the struct for this single list node\n+ * @param node the entry point\n+ * @param type the type of structure\n+ * @param member the name of list in structure\n+ */\n+#define slist_entry(node, type, member) \\\n+ container_of(node, type, member)\n+\n+/**\n+ * slist_first_entry - get the first element from a slist\n+ * @ptr: the slist head to take the element from.\n+ * @type: the type of the struct this is embedded in.\n+ * @member: the name of the slist_struct within the struct.\n+ *\n+ * Note, that slist is expected to be not empty.\n+ */\n+#define slist_first_entry(ptr, type, member) \\\n+ slist_entry((ptr)->next, type, member)\n+\n+/**\n+ * slist_tail_entry - get the tail element from a slist\n+ * @ptr: the slist head to take the element from.\n+ * @type: the type of the struct this is embedded in.\n+ * @member: the name of the slist_struct within the struct.\n+ *\n+ * Note, that slist is expected to be not empty.\n+ */\n+#define slist_tail_entry(ptr, type, member) \\\n+ slist_entry(slist_tail(ptr), type, member)\n+\n+/**\n+ * slist_first_entry_or_null - get the first element from a slist\n+ * @ptr: the slist head to take the element from.\n+ * @type: the type of the struct this is embedded in.\n+ * @member: the name of the slist_struct within the struct.\n+ *\n+ * Note, that slist is expected to be not empty.\n+ */\n+#define slist_first_entry_or_null(ptr, type, member) \\\n+ (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member))\n+\n+/**\n+ * slist_for_each - iterate over a single list\n+ * @pos: the slist_t * to use as a loop cursor.\n+ * @head: the head for your single list.\n+ */\n+#define slist_for_each(pos, head) \\\n+ for (pos = (head)->next; pos != NULL; pos = pos->next)\n+\n+#define slist_for_each_safe(pos, next, head) \\\n+ for (pos = (head)->next, next = pos->next; pos; \\\n+ pos = next, next = pos->next)\n+\n+/**\n+ * slist_for_each_entry - iterate over single list of given type\n+ * @pos: the type * to use as a loop cursor.\n+ * @head: the head for your single list.\n+ * @member: the name of the list_struct within the struct.\n+ */\n+#define slist_for_each_entry(pos, head, member) \\\n+ for (pos = slist_entry((head)->next, typeof(*pos), member); \\\n+ &pos->member != (NULL); \\\n+ pos = slist_entry(pos->member.next, typeof(*pos), member))\n+\n+#define slist_for_each_entry_safe(pos, n, head, member) \\\n+ for (pos = slist_entry((head)->next, typeof(*pos), member), \\\n+ n = slist_entry(pos->member.next, typeof(*pos), member); \\\n+ &pos->member != (NULL); \\\n+ pos = n, n = slist_entry(pos->member.next, typeof(*pos), member))\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5e053f259744636724e0397fe97c5287d09d8441\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c\n@@ -0,0 +1,421 @@\n+/**\n+ * @file drv_mmheap.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#include \"drv_mmheap.h\"\n+\n+#define MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT 8\n+#define MEM_MANAGE_BITS_PER_BYTE 8\n+#define MEM_MANAGE_MEM_STRUCT_SIZE mmheap_align_up(sizeof(struct heap_node), MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT)\n+#define MEM_MANAGE_MINUM_MEM_SIZE (MEM_MANAGE_MEM_STRUCT_SIZE << 1)\n+#define MEM_MANAGE_ALLOCA_LABAL ((size_t)((size_t)1 << (sizeof(size_t) * MEM_MANAGE_BITS_PER_BYTE - 1)))\n+\n+static inline size_t mmheap_align_down(size_t data, size_t align_byte)\n+{\n+ return data & ~(align_byte - 1);\n+}\n+\n+static inline size_t mmheap_align_up(size_t data, size_t align_byte)\n+{\n+ return (data + align_byte - 1) & ~(align_byte - 1);\n+}\n+\n+static inline struct heap_node *mmheap_addr_sub(const void *addr)\n+{\n+ return (struct heap_node *)((const uint8_t *)addr - MEM_MANAGE_MEM_STRUCT_SIZE);\n+}\n+\n+static inline void *mmheap_addr_add(const struct heap_node *mem_node)\n+{\n+ return (void *)((const uint8_t *)mem_node + MEM_MANAGE_MEM_STRUCT_SIZE);\n+}\n+\n+/**\n+ * @brief mmheap_insert_node_to_freelist\n+ *\n+ * @param pRoot\n+ * @param pNode\n+ */\n+static inline void mmheap_insert_node_to_freelist(struct heap_info *pRoot, struct heap_node *pNode)\n+{\n+ struct heap_node *pPriv_Node;\n+ struct heap_node *pNext_Node;\n+ /*Find the node with an address similar to pNode*/\n+ for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pNode; pPriv_Node = pPriv_Node->next_node) {\n+ }\n+\n+ pNext_Node = pPriv_Node->next_node;\n+ /*Try to merge the pNode with the previous block*/\n+ if ((uint8_t *)mmheap_addr_add(pPriv_Node) + pPriv_Node->mem_size == (uint8_t *)pNode) {\n+ if (pPriv_Node != pRoot->pStart) { /*can merge if not start block*/\n+ pPriv_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNode->mem_size;\n+ pNode = pPriv_Node;\n+ } else {\n+ /*The latter is not merged if it is a Start block to avoid wasting memory*/\n+ pRoot->pStart->next_node = pNode;\n+ }\n+ } else {\n+ /*Insert directly into the free single-chain table when merging is not possible*/\n+ pPriv_Node->next_node = pNode;\n+ }\n+ /*Try to merge the pNode with the next block*/\n+ if ((uint8_t *)mmheap_addr_add(pNode) + pNode->mem_size == (uint8_t *)pNext_Node) {\n+ if (pNext_Node != pRoot->pEnd) {\n+ pNode->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size;\n+ pNode->next_node = pNext_Node->next_node;\n+ } else {\n+ pNode->next_node = pRoot->pEnd;\n+ }\n+ } else {\n+ /*Insert directly into the free single-chain table when merging is not possible*/\n+ pNode->next_node = pNext_Node;\n+ }\n+}\n+\n+/**\n+ * @brief mmheap_get_state\n+ *\n+ * @param pRoot\n+ * @param pState\n+ */\n+void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState)\n+{\n+ MMHEAP_ASSERT(pRoot->pStart != NULL);\n+ MMHEAP_ASSERT(pRoot->pEnd != NULL);\n+ pState->max_node_size = pRoot->pStart->next_node->mem_size;\n+ pState->min_node_size = pRoot->pStart->next_node->mem_size;\n+ pState->remain_size = 0;\n+ pState->free_node_num = 0;\n+ MMHEAP_LOCK();\n+ for (struct heap_node *pNode = pRoot->pStart->next_node; pNode->next_node != NULL; pNode = pNode->next_node) {\n+ pState->remain_size += pNode->mem_size;\n+ pState->free_node_num++;\n+ if (pNode->mem_size > pState->max_node_size)\n+ pState->max_node_size = pNode->mem_size;\n+ if (pNode->mem_size < pState->min_node_size)\n+ pState->min_node_size = pNode->mem_size;\n+ }\n+ MMHEAP_UNLOCK();\n+}\n+/**\n+ * @brief mmheap_align_alloc\n+ *\n+ * @param pRoot\n+ * @param align_size\n+ * @param want_size\n+ * @return void*\n+ */\n+void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size)\n+{\n+ void *pReturn = NULL;\n+ struct heap_node *pPriv_Node, *pNow_Node;\n+\n+ MMHEAP_ASSERT(pRoot->pStart != NULL);\n+ MMHEAP_ASSERT(pRoot->pEnd != NULL);\n+\n+ if (want_size == 0) {\n+ return NULL;\n+ }\n+\n+ if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) {\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+\n+ if (align_size & (align_size - 1)) {\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+\n+ MMHEAP_LOCK();\n+ if (want_size < MEM_MANAGE_MINUM_MEM_SIZE)\n+ want_size = MEM_MANAGE_MINUM_MEM_SIZE;\n+ if (align_size < MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT)\n+ align_size = MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT;\n+\n+ want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);\n+\n+ pPriv_Node = pRoot->pStart;\n+ pNow_Node = pRoot->pStart->next_node;\n+\n+ while (pNow_Node->next_node != NULL) {\n+ if (pNow_Node->mem_size >= want_size + MEM_MANAGE_MEM_STRUCT_SIZE) {\n+ size_t use_align_size;\n+ size_t new_size;\n+ pReturn = (void *)mmheap_align_up((size_t)mmheap_addr_add(pNow_Node), align_size); /*Calculate the aligned address*/\n+ use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node); /*Calculate the memory consumed by the alignment*/\n+ if (use_align_size != 0) { /*if Memory misalignment*/\n+ if (use_align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*The unaligned value is too small*/\n+ pReturn = (void *)mmheap_align_up(\n+ (size_t)mmheap_addr_add(pNow_Node) + MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE, align_size);\n+ use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node);\n+ }\n+ if (use_align_size <= pNow_Node->mem_size) {\n+ new_size = pNow_Node->mem_size - use_align_size; /*Calculate the remaining memory size by removing the memory consumed by alignment*/\n+ if (new_size >= want_size) { /*Meet the conditions for distribution*/\n+ struct heap_node *pNew_Node = mmheap_addr_sub(pReturn);\n+ pNow_Node->mem_size -= new_size + MEM_MANAGE_MEM_STRUCT_SIZE; /*Split Node*/\n+ pNew_Node->mem_size = new_size; /*The new node is also not in the free chain and does not need to be discharged from the free chain*/\n+ pNew_Node->next_node = NULL;\n+ pNow_Node = pNew_Node;\n+ break;\n+ }\n+ }\n+ } else { /*Memory is directly aligned*/\n+ pPriv_Node->next_node = pNow_Node->next_node;\n+ pNow_Node->next_node = NULL;\n+ break;\n+ }\n+ }\n+ pPriv_Node = pNow_Node;\n+ pNow_Node = pNow_Node->next_node;\n+ }\n+\n+ if (pNow_Node == pRoot->pEnd) {\n+ MMHEAP_UNLOCK();\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+\n+ if (pNow_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Node memory is still available*/\n+ struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pNow_Node) + want_size); /*Calculate the address of the node that will be moved into the free chain table*/\n+ pNew_Node->mem_size = pNow_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE;\n+ pNew_Node->next_node = NULL;\n+ pNow_Node->mem_size = want_size;\n+ mmheap_insert_node_to_freelist(pRoot, pNew_Node);\n+ }\n+ pNow_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;\n+ MMHEAP_UNLOCK();\n+ return pReturn;\n+}\n+/**\n+ * @brief mmheap_alloc\n+ *\n+ * @param pRoot\n+ * @param want_size\n+ * @return void*\n+ */\n+void *mmheap_alloc(struct heap_info *pRoot, size_t want_size)\n+{\n+ return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size);\n+}\n+/**\n+ * @brief mmheap_realloc\n+ *\n+ * @param pRoot\n+ * @param src_addr\n+ * @param want_size\n+ * @return void*\n+ */\n+void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size)\n+{\n+ void *pReturn = NULL;\n+ struct heap_node *pNext_Node, *pPriv_Node;\n+ struct heap_node *pSrc_Node;\n+ MMHEAP_ASSERT(pRoot->pStart != NULL);\n+ MMHEAP_ASSERT(pRoot->pEnd != NULL);\n+ if (src_addr == NULL) {\n+ return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size);\n+ }\n+ if (want_size == 0) {\n+ mmheap_free(pRoot, src_addr);\n+ return NULL;\n+ }\n+\n+ MMHEAP_LOCK();\n+ if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) {\n+ MMHEAP_UNLOCK();\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+\n+ pSrc_Node = mmheap_addr_sub(src_addr);\n+\n+ if ((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) {\n+ MMHEAP_UNLOCK();\n+ MMHEAP_ASSERT((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0);\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+\n+ pSrc_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL;\n+ if (pSrc_Node->mem_size >= want_size) {\n+ pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;\n+ pReturn = src_addr;\n+ MMHEAP_UNLOCK();\n+ return pReturn;\n+ }\n+ /*Start looking in the free list for blocks similar to this block*/\n+ for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pSrc_Node; pPriv_Node = pPriv_Node->next_node) {\n+ }\n+ pNext_Node = pPriv_Node->next_node;\n+\n+ if (pNext_Node != pRoot->pEnd &&\n+ ((uint8_t *)src_addr + pSrc_Node->mem_size == (uint8_t *)pNext_Node) &&\n+ (pSrc_Node->mem_size + pNext_Node->mem_size + MEM_MANAGE_MEM_STRUCT_SIZE >= want_size)) {\n+ /*Meet next node non-end, memory contiguous, enough memory left*/\n+ pReturn = src_addr;\n+ pPriv_Node->next_node = pNext_Node->next_node;\n+ pSrc_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size;\n+ want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);\n+ if (pSrc_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Removing the remaining space allocated is enough to open new blocks*/\n+ struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pSrc_Node) + want_size);\n+ pNew_Node->next_node = NULL;\n+ pNew_Node->mem_size = pSrc_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE;\n+ pSrc_Node->mem_size = want_size;\n+ mmheap_insert_node_to_freelist(pRoot, pNew_Node);\n+ }\n+ pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;\n+ MMHEAP_UNLOCK();\n+ } else {\n+ MMHEAP_UNLOCK();\n+ pReturn = mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size);\n+ if (pReturn == NULL) {\n+ pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;\n+ MMHEAP_MALLOC_FAIL();\n+ return NULL;\n+ }\n+ MMHEAP_LOCK();\n+ memcpy(pReturn, src_addr, pSrc_Node->mem_size);\n+ pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;\n+ MMHEAP_UNLOCK();\n+ mmheap_free(pRoot, src_addr);\n+ }\n+ return pReturn;\n+}\n+/**\n+ * @brief\n+ *\n+ * @param pRoot\n+ * @param num\n+ * @param size\n+ * @return void*\n+ */\n+void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size)\n+{\n+ void *pReturn = NULL;\n+\n+ pReturn = (void *)mmheap_alloc(pRoot, size * num);\n+\n+ if (pReturn) {\n+ memset(pReturn, 0, num * size);\n+ }\n+\n+ return pReturn;\n+}\n+/**\n+ * @brief mmheap_free\n+ *\n+ * @param pRoot\n+ * @param addr\n+ */\n+void mmheap_free(struct heap_info *pRoot, void *addr)\n+{\n+ struct heap_node *pFree_Node;\n+ MMHEAP_ASSERT(pRoot->pStart != NULL);\n+ MMHEAP_ASSERT(pRoot->pEnd != NULL);\n+ MMHEAP_LOCK();\n+ if (addr == NULL) {\n+ MMHEAP_UNLOCK();\n+ return;\n+ }\n+ pFree_Node = mmheap_addr_sub(addr);\n+\n+ if ((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) {\n+ MMHEAP_UNLOCK();\n+ MMHEAP_ASSERT((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0);\n+ return;\n+ }\n+\n+ if (pFree_Node->next_node != NULL) {\n+ MMHEAP_UNLOCK();\n+ MMHEAP_ASSERT(pFree_Node->next_node == NULL);\n+ return;\n+ }\n+ pFree_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL;\n+ mmheap_insert_node_to_freelist(pRoot, pFree_Node);\n+ MMHEAP_UNLOCK();\n+}\n+/**\n+ * @brief mmheap_init\n+ *\n+ * @param pRoot\n+ * @param pRegion\n+ */\n+void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRegion)\n+{\n+ struct heap_node *align_addr;\n+ size_t align_size;\n+ struct heap_node *pPriv_node = NULL;\n+\n+ pRoot->total_size = 0;\n+ pRoot->pEnd = NULL;\n+ pRoot->pStart = NULL;\n+\n+ for (; pRegion->addr != NULL; pRegion++) {\n+ align_addr = (struct heap_node *)mmheap_align_up((size_t)pRegion->addr, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); /*Calculate the aligned address*/\n+ if ((uint8_t *)align_addr > pRegion->mem_size + (uint8_t *)pRegion->addr) /*Alignment consumes more memory than the memory area*/\n+ continue;\n+ align_size = pRegion->mem_size - ((uint8_t *)align_addr - (uint8_t *)pRegion->addr); /*Calculate the size of memory left after alignment*/\n+ if (align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) /*if Aligning the remaining memory is too small*/\n+ continue;\n+ align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Find the size of the memory block after removing the table header*/\n+ align_addr->mem_size = align_size;\n+ align_addr->next_node = NULL;\n+ if (pRoot->pStart == NULL) {\n+ pRoot->pStart = align_addr; /*set current addr for start*/\n+ if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*If the remaining blocks are large enough*/\n+ align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Remove the next block of table headers remaining memory size*/\n+ align_addr = (struct heap_node *)((uint8_t *)pRoot->pStart + MEM_MANAGE_MEM_STRUCT_SIZE); //the next block addr\n+ align_addr->mem_size = align_size;\n+ align_addr->next_node = NULL;\n+ pRoot->pStart->mem_size = 0;\n+ pRoot->pStart->next_node = align_addr;\n+ pRoot->total_size = align_addr->mem_size;\n+ } else { /*The memory is too small, and the address of the current memory block is recorded as start*/\n+ pRoot->total_size = 0;\n+ pRoot->pStart->mem_size = 0;\n+ }\n+ } else {\n+ pPriv_node->next_node = align_addr;\n+ pRoot->total_size += align_size;\n+ }\n+ pPriv_node = align_addr;\n+ }\n+ //At this point, pPriv_node is the last block, then place the end of the table at the end of the block, find the address to place the end block, end block is only convenient for traversal, so as small as possible, assigned to MEM_MANAGE_MEM_STRUCT_SIZE\n+ align_addr = (struct heap_node *)mmheap_align_down(\n+ (size_t)mmheap_addr_add(pPriv_node) + pPriv_node->mem_size - MEM_MANAGE_MEM_STRUCT_SIZE, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);\n+ align_size = (uint8_t *)align_addr - (uint8_t *)mmheap_addr_add(pPriv_node); /*Find the remaining size of the previous block after the end block is allocated*/\n+ if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE) {\n+ pRoot->total_size -= pPriv_node->mem_size - align_size; /*Removing memory consumed by allocating end blocks*/\n+ pRoot->pEnd = align_addr; /*Update the address at the end of the list*/\n+ pPriv_node->next_node = align_addr;\n+ pPriv_node->mem_size = align_size;\n+ align_addr->next_node = NULL;\n+ align_addr->mem_size = 0; /*The end block is not involved in memory allocation, so a direct 0 is sufficient*/\n+ } else { /*The last block is too small, directly as the end block*/\n+ pRoot->pEnd = pPriv_node;\n+ pRoot->total_size -= pPriv_node->mem_size;\n+ }\n+ MMHEAP_ASSERT(pRoot->pStart != NULL);\n+ MMHEAP_ASSERT(pRoot->pEnd != NULL);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bfe3e5662158c865b7286c5ee624c4c49954a89c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h\n@@ -0,0 +1,159 @@\n+/**\n+ * @file drv_mmheap.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef __DRV_MMHEAP_H\n+#define __DRV_MMHEAP_H\n+\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <string.h>\n+\n+#ifndef MMHEAP_LOCK\n+#define MMHEAP_LOCK()\n+#endif\n+\n+#ifndef MMHEAP_UNLOCK\n+#define MMHEAP_UNLOCK()\n+#endif\n+\n+#ifndef MMHEAP_ASSERT\n+#define MMHEAP_ASSERT(A) \\\n+ if (!(A)) \\\n+ printf(\"mmheap malloc error:drv_mmheap,%d\\r\\n\", __LINE__)\n+\n+#endif\n+\n+#ifndef MMHEAP_MALLOC_FAIL\n+#define MMHEAP_MALLOC_FAIL() printf(\"mmheap malloc fail:drv_mmheap,%d\\r\\n\", __LINE__)\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+struct heap_region {\n+ void *addr;\n+ size_t mem_size;\n+};\n+\n+struct heap_node {\n+ struct heap_node *next_node;\n+ size_t mem_size;\n+};\n+\n+struct heap_info {\n+ struct heap_node *pStart;\n+ struct heap_node *pEnd;\n+ size_t total_size;\n+};\n+\n+struct heap_state {\n+ size_t remain_size;\n+ size_t free_node_num;\n+ size_t max_node_size;\n+ size_t min_node_size;\n+};\n+\n+void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRigon);\n+/**\n+ * @brief Alloc start address aligned memory from the heap.\n+ * Alloc aligned address and specified size memory from the heap.\n+ *\n+ * @attention\n+ *\n+ * @param[in] pRoot heap info.\n+ * @param[in] align_size address align mask of the memory.\n+ * @param[in] want_size size of the memory.\n+ *\n+ * @return the pointer to the allocated memory.\n+ */\n+void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size);\n+/**\n+ * @brief Alloc memory.\n+ * Allocate size bytes and returns a pointer to the allocated memory.\n+ *\n+ * @attention size should no bigger than MMHEAP_BLK_SIZE_MAX.\n+ *\n+ * @param[in] pRoot heap info.\n+ * @param[in] want_size size of the memory.\n+ *\n+ * @return the pointer to the allocated memory.\n+ */\n+void *mmheap_alloc(struct heap_info *pRoot, size_t want_size);\n+/**\n+ * @brief Realloc memory from the heap.\n+ * Change the size of the memory block pointed to by ptr to size bytes.\n+ *\n+ * @attention\n+ * <ul>\n+ * <li> if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size.\n+ * <li> if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr).\n+ * </ul>\n+ *\n+ * @param[in] pRoot heap info.\n+ * @param[in] src_addr old pointer to the memory space.\n+ * @param[in] want_size new size of the memory space.\n+ *\n+ * @return the new pointer to the allocated memory.\n+ */\n+void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size);\n+/**\n+ * @brief Cealloc memory from the heap.\n+ * Change the size of the memory block pointed to by ptr to size bytes.\n+ *\n+ * @attention\n+ * <ul>\n+ * <li> if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size.\n+ * <li> if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr).\n+ * </ul>\n+ *\n+ * @param[in] pRoot heap info.\n+ * @param[in] num size number.\n+ * @param[in] size new size of the memory space.\n+ *\n+ * @return the new pointer to the allocated memory.\n+ */\n+void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size);\n+/**\n+ * @brief Free the memory.\n+ * Free the memory space pointed to by ptr, which must have been returned by a previous call to mmheap_alloc(), mmheap_aligned_alloc(), or mmheap_realloc().\n+ *\n+ * @attention\n+ *\n+ * @param[in] pRoot heap info.\n+ * @param[in] addr pointer to the memory.\n+ *\n+ * @return None.\n+ */\n+void mmheap_free(struct heap_info *pRoot, void *addr);\n+/**\n+ * @brief get mmheap state\n+ *\n+ * @param pRoot heap info.\n+ * @param pState heap state\n+ */\n+void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState);\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..29489e3c1dc7ecdf9cc1c571a75c7a4454536fff\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h\n@@ -0,0 +1,63 @@\n+#ifndef __COMMON_H\n+#define __COMMON_H\n+\n+/**\n+ * @brief Memory access macro\n+ */\n+#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr)))\n+#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))\n+#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr)))\n+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))\n+#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr)))\n+#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))\n+#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))\n+\n+#define BL_WRWD_TO_BYTEP(p, val) \\\n+ { \\\n+ p[0] = val & 0xff; \\\n+ p[1] = (val >> 8) & 0xff; \\\n+ p[2] = (val >> 16) & 0xff; \\\n+ p[3] = (val >> 24) & 0xff; \\\n+ }\n+/**\n+ * @brief Register access macro\n+ */\n+#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)\n+#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val)\n+#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)\n+#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)\n+#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))\n+#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)\n+#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS)\n+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))\n+#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0)\n+#define BL_DRV_DUMMY \\\n+ { \\\n+ __ASM volatile(\"nop\"); \\\n+ __ASM volatile(\"nop\"); \\\n+ __ASM volatile(\"nop\"); \\\n+ __ASM volatile(\"nop\"); \\\n+ }\n+\n+/* Std driver attribute macro*/\n+#ifndef BFLB_USE_CUSTOM_LD_SECTIONS\n+//#define ATTR_UNI_SYMBOL\n+#define ATTR_STRINGIFY(x) #x\n+#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x)\n+#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__)\n+#define ATTR_CLOCK_SECTION __attribute__((section(\".sclock_rlt_code.\" ATTR_UNI_SYMBOL)))\n+#define ATTR_CLOCK_CONST_SECTION __attribute__((section(\".sclock_rlt_const.\" ATTR_UNI_SYMBOL)))\n+#define ATTR_TCM_SECTION __attribute__((section(\".tcm_code.\" ATTR_UNI_SYMBOL)))\n+#define ATTR_TCM_CONST_SECTION __attribute__((section(\".tcm_const.\" ATTR_UNI_SYMBOL)))\n+#define ATTR_DTCM_SECTION __attribute__((section(\".tcm_data\")))\n+#define ATTR_HSRAM_SECTION __attribute__((section(\".hsram_code\")))\n+#define ATTR_DMA_RAM_SECTION __attribute__((section(\".system_ram\")))\n+#define ATTR_HBN_RAM_SECTION __attribute__((section(\".hbn_ram_code\")))\n+#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(\".hbn_ram_data\")))\n+#define ATTR_EALIGN(x) __attribute__((aligned(x)))\n+#define ATTR_FALLTHROUGH() __attribute__((fallthrough))\n+#define ATTR_USED __attribute__((__used__))\n+#else\n+#include \"bl_ld_sections.h\"\n+#endif /* BFLB_USE_CUSTOM_LD_SECTIONS */\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..844dd00d8657f9f67b34a579ccc7fe0de9c8f65c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h\n@@ -0,0 +1,112 @@\n+#ifndef __GCC_H\n+#define __GCC_H\n+\n+#ifndef __ORDER_BIG_ENDIAN__\n+#define __ORDER_BIG_ENDIAN__ (1)\n+#endif\n+\n+#ifndef __ORDER_LITTLE_ENDIAN__\n+#define __ORDER_LITTLE_ENDIAN__ (2)\n+#endif\n+\n+#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__\n+\n+/* CPP header guards */\n+#ifdef __cplusplus\n+#define EXTERN_C_BEGIN extern \"C\" {\n+#define EXTERN_C_END }\n+#else\n+#define EXTERN_C_BEGIN\n+#define EXTERN_C_END\n+#endif\n+\n+#define __MACRO_BEGIN do {\n+#define __MACRO_END \\\n+ } \\\n+ while (0)\n+\n+#if defined(__GNUC__)\n+#ifndef __ASM\n+#define __ASM __asm\n+#endif\n+#ifndef __INLINE\n+#define __INLINE inline\n+#endif\n+#ifndef __INLINE__\n+#define __INLINE__ inline\n+#endif\n+#ifndef __ALWAYS_INLINE\n+#define __ALWAYS_INLINE inline __attribute__((always_inline))\n+#endif\n+#ifndef __ALWAYS_STATIC_INLINE\n+#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline\n+#endif\n+#ifndef __STATIC_INLINE\n+#define __STATIC_INLINE static inline\n+#endif\n+#ifndef __NO_RETURN\n+#define __NO_RETURN __attribute__((noreturn))\n+#endif\n+#ifndef __USED\n+#define __USED __attribute__((used))\n+#endif\n+#ifndef __UNUSED__\n+#define __UNUSED__ __attribute__((__unused__))\n+#endif\n+#ifndef __WEAK\n+#define __WEAK __attribute__((weak))\n+#endif\n+#ifndef __WEAK__\n+#define __WEAK__ __attribute__((weak))\n+#endif\n+#ifndef __PACKED\n+#define __PACKED __attribute__((packed, aligned(1)))\n+#endif\n+#ifndef __PACKED__\n+#define __PACKED__ __attribute__((packed))\n+#endif\n+#ifndef __PACKED_STRUCT\n+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n+#endif\n+#ifndef __PACKED_UNION\n+#define __PACKED_UNION union __attribute__((packed, aligned(1)))\n+#endif\n+#ifndef __IRQ\n+#define __IRQ __attribute__((interrupt))\n+#endif\n+#ifndef __IRQ_ALIGN64\n+#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64)))\n+#endif\n+#ifndef ALIGN4\n+#define ALIGN4 __attribute((aligned(4)))\n+#endif\n+#ifndef PACK_START\n+#define PACK_START\n+#endif\n+#ifndef PACK_END\n+#define PACK_END __attribute__((packed))\n+#endif\n+#ifndef likely\n+#define likely(x) __builtin_expect(!!(x), 1)\n+#endif\n+#ifndef unlikely\n+#define unlikely(x) __builtin_expect(!!(x), 0)\n+#endif\n+#ifndef __ALIGNED__\n+#define __ALIGNED__(x) __attribute__((aligned(x)))\n+#endif\n+#ifndef SECTION\n+#define SECTION(x) __attribute__((section(x)))\n+#endif\n+#ifndef __CONST__\n+#define __CONST__ __attribute__((__const__))\n+#endif\n+#ifndef __NAKED__\n+#define __NAKED__ __attribute__((naked))\n+#endif\n+#ifndef __deprecated\n+#define __deprecated __attribute__((deprecated))\n+#endif\n+#endif\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3292a68359244dd833b3e70bf902cbefbe6a4f75\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c\n@@ -0,0 +1,253 @@\n+/**\n+ * @file misc.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#include \"misc.h\"\n+\n+#ifndef BFLB_USE_ROM_DRIVER\n+/****************************************************************************/ /**\n+ * @brief Char memcpy\n+ *\n+ * @param dst: Destination\n+ * @param src: Source\n+ * @param n: Count of char\n+ *\n+ * @return Destination pointer\n+ *\n+ *******************************************************************************/\n+__WEAK__ void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n)\n+{\n+ const uint8_t *p = src;\n+ uint8_t *q = dst;\n+\n+ while (n--) {\n+ *q++ = *p++;\n+ }\n+\n+ return dst;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Word memcpy\n+ *\n+ * @param dst: Destination\n+ * @param src: Source\n+ * @param n: Count of words\n+ *\n+ * @return Destination pointer\n+ *\n+ *******************************************************************************/\n+__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n)\n+{\n+ const uint32_t *p = src;\n+ uint32_t *q = dst;\n+\n+ while (n--) {\n+ *q++ = *p++;\n+ }\n+\n+ return dst;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Fast memcpy\n+ *\n+ * @param dst: Destination\n+ * @param src: Source\n+ * @param n: Count of bytes\n+ *\n+ * @return Destination pointer\n+ *\n+ *******************************************************************************/\n+__WEAK__ void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n)\n+{\n+ uint32_t left, done, i = 0;\n+ uint8_t *dst = (uint8_t *)pdst;\n+ uint8_t *src = (uint8_t *)psrc;\n+\n+ if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) {\n+ arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2);\n+ left = n % 4;\n+ done = n - left;\n+\n+ while (i < left) {\n+ dst[done + i] = src[done + i];\n+ i++;\n+ }\n+ } else {\n+ arch_memcpy(dst, src, n);\n+ }\n+\n+ return dst;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief char memset\n+ *\n+ * @param dst: Destination\n+ * @param val: Value to set\n+ * @param n: Count of char\n+ *\n+ * @return Destination pointer\n+ *\n+ *******************************************************************************/\n+__WEAK__ void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n)\n+{\n+ uint8_t *p = (uint8_t *)s;\n+\n+ while (n > 0) {\n+ *p++ = (uint8_t)c;\n+ --n;\n+ }\n+\n+ return s;\n+}\n+/****************************************************************************/ /**\n+ * @brief Word memset\n+ *\n+ * @param dst: Destination\n+ * @param val: Value to set\n+ * @param n: Count of words\n+ *\n+ * @return Destination pointer\n+ *\n+ *******************************************************************************/\n+__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n)\n+{\n+ uint32_t *q = dst;\n+\n+ while (n--) {\n+ *q++ = val;\n+ }\n+\n+ return dst;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief string compare\n+ *\n+ * @param s1: string 1\n+ * @param s2: string 2\n+ * @param n: Count of chars\n+ *\n+ * @return compare result\n+ *\n+ *******************************************************************************/\n+__WEAK__ int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n)\n+{\n+ const unsigned char *c1 = s1, *c2 = s2;\n+ int d = 0;\n+\n+ while (n--) {\n+ d = (int)*c1++ - (int)*c2++;\n+\n+ if (d) {\n+ break;\n+ }\n+ }\n+\n+ return d;\n+}\n+#endif\n+\n+void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length)\n+{\n+ uint8_t *p = (uint8_t *)fifo_addr;\n+ uint8_t *q = data;\n+\n+ while (length--) {\n+ *p = *q++;\n+ }\n+}\n+\n+void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length)\n+{\n+ uint8_t *p = (uint8_t *)fifo_addr;\n+ uint8_t *q = data;\n+\n+ while (length--) {\n+ *q++ = *p;\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief get u64 first number 1 from right to left\n+ *\n+ * @param val: target value\n+ * @param bit: first 1 in bit\n+ *\n+ * @return SUCCESS or ERROR\n+ *\n+*******************************************************************************/\n+int arch_ffsll(uint64_t *val, uint32_t *bit)\n+{\n+ if (!*val) {\n+ return ERROR;\n+ }\n+\n+ *bit = __builtin_ffsll(*val) - 1;\n+ *val &= ~((1ULL) << (*bit));\n+ return 0;\n+}\n+\n+int arch_ctzll(uint64_t *val, uint32_t *bit)\n+{\n+ if (!*val)\n+ return -1;\n+\n+ *bit = __builtin_ctzll(*val);\n+ *val &= ~((1ULL) << (*bit));\n+ return 0;\n+}\n+\n+int arch_clzll(uint64_t *val, uint32_t *bit)\n+{\n+ if (!*val)\n+ return -1;\n+\n+ *bit = __builtin_clzll(*val);\n+ *val &= ~((1ULL) << (*bit));\n+ return 0;\n+}\n+\n+#ifdef DEBUG\n+/*******************************************************************************\n+* @brief Reports the name of the source file and the source line number\n+* where the CHECK_PARAM error has occurred.\n+\n+* @param file: Pointer to the source file name\n+* @param line: assert_param error line source number\n+\n+* @return None\n+*******************************************************************************/\n+void check_failed(uint8_t *file, uint32_t line)\n+{\n+ /* Infinite loop */\n+ while (1)\n+ ;\n+}\n+#endif /* DEBUG */\n+\n+/*@} end of group DRIVER_Public_Functions */\n+\n+/*@} end of group DRIVER_COMMON */\n+\n+/*@} end of group BL602_Periph_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..50ea5cd025eb1ed4c18737558ab7e8392186b45a\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h\n@@ -0,0 +1,131 @@\n+/**\n+ * @file misc.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef _MISC_H\n+#define _MISC_H\n+\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdarg.h>\n+#include <stdbool.h>\n+#include <stdlib.h>\n+#include \"compiler/gcc.h\"\n+#include \"compiler/common.h\"\n+\n+#ifdef BIT\n+#undef BIT\n+#define BIT(n) (1UL << (n))\n+#else\n+#define BIT(n) (1UL << (n))\n+#endif\n+\n+/**\n+ * @brief Null Type definition\n+ */\n+#ifndef NULL\n+#define NULL 0\n+#endif\n+\n+/**\n+ * @brief Error type definition\n+ */\n+typedef enum {\n+ SUCCESS = 0,\n+ ERROR = 1,\n+ TIMEOUT = 2,\n+ INVALID = 3, /* invalid arguments */\n+ NORESC = 4 /* no resource or resource temperary unavailable */\n+} BL_Err_Type;\n+\n+/**\n+ * @brief Functional type definition\n+ */\n+typedef enum {\n+ DISABLE = 0,\n+ ENABLE = 1,\n+} BL_Fun_Type;\n+\n+/**\n+ * @brief Status type definition\n+ */\n+typedef enum {\n+ RESET = 0,\n+ SET = 1,\n+} BL_Sts_Type;\n+\n+/**\n+ * @brief Mask type definition\n+ */\n+typedef enum {\n+ UNMASK = 0,\n+ MASK = 1\n+} BL_Mask_Type;\n+\n+/**\n+ * @brief Logical status Type definition\n+ */\n+typedef enum {\n+ LOGIC_LO = 0,\n+ LOGIC_HI = !LOGIC_LO\n+} LogicalStatus;\n+\n+/**\n+ * @brief Active status Type definition\n+ */\n+typedef enum {\n+ DEACTIVE = 0,\n+ ACTIVE = !DEACTIVE\n+} ActiveStatus;\n+\n+/**\n+ * @brief Interrupt callback function type\n+ */\n+typedef void(intCallback_Type)(void);\n+typedef void (*pFunc)(void);\n+\n+#define ARCH_MemCpy arch_memcpy\n+#define ARCH_MemSet arch_memset\n+#define ARCH_MemCmp arch_memcmp\n+#define ARCH_MemCpy4 arch_memcpy4\n+#define ARCH_MemCpy_Fast arch_memcpy_fast\n+#define ARCH_MemSet4 arch_memset4\n+\n+#ifdef DEBUG\n+void check_failed(uint8_t *file, uint32_t line);\n+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))\n+#else\n+#define CHECK_PARAM(expr) ((void)0)\n+#endif /* DEBUG */\n+\n+void *arch_memcpy(void *dst, const void *src, uint32_t n);\n+void *arch_memset(void *s, uint8_t c, uint32_t n);\n+int arch_memcmp(const void *s1, const void *s2, uint32_t n);\n+uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n);\n+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);\n+uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n);\n+void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length);\n+void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length);\n+int arch_ctzll(uint64_t *val, uint32_t *bit);\n+int arch_clzll(uint64_t *val, uint32_t *bit);\n+int arch_ffsll(uint64_t *val, uint32_t *bit);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..673dcbe88ba9a16acd2cfde6885bb0583f1990a3\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c\n@@ -0,0 +1,544 @@\n+/**\n+ ******************************************************************************\n+ * @file partition.c\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver c file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+\n+#include \"partition.h\"\n+#include \"softcrc.h\"\n+#include \"bflb_platform.h\"\n+\n+/** @addtogroup BFLB_Common_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PARTITION\n+ * @{\n+ */\n+\n+/** @defgroup PARTITION_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group PARTITION_Private_Macros */\n+\n+/** @defgroup PARTITION_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group PARTITION_Private_Types */\n+\n+/** @defgroup PARTITION_Private_Variables\n+ * @{\n+ */\n+p_pt_table_flash_erase gp_pt_table_flash_erase = NULL;\n+p_pt_table_flash_write gp_pt_table_flash_write = NULL;\n+p_pt_table_flash_read gp_pt_table_flash_read = NULL;\n+pt_table_iap_param_type p_iap_param;\n+\n+/*@} end of group PARTITION_Private_Variables */\n+\n+/** @defgroup PARTITION_Global_Variables\n+ * @{\n+ */\n+extern int main(void);\n+\n+/*@} end of group PARTITION_Global_Variables */\n+\n+/** @defgroup PARTITION_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group PARTITION_Private_Fun_Declaration */\n+\n+/** @defgroup PARTITION_Private_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Judge partition table valid\n+ *\n+ * @param ptStuff: Partition table stuff pointer\n+ *\n+ * @return 0 for invalid and 1 for valid\n+ *\n+*******************************************************************************/\n+static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff)\n+{\n+ pt_table_config *pt_table = &pt_stuff->pt_table;\n+ pt_table_entry_config *pt_entries = pt_stuff->pt_entries;\n+ uint32_t *p_crc32;\n+ uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt;\n+\n+ if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) {\n+ if (pt_table->entryCnt > PT_ENTRY_MAX) {\n+ MSG(\"PT Entry Count Error\\r\\n\");\n+ return 0;\n+ }\n+\n+ if (pt_table->crc32 !=\n+ BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) {\n+ MSG(\"PT CRC Error\\r\\n\");\n+ return 0;\n+ }\n+\n+ /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */\n+ p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen);\n+\n+ if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) {\n+ MSG(\"PT Entry CRC Error\\r\\n\");\n+ return 0;\n+ }\n+\n+ return 1;\n+ }\n+\n+ return 0;\n+}\n+\n+/*@} end of group PARTITION_Private_Functions */\n+\n+/** @defgroup PARTITION_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Register partition flash read write erase fucntion\n+ *\n+ * @param erase: Flash erase function\n+ * @param write: Flash write function\n+ * @param read: Flash read function\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read)\n+{\n+ gp_pt_table_flash_erase = erase;\n+ gp_pt_table_flash_write = write;\n+ gp_pt_table_flash_read = read;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get active partition table whole stuff\n+ *\n+ * @param ptStuff[2]: Partition table stuff pointer\n+ *\n+ * @return Active partition table ID\n+ *\n+*******************************************************************************/\n+pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2])\n+{\n+ uint32_t pt_valid[2] = { 0, 0 };\n+ pt_table_id_type activePtID;\n+\n+ if (ptStuff == NULL) {\n+ return PT_TABLE_ID_INVALID;\n+ }\n+\n+ activePtID = PT_TABLE_ID_INVALID;\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config));\n+ pt_valid[0] = pt_table_valid(&ptStuff[0]);\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config));\n+ pt_valid[1] = pt_table_valid(&ptStuff[1]);\n+\n+ if (pt_valid[0] == 1 && pt_valid[1] == 1) {\n+ if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) {\n+ activePtID = PT_TABLE_ID_0;\n+ } else {\n+ activePtID = PT_TABLE_ID_1;\n+ }\n+ } else if (pt_valid[0] == 1) {\n+ activePtID = PT_TABLE_ID_0;\n+ } else if (pt_valid[1] == 1) {\n+ activePtID = PT_TABLE_ID_1;\n+ }\n+\n+ return activePtID;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get partition entry according to entry ID\n+ *\n+ * @param ptStuff: Partition table stuff pointer\n+ * @param type: Type of partition entry\n+ * @param ptEntry: Partition entry pointer to store read data\n+ *\n+ * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER\n+ *\n+*******************************************************************************/\n+pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff,\n+ pt_table_entry_type type,\n+ pt_table_entry_config *pt_entry)\n+{\n+ uint32_t i = 0;\n+\n+ if (pt_stuff == NULL || pt_entry == NULL) {\n+ return PT_ERROR_PARAMETER;\n+ }\n+\n+ for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) {\n+ if (pt_stuff->pt_entries[i].type == type) {\n+ ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config));\n+ return PT_ERROR_SUCCESS;\n+ }\n+ }\n+\n+ return PT_ERROR_ENTRY_NOT_FOUND;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get partition entry according to entry name\n+ *\n+ * @param ptStuff: Partition table stuff pointer\n+ * @param name: Name of partition entry\n+ * @param ptEntry: Partition entry pointer to store read data\n+ *\n+ * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER\n+ *\n+*******************************************************************************/\n+pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff,\n+ uint8_t *name,\n+ pt_table_entry_config *pt_entry)\n+{\n+ uint32_t i = 0;\n+ uint32_t len = strlen((char *)name);\n+\n+ if (pt_stuff == NULL || pt_entry == NULL) {\n+ return PT_ERROR_PARAMETER;\n+ }\n+\n+ for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) {\n+ if (strlen((char *)pt_stuff->pt_entries[i].name) == len &&\n+ memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) {\n+ ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config));\n+ return PT_ERROR_SUCCESS;\n+ }\n+ }\n+\n+ return PT_ERROR_ENTRY_NOT_FOUND;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Update partition entry\n+ *\n+ * @param targetTableID: Target partition table to update\n+ * @param ptStuff: Partition table stuff pointer\n+ * @param ptEntry: Partition entry pointer to update\n+ *\n+ * @return Partition update result\n+ *\n+*******************************************************************************/\n+pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id,\n+ pt_table_stuff_config *pt_stuff,\n+ pt_table_entry_config *pt_entry)\n+{\n+ uint32_t i = 0;\n+ BL_Err_Type ret;\n+ uint32_t write_addr;\n+ uint32_t entries_len;\n+ pt_table_config *pt_table;\n+ pt_table_entry_config *pt_entries;\n+ uint32_t *crc32;\n+\n+ if (pt_entry == NULL || pt_stuff == NULL) {\n+ return PT_ERROR_PARAMETER;\n+ }\n+\n+ pt_table = &pt_stuff->pt_table;\n+ pt_entries = pt_stuff->pt_entries;\n+\n+ if (target_table_id == PT_TABLE_ID_INVALID) {\n+ return PT_ERROR_TABLE_NOT_VALID;\n+ }\n+\n+ if (target_table_id == PT_TABLE_ID_0) {\n+ write_addr = BFLB_PT_TABLE0_ADDRESS;\n+ } else {\n+ write_addr = BFLB_PT_TABLE1_ADDRESS;\n+ }\n+\n+ for (i = 0; i < pt_table->entryCnt; i++) {\n+ if (pt_entries[i].type == pt_entry->type) {\n+ ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config));\n+ break;\n+ }\n+ }\n+\n+ if (i == pt_table->entryCnt) {\n+ /* Not found this entry ,add new one */\n+ if (pt_table->entryCnt < PT_ENTRY_MAX) {\n+ ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config));\n+ pt_table->entryCnt++;\n+ } else {\n+ return PT_ERROR_ENTRY_UPDATE_FAIL;\n+ }\n+ }\n+\n+ /* Prepare write back to flash */\n+ /* Update age */\n+ pt_table->age++;\n+ pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4);\n+\n+ /* Update entries CRC */\n+ entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config);\n+ crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len);\n+ *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len);\n+\n+ /* Write back to flash */\n+ /* Erase flash first */\n+ //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1);\n+ ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4);\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Erase error\\r\\n\");\n+ return PT_ERROR_FALSH_WRITE;\n+ }\n+\n+ /* Write flash */\n+ ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Write error\\r\\n\");\n+ return PT_ERROR_FALSH_WRITE;\n+ }\n+\n+ return PT_ERROR_SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Create partition entry\n+ *\n+ * @param ptID: Partition table ID\n+ *\n+ * @return Partition create result\n+ *\n+*******************************************************************************/\n+pt_table_error_type pt_table_create(pt_table_id_type pt_id)\n+{\n+ uint32_t write_addr;\n+ BL_Err_Type ret;\n+ pt_table_config pt_table;\n+\n+ if (pt_id == PT_TABLE_ID_INVALID) {\n+ return PT_ERROR_TABLE_NOT_VALID;\n+ }\n+\n+ if (pt_id == PT_TABLE_ID_0) {\n+ write_addr = BFLB_PT_TABLE0_ADDRESS;\n+ } else {\n+ write_addr = BFLB_PT_TABLE1_ADDRESS;\n+ }\n+\n+ /* Prepare write back to flash */\n+ pt_table.magicCode = BFLB_PT_MAGIC_CODE;\n+ pt_table.version = 0;\n+ pt_table.entryCnt = 0;\n+ pt_table.age = 0;\n+ pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4);\n+ /* Write back to flash */\n+ //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1);\n+ ret = gp_pt_table_flash_erase(write_addr,sizeof(pt_table_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Erase error\\r\\n\");\n+ return PT_ERROR_FALSH_ERASE;\n+ }\n+\n+ ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Write error\\r\\n\");\n+ return PT_ERROR_FALSH_WRITE;\n+ }\n+\n+ return PT_ERROR_SUCCESS;\n+}\n+\n+pt_table_error_type pt_table_dump(void)\n+{\n+ uint32_t pt_valid[2] = { 0, 0 };\n+ pt_table_stuff_config pt_stuff[2];\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config));\n+ pt_valid[0] = pt_table_valid(&pt_stuff[0]);\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config));\n+ pt_valid[1] = pt_table_valid(&pt_stuff[1]);\n+\n+ if (pt_valid[0]) {\n+ MSG(\"PT TABLE0 valid\\r\\n\");\n+ } else {\n+ MSG(\"PT TABLE0 invalid\\r\\n\");\n+ }\n+\n+ if (pt_valid[1]) {\n+ MSG(\"PT TABLE1 valid\\r\\n\");\n+ } else {\n+ MSG(\"PT TABLE1 invalid\\r\\n\");\n+ }\n+\n+ for (int i = 0; i < 2; i++) {\n+ if (pt_valid[i] == 1) {\n+ MSG(\"ptStuff[%d].pt_table.magicCode 0x%08x\\r\\n\", i, pt_stuff[i].pt_table.magicCode);\n+ MSG(\"ptStuff[%d].pt_table.version 0x%08x\\r\\n\", i, pt_stuff[i].pt_table.version);\n+ MSG(\"ptStuff[%d].pt_table.entryCnt 0x%08x\\r\\n\", i, pt_stuff[i].pt_table.entryCnt);\n+ MSG(\"ptStuff[%d].pt_table.age 0x%08x\\r\\n\", i, pt_stuff[i].pt_table.age);\n+ MSG(\"ptStuff[%d].pt_table.crc32 0x%08x\\r\\n\", i, pt_stuff[i].pt_table.crc32);\n+\n+ for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) {\n+ MSG(\"ptStuff[%d].pt_entries[%d].type 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].type);\n+ MSG(\"ptStuff[%d].pt_entries[%d].device 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].device);\n+ MSG(\"ptStuff[%d].pt_entries[%d].active_index 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].active_index);\n+ MSG(\"ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].start_address[0]);\n+ MSG(\"ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].start_address[1]);\n+ MSG(\"ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].max_len[0]);\n+ MSG(\"ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].max_len[1]);\n+ MSG(\"ptStuff[%d].pt_entries[%d].len 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].len);\n+ MSG(\"ptStuff[%d].pt_entries[%d].age 0x%08x\\r\\n\", i, j, pt_stuff[i].pt_entries[j].age);\n+ }\n+ }\n+ }\n+\n+ return PT_ERROR_SUCCESS;\n+}\n+\n+pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para)\n+{\n+ uint32_t pt_valid[2] = { 0, 0 };\n+ pt_table_stuff_config pt_stuff[2];\n+ uint8_t active_index;\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config));\n+ pt_valid[0] = pt_table_valid(&pt_stuff[0]);\n+\n+ gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config));\n+ pt_valid[1] = pt_table_valid(&pt_stuff[1]);\n+\n+ if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) {\n+ if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) {\n+ active_index = pt_stuff[0].pt_entries[0].active_index;\n+ para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)];\n+ para->inactive_index = !(active_index & 0x01);\n+ para->inactive_table_index = 1;\n+\n+ } else {\n+ active_index = pt_stuff[1].pt_entries[0].active_index;\n+ para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)];\n+ para->inactive_index = !(active_index & 0x01);\n+ para->inactive_table_index = 0;\n+ }\n+\n+ } else if (pt_valid[1] == 1) {\n+ active_index = pt_stuff[1].pt_entries[0].active_index;\n+ para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)];\n+ para->inactive_index = !(active_index & 0x01);\n+ para->inactive_table_index = 0;\n+ } else if (pt_valid[0] == 1) {\n+ active_index = pt_stuff[0].pt_entries[0].active_index;\n+ para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)];\n+ para->inactive_index = !(active_index & 0x01);\n+ para->inactive_table_index = 1;\n+ } else {\n+ return PT_ERROR_TABLE_NOT_VALID;\n+ }\n+\n+ MSG(\"inactive_table_index %d, inactive index %d , IAP start addr %08x \\r\\n\", para->inactive_table_index, para->inactive_index, para->iap_start_addr);\n+ return PT_ERROR_SUCCESS;\n+}\n+\n+pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para)\n+{\n+ pt_table_stuff_config pt_stuff, pt_stuff_write;\n+ int32_t ret;\n+ uint32_t *p_crc32;\n+ uint32_t entries_len;\n+\n+ if (para->inactive_table_index == 1) {\n+ gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config));\n+ } else if (para->inactive_table_index == 0) {\n+ gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config));\n+ }\n+\n+ ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config));\n+ pt_stuff_write.pt_table.age += 1;\n+ pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01);\n+ pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4);\n+ entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt;\n+ //pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len);\n+ p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len);\n+ *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len);\n+\n+ if (para->inactive_table_index == 1) {\n+ //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1);\n+ ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Erase error\\r\\n\");\n+ return PT_ERROR_FALSH_ERASE;\n+ }\n+\n+ ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Write error\\r\\n\");\n+ return PT_ERROR_FALSH_WRITE;\n+ }\n+ } else if (para->inactive_table_index == 0) {\n+ //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1);\n+ ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Erase error\\r\\n\");\n+ return PT_ERROR_FALSH_ERASE;\n+ }\n+\n+ ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config));\n+\n+ if (ret != SUCCESS) {\n+ MSG_ERR(\"Flash Write error\\r\\n\");\n+ return PT_ERROR_FALSH_WRITE;\n+ }\n+ }\n+\n+ MSG(\"Update pt_table suss\\r\\n\");\n+ return PT_ERROR_SUCCESS;\n+}\n+\n+/*@} end of group PARTITION_Public_Functions */\n+\n+/*@} end of group PARTITION */\n+\n+/*@} end of group BFLB_Common_Driver */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f20332dcd8ab5995fcc973cd8f0fadcf3cea5dbc\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h\n@@ -0,0 +1,209 @@\n+/**\n+ ******************************************************************************\n+ * @file partition.h\n+ * @version V1.0\n+ * @date\n+ * @brief This file is the standard driver header file\n+ ******************************************************************************\n+ * @attention\n+ *\n+ * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ ******************************************************************************\n+ */\n+#ifndef __PARTITION_H__\n+#define __PARTITION_H__\n+\n+#include \"misc.h\"\n+\n+/** @addtogroup BFLB_Common_Driver\n+ * @{\n+ */\n+\n+/** @addtogroup PARTITION\n+ * @{\n+ */\n+\n+/** @defgroup PARTITION_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief Partition table error type definition\n+ */\n+typedef enum {\n+ PT_ERROR_SUCCESS, /*!< Partition table error type:success */\n+ PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */\n+ PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */\n+ PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */\n+ PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */\n+ PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */\n+ PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */\n+ PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */\n+ PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */\n+} pt_table_error_type;\n+\n+/**\n+ * @brief Partition id type definition\n+ */\n+typedef enum {\n+ PT_TABLE_ID_0, /*!< Partition table ID 0 */\n+ PT_TABLE_ID_1, /*!< Partition table ID 1 */\n+ PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */\n+} pt_table_id_type;\n+\n+/**\n+ * @brief Partition id type definition\n+ */\n+typedef enum {\n+ PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */\n+ PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */\n+ PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */\n+} pt_table_entry_type;\n+\n+/**\n+ * @brief Partition table config definition\n+ */\n+typedef struct\n+{\n+ uint32_t magicCode; /*!< Partition table magic code */\n+ uint16_t version; /*!< Partition table verdion */\n+ uint16_t entryCnt; /*!< Partition table entry count */\n+ uint32_t age; /*!< Partition table age */\n+ uint32_t crc32; /*!< Partition table CRC32 value */\n+} pt_table_config;\n+\n+/**\n+ * @brief Partition table entry config definition\n+ */\n+typedef struct\n+{\n+ uint8_t type; /*!< Partition entry type */\n+ uint8_t device; /*!< Partition entry device */\n+ uint8_t active_index; /*!< Partition entry active index */\n+ uint8_t name[9]; /*!< Partition entry name */\n+ uint32_t start_address[2]; /*!< Partition entry start address */\n+ uint32_t max_len[2]; /*!< Partition entry max length */\n+ uint32_t len; /*!< Partition entry length */\n+ uint32_t age; /*!< Partition entry age */\n+} pt_table_entry_config;\n+\n+/**\n+ * @brief Partition table stuff config definition\n+ */\n+typedef struct\n+{\n+ pt_table_config pt_table; /*!< Partition table */\n+ pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */\n+ uint32_t crc32; /*!< Partition entries crc32 */\n+} pt_table_stuff_config;\n+\n+/**\n+ * @brief Partition table iap param definition\n+ */\n+typedef struct\n+{\n+ uint32_t iap_start_addr;\n+ uint32_t iap_write_addr;\n+ uint32_t iap_img_len;\n+ uint8_t inactive_index;\n+ uint8_t inactive_table_index;\n+} pt_table_iap_param_type;\n+\n+/*@} end of group PARTITION_Public_Types */\n+\n+/** @defgroup PARTITION_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup pt_table_error_type\n+ * @{\n+ */\n+#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \\\n+ ((type) == PT_ERROR_TABLE_NOT_VALID) || \\\n+ ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \\\n+ ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \\\n+ ((type) == PT_ERROR_CRC32) || \\\n+ ((type) == PT_ERROR_PARAMETER) || \\\n+ ((type) == PT_ERROR_FALSH_READ) || \\\n+ ((type) == PT_ERROR_FALSH_WRITE) || \\\n+ ((type) == PT_ERROR_FALSH_ERASE))\n+\n+/** @defgroup pt_table_id_type\n+ * @{\n+ */\n+#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \\\n+ ((type) == PT_TABLE_ID_1) || \\\n+ ((type) == PT_TABLE_ID_INVALID))\n+\n+/** @defgroup pt_table_entry_type\n+ * @{\n+ */\n+#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \\\n+ ((type) == PT_ENTRY_FW_CPU1) || \\\n+ ((type) == PT_ENTRY_MAX))\n+\n+/*@} end of group PARTITION_Public_Constants */\n+\n+/** @defgroup PARTITION_Public_Macros\n+ * @{\n+ */\n+#define BFLB_PT_TABLE0_ADDRESS 0xE000\n+#define BFLB_PT_TABLE1_ADDRESS 0xF000\n+#define BFLB_PT_MAGIC_CODE 0x54504642\n+typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr);\n+typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len);\n+typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len);\n+\n+/*@} end of group PARTITION_Public_Macros */\n+\n+/** @defgroup PARTITION_Public_Functions\n+ * @{\n+ */\n+void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read);\n+pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]);\n+pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff,\n+ pt_table_entry_type type,\n+ pt_table_entry_config *pt_entry);\n+pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff,\n+ uint8_t *name,\n+ pt_table_entry_config *pt_entry);\n+pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id,\n+ pt_table_stuff_config *pt_stuff,\n+ pt_table_entry_config *pt_entry);\n+pt_table_error_type pt_table_create(pt_table_id_type pt_id);\n+pt_table_error_type pt_table_dump(void);\n+pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para);\n+pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para);\n+\n+/*@} end of group PARTITION_Public_Functions */\n+\n+/*@} end of group PARTITION */\n+\n+/*@} end of group BFLB_Common_Driver */\n+\n+extern pt_table_iap_param_type p_iap_param;\n+\n+#endif /* __PARTITION_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c7d6da85939c5d45d078fdc4b56cde96cdda553e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c\n@@ -0,0 +1,68 @@\n+/**\n+ * @file pid.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#include \"pid.h\"\n+\n+void pid_init(pid_alg_t *pid)\n+{\n+ pid->set_val = 0.0f;\n+ pid->out_val = 0.0f;\n+\n+ pid->last_error = 0.0f;\n+ pid->prev_error = 0.0f;\n+\n+ pid->kp = 3.0f;\n+ pid->ki = 0.0f;\n+ pid->kd = 0.0f;\n+\n+ pid->i_error = 0.0f;\n+ pid->sum_error = 0.0f;\n+\n+ pid->max_val = 32;\n+ pid->min_val = -32;\n+}\n+\n+// standard pid\n+float standard_pid_cal(pid_alg_t *pid, float next_val)\n+{\n+ pid->set_val = next_val;\n+ pid->i_error = pid->set_val - pid->out_val;\n+ pid->sum_error += pid->i_error;\n+ pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error);\n+ pid->last_error = pid->i_error;\n+\n+ return pid->out_val;\n+}\n+\n+// increment pid\n+float increment_pid_cal(pid_alg_t *pid, float next_val)\n+{\n+ pid->set_val = next_val;\n+ pid->i_error = pid->set_val - pid->out_val;\n+ float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error);\n+ pid->out_val += increment;\n+ pid->last_error = pid->prev_error;\n+ pid->prev_error = pid->i_error;\n+\n+ return pid->out_val;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5323790f206155fbfbaa58ddc76092e8bbd2eb53\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h\n@@ -0,0 +1,50 @@\n+/**\n+ * @file pid.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#ifndef __PID_H__\n+#define __PID_H__\n+\n+#include \"stdint.h\"\n+\n+typedef struct pid_alg {\n+ float set_val;\n+ float out_val;\n+\n+ float kp;\n+ float ki;\n+ float kd;\n+\n+ float i_error;\n+ float last_error;\n+ float prev_error;\n+ float sum_error;\n+\n+ int max_val;\n+ int min_val;\n+} pid_alg_t;\n+\n+void pid_init(pid_alg_t *pid);\n+float standard_pid_cal(pid_alg_t *pid, float next_val);\n+float increment_pid_cal(pid_alg_t *pid, float next_val);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ec91c715789c15606ebb6d80f3a389bcd70caad6\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c\n@@ -0,0 +1,679 @@\n+/**\n+ * @file ring_buffer.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#include \"ring_buffer.h\"\n+\n+/** @addtogroup BL_Common_Component\n+ * @{\n+ */\n+\n+/** @addtogroup RING_BUFFER\n+ * @{\n+ */\n+\n+/** @defgroup RING_BUFFER_Private_Macros\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Private_Macros */\n+\n+/** @defgroup RING_BUFFER_Private_Types\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Private_Types */\n+\n+/** @defgroup RING_BUFFER_Private_Fun_Declaration\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Private_Fun_Declaration */\n+\n+/** @defgroup RING_BUFFER_Private_Variables\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Private_Variables */\n+\n+/** @defgroup RING_BUFFER_Global_Variables\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Global_Variables */\n+\n+/** @defgroup RING_BUFFER_Private_Functions\n+ * @{\n+ */\n+\n+/*@} end of group RING_BUFFER_Private_Functions */\n+\n+/** @defgroup RING_BUFFER_Public_Functions\n+ * @{\n+ */\n+\n+/****************************************************************************/ /**\n+ * @brief Ring buffer init function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param buffer: Pointer of ring buffer\n+ * @param size: Size of ring buffer\n+ * @param lockCb: Ring buffer lock callback function pointer\n+ * @param unlockCb: Ring buffer unlock callback function pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb)\n+{\n+ /* Init ring buffer pointer */\n+ rbType->pointer = buffer;\n+\n+ /* Init read/write mirror and index */\n+ rbType->readMirror = 0;\n+ rbType->readIndex = 0;\n+ rbType->writeMirror = 0;\n+ rbType->writeIndex = 0;\n+\n+ /* Set ring buffer size */\n+ rbType->size = size;\n+\n+ /* Set lock and unlock callback function */\n+ rbType->lock = lockCb;\n+ rbType->unlock = unlockCb;\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Ring buffer reset function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ *\n+ * @return SUCCESS\n+ *\n+*******************************************************************************/\n+BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType)\n+{\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Clear read/write mirror and index */\n+ rbType->readMirror = 0;\n+ rbType->readIndex = 0;\n+ rbType->writeMirror = 0;\n+ rbType->writeIndex = 0;\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return SUCCESS;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Use callback function to write ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param length: Length of data want to write\n+ * @param writeCb: Callback function pointer\n+ * @param parameter: Parameter that callback function may use\n+ *\n+ * @return Length of data actually write\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter)\n+{\n+ uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType);\n+\n+ if (writeCb == NULL) {\n+ return 0;\n+ }\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no space for new data */\n+ if (sizeRemained == 0) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ /* Drop part of data when length out of space remained */\n+ if (length > sizeRemained) {\n+ length = sizeRemained;\n+ }\n+\n+ /* Get size of space remained in current mirror */\n+ sizeRemained = rbType->size - rbType->writeIndex;\n+\n+ if (sizeRemained > length) {\n+ /* Space remained is enough for data in current mirror */\n+ writeCb(parameter, &rbType->pointer[rbType->writeIndex], length);\n+ rbType->writeIndex += length;\n+ } else {\n+ /* Data is divided to two parts with different mirror */\n+ writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained);\n+ writeCb(parameter, &rbType->pointer[0], length - sizeRemained);\n+ rbType->writeIndex = length - sizeRemained;\n+ rbType->writeMirror = ~rbType->writeMirror;\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Copy data from data buffer to ring buffer function\n+ *\n+ * @param parameter: Pointer to source pointer\n+ * @param dest: Ring buffer to write\n+ * @param length: Length of data to write\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length)\n+{\n+ uint8_t **src = (uint8_t **)parameter;\n+\n+ ARCH_MemCpy_Fast(dest, *src, length);\n+ *src += length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data to write\n+ * @param length: Length of data\n+ *\n+ * @return Length of data writted actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length)\n+{\n+ return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write 1 byte to ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data to write\n+ *\n+ * @return Length of data writted actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data)\n+{\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no space for new data */\n+ if (!Ring_Buffer_Get_Empty_Length(rbType)) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ rbType->pointer[rbType->writeIndex] = data;\n+\n+ /* Judge to change index and mirror */\n+ if (rbType->writeIndex != (rbType->size - 1)) {\n+ rbType->writeIndex++;\n+ } else {\n+ rbType->writeIndex = 0;\n+ rbType->writeMirror = ~rbType->writeMirror;\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 1;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write ring buffer function, old data will be covered by new data when ring buffer is\n+ * full\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data to write\n+ * @param length: Length of data\n+ *\n+ * @return Length of data writted actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length)\n+{\n+ uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType);\n+ uint32_t indexRemained = rbType->size - rbType->writeIndex;\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Drop extra data when data length is large than size of ring buffer */\n+ if (length > rbType->size) {\n+ data = &data[length - rbType->size];\n+ length = rbType->size;\n+ }\n+\n+ if (indexRemained > length) {\n+ /* Space remained is enough for data in current mirror */\n+ ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length);\n+ rbType->writeIndex += length;\n+\n+ /* Update read index */\n+ if (length > sizeRemained) {\n+ rbType->readIndex = rbType->writeIndex;\n+ }\n+ } else {\n+ /* Data is divided to two parts with different mirror */\n+ ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained);\n+ ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained);\n+ rbType->writeIndex = length - indexRemained;\n+ rbType->writeMirror = ~rbType->writeMirror;\n+\n+ /* Update read index and mirror */\n+ if (length > sizeRemained) {\n+ rbType->readIndex = rbType->writeIndex;\n+ rbType->readMirror = ~rbType->readMirror;\n+ }\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring\n+ * buffer is full\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data to write\n+ *\n+ * @return Length of data writted actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data)\n+{\n+ Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType);\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ rbType->pointer[rbType->writeIndex] = data;\n+\n+ /* Judge to change index and mirror */\n+ if (rbType->writeIndex == rbType->size - 1) {\n+ rbType->writeIndex = 0;\n+ rbType->writeMirror = ~rbType->writeMirror;\n+\n+ /* Update read index and mirror */\n+ if (status == RING_BUFFER_FULL) {\n+ rbType->readIndex = rbType->writeIndex;\n+ rbType->readMirror = ~rbType->readMirror;\n+ }\n+ } else {\n+ rbType->writeIndex++;\n+\n+ /* Update read index */\n+ if (status == RING_BUFFER_FULL) {\n+ rbType->readIndex = rbType->writeIndex;\n+ }\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 1;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Use callback function to read ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param length: Length of data want to read\n+ * @param readCb: Callback function pointer\n+ * @param parameter: Parameter that callback function may use\n+ *\n+ * @return Length of data actually read\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter)\n+{\n+ uint32_t size = Ring_Buffer_Get_Length(rbType);\n+\n+ if (readCb == NULL) {\n+ return 0;\n+ }\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no data */\n+ if (!size) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ /* Ring buffer do not have enough data */\n+ if (size < length) {\n+ length = size;\n+ }\n+\n+ /* Get size of space remained in current mirror */\n+ size = rbType->size - rbType->readIndex;\n+\n+ if (size > length) {\n+ /* Read all data needed */\n+ readCb(parameter, &rbType->pointer[rbType->readIndex], length);\n+ rbType->readIndex += length;\n+ } else {\n+ /* Read two part of data in different mirror */\n+ readCb(parameter, &rbType->pointer[rbType->readIndex], size);\n+ readCb(parameter, &rbType->pointer[0], length - size);\n+ rbType->readIndex = length - size;\n+ rbType->readMirror = ~rbType->readMirror;\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Copy data from ring buffer to data buffer function\n+ *\n+ * @param parameter: Pointer to destination pointer\n+ * @param data: Data buffer to copy\n+ * @param length: Length of data to copy\n+ *\n+ * @return None\n+ *\n+*******************************************************************************/\n+static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length)\n+{\n+ uint8_t **dest = (uint8_t **)parameter;\n+\n+ ARCH_MemCpy_Fast(*dest, data, length);\n+ *dest += length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Buffer for data read\n+ * @param length: Length of data to read\n+ *\n+ * @return Length of data read actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length)\n+{\n+ return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data);\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read 1 byte from ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data read\n+ *\n+ * @return Length of data actually read\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data)\n+{\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no data */\n+ if (!Ring_Buffer_Get_Length(rbType)) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ /* Read data */\n+ *data = rbType->pointer[rbType->readIndex];\n+\n+ /* Update read index and mirror */\n+ if (rbType->readIndex == rbType->size - 1) {\n+ rbType->readIndex = 0;\n+ rbType->readMirror = ~rbType->readMirror;\n+ } else {\n+ rbType->readIndex++;\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 1;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read ring buffer function, do not remove from buffer actually\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Buffer for data read\n+ * @param length: Length of data to read\n+ *\n+ * @return Length of data read actually\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length)\n+{\n+ uint32_t size = Ring_Buffer_Get_Length(rbType);\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no data */\n+ if (!size) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ /* Ring buffer do not have enough data */\n+ if (size < length) {\n+ length = size;\n+ }\n+\n+ /* Get size of space remained in current mirror */\n+ size = rbType->size - rbType->readIndex;\n+\n+ if (size > length) {\n+ /* Read all data needed */\n+ ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length);\n+ } else {\n+ /* Read two part of data in different mirror */\n+ ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size);\n+ ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size);\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return length;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Read 1 byte from ring buffer function, do not remove from buffer actually\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ * @param data: Data read\n+ *\n+ * @return Length of data actually read\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data)\n+{\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Ring buffer has no data */\n+ if (!Ring_Buffer_Get_Length(rbType)) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 0;\n+ }\n+\n+ /* Read data */\n+ *data = rbType->pointer[rbType->readIndex];\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return 1;\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get length of data in ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ *\n+ * @return Length of data\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType)\n+{\n+ uint32_t readMirror = 0;\n+ uint32_t writeMirror = 0;\n+ uint32_t readIndex = 0;\n+ uint32_t writeIndex = 0;\n+ uint32_t size = 0;\n+\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ readMirror = rbType->readMirror;\n+ writeMirror = rbType->writeMirror;\n+ readIndex = rbType->readIndex;\n+ writeIndex = rbType->writeIndex;\n+ size = rbType->size;\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ if (readMirror == writeMirror) {\n+ return writeIndex - readIndex;\n+ } else {\n+ return size - (readIndex - writeIndex);\n+ }\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get space remained in ring buffer function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ *\n+ * @return Length of space remained\n+ *\n+*******************************************************************************/\n+uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType)\n+{\n+ return (rbType->size - Ring_Buffer_Get_Length(rbType));\n+}\n+\n+/****************************************************************************/ /**\n+ * @brief Get ring buffer status function\n+ *\n+ * @param rbType: Ring buffer type structure pointer\n+ *\n+ * @return Status of ring buffer\n+ *\n+*******************************************************************************/\n+Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType)\n+{\n+ if (rbType->lock != NULL) {\n+ rbType->lock();\n+ }\n+\n+ /* Judge empty or full */\n+ if (rbType->readIndex == rbType->writeIndex) {\n+ if (rbType->readMirror == rbType->writeMirror) {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return RING_BUFFER_EMPTY;\n+ } else {\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return RING_BUFFER_FULL;\n+ }\n+ }\n+\n+ if (rbType->unlock != NULL) {\n+ rbType->unlock();\n+ }\n+\n+ return RING_BUFFER_PARTIAL;\n+}\n+\n+/*@} end of group RING_BUFFER_Public_Functions */\n+\n+/*@} end of group RING_BUFFER */\n+\n+/*@} end of group BL_Common_Component */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..dbc66819944c38b27653059a23897139a6b6a432\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h\n@@ -0,0 +1,116 @@\n+/**\n+ * @file ring_buffer.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef __RING_BUFFER_H__\n+#define __RING_BUFFER_H__\n+\n+#include \"misc.h\"\n+\n+/** @addtogroup BL_Common_Component\n+ * @{\n+ */\n+\n+/** @addtogroup RING_BUFFER\n+ * @{\n+ */\n+\n+/** @defgroup RING_BUFFER_Public_Types\n+ * @{\n+ */\n+\n+/**\n+ * @brief Ring buffer status type definition\n+ */\n+typedef enum {\n+ RING_BUFFER_EMPTY, /*!< Ring buffer is empty */\n+ RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */\n+ RING_BUFFER_FULL, /*!< Ring buffer is full */\n+} Ring_Buffer_Status_Type;\n+\n+/**\n+ * @brief Ring buffer structure definition\n+ */\n+typedef struct\n+{\n+ uint8_t *pointer; /*!< Pointer of ring buffer */\n+ uint8_t readMirror; /*!< Read mirror,used to judge empty or full */\n+ uint32_t readIndex; /*!< Index of read address */\n+ uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */\n+ uint32_t writeIndex; /*!< Index of write address */\n+ uint32_t size; /*!< Size of ring buffer */\n+ void (*lock)(void); /*!< Lock ring buffer */\n+ void (*unlock)(void); /*!< Unlock ring buffer */\n+} Ring_Buffer_Type;\n+\n+/*@} end of group RING_BUFFER_Public_Types */\n+\n+/** @defgroup RING_BUFFER_Public_Constants\n+ * @{\n+ */\n+\n+/** @defgroup RING_BUFFER_STATUS_TYPE\n+ * @{\n+ */\n+#define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \\\n+ ((type) == RING_BUFFER_PARTIAL) || \\\n+ ((type) == RING_BUFFER_FULL))\n+\n+/*@} end of group RING_BUFFER_Public_Constants */\n+\n+/** @defgroup RING_BUFFER_Public_Macros\n+ * @{\n+ */\n+typedef void(ringBuffer_Lock_Callback)(void);\n+typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t);\n+typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t);\n+\n+/*@} end of group RING_BUFFER_Public_Macros */\n+\n+/** @defgroup RING_BUFFER_Public_Functions\n+ * @{\n+ */\n+BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb,\n+ ringBuffer_Lock_Callback *unlockCb);\n+BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType);\n+uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb,\n+ void *parameter);\n+uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length);\n+uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data);\n+uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length);\n+uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data);\n+uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb,\n+ void *parameter);\n+uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length);\n+uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data);\n+uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length);\n+uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data);\n+uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType);\n+uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType);\n+Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType);\n+\n+/*@} end of group RING_BUFFER_Public_Functions */\n+\n+/*@} end of group RING_BUFFER */\n+\n+/*@} end of group BL_Common_Component */\n+\n+#endif /* __RING_BUFFER_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4c4cbe55cb518700a698870c959e200d9b008085\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c\n@@ -0,0 +1,194 @@\n+/**\n+ * @file softcrc.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#include \"softcrc.h\"\n+#include \"misc.h\"\n+// ---------------- POPULAR POLYNOMIALS ----------------\n+// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000)\n+// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF)\n+// we use 0x8005 here and\n+\n+const uint8_t chCRCHTalbe[] = {\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+ 0x00, 0xC1, 0x81, 0x40\n+};\n+\n+const uint8_t chCRCLTalbe[] = {\n+ 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,\n+ 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,\n+ 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,\n+ 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,\n+ 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,\n+ 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,\n+ 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,\n+ 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,\n+ 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,\n+ 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,\n+ 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,\n+ 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,\n+ 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,\n+ 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,\n+ 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,\n+ 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,\n+ 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,\n+ 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,\n+ 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,\n+ 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,\n+ 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,\n+ 0x41, 0x81, 0x80, 0x40\n+};\n+\n+uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len)\n+{\n+ uint8_t chCRCHi = 0xFF;\n+ uint8_t chCRCLo = 0xFF;\n+ uint16_t wIndex;\n+ uint8_t *data = (uint8_t *)dataIn;\n+\n+ while (len--) {\n+ wIndex = chCRCLo ^ *data++;\n+ chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];\n+ chCRCHi = chCRCLTalbe[wIndex];\n+ }\n+\n+ return ((chCRCHi << 8) | chCRCLo);\n+}\n+\n+/*\n+x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1\n+*/\n+const uint32_t crc32Tab[256] = {\n+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,\n+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,\n+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,\n+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,\n+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,\n+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,\n+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,\n+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,\n+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,\n+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,\n+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,\n+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,\n+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,\n+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,\n+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,\n+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,\n+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,\n+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,\n+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,\n+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,\n+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,\n+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,\n+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,\n+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,\n+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,\n+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,\n+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,\n+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,\n+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,\n+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,\n+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,\n+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,\n+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,\n+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,\n+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,\n+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,\n+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,\n+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,\n+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,\n+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,\n+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,\n+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,\n+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d\n+};\n+\n+uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len)\n+{\n+ uint32_t crc = 0;\n+ uint8_t *data = (uint8_t *)dataIn;\n+\n+ crc = crc ^ 0xffffffff;\n+\n+ while (len--) {\n+ crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8);\n+ }\n+\n+ return crc ^ 0xffffffff;\n+}\n+\n+/******************************************************************************\n+* Name: CRC-32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1\n+* Poly: 0x4C11DB7\n+* Init: 0xFFFFFFF\n+* Refin: True\n+* Refout: True\n+* Xorout: 0xFFFFFFF\n+* Alias: CRC_32/ADCCP\n+* Use: WinRAR,ect.\n+*****************************************************************************/\n+uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len)\n+{\n+ uint8_t i;\n+ uint32_t crc = ~initial; // Initial value\n+ uint8_t *data=(uint8_t *)dataIn;\n+ \n+ while(len--){\n+ crc ^= *data++; // crc ^= *data; data++;\n+ for (i = 0; i < 8; ++i){\n+ if (crc & 1){\n+ crc = (crc >> 1) ^ 0xEDB88320;// 0xEDB88320= reverse 0x04C11DB7\n+ }else{\n+ crc = (crc >> 1);\n+ }\n+ }\n+ }\n+ return ~crc;\n+}\n+\n+#ifndef BFLB_USE_ROM_DRIVER\n+__WEAK__\n+uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len)\n+{\n+ return BFLB_Soft_CRC32_Ex(0,dataIn,len);\n+}\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c56ab26d23d906eb853b94e51b95d983268cec74\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h\n@@ -0,0 +1,32 @@\n+/**\n+ * @file softcrc.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef __SOFTCRC_H__\n+#define __SOFTCRC_H__\n+\n+#include \"stdint.h\"\n+\n+uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len);\n+uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len);\n+uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3454ff47ae1e8bb35f9573b938063873eec890ee\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c\n@@ -0,0 +1,136 @@\n+/**\n+ * @file timestamp.c\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+\n+#include \"timestamp.h\"\n+\n+#define FOUR_YEAR_DAY ((365 << 2) + 1) //The total number of days in a 4-year cycle\n+#define TIMEZONE (8) //Beijing time Zone adjustment\n+\n+#define SEC_NUM_PER_DAY (24 * 60 * 60)\n+#define SEC_NUM_PER_HOUR (60 * 60)\n+#define SEC_NUM_PER_MINUTE (60)\n+\n+static uint8_t month_day[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //平年\n+static uint8_t Leap_month_day[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //闰年\n+\n+/**\n+* @bref judge if it is a leap year\n+* @para year to be judge\n+* @return 1：leap year 0： nonleap year\n+*/\n+bool check_leap_year(uint16_t year)\n+{\n+ if (year % 4) {\n+ return false;\n+ } else {\n+ if ((year % 100 == 0) && (year % 400 != 0)) {\n+ return false;\n+ } else {\n+ return true;\n+ }\n+ }\n+}\n+\n+void cal_weekday(rtc_time *beijing_time)\n+{\n+\tuint32_t y,m,d,w;\n+\n+\ty=beijing_time->year;\n+\tm=beijing_time->month;\n+\td=beijing_time->day;\n+\n+\tif((m==1)||(m==2))\n+\t{\n+\t\tm+=12;\n+\t\ty--;\n+\t}\n+\t/*\n+\t把一月和二月看成是上一年的十三月和十四月，例：如果是2004-1-10则换算成：2003-13-10来代入公式计算。\n+\t以公元元年为参考，公元元年1月1日为星期一</PRE><PRE>程序如下：\n+\t利用基姆拉尔森计算日期公式 w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)\n+\t*/\n+\tw=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400+1)%7;\n+\n+\tbeijing_time->week=(uint8_t)w;\n+}\n+\n+void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time)\n+{\n+ uint32_t totle_day_num;\n+ uint32_t current_sec_num;\n+\n+ uint16_t remain_day;\n+\n+ uint16_t temp_year;\n+\n+ uint8_t *p = NULL;\n+\n+ totle_day_num = unixtime / SEC_NUM_PER_DAY; //The total number of days\n+ current_sec_num = unixtime % SEC_NUM_PER_DAY; //The number of seconds this day\n+\n+ /* use the number of seconds this day, To calculate hour\\minute\\second */\n+ beijing_time->hour = current_sec_num / SEC_NUM_PER_HOUR;\n+ beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;\n+ beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;\n+\n+ /* Adjust the time zone and check whether the date is +1 */\n+ beijing_time->hour += 8;\n+ if (beijing_time->hour > 23) {\n+ beijing_time->hour -= 24;\n+ totle_day_num++;\n+ }\n+\n+\n+ /* calculate year */\n+ beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle\n+ remain_day = totle_day_num % FOUR_YEAR_DAY; //remaining day nym( < 4 year )\n+\n+ /* calculate year & day */\n+ temp_year = check_leap_year(beijing_time->year) ? 366 : 365;\n+ while (remain_day >= temp_year) {\n+ beijing_time->year++;\n+ remain_day -= temp_year;\n+ temp_year = check_leap_year(beijing_time->year) ? 366 : 365;\n+ }\n+\n+ /* Calculate specific dates(month\\day)*/\n+ p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;\n+ remain_day++; //The actual day starts at 1\n+ beijing_time->month = 0;\n+ while (remain_day > *(p + beijing_time->month)) {\n+ remain_day -= *(p + beijing_time->month);\n+ beijing_time->month++;\n+ }\n+\n+ beijing_time->month++; //The actual month starts at 1\n+ beijing_time->day = remain_day;\n+\n+\n+\n+\t/*利用基姆拉尔森计算日期公式 w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/\n+\n+\tbeijing_time->week = beijing_time->day + 2*beijing_time->month + 3*(beijing_time->month+1)/5 + \\\n+\tbeijing_time->year + beijing_time->year/4 - beijing_time->year/100 +beijing_time->year/400 ;\n+\n+\tcal_weekday(beijing_time);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..dfa95e2d04e03f09c884c5a93b8d46abff20135b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h\n@@ -0,0 +1,45 @@\n+/**\n+ * @file timestamp.h\n+ * @brief\n+ *\n+ * Copyright (c) 2021 Bouffalolab team\n+ *\n+ * Licensed to the Apache Software Foundation (ASF) under one or more\n+ * contributor license agreements. See the NOTICE file distributed with\n+ * this work for additional information regarding copyright ownership. The\n+ * ASF licenses this file to you under the Apache License, Version 2.0 (the\n+ * \"License\"); you may not use this file except in compliance with the\n+ * License. You may obtain a copy of the License at\n+ *\n+ * http://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the\n+ * License for the specific language governing permissions and limitations\n+ * under the License.\n+ *\n+ */\n+#ifndef _TIMESTAMP_\n+#define _TIMESTAMP_\n+\n+#include \"stdint.h\"\n+#include \"stddef.h\"\n+#include \"stdbool.h\"\n+\n+typedef struct _rtc_time_t\n+{\n+\tuint16_t year;\n+\tuint8_t month;\n+\tuint8_t day;\n+\tuint8_t week;\n+\tuint8_t hour;\n+\tuint8_t minute;\n+\tuint8_t second;\n+}rtc_time;\n+\n+void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);\n+\n+#endif\n+\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..da0ef735e203ef39374b312ce738abf733d0f47b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld\n@@ -0,0 +1,350 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+BOOT2_PT_ADDR = 0x62047e00;\n+BOOT2_FLASHCFG_ADDR = 0x62047f14;\n+\n+MEMORY\n+{\n+ flash (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M\n+ xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K \n+ ram_memory (!rx) : ORIGIN = 0x22024000, LENGTH = 48K\n+ ram_wifi (!rx) : ORIGIN = 0x22030000, LENGTH = 96K \n+ ram_psram (!rx) : ORIGIN = 0x54000000, LENGTH = 4M\n+ bugkill (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text.boot :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text.entry)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .bugkiller_command :\n+ {\n+ PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );\n+ PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );\n+ KEEP (*(.static_bugkiller_command))\n+ } > bugkill\n+\n+ .bugkiller :\n+ {\n+ KEEP (*(.bugkiller_code))\n+ KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))\n+ } > bugkill\n+\n+ .psram_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __psram_ram_data_start__ = .;\n+ \n+ *(.psram_data.*)\n+ *liblwip.a:*.o(.text*)\n+ *libwifi.a:*.o(.text*)\n+ *libwifi_manager.a:*.o(.text*)\n+ *libfreertos_e907.a:*.o(.text*)\n+ *libnetutils.a:*.o(.text*)\n+ *libutils.a:*.o(.text*)\n+ *libstartup_bl808.a:debug.o(.text*)\n+\n+ *liblwip.a:*.o(.rodata*)\n+ *libwifi.a:*.o(.rodata*)\n+ *libwifi_manager.a:*.o(.rodata*)\n+ *libfreertos_e907.a:*.o(.rodata*)\n+ *libnetutils.a:*.o(.rodata*)\n+ *libutils.a:*.o(.rodata*)\n+ *libstartup_bl808.a:debug.o(.rodata*)\n+ \n+ . = ALIGN(4);\n+ __psram_ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .text :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text)\n+ *(.text.*)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .rodata :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ } > flash\n+\n+ .itcm_region :\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+\n+ *(.tcm_code)\n+ *(.tcm_code.*)\n+ *(.tcm_const)\n+ *(.tcm_const.*)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_code.*)\n+ *(.sclock_rlt_const)\n+ *(.sclock_rlt_const.*)\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .dtcm_region : \n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .stack_dummy (NOLOAD):\n+ {\n+\tPROVIDE ( _sp_base = . );\n+ . = ALIGN(64);\n+ __stack_protect_start = .;\n+ . = . + 256;\n+ __stack_protect_end = .;\n+ . = . + StackSize;\n+ . = ALIGN(64);\n+\tPROVIDE( _sp_main = . );\n+ } > ram_psram\n+\n+ .system_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .data : \n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+\n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .xrambss (NOLOAD) :\n+ {\n+ __xram_load_addr = .;\n+ \n+ . = ALIGN(4);\n+ __xram_data_start__ = .;\n+\n+ *(.static_xram_region)\n+\n+ __xram_data_end__ = .;\n+ . = ALIGN(4);\n+ } > xram_memory\n+\n+ .ocram_bss_region (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __ocram_bss_start__ = .;\n+\n+ *(.nocache_ram)\n+\n+ . = ALIGN(4);\n+ __ocram_bss_end__ = .;\n+ } > ram_memory\n+\n+ .boot2 (NOLOAD) :\n+ {\n+ PROVIDE ( __boot2_pt_addr_start = . );\n+ *(.bss.boot2_partition_table)\n+ PROVIDE ( __boot2_pt_addr_end = . );\n+\n+ PROVIDE ( __boot2_flashCfg_start = . );\n+ *(.bss.boot2_flashCfg)\n+ PROVIDE ( __boot2_flashCfg_end = . );\n+\n+ } > ram_psram\n+ \n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(.noinit_data*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_psram \n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ _heap_end = .;\n+ } > ram_psram \n+\n+ __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = ADDR(.stack_dummy);\n+\n+ __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);\n+ _heap_size = __HeapLimit - _heap_start;\n+\n+ PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));\n+ PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));\n+ PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));\n+ PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));\n+ PROVIDE( __ram_load_addr = LOADADDR(.data));\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ /*BOOT2 sections*/\n+ PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );\n+ PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );\n+ \n+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );\n+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );\n+ PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );\n+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );\n+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+ PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );\n+ PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );\n+ PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );\n+ PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );\n+ \n+ /* blog */\n+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d2001b4ffd91a5de852b512e669a48cd911da780\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld\n@@ -0,0 +1,252 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ flash (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M\n+ itcm_memory (rx) : ORIGIN = 0xC2024000, LENGTH = 48K\n+ dtcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K\n+ ram_memory (!rx) : ORIGIN = 0x22010000, LENGTH = 64K\n+ ram_wifi (!rx) : ORIGIN = 0x22030000, LENGTH = 160K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .rodata :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ } > flash\n+\n+ .itcm_region :\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+\n+ *(.tcm_code)\n+ *(.tcm_code.*)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory AT > flash\n+\n+ .dtcm_region : \n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory AT > flash\n+\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ . = . + StackSize;\n+ . = ALIGN(4);\n+ } > dtcm_memory\n+\n+ .system_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .data : \n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+\n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+ \n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(.noinit_data*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory \n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ _heap_end = .;\n+ } > ram_memory \n+\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - _heap_start;\n+\n+ PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));\n+ PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));\n+ PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));\n+ PROVIDE( __ram_load_addr = LOADADDR(.data));\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+ \n+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );\n+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );\n+ PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );\n+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );\n+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+ \n+ /* blog */\n+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fe07f7ebe93737fc7b89c1f3fea1466e1a712971\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld\n@@ -0,0 +1,277 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ code_memory (rx) : ORIGIN = 0x22030000, LENGTH = 128K\n+ itcm_memory (rx) : ORIGIN = 0x22028000, LENGTH = 16K\n+ dtcm_memory (rx) : ORIGIN = 0x2202c000, LENGTH = 16K\n+ ram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 32K\n+ ram_wifi (!rx) : ORIGIN = 0x22050000, LENGTH = 32K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ __text_code_start__ = .;\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+ \n+ *(.tcm_code)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ __text_code_end__ = .;\n+ } > code_memory\n+\n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ \n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ . = ALIGN(4);\n+ __itcm_load_addr = .;\n+ \n+ .itcm_region : AT (__itcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory\n+ \n+ __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);\n+ \n+ .dtcm_region : AT (__dtcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ /* *finger_print.o(.data*) */\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory\n+ \n+ /*************************************************************************/\n+ /* .stack_dummy section doesn't contains any symbols. It is only\n+ * used for linker to calculate size of stack sections, and assign\n+ * values to stack symbols later */\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(0x4);\n+ . = . + StackSize;\n+ . = ALIGN(0x4);\n+ } > dtcm_memory\n+ \n+ /* Set stack top to end of RAM, and stack limit move down by\n+ * size of stack_dummy section */\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+ \n+ /* Check if data + heap + stack exceeds RAM limit */\n+ ASSERT(__StackLimit >= __tcm_data_end__, \"region RAM overflowed with stack\")\n+ /*************************************************************************/\n+ \n+ __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);\n+ \n+ .system_ram_data_region : AT (__system_ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);\n+ \n+ /* Data section */\n+ RAM_DATA : AT (__ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+ \n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ \n+ .noinit_data (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __noinit_data_start__ = .;\n+ \n+ *(.noinit_data*)\n+ \n+ . = ALIGN(4);\n+ __noinit_data_end__ = .;\n+ } > ram_memory\n+ \n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory\n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ /*__end__ = .;*/\n+ /*end = __end__;*/\n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ } > ram_memory\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - __HeapBase;\n+}\n+\n+PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );\n+PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );\n+PROVIDE( _ld_ram_size1 = 0);\n+PROVIDE( _ld_ram_addr1 = 0);\n+PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+\n+/* blog */\n+PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+\n+PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..23ff22baef932af007252a0e509b9bd521ebf0a9\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld\n@@ -0,0 +1,288 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ code_memory (rx) : ORIGIN = 0x22030000, LENGTH = 128K\n+ ram_wifi (!rx) : ORIGIN = 0x22050000, LENGTH = 32K\n+ ram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 28K\n+ itcm_memory (rx) : ORIGIN = 0x22027000, LENGTH = 2K\n+ dtcm_memory (rx) : ORIGIN = 0x22027800, LENGTH = 2K\n+ test_ocram (!rx) : ORIGIN = 0x22028000, LENGTH = 32K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ __text_code_start__ = .;\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+ \n+ *(.tcm_code)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ __text_code_end__ = .;\n+ } > code_memory\n+\n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ . = ALIGN(4);\n+ __itcm_load_addr = .;\n+ \n+ .itcm_region : AT (__itcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory\n+ \n+ __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);\n+ \n+ .dtcm_region : AT (__dtcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ /* *finger_print.o(.data*) */\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory\n+ \n+ /*************************************************************************/\n+ /* .stack_dummy section doesn't contains any symbols. It is only\n+ * used for linker to calculate size of stack sections, and assign\n+ * values to stack symbols later */\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(0x4);\n+ . = . + StackSize;\n+ . = ALIGN(0x4);\n+ } > dtcm_memory\n+ \n+ /* Set stack top to end of RAM, and stack limit move down by\n+ * size of stack_dummy section */\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+ \n+ /* Check if data + heap + stack exceeds RAM limit */\n+ ASSERT(__StackLimit >= __tcm_data_end__, \"region RAM overflowed with stack\")\n+ /*************************************************************************/\n+ \n+ __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);\n+ \n+ .system_ram_data_region : AT (__system_ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);\n+ \n+ /* Data section */\n+ RAM_DATA : AT (__ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+ \n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ .noinit_data (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __noinit_data_start__ = .;\n+ \n+ *(.noinit_data*)\n+ \n+ . = ALIGN(4);\n+ __noinit_data_end__ = .;\n+ } > ram_memory\n+ \n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory\n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ /*__end__ = .;*/\n+ /*end = __end__;*/\n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ } > ram_memory\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - __HeapBase;\n+\n+ /* keep my variable even if not referenced */\n+ /* .testmem_at_ocram (NOLOAD) : \n+ {\n+ PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );\n+ PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );\n+ KEEP(*(.testmem_at_ocram))\n+ } > ram_test */\n+\n+ /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);\n+ __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */\n+\n+ __testmem_at_ocram_start_addr = ORIGIN(test_ocram);\n+ __testmem_at_wram_start_addr = ORIGIN(ram_wifi);\n+}\n+\n+PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );\n+PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );\n+PROVIDE( _ld_ram_size1 = 0);\n+PROVIDE( _ld_ram_addr1 = 0);\n+PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+\n+/* blog */\n+PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+\n+PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..abb4c12666d94a431d6528e68c1bee32e91373bf\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld\n@@ -0,0 +1,374 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+BOOT2_PT_ADDR = 0x22057C00;\n+BOOT2_FLASHCFG_ADDR = 0x22057c18;\n+\n+MEMORY\n+{\n+ flash (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M\n+ xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K \n+ ram_memory (!rx) : ORIGIN = 0x22024000, LENGTH = 48K\n+ ram_wifi (!rx) : ORIGIN = 0x22030000, LENGTH = 96K \n+ ram_psram (!rx) : ORIGIN = 0x50000000, LENGTH = 1M\n+ bugkill (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text.boot :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text.startup)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .bugkiller_command :\n+ {\n+ PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );\n+ PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );\n+ KEEP (*(.static_bugkiller_command))\n+ } > bugkill\n+\n+ .bugkiller :\n+ {\n+ KEEP (*(.bugkiller_code))\n+ KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))\n+ } > bugkill\n+\n+ .psram_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __psram_ram_data_start__ = .;\n+ \n+ *(.psram_data.*)\n+ *liblwip.a:*.o(.text*)\n+ *libwifi.a:*.o(.text*)\n+ *libwifi_manager.a:*.o(.text*)\n+ *libfreertos_e907.a:*.o(.text*)\n+ *libnetutils.a:*.o(.text*)\n+ *libutils.a:*.o(.text*)\n+ *libstartup_bl808.a:debug.o(.text*)\n+\n+ *liblwip.a:*.o(.rodata*)\n+ *libwifi.a:*.o(.rodata*)\n+ *libwifi_manager.a:*.o(.rodata*)\n+ *libfreertos_e907.a:*.o(.rodata*)\n+ *libnetutils.a:*.o(.rodata*)\n+ *libutils.a:*.o(.rodata*)\n+ *libstartup_bl808.a:debug.o(.rodata*)\n+ \n+ . = ALIGN(4);\n+ __psram_ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .text :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text)\n+ *(.text.*)\n+\n+ . = ALIGN(4);\n+\n+ /* section information for finsh shell */\n+ . = ALIGN(4);\n+ __fsymtab_start = .;\n+ KEEP(*(FSymTab))\n+ __fsymtab_end = .;\n+ . = ALIGN(4);\n+ __vsymtab_start = .;\n+ KEEP(*(VSymTab))\n+ __vsymtab_end = .;\n+ . = ALIGN(4);\n+\n+ /* section information for modules */\n+ . = ALIGN(4);\n+ __rtmsymtab_start = .;\n+ KEEP(*(RTMSymTab))\n+ __rtmsymtab_end = .;\n+\n+ /* section information for initialization */\n+ . = ALIGN(4);\n+ __rt_init_start = .;\n+ KEEP(*(SORT(.rti_fn*)))\n+ __rt_init_end = .;\n+\n+ } > flash\n+\n+ .rodata :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ } > flash\n+\n+ .itcm_region :\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+\n+ *(.tcm_code)\n+ *(.tcm_code.*)\n+ *(.tcm_const)\n+ *(.tcm_const.*)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_code.*)\n+ *(.sclock_rlt_const)\n+ *(.sclock_rlt_const.*)\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .dtcm_region : \n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .stack_dummy (NOLOAD):\n+ {\n+\tPROVIDE ( _sp_base = . );\n+ . = ALIGN(64);\n+ __stack_protect_start = .;\n+ . = . + 256;\n+ __stack_protect_end = .;\n+ . = . + StackSize;\n+ . = ALIGN(64);\n+\tPROVIDE( _sp_main = . );\n+ } > ram_psram\n+\n+ .system_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .data : \n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+\n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_psram AT > flash\n+\n+ .xrambss (NOLOAD) :\n+ {\n+ __xram_load_addr = .;\n+ \n+ . = ALIGN(4);\n+ __xram_data_start__ = .;\n+\n+ *(.static_xram_region)\n+\n+ __xram_data_end__ = .;\n+ . = ALIGN(4);\n+ } > xram_memory\n+\n+ .ocram_bss_region (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __ocram_bss_start__ = .;\n+\n+ *(.nocache_ram)\n+\n+ . = ALIGN(4);\n+ __ocram_bss_end__ = .;\n+ } > ram_memory\n+\n+ .boot2 (NOLOAD) :\n+ {\n+ PROVIDE ( __boot2_pt_addr_start = . );\n+ *(.bss.boot2_partition_table)\n+ PROVIDE ( __boot2_pt_addr_end = . );\n+\n+ PROVIDE ( __boot2_flashCfg_start = . );\n+ *(.bss.boot2_flashCfg)\n+ PROVIDE ( __boot2_flashCfg_end = . );\n+\n+ } > ram_psram\n+ \n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(.noinit_data*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_psram \n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ _heap_end = .;\n+ } > ram_psram \n+\n+ __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = ADDR(.stack_dummy);\n+\n+ __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);\n+ _heap_size = __HeapLimit - _heap_start;\n+\n+ PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));\n+ PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));\n+ PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));\n+ PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));\n+ PROVIDE( __ram_load_addr = LOADADDR(.data));\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ /*BOOT2 sections*/\n+ PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );\n+ PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );\n+ \n+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );\n+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );\n+ PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );\n+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );\n+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+ PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );\n+ PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );\n+ PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );\n+ PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );\n+ \n+ /* blog */\n+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1a9a7a5105303b21d3861524aa0dff9451546e24\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld\n@@ -0,0 +1,357 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+BOOT2_PT_ADDR = 0x22057C00;\n+BOOT2_FLASHCFG_ADDR = 0x22057c18;\n+\n+MEMORY\n+{\n+ flash (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M\n+ xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K \n+ ram_memory (!rx) : ORIGIN = 0x22024000, LENGTH = 208K\n+ ram_wifi (!rx) : ORIGIN = 0x22058000, LENGTH = 0K\n+ ram_psram (!rx) : ORIGIN = 0x50000000, LENGTH = 1M\n+ bugkill (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text.boot :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text.startup)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .bugkiller_command :\n+ {\n+ PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );\n+ PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );\n+ KEEP (*(.static_bugkiller_command))\n+ } > bugkill\n+\n+ .bugkiller :\n+ {\n+ KEEP (*(.bugkiller_code))\n+ KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))\n+ } > bugkill\n+\n+ .psram_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __psram_ram_data_start__ = .;\n+ \n+ *(.psram_data.*)\n+ *liblwip.a:*.o(.text*)\n+ *libwifi.a:*.o(.text*)\n+ *libwifi_manager.a:*.o(.text*)\n+ *libfreertos_e907.a:*.o(.text*)\n+ *libnetutils.a:*.o(.text*)\n+ *libutils.a:*.o(.text*)\n+ *libstartup_bl808.a:debug.o(.text*)\n+\n+ *liblwip.a:*.o(.rodata*)\n+ *libwifi.a:*.o(.rodata*)\n+ *libwifi_manager.a:*.o(.rodata*)\n+ *libfreertos_e907.a:*.o(.rodata*)\n+ *libnetutils.a:*.o(.rodata*)\n+ *libutils.a:*.o(.rodata*)\n+ *libstartup_bl808.a:debug.o(.rodata*)\n+ \n+ . = ALIGN(4);\n+ __psram_ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .text :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.text)\n+ *(.text.*)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .rodata :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ } > flash\n+\n+ .itcm_region :\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+\n+ *(.tcm_code)\n+ *(.tcm_code.*)\n+ *(.tcm_const)\n+ *(.tcm_const.*)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_code.*)\n+ *(.sclock_rlt_const)\n+ *(.sclock_rlt_const.*)\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .dtcm_region : \n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .system_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .data : \n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+\n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .xrambss (NOLOAD) :\n+ {\n+ __xram_load_addr = .;\n+ \n+ . = ALIGN(4);\n+ __xram_data_start__ = .;\n+\n+ *(.static_xram_region)\n+\n+ __xram_data_end__ = .;\n+ . = ALIGN(4);\n+ } > xram_memory\n+\n+ .ocram_bss_region (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __ocram_bss_start__ = .;\n+\n+ *(.nocache_ram)\n+\n+ . = ALIGN(4);\n+ __ocram_bss_end__ = .;\n+ } > ram_memory\n+\n+ .boot2 (NOLOAD) :\n+ {\n+ PROVIDE ( __boot2_pt_addr_start = . );\n+ *(.bss.boot2_partition_table)\n+ PROVIDE ( __boot2_pt_addr_end = . );\n+\n+ PROVIDE ( __boot2_flashCfg_start = . );\n+ *(.bss.boot2_flashCfg)\n+ PROVIDE ( __boot2_flashCfg_end = . );\n+\n+ } > ram_memory\n+ \n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_memory\n+\n+ .psram_bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ *(.custom_psram_bss*)\n+ . = ALIGN(4);\n+ } > ram_psram\n+\n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(.noinit_data*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory\n+\n+ .stack_dummy (NOLOAD):\n+ {\n+\tPROVIDE ( _sp_base = . );\n+ . = ALIGN(64);\n+ __stack_protect_start = .;\n+ . = . + 256;\n+ __stack_protect_end = .;\n+ . = . + StackSize;\n+ . = ALIGN(64);\n+\tPROVIDE( _sp_main = . );\n+ } > ram_memory\n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ _heap_end = .;\n+ } > ram_memory\n+\n+ __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = ADDR(.stack_dummy);\n+\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - _heap_start;\n+\n+ PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));\n+ PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));\n+ PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));\n+ PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));\n+ PROVIDE( __ram_load_addr = LOADADDR(.data));\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ /*BOOT2 sections*/\n+ PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );\n+ PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );\n+ \n+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );\n+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );\n+ PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );\n+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );\n+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+ PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );\n+ PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );\n+ PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );\n+ PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );\n+ \n+ /* blog */\n+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d2001b4ffd91a5de852b512e669a48cd911da780\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld\n@@ -0,0 +1,252 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ flash (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M\n+ itcm_memory (rx) : ORIGIN = 0xC2024000, LENGTH = 48K\n+ dtcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K\n+ ram_memory (!rx) : ORIGIN = 0x22010000, LENGTH = 64K\n+ ram_wifi (!rx) : ORIGIN = 0x22030000, LENGTH = 160K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+\n+ . = ALIGN(4);\n+ } > flash\n+\n+ .rodata :\n+ {\n+ . = ALIGN(4);\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ } > flash\n+\n+ .itcm_region :\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+\n+ *(.tcm_code)\n+ *(.tcm_code.*)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory AT > flash\n+\n+ .dtcm_region : \n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory AT > flash\n+\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ . = . + StackSize;\n+ . = ALIGN(4);\n+ } > dtcm_memory\n+\n+ .system_ram_data_region : \n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+\n+ .data : \n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+\n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory AT > flash\n+ \n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(.noinit_data*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory \n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ _heap_end = .;\n+ } > ram_memory \n+\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - _heap_start;\n+\n+ PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));\n+ PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));\n+ PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));\n+ PROVIDE( __ram_load_addr = LOADADDR(.data));\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+ \n+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );\n+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );\n+ PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );\n+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );\n+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+ \n+ /* blog */\n+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fe07f7ebe93737fc7b89c1f3fea1466e1a712971\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld\n@@ -0,0 +1,277 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ code_memory (rx) : ORIGIN = 0x22030000, LENGTH = 128K\n+ itcm_memory (rx) : ORIGIN = 0x22028000, LENGTH = 16K\n+ dtcm_memory (rx) : ORIGIN = 0x2202c000, LENGTH = 16K\n+ ram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 32K\n+ ram_wifi (!rx) : ORIGIN = 0x22050000, LENGTH = 32K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ __text_code_start__ = .;\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+ \n+ *(.tcm_code)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ __text_code_end__ = .;\n+ } > code_memory\n+\n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ \n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ . = ALIGN(4);\n+ __itcm_load_addr = .;\n+ \n+ .itcm_region : AT (__itcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory\n+ \n+ __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);\n+ \n+ .dtcm_region : AT (__dtcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ /* *finger_print.o(.data*) */\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory\n+ \n+ /*************************************************************************/\n+ /* .stack_dummy section doesn't contains any symbols. It is only\n+ * used for linker to calculate size of stack sections, and assign\n+ * values to stack symbols later */\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(0x4);\n+ . = . + StackSize;\n+ . = ALIGN(0x4);\n+ } > dtcm_memory\n+ \n+ /* Set stack top to end of RAM, and stack limit move down by\n+ * size of stack_dummy section */\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+ \n+ /* Check if data + heap + stack exceeds RAM limit */\n+ ASSERT(__StackLimit >= __tcm_data_end__, \"region RAM overflowed with stack\")\n+ /*************************************************************************/\n+ \n+ __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);\n+ \n+ .system_ram_data_region : AT (__system_ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);\n+ \n+ /* Data section */\n+ RAM_DATA : AT (__ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+ \n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ \n+ .noinit_data (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __noinit_data_start__ = .;\n+ \n+ *(.noinit_data*)\n+ \n+ . = ALIGN(4);\n+ __noinit_data_end__ = .;\n+ } > ram_memory\n+ \n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory\n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ /*__end__ = .;*/\n+ /*end = __end__;*/\n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ } > ram_memory\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - __HeapBase;\n+}\n+\n+PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );\n+PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );\n+PROVIDE( _ld_ram_size1 = 0);\n+PROVIDE( _ld_ram_addr1 = 0);\n+PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+\n+/* blog */\n+PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+\n+PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..23ff22baef932af007252a0e509b9bd521ebf0a9\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld\n@@ -0,0 +1,288 @@\n+/****************************************************************************************\n+* @file map.txt\n+*\n+* @brief This file is the map file (gnuarm or armgcc).\n+*\n+* Copyright (C) BouffaloLab 2018\n+*\n+****************************************************************************************\n+*/\n+\n+/* configure the CPU type */\n+OUTPUT_ARCH( \"riscv\" )\n+/* link with the standard c library */\n+INPUT(-lc)\n+/* link with the standard GCC library */\n+INPUT(-lgcc)\n+/* configure the entry point */\n+ENTRY(risc_e906_start)\n+\n+StackSize = 0x0400; /* 1KB */\n+\n+MEMORY\n+{\n+ code_memory (rx) : ORIGIN = 0x22030000, LENGTH = 128K\n+ ram_wifi (!rx) : ORIGIN = 0x22050000, LENGTH = 32K\n+ ram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 28K\n+ itcm_memory (rx) : ORIGIN = 0x22027000, LENGTH = 2K\n+ dtcm_memory (rx) : ORIGIN = 0x22027800, LENGTH = 2K\n+ test_ocram (!rx) : ORIGIN = 0x22028000, LENGTH = 32K\n+}\n+\n+SECTIONS\n+{\n+ PROVIDE(__metal_chicken_bit = 0);\n+ \n+ .text :\n+ {\n+ . = ALIGN(4);\n+ __text_code_start__ = .;\n+ \n+ KEEP (*(SORT_NONE(_start)))\n+ KEEP (*(SORT_NONE(risc_e906_start)))\n+ \n+ *(.text)\n+ *(.text.*)\n+ \n+ *(.rodata)\n+ *(.rodata.*)\n+ \n+ *(.srodata)\n+ *(.srodata.*)\n+ \n+ *(.tcm_code)\n+ *(.tcm_const)\n+ *(.sclock_rlt_code)\n+ *(.sclock_rlt_const)\n+\n+ /* static cli cmds */\n+ . = ALIGN(4);\n+ _bl_static_cli_cmds_start = .;\n+ KEEP(*(.static_cli_cmds))\n+ *(.static_cli_cmds)\n+ _bl_static_cli_cmds_end = .; \n+ \n+ /* static blog code1 */\n+ . = ALIGN(4);\n+ _bl_static_blogcomponent_code_start = .;\n+ KEEP(SORT(*)(.static_blogcomponent_code*))\n+ *(.static_blogcomponent_code*)\n+ _bl_static_blogcomponent_code_end = .;\n+ \n+ /* static blog code2 */\n+ . = ALIGN(4);\n+ _bl_static_blogfile_code_start = .;\n+ KEEP(SORT(*)(.static_blogfile_code*))\n+ *(.static_blogfile_code*)\n+ _bl_static_blogfile_code_end = .;\n+ \n+ /* static blog code3 */\n+ . = ALIGN(4);\n+ _bl_static_blogpri_code_start = .;\n+ KEEP(SORT(*)(.static_blogpri_code*))\n+ *(.static_blogpri_code*)\n+ _bl_static_blogpri_code_end = .;\n+ \n+ /* static fw attribute entry */\n+ . = ALIGN(4);\n+ _bl_static_fw_cfg_entry_start = .;\n+ KEEP(*(.wifi.cfg.entry))\n+ _bl_static_fw_cfg_entry_end = .;\n+ . = ALIGN(4);\n+\n+ __text_code_end__ = .;\n+ } > code_memory\n+\n+ .wifibss (NOLOAD) :\n+ {\n+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );\n+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );\n+ *ipc_shared.o(COMMON)\n+ *sdu_shared.o(COMMON)\n+ *hal_desc.o(COMMON)\n+ *txl_buffer_shared.o(COMMON)\n+ *txl_frame_shared.o(COMMON)\n+ *scan_shared.o(COMMON)\n+ *scanu_shared.o(COMMON)\n+ *mfp_bip.o(COMMON)\n+ *me_mic.o(COMMON)\n+ *bl_sta_mgmt_others.o(COMMON)\n+ *bl_pmk_mgmt.o(COMMON)\n+ *bl_pmk_mgmt_internal.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(COMMON)\n+ *libwifi_drv.a:bl_utils.o(.bss*)\n+ *(.wifi_ram*)\n+ . = ALIGN(16);\n+ } > ram_wifi\n+\n+ PROVIDE( _heap_wifi_start = . );\n+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );\n+\n+ /*SYMOBOL used in code*/\n+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );\n+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );\n+\n+ . = ALIGN(4);\n+ __itcm_load_addr = .;\n+ \n+ .itcm_region : AT (__itcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_code_start__ = .;\n+ \n+ . = ALIGN(4);\n+ __tcm_code_end__ = .;\n+ } > itcm_memory\n+ \n+ __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);\n+ \n+ .dtcm_region : AT (__dtcm_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __tcm_data_start__ = .;\n+ \n+ *(.tcm_data)\n+ /* *finger_print.o(.data*) */\n+ \n+ . = ALIGN(4);\n+ __tcm_data_end__ = .;\n+ } > dtcm_memory\n+ \n+ /*************************************************************************/\n+ /* .stack_dummy section doesn't contains any symbols. It is only\n+ * used for linker to calculate size of stack sections, and assign\n+ * values to stack symbols later */\n+ .stack_dummy (NOLOAD):\n+ {\n+ . = ALIGN(0x4);\n+ . = . + StackSize;\n+ . = ALIGN(0x4);\n+ } > dtcm_memory\n+ \n+ /* Set stack top to end of RAM, and stack limit move down by\n+ * size of stack_dummy section */\n+ __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);\n+ PROVIDE( __freertos_irq_stack_top = __StackTop);\n+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\n+ \n+ /* Check if data + heap + stack exceeds RAM limit */\n+ ASSERT(__StackLimit >= __tcm_data_end__, \"region RAM overflowed with stack\")\n+ /*************************************************************************/\n+ \n+ __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);\n+ \n+ .system_ram_data_region : AT (__system_ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __system_ram_data_start__ = .;\n+ \n+ *(.system_ram)\n+ \n+ . = ALIGN(4);\n+ __system_ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);\n+ \n+ /* Data section */\n+ RAM_DATA : AT (__ram_load_addr)\n+ {\n+ . = ALIGN(4);\n+ __ram_data_start__ = .;\n+ \n+ PROVIDE( __global_pointer$ = . + 0x800 );\n+ \n+ *(.data)\n+ *(.data.*)\n+ *(.sdata)\n+ *(.sdata.*)\n+ *(.sdata2)\n+ *(.sdata2.*)\n+ \n+ _bt_gatt_service_static_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_gatt_service_static.static.*\")))\n+ _bt_gatt_service_static_list_end = .;\n+ _bt_l2cap_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_fixed_chan.static.*\")))\n+ _bt_l2cap_fixed_chan_list_end = .;\n+ _bt_l2cap_br_fixed_chan_list_start = .;\n+ KEEP(*(SORT_BY_NAME(\"._bt_l2cap_br_fixed_chan.static.*\")))\n+ _bt_l2cap_br_fixed_chan_list_end = .;\n+\n+ . = ALIGN(4);\n+ __ram_data_end__ = .;\n+ } > ram_memory\n+ \n+ .noinit_data (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __noinit_data_start__ = .;\n+ \n+ *(.noinit_data*)\n+ \n+ . = ALIGN(4);\n+ __noinit_data_end__ = .;\n+ } > ram_memory\n+ \n+ .bss (NOLOAD) :\n+ {\n+ . = ALIGN(4);\n+ __bss_start__ = .;\n+ \n+ *(.bss*)\n+ *(.sbss*)\n+ *(COMMON)\n+ \n+ . = ALIGN(4);\n+ __bss_end__ = .;\n+ } > ram_memory\n+\n+ .heap (NOLOAD):\n+ {\n+ . = ALIGN(4);\n+ __HeapBase = .;\n+ _heap_start = .;\n+ \n+ /*__end__ = .;*/\n+ /*end = __end__;*/\n+ KEEP(*(.heap*))\n+ \n+ . = ALIGN(4);\n+ __HeapLimit = .;\n+ } > ram_memory\n+ __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);\n+ _heap_size = __HeapLimit - __HeapBase;\n+\n+ /* keep my variable even if not referenced */\n+ /* .testmem_at_ocram (NOLOAD) : \n+ {\n+ PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );\n+ PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );\n+ KEEP(*(.testmem_at_ocram))\n+ } > ram_test */\n+\n+ /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);\n+ __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */\n+\n+ __testmem_at_ocram_start_addr = ORIGIN(test_ocram);\n+ __testmem_at_wram_start_addr = ORIGIN(ram_wifi);\n+}\n+\n+PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );\n+PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );\n+PROVIDE( _ld_ram_size1 = 0);\n+PROVIDE( _ld_ram_addr1 = 0);\n+PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );\n+PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );\n+\n+/* blog */\n+PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );\n+PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );\n+PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );\n+PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );\n+PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );\n+PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );\n+\n+\n+PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );\n+PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..705babcd159ee6ef58ee652db03635ac5b58c490\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c\n@@ -0,0 +1,109 @@\n+#include <stdint.h>\n+#include <core_rv32.h>\n+#define __STARTUP_CLEAR_BSS 1\n+\n+/*----------------------------------------------------------------------------\n+ Linker generated Symbols\n+ *----------------------------------------------------------------------------*/\n+extern uint32_t __itcm_load_addr;\n+extern uint32_t __dtcm_load_addr;\n+extern uint32_t __system_ram_load_addr;\n+extern uint32_t __psram_ram_load_addr;\n+extern uint32_t __ram_load_addr;\n+\n+extern uint32_t __text_code_start__;\n+extern uint32_t __text_code_end__;\n+extern uint32_t __tcm_code_start__;\n+extern uint32_t __tcm_code_end__;\n+extern uint32_t __tcm_data_start__;\n+extern uint32_t __tcm_data_end__;\n+extern uint32_t __system_ram_data_start__;\n+extern uint32_t __system_ram_data_end__;\n+extern uint32_t __psram_ram_data_start__;\n+extern uint32_t __psram_ram_data_end__;\n+extern uint32_t __ram_data_start__;\n+extern uint32_t __ram_data_end__;\n+extern uint32_t __wifi_bss_start;\n+extern uint32_t __wifi_bss_end;\n+extern uint32_t __bss_start__;\n+extern uint32_t __bss_end__;\n+extern uint32_t __ocram_bss_start__;\n+extern uint32_t __ocram_bss_end__;\n+extern uint32_t __noinit_data_start__;\n+extern uint32_t __noinit_data_end__;\n+\n+extern uint32_t __StackTop;\n+extern uint32_t __StackLimit;\n+extern uint32_t __HeapBase;\n+extern uint32_t __HeapLimit;\n+\n+//extern uint32_t __copy_table_start__;\n+//extern uint32_t __copy_table_end__;\n+//extern uint32_t __zero_table_start__;\n+//extern uint32_t __zero_table_end__;\n+\n+\n+void start_load(void) {\n+ uint32_t *pSrc, *pDest;\n+ /*boot2 dcache is enable need disable*/\n+ csi_dcache_disable();\n+\n+ /* Copy ITCM code */\n+ pSrc = &__itcm_load_addr;\n+ pDest = &__tcm_code_start__;\n+ for ( ; pDest < &__tcm_code_end__ ; ) {\n+ *pDest++ = *pSrc++;\n+ }\n+\n+ /* Copy DTCM code */\n+ pSrc = &__dtcm_load_addr;\n+ pDest = &__tcm_data_start__;\n+ for( ; pDest < &__tcm_data_end__; ){\n+ *pDest++ = *pSrc++;\n+ }\n+\n+ /* BF Add system RAM data copy */\n+ pSrc = &__system_ram_load_addr;\n+ pDest = &__system_ram_data_start__;\n+ for ( ; pDest < &__system_ram_data_end__ ; ) {\n+ *pDest++ = *pSrc++;\n+ }\n+\n+ /* BF Add OCARAM data copy */\n+ pSrc = &__ram_load_addr;\n+ pDest = &__ram_data_start__;\n+ for ( ; pDest < &__ram_data_end__ ; ) {\n+ *pDest++ = *pSrc++;\n+ }\n+\n+#ifdef __STARTUP_CLEAR_BSS\n+ /*\n+ * The BSS section is specified by following symbols\n+ * __bss_start__: start of the BSS section.\n+ * __bss_end__: end of the BSS section.\n+ *\n+ * Both addresses must be aligned to 4 bytes boundary.\n+ */\n+ pDest = &__bss_start__;\n+ for ( ; pDest < &__bss_end__ ; ) {\n+ *pDest++ = 0ul;\n+ }\n+\n+ pDest = &__wifi_bss_start;\n+ for ( ; pDest < &__wifi_bss_end ; ) {\n+ *pDest++ = 0ul;\n+ }\n+\n+ pDest = &__ocram_bss_start__;\n+ for ( ; pDest < &__ocram_bss_end__ ; ) {\n+ *pDest++ = 0ul;\n+ }\n+#endif\n+\n+ /* BF Add PSRAM RAM data copy */\n+ pSrc = &__psram_ram_load_addr;\n+ pDest = &__psram_ram_data_start__;\n+ for ( ; pDest < &__psram_ram_data_end__ ; ) {\n+ *pDest++ = *pSrc++;\n+ }\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..cb74576c0e5699612306558ad64e722a48e109bd\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S\n@@ -0,0 +1,84 @@\n+/*\n+ * Copyright (C) 2016-2020 Bouffalo Lab\n+ */\n+\n+_start:\n+ .section .text.startup\n+ .align 2\n+ .globl risc_e906_start\n+ .type risc_e906_start, %function\n+risc_e906_start:\n+.option push\n+.option norelax\n+ la gp, __global_pointer$\n+.option pop\n+ la a0, IRQ_Handler\n+ ori a0, a0, 3\n+ csrw mtvec, a0 \n+#1:\n+# j 1b\n+\n+ la a0, __Vectors\n+ csrw mtvt, a0\n+\n+ .weak __StackTop\n+ la sp, __StackTop\n+ csrw mscratch, sp\n+\n+#ifndef RUN_IN_RAM\n+\t/* Load boot2 partition address */\n+\tla a0, __boot2_pt_addr_src\n+\tla a1, __boot2_pt_addr_start\n+\tla a2, __boot2_pt_addr_end\n+\tbgeu a1, a2, 2f\n+1:\n+\tlw t0, (a0)\n+\tsw t0, (a1)\n+\taddi a0, a0, 4\n+\taddi a1, a1, 4\n+\tbltu a1, a2, 1b\n+2:\n+\n+\n+\t/* Load boot2 flashCfg address */\n+\tla a0, hal_boot2_get_flash_addr\n+\tjalr a0\n+\tla a1, __boot2_flashCfg_start\n+\tla a2, __boot2_flashCfg_end\n+\tbgeu a1, a2, 2f\n+1:\n+\tlw t0, (a0)\n+\tsw t0, (a1)\n+\taddi a0, a0, 4\n+\taddi a1, a1, 4\n+\tbltu a1, a2, 1b\n+2:\n+#endif\n+\n+ /* Load data section removed */\n+ \n+ /* start load code to itcm like. */\n+ la a0, start_load\n+ jalr a0\n+ \n+ /* Clear bss section removed */\n+\n+#ifndef __NO_SYSTEM_INIT\n+ la a0, system_init_bl606p\n+ jalr a0\n+#endif\n+\n+#ifndef __NO_BOARD_INIT\n+ la a0, board_init\n+ jalr a0\n+#endif\n+ \n+\t//la a0, bfl_main\n+\tla a0, entry\n+ jalr a0\n+\n+ .size risc_e906_start, . - risc_e906_start\n+\n+__exit:\n+ j __exit\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..94f538fdae041140e7175905b3296b427de44b4d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S\n@@ -0,0 +1,327 @@\n+/*\n+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited\n+ */\n+ /******************************************************************************\n+ * @file vectors.S\n+ * @brief define default vector handlers. Should use with\n+ * GCC for CSKY Embedded Processors\n+ * @version V1.0\n+ * @date 28. Nove 2017\n+ ******************************************************************************/\n+\n+/* Enable interrupts when returning from the handler */\n+#define MSTATUS_PRV1 0x1880\n+\n+.section .bss\n+ .align 2\n+ .globl g_trapstackalloc\n+ .global g_trapstackbase\n+ .global g_top_trapstack\n+g_trapstackalloc:\n+g_trapstackbase:\n+ .space 768\n+g_top_trapstack:\n+\n+ .align 2\n+ .globl g_trap_sp\n+ .type g_trap_sp, object\n+g_trap_sp:\n+ .long 0\n+ .size g_trap_sp, .-g_trap_sp\n+\n+irq_nested_level:\n+.long 0\n+irq_mstatus_fs_flag:\n+.long 0\n+\n+.text\n+\n+ .align 2\n+ .global Default_IRQHandler\n+ .weak Default_IRQHandler\n+ .type Default_IRQHandler, %function\n+Default_IRQHandler:\n+ ipush\n+\n+#if 0\n+ csrr t1, mstatus\n+ srli t1, t1, 13\n+ andi t1, t1, 0x3\n+ la t3, irq_mstatus_fs_flag\n+ sw t1, (t3)\n+ li t0, 0x3\n+ bne t1, t0, .F_RegNotSave1\n+\n+\n+ addi sp, sp, -80\n+ fsw ft0, 0(sp)\n+ fsw ft1, 4(sp)\n+ fsw ft2, 8(sp)\n+ fsw ft3, 12(sp)\n+ fsw ft4, 16(sp)\n+ fsw ft5, 20(sp)\n+ fsw ft6, 24(sp)\n+ fsw ft7, 28(sp)\n+ fsw fa0, 32(sp)\n+ fsw fa1, 36(sp)\n+ fsw fa2, 40(sp)\n+ fsw fa3, 44(sp)\n+ fsw fa4, 48(sp)\n+ fsw fa5, 52(sp)\n+ fsw fa6, 56(sp)\n+ fsw fa7, 60(sp)\n+ fsw ft8, 64(sp)\n+ fsw ft9, 68(sp)\n+ fsw ft10,72(sp)\n+ fsw ft11,76(sp)\n+.F_RegNotSave1:\n+#endif\n+ \n+ /* disable irq */\n+ csrc mstatus, 8 \n+\n+ /* Set IRQ stack pointer */\n+ la t0, __freertos_irq_stack_top\n+ addi t1, sp, 0\n+ addi sp, t0, -8\n+ /* save t1 to stack */\n+ sw t1, 4(sp)\n+\n+ csrr t1, mcause\n+ andi t1, t1, 0x3FF\n+ slli t1, t1, 2\n+ la t0, g_irqvector\n+ add t0, t0, t1\n+ lw t2, (t0)\n+ jalr t2\n+ \n+ la t0, __freertos_irq_stack_top\n+ lw sp, t0, -4\n+\n+ /* enable irq */\n+ csrs mstatus, 8 \n+\n+ li t0, MSTATUS_PRV1\n+ csrs mstatus, t0\n+\n+#if 0\n+ la t0, irq_mstatus_fs_flag\n+ lw t1, (t0)\n+ li t0, 0x3\n+ bne t1, t0, .F_RegNotLoad\n+\n+ flw ft0, 0(sp)\n+ flw ft1, 4(sp)\n+ flw ft2, 8(sp)\n+ flw ft3, 12(sp)\n+ flw ft4, 16(sp)\n+ flw ft5, 20(sp)\n+ flw ft6, 24(sp)\n+ flw ft7, 28(sp)\n+ flw fa0, 32(sp)\n+ flw fa1, 36(sp)\n+ flw fa2, 40(sp)\n+ flw fa3, 44(sp)\n+ flw fa4, 48(sp)\n+ flw fa5, 52(sp)\n+ flw fa6, 56(sp)\n+ flw fa7, 60(sp)\n+ flw ft8, 64(sp)\n+ flw ft9, 68(sp)\n+ flw ft10,72(sp)\n+ flw ft11,76(sp)\n+ addi sp, sp, 80\n+\n+.F_RegNotLoad:\n+#endif\n+\n+ ipop\n+\n+\n+/******************************************************************************\n+ * Functions:\n+ * void trap(void);\n+ * default exception handler\n+ ******************************************************************************/\n+ .align 2\n+ .global trap\n+ .type trap, %function\n+trap:\n+ /* Check for interrupt */\n+ addi sp, sp, -4\n+ sw t0, 0x0(sp)\n+ csrr t0, mcause\n+\n+ blt t0, x0, .Lirq\n+\n+ addi sp, sp, 4\n+\n+ la t0, g_trap_sp\n+ addi t0, t0, -132\n+ sw x1, 0(t0)\n+ sw x2, 4(t0)\n+ sw x3, 8(t0)\n+ sw x4, 12(t0)\n+ sw x6, 20(t0)\n+ sw x7, 24(t0)\n+ sw x8, 28(t0)\n+ sw x9, 32(t0)\n+ sw x10, 36(t0)\n+ sw x11, 40(t0)\n+ sw x12, 44(t0)\n+ sw x13, 48(t0)\n+ sw x14, 52(t0)\n+ sw x15, 56(t0)\n+ sw x16, 60(t0)\n+ sw x17, 64(t0)\n+ sw x18, 68(t0)\n+ sw x19, 72(t0)\n+ sw x20, 76(t0)\n+ sw x21, 80(t0)\n+ sw x22, 84(t0)\n+ sw x23, 88(t0)\n+ sw x24, 92(t0)\n+ sw x25, 96(t0)\n+ sw x26, 100(t0)\n+ sw x27, 104(t0)\n+ sw x28, 108(t0)\n+ sw x29, 112(t0)\n+ sw x30, 116(t0)\n+ sw x31, 120(t0)\n+ csrr a0, mepc\n+ sw a0, 124(t0)\n+ csrr a0, mstatus\n+ sw a0, 128(t0)\n+\n+ mv a0, t0\n+ lw t0, -4(sp)\n+ mv sp, a0\n+ sw t0, 16(sp)\n+\n+ jal trap_c\n+\n+\n+.Lirq:\n+ lw t0, 0x0(sp)\n+ addi sp, sp, 4\n+ j Default_IRQHandler\n+\n+ .align 6\n+ .weak Default_Handler\n+ .global Default_Handler\n+ .type Default_Handler, %function\n+Default_Handler:\n+ /* Check for nmi */\n+ addi sp, sp, -8\n+ sw t0, 0x0(sp)\n+ sw t1, 0x4(sp)\n+ csrr t0, mcause\n+ andi t0, t0, 0x3FF\n+ li t1, 24\n+ beq t0, t1, .NMI_Handler\n+ lw t0, 0x0(sp)\n+ lw t1, 0x4(sp)\n+ addi sp, sp, 8\n+ j trap\n+\n+.NMI_Handler:\n+ lw t0, 0x0(sp)\n+ lw t1, 0x4(sp)\n+ addi sp, sp, 8\n+\n+ addi sp, sp, -64\n+ sw ra, 0(sp)\n+ sw t0, 4(sp)\n+ sw t1, 8(sp)\n+ sw t2, 12(sp)\n+ sw a0, 16(sp)\n+ sw a1, 20(sp)\n+ sw a2, 24(sp)\n+ sw a3, 28(sp)\n+ sw a4, 32(sp)\n+ sw a5, 36(sp)\n+ sw a6, 40(sp)\n+ sw a7, 44(sp)\n+ sw t3, 48(sp)\n+ sw t4, 52(sp)\n+ sw t5, 56(sp)\n+ sw t6, 60(sp)\n+\n+ addi sp, sp, -80\n+ fsw ft0, 0(sp)\n+ fsw ft1, 4(sp)\n+ fsw ft2, 8(sp)\n+ fsw ft3, 12(sp)\n+ fsw ft4, 16(sp)\n+ fsw ft5, 20(sp)\n+ fsw ft6, 24(sp)\n+ fsw ft7, 28(sp)\n+ fsw fa0, 32(sp)\n+ fsw fa1, 36(sp)\n+ fsw fa2, 40(sp)\n+ fsw fa3, 44(sp)\n+ fsw fa4, 48(sp)\n+ fsw fa5, 52(sp)\n+ fsw fa6, 56(sp)\n+ fsw fa7, 60(sp)\n+ fsw ft8, 64(sp)\n+ fsw ft9, 68(sp)\n+ fsw ft10,72(sp)\n+ fsw ft11,76(sp)\n+\n+ la t0, g_nmivector\n+ lw t0, (t0)\n+ jalr t0\n+\n+ flw ft0, 0(sp)\n+ flw ft1, 4(sp)\n+ flw ft2, 8(sp)\n+ flw ft3, 12(sp)\n+ flw ft4, 16(sp)\n+ flw ft5, 20(sp)\n+ flw ft6, 24(sp)\n+ flw ft7, 28(sp)\n+ flw fa0, 32(sp)\n+ flw fa1, 36(sp)\n+ flw fa2, 40(sp)\n+ flw fa3, 44(sp)\n+ flw fa4, 48(sp)\n+ flw fa5, 52(sp)\n+ flw fa6, 56(sp)\n+ flw fa7, 60(sp)\n+ flw ft8, 64(sp)\n+ flw ft9, 68(sp)\n+ flw ft10,72(sp)\n+ flw ft11,76(sp)\n+\n+ addi sp, sp, 80\n+\n+ lw ra, 0(sp)\n+ lw t0, 4(sp)\n+ lw t1, 8(sp)\n+ lw t2, 12(sp)\n+ lw a0, 16(sp)\n+ lw a1, 20(sp)\n+ lw a2, 24(sp)\n+ lw a3, 28(sp)\n+ lw a4, 32(sp)\n+ lw a5, 36(sp)\n+ lw a6, 40(sp)\n+ lw a7, 44(sp)\n+ lw t3, 48(sp)\n+ lw t4, 52(sp)\n+ lw t5, 56(sp)\n+ lw t6, 60(sp)\n+ addi sp, sp, 64\n+ mret\n+\n+ .size Default_Handler, . - Default_Handler\n+\n+/* Macro to define default handlers. Default handler\n+ * will be weak symbol and just dead loops. They can be\n+ * overwritten by other handlers */\n+ .macro def_irq_handler handler_name\n+ .weak \\handler_name\n+ .globl \\handler_name\n+ .set \\handler_name, Default_Handler\n+ .endm\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7f26dfb3a816e7f3e6419f4bf8599dc8ffa9c19e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c\n@@ -0,0 +1,914 @@\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <limits.h>\n+\n+#define DEFAULT_UART_ID 0\n+\n+uint32_t debug_uart_id = DEFAULT_UART_ID;\n+\n+//#define CHAR_BIT\t8\n+//FIXME no ugly declare\n+extern int bl_uart_data_send(uint8_t id, uint8_t data);\n+\n+volatile bool sys_log_all_enable = true;\n+\n+enum flag {\n+\tFL_ZERO\t\t= 0x01,\t/* Zero modifier */\n+\tFL_MINUS\t= 0x02,\t/* Minus modifier */\n+\tFL_PLUS\t\t= 0x04,\t/* Plus modifier */\n+\tFL_TICK\t\t= 0x08,\t/* ' modifier */\n+\tFL_SPACE\t= 0x10,\t/* Space modifier */\n+\tFL_HASH\t\t= 0x20,\t/* # modifier */\n+\tFL_SIGNED\t= 0x40,\t/* Number is signed */\n+\tFL_UPPER\t= 0x80\t/* Upper case digits */\n+};\n+\n+/* These may have to be adjusted on certain implementations */\n+enum ranks {\n+\trank_char\t= -2,\n+\trank_short\t= -1,\n+\trank_int\t= 0,\n+\trank_long\t= 1,\n+\trank_longlong\t= 2\n+};\n+\n+#define MIN_RANK\trank_char\n+#define MAX_RANK\trank_longlong\n+\n+#define INTMAX_RANK\trank_longlong\n+#define SIZE_T_RANK\trank_long\n+#define PTRDIFF_T_RANK\trank_long\n+\n+#define EMIT(x) { if (o < n) { *q++ = (x); } o++; }\n+\n+void debug_uart_id_set(uint8_t id)\n+{\n+\tdebug_uart_id = id;\n+}\n+\n+static size_t\n+format_int(char *q, size_t n, uintmax_t val, unsigned int flags,\n+\t int base, int width, int prec)\n+{\n+\tchar *qq;\n+\tsize_t o = 0, oo;\n+\tstatic const char lcdigits[] = \"0123456789abcdef\";\n+\tstatic const char ucdigits[] = \"0123456789ABCDEF\";\n+\tconst char *digits;\n+\tuintmax_t tmpval;\n+\tint minus = 0;\n+\tint ndigits = 0, nchars;\n+\tint tickskip, b4tick;\n+\n+\t/* Select type of digits */\n+\tdigits = (flags & FL_UPPER) ? ucdigits : lcdigits;\n+\n+\t/* If signed, separate out the minus */\n+\tif (flags & FL_SIGNED && (intmax_t) val < 0) {\n+\t\tminus = 1;\n+\t\tval = (uintmax_t) (-(intmax_t) val);\n+\t}\n+\n+\t/* Count the number of digits needed. This returns zero for 0. */\n+\ttmpval = val;\n+\twhile (tmpval) {\n+\t\ttmpval /= base;\n+\t\tndigits++;\n+\t}\n+\n+\t/* Adjust ndigits for size of output */\n+\n+\tif (flags & FL_HASH && base == 8) {\n+\t\tif (prec < ndigits + 1)\n+\t\t\tprec = ndigits + 1;\n+\t}\n+\n+\tif (ndigits < prec) {\n+\t\tndigits = prec;\t/* Mandatory number padding */\n+\t} else if (val == 0) {\n+\t\tndigits = 1;\t/* Zero still requires space */\n+\t}\n+\n+\t/* For ', figure out what the skip should be */\n+\tif (flags & FL_TICK) {\n+\t\ttickskip = (base == 16) ? 4 : 3;\n+\t} else {\n+\t\ttickskip = ndigits;\t/* No tick marks */\n+\t}\n+\n+\t/* Tick marks aren't digits, but generated by the number converter */\n+\tndigits += (ndigits - 1) / tickskip;\n+\n+\t/* Now compute the number of nondigits */\n+\tnchars = ndigits;\n+\n+\tif (minus || (flags & (FL_PLUS | FL_SPACE)))\n+\t\tnchars++;\t/* Need space for sign */\n+\tif ((flags & FL_HASH) && base == 16) {\n+\t\tnchars += 2;\t/* Add 0x for hex */\n+\t}\n+\n+\t/* Emit early space padding */\n+\tif (!(flags & (FL_MINUS | FL_ZERO)) && width > nchars) {\n+\t\twhile (width > nchars) {\n+\t\t\tEMIT(' ');\n+\t\t\twidth--;\n+\t\t}\n+\t}\n+\n+\t/* Emit nondigits */\n+\tif (minus) {\n+\t\tEMIT('-');\n+\t} else if (flags & FL_PLUS) {\n+\t\tEMIT('+');\n+\t} else if (flags & FL_SPACE) {\n+\t\tEMIT(' ');\n+\t}\n+\n+\tif ((flags & FL_HASH) && base == 16) {\n+\t\tEMIT('0');\n+\t\tEMIT((flags & FL_UPPER) ? 'X' : 'x');\n+\t}\n+\n+\t/* Emit zero padding */\n+\tif ((flags & (FL_MINUS | FL_ZERO)) == FL_ZERO && width > ndigits) {\n+\t\twhile (width > nchars) {\n+\t\t\tEMIT('0');\n+\t\t\twidth--;\n+\t\t}\n+\t}\n+\n+\t/* Generate the number. This is done from right to left. */\n+\tq += ndigits;\t\t/* Advance the pointer to end of number */\n+\to += ndigits;\n+\tqq = q;\n+\too = o;\t\t\t/* Temporary values */\n+\n+\tb4tick = tickskip;\n+\twhile (ndigits > 0) {\n+\t\tif (!b4tick--) {\n+\t\t\tqq--;\n+\t\t\too--;\n+\t\t\tndigits--;\n+\t\t\tif (oo < n)\n+\t\t\t\t*qq = '_';\n+\t\t\tb4tick = tickskip - 1;\n+\t\t}\n+\t\tqq--;\n+\t\too--;\n+\t\tndigits--;\n+\t\tif (oo < n)\n+\t\t\t*qq = digits[val % base];\n+\t\tval /= base;\n+\t}\n+\n+\t/* Emit late space padding */\n+\twhile ((flags & FL_MINUS) && width > nchars) {\n+\t\tEMIT(' ');\n+\t\twidth--;\n+\t}\n+\n+\treturn o;\n+}\n+\n+#define ZEROPAD \t(1<<0)\t/* Pad with zero */\n+#define SIGN \t(1<<1)\t/* Unsigned/signed long */\n+#define PLUS \t(1<<2)\t/* Show plus */\n+#define SPACE \t(1<<3)\t/* Spacer */\n+#define LEFT \t(1<<4)\t/* Left justified */\n+#define HEX_PREP \t(1<<5)\t/* 0x */\n+#define UPPERCASE (1<<6)\t/* 'ABCDEF' */\n+\n+#include <math.h>\n+#define CVTBUFSIZE 80\n+\n+static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag)\n+{\n+ int r2;\n+ double fi, fj;\n+ char *p, *p1;\n+\n+ if (ndigits < 0) ndigits = 0;\n+ if (ndigits >= CVTBUFSIZE - 1) ndigits = CVTBUFSIZE - 2;\n+ r2 = 0;\n+ *sign = 0;\n+ p = &buf[0];\n+ if (arg < 0)\n+ {\n+ *sign = 1;\n+ arg = -arg;\n+ }\n+ arg = modf(arg, &fi);\n+ p1 = &buf[CVTBUFSIZE];\n+\n+ if (fi != 0) \n+ {\n+ p1 = &buf[CVTBUFSIZE];\n+ while (fi != 0) \n+ {\n+ fj = modf(fi / 10, &fi);\n+ *--p1 = (int)((fj + 0.03) * 10) + '0';\n+ r2++;\n+ }\n+ while (p1 < &buf[CVTBUFSIZE]) *p++ = *p1++;\n+ }\n+ else if (arg > 0)\n+ {\n+ while ((fj = arg * 10) < 1) \n+ {\n+ arg = fj;\n+ r2--;\n+ }\n+ }\n+ p1 = &buf[ndigits];\n+ if (eflag == 0) p1 += r2;\n+ *decpt = r2;\n+ if (p1 < &buf[0]) \n+ {\n+ buf[0] = '\\0';\n+ return buf;\n+ }\n+ while (p <= p1 && p < &buf[CVTBUFSIZE])\n+ {\n+ arg *= 10;\n+ arg = modf(arg, &fj);\n+ *p++ = (int) fj + '0';\n+ }\n+ if (p1 >= &buf[CVTBUFSIZE]) \n+ {\n+ buf[CVTBUFSIZE - 1] = '\\0';\n+ return buf;\n+ }\n+ p = p1;\n+ *p1 += 5;\n+ while (*p1 > '9')\n+ {\n+ *p1 = '0';\n+ if (p1 > buf)\n+ ++*--p1;\n+ else\n+ {\n+ *p1 = '1';\n+ (*decpt)++;\n+ if (eflag == 0)\n+ {\n+ if (p > buf) *p = '0';\n+ p++;\n+ }\n+ }\n+ }\n+ *p = '\\0';\n+ return buf;\n+}\n+\n+char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)\n+{\n+ return cvt(arg, ndigits, decpt, sign, buf, 1);\n+}\n+\n+char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)\n+{\n+ return cvt(arg, ndigits, decpt, sign, buf, 0);\n+}\n+\n+static void ee_bufcpy(char *d, char *s, int count); \n+ \n+void ee_bufcpy(char *pd, char *ps, int count) {\n+\tchar *pe=ps+count;\n+\twhile (ps!=pe)\n+\t\t*pd++=*ps++;\n+}\n+\n+static void parse_float(double value, char *buffer, char fmt, int precision)\n+{\n+ int decpt, sign, exp, pos;\n+ char *digits = NULL;\n+ char cvtbuf[80];\n+ int capexp = 0;\n+ int magnitude;\n+\n+ if (fmt == 'G' || fmt == 'E')\n+ {\n+ capexp = 1;\n+ fmt += 'a' - 'A';\n+ }\n+\n+ if (fmt == 'g')\n+ {\n+ digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf);\n+ magnitude = decpt - 1;\n+ if (magnitude < -4 || magnitude > precision - 1)\n+ {\n+ fmt = 'e';\n+ precision -= 1;\n+ }\n+ else\n+ {\n+ fmt = 'f';\n+ precision -= decpt;\n+ }\n+ }\n+\n+ if (fmt == 'e')\n+ {\n+ digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf);\n+\n+ if (sign) *buffer++ = '-';\n+ *buffer++ = *digits;\n+ if (precision > 0) *buffer++ = '.';\n+ ee_bufcpy(buffer, digits + 1, precision);\n+ buffer += precision;\n+ *buffer++ = capexp ? 'E' : 'e';\n+\n+ if (decpt == 0)\n+ {\n+ if (value == 0.0)\n+ exp = 0;\n+ else\n+ exp = -1;\n+ }\n+ else\n+ exp = decpt - 1;\n+\n+ if (exp < 0)\n+ {\n+ *buffer++ = '-';\n+ exp = -exp;\n+ }\n+ else\n+ *buffer++ = '+';\n+\n+ buffer[2] = (exp % 10) + '0';\n+ exp = exp / 10;\n+ buffer[1] = (exp % 10) + '0';\n+ exp = exp / 10;\n+ buffer[0] = (exp % 10) + '0';\n+ buffer += 3;\n+ }\n+ else if (fmt == 'f')\n+ {\n+ digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf);\n+ if (sign) *buffer++ = '-';\n+ if (*digits)\n+ {\n+ if (decpt <= 0)\n+ {\n+ *buffer++ = '0';\n+ *buffer++ = '.';\n+ for (pos = 0; pos < -decpt; pos++) *buffer++ = '0';\n+ while (*digits) *buffer++ = *digits++;\n+ }\n+ else\n+ {\n+ pos = 0;\n+ while (*digits)\n+ {\n+ if (pos++ == decpt) *buffer++ = '.';\n+ *buffer++ = *digits++;\n+ }\n+ }\n+ }\n+ else\n+ {\n+ *buffer++ = '0';\n+ if (precision > 0)\n+ {\n+ *buffer++ = '.';\n+ for (pos = 0; pos < precision; pos++) *buffer++ = '0';\n+ }\n+ }\n+ }\n+\n+ *buffer = '\\0';\n+}\n+\n+static void decimal_point(char *buffer)\n+{\n+ while (*buffer)\n+ {\n+ if (*buffer == '.') return;\n+ if (*buffer == 'e' || *buffer == 'E') break;\n+ buffer++;\n+ }\n+\n+ if (*buffer)\n+ {\n+ int n = strnlen(buffer,256);\n+ while (n > 0) \n+ {\n+ buffer[n + 1] = buffer[n];\n+ n--;\n+ }\n+\n+ *buffer = '.';\n+ }\n+ else\n+ {\n+ *buffer++ = '.';\n+ *buffer = '\\0';\n+ }\n+}\n+\n+static void cropzeros(char *buffer)\n+{\n+ char *stop;\n+\n+ while (*buffer && *buffer != '.') buffer++;\n+ if (*buffer++)\n+ {\n+ while (*buffer && *buffer != 'e' && *buffer != 'E') buffer++;\n+ stop = buffer--;\n+ while (*buffer == '0') buffer--;\n+ if (*buffer == '.') buffer--;\n+ while (buffer!=stop)\n+\t\t*++buffer=0;\n+ }\n+}\n+\n+static char *flt(char *str, double num, int size, int precision, char fmt, int flags)\n+{\n+ char tmp[80];\n+ char c, sign;\n+ int n, i;\n+\n+ // Left align means no zero padding\n+ if (flags & LEFT) flags &= ~ZEROPAD;\n+\n+ // Determine padding and sign char\n+ c = (flags & ZEROPAD) ? '0' : ' ';\n+ sign = 0;\n+ if (flags & SIGN)\n+ {\n+ if (num < 0.0)\n+ {\n+ sign = '-';\n+ num = -num;\n+ size--;\n+ }\n+ else if (flags & PLUS)\n+ {\n+ sign = '+';\n+ size--;\n+ }\n+ else if (flags & SPACE)\n+ {\n+ sign = ' ';\n+ size--;\n+ }\n+ }\n+\n+ // Compute the precision value\n+ if (precision < 0)\n+ precision = 6; // Default precision: 6\n+\n+ // Convert floating point number to text\n+ parse_float(num, tmp, fmt, precision);\n+\n+ if ((flags & HEX_PREP) && precision == 0) decimal_point(tmp);\n+ if (fmt == 'g' && !(flags & HEX_PREP)) cropzeros(tmp);\n+\n+ n = strnlen(tmp,256);\n+\n+ // Output number with alignment and padding\n+ size -= n;\n+ if (!(flags & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' ';\n+ if (sign) *str++ = sign;\n+ if (!(flags & LEFT)) while (size-- > 0) *str++ = c;\n+ for (i = 0; i < n; i++) *str++ = tmp[i];\n+ while (size-- > 0) *str++ = ' ';\n+\n+ return str;\n+}\n+\n+\n+/*use O0 preventing consuming more stack*/\n+int __attribute__((optimize(\"O1\"))) vsnprintf(char *buffer, size_t n, const char *format, va_list ap)\n+{\n+\tconst char *p = format;\n+\tchar ch;\n+\tchar *q = buffer;\n+\tchar *tmp;\n+\tsize_t o = 0;\t\t/* Number of characters output */\n+\tuintmax_t val = 0;\n+\tint rank = rank_int;\t/* Default rank */\n+\tint width = 0;\n+\tint prec = -1;\n+\tint base;\n+\tsize_t sz;\n+\tunsigned int flags = 0;\n+\tenum {\n+\t\tst_normal,\t/* Ground state */\n+\t\tst_flags,\t/* Special flags */\n+\t\tst_width,\t/* Field width */\n+\t\tst_prec,\t/* Field precision */\n+\t\tst_modifiers\t/* Length or conversion modifiers */\n+\t} state = st_normal;\n+\tconst char *sarg;\t/* %s string argument */\n+\tchar carg;\t\t/* %c char argument */\n+\tint slen;\t\t/* String length */\n+\n+\twhile ((ch = *p++)) {\n+\t\tswitch (state) {\n+\t\tcase st_normal:\n+\t\t\tif (ch == '%') {\n+\t\t\t\tstate = st_flags;\n+\t\t\t\tflags = 0;\n+\t\t\t\trank = rank_int;\n+\t\t\t\twidth = 0;\n+\t\t\t\tprec = -1;\n+\t\t\t} else {\n+\t\t\t\tEMIT(ch);\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase st_flags:\n+\t\t\tswitch (ch) {\n+\t\t\tcase '-':\n+\t\t\t\tflags |= FL_MINUS;\n+\t\t\t\tbreak;\n+\t\t\tcase '+':\n+\t\t\t\tflags |= FL_PLUS;\n+\t\t\t\tbreak;\n+\t\t\tcase '\\'':\n+\t\t\t\tflags |= FL_TICK;\n+\t\t\t\tbreak;\n+\t\t\tcase ' ':\n+\t\t\t\tflags |= FL_SPACE;\n+\t\t\t\tbreak;\n+\t\t\tcase '#':\n+\t\t\t\tflags |= FL_HASH;\n+\t\t\t\tbreak;\n+\t\t\tcase '0':\n+\t\t\t\tflags |= FL_ZERO;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tstate = st_width;\n+\t\t\t\tp--;\t/* Process this character again */\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase st_width:\n+\t\t\tif (ch >= '0' && ch <= '9') {\n+\t\t\t\twidth = width * 10 + (ch - '0');\n+\t\t\t} else if (ch == '*') {\n+\t\t\t\twidth = va_arg(ap, int);\n+\t\t\t\tif (width < 0) {\n+\t\t\t\t\twidth = -width;\n+\t\t\t\t\tflags |= FL_MINUS;\n+\t\t\t\t}\n+\t\t\t} else if (ch == '.') {\n+\t\t\t\tprec = 0;\t/* Precision given */\n+\t\t\t\tstate = st_prec;\n+\t\t\t} else {\n+\t\t\t\tstate = st_modifiers;\n+\t\t\t\tp--;\t/* Process this character again */\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase st_prec:\n+\t\t\tif (ch >= '0' && ch <= '9') {\n+\t\t\t\tprec = prec * 10 + (ch - '0');\n+\t\t\t} else if (ch == '*') {\n+\t\t\t\tprec = va_arg(ap, int);\n+\t\t\t\tif (prec < 0)\n+\t\t\t\t\tprec = -1;\n+\t\t\t} else {\n+\t\t\t\tstate = st_modifiers;\n+\t\t\t\tp--;\t/* Process this character again */\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase st_modifiers:\n+\t\t\tswitch (ch) {\n+\t\t\t\t/* Length modifiers - nonterminal sequences */\n+\t\t\tcase 'h':\n+\t\t\t\trank--;\t/* Shorter rank */\n+\t\t\t\tbreak;\n+\t\t\tcase 'l':\n+\t\t\t\trank++;\t/* Longer rank */\n+\t\t\t\tbreak;\n+\t\t\tcase 'j':\n+\t\t\t\trank = INTMAX_RANK;\n+\t\t\t\tbreak;\n+\t\t\tcase 'z':\n+\t\t\t\trank = SIZE_T_RANK;\n+\t\t\t\tbreak;\n+\t\t\tcase 't':\n+\t\t\t\trank = PTRDIFF_T_RANK;\n+\t\t\t\tbreak;\n+\t\t\tcase 'L':\n+\t\t\tcase 'q':\n+\t\t\t\trank += 2;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\t/* Output modifiers - terminal sequences */\n+\n+\t\t\t\t/* Next state will be normal */\n+\t\t\t\tstate = st_normal;\n+\n+\t\t\t\t/* Canonicalize rank */\n+\t\t\t\tif (rank < MIN_RANK)\n+\t\t\t\t\trank = MIN_RANK;\n+\t\t\t\telse if (rank > MAX_RANK)\n+\t\t\t\t\trank = MAX_RANK;\n+\n+\t\t\t\tswitch (ch) {\n+\t\t\t\tcase 'P':\t/* Upper case pointer */\n+\t\t\t\t\tflags |= FL_UPPER;\n+ __attribute__ ((fallthrough));\n+\t\t\t\t\t/* fall through */\n+\t\t\t\tcase 'p':\t/* Pointer */\n+\t\t\t\t\tbase = 16;\n+\t\t\t\t\tprec = (CHAR_BIT*sizeof(void *)+3)/4;\n+\t\t\t\t\tflags |= FL_HASH;\n+\t\t\t\t\tval = (uintmax_t)(uintptr_t)\n+\t\t\t\t\t\tva_arg(ap, void *);\n+\t\t\t\t\tgoto is_integer;\n+\n+\t\t\t\tcase 'd':\t/* Signed decimal output */\n+\t\t\t\tcase 'i':\n+\t\t\t\t\tbase = 10;\n+\t\t\t\t\tflags |= FL_SIGNED;\n+\t\t\t\t\tswitch (rank) {\n+\t\t\t\t\tcase rank_char:\n+\t\t\t\t\t\t/* Yes, all these casts are\n+\t\t\t\t\t\t needed... */\n+\t\t\t\t\t\tval = (uintmax_t)(intmax_t)\n+\t\t\t\t\t\t\t(signed char)\n+\t\t\t\t\t\t\tva_arg(ap, signed int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_short:\n+\t\t\t\t\t\tval = (uintmax_t)(intmax_t)\n+\t\t\t\t\t\t\t(signed short)\n+\t\t\t\t\t\t\tva_arg(ap, signed int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_int:\n+\t\t\t\t\t\tval = (uintmax_t)(intmax_t)\n+\t\t\t\t\t\t va_arg(ap, signed int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_long:\n+\t\t\t\t\t\tval = (uintmax_t)(intmax_t)\n+\t\t\t\t\t\t va_arg(ap, signed long);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_longlong:\n+\t\t\t\t\t\tval = (uintmax_t)(intmax_t)\n+\t\t\t\t\t\t va_arg(ap,\n+\t\t\t\t\t\t\t signed long long);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t\tgoto is_integer;\n+\t\t\t\tcase 'o':\t/* Octal */\n+\t\t\t\t\tbase = 8;\n+\t\t\t\t\tgoto is_unsigned;\n+\t\t\t\tcase 'u':\t/* Unsigned decimal */\n+\t\t\t\t\tbase = 10;\n+\t\t\t\t\tgoto is_unsigned;\n+\t\t\t\tcase 'X':\t/* Upper case hexadecimal */\n+\t\t\t\t\tflags |= FL_UPPER;\n+ __attribute__ ((fallthrough));\n+\t\t\t\t\t/* fall through */\n+\t\t\t\tcase 'x':\t/* Hexadecimal */\n+\t\t\t\t\tbase = 16;\n+\t\t\t\t\tgoto is_unsigned;\n+\n+\t\t\t\tis_unsigned:\n+\t\t\t\t\tswitch (rank) {\n+\t\t\t\t\tcase rank_char:\n+\t\t\t\t\t\tval = (uintmax_t)\n+\t\t\t\t\t\t\t(unsigned char)\n+\t\t\t\t\t\t\tva_arg(ap, unsigned\n+\t\t\t\t\t\t\t int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_short:\n+\t\t\t\t\t\tval = (uintmax_t)\n+\t\t\t\t\t\t\t(unsigned short)\n+\t\t\t\t\t\t\tva_arg(ap, unsigned\n+\t\t\t\t\t\t\t int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_int:\n+\t\t\t\t\t\tval = (uintmax_t)\n+\t\t\t\t\t\t\tva_arg(ap, unsigned\n+\t\t\t\t\t\t\t int);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_long:\n+\t\t\t\t\t\tval = (uintmax_t)\n+\t\t\t\t\t\t\tva_arg(ap, unsigned\n+\t\t\t\t\t\t\t long);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\tcase rank_longlong:\n+\t\t\t\t\t\tval = (uintmax_t)\n+\t\t\t\t\t\t\tva_arg(ap, unsigned\n+\t\t\t\t\t\t\t long long);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t\t/* fall through */\n+\n+\t\t\t\tis_integer:\n+\t\t\t\t\tsz = format_int(q, (o < n) ? n - o : 0,\n+\t\t\t\t\t\t\tval, flags, base,\n+\t\t\t\t\t\t\twidth, prec);\n+\t\t\t\t\tq += sz;\n+\t\t\t\t\to += sz;\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 'c':\t/* Character */\n+\t\t\t\t\tcarg = (char)va_arg(ap, int);\n+\t\t\t\t\tsarg = &carg;\n+\t\t\t\t\tslen = 1;\n+\t\t\t\t\tgoto is_string;\n+\t\t\t\tcase 's':\t/* String */\n+\t\t\t\t\tsarg = va_arg(ap, const char *);\n+\t\t\t\t\tsarg = sarg ? sarg : \"(null)\";\n+\t\t\t\t\tslen = strlen(sarg);\n+\t\t\t\t\tgoto is_string;\n+\n+\t\t\t\tis_string:\n+\t\t\t\t\t{\n+\t\t\t\t\t\tchar sch;\n+\t\t\t\t\t\tint i;\n+\n+\t\t\t\t\t\tif (prec != -1 && slen > prec)\n+\t\t\t\t\t\t\tslen = prec;\n+\n+\t\t\t\t\t\tif (width > slen\n+\t\t\t\t\t\t && !(flags & FL_MINUS)) {\n+\t\t\t\t\t\t\tchar pad =\n+\t\t\t\t\t\t\t (flags & FL_ZERO) ?\n+\t\t\t\t\t\t\t '0' : ' ';\n+\t\t\t\t\t\t\twhile (width > slen) {\n+\t\t\t\t\t\t\t\tEMIT(pad);\n+\t\t\t\t\t\t\t\twidth--;\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tfor (i = slen; i; i--) {\n+\t\t\t\t\t\t\tsch = *sarg++;\n+\t\t\t\t\t\t\tEMIT(sch);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tif (width > slen\n+\t\t\t\t\t\t && (flags & FL_MINUS)) {\n+\t\t\t\t\t\t\twhile (width > slen) {\n+\t\t\t\t\t\t\t\tEMIT(' ');\n+\t\t\t\t\t\t\t\twidth--;\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 'n':\n+\t\t\t\t\t{\n+\t\t\t\t\t\t/* Output the number of\n+\t\t\t\t\t\t characters written */\n+\n+\t\t\t\t\t\tswitch (rank) {\n+\t\t\t\t\t\tcase rank_char:\n+\t\t\t\t\t\t\t*va_arg(ap,\n+\t\t\t\t\t\t\t\tsigned char *)\n+\t\t\t\t\t\t\t\t= o;\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase rank_short:\n+\t\t\t\t\t\t\t*va_arg(ap,\n+\t\t\t\t\t\t\t\tsigned short *)\n+\t\t\t\t\t\t\t\t= o;\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase rank_int:\n+\t\t\t\t\t\t\t*va_arg(ap,\n+\t\t\t\t\t\t\t\tsigned int *)\n+\t\t\t\t\t\t\t\t= o;\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase rank_long:\n+\t\t\t\t\t\t\t*va_arg(ap,\n+\t\t\t\t\t\t\t\tsigned long *)\n+\t\t\t\t\t\t\t\t= o;\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tcase rank_longlong:\n+\t\t\t\t\t\t\t*va_arg(ap,\n+\t\t\t\t\t\t\t\tsigned long long *)\n+\t\t\t\t\t\t\t\t= o;\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t\tbreak;\n+#ifndef DISABLE_PRINT_FLOAT\n+\t\t\t\tcase 'f':\n+\t\t\t\t\t{\n+\t\t\t\t\t tmp = q;\n+\t\t\t\t\t\tq = flt(q, va_arg(ap, double), width, prec, ch, SIGN);\n+\t\t\t\t\t o += q - tmp;\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t}\n+#endif\n+\t\t\t\tdefault:\t/* Anything else, including % */\n+\t\t\t\t\tEMIT(ch);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Null-terminate the string */\n+\tif (o < n)\n+\t\t*q = '\\0';\t/* No overflow */\n+\telse if (n > 0)\n+\t\tbuffer[n - 1] = '\\0';\t/* Overflow - terminate at end of buffer */\n+\n+\treturn o;\n+}\n+\n+#ifdef SYS_BIG_DEBUG_BUFFER\n+static char string[2048];\n+#else\n+static char string[512];\n+#endif\n+\n+int vsprintf(char *buffer, const char *format, va_list ap)\n+{\n+\treturn vsnprintf(buffer, sizeof(string) - 32, format, ap);\n+}\n+\n+extern volatile bool sys_log_all_enable;\n+\n+void vprint(const char *fmt, va_list argp)\n+{\n+ char *str;\n+ int ch;\n+\n+ if (sys_log_all_enable) {\n+ str = string;\n+ if (0 < vsprintf(string, fmt, argp)) {\n+ while ('\\0' != (ch = *(str++))) {\n+#if !defined(DISABLE_PRINT)\n+ bl_uart_data_send(debug_uart_id, ch);\n+#endif\n+ }\n+ }\n+ }\n+}\n+\n+int bl_putchar(int c)\n+{\n+#if !defined(DISABLE_PRINT)\n+ bl_uart_data_send(debug_uart_id, c);\n+#endif\n+ return 0;\n+}\n+\n+int puts(const char *s)\n+{\n+ int counter = 0;\n+ char c;\n+\n+ if (sys_log_all_enable) {\n+ while ('\\0' != (c = *(s++))) {\n+#if !defined(DISABLE_PRINT)\n+ bl_uart_data_send(debug_uart_id, c);\n+#endif\n+ counter++;\n+ }\n+ }\n+ return counter;\n+}\n+\n+int printf(const char *fmt, ...)\n+{\n+ va_list argp;\n+\n+ if (sys_log_all_enable) {\n+ va_start(argp, fmt);\n+ vprint(fmt, argp);\n+ va_end(argp);\n+ }\n+\n+ return 0;\n+}\n+\n+int sprintf(char *buffer, const char *format, ...)\n+{\n+\tva_list ap;\n+\tint rv;\n+\n+\tva_start(ap, format);\n+\trv = vsnprintf(buffer, ~(size_t) 0, format, ap);\n+\tva_end(ap);\n+\n+\treturn rv;\n+}\n+\n+int snprintf(char *buffer, size_t n, const char *format, ...)\n+{\n+\tva_list ap;\n+\tint rv;\n+\n+\tva_start(ap, format);\n+\trv = vsnprintf(buffer, n, format, ap);\n+\tva_end(ap);\n+\treturn rv;\n+}\n+\n+void vMainUARTPrintString(char *pcString)\n+{\n+ puts(pcString);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f87af6e1514ecf61a22823d28d1ecc9c775b4425\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c\n@@ -0,0 +1,399 @@\n+#ifdef BL808\n+#include \"bl808.h\"\n+#include \"bl808_clock.h\"\n+#include \"bl808_pds.h\"\n+#include \"bl808_glb.h\"\n+#elif defined(BL606P)\n+#include \"bl606p.h\"\n+#include \"bl606p_clock.h\"\n+#include \"bl606p_pds.h\"\n+#include \"bl606p_glb.h\"\n+#else\n+#error \"Use CHIP BL808/BL606P for this module\"\n+#endif\n+\n+/*----------------------------------------------------------------------------\n+ Define clocks\n+ *----------------------------------------------------------------------------*/\n+#define SYSTEM_CLOCK (32000000UL)\n+\n+/*----------------------------------------------------------------------------\n+ System initialization function\n+ *----------------------------------------------------------------------------*/\n+\n+void System_BOR_Init(void)\n+{\n+ //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};\n+ //HBN_Set_BOR_Cfg(&borCfg);\n+}\n+\n+void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock)\n+{\n+ Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR;\n+\n+ CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type));\n+\n+ if (type < BL_SYSTEM_CLOCK_MAX) {\n+ pClk->systemClock[type] = clock;\n+ pClk->magic = SYS_CLOCK_CFG_MAGIC;\n+ }\n+}\n+\n+void board_init(void)\n+{\n+\n+}\n+\n+void system_init_bl606p(void)\n+#if 0\n+{\n+ uint32_t i = 0;\n+\n+ /* enable mstatus FS */\n+ uint32_t mstatus = __get_MSTATUS();\n+ mstatus |= (1 << 13);\n+ __set_MSTATUS(mstatus);\n+\n+ /* enable mxstatus THEADISAEE */\n+ uint32_t mxstatus = __get_MXSTATUS();\n+ mxstatus |= (1 << 22);\n+ /* enable mxstatus MM */\n+ mxstatus |= (1 << 15);\n+ __set_MXSTATUS(mxstatus);\n+\n+ /* get interrupt level from info */\n+ CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);\n+\n+ /* Every interrupt should be clear by software*/\n+ for (i = 0; i < IRQn_LAST; i++) {\n+ CLIC->CLICINT[i].IP = 0;\n+ CLIC->CLICINT[i].IE = 0;\n+ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */\n+ }\n+\n+ /* tspend interrupt will be clear auto*/\n+ /* tspend use positive interrupt */\n+ CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;\n+\n+#ifdef BOOTROM\n+ /* i cache enable d cache disable*/\n+ uint32_t cache;\n+ __DSB();\n+ __ISB();\n+ __ICACHE_IALL();\n+ cache = __get_MHCR();\n+ cache |= CACHE_MHCR_IE_Msk;\n+ //cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */\n+ cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */\n+ __set_MHCR(cache);\n+ __DCACHE_IALL(); /* invalidate all Cache */\n+ __DSB();\n+ __ISB();\n+ //csi_dcache_disable();\n+#else\n+ csi_icache_enable();\n+ csi_dcache_enable();\n+ /* enable preload $ AMR for D$ */\n+ __set_MHINT(0x000c);\n+#endif\n+\n+#ifndef CONFIG_OS_SUPPORT\n+ /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack */\n+ uint32_t mexstatus = __get_MEXSTATUS();\n+ mexstatus |= (0x03 << 16);\n+ __set_MEXSTATUS(mexstatus);\n+#else\n+ /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack*/\n+ uint32_t mexstatus = __get_MEXSTATUS();\n+ mexstatus |= (0x3 << 16);\n+ __set_MEXSTATUS(mexstatus);\n+#endif\n+\n+#ifdef BOOTROM\n+ extern void GLB_Power_On_LDO18_IO(void);\n+ extern void WDT_Disable(void);\n+ extern BL_Err_Type HBN_Clear_RTC_INT(void);\n+ uint32_t *p;\n+ BMX_TO_Cfg_Type bmxCfg = {\n+ .arbMod = BMX_ARB_FIX,\n+ .timeoutEn = 0x1F,\n+ //.errEn=DISABLE,\n+ };\n+\n+ /* M0 boot log Flag */\n+ extern uint32_t __bootrom_data_section_end;\n+ p = (uint32_t *)(&__bootrom_data_section_end);\n+ *p = 0x5A5AA5A5;\n+ /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,\n+\tif not disable this bit, CPU will also get hardfault at the same time*/\n+ GLB_BMX_TO_Init(&bmxCfg);\n+ //GLB_BMX_Addr_Monitor_Disable();\n+\n+ /* Do the same for L1C BMX*/\n+ //L1C_BMX_Init(&l1cBmxCfg);\n+ //L1C_BMX_Addr_Monitor_Disable();\n+\n+ /* make ram max*/\n+ //L1C_Set_Way_Disable(0x0f);\n+ //GLB_Set_EM_Sel(GLB_EM_0KB);\n+\n+ /* Disable Watchdog */\n+ WDT_Disable();\n+ /* Clear RTC */\n+ HBN_Clear_RTC_INT();\n+\n+ /*TODO*/\n+ /* Make OCRAM Idle from retention or sleep */\n+ //GLB_Set_OCRAM_Idle();\n+ //GLB_Set_SRAM_RET(0x0);\n+ //GLB_Set_SRAM_SLP(0x0);\n+ /* Disable embedded flash power up*/\n+ //HBN_Set_Embedded_Flash_Pullup(DISABLE);\n+#if 0\n+\t/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */\n+\ttmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);\n+\ttmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);\n+\tBL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);\n+\n+\t/* Restore default setting*/\n+\tGLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);\n+\tGLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);\n+\n+\t/*Power up soc 11 power domain,TODO: This should be optional */\n+\t//AON_Power_On_SOC_11();\n+\t/* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/\n+\t//BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);\n+\t/* Power up flash power*/\n+\t//GLB_Power_On_LDO18_IO();\n+\n+#endif\n+#endif\n+\n+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1);\n+ GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1);\n+\n+ /* init bor for all platform */\n+ System_BOR_Init();\n+}\n+#else\n+{\n+ uint32_t i=0;\n+\n+ /* enable mstatus FS */\n+ uint32_t mstatus = __get_MSTATUS();\n+ mstatus |= (1 << 13);\n+ __set_MSTATUS(mstatus);\n+\n+ /* enable mxstatus THEADISAEE */\n+ uint32_t mxstatus = __get_MXSTATUS();\n+ mxstatus |= (1 << 22);\n+ /* enable mxstatus MM */\n+ mxstatus |= (1 << 15);\n+ __set_MXSTATUS(mxstatus);\n+\n+ /* get interrupt level from info */\n+ CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);\n+\n+ /* Every interrupt should be clear by software*/\n+ for (i = 0; i < IRQn_LAST; i++) {\n+ CLIC->CLICINT[i].IP = 0;\n+ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */\n+ }\n+\n+ /* tspend interrupt will be clear auto*/\n+ /* tspend use positive interrupt */\n+ CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;\n+\n+ csi_dcache_enable();\n+ csi_icache_enable();\n+ /* enable preload $ AMR for D$*/\n+ __set_MHINT(0x0004);\n+ CPU_Interrupt_Enable(MSOFT_IRQn);\n+\n+ /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/\n+ uint32_t mexstatus = __get_MEXSTATUS();\n+ mexstatus &= ~(0x3 << 16);\n+ __set_MEXSTATUS(mexstatus);\n+\n+#ifdef BOOTROM\n+ extern void GLB_Power_On_LDO18_IO(void);\n+ extern void WDT_Disable(void);\n+ extern void HBN_Clear_RTC_INT(void);\n+\n+ BMX_Cfg_Type bmxCfg={\n+ .timeoutEn=0,\n+ .errEn=DISABLE,\n+ .arbMod=BMX_ARB_FIX\n+ };\n+ L1C_BMX_Cfg_Type l1cBmxCfg={\n+ .timeoutEn=0,\n+ .errEn=DISABLE,\n+ .arbMod=L1C_BMX_ARB_FIX,\n+ };\n+\n+ /* NP boot log Flag */\n+ p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);\n+ *p=0x5A5AA5A5;\n+ /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,\n+ if not disable this bit, CPU will also get hardfault at the same time*/\n+ //GLB->bmx_cfg1.BF.bmx_err_en=0;\n+ //GLB->bmx_cfg1.BF.bmx_timeout_en=0;\n+ //GLB->bmx_cfg2.BF.bmx_err_addr_dis=1;\n+ GLB_BMX_Init(&bmxCfg);\n+ GLB_BMX_Addr_Monitor_Disable();\n+ //L1C->l1c_config.BF.l1c_bmx_err_en=0;\n+ //L1C->l1c_config.BF.l1c_bmx_timeout_en=0;\n+ //L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1;\n+ L1C_BMX_Init(&l1cBmxCfg);\n+ L1C_BMX_Addr_Monitor_Disable();\n+ //L1C->l1c_config.BF.l1c_way_dis=0xf;\n+ L1C_Set_Way_Disable(0x0f);\n+ /* Disable Watchdog */\n+ WDT_Disable();\n+ /* Clear RTC */\n+ HBN_Clear_RTC_INT();\n+ /* Make OCRAM Idle from retention or sleep */\n+ GLB_Set_OCRAM_Idle();\n+ /* Disable embedded flash power up*/\n+ HBN_Set_Embedded_Flash_Pullup(DISABLE);\n+#endif\n+\n+#if 0\n+ /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */\n+ tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);\n+ tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD);\n+ BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);\n+\n+ GLB_Set_EM_Sel(GLB_EM_0KB);\n+\n+ /* Fix 26M xtal clkpll_sdmin */\n+ tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM);\n+ if(0x49D39D==BL_GET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN)){\n+ tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN,0x49D89E);\n+ BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal);\n+ }\n+\n+ /* Restore default setting*/\n+ GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);\n+ GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);\n+\n+ /* CLear all interrupt */\n+ p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE);\n+ for(i=0;i<(IRQn_LAST+3)/4;i++){\n+ p[i]=0;\n+ }\n+ p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP);\n+ for(i=0;i<(IRQn_LAST+3)/4;i++){\n+ p[i]=0;\n+ }\n+#endif\n+ /* global IRQ disable */\n+ __disable_irq();\n+\n+ //__asm volatile(\"csrw mnxti, %0\" : : \"i\"(0x1 << 3));\n+ /* init bor for all platform */\n+ //system_bor_init();\n+\n+#ifdef BOOTROM\n+ /*Power up soc 11 power domain,TODO: This should be optional */\n+ //AON_Power_On_SOC_11();\n+ /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/\n+ //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);\n+ /* Power up flash power*/\n+ //GLB_Power_On_LDO18_IO();\n+#endif\n+\n+}\n+#endif\n+\n+void System_Post_Init(void)\n+{\n+#ifndef BOOTROM\n+ //PDS_Power_On_MM_System();\n+ //FIXME\n+ GLB_Set_EM_Sel(1);\n+#endif\n+\n+ System_Interrupt_Init();\n+\n+ CPU_Interrupt_Enable(MSOFT_IRQn);\n+\n+#ifndef BOOTROM\n+ /* global IRQ enable */\n+ __enable_irq();\n+#endif\n+}\n+\n+void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\n+{\n+ csi_vic_set_prio(IRQn, PreemptPriority);\n+}\n+\n+int32_t drv_get_cpu_id(void)\n+{\n+ return __get_MHARTID();\n+}\n+\n+int32_t drv_get_cpu_freq(int32_t idx)\n+{\n+ return 32 * 1000 * 1000UL;\n+}\n+\n+#if defined(DUAL_CORE)\n+extern void Reset_Handler(void);\n+#endif\n+\n+/**\n+ \\brief enable irq.\n+ \\param[in] irq_num Number of IRQ.\n+ \\return None.\n+*/\n+__attribute__((weak)) void CPU_Interrupt_Enable(uint32_t irq_num)\n+{\n+ if (irq_num >= IRQn_LAST) {\n+ // MSG(\"Error! This interrupt don't support!\\n\");\n+ } else {\n+#ifdef CONFIG_SYSTEM_SECURE\n+ csi_vic_enable_sirq(irq_num);\n+#else\n+ csi_vic_enable_irq(irq_num);\n+#endif\n+ }\n+}\n+\n+/**\n+ \\brief disable irq.\n+ \\param[in] irq_num Number of IRQ.\n+ \\return None.\n+*/\n+__attribute__((weak)) void CPU_Interrupt_Disable(uint32_t irq_num)\n+{\n+ if (irq_num >= IRQn_LAST) {\n+ //MSG(\"Error! This interrupt don't support!\\n\");\n+ } else {\n+#ifdef CONFIG_SYSTEM_SECURE\n+ csi_vic_disable_sirq(irq_num);\n+#else\n+ csi_vic_disable_irq(irq_num);\n+#endif\n+ }\n+}\n+\n+/**\n+ \\brief Clear Pending Interrupt\n+ \\details Clear the pending bit of an external interrupt.\n+ \\param [in] IRQn External interrupt number. Value cannot be negative.\n+ */\n+__attribute__((weak)) void CPU_Interrupt_Pending_Clear(uint32_t irq_num)\n+{\n+ if (irq_num >= IRQn_LAST) {\n+ //MSG(\"Error! This interrupt don't support!\\n\");\n+ return;\n+ } else {\n+#ifdef CONFIG_SYSTEM_SECURE\n+ csi_vic_clear_pending_irq(irq_num);\n+#else\n+ csi_vic_clear_pending_irq(irq_num);\n+#endif\n+ }\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c\ndiff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..dff511ad059b4b37b9dad34552776f12d42a10ac\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c\n@@ -0,0 +1,180 @@\n+\n+#include <stdint.h>\n+#include <clic.h>\n+#include <csi_rv32_gcc.h>\n+#ifdef BL808\n+#include \"bl808.h\"\n+#elif defined(BL606P)\n+#include \"bl606p.h\"\n+#else\n+#error \"Use CHIP BL808/BL606P for this module\"\n+#endif\n+\n+\n+#define MSG(...)\n+\n+typedef void( *pFunc )( void );\n+void NMI_Handler(void);\n+\n+pFunc g_irqvector[IRQn_LAST]={0};\n+pFunc g_nmivector=NMI_Handler;\n+\n+extern void Default_IRQHandler(void);\n+extern void Default_Handler(void);\n+extern void IRQ_Handler(void);\n+\n+const pFunc __Vectors[] __attribute__ ((section(\".init\"),aligned(64))) = {\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+ IRQ_Handler, /* */\n+\n+ IRQ_Handler,//BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */\n+ IRQ_Handler,//BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */\n+ IRQ_Handler,//L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */\n+ IRQ_Handler,//L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */\n+ IRQ_Handler,//SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */\n+ IRQ_Handler,//RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */\n+ IRQ_Handler,//RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */\n+ IRQ_Handler,//SDIO_IRQHandler_Wrapper, /* 16 + 7 */\n+ IRQ_Handler,//DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */\n+ IRQ_Handler,//SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */\n+ IRQ_Handler,//SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */\n+ IRQ_Handler,//SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */\n+ IRQ_Handler,//SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */\n+ IRQ_Handler,//SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */\n+ IRQ_Handler,//SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */\n+ IRQ_Handler,//DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */\n+ IRQ_Handler,//0, /* 16 + 16 */\n+ IRQ_Handler,//0, /* 16 + 17 */\n+ IRQ_Handler,//0, /* 16 + 18 */\n+ IRQ_Handler,//IRTX_IRQHandler_Wrapper, /* 16 + 19 */\n+ IRQ_Handler,//IRRX_IRQHandler_Wrapper, /* 16 + 20 */\n+ IRQ_Handler,//0, /* 16 + 21 */\n+ IRQ_Handler,//0, /* 16 + 22 */\n+ IRQ_Handler,//SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */\n+ IRQ_Handler,//0, /* 16 + 24 */\n+ IRQ_Handler,//GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */\n+ IRQ_Handler,//EFUSE_IRQHandler_Wrapper, /* 16 + 26 */\n+ IRQ_Handler,//SPI_IRQHandler_Wrapper, /* 16 + 27 */\n+ IRQ_Handler,//0, /* 16 + 28 */\n+ IRQ_Handler,//UART0_IRQHandler_Wrapper, /* 16 + 29 */\n+ IRQ_Handler,//UART1_IRQHandler_Wrapper, /* 16 + 30 */\n+ IRQ_Handler,//0, /* 16 + 31 */\n+ IRQ_Handler,//I2C_IRQHandler_Wrapper, /* 16 + 32 */\n+ IRQ_Handler,//0, /* 16 + 33 */\n+ IRQ_Handler,//PWM_IRQHandler_Wrapper, /* 16 + 34 */\n+ IRQ_Handler,//0, /* 16 + 35 */\n+ IRQ_Handler,//TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */\n+ IRQ_Handler,//TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */\n+ IRQ_Handler,//TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */\n+ IRQ_Handler,//0, /* 16 + 39 */\n+ IRQ_Handler,//0, /* 16 + 40 */\n+ IRQ_Handler,//0, /* 16 + 41 */\n+ IRQ_Handler,//0, /* 16 + 42 */\n+ IRQ_Handler,//0, /* 16 + 43 */\n+ IRQ_Handler,//GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */\n+ IRQ_Handler,//0, /* 16 + 45 */\n+ IRQ_Handler,//0, /* 16 + 46 */\n+ IRQ_Handler,//0, /* 16 + 47 */\n+ IRQ_Handler,//0, /* 16 + 48 */\n+ IRQ_Handler,//0, /* 16 + 49 */\n+ IRQ_Handler,//PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */\n+ IRQ_Handler,//HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */\n+ IRQ_Handler,//HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */\n+ IRQ_Handler,//BOR_IRQHandler_Wrapper, /* 16 + 53 */\n+ IRQ_Handler,//WIFI_IRQHandler_Wrapper, /* 16 + 54 */\n+ IRQ_Handler,//BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */\n+ IRQ_Handler,//BLE_IRQHandler_Wrapper, /* 16 + 56 */\n+ IRQ_Handler,//MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */\n+ IRQ_Handler,//MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */\n+ IRQ_Handler,//MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */\n+ IRQ_Handler,//MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */\n+ IRQ_Handler,//MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */\n+ IRQ_Handler,//MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */\n+ IRQ_Handler,//WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */\n+};\n+\n+void trap_c(uint32_t *regs)\n+{\n+ int i;\n+ uint32_t vec = 0;\n+\n+ vec = __get_MCAUSE() & 0x3FF;\n+\n+ MSG(\"CPU Exception: NO.%d\", vec);\n+ MSG(\"\\n\");\n+\n+ for (i = 0; i < 31; i++) {\n+ MSG(\"x%d: %08x\\t\", i + 1, regs[i]);\n+\n+ if ((i % 4) == 3) {\n+ MSG(\"\\n\");\n+ }\n+ }\n+\n+ MSG(\"\\n\");\n+ MSG(\"mepc : %08x\\n\", regs[31]);\n+ MSG(\"mstatus: %08x\\n\", regs[32]);\n+\n+ //if (trap_c_callback) {\n+ // trap_c_callback();\n+ //}\n+\n+ while (1);\n+}\n+\n+void NMI_Handler(void)\n+{\n+\n+ MSG(\"NMI_Handler\\r\\n\");\n+\n+ while (1);\n+}\n+\n+void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun)\n+{\n+ if(irq<IRQn_LAST){\n+ g_irqvector[irq]=interruptFun;\n+ }\n+}\n+\n+/**\n+ \\brief enable irq.\n+ \\param[in] irq_num Number of IRQ.\n+ \\return None.\n+*/\n+void CPU_Interrupt_Enable(uint32_t irq_num)\n+{\n+#ifdef CONFIG_SYSTEM_SECURE\n+ csi_vic_enable_sirq(irq_num);\n+#else\n+ csi_vic_enable_irq(irq_num);\n+#endif\n+}\n+\n+/**\n+ \\brief disable irq.\n+ \\param[in] irq_num Number of IRQ.\n+ \\return None.\n+*/\n+void CPU_Interrupt_Disable(uint32_t irq_num)\n+{\n+#ifdef CONFIG_SYSTEM_SECURE\n+ csi_vic_disable_sirq(irq_num);\n+#else\n+ csi_vic_disable_irq(irq_num);\n+#endif\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/inc/fdt.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/fdt.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/fdt.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..cbaeae1f08cfdc6030f364dfcfaecacf9d53b2ef\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/inc/fdt.h\n@@ -0,0 +1,143 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef FDT_H\n+#define FDT_H\n+#include \"libfdt_env.h\"\n+/*\n+ * libfdt - Flat Device Tree manipulation\n+ * Copyright (C) 2006 David Gibson, IBM Corporation.\n+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.\n+ *\n+ * libfdt is dual licensed: you can use it either under the terms of\n+ * the GPL, or the BSD license, at your option.\n+ *\n+ * a) This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public\n+ * License along with this library; if not, write to the Free\n+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ *\n+ * Alternatively,\n+ *\n+ * b) Redistribution and use in source and binary forms, with or\n+ * without modification, are permitted provided that the following\n+ * conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer in the documentation and/or other materials\n+ * provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n+ * CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __ASSEMBLY__\n+\n+struct fdt_header {\n+ fdt32_t magic; /* magic word FDT_MAGIC */\n+ fdt32_t totalsize; /* total size of DT block */\n+ fdt32_t off_dt_struct; /* offset to structure */\n+ fdt32_t off_dt_strings; /* offset to strings */\n+ fdt32_t off_mem_rsvmap; /* offset to memory reserve map */\n+ fdt32_t version; /* format version */\n+ fdt32_t last_comp_version; /* last compatible version */\n+\n+ /* version 2 fields below */\n+ fdt32_t boot_cpuid_phys; /* Which physical CPU id we're\n+ booting on */\n+ /* version 3 fields below */\n+ fdt32_t size_dt_strings; /* size of the strings block */\n+\n+ /* version 17 fields below */\n+ fdt32_t size_dt_struct; /* size of the structure block */\n+};\n+\n+struct fdt_reserve_entry {\n+ fdt64_t address;\n+ fdt64_t size;\n+};\n+\n+struct fdt_node_header {\n+ fdt32_t tag;\n+ char name[0];\n+};\n+\n+struct fdt_property {\n+ fdt32_t tag;\n+ fdt32_t len;\n+ fdt32_t nameoff;\n+ char data[0];\n+};\n+\n+#endif /* !__ASSEMBLY */\n+\n+#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */\n+#define FDT_TAGSIZE sizeof(fdt32_t)\n+\n+#define FDT_BEGIN_NODE 0x1 /* Start node: full name */\n+#define FDT_END_NODE 0x2 /* End node */\n+#define FDT_PROP 0x3 /* Property: name off,\n+ size, content */\n+#define FDT_NOP 0x4 /* nop */\n+#define FDT_END 0x9\n+\n+#define FDT_V1_SIZE (7*sizeof(fdt32_t))\n+#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))\n+#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))\n+#define FDT_V16_SIZE FDT_V3_SIZE\n+#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))\n+\n+int blfdt_cli_init(void);\n+\n+#endif /* FDT_H */\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fa6154b28e4db53e7ba741b8b5bec9de014f6bf0\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt.h\n@@ -0,0 +1,1997 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef LIBFDT_H\n+#define LIBFDT_H\n+/*\n+ * libfdt - Flat Device Tree manipulation\n+ * Copyright (C) 2006 David Gibson, IBM Corporation.\n+ *\n+ * libfdt is dual licensed: you can use it either under the terms of\n+ * the GPL, or the BSD license, at your option.\n+ *\n+ * a) This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public\n+ * License along with this library; if not, write to the Free\n+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ *\n+ * Alternatively,\n+ *\n+ * b) Redistribution and use in source and binary forms, with or\n+ * without modification, are permitted provided that the following\n+ * conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer in the documentation and/or other materials\n+ * provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n+ * CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <libfdt_env.h>\n+#include <fdt.h>\n+\n+#define FDT_FIRST_SUPPORTED_VERSION 0x02\n+#define FDT_LAST_SUPPORTED_VERSION 0x11\n+\n+/* Error codes: informative error codes */\n+#define FDT_ERR_NOTFOUND 1\n+ /* FDT_ERR_NOTFOUND: The requested node or property does not exist */\n+#define FDT_ERR_EXISTS 2\n+ /* FDT_ERR_EXISTS: Attempted to create a node or property which\n+ * already exists */\n+#define FDT_ERR_NOSPACE 3\n+ /* FDT_ERR_NOSPACE: Operation needed to expand the device\n+ * tree, but its buffer did not have sufficient space to\n+ * contain the expanded tree. Use fdt_open_into() to move the\n+ * device tree to a buffer with more space. */\n+\n+/* Error codes: codes for bad parameters */\n+#define FDT_ERR_BADOFFSET 4\n+ /* FDT_ERR_BADOFFSET: Function was passed a structure block\n+ * offset which is out-of-bounds, or which points to an\n+ * unsuitable part of the structure for the operation. */\n+#define FDT_ERR_BADPATH 5\n+ /* FDT_ERR_BADPATH: Function was passed a badly formatted path\n+ * (e.g. missing a leading / for a function which requires an\n+ * absolute path) */\n+#define FDT_ERR_BADPHANDLE 6\n+ /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.\n+ * This can be caused either by an invalid phandle property\n+ * length, or the phandle value was either 0 or -1, which are\n+ * not permitted. */\n+#define FDT_ERR_BADSTATE 7\n+ /* FDT_ERR_BADSTATE: Function was passed an incomplete device\n+ * tree created by the sequential-write functions, which is\n+ * not sufficiently complete for the requested operation. */\n+\n+/* Error codes: codes for bad device tree blobs */\n+#define FDT_ERR_TRUNCATED 8\n+ /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly\n+ * terminated (overflows, goes outside allowed bounds, or\n+ * isn't properly terminated). */\n+#define FDT_ERR_BADMAGIC 9\n+ /* FDT_ERR_BADMAGIC: Given \"device tree\" appears not to be a\n+ * device tree at all - it is missing the flattened device\n+ * tree magic number. */\n+#define FDT_ERR_BADVERSION 10\n+ /* FDT_ERR_BADVERSION: Given device tree has a version which\n+ * can't be handled by the requested operation. For\n+ * read-write functions, this may mean that fdt_open_into() is\n+ * required to convert the tree to the expected version. */\n+#define FDT_ERR_BADSTRUCTURE 11\n+ /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt\n+ * structure block or other serious error (e.g. misnested\n+ * nodes, or subnodes preceding properties). */\n+#define FDT_ERR_BADLAYOUT 12\n+ /* FDT_ERR_BADLAYOUT: For read-write functions, the given\n+ * device tree has it's sub-blocks in an order that the\n+ * function can't handle (memory reserve map, then structure,\n+ * then strings). Use fdt_open_into() to reorganize the tree\n+ * into a form suitable for the read-write operations. */\n+\n+/* \"Can't happen\" error indicating a bug in libfdt */\n+#define FDT_ERR_INTERNAL 13\n+ /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.\n+ * Should never be returned, if it is, it indicates a bug in\n+ * libfdt itself. */\n+\n+/* Errors in device tree content */\n+#define FDT_ERR_BADNCELLS 14\n+ /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells\n+ * or similar property with a bad format or value */\n+\n+#define FDT_ERR_BADVALUE 15\n+ /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected\n+ * value. For example: a property expected to contain a string list\n+ * is not NUL-terminated within the length of its value. */\n+\n+#define FDT_ERR_BADOVERLAY 16\n+ /* FDT_ERR_BADOVERLAY: The device tree overlay, while\n+ * correctly structured, cannot be applied due to some\n+ * unexpected or missing value, property or node. */\n+\n+#define FDT_ERR_NOPHANDLES 17\n+ /* FDT_ERR_NOPHANDLES: The device tree doesn't have any\n+ * phandle available anymore without causing an overflow */\n+\n+#define FDT_ERR_MAX 17\n+\n+/**********************************************************************/\n+/* Low-level functions (you probably don't need these) */\n+/**********************************************************************/\n+\n+#ifndef SWIG /* This function is not useful in Python */\n+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);\n+#endif\n+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)\n+{\n+ return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);\n+}\n+\n+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);\n+\n+/*\n+ * Alignment helpers:\n+ * These helpers access words from a device tree blob. They're\n+ * built to work even with unaligned pointers on platforms (ike\n+ * ARM) that don't like unaligned loads and stores\n+ */\n+\n+static inline uint32_t fdt32_ld(const fdt32_t *p)\n+{\n+ const uint8_t *bp = (const uint8_t *)p;\n+\n+ return ((uint32_t)bp[0] << 24)\n+ | ((uint32_t)bp[1] << 16)\n+ | ((uint32_t)bp[2] << 8)\n+ | bp[3];\n+}\n+\n+static inline uint64_t fdt64_ld(const fdt64_t *p)\n+{\n+ const uint8_t *bp = (const uint8_t *)p;\n+\n+ return ((uint64_t)bp[0] << 56)\n+ | ((uint64_t)bp[1] << 48)\n+ | ((uint64_t)bp[2] << 40)\n+ | ((uint64_t)bp[3] << 32)\n+ | ((uint64_t)bp[4] << 24)\n+ | ((uint64_t)bp[5] << 16)\n+ | ((uint64_t)bp[6] << 8)\n+ | bp[7];\n+}\n+\n+/**********************************************************************/\n+/* Traversal functions */\n+/**********************************************************************/\n+\n+int fdt_next_node(const void *fdt, int offset, int *depth);\n+\n+/**\n+ * fdt_first_subnode() - get offset of first direct subnode\n+ *\n+ * @fdt: FDT blob\n+ * @offset: Offset of node to check\n+ * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none\n+ */\n+int fdt_first_subnode(const void *fdt, int offset);\n+\n+/**\n+ * fdt_next_subnode() - get offset of next direct subnode\n+ *\n+ * After first calling fdt_first_subnode(), call this function repeatedly to\n+ * get direct subnodes of a parent node.\n+ *\n+ * @fdt: FDT blob\n+ * @offset: Offset of previous subnode\n+ * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more\n+ * subnodes\n+ */\n+int fdt_next_subnode(const void *fdt, int offset);\n+\n+/**\n+ * fdt_for_each_subnode - iterate over all subnodes of a parent\n+ *\n+ * @node: child node (int, lvalue)\n+ * @fdt: FDT blob (const void *)\n+ * @parent: parent node (int)\n+ *\n+ * This is actually a wrapper around a for loop and would be used like so:\n+ *\n+ * fdt_for_each_subnode(node, fdt, parent) {\n+ * Use node\n+ * ...\n+ * }\n+ *\n+ * if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) {\n+ * Error handling\n+ * }\n+ *\n+ * Note that this is implemented as a macro and @node is used as\n+ * iterator in the loop. The parent variable be constant or even a\n+ * literal.\n+ *\n+ */\n+#define fdt_for_each_subnode(node, fdt, parent) \\\n+ for (node = fdt_first_subnode(fdt, parent); \\\n+ node >= 0; \\\n+ node = fdt_next_subnode(fdt, node))\n+\n+/**********************************************************************/\n+/* General functions */\n+/**********************************************************************/\n+#define fdt_get_header(fdt, field) \\\n+ (fdt32_ld(&((const struct fdt_header *)(fdt))->field))\n+#define fdt_magic(fdt) (fdt_get_header(fdt, magic))\n+#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize))\n+#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct))\n+#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings))\n+#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap))\n+#define fdt_version(fdt) (fdt_get_header(fdt, version))\n+#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))\n+#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))\n+#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))\n+#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct))\n+\n+#define fdt_set_hdr_(name) \\\n+ static inline void fdt_set_##name(void *fdt, uint32_t val) \\\n+ { \\\n+ struct fdt_header *fdth = (struct fdt_header *)fdt; \\\n+ fdth->name = cpu_to_fdt32(val); \\\n+ }\n+fdt_set_hdr_(magic);\n+fdt_set_hdr_(totalsize);\n+fdt_set_hdr_(off_dt_struct);\n+fdt_set_hdr_(off_dt_strings);\n+fdt_set_hdr_(off_mem_rsvmap);\n+fdt_set_hdr_(version);\n+fdt_set_hdr_(last_comp_version);\n+fdt_set_hdr_(boot_cpuid_phys);\n+fdt_set_hdr_(size_dt_strings);\n+fdt_set_hdr_(size_dt_struct);\n+#undef fdt_set_hdr_\n+\n+/**\n+ * fdt_header_size - return the size of the tree's header\n+ * @fdt: pointer to a flattened device tree\n+ */\n+size_t fdt_header_size_(uint32_t version);\n+static inline size_t fdt_header_size(const void *fdt)\n+{\n+ return fdt_header_size_(fdt_version(fdt));\n+}\n+\n+/**\n+ * fdt_check_header - sanity check a device tree header\n+\n+ * @fdt: pointer to data which might be a flattened device tree\n+ *\n+ * fdt_check_header() checks that the given buffer contains what\n+ * appears to be a flattened device tree, and that the header contains\n+ * valid information (to the extent that can be determined from the\n+ * header alone).\n+ *\n+ * returns:\n+ * 0, if the buffer appears to contain a valid device tree\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_TRUNCATED, standard meanings, as above\n+ */\n+int fdt_check_header(const void *fdt);\n+\n+/**\n+ * fdt_move - move a device tree around in memory\n+ * @fdt: pointer to the device tree to move\n+ * @buf: pointer to memory where the device is to be moved\n+ * @bufsize: size of the memory space at buf\n+ *\n+ * fdt_move() relocates, if possible, the device tree blob located at\n+ * fdt to the buffer at buf of size bufsize. The buffer may overlap\n+ * with the existing device tree blob at fdt. Therefore,\n+ * fdt_move(fdt, fdt, fdt_totalsize(fdt))\n+ * should always succeed.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE, standard meanings\n+ */\n+int fdt_move(const void *fdt, void *buf, int bufsize);\n+\n+/**********************************************************************/\n+/* Read-only functions */\n+/**********************************************************************/\n+\n+int fdt_check_full(const void *fdt, size_t bufsize);\n+\n+/**\n+ * fdt_get_string - retrieve a string from the strings block of a device tree\n+ * @fdt: pointer to the device tree blob\n+ * @stroffset: offset of the string within the strings block (native endian)\n+ * @lenp: optional pointer to return the string's length\n+ *\n+ * fdt_get_string() retrieves a pointer to a single string from the\n+ * strings block of the device tree blob at fdt, and optionally also\n+ * returns the string's length in *lenp.\n+ *\n+ * returns:\n+ * a pointer to the string, on success\n+ * NULL, if stroffset is out of bounds, or doesn't point to a valid string\n+ */\n+const char *fdt_get_string(const void *fdt, int stroffset, int *lenp);\n+\n+/**\n+ * fdt_string - retrieve a string from the strings block of a device tree\n+ * @fdt: pointer to the device tree blob\n+ * @stroffset: offset of the string within the strings block (native endian)\n+ *\n+ * fdt_string() retrieves a pointer to a single string from the\n+ * strings block of the device tree blob at fdt.\n+ *\n+ * returns:\n+ * a pointer to the string, on success\n+ * NULL, if stroffset is out of bounds, or doesn't point to a valid string\n+ */\n+const char *fdt_string(const void *fdt, int stroffset);\n+\n+/**\n+ * fdt_get_max_phandle - retrieves the highest phandle in a tree\n+ * @fdt: pointer to the device tree blob\n+ *\n+ * fdt_get_max_phandle retrieves the highest phandle in the given\n+ * device tree. This will ignore badly formatted phandles, or phandles\n+ * with a value of 0 or -1.\n+ *\n+ * returns:\n+ * the highest phandle on success\n+ * 0, if no phandle was found in the device tree\n+ * -1, if an error occurred\n+ */\n+uint32_t fdt_get_max_phandle(const void *fdt);\n+\n+/**\n+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries\n+ * @fdt: pointer to the device tree blob\n+ *\n+ * Returns the number of entries in the device tree blob's memory\n+ * reservation map. This does not include the terminating 0,0 entry\n+ * or any other (0,0) entries reserved for expansion.\n+ *\n+ * returns:\n+ * the number of entries\n+ */\n+int fdt_num_mem_rsv(const void *fdt);\n+\n+/**\n+ * fdt_get_mem_rsv - retrieve one memory reserve map entry\n+ * @fdt: pointer to the device tree blob\n+ * @address, @size: pointers to 64-bit variables\n+ *\n+ * On success, *address and *size will contain the address and size of\n+ * the n-th reserve map entry from the device tree blob, in\n+ * native-endian format.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE, standard meanings\n+ */\n+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);\n+\n+/**\n+ * fdt_subnode_offset_namelen - find a subnode based on substring\n+ * @fdt: pointer to the device tree blob\n+ * @parentoffset: structure block offset of a node\n+ * @name: name of the subnode to locate\n+ * @namelen: number of characters of name to consider\n+ *\n+ * Identical to fdt_subnode_offset(), but only examine the first\n+ * namelen characters of name for matching the subnode name. This is\n+ * useful for finding subnodes based on a portion of a larger string,\n+ * such as a full path.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,\n+ const char *name, int namelen);\n+#endif\n+/**\n+ * fdt_subnode_offset - find a subnode of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @parentoffset: structure block offset of a node\n+ * @name: name of the subnode to locate\n+ *\n+ * fdt_subnode_offset() finds a subnode of the node at structure block\n+ * offset parentoffset with the given name. name may include a unit\n+ * address, in which case fdt_subnode_offset() will find the subnode\n+ * with that unit address, or the unit address may be omitted, in\n+ * which case fdt_subnode_offset() will find an arbitrary subnode\n+ * whose name excluding unit address matches the given name.\n+ *\n+ * returns:\n+ * structure block offset of the requested subnode (>=0), on success\n+ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist\n+ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE\n+ * tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings.\n+ */\n+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);\n+\n+/**\n+ * fdt_path_offset_namelen - find a tree node by its full path\n+ * @fdt: pointer to the device tree blob\n+ * @path: full path of the node to locate\n+ * @namelen: number of characters of path to consider\n+ *\n+ * Identical to fdt_path_offset(), but only consider the first namelen\n+ * characters of path as the path name.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen);\n+#endif\n+\n+/**\n+ * fdt_path_offset - find a tree node by its full path\n+ * @fdt: pointer to the device tree blob\n+ * @path: full path of the node to locate\n+ *\n+ * fdt_path_offset() finds a node of a given path in the device tree.\n+ * Each path component may omit the unit address portion, but the\n+ * results of this are undefined if any such path component is\n+ * ambiguous (that is if there are multiple nodes at the relevant\n+ * level matching the given component, differentiated only by unit\n+ * address).\n+ *\n+ * returns:\n+ * structure block offset of the node with the requested path (>=0), on\n+ * success\n+ * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid\n+ * -FDT_ERR_NOTFOUND, if the requested node does not exist\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings.\n+ */\n+int fdt_path_offset(const void *fdt, const char *path);\n+\n+/**\n+ * fdt_get_name - retrieve the name of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: structure block offset of the starting node\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_get_name() retrieves the name (including unit address) of the\n+ * device tree node at structure block offset nodeoffset. If lenp is\n+ * non-NULL, the length of this name is also returned, in the integer\n+ * pointed to by lenp.\n+ *\n+ * returns:\n+ * pointer to the node's name, on success\n+ * If lenp is non-NULL, *lenp contains the length of that name\n+ * (>=0)\n+ * NULL, on error\n+ * if lenp is non-NULL *lenp contains an error code (<0):\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE\n+ * tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE, standard meanings\n+ */\n+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);\n+\n+/**\n+ * fdt_first_property_offset - find the offset of a node's first property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: structure block offset of a node\n+ *\n+ * fdt_first_property_offset() finds the first property of the node at\n+ * the given structure block offset.\n+ *\n+ * returns:\n+ * structure block offset of the property (>=0), on success\n+ * -FDT_ERR_NOTFOUND, if the requested node has no properties\n+ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings.\n+ */\n+int fdt_first_property_offset(const void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_next_property_offset - step through a node's properties\n+ * @fdt: pointer to the device tree blob\n+ * @offset: structure block offset of a property\n+ *\n+ * fdt_next_property_offset() finds the property immediately after the\n+ * one at the given structure block offset. This will be a property\n+ * of the same node as the given property.\n+ *\n+ * returns:\n+ * structure block offset of the next property (>=0), on success\n+ * -FDT_ERR_NOTFOUND, if the given property is the last in its node\n+ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings.\n+ */\n+int fdt_next_property_offset(const void *fdt, int offset);\n+\n+/**\n+ * fdt_for_each_property_offset - iterate over all properties of a node\n+ *\n+ * @property_offset: property offset (int, lvalue)\n+ * @fdt: FDT blob (const void *)\n+ * @node: node offset (int)\n+ *\n+ * This is actually a wrapper around a for loop and would be used like so:\n+ *\n+ * fdt_for_each_property_offset(property, fdt, node) {\n+ * Use property\n+ * ...\n+ * }\n+ *\n+ * if ((property < 0) && (property != -FDT_ERR_NOTFOUND)) {\n+ * Error handling\n+ * }\n+ *\n+ * Note that this is implemented as a macro and property is used as\n+ * iterator in the loop. The node variable can be constant or even a\n+ * literal.\n+ */\n+#define fdt_for_each_property_offset(property, fdt, node) \\\n+ for (property = fdt_first_property_offset(fdt, node); \\\n+ property >= 0; \\\n+ property = fdt_next_property_offset(fdt, property))\n+\n+/**\n+ * fdt_get_property_by_offset - retrieve the property at a given offset\n+ * @fdt: pointer to the device tree blob\n+ * @offset: offset of the property to retrieve\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_get_property_by_offset() retrieves a pointer to the\n+ * fdt_property structure within the device tree blob at the given\n+ * offset. If lenp is non-NULL, the length of the property value is\n+ * also returned, in the integer pointed to by lenp.\n+ *\n+ * Note that this code only works on device tree versions >= 16. fdt_getprop()\n+ * works on all versions.\n+ *\n+ * returns:\n+ * pointer to the structure representing the property\n+ * if lenp is non-NULL, *lenp contains the length of the property\n+ * value (>=0)\n+ * NULL, on error\n+ * if lenp is non-NULL, *lenp contains an error code (<0):\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,\n+ int offset,\n+ int *lenp);\n+\n+/**\n+ * fdt_get_property_namelen - find a property based on substring\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to find\n+ * @name: name of the property to find\n+ * @namelen: number of characters of name to consider\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * Identical to fdt_get_property(), but only examine the first namelen\n+ * characters of name for matching the property name.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+const struct fdt_property *fdt_get_property_namelen(const void *fdt,\n+ int nodeoffset,\n+ const char *name,\n+ int namelen, int *lenp);\n+#endif\n+\n+/**\n+ * fdt_get_property - find a given property in a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to find\n+ * @name: name of the property to find\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_get_property() retrieves a pointer to the fdt_property\n+ * structure within the device tree blob corresponding to the property\n+ * named 'name' of the node at offset nodeoffset. If lenp is\n+ * non-NULL, the length of the property value is also returned, in the\n+ * integer pointed to by lenp.\n+ *\n+ * returns:\n+ * pointer to the structure representing the property\n+ * if lenp is non-NULL, *lenp contains the length of the property\n+ * value (>=0)\n+ * NULL, on error\n+ * if lenp is non-NULL, *lenp contains an error code (<0):\n+ * -FDT_ERR_NOTFOUND, node does not have named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE\n+ * tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,\n+ const char *name, int *lenp);\n+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,\n+ const char *name,\n+ int *lenp)\n+{\n+ return (struct fdt_property *)(uintptr_t)\n+ fdt_get_property(fdt, nodeoffset, name, lenp);\n+}\n+\n+/**\n+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset\n+ * @fdt: pointer to the device tree blob\n+ * @offset: offset of the property to read\n+ * @namep: pointer to a string variable (will be overwritten) or NULL\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_getprop_by_offset() retrieves a pointer to the value of the\n+ * property at structure block offset 'offset' (this will be a pointer\n+ * to within the device blob itself, not a copy of the value). If\n+ * lenp is non-NULL, the length of the property value is also\n+ * returned, in the integer pointed to by lenp. If namep is non-NULL,\n+ * the property's namne will also be returned in the char * pointed to\n+ * by namep (this will be a pointer to within the device tree's string\n+ * block, not a new copy of the name).\n+ *\n+ * returns:\n+ * pointer to the property's value\n+ * if lenp is non-NULL, *lenp contains the length of the property\n+ * value (>=0)\n+ * if namep is non-NULL *namep contiains a pointer to the property\n+ * name.\n+ * NULL, on error\n+ * if lenp is non-NULL, *lenp contains an error code (<0):\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+#ifndef SWIG /* This function is not useful in Python */\n+const void *fdt_getprop_by_offset(const void *fdt, int offset,\n+ const char **namep, int *lenp);\n+#endif\n+\n+/**\n+ * fdt_getprop_namelen - get property value based on substring\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to find\n+ * @name: name of the property to find\n+ * @namelen: number of characters of name to consider\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * Identical to fdt_getprop(), but only examine the first namelen\n+ * characters of name for matching the property name.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,\n+ const char *name, int namelen, int *lenp);\n+static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset,\n+ const char *name, int namelen,\n+ int *lenp)\n+{\n+ return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name,\n+ namelen, lenp);\n+}\n+#endif\n+\n+/**\n+ * fdt_getprop - retrieve the value of a given property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to find\n+ * @name: name of the property to find\n+ * @lenp: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_getprop() retrieves a pointer to the value of the property\n+ * named 'name' of the node at offset nodeoffset (this will be a\n+ * pointer to within the device blob itself, not a copy of the value).\n+ * If lenp is non-NULL, the length of the property value is also\n+ * returned, in the integer pointed to by lenp.\n+ *\n+ * returns:\n+ * pointer to the property's value\n+ * if lenp is non-NULL, *lenp contains the length of the property\n+ * value (>=0)\n+ * NULL, on error\n+ * if lenp is non-NULL, *lenp contains an error code (<0):\n+ * -FDT_ERR_NOTFOUND, node does not have named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE\n+ * tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+const void *fdt_getprop(const void *fdt, int nodeoffset,\n+ const char *name, int *lenp);\n+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,\n+ const char *name, int *lenp)\n+{\n+ return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);\n+}\n+\n+/**\n+ * fdt_get_phandle - retrieve the phandle of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: structure block offset of the node\n+ *\n+ * fdt_get_phandle() retrieves the phandle of the device tree node at\n+ * structure block offset nodeoffset.\n+ *\n+ * returns:\n+ * the phandle of the node at nodeoffset, on success (!= 0, != -1)\n+ * 0, if the node has no phandle, or another error occurs\n+ */\n+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_get_alias_namelen - get alias based on substring\n+ * @fdt: pointer to the device tree blob\n+ * @name: name of the alias th look up\n+ * @namelen: number of characters of name to consider\n+ *\n+ * Identical to fdt_get_alias(), but only examine the first namelen\n+ * characters of name for matching the alias name.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+const char *fdt_get_alias_namelen(const void *fdt,\n+ const char *name, int namelen);\n+#endif\n+\n+/**\n+ * fdt_get_alias - retrieve the path referenced by a given alias\n+ * @fdt: pointer to the device tree blob\n+ * @name: name of the alias th look up\n+ *\n+ * fdt_get_alias() retrieves the value of a given alias. That is, the\n+ * value of the property named 'name' in the node /aliases.\n+ *\n+ * returns:\n+ * a pointer to the expansion of the alias named 'name', if it exists\n+ * NULL, if the given alias or the /aliases node does not exist\n+ */\n+const char *fdt_get_alias(const void *fdt, const char *name);\n+\n+/**\n+ * fdt_get_path - determine the full path of a node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose path to find\n+ * @buf: character buffer to contain the returned path (will be overwritten)\n+ * @buflen: size of the character buffer at buf\n+ *\n+ * fdt_get_path() computes the full path of the node at offset\n+ * nodeoffset, and records that path in the buffer at buf.\n+ *\n+ * NOTE: This function is expensive, as it must scan the device tree\n+ * structure from the start to nodeoffset.\n+ *\n+ * returns:\n+ * 0, on success\n+ * buf contains the absolute path of the node at\n+ * nodeoffset, as a NUL-terminated string.\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)\n+ * characters and will not fit in the given buffer.\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);\n+\n+/**\n+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose parent to find\n+ * @supernodedepth: depth of the ancestor to find\n+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL\n+ *\n+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node\n+ * at a specific depth from the root (where the root itself has depth\n+ * 0, its immediate subnodes depth 1 and so forth). So\n+ * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);\n+ * will always return 0, the offset of the root node. If the node at\n+ * nodeoffset has depth D, then:\n+ * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);\n+ * will return nodeoffset itself.\n+ *\n+ * NOTE: This function is expensive, as it must scan the device tree\n+ * structure from the start to nodeoffset.\n+ *\n+ * returns:\n+ * structure block offset of the node at node offset's ancestor\n+ * of depth supernodedepth (>=0), on success\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of\n+ * nodeoffset\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,\n+ int supernodedepth, int *nodedepth);\n+\n+/**\n+ * fdt_node_depth - find the depth of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose parent to find\n+ *\n+ * fdt_node_depth() finds the depth of a given node. The root node\n+ * has depth 0, its immediate subnodes depth 1 and so forth.\n+ *\n+ * NOTE: This function is expensive, as it must scan the device tree\n+ * structure from the start to nodeoffset.\n+ *\n+ * returns:\n+ * depth of the node at nodeoffset (>=0), on success\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_node_depth(const void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_parent_offset - find the parent of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose parent to find\n+ *\n+ * fdt_parent_offset() locates the parent node of a given node (that\n+ * is, it finds the offset of the node which contains the node at\n+ * nodeoffset as a subnode).\n+ *\n+ * NOTE: This function is expensive, as it must scan the device tree\n+ * structure from the start to nodeoffset, *twice*.\n+ *\n+ * returns:\n+ * structure block offset of the parent of the node at nodeoffset\n+ * (>=0), on success\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_parent_offset(const void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_node_offset_by_prop_value - find nodes with a given property value\n+ * @fdt: pointer to the device tree blob\n+ * @startoffset: only find nodes after this offset\n+ * @propname: property name to check\n+ * @propval: property value to search for\n+ * @proplen: length of the value in propval\n+ *\n+ * fdt_node_offset_by_prop_value() returns the offset of the first\n+ * node after startoffset, which has a property named propname whose\n+ * value is of length proplen and has value equal to propval; or if\n+ * startoffset is -1, the very first such node in the tree.\n+ *\n+ * To iterate through all nodes matching the criterion, the following\n+ * idiom can be used:\n+ * offset = fdt_node_offset_by_prop_value(fdt, -1, propname,\n+ * propval, proplen);\n+ * while (offset != -FDT_ERR_NOTFOUND) {\n+ * // other code here\n+ * offset = fdt_node_offset_by_prop_value(fdt, offset, propname,\n+ * propval, proplen);\n+ * }\n+ *\n+ * Note the -1 in the first call to the function, if 0 is used here\n+ * instead, the function will never locate the root node, even if it\n+ * matches the criterion.\n+ *\n+ * returns:\n+ * structure block offset of the located node (>= 0, >startoffset),\n+ * on success\n+ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the\n+ * tree after startoffset\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,\n+ const char *propname,\n+ const void *propval, int proplen);\n+\n+/**\n+ * fdt_node_offset_by_phandle - find the node with a given phandle\n+ * @fdt: pointer to the device tree blob\n+ * @phandle: phandle value\n+ *\n+ * fdt_node_offset_by_phandle() returns the offset of the node\n+ * which has the given phandle value. If there is more than one node\n+ * in the tree with the given phandle (an invalid tree), results are\n+ * undefined.\n+ *\n+ * returns:\n+ * structure block offset of the located node (>= 0), on success\n+ * -FDT_ERR_NOTFOUND, no node with that phandle exists\n+ * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);\n+\n+/**\n+ * fdt_node_check_compatible: check a node's compatible property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of a tree node\n+ * @compatible: string to match against\n+ *\n+ *\n+ * fdt_node_check_compatible() returns 0 if the given node contains a\n+ * 'compatible' property with the given string as one of its elements,\n+ * it returns non-zero otherwise, or on error.\n+ *\n+ * returns:\n+ * 0, if the node has a 'compatible' property listing the given string\n+ * 1, if the node has a 'compatible' property, but it does not list\n+ * the given string\n+ * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property\n+ * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_node_check_compatible(const void *fdt, int nodeoffset,\n+ const char *compatible);\n+\n+/**\n+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value\n+ * @fdt: pointer to the device tree blob\n+ * @startoffset: only find nodes after this offset\n+ * @compatible: 'compatible' string to match against\n+ *\n+ * fdt_node_offset_by_compatible() returns the offset of the first\n+ * node after startoffset, which has a 'compatible' property which\n+ * lists the given compatible string; or if startoffset is -1, the\n+ * very first such node in the tree.\n+ *\n+ * To iterate through all nodes matching the criterion, the following\n+ * idiom can be used:\n+ * offset = fdt_node_offset_by_compatible(fdt, -1, compatible);\n+ * while (offset != -FDT_ERR_NOTFOUND) {\n+ * // other code here\n+ * offset = fdt_node_offset_by_compatible(fdt, offset, compatible);\n+ * }\n+ *\n+ * Note the -1 in the first call to the function, if 0 is used here\n+ * instead, the function will never locate the root node, even if it\n+ * matches the criterion.\n+ *\n+ * returns:\n+ * structure block offset of the located node (>= 0, >startoffset),\n+ * on success\n+ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the\n+ * tree after startoffset\n+ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE, standard meanings\n+ */\n+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,\n+ const char *compatible);\n+\n+/**\n+ * fdt_stringlist_contains - check a string list property for a string\n+ * @strlist: Property containing a list of strings to check\n+ * @listlen: Length of property\n+ * @str: String to search for\n+ *\n+ * This is a utility function provided for convenience. The list contains\n+ * one or more strings, each terminated by \\0, as is found in a device tree\n+ * \"compatible\" property.\n+ *\n+ * @return: 1 if the string is found in the list, 0 not found, or invalid list\n+ */\n+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);\n+\n+/**\n+ * fdt_stringlist_count - count the number of strings in a string list\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of a tree node\n+ * @property: name of the property containing the string list\n+ * @return:\n+ * the number of strings in the given property\n+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated\n+ * -FDT_ERR_NOTFOUND if the property does not exist\n+ */\n+int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property);\n+\n+/**\n+ * fdt_stringlist_search - find a string in a string list and return its index\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of a tree node\n+ * @property: name of the property containing the string list\n+ * @string: string to look up in the string list\n+ *\n+ * Note that it is possible for this function to succeed on property values\n+ * that are not NUL-terminated. That's because the function will stop after\n+ * finding the first occurrence of @string. This can for example happen with\n+ * small-valued cell properties, such as #address-cells, when searching for\n+ * the empty string.\n+ *\n+ * @return:\n+ * the index of the string in the list of strings\n+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated\n+ * -FDT_ERR_NOTFOUND if the property does not exist or does not contain\n+ * the given string\n+ */\n+int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,\n+ const char *string);\n+\n+/**\n+ * fdt_stringlist_get() - obtain the string at a given index in a string list\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of a tree node\n+ * @property: name of the property containing the string list\n+ * @index: index of the string to return\n+ * @lenp: return location for the string length or an error code on failure\n+ *\n+ * Note that this will successfully extract strings from properties with\n+ * non-NUL-terminated values. For example on small-valued cell properties\n+ * this function will return the empty string.\n+ *\n+ * If non-NULL, the length of the string (on success) or a negative error-code\n+ * (on failure) will be stored in the integer pointer to by lenp.\n+ *\n+ * @return:\n+ * A pointer to the string at the given index in the string list or NULL on\n+ * failure. On success the length of the string will be stored in the memory\n+ * location pointed to by the lenp parameter, if non-NULL. On failure one of\n+ * the following negative error codes will be returned in the lenp parameter\n+ * (if non-NULL):\n+ * -FDT_ERR_BADVALUE if the property value is not NUL-terminated\n+ * -FDT_ERR_NOTFOUND if the property does not exist\n+ */\n+const char *fdt_stringlist_get(const void *fdt, int nodeoffset,\n+ const char *property, int index,\n+ int *lenp);\n+\n+/**********************************************************************/\n+/* Read-only functions (addressing related) */\n+/**********************************************************************/\n+\n+/**\n+ * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells\n+ *\n+ * This is the maximum value for #address-cells, #size-cells and\n+ * similar properties that will be processed by libfdt. IEE1275\n+ * requires that OF implementations handle values up to 4.\n+ * Implementations may support larger values, but in practice higher\n+ * values aren't used.\n+ */\n+#define FDT_MAX_NCELLS 4\n+\n+/**\n+ * fdt_address_cells - retrieve address size for a bus represented in the tree\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node to find the address size for\n+ *\n+ * When the node has a valid #address-cells property, returns its value.\n+ *\n+ * returns:\n+ * 0 <= n < FDT_MAX_NCELLS, on success\n+ * 2, if the node has no #address-cells property\n+ * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid\n+ * #address-cells property\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_address_cells(const void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_size_cells - retrieve address range size for a bus represented in the\n+ * tree\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node to find the address range size for\n+ *\n+ * When the node has a valid #size-cells property, returns its value.\n+ *\n+ * returns:\n+ * 0 <= n < FDT_MAX_NCELLS, on success\n+ * 1, if the node has no #size-cells property\n+ * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid\n+ * #size-cells property\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_size_cells(const void *fdt, int nodeoffset);\n+\n+\n+/**********************************************************************/\n+/* Write-in-place functions */\n+/**********************************************************************/\n+\n+/**\n+ * fdt_setprop_inplace_namelen_partial - change a property's value,\n+ * but not its size\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @namelen: number of characters of name to consider\n+ * @idx: index of the property to change in the array\n+ * @val: pointer to data to replace the property value with\n+ * @len: length of the property value\n+ *\n+ * Identical to fdt_setprop_inplace(), but modifies the given property\n+ * starting from the given index, and using only the first characters\n+ * of the name. It is useful when you want to manipulate only one value of\n+ * an array and you have a string that doesn't end with \\0.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,\n+ const char *name, int namelen,\n+ uint32_t idx, const void *val,\n+ int len);\n+#endif\n+\n+/**\n+ * fdt_setprop_inplace - change a property's value, but not its size\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: pointer to data to replace the property value with\n+ * @len: length of the property value\n+ *\n+ * fdt_setprop_inplace() replaces the value of a given property with\n+ * the data in val, of length len. This function cannot change the\n+ * size of a property, and so will only work if len is equal to the\n+ * current length of the property.\n+ *\n+ * This function will alter only the bytes in the blob which contain\n+ * the given property value, and will not alter or move any other part\n+ * of the tree.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, if len is not equal to the property's current length\n+ * -FDT_ERR_NOTFOUND, node does not have the named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+#ifndef SWIG /* Not available in Python */\n+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len);\n+#endif\n+\n+/**\n+ * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 32-bit integer value to replace the property with\n+ *\n+ * fdt_setprop_inplace_u32() replaces the value of a given property\n+ * with the 32-bit integer value in val, converting val to big-endian\n+ * if necessary. This function cannot change the size of a property,\n+ * and so will only work if the property already exists and has length\n+ * 4.\n+ *\n+ * This function will alter only the bytes in the blob which contain\n+ * the given property value, and will not alter or move any other part\n+ * of the tree.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, if the property's length is not equal to 4\n+ * -FDT_ERR_NOTFOUND, node does not have the named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,\n+ const char *name, uint32_t val)\n+{\n+ fdt32_t tmp = cpu_to_fdt32(val);\n+ return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 64-bit integer value to replace the property with\n+ *\n+ * fdt_setprop_inplace_u64() replaces the value of a given property\n+ * with the 64-bit integer value in val, converting val to big-endian\n+ * if necessary. This function cannot change the size of a property,\n+ * and so will only work if the property already exists and has length\n+ * 8.\n+ *\n+ * This function will alter only the bytes in the blob which contain\n+ * the given property value, and will not alter or move any other part\n+ * of the tree.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, if the property's length is not equal to 8\n+ * -FDT_ERR_NOTFOUND, node does not have the named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,\n+ const char *name, uint64_t val)\n+{\n+ fdt64_t tmp = cpu_to_fdt64(val);\n+ return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_setprop_inplace_cell - change the value of a single-cell property\n+ *\n+ * This is an alternative name for fdt_setprop_inplace_u32()\n+ */\n+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,\n+ const char *name, uint32_t val)\n+{\n+ return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);\n+}\n+\n+/**\n+ * fdt_nop_property - replace a property with nop tags\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to nop\n+ * @name: name of the property to nop\n+ *\n+ * fdt_nop_property() will replace a given property's representation\n+ * in the blob with FDT_NOP tags, effectively removing it from the\n+ * tree.\n+ *\n+ * This function will alter only the bytes in the blob which contain\n+ * the property, and will not alter or move any other part of the\n+ * tree.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOTFOUND, node does not have the named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);\n+\n+/**\n+ * fdt_nop_node - replace a node (subtree) with nop tags\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node to nop\n+ *\n+ * fdt_nop_node() will replace a given node's representation in the\n+ * blob, including all its subnodes, if any, with FDT_NOP tags,\n+ * effectively removing it from the tree.\n+ *\n+ * This function will alter only the bytes in the blob which contain\n+ * the node and its properties and subnodes, and will not alter or\n+ * move any other part of the tree.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_nop_node(void *fdt, int nodeoffset);\n+\n+/**********************************************************************/\n+/* Sequential write functions */\n+/**********************************************************************/\n+\n+int fdt_create(void *buf, int bufsize);\n+int fdt_resize(void *fdt, void *buf, int bufsize);\n+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);\n+int fdt_finish_reservemap(void *fdt);\n+int fdt_begin_node(void *fdt, const char *name);\n+int fdt_property(void *fdt, const char *name, const void *val, int len);\n+static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)\n+{\n+ fdt32_t tmp = cpu_to_fdt32(val);\n+ return fdt_property(fdt, name, &tmp, sizeof(tmp));\n+}\n+static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)\n+{\n+ fdt64_t tmp = cpu_to_fdt64(val);\n+ return fdt_property(fdt, name, &tmp, sizeof(tmp));\n+}\n+\n+#ifndef SWIG /* Not available in Python */\n+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)\n+{\n+ return fdt_property_u32(fdt, name, val);\n+}\n+#endif\n+\n+/**\n+ * fdt_property_placeholder - add a new property and return a ptr to its value\n+ *\n+ * @fdt: pointer to the device tree blob\n+ * @name: name of property to add\n+ * @len: length of property value in bytes\n+ * @valp: returns a pointer to where where the value should be placed\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_NOSPACE, standard meanings\n+ */\n+int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp);\n+\n+#define fdt_property_string(fdt, name, str) \\\n+ fdt_property(fdt, name, str, strlen(str)+1)\n+int fdt_end_node(void *fdt);\n+int fdt_finish(void *fdt);\n+\n+/**********************************************************************/\n+/* Read-write functions */\n+/**********************************************************************/\n+\n+int fdt_create_empty_tree(void *buf, int bufsize);\n+int fdt_open_into(const void *fdt, void *buf, int bufsize);\n+int fdt_pack(void *fdt);\n+\n+/**\n+ * fdt_add_mem_rsv - add one memory reserve map entry\n+ * @fdt: pointer to the device tree blob\n+ * @address, @size: 64-bit values (native endian)\n+ *\n+ * Adds a reserve map entry to the given blob reserving a region at\n+ * address address of length size.\n+ *\n+ * This function will insert data into the reserve map and will\n+ * therefore change the indexes of some entries in the table.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new reservation entry\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);\n+\n+/**\n+ * fdt_del_mem_rsv - remove a memory reserve map entry\n+ * @fdt: pointer to the device tree blob\n+ * @n: entry to remove\n+ *\n+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from\n+ * the blob.\n+ *\n+ * This function will delete data from the reservation table and will\n+ * therefore change the indexes of some entries in the table.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there\n+ * are less than n+1 reserve map entries)\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_del_mem_rsv(void *fdt, int n);\n+\n+/**\n+ * fdt_set_name - change the name of a given node\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: structure block offset of a node\n+ * @name: name to give the node\n+ *\n+ * fdt_set_name() replaces the name (including unit address, if any)\n+ * of the given node with the given string. NOTE: this function can't\n+ * efficiently check if the new name is unique amongst the given\n+ * node's siblings; results are undefined if this function is invoked\n+ * with a name equal to one of the given node's siblings.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob\n+ * to contain the new name\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE, standard meanings\n+ */\n+int fdt_set_name(void *fdt, int nodeoffset, const char *name);\n+\n+/**\n+ * fdt_setprop - create or change a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: pointer to data to set the property value to\n+ * @len: length of the property value\n+ *\n+ * fdt_setprop() sets the value of the named property in the given\n+ * node to the given value and length, creating the property if it\n+ * does not already exist.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_setprop(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len);\n+\n+/**\n+ * fdt_setprop_placeholder - allocate space for a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @len: length of the property value\n+ * @prop_data: return pointer to property data\n+ *\n+ * fdt_setprop_placeholer() allocates the named property in the given node.\n+ * If the property exists it is resized. In either case a pointer to the\n+ * property data is returned.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,\n+ int len, void **prop_data);\n+\n+/**\n+ * fdt_setprop_u32 - set a property to a 32-bit integer\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 32-bit integer value for the property (native endian)\n+ *\n+ * fdt_setprop_u32() sets the value of the named property in the given\n+ * node to the given 32-bit integer value (converting to big-endian if\n+ * necessary), or creates a new property with that value if it does\n+ * not already exist.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,\n+ uint32_t val)\n+{\n+ fdt32_t tmp = cpu_to_fdt32(val);\n+ return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_setprop_u64 - set a property to a 64-bit integer\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 64-bit integer value for the property (native endian)\n+ *\n+ * fdt_setprop_u64() sets the value of the named property in the given\n+ * node to the given 64-bit integer value (converting to big-endian if\n+ * necessary), or creates a new property with that value if it does\n+ * not already exist.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,\n+ uint64_t val)\n+{\n+ fdt64_t tmp = cpu_to_fdt64(val);\n+ return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_setprop_cell - set a property to a single cell value\n+ *\n+ * This is an alternative name for fdt_setprop_u32()\n+ */\n+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,\n+ uint32_t val)\n+{\n+ return fdt_setprop_u32(fdt, nodeoffset, name, val);\n+}\n+\n+/**\n+ * fdt_setprop_string - set a property to a string value\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @str: string value for the property\n+ *\n+ * fdt_setprop_string() sets the value of the named property in the\n+ * given node to the given string value (using the length of the\n+ * string to determine the new length of the property), or creates a\n+ * new property with that value if it does not already exist.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+#define fdt_setprop_string(fdt, nodeoffset, name, str) \\\n+ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)\n+\n+\n+/**\n+ * fdt_setprop_empty - set a property to an empty value\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ *\n+ * fdt_setprop_empty() sets the value of the named property in the\n+ * given node to an empty (zero length) value, or creates a new empty\n+ * property if it does not already exist.\n+ *\n+ * This function may insert or delete data from the blob, and will\n+ * therefore change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+#define fdt_setprop_empty(fdt, nodeoffset, name) \\\n+ fdt_setprop((fdt), (nodeoffset), (name), NULL, 0)\n+\n+/**\n+ * fdt_appendprop - append to or create a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to append to\n+ * @val: pointer to data to append to the property value\n+ * @len: length of the data to append to the property value\n+ *\n+ * fdt_appendprop() appends the value to the named property in the\n+ * given node, creating the property if it does not already exist.\n+ *\n+ * This function may insert data into the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_appendprop(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len);\n+\n+/**\n+ * fdt_appendprop_u32 - append a 32-bit integer value to a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 32-bit integer value to append to the property (native endian)\n+ *\n+ * fdt_appendprop_u32() appends the given 32-bit integer value\n+ * (converting to big-endian if necessary) to the value of the named\n+ * property in the given node, or creates a new property with that\n+ * value if it does not already exist.\n+ *\n+ * This function may insert data into the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,\n+ const char *name, uint32_t val)\n+{\n+ fdt32_t tmp = cpu_to_fdt32(val);\n+ return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_appendprop_u64 - append a 64-bit integer value to a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @val: 64-bit integer value to append to the property (native endian)\n+ *\n+ * fdt_appendprop_u64() appends the given 64-bit integer value\n+ * (converting to big-endian if necessary) to the value of the named\n+ * property in the given node, or creates a new property with that\n+ * value if it does not already exist.\n+ *\n+ * This function may insert data into the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,\n+ const char *name, uint64_t val)\n+{\n+ fdt64_t tmp = cpu_to_fdt64(val);\n+ return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));\n+}\n+\n+/**\n+ * fdt_appendprop_cell - append a single cell value to a property\n+ *\n+ * This is an alternative name for fdt_appendprop_u32()\n+ */\n+static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,\n+ const char *name, uint32_t val)\n+{\n+ return fdt_appendprop_u32(fdt, nodeoffset, name, val);\n+}\n+\n+/**\n+ * fdt_appendprop_string - append a string to a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to change\n+ * @name: name of the property to change\n+ * @str: string value to append to the property\n+ *\n+ * fdt_appendprop_string() appends the given string to the value of\n+ * the named property in the given node, or creates a new property\n+ * with that value if it does not already exist.\n+ *\n+ * This function may insert data into the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to\n+ * contain the new property value\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+#define fdt_appendprop_string(fdt, nodeoffset, name, str) \\\n+ fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)\n+\n+/**\n+ * fdt_delprop - delete a property\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node whose property to nop\n+ * @name: name of the property to nop\n+ *\n+ * fdt_del_property() will delete the given property.\n+ *\n+ * This function will delete data from the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOTFOUND, node does not have the named property\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_delprop(void *fdt, int nodeoffset, const char *name);\n+\n+/**\n+ * fdt_add_subnode_namelen - creates a new node based on substring\n+ * @fdt: pointer to the device tree blob\n+ * @parentoffset: structure block offset of a node\n+ * @name: name of the subnode to locate\n+ * @namelen: number of characters of name to consider\n+ *\n+ * Identical to fdt_add_subnode(), but use only the first namelen\n+ * characters of name as the name of the new node. This is useful for\n+ * creating subnodes based on a portion of a larger string, such as a\n+ * full path.\n+ */\n+#ifndef SWIG /* Not available in Python */\n+int fdt_add_subnode_namelen(void *fdt, int parentoffset,\n+ const char *name, int namelen);\n+#endif\n+\n+/**\n+ * fdt_add_subnode - creates a new node\n+ * @fdt: pointer to the device tree blob\n+ * @parentoffset: structure block offset of a node\n+ * @name: name of the subnode to locate\n+ *\n+ * fdt_add_subnode() creates a new node as a subnode of the node at\n+ * structure block offset parentoffset, with the given name (which\n+ * should include the unit address, if any).\n+ *\n+ * This function will insert data into the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+\n+ * returns:\n+ * structure block offset of the created nodeequested subnode (>=0), on\n+ * success\n+ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist\n+ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE\n+ * tag\n+ * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of\n+ * the given name\n+ * -FDT_ERR_NOSPACE, if there is insufficient free space in the\n+ * blob to contain the new node\n+ * -FDT_ERR_NOSPACE\n+ * -FDT_ERR_BADLAYOUT\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings.\n+ */\n+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);\n+\n+/**\n+ * fdt_del_node - delete a node (subtree)\n+ * @fdt: pointer to the device tree blob\n+ * @nodeoffset: offset of the node to nop\n+ *\n+ * fdt_del_node() will remove the given node, including all its\n+ * subnodes if any, from the blob.\n+ *\n+ * This function will delete data from the blob, and will therefore\n+ * change the offsets of some existing nodes.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_del_node(void *fdt, int nodeoffset);\n+\n+/**\n+ * fdt_overlay_apply - Applies a DT overlay on a base DT\n+ * @fdt: pointer to the base device tree blob\n+ * @fdto: pointer to the device tree overlay blob\n+ *\n+ * fdt_overlay_apply() will apply the given device tree overlay on the\n+ * given base device tree.\n+ *\n+ * Expect the base device tree to be modified, even if the function\n+ * returns an error.\n+ *\n+ * returns:\n+ * 0, on success\n+ * -FDT_ERR_NOSPACE, there's not enough space in the base device tree\n+ * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or\n+ * properties in the base DT\n+ * -FDT_ERR_BADPHANDLE,\n+ * -FDT_ERR_BADOVERLAY,\n+ * -FDT_ERR_NOPHANDLES,\n+ * -FDT_ERR_INTERNAL,\n+ * -FDT_ERR_BADLAYOUT,\n+ * -FDT_ERR_BADMAGIC,\n+ * -FDT_ERR_BADOFFSET,\n+ * -FDT_ERR_BADPATH,\n+ * -FDT_ERR_BADVERSION,\n+ * -FDT_ERR_BADSTRUCTURE,\n+ * -FDT_ERR_BADSTATE,\n+ * -FDT_ERR_TRUNCATED, standard meanings\n+ */\n+int fdt_overlay_apply(void *fdt, void *fdto);\n+\n+/**********************************************************************/\n+/* Debugging / informational functions */\n+/**********************************************************************/\n+\n+const char *fdt_strerror(int errval);\n+\n+#endif /* LIBFDT_H */\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e7a0e02f55527cf8a66053faa5904f05f7479558\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h\n@@ -0,0 +1,169 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef LIBFDT_ENV_H\n+#define LIBFDT_ENV_H\n+/*\n+ * libfdt - Flat Device Tree manipulation\n+ * Copyright (C) 2006 David Gibson, IBM Corporation.\n+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.\n+ *\n+ * libfdt is dual licensed: you can use it either under the terms of\n+ * the GPL, or the BSD license, at your option.\n+ *\n+ * a) This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public\n+ * License along with this library; if not, write to the Free\n+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ *\n+ * Alternatively,\n+ *\n+ * b) Redistribution and use in source and binary forms, with or\n+ * without modification, are permitted provided that the following\n+ * conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer in the documentation and/or other materials\n+ * provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n+ * CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <limits.h>\n+\n+#ifdef __CHECKER__\n+#define FDT_FORCE __attribute__((force))\n+#define FDT_BITWISE __attribute__((bitwise))\n+#else\n+#define FDT_FORCE\n+#define FDT_BITWISE\n+#endif\n+\n+typedef uint16_t FDT_BITWISE fdt16_t;\n+typedef uint32_t FDT_BITWISE fdt32_t;\n+typedef uint64_t FDT_BITWISE fdt64_t;\n+\n+#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n])\n+#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1))\n+#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \\\n+ (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))\n+#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \\\n+ (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \\\n+ (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \\\n+ (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7))\n+\n+static inline uint16_t fdt16_to_cpu(fdt16_t x)\n+{\n+ return (FDT_FORCE uint16_t)CPU_TO_FDT16(x);\n+}\n+static inline fdt16_t cpu_to_fdt16(uint16_t x)\n+{\n+ return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x);\n+}\n+\n+static inline uint32_t fdt32_to_cpu(fdt32_t x)\n+{\n+ return (FDT_FORCE uint32_t)CPU_TO_FDT32(x);\n+}\n+static inline fdt32_t cpu_to_fdt32(uint32_t x)\n+{\n+ return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x);\n+}\n+\n+static inline uint64_t fdt64_to_cpu(fdt64_t x)\n+{\n+ return (FDT_FORCE uint64_t)CPU_TO_FDT64(x);\n+}\n+static inline fdt64_t cpu_to_fdt64(uint64_t x)\n+{\n+ return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x);\n+}\n+#undef CPU_TO_FDT64\n+#undef CPU_TO_FDT32\n+#undef CPU_TO_FDT16\n+#undef EXTRACT_BYTE\n+\n+#ifdef __APPLE__\n+#include <AvailabilityMacros.h>\n+\n+/* strnlen() is not available on Mac OS < 10.7 */\n+# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \\\n+ MAC_OS_X_VERSION_10_7)\n+\n+#define strnlen fdt_strnlen\n+\n+/*\n+ * fdt_strnlen: returns the length of a string or max_count - which ever is\n+ * smallest.\n+ * Input 1 string: the string whose size is to be determined\n+ * Input 2 max_count: the maximum value returned by this function\n+ * Output: length of the string or max_count (the smallest of the two)\n+ */\n+static inline size_t fdt_strnlen(const char *string, size_t max_count)\n+{\n+ const char *p = memchr(string, 0, max_count);\n+ return p ? p - string : max_count;\n+}\n+\n+#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED <\n+ MAC_OS_X_VERSION_10_7) */\n+\n+#endif /* __APPLE__ */\n+\n+#endif /* LIBFDT_ENV_H */\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..dec0382a0c18b8780d47d760f182a48347704d12\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h\n@@ -0,0 +1,125 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef LIBFDT_INTERNAL_H\n+#define LIBFDT_INTERNAL_H\n+/*\n+ * libfdt - Flat Device Tree manipulation\n+ * Copyright (C) 2006 David Gibson, IBM Corporation.\n+ *\n+ * libfdt is dual licensed: you can use it either under the terms of\n+ * the GPL, or the BSD license, at your option.\n+ *\n+ * a) This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public\n+ * License along with this library; if not, write to the Free\n+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ *\n+ * Alternatively,\n+ *\n+ * b) Redistribution and use in source and binary forms, with or\n+ * without modification, are permitted provided that the following\n+ * conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above\n+ * copyright notice, this list of conditions and the following\n+ * disclaimer in the documentation and/or other materials\n+ * provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n+ * CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <fdt.h>\n+\n+#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))\n+#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE))\n+\n+int fdt_ro_probe_(const void *fdt);\n+#define FDT_RO_PROBE(fdt) \\\n+ { \\\n+ int err_; \\\n+ if ((err_ = fdt_ro_probe_(fdt)) != 0) \\\n+ return err_; \\\n+ }\n+\n+int fdt_check_node_offset_(const void *fdt, int offset);\n+int fdt_check_prop_offset_(const void *fdt, int offset);\n+const char *fdt_find_string_(const char *strtab, int tabsize, const char *s);\n+int fdt_node_end_offset_(void *fdt, int nodeoffset);\n+\n+static inline const void *fdt_offset_ptr_(const void *fdt, int offset)\n+{\n+ return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;\n+}\n+\n+static inline void *fdt_offset_ptr_w_(void *fdt, int offset)\n+{\n+ return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset);\n+}\n+\n+static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n)\n+{\n+ const struct fdt_reserve_entry *rsv_table =\n+ (const struct fdt_reserve_entry *)\n+ ((const char *)fdt + fdt_off_mem_rsvmap(fdt));\n+\n+ return rsv_table + n;\n+}\n+static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n)\n+{\n+ return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n);\n+}\n+\n+#define FDT_SW_MAGIC (~FDT_MAGIC)\n+\n+#endif /* LIBFDT_INTERNAL_H */\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f77dc17a6cefd5b4438b6898e9e37614c8f0bf3d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c\n@@ -0,0 +1,310 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+/*\n+ * Minimal sanity check for a read-only tree. fdt_ro_probe_() checks\n+ * that the given buffer contains what appears to be a flattened\n+ * device tree with sane information in its header.\n+ */\n+int fdt_ro_probe_(const void *fdt)\n+{\n+ if (fdt_magic(fdt) == FDT_MAGIC) {\n+ /* Complete tree */\n+ if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)\n+ return -FDT_ERR_BADVERSION;\n+ if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)\n+ return -FDT_ERR_BADVERSION;\n+ } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {\n+ /* Unfinished sequential-write blob */\n+ if (fdt_size_dt_struct(fdt) == 0)\n+ return -FDT_ERR_BADSTATE;\n+ } else {\n+ return -FDT_ERR_BADMAGIC;\n+ }\n+\n+ return 0;\n+}\n+\n+static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off)\n+{\n+ return (off >= hdrsize) && (off <= totalsize);\n+}\n+\n+static int check_block_(uint32_t hdrsize, uint32_t totalsize,\n+ uint32_t base, uint32_t size)\n+{\n+ if (!check_off_(hdrsize, totalsize, base))\n+ return 0; /* block start out of bounds */\n+ if ((base + size) < base)\n+ return 0; /* overflow */\n+ if (!check_off_(hdrsize, totalsize, base + size))\n+ return 0; /* block end out of bounds */\n+ return 1;\n+}\n+\n+size_t fdt_header_size_(uint32_t version)\n+{\n+ if (version <= 1)\n+ return FDT_V1_SIZE;\n+ else if (version <= 2)\n+ return FDT_V2_SIZE;\n+ else if (version <= 3)\n+ return FDT_V3_SIZE;\n+ else if (version <= 16)\n+ return FDT_V16_SIZE;\n+ else\n+ return FDT_V17_SIZE;\n+}\n+\n+int fdt_check_header(const void *fdt)\n+{\n+ size_t hdrsize;\n+\n+ if (fdt_magic(fdt) != FDT_MAGIC)\n+ return -FDT_ERR_BADMAGIC;\n+ hdrsize = fdt_header_size(fdt);\n+ if ((fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)\n+ || (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION))\n+ return -FDT_ERR_BADVERSION;\n+ if (fdt_version(fdt) < fdt_last_comp_version(fdt))\n+ return -FDT_ERR_BADVERSION;\n+\n+ if ((fdt_totalsize(fdt) < hdrsize)\n+ || (fdt_totalsize(fdt) > INT_MAX))\n+ return -FDT_ERR_TRUNCATED;\n+\n+ /* Bounds check memrsv block */\n+ if (!check_off_(hdrsize, fdt_totalsize(fdt), fdt_off_mem_rsvmap(fdt)))\n+ return -FDT_ERR_TRUNCATED;\n+\n+ /* Bounds check structure block */\n+ if (fdt_version(fdt) < 17) {\n+ if (!check_off_(hdrsize, fdt_totalsize(fdt),\n+ fdt_off_dt_struct(fdt)))\n+ return -FDT_ERR_TRUNCATED;\n+ } else {\n+ if (!check_block_(hdrsize, fdt_totalsize(fdt),\n+ fdt_off_dt_struct(fdt),\n+ fdt_size_dt_struct(fdt)))\n+ return -FDT_ERR_TRUNCATED;\n+ }\n+\n+ /* Bounds check strings block */\n+ if (!check_block_(hdrsize, fdt_totalsize(fdt),\n+ fdt_off_dt_strings(fdt), fdt_size_dt_strings(fdt)))\n+ return -FDT_ERR_TRUNCATED;\n+\n+ return 0;\n+}\n+\n+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)\n+{\n+ unsigned absoffset = offset + fdt_off_dt_struct(fdt);\n+\n+ if ((absoffset < offset)\n+ || ((absoffset + len) < absoffset)\n+ || (absoffset + len) > fdt_totalsize(fdt))\n+ return NULL;\n+\n+ if (fdt_version(fdt) >= 0x11)\n+ if (((offset + len) < offset)\n+ || ((offset + len) > fdt_size_dt_struct(fdt)))\n+ return NULL;\n+\n+ return fdt_offset_ptr_(fdt, offset);\n+}\n+\n+uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)\n+{\n+ const fdt32_t *tagp, *lenp;\n+ uint32_t tag;\n+ int offset = startoffset;\n+ const char *p;\n+\n+ *nextoffset = -FDT_ERR_TRUNCATED;\n+ tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);\n+ if (!tagp)\n+ return FDT_END; /* premature end */\n+ tag = fdt32_to_cpu(*tagp);\n+ offset += FDT_TAGSIZE;\n+\n+ *nextoffset = -FDT_ERR_BADSTRUCTURE;\n+ switch (tag) {\n+ case FDT_BEGIN_NODE:\n+ /* skip name */\n+ do {\n+ p = fdt_offset_ptr(fdt, offset++, 1);\n+ } while (p && (*p != '\\0'));\n+ if (!p)\n+ return FDT_END; /* premature end */\n+ break;\n+\n+ case FDT_PROP:\n+ lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));\n+ if (!lenp)\n+ return FDT_END; /* premature end */\n+ /* skip-name offset, length and value */\n+ offset += sizeof(struct fdt_property) - FDT_TAGSIZE\n+ + fdt32_to_cpu(*lenp);\n+ if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&\n+ ((offset - fdt32_to_cpu(*lenp)) % 8) != 0)\n+ offset += 4;\n+ break;\n+\n+ case FDT_END:\n+ case FDT_END_NODE:\n+ case FDT_NOP:\n+ break;\n+\n+ default:\n+ return FDT_END;\n+ }\n+\n+ if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))\n+ return FDT_END; /* premature end */\n+\n+ *nextoffset = FDT_TAGALIGN(offset);\n+ return tag;\n+}\n+\n+int fdt_check_node_offset_(const void *fdt, int offset)\n+{\n+ if ((offset < 0) || (offset % FDT_TAGSIZE)\n+ || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))\n+ return -FDT_ERR_BADOFFSET;\n+\n+ return offset;\n+}\n+\n+int fdt_check_prop_offset_(const void *fdt, int offset)\n+{\n+ if ((offset < 0) || (offset % FDT_TAGSIZE)\n+ || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))\n+ return -FDT_ERR_BADOFFSET;\n+\n+ return offset;\n+}\n+\n+int fdt_next_node(const void *fdt, int offset, int *depth)\n+{\n+ int nextoffset = 0;\n+ uint32_t tag;\n+\n+ if (offset >= 0)\n+ if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0)\n+ return nextoffset;\n+\n+ do {\n+ offset = nextoffset;\n+ tag = fdt_next_tag(fdt, offset, &nextoffset);\n+\n+ switch (tag) {\n+ case FDT_PROP:\n+ case FDT_NOP:\n+ break;\n+\n+ case FDT_BEGIN_NODE:\n+ if (depth)\n+ (*depth)++;\n+ break;\n+\n+ case FDT_END_NODE:\n+ if (depth && ((--(*depth)) < 0))\n+ return nextoffset;\n+ break;\n+\n+ case FDT_END:\n+ if ((nextoffset >= 0)\n+ || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))\n+ return -FDT_ERR_NOTFOUND;\n+ else\n+ return nextoffset;\n+ }\n+ } while (tag != FDT_BEGIN_NODE);\n+\n+ return offset;\n+}\n+\n+int fdt_first_subnode(const void *fdt, int offset)\n+{\n+ int depth = 0;\n+\n+ offset = fdt_next_node(fdt, offset, &depth);\n+ if (offset < 0 || depth != 1)\n+ return -FDT_ERR_NOTFOUND;\n+\n+ return offset;\n+}\n+\n+int fdt_next_subnode(const void *fdt, int offset)\n+{\n+ int depth = 1;\n+\n+ /*\n+ * With respect to the parent, the depth of the next subnode will be\n+ * the same as the last.\n+ */\n+ do {\n+ offset = fdt_next_node(fdt, offset, &depth);\n+ if (offset < 0 || depth < 1)\n+ return -FDT_ERR_NOTFOUND;\n+ } while (depth > 1);\n+\n+ return offset;\n+}\n+\n+const char *fdt_find_string_(const char *strtab, int tabsize, const char *s)\n+{\n+ int len = strlen(s) + 1;\n+ const char *last = strtab + tabsize - len;\n+ const char *p;\n+\n+ for (p = strtab; p <= last; p++)\n+ if (memcmp(p, s, len) == 0)\n+ return p;\n+ return NULL;\n+}\n+\n+int fdt_move(const void *fdt, void *buf, int bufsize)\n+{\n+ FDT_RO_PROBE(fdt);\n+\n+ if (fdt_totalsize(fdt) > bufsize)\n+ return -FDT_ERR_NOSPACE;\n+\n+ memmove(buf, fdt, fdt_totalsize(fdt));\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c854c90e12f5b177c4c5c180d740004f110b01d9\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c\n@@ -0,0 +1,75 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+static int fdt_cells(const void *fdt, int nodeoffset, const char *name)\n+{\n+ const fdt32_t *c;\n+ int val;\n+ int len;\n+\n+ c = fdt_getprop(fdt, nodeoffset, name, &len);\n+ if (!c)\n+ return len;\n+\n+ if (len != sizeof(*c))\n+ return -FDT_ERR_BADNCELLS;\n+\n+ val = fdt32_to_cpu(*c);\n+ if ((val <= 0) || (val > FDT_MAX_NCELLS))\n+ return -FDT_ERR_BADNCELLS;\n+\n+ return val;\n+}\n+\n+int fdt_address_cells(const void *fdt, int nodeoffset)\n+{\n+ int val;\n+\n+ val = fdt_cells(fdt, nodeoffset, \"#address-cells\");\n+ if (val == -FDT_ERR_NOTFOUND)\n+ return 2;\n+ return val;\n+}\n+\n+int fdt_size_cells(const void *fdt, int nodeoffset)\n+{\n+ int val;\n+\n+ val = fdt_cells(fdt, nodeoffset, \"#size-cells\");\n+ if (val == -FDT_ERR_NOTFOUND)\n+ return 1;\n+ return val;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8c9a9f5e57a69a7575c8f89e76ad09bb23d39831\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c\n@@ -0,0 +1,62 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+int fdt_create_empty_tree(void *buf, int bufsize)\n+{\n+ int err;\n+\n+ err = fdt_create(buf, bufsize);\n+ if (err)\n+ return err;\n+\n+ err = fdt_finish_reservemap(buf);\n+ if (err)\n+ return err;\n+\n+ err = fdt_begin_node(buf, \"\");\n+ if (err)\n+ return err;\n+\n+ err = fdt_end_node(buf);\n+ if (err)\n+ return err;\n+\n+ err = fdt_finish(buf);\n+ if (err)\n+ return err;\n+\n+ return fdt_open_into(buf, buf, bufsize);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e7d14b1e4cbb3d4dee17ce1d41ad24902b1b6d9e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c\n@@ -0,0 +1,890 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+/**\n+ * overlay_get_target_phandle - retrieves the target phandle of a fragment\n+ * @fdto: pointer to the device tree overlay blob\n+ * @fragment: node offset of the fragment in the overlay\n+ *\n+ * overlay_get_target_phandle() retrieves the target phandle of an\n+ * overlay fragment when that fragment uses a phandle (target\n+ * property) instead of a path (target-path property).\n+ *\n+ * returns:\n+ * the phandle pointed by the target property\n+ * 0, if the phandle was not found\n+ * -1, if the phandle was malformed\n+ */\n+static uint32_t overlay_get_target_phandle(const void *fdto, int fragment)\n+{\n+ const fdt32_t *val;\n+ int len;\n+\n+ val = fdt_getprop(fdto, fragment, \"target\", &len);\n+ if (!val)\n+ return 0;\n+\n+ if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1))\n+ return (uint32_t)-1;\n+\n+ return fdt32_to_cpu(*val);\n+}\n+\n+/**\n+ * overlay_get_target - retrieves the offset of a fragment's target\n+ * @fdt: Base device tree blob\n+ * @fdto: Device tree overlay blob\n+ * @fragment: node offset of the fragment in the overlay\n+ * @pathp: pointer which receives the path of the target (or NULL)\n+ *\n+ * overlay_get_target() retrieves the target offset in the base\n+ * device tree of a fragment, no matter how the actual targetting is\n+ * done (through a phandle or a path)\n+ *\n+ * returns:\n+ * the targetted node offset in the base device tree\n+ * Negative error code on error\n+ */\n+static int overlay_get_target(const void *fdt, const void *fdto,\n+ int fragment, char const **pathp)\n+{\n+ uint32_t phandle;\n+ const char *path = NULL;\n+ int path_len = 0, ret;\n+\n+ /* Try first to do a phandle based lookup */\n+ phandle = overlay_get_target_phandle(fdto, fragment);\n+ if (phandle == (uint32_t)-1)\n+ return -FDT_ERR_BADPHANDLE;\n+\n+ /* no phandle, try path */\n+ if (!phandle) {\n+ /* And then a path based lookup */\n+ path = fdt_getprop(fdto, fragment, \"target-path\", &path_len);\n+ if (path)\n+ ret = fdt_path_offset(fdt, path);\n+ else\n+ ret = path_len;\n+ } else\n+ ret = fdt_node_offset_by_phandle(fdt, phandle);\n+\n+ /*\n+ * If we haven't found either a target or a\n+ * target-path property in a node that contains a\n+ * __overlay__ subnode (we wouldn't be called\n+ * otherwise), consider it a improperly written\n+ * overlay\n+ */\n+ if (ret < 0 && path_len == -FDT_ERR_NOTFOUND)\n+ ret = -FDT_ERR_BADOVERLAY;\n+\n+ /* return on error */\n+ if (ret < 0)\n+ return ret;\n+\n+ /* return pointer to path (if available) */\n+ if (pathp)\n+ *pathp = path ? path : NULL;\n+\n+ return ret;\n+}\n+\n+/**\n+ * overlay_phandle_add_offset - Increases a phandle by an offset\n+ * @fdt: Base device tree blob\n+ * @node: Device tree overlay blob\n+ * @name: Name of the property to modify (phandle or linux,phandle)\n+ * @delta: offset to apply\n+ *\n+ * overlay_phandle_add_offset() increments a node phandle by a given\n+ * offset.\n+ *\n+ * returns:\n+ * 0 on success.\n+ * Negative error code on error\n+ */\n+static int overlay_phandle_add_offset(void *fdt, int node,\n+ const char *name, uint32_t delta)\n+{\n+ const fdt32_t *val;\n+ uint32_t adj_val;\n+ int len;\n+\n+ val = fdt_getprop(fdt, node, name, &len);\n+ if (!val)\n+ return len;\n+\n+ if (len != sizeof(*val))\n+ return -FDT_ERR_BADPHANDLE;\n+\n+ adj_val = fdt32_to_cpu(*val);\n+ if ((adj_val + delta) < adj_val)\n+ return -FDT_ERR_NOPHANDLES;\n+\n+ adj_val += delta;\n+ if (adj_val == (uint32_t)-1)\n+ return -FDT_ERR_NOPHANDLES;\n+\n+ return fdt_setprop_inplace_u32(fdt, node, name, adj_val);\n+}\n+\n+/**\n+ * overlay_adjust_node_phandles - Offsets the phandles of a node\n+ * @fdto: Device tree overlay blob\n+ * @node: Offset of the node we want to adjust\n+ * @delta: Offset to shift the phandles of\n+ *\n+ * overlay_adjust_node_phandles() adds a constant to all the phandles\n+ * of a given node. This is mainly use as part of the overlay\n+ * application process, when we want to update all the overlay\n+ * phandles to not conflict with the overlays of the base device tree.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_adjust_node_phandles(void *fdto, int node,\n+ uint32_t delta)\n+{\n+ int child;\n+ int ret;\n+\n+ ret = overlay_phandle_add_offset(fdto, node, \"phandle\", delta);\n+ if (ret && ret != -FDT_ERR_NOTFOUND)\n+ return ret;\n+\n+ ret = overlay_phandle_add_offset(fdto, node, \"linux,phandle\", delta);\n+ if (ret && ret != -FDT_ERR_NOTFOUND)\n+ return ret;\n+\n+ fdt_for_each_subnode(child, fdto, node) {\n+ ret = overlay_adjust_node_phandles(fdto, child, delta);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ return 0;\n+}\n+\n+/**\n+ * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay\n+ * @fdto: Device tree overlay blob\n+ * @delta: Offset to shift the phandles of\n+ *\n+ * overlay_adjust_local_phandles() adds a constant to all the\n+ * phandles of an overlay. This is mainly use as part of the overlay\n+ * application process, when we want to update all the overlay\n+ * phandles to not conflict with the overlays of the base device tree.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_adjust_local_phandles(void *fdto, uint32_t delta)\n+{\n+ /*\n+ * Start adjusting the phandles from the overlay root\n+ */\n+ return overlay_adjust_node_phandles(fdto, 0, delta);\n+}\n+\n+/**\n+ * overlay_update_local_node_references - Adjust the overlay references\n+ * @fdto: Device tree overlay blob\n+ * @tree_node: Node offset of the node to operate on\n+ * @fixup_node: Node offset of the matching local fixups node\n+ * @delta: Offset to shift the phandles of\n+ *\n+ * overlay_update_local_nodes_references() update the phandles\n+ * pointing to a node within the device tree overlay by adding a\n+ * constant delta.\n+ *\n+ * This is mainly used as part of a device tree application process,\n+ * where you want the device tree overlays phandles to not conflict\n+ * with the ones from the base device tree before merging them.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_update_local_node_references(void *fdto,\n+ int tree_node,\n+ int fixup_node,\n+ uint32_t delta)\n+{\n+ int fixup_prop;\n+ int fixup_child;\n+ int ret;\n+\n+ fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) {\n+ const fdt32_t *fixup_val;\n+ const char *tree_val;\n+ const char *name;\n+ int fixup_len;\n+ int tree_len;\n+ int i;\n+\n+ fixup_val = fdt_getprop_by_offset(fdto, fixup_prop,\n+ &name, &fixup_len);\n+ if (!fixup_val)\n+ return fixup_len;\n+\n+ if (fixup_len % sizeof(uint32_t))\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ tree_val = fdt_getprop(fdto, tree_node, name, &tree_len);\n+ if (!tree_val) {\n+ if (tree_len == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ return tree_len;\n+ }\n+\n+ for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {\n+ fdt32_t adj_val;\n+ uint32_t poffset;\n+\n+ poffset = fdt32_to_cpu(fixup_val[i]);\n+\n+ /*\n+ * phandles to fixup can be unaligned.\n+ *\n+ * Use a memcpy for the architectures that do\n+ * not support unaligned accesses.\n+ */\n+ memcpy(&adj_val, tree_val + poffset, sizeof(adj_val));\n+\n+ adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta);\n+\n+ ret = fdt_setprop_inplace_namelen_partial(fdto,\n+ tree_node,\n+ name,\n+ strlen(name),\n+ poffset,\n+ &adj_val,\n+ sizeof(adj_val));\n+ if (ret == -FDT_ERR_NOSPACE)\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ if (ret)\n+ return ret;\n+ }\n+ }\n+\n+ fdt_for_each_subnode(fixup_child, fdto, fixup_node) {\n+ const char *fixup_child_name = fdt_get_name(fdto, fixup_child,\n+ NULL);\n+ int tree_child;\n+\n+ tree_child = fdt_subnode_offset(fdto, tree_node,\n+ fixup_child_name);\n+ if (tree_child == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_BADOVERLAY;\n+ if (tree_child < 0)\n+ return tree_child;\n+\n+ ret = overlay_update_local_node_references(fdto,\n+ tree_child,\n+ fixup_child,\n+ delta);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ return 0;\n+}\n+\n+/**\n+ * overlay_update_local_references - Adjust the overlay references\n+ * @fdto: Device tree overlay blob\n+ * @delta: Offset to shift the phandles of\n+ *\n+ * overlay_update_local_references() update all the phandles pointing\n+ * to a node within the device tree overlay by adding a constant\n+ * delta to not conflict with the base overlay.\n+ *\n+ * This is mainly used as part of a device tree application process,\n+ * where you want the device tree overlays phandles to not conflict\n+ * with the ones from the base device tree before merging them.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_update_local_references(void *fdto, uint32_t delta)\n+{\n+ int fixups;\n+\n+ fixups = fdt_path_offset(fdto, \"/__local_fixups__\");\n+ if (fixups < 0) {\n+ /* There's no local phandles to adjust, bail out */\n+ if (fixups == -FDT_ERR_NOTFOUND)\n+ return 0;\n+\n+ return fixups;\n+ }\n+\n+ /*\n+ * Update our local references from the root of the tree\n+ */\n+ return overlay_update_local_node_references(fdto, 0, fixups,\n+ delta);\n+}\n+\n+/**\n+ * overlay_fixup_one_phandle - Set an overlay phandle to the base one\n+ * @fdt: Base Device Tree blob\n+ * @fdto: Device tree overlay blob\n+ * @symbols_off: Node offset of the symbols node in the base device tree\n+ * @path: Path to a node holding a phandle in the overlay\n+ * @path_len: number of path characters to consider\n+ * @name: Name of the property holding the phandle reference in the overlay\n+ * @name_len: number of name characters to consider\n+ * @poffset: Offset within the overlay property where the phandle is stored\n+ * @label: Label of the node referenced by the phandle\n+ *\n+ * overlay_fixup_one_phandle() resolves an overlay phandle pointing to\n+ * a node in the base device tree.\n+ *\n+ * This is part of the device tree overlay application process, when\n+ * you want all the phandles in the overlay to point to the actual\n+ * base dt nodes.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_fixup_one_phandle(void *fdt, void *fdto,\n+ int symbols_off,\n+ const char *path, uint32_t path_len,\n+ const char *name, uint32_t name_len,\n+ int poffset, const char *label)\n+{\n+ const char *symbol_path;\n+ uint32_t phandle;\n+ fdt32_t phandle_prop;\n+ int symbol_off, fixup_off;\n+ int prop_len;\n+\n+ if (symbols_off < 0)\n+ return symbols_off;\n+\n+ symbol_path = fdt_getprop(fdt, symbols_off, label,\n+ &prop_len);\n+ if (!symbol_path)\n+ return prop_len;\n+\n+ symbol_off = fdt_path_offset(fdt, symbol_path);\n+ if (symbol_off < 0)\n+ return symbol_off;\n+\n+ phandle = fdt_get_phandle(fdt, symbol_off);\n+ if (!phandle)\n+ return -FDT_ERR_NOTFOUND;\n+\n+ fixup_off = fdt_path_offset_namelen(fdto, path, path_len);\n+ if (fixup_off == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_BADOVERLAY;\n+ if (fixup_off < 0)\n+ return fixup_off;\n+\n+ phandle_prop = cpu_to_fdt32(phandle);\n+ return fdt_setprop_inplace_namelen_partial(fdto, fixup_off,\n+ name, name_len, poffset,\n+ &phandle_prop,\n+ sizeof(phandle_prop));\n+};\n+\n+/**\n+ * overlay_fixup_phandle - Set an overlay phandle to the base one\n+ * @fdt: Base Device Tree blob\n+ * @fdto: Device tree overlay blob\n+ * @symbols_off: Node offset of the symbols node in the base device tree\n+ * @property: Property offset in the overlay holding the list of fixups\n+ *\n+ * overlay_fixup_phandle() resolves all the overlay phandles pointed\n+ * to in a __fixups__ property, and updates them to match the phandles\n+ * in use in the base device tree.\n+ *\n+ * This is part of the device tree overlay application process, when\n+ * you want all the phandles in the overlay to point to the actual\n+ * base dt nodes.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off,\n+ int property)\n+{\n+ const char *value;\n+ const char *label;\n+ int len;\n+\n+ value = fdt_getprop_by_offset(fdto, property,\n+ &label, &len);\n+ if (!value) {\n+ if (len == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_INTERNAL;\n+\n+ return len;\n+ }\n+\n+ do {\n+ const char *path, *name, *fixup_end;\n+ const char *fixup_str = value;\n+ uint32_t path_len, name_len;\n+ uint32_t fixup_len;\n+ char *sep, *endptr;\n+ int poffset, ret;\n+\n+ fixup_end = memchr(value, '\\0', len);\n+ if (!fixup_end)\n+ return -FDT_ERR_BADOVERLAY;\n+ fixup_len = fixup_end - fixup_str;\n+\n+ len -= fixup_len + 1;\n+ value += fixup_len + 1;\n+\n+ path = fixup_str;\n+ sep = memchr(fixup_str, ':', fixup_len);\n+ if (!sep || *sep != ':')\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ path_len = sep - path;\n+ if (path_len == (fixup_len - 1))\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ fixup_len -= path_len + 1;\n+ name = sep + 1;\n+ sep = memchr(name, ':', fixup_len);\n+ if (!sep || *sep != ':')\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ name_len = sep - name;\n+ if (!name_len)\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ poffset = strtoul(sep + 1, &endptr, 10);\n+ if ((*endptr != '\\0') || (endptr <= (sep + 1)))\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off,\n+ path, path_len, name, name_len,\n+ poffset, label);\n+ if (ret)\n+ return ret;\n+ } while (len > 0);\n+\n+ return 0;\n+}\n+\n+/**\n+ * overlay_fixup_phandles - Resolve the overlay phandles to the base\n+ * device tree\n+ * @fdt: Base Device Tree blob\n+ * @fdto: Device tree overlay blob\n+ *\n+ * overlay_fixup_phandles() resolves all the overlay phandles pointing\n+ * to nodes in the base device tree.\n+ *\n+ * This is one of the steps of the device tree overlay application\n+ * process, when you want all the phandles in the overlay to point to\n+ * the actual base dt nodes.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_fixup_phandles(void *fdt, void *fdto)\n+{\n+ int fixups_off, symbols_off;\n+ int property;\n+\n+ /* We can have overlays without any fixups */\n+ fixups_off = fdt_path_offset(fdto, \"/__fixups__\");\n+ if (fixups_off == -FDT_ERR_NOTFOUND)\n+ return 0; /* nothing to do */\n+ if (fixups_off < 0)\n+ return fixups_off;\n+\n+ /* And base DTs without symbols */\n+ symbols_off = fdt_path_offset(fdt, \"/__symbols__\");\n+ if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND)))\n+ return symbols_off;\n+\n+ fdt_for_each_property_offset(property, fdto, fixups_off) {\n+ int ret;\n+\n+ ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ return 0;\n+}\n+\n+/**\n+ * overlay_apply_node - Merges a node into the base device tree\n+ * @fdt: Base Device Tree blob\n+ * @target: Node offset in the base device tree to apply the fragment to\n+ * @fdto: Device tree overlay blob\n+ * @node: Node offset in the overlay holding the changes to merge\n+ *\n+ * overlay_apply_node() merges a node into a target base device tree\n+ * node pointed.\n+ *\n+ * This is part of the final step in the device tree overlay\n+ * application process, when all the phandles have been adjusted and\n+ * resolved and you just have to merge overlay into the base device\n+ * tree.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_apply_node(void *fdt, int target,\n+ void *fdto, int node)\n+{\n+ int property;\n+ int subnode;\n+\n+ fdt_for_each_property_offset(property, fdto, node) {\n+ const char *name;\n+ const void *prop;\n+ int prop_len;\n+ int ret;\n+\n+ prop = fdt_getprop_by_offset(fdto, property, &name,\n+ &prop_len);\n+ if (prop_len == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_INTERNAL;\n+ if (prop_len < 0)\n+ return prop_len;\n+\n+ ret = fdt_setprop(fdt, target, name, prop, prop_len);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ fdt_for_each_subnode(subnode, fdto, node) {\n+ const char *name = fdt_get_name(fdto, subnode, NULL);\n+ int nnode;\n+ int ret;\n+\n+ nnode = fdt_add_subnode(fdt, target, name);\n+ if (nnode == -FDT_ERR_EXISTS) {\n+ nnode = fdt_subnode_offset(fdt, target, name);\n+ if (nnode == -FDT_ERR_NOTFOUND)\n+ return -FDT_ERR_INTERNAL;\n+ }\n+\n+ if (nnode < 0)\n+ return nnode;\n+\n+ ret = overlay_apply_node(fdt, nnode, fdto, subnode);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ return 0;\n+}\n+\n+/**\n+ * overlay_merge - Merge an overlay into its base device tree\n+ * @fdt: Base Device Tree blob\n+ * @fdto: Device tree overlay blob\n+ *\n+ * overlay_merge() merges an overlay into its base device tree.\n+ *\n+ * This is the next to last step in the device tree overlay application\n+ * process, when all the phandles have been adjusted and resolved and\n+ * you just have to merge overlay into the base device tree.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_merge(void *fdt, void *fdto)\n+{\n+ int fragment;\n+\n+ fdt_for_each_subnode(fragment, fdto, 0) {\n+ int overlay;\n+ int target;\n+ int ret;\n+\n+ /*\n+ * Each fragments will have an __overlay__ node. If\n+ * they don't, it's not supposed to be merged\n+ */\n+ overlay = fdt_subnode_offset(fdto, fragment, \"__overlay__\");\n+ if (overlay == -FDT_ERR_NOTFOUND)\n+ continue;\n+\n+ if (overlay < 0)\n+ return overlay;\n+\n+ target = overlay_get_target(fdt, fdto, fragment, NULL);\n+ if (target < 0)\n+ return target;\n+\n+ ret = overlay_apply_node(fdt, target, fdto, overlay);\n+ if (ret)\n+ return ret;\n+ }\n+\n+ return 0;\n+}\n+\n+static int get_path_len(const void *fdt, int nodeoffset)\n+{\n+ int len = 0, namelen;\n+ const char *name;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ for (;;) {\n+ name = fdt_get_name(fdt, nodeoffset, &namelen);\n+ if (!name)\n+ return namelen;\n+\n+ /* root? we're done */\n+ if (namelen == 0)\n+ break;\n+\n+ nodeoffset = fdt_parent_offset(fdt, nodeoffset);\n+ if (nodeoffset < 0)\n+ return nodeoffset;\n+ len += namelen + 1;\n+ }\n+\n+ /* in case of root pretend it's \"/\" */\n+ if (len == 0)\n+ len++;\n+ return len;\n+}\n+\n+/**\n+ * overlay_symbol_update - Update the symbols of base tree after a merge\n+ * @fdt: Base Device Tree blob\n+ * @fdto: Device tree overlay blob\n+ *\n+ * overlay_symbol_update() updates the symbols of the base tree with the\n+ * symbols of the applied overlay\n+ *\n+ * This is the last step in the device tree overlay application\n+ * process, allowing the reference of overlay symbols by subsequent\n+ * overlay operations.\n+ *\n+ * returns:\n+ * 0 on success\n+ * Negative error code on failure\n+ */\n+static int overlay_symbol_update(void *fdt, void *fdto)\n+{\n+ int root_sym, ov_sym, prop, path_len, fragment, target;\n+ int len, frag_name_len, ret, rel_path_len;\n+ const char *s, *e;\n+ const char *path;\n+ const char *name;\n+ const char *frag_name;\n+ const char *rel_path;\n+ const char *target_path;\n+ char *buf;\n+ void *p;\n+\n+ ov_sym = fdt_subnode_offset(fdto, 0, \"__symbols__\");\n+\n+ /* if no overlay symbols exist no problem */\n+ if (ov_sym < 0)\n+ return 0;\n+\n+ root_sym = fdt_subnode_offset(fdt, 0, \"__symbols__\");\n+\n+ /* it no root symbols exist we should create them */\n+ if (root_sym == -FDT_ERR_NOTFOUND)\n+ root_sym = fdt_add_subnode(fdt, 0, \"__symbols__\");\n+\n+ /* any error is fatal now */\n+ if (root_sym < 0)\n+ return root_sym;\n+\n+ /* iterate over each overlay symbol */\n+ fdt_for_each_property_offset(prop, fdto, ov_sym) {\n+ path = fdt_getprop_by_offset(fdto, prop, &name, &path_len);\n+ if (!path)\n+ return path_len;\n+\n+ /* verify it's a string property (terminated by a single \\0) */\n+ if (path_len < 1 || memchr(path, '\\0', path_len) != &path[path_len - 1])\n+ return -FDT_ERR_BADVALUE;\n+\n+ /* keep end marker to avoid strlen() */\n+ e = path + path_len;\n+\n+ /* format: /<fragment-name>/__overlay__/<relative-subnode-path> */\n+\n+ if (*path != '/')\n+ return -FDT_ERR_BADVALUE;\n+\n+ /* get fragment name first */\n+ s = strchr(path + 1, '/');\n+ if (!s)\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ frag_name = path + 1;\n+ frag_name_len = s - path - 1;\n+\n+ /* verify format; safe since \"s\" lies in \\0 terminated prop */\n+ len = sizeof(\"/__overlay__/\") - 1;\n+ if ((e - s) < len || memcmp(s, \"/__overlay__/\", len))\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ rel_path = s + len;\n+ rel_path_len = e - rel_path;\n+\n+ /* find the fragment index in which the symbol lies */\n+ ret = fdt_subnode_offset_namelen(fdto, 0, frag_name,\n+ frag_name_len);\n+ /* not found? */\n+ if (ret < 0)\n+ return -FDT_ERR_BADOVERLAY;\n+ fragment = ret;\n+\n+ /* an __overlay__ subnode must exist */\n+ ret = fdt_subnode_offset(fdto, fragment, \"__overlay__\");\n+ if (ret < 0)\n+ return -FDT_ERR_BADOVERLAY;\n+\n+ /* get the target of the fragment */\n+ ret = overlay_get_target(fdt, fdto, fragment, &target_path);\n+ if (ret < 0)\n+ return ret;\n+ target = ret;\n+\n+ /* if we have a target path use */\n+ if (!target_path) {\n+ ret = get_path_len(fdt, target);\n+ if (ret < 0)\n+ return ret;\n+ len = ret;\n+ } else {\n+ len = strlen(target_path);\n+ }\n+\n+ ret = fdt_setprop_placeholder(fdt, root_sym, name,\n+ len + (len > 1) + rel_path_len + 1, &p);\n+ if (ret < 0)\n+ return ret;\n+\n+ if (!target_path) {\n+ /* again in case setprop_placeholder changed it */\n+ ret = overlay_get_target(fdt, fdto, fragment, &target_path);\n+ if (ret < 0)\n+ return ret;\n+ target = ret;\n+ }\n+\n+ buf = p;\n+ if (len > 1) { /* target is not root */\n+ if (!target_path) {\n+ ret = fdt_get_path(fdt, target, buf, len + 1);\n+ if (ret < 0)\n+ return ret;\n+ } else\n+ memcpy(buf, target_path, len + 1);\n+\n+ } else\n+ len--;\n+\n+ buf[len] = '/';\n+ memcpy(buf + len + 1, rel_path, rel_path_len);\n+ buf[len + 1 + rel_path_len] = '\\0';\n+ }\n+\n+ return 0;\n+}\n+\n+int fdt_overlay_apply(void *fdt, void *fdto)\n+{\n+ uint32_t delta = fdt_get_max_phandle(fdt);\n+ int ret;\n+\n+ FDT_RO_PROBE(fdt);\n+ FDT_RO_PROBE(fdto);\n+\n+ ret = overlay_adjust_local_phandles(fdto, delta);\n+ if (ret)\n+ goto err;\n+\n+ ret = overlay_update_local_references(fdto, delta);\n+ if (ret)\n+ goto err;\n+\n+ ret = overlay_fixup_phandles(fdt, fdto);\n+ if (ret)\n+ goto err;\n+\n+ ret = overlay_merge(fdt, fdto);\n+ if (ret)\n+ goto err;\n+\n+ ret = overlay_symbol_update(fdt, fdto);\n+ if (ret)\n+ goto err;\n+\n+ /*\n+ * The overlay has been damaged, erase its magic.\n+ */\n+ fdt_set_magic(fdto, ~0);\n+\n+ return 0;\n+\n+err:\n+ /*\n+ * The overlay might have been damaged, erase its magic.\n+ */\n+ fdt_set_magic(fdto, ~0);\n+\n+ /*\n+ * The base device tree might have been damaged, erase its\n+ * magic.\n+ */\n+ fdt_set_magic(fdt, ~0);\n+\n+ return ret;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..64aff00b799a1a5e412210ffce97c69a05f0fabe\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c\n@@ -0,0 +1,901 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+static int fdt_nodename_eq_(const void *fdt, int offset,\n+ const char *s, int len)\n+{\n+ int olen;\n+ const char *p = fdt_get_name(fdt, offset, &olen);\n+\n+ if (!p || olen < len)\n+ /* short match */\n+ return 0;\n+\n+ if (memcmp(p, s, len) != 0)\n+ return 0;\n+\n+ if (p[len] == '\\0')\n+ return 1;\n+ else if (!memchr(s, '@', len) && (p[len] == '@'))\n+ return 1;\n+ else\n+ return 0;\n+}\n+\n+const char *fdt_get_string(const void *fdt, int stroffset, int *lenp)\n+{\n+ uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt);\n+ size_t len;\n+ int err;\n+ const char *s, *n;\n+\n+ err = fdt_ro_probe_(fdt);\n+ if (err != 0)\n+ goto fail;\n+\n+ err = -FDT_ERR_BADOFFSET;\n+ if (absoffset >= fdt_totalsize(fdt))\n+ goto fail;\n+ len = fdt_totalsize(fdt) - absoffset;\n+\n+ if (fdt_magic(fdt) == FDT_MAGIC) {\n+ if (stroffset < 0)\n+ goto fail;\n+ if (fdt_version(fdt) >= 17) {\n+ if (stroffset >= fdt_size_dt_strings(fdt))\n+ goto fail;\n+ if ((fdt_size_dt_strings(fdt) - stroffset) < len)\n+ len = fdt_size_dt_strings(fdt) - stroffset;\n+ }\n+ } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {\n+ if ((stroffset >= 0)\n+ || (stroffset < -fdt_size_dt_strings(fdt)))\n+ goto fail;\n+ if ((-stroffset) < len)\n+ len = -stroffset;\n+ } else {\n+ err = -FDT_ERR_INTERNAL;\n+ goto fail;\n+ }\n+\n+ s = (const char *)fdt + absoffset;\n+ n = memchr(s, '\\0', len);\n+ if (!n) {\n+ /* missing terminating NULL */\n+ err = -FDT_ERR_TRUNCATED;\n+ goto fail;\n+ }\n+\n+ if (lenp)\n+ *lenp = n - s;\n+ return s;\n+\n+fail:\n+ if (lenp)\n+ *lenp = err;\n+ return NULL;\n+}\n+\n+const char *fdt_string(const void *fdt, int stroffset)\n+{\n+ return fdt_get_string(fdt, stroffset, NULL);\n+}\n+\n+static int fdt_string_eq_(const void *fdt, int stroffset,\n+ const char *s, int len)\n+{\n+ int slen;\n+ const char *p = fdt_get_string(fdt, stroffset, &slen);\n+\n+ return p && (slen == len) && (memcmp(p, s, len) == 0);\n+}\n+\n+uint32_t fdt_get_max_phandle(const void *fdt)\n+{\n+ uint32_t max_phandle = 0;\n+ int offset;\n+\n+ for (offset = fdt_next_node(fdt, -1, NULL);;\n+ offset = fdt_next_node(fdt, offset, NULL)) {\n+ uint32_t phandle;\n+\n+ if (offset == -FDT_ERR_NOTFOUND)\n+ return max_phandle;\n+\n+ if (offset < 0)\n+ return (uint32_t)-1;\n+\n+ phandle = fdt_get_phandle(fdt, offset);\n+ if (phandle == (uint32_t)-1)\n+ continue;\n+\n+ if (phandle > max_phandle)\n+ max_phandle = phandle;\n+ }\n+\n+ return 0;\n+}\n+\n+static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n)\n+{\n+ int offset = n * sizeof(struct fdt_reserve_entry);\n+ int absoffset = fdt_off_mem_rsvmap(fdt) + offset;\n+\n+ if (absoffset < fdt_off_mem_rsvmap(fdt))\n+ return NULL;\n+ if (absoffset > fdt_totalsize(fdt) - sizeof(struct fdt_reserve_entry))\n+ return NULL;\n+ return fdt_mem_rsv_(fdt, n);\n+}\n+\n+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)\n+{\n+ const struct fdt_reserve_entry *re;\n+\n+ FDT_RO_PROBE(fdt);\n+ re = fdt_mem_rsv(fdt, n);\n+ if (!re)\n+ return -FDT_ERR_BADOFFSET;\n+\n+ *address = fdt64_ld(&re->address);\n+ *size = fdt64_ld(&re->size);\n+ return 0;\n+}\n+\n+int fdt_num_mem_rsv(const void *fdt)\n+{\n+ int i;\n+ const struct fdt_reserve_entry *re;\n+\n+ for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) {\n+ if (fdt64_ld(&re->size) == 0)\n+ return i;\n+ }\n+ return -FDT_ERR_TRUNCATED;\n+}\n+\n+static int nextprop_(const void *fdt, int offset)\n+{\n+ uint32_t tag;\n+ int nextoffset;\n+\n+ do {\n+ tag = fdt_next_tag(fdt, offset, &nextoffset);\n+\n+ switch (tag) {\n+ case FDT_END:\n+ if (nextoffset >= 0)\n+ return -FDT_ERR_BADSTRUCTURE;\n+ else\n+ return nextoffset;\n+\n+ case FDT_PROP:\n+ return offset;\n+ }\n+ offset = nextoffset;\n+ } while (tag == FDT_NOP);\n+\n+ return -FDT_ERR_NOTFOUND;\n+}\n+\n+int fdt_subnode_offset_namelen(const void *fdt, int offset,\n+ const char *name, int namelen)\n+{\n+ int depth;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ for (depth = 0;\n+ (offset >= 0) && (depth >= 0);\n+ offset = fdt_next_node(fdt, offset, &depth))\n+ if ((depth == 1)\n+ && fdt_nodename_eq_(fdt, offset, name, namelen))\n+ return offset;\n+\n+ if (depth < 0)\n+ return -FDT_ERR_NOTFOUND;\n+ return offset; /* error */\n+}\n+\n+int fdt_subnode_offset(const void *fdt, int parentoffset,\n+ const char *name)\n+{\n+ return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));\n+}\n+\n+int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen)\n+{\n+ const char *end = path + namelen;\n+ const char *p = path;\n+ int offset = 0;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ /* see if we have an alias */\n+ if (*path != '/') {\n+ const char *q = memchr(path, '/', end - p);\n+\n+ if (!q)\n+ q = end;\n+\n+ p = fdt_get_alias_namelen(fdt, p, q - p);\n+ if (!p)\n+ return -FDT_ERR_BADPATH;\n+ offset = fdt_path_offset(fdt, p);\n+\n+ p = q;\n+ }\n+\n+ while (p < end) {\n+ const char *q;\n+\n+ while (*p == '/') {\n+ p++;\n+ if (p == end)\n+ return offset;\n+ }\n+ q = memchr(p, '/', end - p);\n+ if (! q)\n+ q = end;\n+\n+ offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);\n+ if (offset < 0)\n+ return offset;\n+\n+ p = q;\n+ }\n+\n+ return offset;\n+}\n+\n+int fdt_path_offset(const void *fdt, const char *path)\n+{\n+ return fdt_path_offset_namelen(fdt, path, strlen(path));\n+}\n+\n+const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)\n+{\n+ const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset);\n+ const char *nameptr;\n+ int err;\n+\n+ if (((err = fdt_ro_probe_(fdt)) != 0)\n+ || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0))\n+ goto fail;\n+\n+ nameptr = nh->name;\n+\n+ if (fdt_version(fdt) < 0x10) {\n+ /*\n+ * For old FDT versions, match the naming conventions of V16:\n+ * give only the leaf name (after all /). The actual tree\n+ * contents are loosely checked.\n+ */\n+ const char *leaf;\n+ leaf = strrchr(nameptr, '/');\n+ if (leaf == NULL) {\n+ err = -FDT_ERR_BADSTRUCTURE;\n+ goto fail;\n+ }\n+ nameptr = leaf+1;\n+ }\n+\n+ if (len)\n+ *len = strlen(nameptr);\n+\n+ return nameptr;\n+\n+ fail:\n+ if (len)\n+ *len = err;\n+ return NULL;\n+}\n+\n+int fdt_first_property_offset(const void *fdt, int nodeoffset)\n+{\n+ int offset;\n+\n+ if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)\n+ return offset;\n+\n+ return nextprop_(fdt, offset);\n+}\n+\n+int fdt_next_property_offset(const void *fdt, int offset)\n+{\n+ if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0)\n+ return offset;\n+\n+ return nextprop_(fdt, offset);\n+}\n+\n+static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt,\n+ int offset,\n+ int *lenp)\n+{\n+ int err;\n+ const struct fdt_property *prop;\n+\n+ if ((err = fdt_check_prop_offset_(fdt, offset)) < 0) {\n+ if (lenp)\n+ *lenp = err;\n+ return NULL;\n+ }\n+\n+ prop = fdt_offset_ptr_(fdt, offset);\n+\n+ if (lenp)\n+ *lenp = fdt32_ld(&prop->len);\n+\n+ return prop;\n+}\n+\n+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,\n+ int offset,\n+ int *lenp)\n+{\n+ /* Prior to version 16, properties may need realignment\n+ * and this API does not work. fdt_getprop_*() will, however. */\n+\n+ if (fdt_version(fdt) < 0x10) {\n+ if (lenp)\n+ *lenp = -FDT_ERR_BADVERSION;\n+ return NULL;\n+ }\n+\n+ return fdt_get_property_by_offset_(fdt, offset, lenp);\n+}\n+\n+static const struct fdt_property *fdt_get_property_namelen_(const void *fdt,\n+ int offset,\n+ const char *name,\n+ int namelen,\n+ int *lenp,\n+ int *poffset)\n+{\n+ for (offset = fdt_first_property_offset(fdt, offset);\n+ (offset >= 0);\n+ (offset = fdt_next_property_offset(fdt, offset))) {\n+ const struct fdt_property *prop;\n+\n+ if (!(prop = fdt_get_property_by_offset_(fdt, offset, lenp))) {\n+ offset = -FDT_ERR_INTERNAL;\n+ break;\n+ }\n+ if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff),\n+ name, namelen)) {\n+ if (poffset)\n+ *poffset = offset;\n+ return prop;\n+ }\n+ }\n+\n+ if (lenp)\n+ *lenp = offset;\n+ return NULL;\n+}\n+\n+\n+const struct fdt_property *fdt_get_property_namelen(const void *fdt,\n+ int offset,\n+ const char *name,\n+ int namelen, int *lenp)\n+{\n+ /* Prior to version 16, properties may need realignment\n+ * and this API does not work. fdt_getprop_*() will, however. */\n+ if (fdt_version(fdt) < 0x10) {\n+ if (lenp)\n+ *lenp = -FDT_ERR_BADVERSION;\n+ return NULL;\n+ }\n+\n+ return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp,\n+ NULL);\n+}\n+\n+\n+const struct fdt_property *fdt_get_property(const void *fdt,\n+ int nodeoffset,\n+ const char *name, int *lenp)\n+{\n+ return fdt_get_property_namelen(fdt, nodeoffset, name,\n+ strlen(name), lenp);\n+}\n+\n+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,\n+ const char *name, int namelen, int *lenp)\n+{\n+ int poffset;\n+ const struct fdt_property *prop;\n+\n+ prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp,\n+ &poffset);\n+ if (!prop)\n+ return NULL;\n+\n+ /* Handle realignment */\n+ if (fdt_version(fdt) < 0x10 && (poffset + sizeof(*prop)) % 8 &&\n+ fdt32_ld(&prop->len) >= 8)\n+ return prop->data + 4;\n+ return prop->data;\n+}\n+\n+const void *fdt_getprop_by_offset(const void *fdt, int offset,\n+ const char **namep, int *lenp)\n+{\n+ const struct fdt_property *prop;\n+\n+ prop = fdt_get_property_by_offset_(fdt, offset, lenp);\n+ if (!prop)\n+ return NULL;\n+ if (namep) {\n+ const char *name;\n+ int namelen;\n+ name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff),\n+ &namelen);\n+ if (!name) {\n+ if (lenp)\n+ *lenp = namelen;\n+ return NULL;\n+ }\n+ *namep = name;\n+ }\n+\n+ /* Handle realignment */\n+ if (fdt_version(fdt) < 0x10 && (offset + sizeof(*prop)) % 8 &&\n+ fdt32_ld(&prop->len) >= 8)\n+ return prop->data + 4;\n+ return prop->data;\n+}\n+\n+const void *fdt_getprop(const void *fdt, int nodeoffset,\n+ const char *name, int *lenp)\n+{\n+ return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);\n+}\n+\n+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)\n+{\n+ const fdt32_t *php;\n+ int len;\n+\n+ /* FIXME: This is a bit sub-optimal, since we potentially scan\n+ * over all the properties twice. */\n+ php = fdt_getprop(fdt, nodeoffset, \"phandle\", &len);\n+ if (!php || (len != sizeof(*php))) {\n+ php = fdt_getprop(fdt, nodeoffset, \"linux,phandle\", &len);\n+ if (!php || (len != sizeof(*php)))\n+ return 0;\n+ }\n+\n+ return fdt32_ld(php);\n+}\n+\n+const char *fdt_get_alias_namelen(const void *fdt,\n+ const char *name, int namelen)\n+{\n+ int aliasoffset;\n+\n+ aliasoffset = fdt_path_offset(fdt, \"/aliases\");\n+ if (aliasoffset < 0)\n+ return NULL;\n+\n+ return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);\n+}\n+\n+const char *fdt_get_alias(const void *fdt, const char *name)\n+{\n+ return fdt_get_alias_namelen(fdt, name, strlen(name));\n+}\n+\n+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)\n+{\n+ int pdepth = 0, p = 0;\n+ int offset, depth, namelen;\n+ const char *name;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ if (buflen < 2)\n+ return -FDT_ERR_NOSPACE;\n+\n+ for (offset = 0, depth = 0;\n+ (offset >= 0) && (offset <= nodeoffset);\n+ offset = fdt_next_node(fdt, offset, &depth)) {\n+ while (pdepth > depth) {\n+ do {\n+ p--;\n+ } while (buf[p-1] != '/');\n+ pdepth--;\n+ }\n+\n+ if (pdepth >= depth) {\n+ name = fdt_get_name(fdt, offset, &namelen);\n+ if (!name)\n+ return namelen;\n+ if ((p + namelen + 1) <= buflen) {\n+ memcpy(buf + p, name, namelen);\n+ p += namelen;\n+ buf[p++] = '/';\n+ pdepth++;\n+ }\n+ }\n+\n+ if (offset == nodeoffset) {\n+ if (pdepth < (depth + 1))\n+ return -FDT_ERR_NOSPACE;\n+\n+ if (p > 1) /* special case so that root path is \"/\", not \"\" */\n+ p--;\n+ buf[p] = '\\0';\n+ return 0;\n+ }\n+ }\n+\n+ if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))\n+ return -FDT_ERR_BADOFFSET;\n+ else if (offset == -FDT_ERR_BADOFFSET)\n+ return -FDT_ERR_BADSTRUCTURE;\n+\n+ return offset; /* error from fdt_next_node() */\n+}\n+\n+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,\n+ int supernodedepth, int *nodedepth)\n+{\n+ int offset, depth;\n+ int supernodeoffset = -FDT_ERR_INTERNAL;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ if (supernodedepth < 0)\n+ return -FDT_ERR_NOTFOUND;\n+\n+ for (offset = 0, depth = 0;\n+ (offset >= 0) && (offset <= nodeoffset);\n+ offset = fdt_next_node(fdt, offset, &depth)) {\n+ if (depth == supernodedepth)\n+ supernodeoffset = offset;\n+\n+ if (offset == nodeoffset) {\n+ if (nodedepth)\n+ *nodedepth = depth;\n+\n+ if (supernodedepth > depth)\n+ return -FDT_ERR_NOTFOUND;\n+ else\n+ return supernodeoffset;\n+ }\n+ }\n+\n+ if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))\n+ return -FDT_ERR_BADOFFSET;\n+ else if (offset == -FDT_ERR_BADOFFSET)\n+ return -FDT_ERR_BADSTRUCTURE;\n+\n+ return offset; /* error from fdt_next_node() */\n+}\n+\n+int fdt_node_depth(const void *fdt, int nodeoffset)\n+{\n+ int nodedepth;\n+ int err;\n+\n+ err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);\n+ if (err)\n+ return (err < 0) ? err : -FDT_ERR_INTERNAL;\n+ return nodedepth;\n+}\n+\n+int fdt_parent_offset(const void *fdt, int nodeoffset)\n+{\n+ int nodedepth = fdt_node_depth(fdt, nodeoffset);\n+\n+ if (nodedepth < 0)\n+ return nodedepth;\n+ return fdt_supernode_atdepth_offset(fdt, nodeoffset,\n+ nodedepth - 1, NULL);\n+}\n+\n+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,\n+ const char *propname,\n+ const void *propval, int proplen)\n+{\n+ int offset;\n+ const void *val;\n+ int len;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ /* FIXME: The algorithm here is pretty horrible: we scan each\n+ * property of a node in fdt_getprop(), then if that didn't\n+ * find what we want, we scan over them again making our way\n+ * to the next node. Still it's the easiest to implement\n+ * approach; performance can come later. */\n+ for (offset = fdt_next_node(fdt, startoffset, NULL);\n+ offset >= 0;\n+ offset = fdt_next_node(fdt, offset, NULL)) {\n+ val = fdt_getprop(fdt, offset, propname, &len);\n+ if (val && (len == proplen)\n+ && (memcmp(val, propval, len) == 0))\n+ return offset;\n+ }\n+\n+ return offset; /* error from fdt_next_node() */\n+}\n+\n+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)\n+{\n+ int offset;\n+\n+ if ((phandle == 0) || (phandle == -1))\n+ return -FDT_ERR_BADPHANDLE;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ /* FIXME: The algorithm here is pretty horrible: we\n+ * potentially scan each property of a node in\n+ * fdt_get_phandle(), then if that didn't find what\n+ * we want, we scan over them again making our way to the next\n+ * node. Still it's the easiest to implement approach;\n+ * performance can come later. */\n+ for (offset = fdt_next_node(fdt, -1, NULL);\n+ offset >= 0;\n+ offset = fdt_next_node(fdt, offset, NULL)) {\n+ if (fdt_get_phandle(fdt, offset) == phandle)\n+ return offset;\n+ }\n+\n+ return offset; /* error from fdt_next_node() */\n+}\n+\n+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)\n+{\n+ int len = strlen(str);\n+ const char *p;\n+\n+ while (listlen >= len) {\n+ if (memcmp(str, strlist, len+1) == 0)\n+ return 1;\n+ p = memchr(strlist, '\\0', listlen);\n+ if (!p)\n+ return 0; /* malformed strlist.. */\n+ listlen -= (p-strlist) + 1;\n+ strlist = p + 1;\n+ }\n+ return 0;\n+}\n+\n+int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property)\n+{\n+ const char *list, *end;\n+ int length, count = 0;\n+\n+ list = fdt_getprop(fdt, nodeoffset, property, &length);\n+ if (!list)\n+ return length;\n+\n+ end = list + length;\n+\n+ while (list < end) {\n+ length = strnlen(list, end - list) + 1;\n+\n+ /* Abort if the last string isn't properly NUL-terminated. */\n+ if (list + length > end)\n+ return -FDT_ERR_BADVALUE;\n+\n+ list += length;\n+ count++;\n+ }\n+\n+ return count;\n+}\n+\n+int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,\n+ const char *string)\n+{\n+ int length, len, idx = 0;\n+ const char *list, *end;\n+\n+ list = fdt_getprop(fdt, nodeoffset, property, &length);\n+ if (!list)\n+ return length;\n+\n+ len = strlen(string) + 1;\n+ end = list + length;\n+\n+ while (list < end) {\n+ length = strnlen(list, end - list) + 1;\n+\n+ /* Abort if the last string isn't properly NUL-terminated. */\n+ if (list + length > end)\n+ return -FDT_ERR_BADVALUE;\n+\n+ if (length == len && memcmp(list, string, length) == 0)\n+ return idx;\n+\n+ list += length;\n+ idx++;\n+ }\n+\n+ return -FDT_ERR_NOTFOUND;\n+}\n+\n+const char *fdt_stringlist_get(const void *fdt, int nodeoffset,\n+ const char *property, int idx,\n+ int *lenp)\n+{\n+ const char *list, *end;\n+ int length;\n+\n+ list = fdt_getprop(fdt, nodeoffset, property, &length);\n+ if (!list) {\n+ if (lenp)\n+ *lenp = length;\n+\n+ return NULL;\n+ }\n+\n+ end = list + length;\n+\n+ while (list < end) {\n+ length = strnlen(list, end - list) + 1;\n+\n+ /* Abort if the last string isn't properly NUL-terminated. */\n+ if (list + length > end) {\n+ if (lenp)\n+ *lenp = -FDT_ERR_BADVALUE;\n+\n+ return NULL;\n+ }\n+\n+ if (idx == 0) {\n+ if (lenp)\n+ *lenp = length - 1;\n+\n+ return list;\n+ }\n+\n+ list += length;\n+ idx--;\n+ }\n+\n+ if (lenp)\n+ *lenp = -FDT_ERR_NOTFOUND;\n+\n+ return NULL;\n+}\n+\n+int fdt_node_check_compatible(const void *fdt, int nodeoffset,\n+ const char *compatible)\n+{\n+ const void *prop;\n+ int len;\n+\n+ prop = fdt_getprop(fdt, nodeoffset, \"compatible\", &len);\n+ if (!prop)\n+ return len;\n+\n+ return !fdt_stringlist_contains(prop, len, compatible);\n+}\n+\n+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,\n+ const char *compatible)\n+{\n+ int offset, err;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ /* FIXME: The algorithm here is pretty horrible: we scan each\n+ * property of a node in fdt_node_check_compatible(), then if\n+ * that didn't find what we want, we scan over them again\n+ * making our way to the next node. Still it's the easiest to\n+ * implement approach; performance can come later. */\n+ for (offset = fdt_next_node(fdt, startoffset, NULL);\n+ offset >= 0;\n+ offset = fdt_next_node(fdt, offset, NULL)) {\n+ err = fdt_node_check_compatible(fdt, offset, compatible);\n+ if ((err < 0) && (err != -FDT_ERR_NOTFOUND))\n+ return err;\n+ else if (err == 0)\n+ return offset;\n+ }\n+\n+ return offset; /* error from fdt_next_node() */\n+}\n+\n+int fdt_check_full(const void *fdt, size_t bufsize)\n+{\n+ int err;\n+ int num_memrsv;\n+ int offset, nextoffset = 0;\n+ uint32_t tag;\n+ unsigned depth = 0;\n+ const void *prop;\n+ const char *propname;\n+\n+ if (bufsize < FDT_V1_SIZE)\n+ return -FDT_ERR_TRUNCATED;\n+ err = fdt_check_header(fdt);\n+ if (err != 0)\n+ return err;\n+ if (bufsize < fdt_totalsize(fdt))\n+ return -FDT_ERR_TRUNCATED;\n+\n+ num_memrsv = fdt_num_mem_rsv(fdt);\n+ if (num_memrsv < 0)\n+ return num_memrsv;\n+\n+ while (1) {\n+ offset = nextoffset;\n+ tag = fdt_next_tag(fdt, offset, &nextoffset);\n+\n+ if (nextoffset < 0)\n+ return nextoffset;\n+\n+ switch (tag) {\n+ case FDT_NOP:\n+ break;\n+\n+ case FDT_END:\n+ if (depth != 0)\n+ return -FDT_ERR_BADSTRUCTURE;\n+ return 0;\n+\n+ case FDT_BEGIN_NODE:\n+ depth++;\n+ if (depth > INT_MAX)\n+ return -FDT_ERR_BADSTRUCTURE;\n+ break;\n+\n+ case FDT_END_NODE:\n+ if (depth == 0)\n+ return -FDT_ERR_BADSTRUCTURE;\n+ depth--;\n+ break;\n+\n+ case FDT_PROP:\n+ prop = fdt_getprop_by_offset(fdt, offset, &propname,\n+ &err);\n+ if (!prop)\n+ return err;\n+ break;\n+\n+ default:\n+ return -FDT_ERR_INTERNAL;\n+ }\n+ }\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e9b446b99f6243cada532b8aa51a59867934efda\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c\n@@ -0,0 +1,484 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+static int fdt_blocks_misordered_(const void *fdt,\n+ int mem_rsv_size, int struct_size)\n+{\n+ return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))\n+ || (fdt_off_dt_struct(fdt) <\n+ (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))\n+ || (fdt_off_dt_strings(fdt) <\n+ (fdt_off_dt_struct(fdt) + struct_size))\n+ || (fdt_totalsize(fdt) <\n+ (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));\n+}\n+\n+static int fdt_rw_probe_(void *fdt)\n+{\n+ FDT_RO_PROBE(fdt);\n+\n+ if (fdt_version(fdt) < 17)\n+ return -FDT_ERR_BADVERSION;\n+ if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry),\n+ fdt_size_dt_struct(fdt)))\n+ return -FDT_ERR_BADLAYOUT;\n+ if (fdt_version(fdt) > 17)\n+ fdt_set_version(fdt, 17);\n+\n+ return 0;\n+}\n+\n+#define FDT_RW_PROBE(fdt) \\\n+ { \\\n+ int err_; \\\n+ if ((err_ = fdt_rw_probe_(fdt)) != 0) \\\n+ return err_; \\\n+ }\n+\n+static inline int fdt_data_size_(void *fdt)\n+{\n+ return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);\n+}\n+\n+static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen)\n+{\n+ char *p = splicepoint;\n+ char *end = (char *)fdt + fdt_data_size_(fdt);\n+\n+ if (((p + oldlen) < p) || ((p + oldlen) > end))\n+ return -FDT_ERR_BADOFFSET;\n+ if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt))\n+ return -FDT_ERR_BADOFFSET;\n+ if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))\n+ return -FDT_ERR_NOSPACE;\n+ memmove(p + newlen, p + oldlen, end - p - oldlen);\n+ return 0;\n+}\n+\n+static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p,\n+ int oldn, int newn)\n+{\n+ int delta = (newn - oldn) * sizeof(*p);\n+ int err;\n+ err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));\n+ if (err)\n+ return err;\n+ fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);\n+ fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);\n+ return 0;\n+}\n+\n+static int fdt_splice_struct_(void *fdt, void *p,\n+ int oldlen, int newlen)\n+{\n+ int delta = newlen - oldlen;\n+ int err;\n+\n+ if ((err = fdt_splice_(fdt, p, oldlen, newlen)))\n+ return err;\n+\n+ fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);\n+ fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);\n+ return 0;\n+}\n+\n+static int fdt_splice_string_(void *fdt, int newlen)\n+{\n+ void *p = (char *)fdt\n+ + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);\n+ int err;\n+\n+ if ((err = fdt_splice_(fdt, p, 0, newlen)))\n+ return err;\n+\n+ fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);\n+ return 0;\n+}\n+\n+static int fdt_find_add_string_(void *fdt, const char *s)\n+{\n+ char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);\n+ const char *p;\n+ char *new;\n+ int len = strlen(s) + 1;\n+ int err;\n+\n+ p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s);\n+ if (p)\n+ /* found it */\n+ return (p - strtab);\n+\n+ new = strtab + fdt_size_dt_strings(fdt);\n+ err = fdt_splice_string_(fdt, len);\n+ if (err)\n+ return err;\n+\n+ memcpy(new, s, len);\n+ return (new - strtab);\n+}\n+\n+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)\n+{\n+ struct fdt_reserve_entry *re;\n+ int err;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt));\n+ err = fdt_splice_mem_rsv_(fdt, re, 0, 1);\n+ if (err)\n+ return err;\n+\n+ re->address = cpu_to_fdt64(address);\n+ re->size = cpu_to_fdt64(size);\n+ return 0;\n+}\n+\n+int fdt_del_mem_rsv(void *fdt, int n)\n+{\n+ struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n);\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ if (n >= fdt_num_mem_rsv(fdt))\n+ return -FDT_ERR_NOTFOUND;\n+\n+ return fdt_splice_mem_rsv_(fdt, re, 1, 0);\n+}\n+\n+static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name,\n+ int len, struct fdt_property **prop)\n+{\n+ int oldlen;\n+ int err;\n+\n+ *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);\n+ if (!*prop)\n+ return oldlen;\n+\n+ if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),\n+ FDT_TAGALIGN(len))))\n+ return err;\n+\n+ (*prop)->len = cpu_to_fdt32(len);\n+ return 0;\n+}\n+\n+static int fdt_add_property_(void *fdt, int nodeoffset, const char *name,\n+ int len, struct fdt_property **prop)\n+{\n+ int proplen;\n+ int nextoffset;\n+ int namestroff;\n+ int err;\n+\n+ if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)\n+ return nextoffset;\n+\n+ namestroff = fdt_find_add_string_(fdt, name);\n+ if (namestroff < 0)\n+ return namestroff;\n+\n+ *prop = fdt_offset_ptr_w_(fdt, nextoffset);\n+ proplen = sizeof(**prop) + FDT_TAGALIGN(len);\n+\n+ err = fdt_splice_struct_(fdt, *prop, 0, proplen);\n+ if (err)\n+ return err;\n+\n+ (*prop)->tag = cpu_to_fdt32(FDT_PROP);\n+ (*prop)->nameoff = cpu_to_fdt32(namestroff);\n+ (*prop)->len = cpu_to_fdt32(len);\n+ return 0;\n+}\n+\n+int fdt_set_name(void *fdt, int nodeoffset, const char *name)\n+{\n+ char *namep;\n+ int oldlen, newlen;\n+ int err;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);\n+ if (!namep)\n+ return oldlen;\n+\n+ newlen = strlen(name);\n+\n+ err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1),\n+ FDT_TAGALIGN(newlen+1));\n+ if (err)\n+ return err;\n+\n+ memcpy(namep, name, newlen+1);\n+ return 0;\n+}\n+\n+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,\n+ int len, void **prop_data)\n+{\n+ struct fdt_property *prop;\n+ int err;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop);\n+ if (err == -FDT_ERR_NOTFOUND)\n+ err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);\n+ if (err)\n+ return err;\n+\n+ *prop_data = prop->data;\n+ return 0;\n+}\n+\n+int fdt_setprop(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len)\n+{\n+ void *prop_data;\n+ int err;\n+\n+ err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data);\n+ if (err)\n+ return err;\n+\n+ if (len)\n+ memcpy(prop_data, val, len);\n+ return 0;\n+}\n+\n+int fdt_appendprop(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len)\n+{\n+ struct fdt_property *prop;\n+ int err, oldlen, newlen;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);\n+ if (prop) {\n+ newlen = len + oldlen;\n+ err = fdt_splice_struct_(fdt, prop->data,\n+ FDT_TAGALIGN(oldlen),\n+ FDT_TAGALIGN(newlen));\n+ if (err)\n+ return err;\n+ prop->len = cpu_to_fdt32(newlen);\n+ memcpy(prop->data + oldlen, val, len);\n+ } else {\n+ err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);\n+ if (err)\n+ return err;\n+ memcpy(prop->data, val, len);\n+ }\n+ return 0;\n+}\n+\n+int fdt_delprop(void *fdt, int nodeoffset, const char *name)\n+{\n+ struct fdt_property *prop;\n+ int len, proplen;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ prop = fdt_get_property_w(fdt, nodeoffset, name, &len);\n+ if (!prop)\n+ return len;\n+\n+ proplen = sizeof(*prop) + FDT_TAGALIGN(len);\n+ return fdt_splice_struct_(fdt, prop, proplen, 0);\n+}\n+\n+int fdt_add_subnode_namelen(void *fdt, int parentoffset,\n+ const char *name, int namelen)\n+{\n+ struct fdt_node_header *nh;\n+ int offset, nextoffset;\n+ int nodelen;\n+ int err;\n+ uint32_t tag;\n+ fdt32_t *endtag;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);\n+ if (offset >= 0)\n+ return -FDT_ERR_EXISTS;\n+ else if (offset != -FDT_ERR_NOTFOUND)\n+ return offset;\n+\n+ /* Try to place the new node after the parent's properties */\n+ fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */\n+ do {\n+ offset = nextoffset;\n+ tag = fdt_next_tag(fdt, offset, &nextoffset);\n+ } while ((tag == FDT_PROP) || (tag == FDT_NOP));\n+\n+ nh = fdt_offset_ptr_w_(fdt, offset);\n+ nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;\n+\n+ err = fdt_splice_struct_(fdt, nh, 0, nodelen);\n+ if (err)\n+ return err;\n+\n+ nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);\n+ memset(nh->name, 0, FDT_TAGALIGN(namelen+1));\n+ memcpy(nh->name, name, namelen);\n+ endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);\n+ *endtag = cpu_to_fdt32(FDT_END_NODE);\n+\n+ return offset;\n+}\n+\n+int fdt_add_subnode(void *fdt, int parentoffset, const char *name)\n+{\n+ return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));\n+}\n+\n+int fdt_del_node(void *fdt, int nodeoffset)\n+{\n+ int endoffset;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ endoffset = fdt_node_end_offset_(fdt, nodeoffset);\n+ if (endoffset < 0)\n+ return endoffset;\n+\n+ return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset),\n+ endoffset - nodeoffset, 0);\n+}\n+\n+static void fdt_packblocks_(const char *old, char *new,\n+ int mem_rsv_size, int struct_size)\n+{\n+ int mem_rsv_off, struct_off, strings_off;\n+\n+ mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);\n+ struct_off = mem_rsv_off + mem_rsv_size;\n+ strings_off = struct_off + struct_size;\n+\n+ memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);\n+ fdt_set_off_mem_rsvmap(new, mem_rsv_off);\n+\n+ memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);\n+ fdt_set_off_dt_struct(new, struct_off);\n+ fdt_set_size_dt_struct(new, struct_size);\n+\n+ memmove(new + strings_off, old + fdt_off_dt_strings(old),\n+ fdt_size_dt_strings(old));\n+ fdt_set_off_dt_strings(new, strings_off);\n+ fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));\n+}\n+\n+int fdt_open_into(const void *fdt, void *buf, int bufsize)\n+{\n+ int err;\n+ int mem_rsv_size, struct_size;\n+ int newsize;\n+ const char *fdtstart = fdt;\n+ const char *fdtend = fdtstart + fdt_totalsize(fdt);\n+ char *tmp;\n+\n+ FDT_RO_PROBE(fdt);\n+\n+ mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)\n+ * sizeof(struct fdt_reserve_entry);\n+\n+ if (fdt_version(fdt) >= 17) {\n+ struct_size = fdt_size_dt_struct(fdt);\n+ } else {\n+ struct_size = 0;\n+ while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)\n+ ;\n+ if (struct_size < 0)\n+ return struct_size;\n+ }\n+\n+ if (!fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) {\n+ /* no further work necessary */\n+ err = fdt_move(fdt, buf, bufsize);\n+ if (err)\n+ return err;\n+ fdt_set_version(buf, 17);\n+ fdt_set_size_dt_struct(buf, struct_size);\n+ fdt_set_totalsize(buf, bufsize);\n+ return 0;\n+ }\n+\n+ /* Need to reorder */\n+ newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size\n+ + struct_size + fdt_size_dt_strings(fdt);\n+\n+ if (bufsize < newsize)\n+ return -FDT_ERR_NOSPACE;\n+\n+ /* First attempt to build converted tree at beginning of buffer */\n+ tmp = buf;\n+ /* But if that overlaps with the old tree... */\n+ if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {\n+ /* Try right after the old tree instead */\n+ tmp = (char *)(uintptr_t)fdtend;\n+ if ((tmp + newsize) > ((char *)buf + bufsize))\n+ return -FDT_ERR_NOSPACE;\n+ }\n+\n+ fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size);\n+ memmove(buf, tmp, newsize);\n+\n+ fdt_set_magic(buf, FDT_MAGIC);\n+ fdt_set_totalsize(buf, bufsize);\n+ fdt_set_version(buf, 17);\n+ fdt_set_last_comp_version(buf, 16);\n+ fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));\n+\n+ return 0;\n+}\n+\n+int fdt_pack(void *fdt)\n+{\n+ int mem_rsv_size;\n+\n+ FDT_RW_PROBE(fdt);\n+\n+ mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)\n+ * sizeof(struct fdt_reserve_entry);\n+ fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));\n+ fdt_set_totalsize(fdt, fdt_data_size_(fdt));\n+\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..92853fe6a25352cae9ba7abe92d964fdcfcac66e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c\n@@ -0,0 +1,81 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+struct fdt_errtabent {\n+ const char *str;\n+};\n+\n+#define FDT_ERRTABENT(val) \\\n+ [(val)] = { .str = #val, }\n+\n+static struct fdt_errtabent fdt_errtable[] = {\n+ FDT_ERRTABENT(FDT_ERR_NOTFOUND),\n+ FDT_ERRTABENT(FDT_ERR_EXISTS),\n+ FDT_ERRTABENT(FDT_ERR_NOSPACE),\n+\n+ FDT_ERRTABENT(FDT_ERR_BADOFFSET),\n+ FDT_ERRTABENT(FDT_ERR_BADPATH),\n+ FDT_ERRTABENT(FDT_ERR_BADPHANDLE),\n+ FDT_ERRTABENT(FDT_ERR_BADSTATE),\n+\n+ FDT_ERRTABENT(FDT_ERR_TRUNCATED),\n+ FDT_ERRTABENT(FDT_ERR_BADMAGIC),\n+ FDT_ERRTABENT(FDT_ERR_BADVERSION),\n+ FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),\n+ FDT_ERRTABENT(FDT_ERR_BADLAYOUT),\n+ FDT_ERRTABENT(FDT_ERR_INTERNAL),\n+ FDT_ERRTABENT(FDT_ERR_BADNCELLS),\n+ FDT_ERRTABENT(FDT_ERR_BADVALUE),\n+ FDT_ERRTABENT(FDT_ERR_BADOVERLAY),\n+ FDT_ERRTABENT(FDT_ERR_NOPHANDLES),\n+};\n+#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))\n+\n+const char *fdt_strerror(int errval)\n+{\n+ if (errval > 0)\n+ return \"<valid offset/length>\";\n+ else if (errval == 0)\n+ return \"<no error>\";\n+ else if (errval > -FDT_ERRTABSIZE) {\n+ const char *s = fdt_errtable[-errval].str;\n+\n+ if (s)\n+ return s;\n+ }\n+\n+ return \"<unknown error>\";\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a16d4c3f38652b61c609fda9d77f33da3ff1f383\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c\n@@ -0,0 +1,344 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+static int fdt_sw_probe_(void *fdt)\n+{\n+ if (fdt_magic(fdt) == FDT_MAGIC)\n+ return -FDT_ERR_BADSTATE;\n+ else if (fdt_magic(fdt) != FDT_SW_MAGIC)\n+ return -FDT_ERR_BADMAGIC;\n+ return 0;\n+}\n+\n+#define FDT_SW_PROBE(fdt) \\\n+ { \\\n+ int err; \\\n+ if ((err = fdt_sw_probe_(fdt)) != 0) \\\n+ return err; \\\n+ }\n+\n+/* 'memrsv' state: Initial state after fdt_create()\n+ *\n+ * Allowed functions:\n+ * fdt_add_reservmap_entry()\n+ * fdt_finish_reservemap() [moves to 'struct' state]\n+ */\n+static int fdt_sw_probe_memrsv_(void *fdt)\n+{\n+ int err = fdt_sw_probe_(fdt);\n+ if (err)\n+ return err;\n+\n+ if (fdt_off_dt_strings(fdt) != 0)\n+ return -FDT_ERR_BADSTATE;\n+ return 0;\n+}\n+\n+#define FDT_SW_PROBE_MEMRSV(fdt) \\\n+ { \\\n+ int err; \\\n+ if ((err = fdt_sw_probe_memrsv_(fdt)) != 0) \\\n+ return err; \\\n+ }\n+\n+/* 'struct' state: Enter this state after fdt_finish_reservemap()\n+ *\n+ * Allowed functions:\n+ * fdt_begin_node()\n+ * fdt_end_node()\n+ * fdt_property*()\n+ * fdt_finish() [moves to 'complete' state]\n+ */\n+static int fdt_sw_probe_struct_(void *fdt)\n+{\n+ int err = fdt_sw_probe_(fdt);\n+ if (err)\n+ return err;\n+\n+ if (fdt_off_dt_strings(fdt) != fdt_totalsize(fdt))\n+ return -FDT_ERR_BADSTATE;\n+ return 0;\n+}\n+\n+#define FDT_SW_PROBE_STRUCT(fdt) \\\n+ { \\\n+ int err; \\\n+ if ((err = fdt_sw_probe_struct_(fdt)) != 0) \\\n+ return err; \\\n+ }\n+\n+/* 'complete' state: Enter this state after fdt_finish()\n+ *\n+ * Allowed functions: none\n+ */\n+\n+static void *fdt_grab_space_(void *fdt, size_t len)\n+{\n+ int offset = fdt_size_dt_struct(fdt);\n+ int spaceleft;\n+\n+ spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)\n+ - fdt_size_dt_strings(fdt);\n+\n+ if ((offset + len < offset) || (offset + len > spaceleft))\n+ return NULL;\n+\n+ fdt_set_size_dt_struct(fdt, offset + len);\n+ return fdt_offset_ptr_w_(fdt, offset);\n+}\n+\n+int fdt_create(void *buf, int bufsize)\n+{\n+ const size_t hdrsize = FDT_ALIGN(sizeof(struct fdt_header),\n+ sizeof(struct fdt_reserve_entry));\n+ void *fdt = buf;\n+\n+ if (bufsize < hdrsize)\n+ return -FDT_ERR_NOSPACE;\n+\n+ memset(buf, 0, bufsize);\n+\n+ fdt_set_magic(fdt, FDT_SW_MAGIC);\n+ fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);\n+ fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);\n+ fdt_set_totalsize(fdt, bufsize);\n+\n+ fdt_set_off_mem_rsvmap(fdt, hdrsize);\n+ fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));\n+ fdt_set_off_dt_strings(fdt, 0);\n+\n+ return 0;\n+}\n+\n+int fdt_resize(void *fdt, void *buf, int bufsize)\n+{\n+ size_t headsize, tailsize;\n+ char *oldtail, *newtail;\n+\n+ FDT_SW_PROBE(fdt);\n+\n+ headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);\n+ tailsize = fdt_size_dt_strings(fdt);\n+\n+ if ((headsize + tailsize) > fdt_totalsize(fdt))\n+ return -FDT_ERR_INTERNAL;\n+\n+ if ((headsize + tailsize) > bufsize)\n+ return -FDT_ERR_NOSPACE;\n+\n+ oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize;\n+ newtail = (char *)buf + bufsize - tailsize;\n+\n+ /* Two cases to avoid clobbering data if the old and new\n+ * buffers partially overlap */\n+ if (buf <= fdt) {\n+ memmove(buf, fdt, headsize);\n+ memmove(newtail, oldtail, tailsize);\n+ } else {\n+ memmove(newtail, oldtail, tailsize);\n+ memmove(buf, fdt, headsize);\n+ }\n+\n+ fdt_set_totalsize(buf, bufsize);\n+ if (fdt_off_dt_strings(buf))\n+ fdt_set_off_dt_strings(buf, bufsize);\n+\n+ return 0;\n+}\n+\n+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)\n+{\n+ struct fdt_reserve_entry *re;\n+ int offset;\n+\n+ FDT_SW_PROBE_MEMRSV(fdt);\n+\n+ offset = fdt_off_dt_struct(fdt);\n+ if ((offset + sizeof(*re)) > fdt_totalsize(fdt))\n+ return -FDT_ERR_NOSPACE;\n+\n+ re = (struct fdt_reserve_entry *)((char *)fdt + offset);\n+ re->address = cpu_to_fdt64(addr);\n+ re->size = cpu_to_fdt64(size);\n+\n+ fdt_set_off_dt_struct(fdt, offset + sizeof(*re));\n+\n+ return 0;\n+}\n+\n+int fdt_finish_reservemap(void *fdt)\n+{\n+ int err = fdt_add_reservemap_entry(fdt, 0, 0);\n+\n+ if (err)\n+ return err;\n+\n+ fdt_set_off_dt_strings(fdt, fdt_totalsize(fdt));\n+ return 0;\n+}\n+\n+int fdt_begin_node(void *fdt, const char *name)\n+{\n+ struct fdt_node_header *nh;\n+ int namelen;\n+\n+ FDT_SW_PROBE_STRUCT(fdt);\n+\n+ namelen = strlen(name) + 1;\n+ nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));\n+ if (! nh)\n+ return -FDT_ERR_NOSPACE;\n+\n+ nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);\n+ memcpy(nh->name, name, namelen);\n+ return 0;\n+}\n+\n+int fdt_end_node(void *fdt)\n+{\n+ fdt32_t *en;\n+\n+ FDT_SW_PROBE_STRUCT(fdt);\n+\n+ en = fdt_grab_space_(fdt, FDT_TAGSIZE);\n+ if (! en)\n+ return -FDT_ERR_NOSPACE;\n+\n+ *en = cpu_to_fdt32(FDT_END_NODE);\n+ return 0;\n+}\n+\n+static int fdt_find_add_string_(void *fdt, const char *s)\n+{\n+ char *strtab = (char *)fdt + fdt_totalsize(fdt);\n+ const char *p;\n+ int strtabsize = fdt_size_dt_strings(fdt);\n+ int len = strlen(s) + 1;\n+ int struct_top, offset;\n+\n+ p = fdt_find_string_(strtab - strtabsize, strtabsize, s);\n+ if (p)\n+ return p - strtab;\n+\n+ /* Add it */\n+ offset = -strtabsize - len;\n+ struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);\n+ if (fdt_totalsize(fdt) + offset < struct_top)\n+ return 0; /* no more room :( */\n+\n+ memcpy(strtab + offset, s, len);\n+ fdt_set_size_dt_strings(fdt, strtabsize + len);\n+ return offset;\n+}\n+\n+int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp)\n+{\n+ struct fdt_property *prop;\n+ int nameoff;\n+\n+ FDT_SW_PROBE_STRUCT(fdt);\n+\n+ nameoff = fdt_find_add_string_(fdt, name);\n+ if (nameoff == 0)\n+ return -FDT_ERR_NOSPACE;\n+\n+ prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len));\n+ if (! prop)\n+ return -FDT_ERR_NOSPACE;\n+\n+ prop->tag = cpu_to_fdt32(FDT_PROP);\n+ prop->nameoff = cpu_to_fdt32(nameoff);\n+ prop->len = cpu_to_fdt32(len);\n+ *valp = prop->data;\n+ return 0;\n+}\n+\n+int fdt_property(void *fdt, const char *name, const void *val, int len)\n+{\n+ void *ptr;\n+ int ret;\n+\n+ ret = fdt_property_placeholder(fdt, name, len, &ptr);\n+ if (ret)\n+ return ret;\n+ memcpy(ptr, val, len);\n+ return 0;\n+}\n+\n+int fdt_finish(void *fdt)\n+{\n+ char *p = (char *)fdt;\n+ fdt32_t *end;\n+ int oldstroffset, newstroffset;\n+ uint32_t tag;\n+ int offset, nextoffset;\n+\n+ FDT_SW_PROBE_STRUCT(fdt);\n+\n+ /* Add terminator */\n+ end = fdt_grab_space_(fdt, sizeof(*end));\n+ if (! end)\n+ return -FDT_ERR_NOSPACE;\n+ *end = cpu_to_fdt32(FDT_END);\n+\n+ /* Relocate the string table */\n+ oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);\n+ newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);\n+ memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));\n+ fdt_set_off_dt_strings(fdt, newstroffset);\n+\n+ /* Walk the structure, correcting string offsets */\n+ offset = 0;\n+ while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {\n+ if (tag == FDT_PROP) {\n+ struct fdt_property *prop =\n+ fdt_offset_ptr_w_(fdt, offset);\n+ int nameoff;\n+\n+ nameoff = fdt32_to_cpu(prop->nameoff);\n+ nameoff += fdt_size_dt_strings(fdt);\n+ prop->nameoff = cpu_to_fdt32(nameoff);\n+ }\n+ offset = nextoffset;\n+ }\n+ if (nextoffset < 0)\n+ return nextoffset;\n+\n+ /* Finally, adjust the header */\n+ fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));\n+ fdt_set_magic(fdt, FDT_MAGIC);\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e97f2828516b2181042e0044d5d07662150b4cab\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c\n@@ -0,0 +1,118 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"libfdt_env.h\"\n+\n+#include <fdt.h>\n+#include <libfdt.h>\n+\n+#include \"libfdt_internal.h\"\n+\n+int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,\n+ const char *name, int namelen,\n+ uint32_t idx, const void *val,\n+ int len)\n+{\n+ void *propval;\n+ int proplen;\n+\n+ propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen,\n+ &proplen);\n+ if (!propval)\n+ return proplen;\n+\n+ if (proplen < (len + idx))\n+ return -FDT_ERR_NOSPACE;\n+\n+ memcpy((char *)propval + idx, val, len);\n+ return 0;\n+}\n+\n+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,\n+ const void *val, int len)\n+{\n+ const void *propval;\n+ int proplen;\n+\n+ propval = fdt_getprop(fdt, nodeoffset, name, &proplen);\n+ if (!propval)\n+ return proplen;\n+\n+ if (proplen != len)\n+ return -FDT_ERR_NOSPACE;\n+\n+ return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,\n+ strlen(name), 0,\n+ val, len);\n+}\n+\n+static void fdt_nop_region_(void *start, int len)\n+{\n+ fdt32_t *p;\n+\n+ for (p = start; (char *)p < ((char *)start + len); p++)\n+ *p = cpu_to_fdt32(FDT_NOP);\n+}\n+\n+int fdt_nop_property(void *fdt, int nodeoffset, const char *name)\n+{\n+ struct fdt_property *prop;\n+ int len;\n+\n+ prop = fdt_get_property_w(fdt, nodeoffset, name, &len);\n+ if (!prop)\n+ return len;\n+\n+ fdt_nop_region_(prop, len + sizeof(*prop));\n+\n+ return 0;\n+}\n+\n+int fdt_node_end_offset_(void *fdt, int offset)\n+{\n+ int depth = 0;\n+\n+ while ((offset >= 0) && (depth >= 0))\n+ offset = fdt_next_node(fdt, offset, &depth);\n+\n+ return offset;\n+}\n+\n+int fdt_nop_node(void *fdt, int nodeoffset)\n+{\n+ int endoffset;\n+\n+ endoffset = fdt_node_end_offset_(fdt, nodeoffset);\n+ if (endoffset < 0)\n+ return endoffset;\n+\n+ fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0),\n+ endoffset - nodeoffset);\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c b/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e0e7ddd421b79cd1569aee9f1c8185ac59d99dab\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c\n@@ -0,0 +1,67 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <string.h>\n+#include <FreeRTOS.h>\n+#include <task.h>\n+#include <queue.h>\n+#include <timers.h>\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+#include <cli.h>\n+#endif\n+\n+#include <utils_log.h>\n+#include <utils_fec.h>\n+\n+static void blfdt(char *buf, int len, int argc, char **argv)\n+{\n+ int tc_fdt_wifi(void);\n+ int tc_blfdtdump(void);\n+\n+ tc_fdt_wifi();\n+ tc_blfdtdump();\n+}\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+// STATIC_CLI_CMD_ATTRIBUTE makes this(these) command(s) static\n+const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {\n+ { \"blfdt\", \"blfdt\", blfdt}\n+};\n+#endif\n+\n+int blfdt_cli_init(void)\n+{\n+ // static command(s) do NOT need to call aos_cli_register_command(s) to register.\n+ // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.\n+ // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.\n+ //return aos_cli_register_commands(cmds_user, sizeof(cmds_user)/sizeof(cmds_user[0]));\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3356eaea05f48905b4209e256a3d3879434badd0\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c\n@@ -0,0 +1,766 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/*\n+ * fdtdump.c - Contributed by Pantelis Antoniou <pantelis.antoniou AT gmail.com>\n+ */\n+\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <ctype.h>\n+#include <inttypes.h>\n+\n+#include <libfdt.h>\n+\n+#include <utils_log.h>\n+// #include \"log/log.h\"\n+\n+#define FDT_MAGIC_SIZE 4\n+#define MAX_VERSION 17\n+\n+#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1))\n+#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a))))\n+#define GET_CELL(p) (p += 4, *((const fdt32_t *)(p-4)))\n+\n+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n+\n+static const char *tagname(uint32_t tag)\n+{\n+ static const char * const names[] = {\n+#define TN(t) [t] = #t\n+ TN(FDT_BEGIN_NODE),\n+ TN(FDT_END_NODE),\n+ TN(FDT_PROP),\n+ TN(FDT_NOP),\n+ TN(FDT_END),\n+#undef TN\n+ };\n+ if (tag < ARRAY_SIZE(names)) {\n+ if (names[tag]) {\n+ return names[tag];\n+ }\n+ }\n+\n+ return \"FDT_???\";\n+}\n+\n+#define dumpf(fmt, args...) \\\n+ do { if (debug) printf(\"// \" fmt, ## args); } while (0)\n+\n+bool util_is_printable_string(const void *data, int len)\n+{\n+ const char *s = data;\n+ const char *ss, *se;\n+\n+ /* zero length is not */\n+ if (len == 0) {\n+ return 0;\n+ }\n+\n+ /* must terminate with zero */\n+ if (s[len - 1] != '\\0') {\n+ return 0;\n+ }\n+\n+ se = s + len;\n+\n+ while (s < se) {\n+ ss = s;\n+ while (s < se && *s && isprint((unsigned char)*s)) {\n+ s++;\n+ }\n+\n+ /* not zero, or not done yet */\n+ if (*s != '\\0' || s == ss) {\n+ return 0;\n+ }\n+\n+ s++;\n+ }\n+\n+ return 1;\n+}\n+\n+void utilfdt_print_data(const char *data, int len)\n+{\n+ int i;\n+ const char *s;\n+\n+ /* no data, don't print */\n+ if (len == 0) {\n+ return;\n+ }\n+\n+ if (util_is_printable_string(data, len)) {\n+ printf(\" = \");\n+\n+ s = data;\n+ do {\n+ printf(\"\\\"%s\\\"\", s);\n+ s += strlen(s) + 1;\n+ if (s < data + len)\n+ printf(\", \");\n+ } while (s < data + len);\n+\n+ } else if ((len % 4) == 0) {\n+ const fdt32_t *cell = (const fdt32_t *)data;\n+\n+ printf(\" = <\");\n+ for (i = 0, len /= 4; i < len; i++) {\n+ printf(\"0x%08x%s\", (unsigned int)fdt32_to_cpu(cell[i]),\n+ i < (len - 1) ? \" \" : \"\");\n+ }\n+ printf(\">\");\n+ } else {\n+ const unsigned char *p = (const unsigned char *)data;\n+ printf(\" = [\");\n+ for (i = 0; i < len; i++) {\n+ printf(\"%02x%s\", *p++, i < len - 1 ? \" \" : \"\");\n+ }\n+ printf(\"]\");\n+ }\n+}\n+\n+static void dump_blob(void *blob, bool debug)\n+{\n+ uintptr_t blob_off = (uintptr_t)blob;\n+ struct fdt_header *bph = blob;\n+ uint32_t off_mem_rsvmap = fdt32_to_cpu(bph->off_mem_rsvmap);\n+ uint32_t off_dt = fdt32_to_cpu(bph->off_dt_struct);\n+ uint32_t off_str = fdt32_to_cpu(bph->off_dt_strings);\n+ struct fdt_reserve_entry *p_rsvmap =\n+ (struct fdt_reserve_entry *)((char *)blob + off_mem_rsvmap);\n+ const char *p_struct = (const char *)blob + off_dt;\n+ const char *p_strings = (const char *)blob + off_str;\n+ uint32_t version = fdt32_to_cpu(bph->version);\n+ uint32_t totalsize = fdt32_to_cpu(bph->totalsize);\n+ uint32_t tag;\n+ const char *p, *s, *t;\n+ int depth, sz, shift;\n+ int i;\n+ uint64_t addr, size;\n+\n+ depth = 0;\n+ shift = 4;\n+\n+ printf(\"/dts-v1/;\\r\\n\");\n+ printf(\"// magic:\\t\\t0x%\"PRIx32\"\\r\\n\", fdt32_to_cpu(bph->magic));\n+ printf(\"// totalsize:\\t\\t0x%\"PRIx32\" (%\"PRIu32\")\\r\\n\",\n+ totalsize, totalsize);\n+ printf(\"// off_dt_struct:\\t0x%\"PRIx32\"\\r\\n\", off_dt);\n+ printf(\"// off_dt_strings:\\t0x%\"PRIx32\"\\r\\n\", off_str);\n+ printf(\"// off_mem_rsvmap:\\t0x%\"PRIx32\"\\r\\n\", off_mem_rsvmap);\n+ printf(\"// version:\\t\\t%\"PRIu32\"\\r\\n\", version);\n+ printf(\"// last_comp_version:\\t%\"PRIu32\"\\r\\n\",\n+ fdt32_to_cpu(bph->last_comp_version));\n+ if (version >= 2) {\n+ printf(\"// boot_cpuid_phys:\\t0x%\"PRIx32\"\\r\\n\",\n+ fdt32_to_cpu(bph->boot_cpuid_phys));\n+ }\n+\n+ if (version >= 3) {\n+ printf(\"// size_dt_strings:\\t0x%\"PRIx32\"\\r\\n\",\n+ fdt32_to_cpu(bph->size_dt_strings));\n+ }\n+\n+ if (version >= 17) {\n+ printf(\"// size_dt_struct:\\t0x%\"PRIx32\"\\r\\n\",\n+ fdt32_to_cpu(bph->size_dt_struct));\n+ }\n+\n+ printf(\"\\r\\n\");\n+\n+ for (i = 0; ; i++) {\n+ addr = fdt64_to_cpu(p_rsvmap[i].address);\n+ size = fdt64_to_cpu(p_rsvmap[i].size);\n+ if (addr == 0 && size == 0)\n+ break;\n+\n+ printf(\"/memreserve/ %#\"PRIx64\" %#\"PRIx64\";\\r\\n\",\n+ addr, size);\n+ }\n+\n+ p = p_struct;\n+\n+ // uint32_t index = 0;\n+ while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) {\n+\n+ // printf(\"index = %d\\r\\n\", index++);\n+ dumpf(\"%04\"PRIxPTR\": tag: 0x%08\"PRIx32\" (%s)\\r\\n\",\n+ (uintptr_t)p - blob_off - 4, tag, tagname(tag));\n+\n+ if (tag == FDT_BEGIN_NODE) {\n+ s = p;\n+ p = PALIGN(p + strlen(s) + 1, 4);\n+\n+ if (*s == '\\0')\n+ s = \"/\";\n+\n+ printf(\"%*s%s {\\r\\n\", depth * shift, \"\", s);\n+\n+ depth++;\n+ continue;\n+ }\n+\n+ if (tag == FDT_END_NODE) {\n+ depth--;\n+\n+ printf(\"%*s};\\r\\n\", depth * shift, \"\");\n+ continue;\n+ }\n+\n+ if (tag == FDT_NOP) {\n+ printf(\"%*s// [NOP]\\r\\n\", depth * shift, \"\");\n+ continue;\n+ }\n+\n+ if (tag != FDT_PROP) {\n+ log_error(\"%*s ** Unknown tag 0x%08\"PRIx32\"\\r\\n\", depth * shift, \"\", tag);\n+ break;\n+ }\n+ sz = fdt32_to_cpu(GET_CELL(p));\n+ s = p_strings + fdt32_to_cpu(GET_CELL(p));\n+ if (version < 16 && sz >= 8)\n+ p = PALIGN(p, 8);\n+ t = p;\n+\n+ p = PALIGN(p + sz, 4);\n+\n+ dumpf(\"%04\"PRIxPTR\": string: %s\\r\\n\", (uintptr_t)s - blob_off, s);\n+ dumpf(\"%04\"PRIxPTR\": value\\r\\n\", (uintptr_t)t - blob_off);\n+ printf(\"%*s%s\", depth * shift, \"\", s);\n+ utilfdt_print_data(t, sz);\n+ printf(\";\\r\\n\");\n+ }\n+}\n+\n+\n+static bool valid_header(char *p, uint32_t len)\n+{\n+ if (len < sizeof(struct fdt_header) ||\n+ fdt_magic(p) != FDT_MAGIC ||\n+ fdt_version(p) > MAX_VERSION ||\n+ fdt_last_comp_version(p) > MAX_VERSION ||\n+ fdt_totalsize(p) >= len ||\n+ fdt_off_dt_struct(p) >= len ||\n+ fdt_off_dt_strings(p) >= len) {\n+ return 0;\n+ }\n+ return 1;\n+}\n+/*\n+ input_buf\n+ input_len\n+ debug Dump debug information while decoding the file\n+ scan Scan for an embedded fdt in file\n+*/\n+\n+static int blfdtdump(const unsigned char *input_buf, const uint32_t input_len, uint8_t arg_debug, uint8_t arg_scan)\n+{\n+ const char *file = \"fdtbuff\";\n+ char *buf = (char *)input_buf;\n+ uint8_t debug = arg_debug;\n+ uint8_t scan = arg_scan;\n+ uint32_t len = (uint32_t)input_len;\n+ uint32_t this_len = 0;\n+\n+ // log_info(\"**** fdtdump is a low-level debugging tool, not meant for general use.\\r\\n\"\n+ // \"**** If you want to decompile a dtb, you probably want\\r\\n\"\n+ // \"**** dtc -I dtb -O dts <filename>\\r\\n\\r\\n\"\n+ // );\n+\n+ /* try and locate an embedded fdt in a bigger blob */\n+ if (scan) {\n+ unsigned char smagic[FDT_MAGIC_SIZE];\n+ char *p = buf;\n+ char *endp = buf + len;\n+\n+ fdt_set_magic(smagic, FDT_MAGIC);\n+\n+ /* poor man's memmem */\n+ while ((endp - p) >= FDT_MAGIC_SIZE) {\n+ p = memchr(p, smagic[0], endp - p - FDT_MAGIC_SIZE);\n+ if (!p) {\n+ break;\n+ }\n+ if (fdt_magic(p) == FDT_MAGIC) {\n+ /* try and validate the main struct */\n+ this_len = endp - p;\n+ if (valid_header(p, this_len)) {\n+ break;\n+ }\n+ if (debug) {\n+ printf(\"%s: skipping fdt magic at offset %#tx\\r\\n\",\n+ file, p - buf);\n+ }\n+ }\n+ ++p;\n+ }\n+ if (!p || endp - p < sizeof(struct fdt_header)) {\n+ log_error(\"%s: could not locate fdt magic\\r\\n\", file);\n+ return -1;\n+ }\n+ printf(\"%s: found fdt at offset %#tx\\r\\n\", file, p - buf);\n+ buf = p;\n+ } else if (!valid_header(buf, len)) {\n+ log_error(\"%s: header is not valid\\r\\n\", file);\n+ return -1;\n+ }\n+\n+ log_info(\"dump_blob.\");\n+\n+ dump_blob(buf, debug);\n+\n+ return 0;\n+}\n+\n+#define TC_WIFI_DTB_LEN (4779 + 4)\n+const uint8_t tc_wifi_dtb[TC_WIFI_DTB_LEN] = {\n+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x12, 0xab, 0x00, 0x00, 0x00, 0x38,\n+ 0x00, 0x00, 0x10, 0xc0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,\n+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xeb,\n+ 0x00, 0x00, 0x10, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13,\n+ 0x00, 0x00, 0x00, 0x00, 0x62, 0x6c, 0x20, 0x62, 0x6c, 0x36, 0x30, 0x78,\n+ 0x20, 0x41, 0x56, 0x42, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x00, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x06,\n+ 0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x2d, 0x73, 0x61, 0x6d,\n+ 0x70, 0x6c, 0x65, 0x00, 0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78,\n+ 0x2d, 0x63, 0x6f, 0x6d, 0x6d, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,\n+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,\n+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x69, 0x70, 0x63, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,\n+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,\n+ 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,\n+ 0x69, 0x70, 0x63, 0x40, 0x34, 0x30, 0x30, 0x31, 0x43, 0x30, 0x30, 0x30,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,\n+ 0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,\n+ 0x40, 0x01, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02,\n+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x73, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,\n+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,\n+ 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,\n+ 0x69, 0x32, 0x73, 0x40, 0x34, 0x30, 0x30, 0x31, 0x37, 0x30, 0x30, 0x30,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,\n+ 0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x06,\n+ 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32, 0x73, 0x00, 0x00, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,\n+ 0x40, 0x01, 0x70, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,\n+ 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x37, 0x6f, 0x6b, 0x61, 0x79,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x41,\n+ 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,\n+ 0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x73, 0x40, 0x34, 0x30, 0x30, 0x31,\n+ 0x37, 0x31, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,\n+ 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79,\n+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,\n+ 0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32,\n+ 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,\n+ 0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x71, 0x00, 0x00, 0x00, 0x01, 0x00,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x37,\n+ 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x01,\n+ 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 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0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32,\n+ 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,\n+ 0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,\n+ 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,\n+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00, 0x20,\n+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x58,\n+ 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,\n+ 0x64, 0x65, 0x76, 0x69, 0x63, 0x65, 0x73, 0x00, 0x00, 0x00, 0x00, 0x03,\n+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x00, 0x18,\n+ 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x17,\n+ 0x00, 0x00, 0x00, 0x66, 0x69, 0x32, 0x63, 0x5f, 0x65, 0x73, 0x38, 0x33,\n+ 0x31, 0x31, 0x00, 0x69, 0x32, 0x63, 0x5f, 0x67, 0x63, 0x30, 0x33, 0x30,\n+ 0x38, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,\n+ 0x00, 0x00, 0x00, 0x01, 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0x77, 0x72, 0x5f, 0x74, 0x61, 0x62,\n+ 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x64,\n+ 0x69, 0x76, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61,\n+ 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x63, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x62,\n+ 0x6c, 0x65, 0x00, 0x6c, 0x6f, 0x5f, 0x66, 0x63, 0x61, 0x6c, 0x5f, 0x64,\n+ 0x69, 0x76, 0x00\n+};\n+\n+int tc_blfdtdump(void)\n+{\n+ int result;\n+\n+ result = blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, true, true);\n+ \n+ if (result) {\n+ printf(\"dump failed\\r\\n\");\n+ } else {\n+ printf(\"dump successed\\r\\n\");\n+ }\n+ \n+ return result;\n+ \n+ // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, true);\n+ // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, false);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4fef123d7c96e2f589e1dda685da7d2141a6b282\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c\n@@ -0,0 +1,239 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <libfdt.h>\n+\n+#include <utils_log.h>\n+// #include \"log/log.h\"\n+\n+#define TC_WIFI_DTB_LEN (4779 + 4)\n+extern const uint8_t tc_wifi_dtb[];\n+\n+static int tc_fdt_wifi_module(void)\n+{\n+ const void *fdt = (const void *)tc_wifi_dtb;/* const tc_wifi_dtb */\n+\n+ int wifi_offset = 0;\n+ int offset1 = 0;\n+\n+ const uint32_t *addr_prop = 0;\n+ const char *result = 0;\n+ int lentmp = 0;\n+ int countindex = 0;\n+ int i;\n+\n+ /* get wifi offset */\n+ wifi_offset = fdt_subnode_offset(fdt, 0, \"wifi\");\n+ // wifi\n+ if (!(wifi_offset > 0)) {\n+ log_error(\"wifi NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi->region->country_code = u32\n+ offset1 = fdt_subnode_offset(fdt, wifi_offset, \"region\");\n+ if (offset1 > 0) {\n+ addr_prop = fdt_getprop(fdt, offset1, \"country_code\", &lentmp);\n+ if (addr_prop) {\n+ log_info(\"value = %ld, lentmp = %d\\r\\n\", fdt32_to_cpu(*addr_prop), lentmp);\n+ } else {\n+ log_error(\"country_code NULL.\\r\\n\");\n+ return -1;\n+ }\n+ }\n+ // wifi->mac\n+ offset1 = fdt_subnode_offset(fdt, wifi_offset, \"mac\");\n+ if (offset1 > 0) {\n+ // wifi->mac->sta_mac_addr = hex dump\n+ addr_prop = fdt_getprop(fdt, offset1, \"sta_mac_addr\", &lentmp);\n+ if (lentmp == 6) {\n+ uint8_t sta_mac[6];\n+\n+ memcpy(sta_mac, addr_prop, 6);\n+ log_info(\"sta_mac :\\r\\n\");\n+ log_buf(sta_mac, 6);\n+ } else {\n+ log_error(\"sta_mac_addr NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi->mac->ap_mac_addr = hex dump\n+ addr_prop = fdt_getprop(fdt, offset1, \"ap_mac_addr\", &lentmp);\n+ if (lentmp == 6) {\n+ uint8_t ap_mac[6];\n+\n+ memcpy(ap_mac, addr_prop, 6);\n+ log_info(\"ap_mac :\\r\\n\");\n+ log_buf(ap_mac, 6);\n+ }\n+ }\n+\n+ // wifi -> ap\n+ offset1 = fdt_subnode_offset(fdt, wifi_offset, \"ap\");\n+ if (offset1 > 0) {\n+ // wifi->ap->ssid = string\n+ countindex = fdt_stringlist_count(fdt, offset1, \"ssid\");\n+ if (countindex > 0) {\n+ for (i = 0; i < countindex; i++) {\n+ result = fdt_stringlist_get(fdt, offset1, \"ssid\", i, &lentmp);\n+ if (lentmp > 0) {/* !NULL */\n+ log_info(\"ap string[%d] = %s, lentmp = %d\\r\\n\", i, result, lentmp);\n+ }\n+ }\n+ } else {\n+ log_error(\"ap NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi->ap->pwd = string\n+ countindex = fdt_stringlist_count(fdt, offset1, \"pwd\");\n+ if (countindex > 0) {\n+ for (i = 0; i < countindex; i++) {\n+ result = fdt_stringlist_get(fdt, offset1, \"pwd\", i, &lentmp);\n+ if (lentmp > 0) {/* !NULL */\n+\n+ log_info(\"pwd string[%d] = %s, lentmp = %d\\r\\n\", i, result, lentmp);\n+ }\n+ }\n+ } else {\n+ log_error(\"pwd NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi->ap->ap_channel = u32\n+ addr_prop = fdt_getprop(fdt, offset1, \"ap_channel\", &lentmp);\n+ if (addr_prop) {\n+ log_info(\"ap_channel = %ld\\r\\n\", fdt32_to_cpu(*addr_prop));\n+ } else {\n+ log_error(\"ap_channel NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi->ap->auto_chan_detect = dis ? en\n+ countindex = fdt_stringlist_count(fdt, offset1, \"auto_chan_detect\");\n+ if (countindex > 0) {\n+ for (i = 0; i < countindex; i++) {\n+ result = fdt_stringlist_get(fdt, offset1, \"auto_chan_detect\", i, &lentmp);\n+ if (lentmp > 0) {/* !NULL */\n+ log_info(\"auto_chan_detect string[%d] = %s, lentmp = %d\\r\\n\", i, result, lentmp);\n+ }\n+ }\n+ } else {\n+ log_error(\"auto_chan_detect NULL.\\r\\n\");\n+ return -1;\n+ }\n+ } else {\n+ log_error(\"ap NULL.\\r\\n\");\n+ return -1;\n+ }\n+\n+ // wifi -> brd_rf\n+ offset1 = fdt_subnode_offset(fdt, wifi_offset, \"brd_rf\");\n+ if (offset1 > 0) {\n+ // wifi->brd_rf->xtal = u32 []\n+ addr_prop = fdt_getprop(fdt, offset1, \"xtal\", &lentmp);\n+ if (lentmp == 5*4) {\n+ uint8_t xtal[5*4];\n+\n+ memcpy(xtal, addr_prop, 5*4);\n+ log_info(\"xtal :\\r\\n\");\n+ log_buf(xtal, 5*4);\n+ } else {\n+ log_error(\"xtal NULL.\");\n+ return -1;\n+ }\n+ // wifi->brd_rf->pwr_table = u32 []\n+ addr_prop = fdt_getprop(fdt, offset1, \"pwr_table\", &lentmp);\n+ if (lentmp == 16*4*4) {\n+ uint8_t pwr_table[16*4*4];\n+\n+ memcpy(pwr_table, addr_prop, 16*4*4);\n+ log_info(\"pwr_table :\\r\\n\");\n+ log_buf(pwr_table, 16*4*4);\n+ } else {\n+ log_error(\"pwr_table NULL. lentmp = %d.\\r\\n\", lentmp);\n+ return -1;\n+ }\n+ // wifi->brd_rf->channel_div_table = u32 []\n+ addr_prop = fdt_getprop(fdt, offset1, \"channel_div_table\", &lentmp);\n+ if (lentmp == 15*4) {\n+ uint8_t channel_div_table[15*4];\n+\n+ memcpy(channel_div_table, addr_prop, 15*4);\n+ log_info(\"channel_div_table :\\r\\n\");\n+ log_buf(channel_div_table, 15*4);\n+ } else {\n+ log_error(\"channel_div_table NULL.\\r\\n\");\n+ return -1;\n+ }\n+ // wifi->brd_rf->channel_cnt_table = u32 []\n+ addr_prop = fdt_getprop(fdt, offset1, \"channel_cnt_table\", &lentmp);\n+ if (lentmp == 14*4) {\n+ uint8_t channel_cnt_table[14*4];\n+\n+ memcpy(channel_cnt_table, addr_prop, 14*4);\n+ log_info(\"channel_cnt_table :\\r\\n\");\n+ log_buf(channel_cnt_table, 14*4);\n+ } else {\n+ log_error(\"channel_cnt_table NULL.\\r\\n\");\n+ return -1;\n+ }\n+ // wifi->brd_rf->lo_fcal_div = u32\n+ addr_prop = fdt_getprop(fdt, offset1, \"lo_fcal_div\", &lentmp);\n+ if (lentmp == 1*4) {\n+ uint8_t lo_fcal_div[1*4];\n+\n+ memcpy(lo_fcal_div, addr_prop, 1*4);\n+ log_info(\"lo_fcal_div :\\r\\n\");\n+ log_buf(lo_fcal_div, 1*4);\n+ } else {\n+ log_error(\"lo_fcal_div NULL.\\r\\n\");\n+ return -1;\n+ }\n+ } else {\n+ log_error(\"brd_rf NULL.\\r\\n\");\n+ return -1;\n+ }\n+ \n+ return 0;\n+}\n+\n+int tc_fdt_wifi(void)\n+{\n+ int result;\n+ result = tc_fdt_wifi_module();\n+ \n+ if (result) {\n+ printf(\"fdt wifi module failed\\r\\n\");\n+ } else {\n+ printf(\"fdt wifi module successed\\r\\n\");\n+ }\n+ \n+ return result;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..9052b8496e8bf1f86ec75b4318c59135c9010e48\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh\n@@ -0,0 +1,40 @@\n+#!/bin/sh\n+##\n+## Copyright (c) 2016-2022 Bouffalolab.\n+##\n+## This file is part of\n+## *** Bouffalolab Software Dev Kit ***\n+## (see www.bouffalolab.com).\n+##\n+## Redistribution and use in source and binary forms, with or without modification,\n+## are permitted provided that the following conditions are met:\n+## 1. Redistributions of source code must retain the above copyright notice,\n+## this list of conditions and the following disclaimer.\n+## 2. Redistributions in binary form must reproduce the above copyright notice,\n+## this list of conditions and the following disclaimer in the documentation\n+## and/or other materials provided with the distribution.\n+## 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+## may be used to endorse or promote products derived from this software\n+## without specific prior written permission.\n+##\n+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+## SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+## CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+## OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+## OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+##\n+\n+curent_dir=$(pwd)\n+cd $curent_dir\n+echo $curent_dir\n+\n+echo \"tc_wifi. dts -> dtb\"\n+dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts\n+\n+echo \"tc_wifi. dtb -> c\"\n+xxd -i tc_wifi.dtb tc_wifi.c\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts\ndiff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e6a4e0dda6c06966ee9e66e8bdcedf6860649c98\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts\n@@ -0,0 +1,310 @@\n+\n+/*\n+ echo \"tc_wifi. dts -> dtb\"\n+ dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts\n+\n+ echo \"tc_wifi. dtb -> c\"\n+ xxd -i tc_wifi.dtb tc_wifi.c\n+*/\n+\n+/dts-v1/;\n+\n+/ {\n+ model = \"bl bl60x AVB board\";\n+ compatible = \"bl,bl60x-sample\", \"bl,bl60x-common\";\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+\n+ ipc {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ ipc@4001C000 {\n+ status = \"disable\";\n+ reg = <0x4001C000 0x100>;\n+ };\n+ };\n+ i2s {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ i2s@40017000 {\n+ status = \"okay\";\n+ compatible = \"bl60x_i2s\";\n+ reg = <0x40017000 0x100>;\n+ mclk_only = \"okay\";\n+ pin {\n+ mclk = <11>;\n+ };\n+ };\n+ i2s@40017100 {\n+ status = \"okay\";\n+ compatible = \"bl60x_i2s\";\n+ reg = <0x40017100 0x100>;\n+ mclk_only = \"disable\";\n+ pin {\n+ bclk = <12>;\n+ fs = <29>;\n+ do = <30>;\n+ di = <31>;\n+ };\n+ };\n+ };\n+ i2c {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ i2c@40011000 {\n+ status = \"okay\";\n+ compatible = \"bl60x_i2c\";\n+ reg = <0x40011000 0x100>;\n+ pin {\n+ scl = <32>;\n+ sda = <13>;\n+ };\n+ devices {\n+ list_addr = <0x18 0x21>;\n+ list_driver = \"i2c_es8311\", \"i2c_gc0308>\";\n+ };\n+ };\n+ i2c@40011100 {\n+ status = \"disable\";\n+ compatible = \"bl60x_i2c\";\n+ reg = <0x40011100 0x100>;\n+ pin {\n+ /*empty here*/\n+ };\n+ };\n+ };\n+ mjpeg {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ mjpeg@40016000 {\n+ status = \"okay\";\n+ compatible = \"bl60x_mjpeg\";\n+ reg = <0x40016000 0x100>;\n+ };\n+ };\n+ timer {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ timer@40014000 {\n+ status = \"disable\";\n+ compatible = \"bl60x_timer\";\n+ reg = <0x40014000 0x100>;\n+ };\n+ timer@40014100 {\n+ status = \"disable\";\n+ compatible = \"bl60x_timer\";\n+ reg = <0x40014100 0x100>;\n+ };\n+ };\n+ pwm {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ pwm@40012000 {\n+ status = \"disable\";\n+ compatible = \"bl60x_pwm\";\n+ reg = <0x40012000 0x100>;\n+ pin {\n+ /*empty here*/\n+ };\n+ };\n+ };\n+ uart {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ uart@40010000 {\n+ status = \"disable\";\n+ id = <0>;\n+ compatible = \"bl60x_uart\";\n+ path = \"/dev/ttyS0\";\n+ reg = <0x40010000 0x100>;\n+ baudrate = <115200>;\n+ pin {\n+ /*empty here*/\n+ };\n+ feature {\n+ rts = \"disable\";\n+ cts = \"disable\";\n+ rx = \"disable\";\n+ tx = \"disable\";\n+ };\n+ };\n+ uart@40010100 {\n+ status = \"disable\";\n+ id = <1>;\n+ compatible = \"bl60x_uart\";\n+ path = \"/dev/ttyS1\";\n+ reg = <0x40010100 0x100>;\n+ baudrate = <115200>;\n+ pin {\n+ /*empty here*/\n+ };\n+ feature {\n+ rts = \"disable\";\n+ cts = \"disable\";\n+ rx = \"disable\";\n+ tx = \"disable\";\n+ };\n+ };\n+ uart@40010200 {\n+ status = \"okay\";\n+ id = <2>;\n+ compatible = \"bl60x_uart\";\n+ path = \"/dev/ttyS2\";\n+ reg = <0x40010200 0x100>;\n+ baudrate = <5000000>;\n+ pin {\n+ tx = <14>;\n+ rx = <7>;\n+ };\n+ feature {\n+ tx = \"okay\";\n+ rx = \"okay\";\n+ cts = \"disable\";\n+ rts = \"disable\";\n+ };\n+ };\n+ };\n+ spi {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ spi@4000F000 {\n+ status = \"disable\";\n+ reg = <0x4000F000 0x100>;/* 4KB */\n+ };\n+ };\n+ gpip {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ adc_key {\n+ status = \"okay\";\n+ pin = <9>;\n+ interrupt = <3>;\n+ key_vol = <0 100 400 300 500>;\n+ key_pcb = \"SW1\", \"SW2\", \"SW3\", \"SW4\",\"SW5\";\n+ key_event = \"Usr1\", \"Usr2\", \"Start\", \"Up\", \"Down\";\n+ key_raw = <1 2 3 4 5>;\n+ };\n+ };\n+ pdm {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ pdm@4000C000 {\n+ status = \"disable\";\n+ reg = <0x4000C000 0x100>;/* 256B */\n+ };\n+ };\n+ cam {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ cam@4000B000 {\n+ status = \"okay\";\n+ compatible = \"bl60x_cam\";\n+ reg = <0x4000B000 0x1000>;/* 4KB */\n+ pin {\n+ PIX_CLK = <0>;\n+ FRAME_VLD = <1>;\n+ LINE_VLD = <2>;\n+ PIX_DAT0 = <3>;\n+ PIX_DAT1 = <4>;\n+ PIX_DAT2 = <5>;\n+ PIX_DAT3 = <6>;\n+ PIX_DAT4 = <25>;\n+ PIX_DAT5 = <26>;\n+ PIX_DAT6 = <27>;\n+ PIX_DAT7 = <28>;\n+ CAM_PWDN = <15>;\n+ CAM_REF_CLK = <24>;\n+ };\n+ feature {\n+ mode = \"HARDWARE\";\n+ };\n+ conf {\n+ sensor = \"auto\";\n+ };\n+ };\n+ };\n+ qspi {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ qspi@4000A000 {\n+ status = \"disable\";\n+ reg = <0x4000A000 0x1000>;/* 4KB */\n+ };\n+ };\n+ sdh {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ sdh@40003000 {\n+ status = \"okay\";\n+ compatible = \"bl60x_sdh\";\n+ reg = <0x40003000 0x1000>;/* 4KB */\n+ pin {\n+ clk = <16>;\n+ cmd = <17>;\n+ dat0 = <18>;\n+ dat1 = <19>;\n+ dat2 = <20>;\n+ dat3 = <21>;\n+ };\n+ };\n+ };\n+ wifi {\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ region {\n+ country_code = <86>;\n+ };\n+ mac {\n+ sta_mac_addr = [C8 43 57 82 73 40];\n+ ap_mac_addr = [C8 43 57 82 73 02];\n+ };\n+ ap {\n+ ssid = \"BL60x_Camera03\";\n+ pwd = \"1234567890a\";\n+ ap_channel = <11>;\n+ auto_chan_detect = \"disable\";\n+ };\n+ brd_rf {\n+ xtal = <41 41 0 63 63>;\n+ pwr_table = <4 3 3 186>,\n+ <4 3 4 176>,\n+ <4 3 5 167>,\n+ <3 3 0 159>,\n+ <3 3 1 149>,\n+ <3 3 2 140>,\n+ <3 3 3 129>,\n+ <3 3 4 119>,\n+ <3 3 5 110>,\n+ <2 3 0 101>,\n+ <2 3 1 91>,\n+ <2 3 2 82>,\n+ <2 3 3 72>,\n+ <2 3 4 62>,\n+ <2 3 5 52>,\n+ <1 3 3 10>;\n+ channel_div_table = <0x14F00000\n+ 0x14FB1C71\n+ 0x150638E3\n+ 0x15115555\n+ 0x151C71C7\n+ 0x15278E38\n+ 0x1532AAAA\n+ 0x153DC71C\n+ 0x1548E38E\n+ 0x15540000\n+ 0x155F1C71\n+ 0x156A38E3\n+ 0x15755555\n+ 0x15900000\n+ 0x15C00000>;\n+ channel_cnt_table = <0xa780 0xa7d8\n+ 0xa831 0xa88a\n+ 0xa8e3 0xa93c\n+ 0xa995 0xa9ee\n+ 0xaa47 0xaaa0\n+ 0xaaf8 0xab51\n+ 0xabaa 0xac80>;\n+ lo_fcal_div = <0x800>;\n+ };\n+ };\n+};\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blog/blog.c\ndiff --git a/bsp/bl808/m0/libraries/stage/blog/blog.c b/bsp/bl808/m0/libraries/stage/blog/blog.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6cb0587babd544f4a82e8d3f296097de7148992f\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blog/blog.c\n@@ -0,0 +1,369 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <stdio.h>\n+#include <string.h>\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+#include <cli.h>\n+#endif\n+\n+#include \"blog_type.h\"\n+#include \"blog_cfg.h\"\n+\n+#include <utils_log.h>\n+\n+#if BLOG_TEST\n+#include <blog_testc.h>\n+#endif\n+\n+/* every line log's buffer */\n+static char log_buf[BLOG_LINE_BUF_SIZE] = { 0 };\n+\n+static int findch_sum(const char *str, char ch)\n+{\n+ int i = 0;\n+ int len = strlen(str);\n+ int ret = 0;\n+\n+ for (i = 0; i < len; i++) {\n+ if (str[i] == ch) {\n+ ret++;\n+ }\n+ }\n+\n+ return ret;\n+}\n+static int set_level(int argc, char **argv)\n+{\n+ extern char _ld_bl_static_blogcomponent_code_start;\n+ extern char _ld_bl_static_blogcomponent_code_end;\n+ extern char _ld_bl_static_blogfile_code_start;\n+ extern char _ld_bl_static_blogfile_code_end;\n+ extern char _ld_bl_static_blogpri_code_start;\n+ extern char _ld_bl_static_blogpri_code_end;\n+\n+ blog_info_t *start;\n+ blog_info_t *end;\n+ blog_info_t *info;\n+\n+ int left;\n+ int right;\n+ uint32_t mid;\n+ int cmp_val;\n+ blog_level_t level;\n+\n+ int ch_sum;\n+\n+ if (argc != 3) {\n+ __blog_printf(\"arg error.\\r\\n\");\n+ return -1;\n+ }\n+\n+ /* get component level */\n+ if (0 == strcmp(argv[1], \"all\")) {\n+ level = BLOG_LEVEL_ALL;\n+ } else if (0 == strcmp(argv[1], \"debug\")) {\n+ level = BLOG_LEVEL_DEBUG;\n+ } else if (0 == strcmp(argv[1], \"info\")) {\n+ level = BLOG_LEVEL_INFO;\n+ } else if (0 == strcmp(argv[1], \"warn\")) {\n+ level = BLOG_LEVEL_WARN;\n+ } else if (0 == strcmp(argv[1], \"error\")) {\n+ level = BLOG_LEVEL_ERROR;\n+ } else if (0 == strcmp(argv[1], \"assert\")) {\n+ level = BLOG_LEVEL_ASSERT;\n+ } else if (0 == strcmp(argv[1], \"never\")) {\n+ level = BLOG_LEVEL_NEVER;\n+ } else {\n+ __blog_printf(\"input level = %s not support.\\r\\n\", argv[1]);\n+ return -1;\n+ }\n+\n+ /* component_name.file_name.pri_name */\n+ ch_sum = findch_sum(argv[2], '.');\n+\n+ if (0 == ch_sum) {\n+ start = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_start);\n+ end = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_end);\n+ } else if (1 == ch_sum) {\n+ start = (blog_info_t *)(&_ld_bl_static_blogfile_code_start);\n+ end = (blog_info_t *)(&_ld_bl_static_blogfile_code_end);\n+ } else if (2 == ch_sum) {\n+ start = (blog_info_t *)(&_ld_bl_static_blogpri_code_start);\n+ end = (blog_info_t *)(&_ld_bl_static_blogpri_code_end);\n+ } else {\n+ __blog_printf(\"input name = %s not support.\\r\\n\", argv[2]);\n+ return -1;\n+ }\n+\n+ left = 0;\n+ right = end - start - 1;\n+ while (left <= right) {\n+ mid = (left + right) >> 1;\n+ cmp_val = strcmp(start[mid].name, argv[2]);\n+ if (cmp_val < 0) {\n+ left = mid + 1;\n+ } else if (cmp_val > 0) {\n+ right = mid - 1;\n+ } else {\n+ info = &start[mid];\n+ break;\n+ }\n+ }\n+\n+ if (left > right) {\n+ __blog_printf(\"input name = %s not find.\\r\\n\", argv[2]);\n+ return -1;\n+ }\n+\n+ /* set level */\n+ *(info->level) = level;\n+ __blog_printf(\"set %s = %d\\r\\n\", info->name, *(info->level));\n+ return 0;\n+}\n+\n+void cmd_blog_set_level(char *buf, int len, int argc, char **argv)\n+{\n+ if (0 != set_level(argc, argv)) {\n+ __blog_printf(\"set blog error.\\r\\n\");\n+ }\n+}\n+\n+void cmd_blog_info_dump(char *buf, int len, int argc, char **argv)\n+{\n+ blog_info_t *info_c, *info_f, *info_p;\n+ char name_buf[BLOG_NAMELEN_MAX] = {0};\n+ \n+ extern char _ld_bl_static_blogcomponent_code_start;\n+ extern char _ld_bl_static_blogcomponent_code_end;\n+ extern char _ld_bl_static_blogfile_code_start;\n+ extern char _ld_bl_static_blogfile_code_end;\n+ extern char _ld_bl_static_blogpri_code_start;\n+ extern char _ld_bl_static_blogpri_code_end;\n+\n+ __blog_printf(\"blog code1 = %p - %p\\r\\n\", &_ld_bl_static_blogcomponent_code_start, &_ld_bl_static_blogcomponent_code_end);\n+ __blog_printf(\"blog code2 = %p - %p\\r\\n\", &_ld_bl_static_blogfile_code_start, &_ld_bl_static_blogfile_code_end);\n+ __blog_printf(\"blog code3 = %p - %p\\r\\n\", &_ld_bl_static_blogpri_code_start, &_ld_bl_static_blogpri_code_end);\n+\n+ for (info_c = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;\n+ (uint32_t)info_c < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info_c++) {\n+ if (strlen(info_c->name) > BLOG_NAMELEN_MAX) {\n+ __blog_printf(\"name too long.\\r\\n\");\n+ return;\n+ }\n+ if (name_buf[0] != 0) {\n+ if (0 == strcmp(name_buf, info_c->name)) {\n+#if BLOG_DUMP_DEDUPLICATE\n+ continue;\n+#endif \n+ } else {\n+ memset(name_buf, 0, strlen(name_buf));\n+ }\n+ }\n+ \n+ __blog_printf(\"[%-48s] = [%d]\\r\\n\", info_c->name, *(info_c->level));\n+ \n+ if ((name_buf[0] != 0) && (strcmp(info_c->name, name_buf) == 0)) {\n+ continue;\n+ }\n+ strcpy(name_buf, info_c->name);\n+\n+ for (info_f = (blog_info_t *)&_ld_bl_static_blogfile_code_start;\n+ (uint32_t)info_f < (uint32_t)&_ld_bl_static_blogfile_code_end; info_f++) {\n+\n+ if (strstr(info_f->name, info_c->name) == info_f->name) {\n+\n+ __blog_printf(\"[%-48s] = [%d]\\r\\n\", info_f->name, *(info_f->level));\n+\n+ for (info_p = (blog_info_t *)&_ld_bl_static_blogpri_code_start;\n+ (uint32_t)info_p < (uint32_t)&_ld_bl_static_blogpri_code_end; info_p++) {\n+\n+ if (strstr(info_p->name, info_f->name) == info_p->name) {\n+ __blog_printf(\"[%-48s] = [%d]\\r\\n\", info_p->name, *(info_p->level));\n+ }\n+ }\n+ }\n+ }\n+ }\n+}\n+\n+#if BLOG_TEST\n+void cmd_blog_test(char *buf, int len, int argc, char **argv)\n+{\n+ blog_testc_init();\n+}\n+#endif\n+\n+static void blog_set_poweron_softlevel(void)\n+{\n+ blog_info_t *info;\n+\n+ extern char _ld_bl_static_blogcomponent_code_start;\n+ extern char _ld_bl_static_blogcomponent_code_end;\n+ extern char _ld_bl_static_blogfile_code_start;\n+ extern char _ld_bl_static_blogfile_code_end;\n+ extern char _ld_bl_static_blogpri_code_start;\n+ extern char _ld_bl_static_blogpri_code_end;\n+\n+ __blog_printf(\"\\r\\nblog init set power on level %d, %d, %d.\\r\\n\", BLOG_POWERON_SOFTLEVEL_COMPONENT,\n+ BLOG_POWERON_SOFTLEVEL_FILE, BLOG_POWERON_SOFTLEVEL_PRI);\n+ for ( info = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;\n+ (uint32_t)info < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info++ ) {\n+ *(info->level) = BLOG_POWERON_SOFTLEVEL_COMPONENT;\n+ }\n+\n+ for ( info = (blog_info_t *)&_ld_bl_static_blogfile_code_start;\n+ (uint32_t)info < (uint32_t)&_ld_bl_static_blogfile_code_end; info++ ) {\n+ *(info->level) = BLOG_POWERON_SOFTLEVEL_FILE;\n+ }\n+\n+ for ( info = (blog_info_t *)&_ld_bl_static_blogpri_code_start;\n+ (uint32_t)info < (uint32_t)&_ld_bl_static_blogpri_code_end; info++ ) {\n+ *(info->level) = BLOG_POWERON_SOFTLEVEL_PRI;\n+ }\n+}\n+\n+/**\n+ * output log port interface\n+ *\n+ * @param log output of log\n+ * @param size log size\n+ */\n+void blog_port_output(const char *log, size_t size) {\n+ /* output to terminal */\n+ __blog_printf(\"%.*s\", size, log);\n+ //TODO output to flash\n+}\n+\n+/**\n+ * another copy string function\n+ *\n+ * @param cur_len current copied log length, max size is BLOG_LINE_BUF_SIZE\n+ * @param dst destination\n+ * @param src source\n+ *\n+ * @return copied length\n+ */\n+size_t blog_strcpy(size_t cur_len, char *dst, const char *src) {\n+ const char *src_old = src;\n+\n+ if ((!dst) || (!src)) {\n+ __blog_printf(\"assert.\\r\\n\");\n+ return 0;\n+ }\n+\n+ while (*src != 0) {\n+ /* make sure destination has enough space */\n+ if (cur_len++ < BLOG_LINE_BUF_SIZE) {\n+ *dst++ = *src++;\n+ } else {\n+ break;\n+ }\n+ }\n+ return src - src_old;\n+}\n+/**\n+ * dump the hex format data to log\n+ *\n+ * @param name name for hex object, it will show on log header\n+ * @param width hex number for every line, such as: 16, 32\n+ * @param buf hex buffer\n+ * @param size buffer size\n+ */\n+void blog_hexdump_out(const char *name, uint8_t width, const uint8_t *buf, uint16_t size)\n+{\n+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')\n+\n+ uint16_t i, j;\n+ uint16_t log_len = 0;\n+ char dump_string[8] = {0};\n+ int fmt_result;\n+\n+ /* lock output */\n+\n+ for (i = 0; i < size; i += width) {\n+ /* package header */\n+ fmt_result = snprintf(log_buf, BLOG_LINE_BUF_SIZE, \"[%s]: %04X-%04X: \", name, i, i + width - 1);\n+ /* calculate log length */\n+ if ((fmt_result > -1) && (fmt_result <= BLOG_LINE_BUF_SIZE)) {\n+ log_len = fmt_result;\n+ } else {\n+ log_len = BLOG_LINE_BUF_SIZE;\n+ }\n+ /* dump hex */\n+ for (j = 0; j < width; j++) {\n+ if (i + j < size) {\n+ snprintf(dump_string, sizeof(dump_string), \"%02X \", buf[i + j]);\n+ } else {\n+ strncpy(dump_string, \" \", sizeof(dump_string));\n+ }\n+ log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);\n+ if ((j + 1) % 8 == 0) {\n+ log_len += blog_strcpy(log_len, log_buf + log_len, \" \");\n+ }\n+ }\n+ log_len += blog_strcpy(log_len, log_buf + log_len, \" \");\n+ /* dump char for hex */\n+ for (j = 0; j < width; j++) {\n+ if (i + j < size) {\n+ snprintf(dump_string, sizeof(dump_string), \"%c\", __is_print(buf[i + j]) ? buf[i + j] : '.');\n+ log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);\n+ }\n+ }\n+ /* overflow check and reserve some space for newline sign */\n+ if (log_len + strlen(\"\\r\\n\") > BLOG_LINE_BUF_SIZE) {\n+ log_len = BLOG_LINE_BUF_SIZE - strlen(\"\\r\\n\");\n+ }\n+ /* package newline sign */\n+ log_len += blog_strcpy(log_len, log_buf + log_len, \"\\r\\n\");\n+\n+ /* do log output */\n+ blog_port_output(log_buf, log_len);\n+ }\n+\n+ /* unlock output */\n+}\n+\n+void blog_init(void)\n+{\n+ blog_set_poweron_softlevel();\n+}\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {\n+ { \"blogset\", \"blog pri set level\", cmd_blog_set_level},\n+ { \"blogdump\", \"blog info dump\", cmd_blog_info_dump},\n+#if BLOG_TEST\n+ { \"blogtest\", \"blog test\", cmd_blog_test},\n+#endif\n+};\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blog/blog.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blog/blog.h b/bsp/bl808/m0/libraries/stage/blog/blog.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..242578bdac125b0d0946f6654077b9d6c9904fa7\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blog/blog.h\n@@ -0,0 +1,268 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __BLOG_H__\n+#define __BLOG_H__\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+\n+// #include <FreeRTOS.h>\n+// #include <task.h>\n+\n+#include <utils_log.h>\n+\n+#include \"blog_type.h\"\n+#include \"blog_cfg.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+#if (CFG_COMPONENT_BLOG_ENABLE == 1)\n+#define ATTR_BLOG_CODE1(name) __attribute__((used, section(\".static_blogcomponent_code.\" #name)))\n+#define ATTR_BLOG_CODE2(name) __attribute__((used, section(\".static_blogfile_code.\" #name)))\n+#define ATTR_BLOG_CODE3(name) __attribute__((used, section(\".static_blogpri_code.\" #name)))\n+\n+/* for hard debug level */\n+const static uint32_t BLOG_HARD_DECLARE_DISABLE __attribute__((used)) = 0;\n+\n+/* component level */\n+#define _REFC_LEVEL(name) _fsymc_level_##name\n+#define REFC_LEVEL(name) _REFC_LEVEL(name)\n+#define _DEFC_LEVEL(name) blog_level_t REFC_LEVEL(name) __attribute__((weak))\n+#define DECLARE_C_LEVEL(name) _DEFC_LEVEL(name)\n+/* component info */\n+#define _REFC_INFO(name) _fsymc_info_##name\n+#define REFC_INFO(name) _REFC_INFO(name)\n+#define _DEFC_INFO(name) static const blog_info_t REFC_INFO(name) ATTR_BLOG_CODE1(name) = {\\\n+ (blog_level_t *)(&REFC_LEVEL(name)), (char *)(#name)}\n+#define DECLARE_C_INFO(name) _DEFC_INFO(name)\n+DECLARE_C_LEVEL(__COMPONENT_NAME_DEQUOTED__);\n+DECLARE_C_INFO(__COMPONENT_NAME_DEQUOTED__);\n+\n+/* file level */\n+#define _REFF_LEVEL(name) _fsymf_level_##name\n+#define REFF_LEVEL(name) _REFF_LEVEL(name)\n+#define _DEFF_LEVEL(name) blog_level_t REFF_LEVEL(name)\n+#define DECLARE_F_LEVEL(name) _DEFF_LEVEL(name)\n+/* file info */\n+#define _REFF_INFO(name) _fsymf_info_##name\n+#define REFF_INFO(name) _REFF_INFO(name)\n+#define _DEFF_INFO(name, named) const blog_info_t REFF_INFO(name) ATTR_BLOG_CODE2(name) = {\\\n+ (blog_level_t *)(&REFF_LEVEL(name)), (char *)(#named)}\n+#define DECLARE_F_INFO(name, named) _DEFF_INFO(name, named)\n+DECLARE_F_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__);\n+DECLARE_F_INFO(__COMPONENT_FILE_NAME_DEQUOTED__, __COMPONENT_FILE_NAMED__);\n+\n+/* pri level */\n+#define _REFP_LEVEL(name) _fsymp_level_##name\n+#define REFP_LEVEL(name) _REFP_LEVEL(name)\n+#define _DEFP_LEVEL(name) blog_level_t REFP_LEVEL(name)\n+#define DECLARE_P_LEVEL(name) _DEFP_LEVEL(name)\n+/* pri info */\n+#define _REFP_INFO(name) _fsymp_info_##name\n+#define REFP_INFO(name) _REFP_INFO(name)\n+#define _DEFP_INFO(name, prefix) const blog_info_t REFP_INFO(name) ATTR_BLOG_CODE3(name) = {\\\n+ (blog_level_t *)(&REFP_LEVEL(name)), (char *)(#prefix\".\"#name)}\n+#define DECLARE_P_INFO(name, prefix) _DEFP_INFO(name, prefix)\n+\n+#define BLOG_DECLARE(name) DECLARE_P_LEVEL(name);\\\n+ DECLARE_P_INFO(name, __COMPONENT_FILE_NAMED__);\n+\n+#define custom_cflog(lowlevel, N, M, ...) do {\\\n+ if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\\\n+ ) {\\\n+ __blog_printf(\"[%10u][%s: %s:%4d] \" M,\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, __FILENAME__, __LINE__,\\\n+ ##__VA_ARGS__);\\\n+ }\\\n+} while(0==1)\n+\n+#define custom_cflog_raw(lowlevel, N, M, ...) do {\\\n+ if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\\\n+ ) {\\\n+ __blog_printf(M,\\\n+ ##__VA_ARGS__);\\\n+ }\\\n+} while(0==1)\n+\n+#define custom_plog(priname, lowlevel, N, M, ...) do {\\\n+ if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFP_LEVEL(priname)) \\\n+ ) {\\\n+ __blog_printf(\"[%10u][%s: %s:%4d] \" M,\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, __FILENAME__, __LINE__,\\\n+ ##__VA_ARGS__);\\\n+ }\\\n+} while(0==1)\n+\n+#define custom_plog_raw(priname, lowlevel, N, M, ...) do {\\\n+ if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFP_LEVEL(priname)) \\\n+ ) {\\\n+ __blog_printf(M,\\\n+ ##__VA_ARGS__);\\\n+ }\\\n+} while(0==1)\n+\n+#define custom_hexdumplog(name, lowlevel, logo, buf, size) do {\\\n+ if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \\\n+ (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\\\n+ ) {\\\n+ __blog_printf(\"[%10u][%s: %s:%4d] %s:\\r\\n\",\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ logo, __FILENAME__, __LINE__,\\\n+ name);\\\n+ blog_hexdump_out(name, 16, buf, size);\\\n+ }\\\n+} while(0==1)\n+\n+#define BLOG_USE_COLOR (0)\n+\n+#if LOG_USE_COLOR\n+#define BLOG_PREFIX_INFO \"\\x1b[32mINFO \\x1b[0m\"\n+#define BLOG_PREFIX_WARN \"\\x1b[33mWARN \\x1b[0m\"\n+#define BLOG_PREFIX_ERROR \"\\x1b[31mERROR \\x1b[0m\"\n+#define BLOG_PREFIX_USER \"\\x1b[35mASSERT\\x1b[0m\"\n+#define BLOG_PREFIX_DUMP \"\\x1b[35mDUMP\\x1b[0m\"\n+#else\n+#define BLOG_PREFIX_INFO \"INFO\"\n+#define BLOG_PREFIX_WARN \"WARN\"\n+#define BLOG_PREFIX_ERROR \"ERROR\"\n+#define BLOG_PREFIX_USER \"ASSERT\"\n+#define BLOG_PREFIX_DUMP \"DUMP\"\n+#endif\n+\n+#define blog_debug(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog(BLOG_LEVEL_DEBUG,\"DEBUG \", M, ##__VA_ARGS__);} // NULL\n+#define blog_info(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);} // F_GREEN\n+#define blog_warn(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);} // F_YELLOW\n+#define blog_error(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);} // F_RED\n+#define blog_assert(assertion) if (0 == (assertion)) {\\\n+ __blog_printf(\"assert, %s:%d\\r\\n\", __FILENAME__, __LINE__);\\\n+ while(1);\\\n+ }\n+#define blog_debug_raw(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog_raw(BLOG_LEVEL_DEBUG,\"DEBUG \", M, ##__VA_ARGS__);} // NULL\n+#define blog_info_raw(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog_raw(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);} // F_GREEN\n+#define blog_warn_raw(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog_raw(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);} // F_YELLOW\n+#define blog_error_raw(M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_cflog_raw(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);} // F_RED\n+\n+#define blog_debug_user(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog(name,BLOG_LEVEL_DEBUG, \"DEBUG \", M, ##__VA_ARGS__);}\n+#define blog_info_user(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}\n+#define blog_warn_user(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}\n+#define blog_error_user(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}\n+#define blog_debug_user_raw(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog_raw(name,BLOG_LEVEL_DEBUG, \"DEBUG \", M, ##__VA_ARGS__);}\n+#define blog_info_user_raw(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog_raw(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}\n+#define blog_warn_user_raw(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog_raw(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN,M, ##__VA_ARGS__);}\n+#define blog_error_user_raw(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog_raw(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}\n+#define blog_assert_user(name, M, ...) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_plog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_USER, M, ##__VA_ARGS__);}\n+\n+#define blog_debug_hexdump(name, buf, size) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_hexdumplog(name,BLOG_LEVEL_DEBUG, \"DEBUG \", buf, size);}\n+#define blog_info_hexdump(name, buf, size) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_hexdumplog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, buf, size);}\n+#define blog_warn_hexdump(name, buf, size) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_hexdumplog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, buf, size);}\n+#define blog_error_hexdump(name, buf, size) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_hexdumplog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, buf, size);}\n+#define blog_assert_hexdump(name, buf, size) if (0 == BLOG_HARD_DECLARE_DISABLE) {\\\n+ custom_hexdumplog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_DUMP, buf, size);}\n+#define blog_print __blog_printf\n+#define blog_buf log_buf//unsupport\n+\n+#else\n+\n+//#define BLOG_HARD_DECLARE_DISABLE 1\n+#define BLOG_DECLARE(name)\n+\n+#define blog_debug(M, ...)\n+#define blog_info(M, ...)\n+#define blog_warn(M, ...)\n+#define blog_error(M, ...)\n+#define blog_debug_raw(M, ...)\n+#define blog_info_raw(M, ...)\n+#define blog_warn_raw(M, ...)\n+#define blog_error_raw(M, ...)\n+#define blog_assert(M, ...)\n+\n+#define blog_debug_user(name, M, ...)\n+#define blog_info_user(name, M, ...)\n+#define blog_warn_user(name, M, ...)\n+#define blog_error_user(name, M, ...)\n+#define blog_debug_user_raw(name, M, ...)\n+#define blog_info_user_raw(name, M, ...)\n+#define blog_warn_user_raw(name, M, ...)\n+#define blog_error_user_raw(name, M, ...)\n+#define blog_assert_user(name, M, ...)\n+\n+#define blog_debug_hexdump(name, buf, size)\n+#define blog_info_hexdump(name, buf, size)\n+#define blog_warn_hexdump(name, buf, size)\n+#define blog_error_hexdump(name, buf, size)\n+#define blog_assert_hexdump(name, buf, size)\n+\n+#define blog_print(...)\n+#define blog_buf(...)\n+\n+#endif\n+\n+void blog_init(void);\n+\n+void blog_hexdump_out(const char *name, uint8_t width, uint8_t *buf, uint16_t size);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blog/blog_cfg.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h b/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..41ad4f0dc5e727882effaa063729c074cd883aef\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h\n@@ -0,0 +1,44 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __BLOG_CFG_H__\n+#define __BLOG_CFG_H__\n+\n+#define BLOG_POWERON_SOFTLEVEL_COMPONENT (BLOG_LEVEL_INFO)\n+#define BLOG_POWERON_SOFTLEVEL_FILE (BLOG_LEVEL_INFO)\n+#define BLOG_POWERON_SOFTLEVEL_PRI (BLOG_LEVEL_INFO)\n+#define BLOG_NAMELEN_MAX (128)\n+#define BLOG_DUMP_DEDUPLICATE (1)\n+#define BLOG_TEST (0)\n+\n+#define BLOG_LINE_BUF_SIZE (256)\n+\n+#define __blog_printf bl_printk\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/stage/blog/blog_type.h\ndiff --git a/bsp/bl808/m0/libraries/stage/blog/blog_type.h b/bsp/bl808/m0/libraries/stage/blog/blog_type.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..538ad60ff6992166d2c66da423c3f2a403c39e72\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/stage/blog/blog_type.h\n@@ -0,0 +1,48 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __BLOG_TYPE_H__\n+#define __BLOG_TYPE_H__\n+\n+typedef enum _blog_leve {\n+ BLOG_LEVEL_ALL = 0,\n+ BLOG_LEVEL_DEBUG,\n+ BLOG_LEVEL_INFO,\n+ BLOG_LEVEL_WARN,\n+ BLOG_LEVEL_ERROR,\n+ BLOG_LEVEL_ASSERT,\n+ BLOG_LEVEL_NEVER,\n+} blog_level_t;\n+\n+typedef struct _blog_info {\n+ blog_level_t *level; //default 0\n+ char *name;\n+} blog_info_t;\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_base64.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_base64.h b/bsp/bl808/m0/libraries/utils/include/utils_base64.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7c7db40874a1283e5334b15ebbb63a77820ab59a\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_base64.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+\n+\n+#ifndef _IOTX_COMMON_BASE64_H_\n+#define _IOTX_COMMON_BASE64_H_\n+\n+#include <stdint.h>\n+\n+#define UTILS_BASE64_TEST\n+\n+typedef enum iotx_err\n+{\n+ FAIL_RETURN = 0,\n+ SUCCESS_RETURN\n+}iotx_err_t;\n+\n+iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,\n+ uint8_t *encodedData, uint32_t *outputLength);\n+iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,\n+ uint8_t *decodedData, uint32_t *outputLength);\n+\n+void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque);\n+int base64_cli_init(void);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h b/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..20a24439fd7c86267f30bd32b0bf2279ffcd3a57\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h\n@@ -0,0 +1,45 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+\n+struct utils_bitmap_ctx {\n+ int ssn;\n+ int ssn_duration;\n+ union {\n+ uint8_t bytes[8];\n+ uint64_t map64;\n+ } bitmap;\n+};\n+\n+int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max);\n+int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos);\n+uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx);\n+int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx);\n+int utils_bitmap_window_cli_init(void);\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_crc.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_crc.h b/bsp/bl808/m0/libraries/utils/include/utils_crc.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..10f62d4c17cda9e3e9f782d4520f45639873ad04\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_crc.h\n@@ -0,0 +1,47 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_CRC_H__\n+#define __UTILS_CRC_H__\n+#include <stdint.h>\n+\n+uint16_t utils_crc16(void *dataIn, uint32_t len);\n+uint32_t utils_crc32(void *dataIn, uint32_t len);\n+uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len);\n+\n+struct crc32_stream_ctx {\n+ uint32_t crc;\n+};\n+\n+void utils_crc32_stream_init(struct crc32_stream_ctx *ctx);\n+void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data);\n+void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len);\n+uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_debug.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_debug.h b/bsp/bl808/m0/libraries/utils/include/utils_debug.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8f5dcecc75f46ea81137629ea4cd0d88beddcfa1\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_debug.h\n@@ -0,0 +1,41 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_DEBUG_H__\n+#define __UTILS_DEBUG_H__\n+#include <stdio.h>\n+#define BL_ASSERT_ERROR(cond) do {\\\n+ if (!(cond)) { \\\n+ printf(\"[ASSERT] [ERR] %s:%d\\r\\n\", __FILENAME__, __LINE__); \\\n+ while (1) { \\\n+ } \\\n+ } \\\n+} while (0)\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_dns.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_dns.h b/bsp/bl808/m0/libraries/utils/include/utils_dns.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..19eeb2bc021b9ca8fd934bd877098115fab4a0f6\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_dns.h\n@@ -0,0 +1,34 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_DNS_H__\n+#define __UTILS_DNS_H__\n+#include <stdint.h>\n+int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_fec.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_fec.h b/bsp/bl808/m0/libraries/utils/include/utils_fec.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..030ed901bbeb957e3badf4b56e77396df1227101\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_fec.h\n@@ -0,0 +1,61 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __UTILS_FEC_H__\n+#define __UTILS_FEC_H__\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define FEC_MSG_LENGTH\t128\n+#define FEC_ECC_LENGTH\t126\n+\n+#define bl_assert(expr)\n+\n+typedef struct\n+{\n+\tint dummy[1120];\n+} fec_t;\n+\n+int reedsolomon_getmemsize(void);\n+void reedsolomon_init(void *context);\n+void reedsolomon_encode(void *context, void* src, void* dst);\n+char reedsolomon_decode(void *context, void* src, void* dst);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_getopt.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_getopt.h b/bsp/bl808/m0/libraries/utils/include/utils_getopt.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a2dc673bf3b85e91c40304e0b3937a4bd5a191c2\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_getopt.h\n@@ -0,0 +1,110 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __GETOPT_H__\n+#define __GETOPT_H__\n+/**\n+ * @brief Parameters needed to parse the command line\n+ *\n+ */\n+typedef struct getopt_env {\n+ char *optarg; /*!< if the option accepts parameters, then optarg point to the option parameter*/\n+ int optind; /*!< current index of argv*/\n+ int opterr; /*!< non-zero enable error message output, while 0,no error message output*/\n+ int optopt; /*!< contain unrecognized option character*/\n+ int __optpos; \n+} getopt_env_t;\n+\n+/**\n+ * @brief Initialize struct getopt_env\n+ *\n+ * @param env pointer to struct getopt_env\n+ * @param opterr set error message output method\n+ *\n+ * @return \n+ * - 0: success\n+ * - -1: fail\n+ */\n+int utils_getopt_init(getopt_env_t *env, int opterr);\n+\n+/**\n+ * @brief Parses the command-line arguments\n+ *\n+ * @param env pointer to struct getopt_env\n+ * @param argc the argument count \n+ * @param argv the argument array\n+ *\n+ * @return \n+ * - option character : an option was successfully found\n+ * - -1 : all command-line options have been parsed \n+ * - '?' : option character was not in optstring\n+ * - ':' or '?' : If utils_getopt() encounters an option with a missing argument, then the return value depends on the first character in optstring: if it is ':', then ':' is returned; otherwise '?' is returned\n+ *\n+ * @note Example\n+ * @code\n+ *\n+ * #include <utils_getopt.h>\n+ * #include <stdio.h>\n+ *\n+ * void cmd(char *buf, int len, int argc, char **argv)\n+ * {\n+ * int opt;\n+ getopt_env_t getopt_env;\n+ utils_getopt_init(&getopt_env, 0);\n+ * //put ':' in the starting of the string so that program can distinguish between '?' and ':'\n+ * while ((opt = utils_getopt(&getopt_env, argc, argv, \":if:lr\")) != -1) {\n+ * switch(opt)\n+ * {\n+ * case 'i':\n+ * case 'l':\n+ * case 'r':\n+ * printf(\"option: %c\\r\\n\", opt);\n+ * break;\n+ * case 'f':\n+ * printf(\"filename: %s\\r\\n\", getopt_env.optarg);\n+ * break;\n+ * case ':':\n+ printf(\"%s: %c requires an argument\\r\\n\", *argv, getopt_env.optopt);\n+ * break;\n+ * case '?':\n+ * printf(\"unknow option: %c\\r\\n\", getopt_env.optopt);\n+ * break;\n+ * }\n+ * }\n+ * //optind is for the extra arguments which are not parsed\n+ * for(; getopt_env.optind < argc; getopt_env.optind++){\n+ * printf(\"extra arguments: %s\\r\\n\", argv[getopt_env.optind]);\n+ * }\n+ *\n+ * }\n+ * @endcode\n+ */\n+int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring);\n+\n+#endif /* __GETOPT_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_hex.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_hex.h b/bsp/bl808/m0/libraries/utils/include/utils_hex.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6361fdad07e1254650393c339de770bb90c0e9aa\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_hex.h\n@@ -0,0 +1,34 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_HEX_H__\n+#define __UTILS_HEX_H__\n+char *utils_bin2hex(char *dst, const void *src, size_t count);\n+size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_hexdump.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h b/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4cbde0c7112bbbda938b306d11491892eab6a020\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h\n@@ -0,0 +1,33 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_HEXDUMP_H__\n+#define __UTILS_HEXDUMP_H__\n+void utils_hexdump(void *mem, unsigned int len);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_hmac.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7949a190c641dd0baee8aa8160b5d7399b88fd0c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_hmac.h\n@@ -0,0 +1,59 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+\n+\n+#ifndef _IOTX_COMMON_HMAC_H_\n+#define _IOTX_COMMON_HMAC_H_\n+\n+#include <string.h>\n+\n+#define KEY_IOPAD_SIZE (64)\n+#define MD5_DIGEST_SIZE (16)\n+#define SHA1_DIGEST_SIZE (20)\n+#define SHA256_DIGEST_SIZE (32)\n+\n+#ifdef UTILS_MD5\n+void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len);\n+#endif\n+\n+#ifdef UTILS_SHA1\n+void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len);\n+\n+void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len);\n+#endif\n+\n+#ifdef UTILS_SHA256\n+void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len);\n+#endif\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e6f9de7a77a65f935492bcc6390de712b73e785f\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h\n@@ -0,0 +1,41 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_HMAC_SHA1_FASH_H__\n+#define __UTILS_HMAC_SHA1_FASH_H__\n+\n+void utils_hmac_sha1_fast(unsigned char ** ppText,\n+ int * pTextLen,\n+ int textNum,\n+ unsigned char *key,\n+ int key_len,\n+ unsigned char *output,\n+ int outputLen);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_list.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_list.h b/bsp/bl808/m0/libraries/utils/include/utils_list.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e33bbe914a364091e173a5780c57da92d15d9743\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_list.h\n@@ -0,0 +1,621 @@\n+\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+#ifndef _UTILS_LIST_H_\n+#define _UTILS_LIST_H_\n+\n+#include <stddef.h>\n+\n+struct utils_list_hdr\n+{\n+ struct utils_list_hdr *next;\n+};\n+\n+struct utils_list\n+{\n+ /// pointer to first element of the list\n+ struct utils_list_hdr *first;\n+ /// pointer to the last element\n+ struct utils_list_hdr *last;\n+};\n+\n+\n+/*\n+ * FUNCTION DECLARATIONS\n+ ****************************************************************************************\n+ */\n+/**\n+ ****************************************************************************************\n+ * @brief Initialize a list to defaults values.\n+ * @param[in] list Pointer to the list structure.\n+ ****************************************************************************************\n+ */\n+void utils_list_init(struct utils_list *list);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Initialize a pool to default values, and initialize the relative free list.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ * @param[in] pool Pointer to the pool to be initialized\n+ * @param[in] elmt_size Size of one element of the pool\n+ * @param[in] elmt_cnt Nb of elements available in the pool\n+ * @param[in] default_value Pointer to the default value of each element (may be NULL)\n+ ****************************************************************************************\n+ */\n+void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Add an element as last on the list.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ * @param[in] list_hdr Pointer to the header to add at the end of the list\n+ ****************************************************************************************\n+ */\n+void utils_list_push_back(struct utils_list *list,\n+ struct utils_list_hdr *list_hdr);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Add an element as first on the list.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ * @param[in] list_hdr Pointer to the header to add at the beginning of the list\n+ ****************************************************************************************\n+ */\n+void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr);\n+/**\n+ ****************************************************************************************\n+ * @brief Extract the first element of the list.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ *\n+ * @return The pointer to the element extracted, and NULL if the list is empty.\n+ ****************************************************************************************\n+ */\n+struct utils_list_hdr *utils_list_pop_front(struct utils_list *list);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Search for a given element in the list, and extract it if found.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ * @param[in] list_hdr Pointer to the searched element\n+ *\n+ * @return CO_EMPTY if the list is empty, CO_FAIL if the element not found in the list,\n+ * CO_OK else.\n+ ****************************************************************************************\n+ */\n+void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Searched a given element in the list.\n+ *\n+ * @param[in] list Pointer to the list structure\n+ * @param[in] list_hdr Pointer to the searched element\n+ *\n+ * @return true if the element is found in the list, false otherwise\n+ ****************************************************************************************\n+ */\n+int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Insert an element in a sorted list.\n+ *\n+ * This primitive use a comparison function from the parameter list to select where the\n+ * element must be inserted.\n+ *\n+ * @param[in] list Pointer to the list.\n+ * @param[in] element Pointer to the element to insert.\n+ * @param[in] cmp Comparison function (return true if first element has to be inserted\n+ * before the second one).\n+ *\n+ * @return Pointer to the element found and removed (NULL otherwise).\n+ ****************************************************************************************\n+ */\n+void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,\n+ int (*cmp)(struct utils_list_hdr const *elementA,\n+ struct utils_list_hdr const *elementB));\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Insert an element in a sorted list after the provided element.\n+ *\n+ * This primitive use a comparison function from the parameter list to select where the\n+ * element must be inserted.\n+ *\n+ * @param[in] list Pointer to the list.\n+ * @param[in] prev_element Pointer to the element to find in the list\n+ * @param[in] element Pointer to the element to insert.\n+ *\n+ * If prev_element is not found, the provided element is not inserted\n+ ****************************************************************************************\n+ */\n+void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Insert an element in a sorted list before the provided element.\n+ *\n+ * This primitive use a comparison function from the parameter list to select where the\n+ * element must be inserted.\n+ *\n+ * @param[in] list Pointer to the list.\n+ * @param[in] next_element Pointer to the element to find in the list\n+ * @param[in] element Pointer to the element to insert.\n+ *\n+ * If next_element is not found, the provided element is not inserted\n+ ****************************************************************************************\n+ */\n+void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Concatenate two lists.\n+ * The resulting list is the list passed as the first parameter. The second list is\n+ * emptied.\n+ *\n+ * @param[in] list1 First list (will get the result of the concatenation)\n+ * @param[in] list2 Second list (will be emptied after the concatenation)\n+ ****************************************************************************************\n+ */\n+void utils_list_concat(struct utils_list *list1, struct utils_list *list2);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Remove the element in the list after the provided element.\n+ *\n+ * This primitive removes an element in the list. It is assume that element is part of\n+ * the list.\n+ *\n+ * @param[in] list Pointer to the list.\n+ * @param[in] prev_element Pointer to the previous element.\n+ * NULL if @p element is the first element in the list\n+ * @param[in] element Pointer to the element to remove.\n+ *\n+ ****************************************************************************************\n+ */\n+void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element);\n+/**\n+ ****************************************************************************************\n+ * @brief Test if the list is empty.\n+ *\n+ * @param[in] list Pointer to the list structure.\n+ *\n+ * @return true if the list is empty, false else otherwise.\n+ ****************************************************************************************\n+ */\n+static inline int utils_list_is_empty(const struct utils_list *const list)\n+{\n+ return (NULL == list->first);\n+}\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Return the number of element of the list.\n+ *\n+ * @param[in] list Pointer to the list structure.\n+ *\n+ * @return The number of elements in the list.\n+ ****************************************************************************************\n+ */\n+unsigned int utils_list_cnt(const struct utils_list *const list);\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Pick the first element from the list without removing it.\n+ *\n+ * @param[in] list Pointer to the list structure.\n+ *\n+ * @return First element address. Returns NULL pointer if the list is empty.\n+ ****************************************************************************************\n+ */\n+static inline struct utils_list_hdr *utils_list_pick(const struct utils_list *const list)\n+{\n+ return list->first;\n+}\n+\n+static inline struct utils_list_hdr *utils_list_pick_last(const struct utils_list *const list)\n+{\n+ return list->last;\n+}\n+\n+static inline struct utils_list_hdr *utils_list_next(const struct utils_list_hdr *const list_hdr)\n+{\n+ return list_hdr->next;\n+}\n+\n+\n+/*\n+ * Get offset of a member variable.\n+ *\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the variable within the struct.\n+ */\n+#define utils_offsetof(type, member) ((size_t)&(((type *)0)->member))\n+\n+/*\n+ * Get the struct for this entry.\n+ *\n+ * @param[in] ptr the list head to take the element from.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the variable within the struct.\n+ */\n+#define utils_container_of(ptr, type, member) \\\n+ ((type *) ((char *) (ptr) - utils_offsetof(type, member)))\n+\n+/* for double link list */\n+typedef struct utils_dlist_s {\n+ struct utils_dlist_s *prev;\n+ struct utils_dlist_s *next;\n+} utils_dlist_t;\n+\n+static inline void __utils_dlist_add(utils_dlist_t *node, utils_dlist_t *prev, utils_dlist_t *next)\n+{\n+ node->next = next;\n+ node->prev = prev;\n+\n+ prev->next = node;\n+ next->prev = node;\n+}\n+\n+/*\n+ * Get the struct for this entry.\n+ *\n+ * @param[in] addr the list head to take the element from.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_dlist_t within the struct.\n+ */\n+#define utils_dlist_entry(addr, type, member) \\\n+ ((type *)((long)addr - utils_offsetof(type, member)))\n+\n+\n+static inline void utils_dlist_add(utils_dlist_t *node, utils_dlist_t *queue)\n+{\n+ __utils_dlist_add(node, queue, queue->next);\n+}\n+\n+static inline void utils_dlist_add_tail(utils_dlist_t *node, utils_dlist_t *queue)\n+{\n+ __utils_dlist_add(node, queue->prev, queue);\n+}\n+\n+static inline void utils_dlist_del(utils_dlist_t *node)\n+{\n+ utils_dlist_t *prev = node->prev;\n+ utils_dlist_t *next = node->next;\n+\n+ prev->next = next;\n+ next->prev = prev;\n+}\n+\n+static inline void utils_dlist_init(utils_dlist_t *node)\n+{\n+ node->next = node->prev = node;\n+}\n+\n+static inline void INIT_UTILS_DLIST_HEAD(utils_dlist_t *list)\n+{\n+ list->next = list;\n+ list->prev = list;\n+}\n+\n+static inline int utils_dlist_empty(const utils_dlist_t *head)\n+{\n+ return head->next == head;\n+}\n+\n+/*\n+ * Initialise the list.\n+ *\n+ * @param[in] list the list to be inited.\n+ */\n+#define UTILS_DLIST_INIT(list) {&(list), &(list)}\n+\n+/*\n+ * Get the first element from a list\n+ *\n+ * @param[in] ptr the list head to take the element from.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_dlist_t within the struct.\n+ */\n+#define utils_dlist_first_entry(ptr, type, member) \\\n+ utils_dlist_entry((ptr)->next, type, member)\n+\n+/*\n+ * Iterate over a list.\n+ *\n+ * @param[in] pos the &struct utils_dlist_t to use as a loop cursor.\n+ * @param[in] head he head for your list.\n+ */\n+#define utils_dlist_for_each(pos, head) \\\n+ for (pos = (head)->next; pos != (head); pos = pos->next)\n+\n+/*\n+ * Iterate over a list safe against removal of list entry.\n+ *\n+ * @param[in] pos the &struct utils_dlist_t to use as a loop cursor.\n+ * @param[in] n another &struct utils_dlist_t to use as temporary storage.\n+ * @param[in] head he head for your list.\n+ */\n+#define utils_dlist_for_each_safe(pos, n, head) \\\n+ for (pos = (head)->next, n = pos->next; pos != (head); \\\n+ pos = n, n = pos->next)\n+\n+/*\n+ * Iterate over list of given type.\n+ *\n+ * @param[in] queue he head for your list.\n+ * @param[in] node the &struct utils_dlist_t to use as a loop cursor.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_dlist_t within the struct.\n+ */\n+#define utils_dlist_for_each_entry(queue, node, type, member) \\\n+ for (node = utils_container_of((queue)->next, type, member); \\\n+ &node->member != (queue); \\\n+ node = utils_container_of(node->member.next, type, member))\n+\n+/*\n+ * Iterate over list of given type safe against removal of list entry.\n+ *\n+ * @param[in] queue the head for your list.\n+ * @param[in] n the type * to use as a temp.\n+ * @param[in] node the type * to use as a loop cursor.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_dlist_t within the struct.\n+ */\n+#define utils_dlist_for_each_entry_safe(queue, n, node, type, member) \\\n+ for (node = utils_container_of((queue)->next, type, member), \\\n+ n = (queue)->next ? (queue)->next->next : NULL; \\\n+ &node->member != (queue); \\\n+ node = utils_container_of(n, type, member), n = n ? n->next : NULL)\n+\n+/*\n+ * Get the struct for this entry.\n+ * @param[in] ptr the list head to take the element from.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the variable within the struct.\n+ */\n+#define utils_list_entry(ptr, type, member) \\\n+ utils_container_of(ptr, type, member)\n+\n+\n+/*\n+ * Iterate backwards over list of given type.\n+ *\n+ * @param[in] pos the type * to use as a loop cursor.\n+ * @param[in] head he head for your list.\n+ * @param[in] member the name of the utils_dlist_t within the struct.\n+ * @param[in] type the type of the struct this is embedded in.\n+ */\n+#define utils_dlist_for_each_entry_reverse(pos, head, member, type) \\\n+ for (pos = utils_list_entry((head)->prev, type, member); \\\n+ &pos->member != (head); \\\n+ pos = utils_list_entry(pos->member.prev, type, member))\n+\n+\n+/*\n+ * Get the list length.\n+ *\n+ * @param[in] queue the head for your list.\n+ */\n+static inline int utils_dlist_entry_number(utils_dlist_t *queue)\n+{\n+\tint num;\n+\tutils_dlist_t *cur = queue; \n+\tfor (num=0;cur->next != queue;cur=cur->next, num++)\n+\t\t;\n+\t\n+\treturn num; \n+}\n+\n+\n+\n+/*\n+ * Initialise the list.\n+ *\n+ * @param[in] name the list to be initialized.\n+ */\n+#define UTILS_DLIST_HEAD_INIT(name) { &(name), &(name) }\n+\n+/*\n+ * Initialise the list.\n+ *\n+ * @param[in] name the list to be initialized.\n+ */\n+#define UTILS_DLIST_HEAD(name) \\\n+ utils_dlist_t name = UTILS_DLIST_HEAD_INIT(name)\n+\n+/* for single link list */\n+typedef struct utils_slist_s {\n+ struct utils_slist_s *next;\n+} utils_slist_t;\n+\n+static inline void utils_slist_add(utils_slist_t *node, utils_slist_t *head)\n+{\n+ node->next = head->next;\n+ head->next = node;\n+}\n+\n+static inline void utils_slist_add_tail(utils_slist_t *node, utils_slist_t *head)\n+{\n+ while (head->next) {\n+ head = head->next;\n+ }\n+\n+ utils_slist_add(node, head);\n+}\n+\n+static inline void utils_slist_append(utils_slist_t *l, utils_slist_t *n)\n+{\n+ utils_slist_t *node;\n+\n+ node = l;\n+ while (node->next) node = node->next;\n+\n+ /* append the node to the tail */\n+ node->next = n;\n+ n->next = NULL;\n+}\n+\n+static inline void utils_slist_del(utils_slist_t *node, utils_slist_t *head)\n+{\n+ while (head->next) {\n+ if (head->next == node) {\n+ head->next = node->next;\n+ break;\n+ }\n+\n+ head = head->next;\n+ }\n+}\n+\n+static inline int utils_slist_empty(const utils_slist_t *head)\n+{\n+ return !head->next;\n+}\n+\n+static inline void utils_slist_init(utils_slist_t *head)\n+{\n+ head->next = 0;\n+}\n+\n+static inline utils_slist_t* utils_slist_first(utils_slist_t *l)\n+{\n+ return l->next;\n+}\n+\n+static inline utils_slist_t* utils_slist_tail(utils_slist_t *l)\n+{\n+ while (l->next) l = l->next;\n+\n+ return l;\n+}\n+\n+static inline utils_slist_t* utils_slist_next(utils_slist_t *l)\n+{\n+ return l->next;\n+}\n+\n+/*\n+* Iterate over list of given type.\n+*\n+* @param[in] queue he head for your list.\n+* @param[in] node the type * to use as a loop cursor.\n+* @param[in] type the type of the struct this is embedded in.\n+* @param[in] member the name of the utils_slist_t within the struct.\n+*/\n+#define utils_slist_for_each_entry(queue, node, type, member) \\\n+ for (node = utils_container_of((queue)->next, type, member); \\\n+ &node->member; \\\n+ node = utils_container_of(node->member.next, type, member))\n+\n+/*\n+ * Iterate over list of given type safe against removal of list entry.\n+ *\n+ * @param[in] queue the head for your list.\n+ * @param[in] tmp the type * to use as a temp.\n+ * @param[in] node the type * to use as a loop cursor.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_slist_t within the struct.\n+ */\n+#define utils_slist_for_each_entry_safe(queue, tmp, node, type, member) \\\n+ for (node = utils_container_of((queue)->next, type, member), \\\n+ tmp = (queue)->next ? (queue)->next->next : NULL; \\\n+ &node->member; \\\n+ node = utils_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)\n+\n+/*\n+ * Initialise the list.\n+ *\n+ * @param[in] name the list to be initialized.\n+ */\n+#define UTILS_SLIST_HEAD_INIT(name) {0}\n+\n+/*\n+ * Initialise the list.\n+ *\n+ * @param[in] name the list to be initialized.\n+ */\n+#define UTILS_SLIST_HEAD(name) \\\n+ utils_slist_t name = UTILS_SLIST_HEAD_INIT(name)\n+\n+/*\n+ * Get the struct for this entry.\n+ * @param[in] addr the list head to take the element from.\n+ * @param[in] type the type of the struct this is embedded in.\n+ * @param[in] member the name of the utils_slist_t within the struct.\n+ */\n+#define utils_slist_entry(addr, type, member) ( \\\n+ addr ? (type *)((long)addr - utils_offsetof(type, member)) : (type *)addr \\\n+)\n+\n+/*\n+* Get the first element from a list.\n+*\n+* @param[in] ptr the list head to take the element from.\n+* @param[in] type the type of the struct this is embedded in.\n+* @param[in] member the name of the utils_slist_t within the struct.\n+*/\n+#define utils_slist_first_entry(ptr, type, member) \\\n+ utils_slist_entry(utils_slist_next(ptr), type, member)\n+\n+\n+/*\n+* Get the last element from a list.\n+*\n+* @param[in] ptr the list head to take the element from.\n+* @param[in] type the type of the struct this is embedded in.\n+* @param[in] member the name of the utils_slist_t within the struct.\n+*/\n+#define utils_slist_tail_entry(ptr, type, member) \\\n+ utils_slist_entry(utils_slist_tail(ptr), type, member)\n+\n+\n+/*\n+ * Get the list length.\n+ *\n+ * @param[in] queue the head for your list.\n+ */\n+static inline int utils_slist_entry_number(utils_slist_t *queue)\n+{\n+\tint num;\n+ utils_slist_t *cur = queue; \n+ for (num=0;cur->next;cur=cur->next, num++)\n+\t\t;\n+\t\n+ return num; \n+}\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_log.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_log.h b/bsp/bl808/m0/libraries/utils/include/utils_log.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..bbf73a7c49d5a4dd71859ba31aeac20e1168df10\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_log.h\n@@ -0,0 +1,168 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __UTILS_LOG_H__\n+#define __UTILS_LOG_H__\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+\n+// #include <FreeRTOS.h>\n+// #include <task.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define __utils_printf bl_printk\n+\n+/* cc */\n+/* define compiler specific symbols */\n+#if defined (__ICCARM__)\n+#define BL_PACK_STRUCT_BEGIN\n+#define BL_PACK_STRUCT_STRUCT\n+#define BL_PACK_STRUCT_END\n+#define BL_PACK_STRUCT_FIELD(x) x\n+#define BL_PACK_STRUCT_USE_INCLUDES\n+#elif defined (__CC_ARM)\n+#define BL_PACK_STRUCT_BEGIN __packed\n+#define BL_PACK_STRUCT_STRUCT\n+#define BL_PACK_STRUCT_END\n+#define BL_PACK_STRUCT_FIELD(x) x\n+#elif defined (__GNUC__)\n+#define BL_PACK_STRUCT_BEGIN //#pragma pack(push, 1)\n+#define BL_PACK_STRUCT_STRUCT //__attribute__ ((__packed__))\n+#define BL_PACK_STRUCT_END //#pragma pack(pop)\n+#define BL_PACK_STRUCT_FIELD(x)\n+#elif defined (__TASKING__)\n+#define BL_PACK_STRUCT_BEGIN\n+#define BL_PACK_STRUCT_STRUCT\n+#define BL_PACK_STRUCT_END\n+#define BL_PACK_STRUCT_FIELD(x) x\n+#endif\n+\n+#if 0\n+#define BL_ASSERT(condition) \\\n+ do { \\\n+ if (!(condition)) { \\\n+ log_assert(\"ASSERT: %s:%d\\r\\n\", __FILENAME__, __LINE__); \\\n+ while (1) { \\\n+ /*deap loop now*/ \\\n+ } \\\n+ } \\\n+ } while (0)\n+#endif\n+#define BL_ASSERT(condition)\n+\n+#define LOG_USE_COLOR (0)\n+typedef enum LOG_BUF_OUT_DATA_TYPE {\n+ LOG_BUF_OUT_DATA_TYPE_HEX,\n+ LOG_BUF_OUT_DATA_TYPE_INT8,\n+ LOG_BUF_OUT_DATA_TYPE_UNT8,\n+} LOG_BUF_OUT_DATA_TYPE_T;\n+//#define LOG_USE_LINE_FEED\n+#define LOG_LOCK_LOCK /* reserved, must diffrent with buf lock */\n+#define LOG_LOCK_UNLOCK /* reserved, must diffrent with buf lock */\n+//#define SHORT_FILE __FILENAME__\n+#define SHORT_FILE __FILE__\n+\n+#ifdef LOG_USE_LINE_FEED\n+#define custom_log(N, M, ...) do { LOG_LOCK_LOCK;\\\n+ __utils_printf(\"[%10u][%s: %s:%4d] \" M \"\\r\\n\",\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, SHORT_FILE, __LINE__,\\\n+ ##__VA_ARGS__);\\\n+ LOG_LOCK_UNLOCK;\\\n+ } while(0==1)\n+#define custom_buf_pri(file, line, N, M, ...) do { LOG_LOCK_LOCK;\\\n+ __utils_printf(\"[%10u][%s: %s:%4d] \" M, \"\\r\\n\",\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, file, line,\\\n+ ##__VA_ARGS__);\\\n+ LOG_LOCK_UNLOCK;\\\n+ } while(0==1)\n+#else\n+#define custom_log(N, M, ...) do { LOG_LOCK_LOCK;\\\n+ __utils_printf(\"[%10u][%s: %s:%4d] \" M,\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, SHORT_FILE, __LINE__,\\\n+ ##__VA_ARGS__);\\\n+ LOG_LOCK_UNLOCK;\\\n+ } while(0==1)\n+#define custom_buf_pri(file, line, N, M, ...) do { LOG_LOCK_LOCK;\\\n+ __utils_printf(\"[%10u][%s: %s:%4d] \" M,\\\n+ (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\\\n+ N, file, line,\\\n+ ##__VA_ARGS__);\\\n+ LOG_LOCK_UNLOCK;\\\n+ } while(0==1)\n+#endif\n+\n+#if LOG_USE_COLOR\n+#define log_buf_pri(file, line, M, ...) custom_buf_pri(file, line, \"\\x1b[36mBUF\\x1b[0m\", M, ##__VA_ARGS__)\n+#else\n+#define log_buf_pri(file, line, M, ...) custom_buf_pri(file, line, \"BUF\", M, ##__VA_ARGS__)\n+#endif\n+\n+#if LOG_USE_COLOR\n+#define log_trace(M, ...) custom_log(\"\\x1b[94mTRACE \\x1b[0m\", M, ##__VA_ARGS__)\n+#define log_debug(M, ...) custom_log(\"\\x1b[36mDEBUG \\x1b[0m\", M, ##__VA_ARGS__)\n+#define log_info(M, ...) custom_log(\"\\x1b[32mINFO \\x1b[0m\", M, ##__VA_ARGS__)\n+#define log_warn(M, ...) custom_log(\"\\x1b[33mWARN \\x1b[0m\", M, ##__VA_ARGS__)\n+#define log_error(M, ...) custom_log(\"\\x1b[31mERROR \\x1b[0m\", M, ##__VA_ARGS__)\n+#define log_assert(M, ...) custom_log(\"\\x1b[35mASSERT\\x1b[0m\", M, ##__VA_ARGS__)\n+#else\n+#define log_trace(M, ...) custom_log(\"TRACE \", M, ##__VA_ARGS__)\n+#define log_debug(M, ...) custom_log(\"DEBUG \", M, ##__VA_ARGS__)\n+#define log_info(M, ...) custom_log(\"INFO \", M, ##__VA_ARGS__)\n+#define log_warn(M, ...) custom_log(\"WARN \", M, ##__VA_ARGS__)\n+#define log_error(M, ...) custom_log(\"ERROR \", M, ##__VA_ARGS__)\n+#define log_assert(M, ...) custom_log(\"ASSERT\", M, ##__VA_ARGS__)\n+#endif\n+#define log_buf(pbuf, len) log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_HEX)\n+#define log_buf_int8(pbuf, len) log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_INT8)\n+#define log_buf_unt8(pbuf, len) log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_UNT8)\n+#define log_compile_time() do {\\\n+ log_info(\"compile date = %s\\r\\n\", __DATE__);\\\n+ log_info(\"compile time = %s\\r\\n\", __TIME__);\\\n+ } while (0 == 1);\n+\n+int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type);\n+\n+void bl_printk(const char *format, ...);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_md5.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_md5.h b/bsp/bl808/m0/libraries/utils/include/utils_md5.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2ac9461e9f5dac794f7eba57aedc5f3c34d9a325\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_md5.h\n@@ -0,0 +1,105 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+\n+\n+#ifndef _IOTX_COMMON_MD5_H_\n+#define _IOTX_COMMON_MD5_H_\n+\n+#include \"iot_import.h\"\n+\n+typedef struct {\n+ uint32_t total[2]; /*!< number of bytes processed */\n+ uint32_t state[4]; /*!< intermediate digest state */\n+ unsigned char buffer[64]; /*!< data block being processed */\n+} iot_md5_context;\n+\n+/**\n+ * \\brief Initialize MD5 context\n+ *\n+ * \\param ctx MD5 context to be initialized\n+ */\n+void utils_md5_init(iot_md5_context *ctx);\n+\n+/**\n+ * \\brief Clear MD5 context\n+ *\n+ * \\param ctx MD5 context to be cleared\n+ */\n+void utils_md5_free(iot_md5_context *ctx);\n+\n+/**\n+ * \\brief Clone (the state of) an MD5 context\n+ *\n+ * \\param dst The destination context\n+ * \\param src The context to be cloned\n+ */\n+void utils_md5_clone(iot_md5_context *dst,\n+ const iot_md5_context *src);\n+\n+/**\n+ * \\brief MD5 context setup\n+ *\n+ * \\param ctx context to be initialized\n+ */\n+void utils_md5_starts(iot_md5_context *ctx);\n+\n+/**\n+ * \\brief MD5 process buffer\n+ *\n+ * \\param ctx MD5 context\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ */\n+void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen);\n+\n+/**\n+ * \\brief MD5 final digest\n+ *\n+ * \\param ctx MD5 context\n+ * \\param output MD5 checksum result\n+ */\n+void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16]);\n+\n+/* Internal use */\n+void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64]);\n+\n+/**\n+ * \\brief Output = MD5( input buffer )\n+ *\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ * \\param output MD5 checksum result\n+ */\n+void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16]);\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_memp.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_memp.h b/bsp/bl808/m0/libraries/utils/include/utils_memp.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e89951d7e41e312e487a953b631ae848b56afc2f\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_memp.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_MEMP_H__\n+#define __UTILS_MEMP_H__\n+\n+\n+struct utils_memp_node {\n+ struct utils_memp_node *next;\n+};\n+\n+typedef struct pool {\n+ uint32_t node_size;\n+ uint32_t pool_cap;\n+ uint32_t pool_size;\n+ uint8_t align_req;\n+ uint32_t padded_node_size;\n+ void *first_node;\n+ void *last_node;\n+ struct utils_memp_node *mem;\n+}utils_memp_pool_t;\n+\n+int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);\n+int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);\n+int utils_memp_deinit(utils_memp_pool_t *pool);\n+void *utils_memp_malloc(utils_memp_pool_t *pool);\n+int utils_memp_free(utils_memp_pool_t *pool, void *node);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_notifier.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_notifier.h b/bsp/bl808/m0/libraries/utils/include/utils_notifier.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3120cb004c09ffcfffce7f391fbd421e8c241c0d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_notifier.h\n@@ -0,0 +1,51 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __NOTIFIER_H__\n+#define __NOTIFIER_H__\n+\n+#include <utils_list.h>\n+\n+typedef struct utils_list ntf_list_t;\n+typedef int (*utils_notifier_fn_t)(void *cb_arg, void *env);\n+\n+typedef struct utils_notifier {\n+ struct utils_list_hdr node;\n+ utils_notifier_fn_t cb;\n+ void *cb_arg;\n+ int priority;\n+} utils_notifier_t;\n+\n+int utils_notifier_chain_init(ntf_list_t *nl);\n+int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node);\n+int utils_notifier_chain_call(ntf_list_t *nl, void *env);\n+\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d178344b0b34ad28c79a213bca945099c99c463b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h\n@@ -0,0 +1,36 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_PSK_FAST_H__\n+#define __UTILS_PSK_FAST_H__\n+\n+int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output);\n+int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output);\n+\n+#endif /* __UTILS_PSK_FAST_H__ */\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_rbtree.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h b/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..068b3daa4aa0a79a47e3f8c34d6563cb678bfd8b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h\n@@ -0,0 +1,100 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __UTILS_RBTREE_H__\n+#define __UTILS_RBTREE_H__\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stddef.h>\n+\n+#ifndef RB_ITER_MAX_HEIGHT\n+#define RB_ITER_MAX_HEIGHT 64 // Tallest allowable tree to iterate\n+#endif\n+\n+struct rb_node;\n+struct rb_tree;\n+\n+typedef int (*rb_tree_node_cmp_f) (struct rb_tree *self, struct rb_node *a, struct rb_node *b);\n+typedef void (*rb_tree_node_f) (struct rb_tree *self, struct rb_node *node);\n+\n+struct rb_node {\n+ int red; // Color red (1), black (0)\n+ struct rb_node *link[2]; // Link left [0] and right [1]\n+ void *value; // User provided, used indirectly via rb_tree_node_cmp_f.\n+};\n+\n+struct rb_tree {\n+ struct rb_node *root;\n+ rb_tree_node_cmp_f cmp;\n+ size_t size;\n+ void *info; // User provided, not used by rb_tree.\n+};\n+\n+struct rb_iter {\n+ struct rb_tree *tree;\n+ struct rb_node *node; // Current node\n+ struct rb_node *path[RB_ITER_MAX_HEIGHT]; // Traversal path\n+ size_t top; // Top of stack\n+ void *info; // User provided, not used by rb_iter.\n+};\n+\n+int rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b);\n+void rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node);\n+\n+struct rb_node *rb_node_alloc ();\n+struct rb_node *rb_node_create (void *value);\n+struct rb_node *rb_node_init (struct rb_node *self, void *value);\n+void rb_node_dealloc (struct rb_node *self);\n+\n+struct rb_tree *rb_tree_alloc ();\n+struct rb_tree *rb_tree_create (rb_tree_node_cmp_f cmp);\n+struct rb_tree *rb_tree_init (struct rb_tree *self, rb_tree_node_cmp_f cmp);\n+void rb_tree_dealloc (struct rb_tree *self, rb_tree_node_f node_cb);\n+void *rb_tree_find (struct rb_tree *self, void *value);\n+int rb_tree_insert (struct rb_tree *self, void *value);\n+int rb_tree_remove (struct rb_tree *self, void *value);\n+size_t rb_tree_size (struct rb_tree *self);\n+\n+int rb_tree_insert_node (struct rb_tree *self, struct rb_node *node);\n+int rb_tree_remove_with_cb (struct rb_tree *self, void *value, rb_tree_node_f node_cb);\n+\n+int rb_tree_test (struct rb_tree *self, struct rb_node *root);\n+\n+struct rb_iter *rb_iter_alloc ();\n+struct rb_iter *rb_iter_init ();\n+struct rb_iter *rb_iter_create ();\n+void rb_iter_dealloc (struct rb_iter *self);\n+void *rb_iter_first (struct rb_iter *self, struct rb_tree *tree);\n+void *rb_iter_last (struct rb_iter *self, struct rb_tree *tree);\n+void *rb_iter_next (struct rb_iter *self);\n+void *rb_iter_prev (struct rb_iter *self);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_ringblk.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h b/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..91526bccf17a7f556920cda5a2c2f7fb4a7c173e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h\n@@ -0,0 +1,136 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _UTILS_RINGBLK_H_\n+#define _UTILS_RINGBLK_H_\n+\n+\n+#include \"stddef.h\"\n+#include <stdint.h>\n+#include \"utils_list.h\"\n+\n+\n+#define UTILS_RINGBLK_TEST\n+\n+/*\n+ * Introduction:\n+ * The rbb is the ring buffer which is composed with many blocks. It is different from the ring buffer.\n+ * The ring buffer is only\u0013 composed with chars. The rbb put and get supported zero copies. So the rbb\n+ * is very suitable for put block and get block by a certain order. Such as DMA block transmit,\n+ * communicate frame send/recv, and so on.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+enum utils_rbb_status\n+{\n+ /* unused status when first initialize or after blk_free() */\n+ RBB_BLK_UNUSED,\n+ /* initialized status after blk_alloc() */\n+ RBB_BLK_INITED,\n+ /* put status after blk_put() */\n+ RBB_BLK_PUT,\n+ /* get status after blk_get() */\n+ RBB_BLK_GET,\n+};\n+typedef enum utils_rbb_status utils_rbb_status_t;\n+\n+/**\n+ * the block of rbb\n+ */\n+struct utils_rbb_blk\n+{\n+ utils_rbb_status_t status :8;\n+ /* less then 2^24 */\n+ uint32_t size :24;\n+ uint8_t *buf;\n+ utils_slist_t list;\n+};\n+typedef struct utils_rbb_blk *utils_rbb_blk_t;\n+\n+/**\n+ * Rbb block queue: the blocks (from block1->buf to blockn->buf) memory which on this queue is continuous.\n+ */\n+struct utils_rbb_blk_queue\n+{\n+ utils_rbb_blk_t blocks;\n+ uint32_t blk_num;\n+};\n+typedef struct utils_rbb_blk_queue *utils_rbb_blk_queue_t;\n+\n+/**\n+ * ring block buffer\n+ */\n+struct utils_rbb\n+{\n+ uint8_t *buf;\n+ uint32_t buf_size;\n+ /* all of blocks */\n+ utils_rbb_blk_t blk_set;\n+ uint32_t blk_max_num;\n+ /* saved the initialized and put status blocks */\n+ utils_slist_t blk_list;\n+};\n+typedef struct utils_rbb *utils_rbb_t;\n+\n+/* rbb (ring block buffer) API */\n+void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num);\n+uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb);\n+\n+utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num);\n+void utils_rbb_destroy(utils_rbb_t rbb);\n+\n+/* rbb block API */\n+utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size);\n+void utils_rbb_blk_put(utils_rbb_blk_t block);\n+utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb);\n+uint32_t utils_rbb_blk_size(utils_rbb_blk_t block);\n+uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block);\n+void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block);\n+utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb);\n+utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb);\n+\n+/* rbb block queue API */\n+uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue);\n+uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue);\n+uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue);\n+void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue);\n+uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb);\n+\n+\n+int utils_rbb_cli_init(void);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _UTILS_RINGBLK_H_ */\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_sha1.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha1.h b/bsp/bl808/m0/libraries/utils/include/utils_sha1.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..422ee3d59e0617cad3eda07e2e4a04f3796849bd\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_sha1.h\n@@ -0,0 +1,108 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+\n+\n+#ifndef _IOTX_COMMON_SHA1_H_\n+#define _IOTX_COMMON_SHA1_H_\n+\n+#include \"iot_import.h\"\n+\n+\n+/**\n+ * \\brief SHA-1 context structure\n+ */\n+typedef struct {\n+ uint32_t total[2]; /*!< number of bytes processed */\n+ uint32_t state[5]; /*!< intermediate digest state */\n+ unsigned char buffer[64]; /*!< data block being processed */\n+} iot_sha1_context;\n+\n+/**\n+ * \\brief Initialize SHA-1 context\n+ *\n+ * \\param ctx SHA-1 context to be initialized\n+ */\n+void utils_sha1_init(iot_sha1_context *ctx);\n+\n+/**\n+ * \\brief Clear SHA-1 context\n+ *\n+ * \\param ctx SHA-1 context to be cleared\n+ */\n+void utils_sha1_free(iot_sha1_context *ctx);\n+\n+/**\n+ * \\brief Clone (the state of) a SHA-1 context\n+ *\n+ * \\param dst The destination context\n+ * \\param src The context to be cloned\n+ */\n+void utils_sha1_clone(iot_sha1_context *dst,\n+ const iot_sha1_context *src);\n+\n+/**\n+ * \\brief SHA-1 context setup\n+ *\n+ * \\param ctx context to be initialized\n+ */\n+void utils_sha1_starts(iot_sha1_context *ctx);\n+\n+/**\n+ * \\brief SHA-1 process buffer\n+ *\n+ * \\param ctx SHA-1 context\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ */\n+void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen);\n+\n+/**\n+ * \\brief SHA-1 final digest\n+ *\n+ * \\param ctx SHA-1 context\n+ * \\param output SHA-1 checksum result\n+ */\n+void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20]);\n+\n+/* Internal use */\n+void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64]);\n+\n+/**\n+ * \\brief Output = SHA-1( input buffer )\n+ *\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ * \\param output SHA-1 checksum result\n+ */\n+void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20]);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_sha256.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha256.h b/bsp/bl808/m0/libraries/utils/include/utils_sha256.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..42379eba45da5d5ae99109ec74d33146c58fe87e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_sha256.h\n@@ -0,0 +1,119 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+\n+\n+#ifndef _IOTX_COMMON_SHA256_H_\n+#define _IOTX_COMMON_SHA256_H_\n+\n+#include <stdint.h>\n+\n+#define SHA256_DIGEST_LENGTH (32)\n+#define SHA256_BLOCK_LENGTH (64)\n+#define SHA256_SHORT_BLOCK_LENGTH (SHA256_BLOCK_LENGTH - 8)\n+#define SHA256_DIGEST_STRING_LENGTH (SHA256_DIGEST_LENGTH * 2 + 1)\n+\n+/**\n+ * \\brief SHA-256 context structure\n+ */\n+typedef struct {\n+ uint32_t total[2]; /*!< number of bytes processed */\n+ uint32_t state[8]; /*!< intermediate digest state */\n+ unsigned char buffer[64]; /*!< data block being processed */\n+ int is224; /*!< 0 => SHA-256, else SHA-224 */\n+} iot_sha256_context;\n+\n+typedef union {\n+ char sptr[8];\n+ uint64_t lint;\n+} u_retLen;\n+\n+/**\n+ * \\brief Initialize SHA-256 context\n+ *\n+ * \\param ctx SHA-256 context to be initialized\n+ */\n+void utils_sha256_init(iot_sha256_context *ctx);\n+\n+/**\n+ * \\brief Clear SHA-256 context\n+ *\n+ * \\param ctx SHA-256 context to be cleared\n+ */\n+void utils_sha256_free(iot_sha256_context *ctx);\n+\n+/**\n+ * \\brief Clone (the state of) a SHA-256 context\n+ *\n+ * \\param dst The destination context\n+ * \\param src The context to be cloned\n+ */\n+void utils_sha256_clone(iot_sha256_context *dst,\n+ const iot_sha256_context *src);\n+\n+/**\n+ * \\brief SHA-256 context setup\n+ *\n+ * \\param ctx context to be initialized\n+ */\n+void utils_sha256_starts(iot_sha256_context *ctx);\n+\n+/**\n+ * \\brief SHA-256 process buffer\n+ *\n+ * \\param ctx SHA-256 context\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ */\n+void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen);\n+\n+/**\n+ * \\brief SHA-256 final digest\n+ *\n+ * \\param ctx SHA-256 context\n+ * \\param output SHA-256 checksum result\n+ */\n+void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32]);\n+\n+/* Internal use */\n+void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64]);\n+\n+/**\n+ * \\brief Output = SHA-256( input buffer )\n+ *\n+ * \\param input buffer holding the data\n+ * \\param ilen length of the input data\n+ * \\param output SHA-256 checksum result\n+ */\n+void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32]);\n+\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_string.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_string.h b/bsp/bl808/m0/libraries/utils/include/utils_string.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6a7626ade607a4d0f64d9b1c484a7296c639c2cb\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_string.h\n@@ -0,0 +1,60 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_STRING_H__\n+#define __UTILS_STRING_H__\n+void get_bytearray_from_string(char** params, uint8_t *result,int array_size);\n+void get_uint8_from_string(char** params, uint8_t *result);\n+void get_uint16_from_string(char** params, uint16_t *result);\n+void get_uint32_from_string(char** params, uint32_t *result);\n+void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base);\n+void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count);\n+unsigned long long convert_arrayToU64(uint8_t* inputArray);\n+void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8]);\n+void utils_memcpy8(void *dst, void *src, size_t len);\n+void utils_memcpy16(void *dst, void *src, size_t len);\n+void utils_memcpy32(void *dst, void *src, size_t len);\n+void utils_memcpy64(void *dst, void *src, size_t len);\n+void utils_memset8(void *src, uint8_t n, size_t len);\n+void utils_memset16(void *src, uint16_t n, size_t len);\n+void utils_memset32(void *src, uint32_t n, size_t len);\n+void utils_memset64(void *src, uint64_t n, size_t len);\n+void utils_memset8_with_seq(void *src, uint8_t seq, size_t len);\n+void utils_memset16_with_seq(void *src, uint16_t seq, size_t len);\n+void utils_memset32_with_seq(void *src, uint32_t seq, size_t len);\n+void utils_memset64_with_seq(void *src, uint64_t seq, size_t len);\n+void utils_memdrain8(void *src, size_t len);\n+void utils_memdrain16(void *src, size_t len);\n+void utils_memdrain32(void *src, size_t len);\n+void utils_memdrain64(void *src, size_t len);\n+void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq);\n+void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq);\n+void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq);\n+void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_time.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_time.h b/bsp/bl808/m0/libraries/utils/include/utils_time.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ef12f1e27228cc4a32636b83ae9d7b56a5cbd683\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_time.h\n@@ -0,0 +1,48 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_TIME_H__\n+#define __UTILS_TIME_H__\n+typedef struct {\n+ unsigned char ntp_hour;\n+ unsigned char ntp_minute;\n+ unsigned char ntp_second;\n+ unsigned char ntp_week_day;\n+ unsigned char ntp_date;\n+ unsigned char ntp_month;\n+ unsigned char leap_days;\n+ unsigned char leap_year_ind;\n+ unsigned int ntp_year;\n+ unsigned int days_since_epoch;\n+ unsigned int day_of_year; \n+} utils_time_date_t;\n+\n+int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date);\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h\ndiff --git a/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h b/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8ee870f6c6da9ce297cd1e1ed40b7c3d9329dd57\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h\n@@ -0,0 +1,80 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __UTILS_TLV_BL_H__\n+#define __UTILS_TLV_BL_H__\n+#include <stdint.h>\n+#include <stdbool.h>\n+\n+#define CFG_ELEMENT_TYPE_SIZE_BOOLEAN (4)\n+#define CFG_ELEMENT_TYPE_SIZE_UINT32 (4)\n+#define UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL (-1)\n+#define UTILS_TLV_BL_ERROR_CODE_UNKOWN (-2)\n+// Wi-Fi CFG API\n+enum CFG_ELEMENT_TYPE {\n+ CFG_ELEMENT_TYPE_UNKNOWN,\n+ CFG_ELEMENT_TYPE_BOOLEAN,\n+ CFG_ELEMENT_TYPE_SINT8,\n+ CFG_ELEMENT_TYPE_UINT8,\n+ CFG_ELEMENT_TYPE_SINT16,\n+ CFG_ELEMENT_TYPE_UINT16,\n+ CFG_ELEMENT_TYPE_SINT32,\n+ CFG_ELEMENT_TYPE_UINT32,\n+ CFG_ELEMENT_TYPE_STRING,\n+};\n+\n+enum CFG_ELEMENT_TYPE_OPS\n+{\n+ CFG_ELEMENT_TYPE_OPS_SET,\n+ CFG_ELEMENT_TYPE_OPS_GET,\n+ CFG_ELEMENT_TYPE_OPS_RESET,\n+ CFG_ELEMENT_TYPE_OPS_DUMP_DEBUG,\n+ CFG_ELEMENT_TYPE_OPS_UNKNOWN,\n+};\n+\n+int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val);\n+int utils_tlv_bl_pack_uint8(uint32_t *buf, int buf_sz, uint8_t val);\n+int utils_tlv_bl_pack_int8(uint32_t *buf, int buf_sz, int8_t val);\n+int utils_tlv_bl_pack_uint16(uint32_t *buf, int buf_sz, uint16_t val);\n+int utils_tlv_bl_pack_int16(uint32_t *buf, int buf_sz, int16_t val);\n+int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val);\n+int utils_tlv_bl_pack_int32(uint32_t *buf, int buf_sz, int32_t val);\n+int utils_tlv_bl_pack_string(uint32_t *buf, int buf_sz, const char *str);\n+int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);\n+\n+int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val);\n+int utils_tlv_bl_unpack_uint8(uint32_t *buf, int buf_sz, uint8_t *val);\n+int utils_tlv_bl_unpack_int8(uint32_t *buf, int buf_sz, int8_t *val);\n+int utils_tlv_bl_unpack_uint16(uint32_t *buf, int buf_sz, uint16_t *val);\n+int utils_tlv_bl_unpack_int16(uint32_t *buf, int buf_sz, int16_t *val);\n+int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val);\n+int utils_tlv_bl_unpack_int32(uint32_t *buf, int buf_sz, int32_t *val);\n+int utils_tlv_bl_unpack_string(uint32_t *buf, int buf_sz, char *str, int size);\n+int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0dee7bc1fcebac9bb0fb1de34cb6dd99020c5560\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c\n@@ -0,0 +1,109 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <stdio.h>\n+#include <FreeRTOS.h>\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+#include <cli.h>\n+#endif\n+#include \"utils_base64.h\"\n+#include <utils_log.h>\n+\n+#ifdef UTILS_BASE64_TEST\n+\n+static void cmd_encode(char *buf, int len, int argc, char **argv)\n+{\n+ uint32_t input_len, output_len = 0;\n+ char *inbuf, *outbuf = NULL;\n+\n+ if (argc != 3)\n+ {\n+ log_error(\"Usage:\\r\\n\");\n+ log_error(\"encode_base64 0x420c0000 512\\r\\n\");\n+ return;\n+ }\n+\n+ inbuf = (char *)strtol(argv[1], NULL, 0);\n+ input_len = strtol(argv[2], NULL, 0);\n+ if (inbuf != NULL && input_len != 0)\n+ {\n+ output_len = 4 * ((input_len + 2) / 3);\n+ outbuf = calloc(1, output_len);\n+\n+ if (outbuf)\n+ {\n+ if (SUCCESS_RETURN == utils_base64encode((uint8_t *)inbuf, input_len, output_len, (uint8_t *)outbuf, &output_len))\n+ {\n+ uint32_t i = 0;\n+ char *addr = outbuf;\n+ for (i = 0; i < output_len; i++)\n+ {\n+ #ifdef CONFIG_CLI_CMD_ENABLE\n+ aos_cli_printf(\"%c\", *(char *)addr);\n+ #endif\n+ addr += 1;\n+ }\n+ }\n+ else\n+ {\n+ log_error(\"base64 encode error\\r\\n\");\n+ }\n+\n+ free(outbuf);\n+ }\n+ else\n+ {\n+ log_error(\"base64 encode mem not enough %d\\r\\n\", output_len);\n+ }\n+ }\n+ else\n+ {\n+ log_error(\"base64 encode argc error\\r\\n\");\n+ }\n+\n+}\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {\n+ { \"encode_base64\", \"base64 encode\", cmd_encode},\n+};\n+#endif\n+\n+int base64_cli_init(void)\n+{\n+ // static command(s) do NOT need to call aos_cli_register_command(s) to register.\n+ // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.\n+ // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.\n+ //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));\n+ return 0;\n+}\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f2cc9e9146b95e0cfb3e497b4df383fb2d9d0e02\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c\n@@ -0,0 +1,105 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <utils_bitmap_window.h>\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+#include <cli.h>\n+#endif\n+#include <stdio.h>\n+\n+static void cmd_bitmap_window_test(char *buf, int len, int argc, char **argv)\n+{\n+ int ret;\n+ struct utils_bitmap_ctx ctx;\n+\n+ utils_bitmap_window_init(&ctx, 0, 4095);\n+\n+ printf(\"Set Seq 1 2 3 4 5 6 7...\\r\\n\");\n+ utils_bitmap_window_bit_set(&ctx, 1);\n+ utils_bitmap_window_bit_set(&ctx, 2);\n+ utils_bitmap_window_bit_set(&ctx, 3);\n+ utils_bitmap_window_bit_set(&ctx, 4);\n+ utils_bitmap_window_bit_set(&ctx, 5);\n+ utils_bitmap_window_bit_set(&ctx, 6);\n+ ret = utils_bitmap_window_bit_set(&ctx, 7);\n+ printf(\" Got ssn %d(0) Bitmap %llx(0), ret %x\\r\\n\",\n+ utils_bitmap_window_ssn_get(&ctx),\n+ utils_bitmap_window_map_get(&ctx),\n+ ret\n+ );\n+\n+ printf(\"Set Seq 0 ...\\r\\n\");\n+ ret = utils_bitmap_window_bit_set(&ctx, 0);\n+ printf(\" Got ssn %d(8) Bitmap %llx(0), ret %x\\r\\n\",\n+ utils_bitmap_window_ssn_get(&ctx),\n+ utils_bitmap_window_map_get(&ctx),\n+ ret\n+ );\n+\n+ printf(\"Set Seq 0 ...\\r\\n\");\n+ ret = utils_bitmap_window_bit_set(&ctx, 0);\n+ printf(\" Got ssn %d(8) Bitmap %llx(0), ret %x\\r\\n\",\n+ utils_bitmap_window_ssn_get(&ctx),\n+ utils_bitmap_window_map_get(&ctx),\n+ ret\n+ );\n+\n+ printf(\"Set Seq 9 ...\\r\\n\");\n+ ret = utils_bitmap_window_bit_set(&ctx, 9);\n+ printf(\" Got ssn %d(8) Bitmap %llx(2), ret %x\\r\\n\",\n+ utils_bitmap_window_ssn_get(&ctx),\n+ utils_bitmap_window_map_get(&ctx),\n+ ret\n+ );\n+\n+ printf(\"Set Seq 9 ...\\r\\n\");\n+ ret = utils_bitmap_window_bit_set(&ctx, 9);\n+ printf(\" Got ssn %d(8) Bitmap %llx(2), ret %d\\r\\n\",\n+ utils_bitmap_window_ssn_get(&ctx),\n+ utils_bitmap_window_map_get(&ctx),\n+ ret\n+ );\n+\n+}\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {\n+ {\"utils_bitmap_widow_test\", \"bitmap window test\", cmd_bitmap_window_test},\n+};\n+#endif\n+\n+int utils_bitmap_window_cli_init(void)\n+{\n+ // static command(s) do NOT need to call aos_cli_register_command(s) to register.\n+ // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.\n+ // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.\n+ //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7ae8670ade21221dfbc4cccb80bbc2da401b5a96\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c\n@@ -0,0 +1,94 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"../../include/utils_rbtree.h\"\n+#include <stdint.h>\n+#include <stdio.h>\n+\n+struct iovec {\n+ void *iov_base; // [XSI] Base address of I/O memory region\n+ size_t iov_len; // [XSI] Size of region iov_base points to\n+};\n+\n+static int my_cmp_cb(struct rb_tree *self, struct rb_node *node_a, struct rb_node *node_b) \n+{\n+ struct iovec *a = (struct iovec *) node_a->value;\n+ struct iovec *b = (struct iovec *) node_b->value;\n+\n+ return (a->iov_len > b->iov_len) - (a->iov_len < b->iov_len);\n+}\n+\n+int main(int argc, char *argv[])\n+{\n+ struct rb_tree *tree = rb_tree_create(my_cmp_cb);\n+ if (tree) {\n+ // Use the tree here...\n+ for (int i = 0; i < 10; i++) {\n+ struct iovec *v = malloc(sizeof *v);\n+ v->iov_base = (void *) i;\n+ v->iov_len = i * i;\n+ // Default insert, which allocates internal rb_nodes for you.\n+ printf(\"[rb_tree_insert] insert %p with base %p len %d\\r\\n\",\n+ v,\n+ v->iov_base,\n+ v->iov_len\n+ );\n+ rb_tree_insert(tree, v);\n+ }\n+\n+ // To f\n+ struct iovec *f = rb_tree_find(tree,\n+ & (struct iovec) { .iov_base = (void *) 7, .iov_len = 0 }\n+ );\n+ if (f) {\n+ printf(\"[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\\n\", f, f->iov_base, f->iov_len);\n+ } else {\n+ printf(\"[rb_tree_find] iov_len 9 not found\\n\");\n+ }\n+\n+ printf(\"[rb_tree_test] testing...\\r\\n\");\n+ rb_tree_test(tree, f);\n+\n+ f = rb_tree_find(tree,\n+ & (struct iovec) { .iov_base = (void *) 7, .iov_len = 10 }\n+ );\n+ if (f) {\n+ printf(\"[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\\n\", f, f->iov_base, f->iov_len);\n+ } else {\n+ printf(\"[rb_tree_find] iov_len 10 not found\\n\");\n+ }\n+\n+ printf(\"[rb_tree_size] is %d\\r\\n\", rb_tree_size(tree));\n+\n+ // Dealloc call can take optional parameter to notify on each node\n+ // being deleted so you can free the node and/or your object:\n+ rb_tree_dealloc(tree, NULL);\n+ }\n+}\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b79f7cd5ac5782fbf0b1ca368a5f3b0ce276fa64\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c\n@@ -0,0 +1,388 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdlib.h>\n+#include <assert.h>\n+#include <inttypes.h>\n+\n+#include <FreeRTOS.h>\n+#include <task.h>\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+#include <cli.h>\n+#endif\n+#include \"utils_ringblk.h\"\n+\n+#ifdef UTILS_RINGBLK_TEST\n+\n+\n+static void cmd_ringblk_test(char *buf, int len, int argc, char **argv)\n+{\n+ utils_rbb_t rbb;\n+ utils_rbb_blk_t blk1, blk2, blk3, blk4, blk5, blk6, _blk1, _blk2;\n+ uint32_t i, j, k, req_size, size;\n+ struct utils_rbb_blk_queue blk_queue1;\n+\n+ /* create ring block buffer */\n+ printf(\"\\n====================== rbb create test =====================\\r\\n\");\n+ rbb = utils_rbb_create(52, 6);\n+ if (rbb)\n+ {\n+ printf(\"6 blocks in 52 bytes ring block buffer object create success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: 6 blocks in 52 bytes ring block buffer object create failed.\\r\\n\");\n+ }\n+ /* allocate block */\n+ printf(\"\\n====================== rbb alloc test =====================\\r\\n\");\n+ blk1 = utils_rbb_blk_alloc(rbb, 2);\n+ if (blk1 && blk1->size == 2)\n+ {\n+ memset(blk1->buf, 1, blk1->size);\n+ printf(\"Block1 (2 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block1 (2 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ blk2 = utils_rbb_blk_alloc(rbb, 4);\n+ if (blk2 && blk2->size == 4)\n+ {\n+ memset(blk2->buf, 2, blk2->size);\n+ printf(\"Block2 (4 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block2 (4 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ blk3 = utils_rbb_blk_alloc(rbb, 8);\n+ if (blk3 && blk3->size == 8)\n+ {\n+ memset(blk3->buf, 3, blk3->size);\n+ printf(\"Block3 (8 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block3 (8 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ blk4 = utils_rbb_blk_alloc(rbb, 16);\n+ if (blk4 && blk4->size == 16)\n+ {\n+ memset(blk4->buf, 4, blk4->size);\n+ printf(\"Block4 (16 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block4 (16 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ blk5 = utils_rbb_blk_alloc(rbb, 32);\n+ if (blk5 && blk5->size == 32)\n+ {\n+ memset(blk5->buf, 5, blk5->size);\n+ printf(\"Block5 (32 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Block5 (32 bytes) allocate failed.\\r\\n\");\n+ }\n+ blk5 = utils_rbb_blk_alloc(rbb, 18);\n+ if (blk5 && blk5->size == 18)\n+ {\n+ memset(blk5->buf, 5, blk5->size);\n+ printf(\"Block5 (18 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block5 (18 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| blcok1 | block2 | block3 | block4 | block5 | empty |\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| inited | inited | inited | inited | inited | |\\r\\n\");\n+ //\n+ /* put block */\n+ printf(\"\\n====================== rbb put test =====================\\r\\n\");\n+ utils_rbb_blk_put(blk1);\n+ utils_rbb_blk_put(blk2);\n+ utils_rbb_blk_put(blk3);\n+ utils_rbb_blk_put(blk4);\n+ utils_rbb_blk_put(blk5);\n+ printf(\"Block1 to block5 put success.\\r\\n\");\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| blcok1 | block2 | block3 | block4 | block5 | empty |\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| put | put | put | put | put | |\\r\\n\");\n+ //\n+ /* get block */\n+ printf(\"\\n====================== rbb get test =====================\\r\\n\");\n+ _blk1 = utils_rbb_blk_get(rbb);\n+ _blk2 = utils_rbb_blk_get(rbb);\n+ for (i = 0; i < _blk1->size; i++)\n+ {\n+ if (_blk1->buf[i] != 1) break;\n+ }\n+ for (j = 0; j < _blk2->size; j++)\n+ {\n+ if (_blk2->buf[j] != 2) break;\n+ }\n+ if (blk1 == _blk1 && blk2 == _blk2 && i == _blk1->size && j == _blk2->size)\n+ {\n+ printf(\"Block1 and block2 get success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block1 and block2 get failed.\\r\\n\");\n+ goto __exit;\n+ }\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| blcok1 | block2 | block3 | block4 | block5 | empty |\\r\\n\");\n+ printf(\"+--------+---------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| get | get | put | put | put | |\\r\\n\");\n+ //\n+ /* free block */\n+ printf(\"\\n====================== rbb free test =====================\\r\\n\");\n+ utils_rbb_blk_free(rbb, blk2);\n+ printf(\"Block2 free success.\\r\\n\");\n+ utils_rbb_blk_free(rbb, blk1);\n+ printf(\"Block1 free success.\\r\\n\");\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<------- 6 ------>|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+------------------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| empty2 | block3 | block4 | block5 | empty1 |\\r\\n\");\n+ printf(\"+------------------+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| | put | put | put | |\\r\\n\");\n+\n+ blk6 = utils_rbb_blk_alloc(rbb, 5);\n+ if (blk6)\n+ {\n+ printf(\"Block6 (5 bytes) allocate success.\\r\\n\");\n+ }\n+ else\n+ {\n+ printf(\"Test error: block6 (5 bytes) allocate failed.\\r\\n\");\n+ goto __exit;\n+ }\n+\n+ utils_rbb_blk_put(blk6);\n+ printf(\"Block6 put success.\\r\\n\");\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+------------+-----+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| block6 |empty| block3 | block4 | block5 | fragment |\\r\\n\");\n+ printf(\"+------------+-----+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| put | | put | put | put | |\\r\\n\");\n+\n+ /* get block queue */\n+ printf(\"\\n====================== rbb block queue get test =====================\\r\\n\");\n+ req_size = utils_rbb_next_blk_queue_len(rbb) + 5;\n+ size = utils_rbb_blk_queue_get(rbb, req_size, &blk_queue1);\n+ i = j = k = 0;\n+ for (; i < blk3->size; i++)\n+ {\n+ if (utils_rbb_blk_queue_buf(&blk_queue1)[i] != 3) break;\n+ }\n+ for (; j < blk4->size; j++)\n+ {\n+ if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j] != 4) break;\n+ }\n+ for (; k < blk5->size; k++)\n+ {\n+ if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j + k] != 5) break;\n+ }\n+ if (size && size == 42 && utils_rbb_blk_queue_len(&blk_queue1) == 42 && k == blk5->size)\n+ {\n+ printf(\"Block queue (request %\"PRIu32\" bytes, actual %\"PRIu32\") get success.\\r\\n\", req_size, size);\n+ }\n+ else\n+ {\n+ printf(\"Test error: Block queue (request %\"PRIu32\" bytes, actual %\"PRIu32\") get failed.\\r\\n\", req_size, size);\n+ goto __exit;\n+ }\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"| | |<----- block queue1 (42 bytes continuous buffer) ----->| |\\r\\n\");\n+ printf(\"|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\\r\\n\");\n+ printf(\"+------------+-----+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| block6 |empty| block3 | block4 | block5 | fragment |\\r\\n\");\n+ printf(\"+------------+-----+--------------+---------------------+------------------+-------------+\\r\\n\");\n+ printf(\"| put | | get | get | get | |\\r\\n\");\n+\n+ /* free block queue */\n+ printf(\"\\n====================== rbb block queue free test =====================\\r\\n\");\n+ utils_rbb_blk_queue_free(rbb, &blk_queue1);\n+ printf(\"Block queue1 free success.\\r\\n\");\n+ printf(\"Ring block buffer current status:\\r\\n\");\n+ printf(\"next block queue length: %\"PRIu32\"\\r\\n\", utils_rbb_next_blk_queue_len(rbb));\n+ printf(\"block list length: %d\\r\\n\", utils_slist_entry_number(&rbb->blk_list));\n+ printf(\"|<--- 5 ---->|<--------------------------------- 47 ------------------------------------>|\\r\\n\");\n+ printf(\"+------------+---------------------------------------------------------------------------+\\r\\n\");\n+ printf(\"| block6 | empty |\\r\\n\");\n+ printf(\"+------------+---------------------------------------------------------------------------+\\r\\n\");\n+ printf(\"| put | |\\r\\n\");\n+ utils_rbb_blk_free(rbb, blk6);\n+\n+ printf(\"\\n====================== rbb static test SUCCESS =====================\\r\\n\");\n+\n+ printf(\"\\n====================== rbb dynamic test =====================\\r\\n\");\n+\n+__exit :\n+\n+ utils_rbb_destroy(rbb);\n+}\n+\n+\n+static uint8_t put_finish = 0;\n+\n+static void put_thread(void *param)\n+{\n+ utils_rbb_t rbb = (utils_rbb_t)param;\n+ utils_rbb_blk_t block;\n+ uint32_t put_count = 0;\n+\n+ put_finish = 0;\n+\n+ while (put_count < 10000)\n+ {\n+ block = utils_rbb_blk_alloc(rbb, rand() % 10 + 4);\n+ if (block)\n+ {\n+ memcpy(&block->buf[0], (void *)&put_count, 4);\n+ utils_rbb_blk_put(block);\n+ printf(\"put block size %d count %\" PRId32 \"\\r\\n\", block->size, put_count++);\n+ }\n+ else\n+ {\n+ printf(\"block alloc failed\\r\\n\");\n+ }\n+ vTaskDelay(rand() % 10);\n+ }\n+ printf(\"Put block data finish.\\r\\n\");\n+\n+ put_finish = 1;\n+\n+ vTaskDelete(NULL);\n+}\n+\n+static void get_thread(void *param)\n+{\n+ utils_rbb_t rbb = (utils_rbb_t)param;\n+ utils_rbb_blk_t block;\n+ uint32_t get_count = 0;\n+\n+ while (get_count < 10000)\n+ {\n+ block = utils_rbb_blk_get(rbb);\n+\n+ if (block)\n+ {\n+ if (memcmp(&block->buf[0], (void *)&get_count, 4) != 0)\n+ {\n+ printf(\"Error: get data (times %\" PRId32 \") has an error!\\r\\n\", get_count);\n+ goto exit_;\n+ }\n+ utils_rbb_blk_free(rbb, block);\n+ printf(\"free block size %d count %\" PRId32 \"\\r\\n\", block->size, get_count++);\n+ }\n+ else if (put_finish)\n+ {\n+ break;\n+ }\n+ vTaskDelay(rand() % 10);\n+ }\n+ printf(\"Get block data finish.\\r\\n\");\n+\n+ utils_rbb_blk_t new_rbb = utils_rbb_find_used_blk(rbb);\n+ if (new_rbb != NULL)\n+ {\n+ printf(\"\\n====================== rbb blk not free =====================\\r\\n\");\n+ }\n+\n+exit_:\n+ printf(\"\\n====================== rbb dynamic test finish =====================\\r\\n\");\n+\n+ utils_rbb_destroy(rbb);\n+\n+ vTaskDelete(NULL);\n+}\n+\n+static void cmd_ringblk_through_test(char *buf, int len, int argc, char **argv)\n+{\n+ utils_rbb_t rbb;\n+\n+ rbb = utils_rbb_create(100, 10);\n+\n+ xTaskCreate(put_thread, \"rbb_put\", 1024, rbb, 10, NULL);\n+\n+ xTaskCreate(get_thread, \"rbb_get\", 1024, rbb, 10, NULL);\n+}\n+\n+#ifdef CONFIG_CLI_CMD_ENABLE\n+const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {\n+ {\"rbb_static_test\", \"ringblk static test\", cmd_ringblk_test},\n+ {\"rbb_through_test\", \"ringblk dynamic test\", cmd_ringblk_through_test},\n+};\n+#endif\n+\n+int utils_rbb_cli_init(void)\n+{\n+ // static command(s) do NOT need to call aos_cli_register_command(s) to register.\n+ // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.\n+ // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.\n+ //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));\n+ return 0;\n+}\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_base64.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_base64.c b/bsp/bl808/m0/libraries/utils/src/utils_base64.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c17b77e98869dc6e0c68f75afce11b5f6b339f24\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_base64.c\n@@ -0,0 +1,206 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include \"utils_base64.h\"\n+#include <utils_log.h>\n+\n+static int8_t g_encodingTable[] = {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H',\n+ 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',\n+ 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X',\n+ 'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f',\n+ 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',\n+ 'o', 'p', 'q', 'r', 's', 't', 'u', 'v',\n+ 'w', 'x', 'y', 'z', '0', '1', '2', '3',\n+ '4', '5', '6', '7', '8', '9', '+', '/'\n+ };\n+\n+static int8_t g_decodingTable[256];\n+static int32_t g_modTable[] = { 0, 2, 1 };\n+\n+static void build_decoding_table()\n+{\n+ static int32_t signal = 0;\n+ int32_t i = 0;\n+\n+ if (signal != 0) {\n+ return;\n+ }\n+\n+ for (i = 0; i < 64; i++) {\n+ g_decodingTable[(uint8_t) g_encodingTable[i]] = i;\n+ }\n+\n+ signal = 1;\n+ return;\n+}\n+\n+iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,\n+ uint8_t *encodedData, uint32_t *outputLength)\n+{\n+ uint32_t i = 0;\n+ uint32_t j = 0;\n+\n+ if (NULL == encodedData) {\n+ log_error(\"pointer of encodedData is NULL!\\r\\n\");\n+ return FAIL_RETURN;\n+ }\n+\n+ *outputLength = 4 * ((inputLength + 2) / 3);\n+\n+ if (outputLenMax < *outputLength) {\n+ log_error(\"the length of output memory is not enough!\\r\\n\");\n+ return FAIL_RETURN;\n+ }\n+\n+ for (i = 0, j = 0; i < inputLength;) {\n+ uint32_t octet_a = i < inputLength ? (uint8_t) data[i++] : 0;\n+ uint32_t octet_b = i < inputLength ? (uint8_t) data[i++] : 0;\n+ uint32_t octet_c = i < inputLength ? (uint8_t) data[i++] : 0;\n+\n+ uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;\n+\n+ encodedData[j++] = g_encodingTable[(triple >> 3 * 6) & 0x3F];\n+ encodedData[j++] = g_encodingTable[(triple >> 2 * 6) & 0x3F];\n+ encodedData[j++] = g_encodingTable[(triple >> 1 * 6) & 0x3F];\n+ encodedData[j++] = g_encodingTable[(triple >> 0 * 6) & 0x3F];\n+ }\n+\n+ for (i = 0; i < g_modTable[inputLength % 3]; i++) {\n+ encodedData[*outputLength - 1 - i] = '=';\n+ }\n+\n+ return SUCCESS_RETURN;\n+}\n+\n+/*\n+ * Streaming Base64 encoder\n+ * param:\n+ * read_data: The callback function when the encoder absorbs data.\n+ * A non-zero return indicates the end of the data.\n+ * write_data: The callback function when the encoder releases data.\n+ * opaque: Callback function context.\n+ */\n+void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque)\n+{\n+ uint8_t encodedData[4], c;\n+ int end = 0, remainder = -1, i;\n+\n+ while (!end) {\n+ uint32_t octet_a = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 0), 0) : c;\n+ uint32_t octet_b = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 1), 0) : c;\n+ uint32_t octet_c = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 2), 0) : c;\n+\n+ uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;\n+\n+ if (end && remainder == 0) {\n+ return;\n+ }\n+\n+ encodedData[0] = g_encodingTable[(triple >> 3 * 6) & 0x3F];\n+ encodedData[1] = g_encodingTable[(triple >> 2 * 6) & 0x3F];\n+ encodedData[2] = g_encodingTable[(triple >> 1 * 6) & 0x3F];\n+ encodedData[3] = g_encodingTable[(triple >> 0 * 6) & 0x3F];\n+\n+ if (!end) {\n+ write_data(encodedData, opaque);\n+ }\n+ }\n+\n+ for (i = 0; i < g_modTable[remainder]; i++) {\n+ encodedData[3 - i] = '=';\n+ }\n+\n+ write_data(encodedData, opaque);\n+\n+ return;\n+}\n+\n+iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,\n+ uint8_t *decodedData, uint32_t *outputLength)\n+{\n+ uint32_t i = 0;\n+ uint32_t j = 0;\n+\n+ build_decoding_table();\n+\n+ if (inputLength % 4 != 0) {\n+ log_error(\"the input length is error!\\r\\n\");\n+ return FAIL_RETURN;\n+ }\n+\n+ *outputLength = inputLength / 4 * 3;\n+\n+\n+ if (data[inputLength - 1] == '=') {\n+ (*outputLength)--;\n+ }\n+\n+ if (data[inputLength - 2] == '=') {\n+ (*outputLength)--;\n+ }\n+\n+ if (outputLenMax < *outputLength) {\n+ log_error(\"the length of output memory is not enough!\\r\\n\");\n+ return FAIL_RETURN;\n+ }\n+\n+ uint32_t sextet_a = 0;\n+ uint32_t sextet_b = 0;\n+ uint32_t sextet_c = 0;\n+ uint32_t sextet_d = 0;\n+ uint32_t triple = 0;\n+\n+ for (i = 0, j = 0; i < inputLength;) {\n+ sextet_a = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];\n+ sextet_b = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];\n+ sextet_c = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];\n+ sextet_d = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];\n+\n+ triple = (sextet_a << 3 * 6) + (sextet_b << 2 * 6) + (sextet_c << 1 * 6) + (sextet_d << 0 * 6);\n+\n+ if (j < *outputLength) {\n+ decodedData[j++] = (triple >> 2 * 8) & 0xFF;\n+ }\n+\n+ if (j < *outputLength) {\n+ decodedData[j++] = (triple >> 1 * 8) & 0xFF;\n+ }\n+\n+ if (j < *outputLength) {\n+ decodedData[j++] = (triple >> 0 * 8) & 0xFF;\n+ }\n+ }\n+\n+ return SUCCESS_RETURN;\n+}\n+\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..3feb69c7656ab885c39ab1ccf2f8ab0a8f8783ab\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c\n@@ -0,0 +1,87 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <string.h>\n+#include <stdio.h>\n+#include <limits.h>\n+#include <utils_bitmap_window.h>\n+\n+int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max)\n+{\n+ memset(ctx, 0, sizeof(struct utils_bitmap_ctx));\n+ ctx->ssn = ssn;\n+ ctx->ssn_duration = ssn_max + 1;//ssn start from 0\n+\n+ return 0;\n+}\n+\n+int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos)\n+{\n+ int i;\n+ int pos_offset;\n+\n+ if (bit_pos < ctx->ssn) {\n+ /*failed case*/\n+ if (ctx->ssn_duration - ctx->ssn + bit_pos + 1 > sizeof(ctx->bitmap) * 8) {\n+ printf(\"small ssn %d\\r\\n\", bit_pos);\n+ return -INT_MAX;\n+ }\n+ }\n+ pos_offset = bit_pos + ctx->ssn_duration - ctx->ssn;\n+ if (pos_offset >= ctx->ssn_duration) {\n+ pos_offset -= ctx->ssn_duration;\n+ }\n+\n+ if (ctx->bitmap.map64 & (1 << pos_offset)) {\n+ printf(\"Dup bit_pos %d with pos_offset %d\\r\\n\", bit_pos, pos_offset);\n+ return -bit_pos;\n+ }\n+ ctx->bitmap.map64 |= (1 << pos_offset);//TODO use bytearray\n+\n+ for (i = 0; i < sizeof(ctx->bitmap.bytes) * 8; i++) {\n+ if (ctx->bitmap.map64 & 0x1) {\n+ ctx->bitmap.map64 >>= 1;\n+ ctx->ssn += 1;\n+ if (ctx->ssn == ctx->ssn_duration) {\n+ ctx->ssn = 0;\n+ }\n+ }\n+ }\n+ return pos_offset;\n+}\n+\n+uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx)\n+{\n+ return ctx->bitmap.map64;\n+}\n+\n+int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx)\n+{\n+ return ctx->ssn;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_crc.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_crc.c b/bsp/bl808/m0/libraries/utils/src/utils_crc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1b3e0fa4b1280c7c3ed0679f50ed316357fbc5c2\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_crc.c\n@@ -0,0 +1,223 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <utils_crc.h>\n+\n+// ---------------- POPULAR POLYNOMIALS ----------------\n+// CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000)\n+// CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF)\n+// we use 0x8005 here and\n+\n+static const uint8_t chCRCHTalbe[] =\n+{\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,\n+0x00, 0xC1, 0x81, 0x40\n+};\n+\n+static const uint8_t chCRCLTalbe[] =\n+{\n+0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,\n+0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,\n+0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,\n+0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,\n+0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,\n+0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,\n+0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,\n+0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,\n+0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,\n+0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,\n+0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,\n+0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,\n+0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,\n+0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,\n+0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,\n+0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,\n+0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,\n+0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,\n+0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,\n+0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,\n+0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,\n+0x41, 0x81, 0x80, 0x40\n+};\n+\n+uint16_t utils_crc16(void * dataIn, uint32_t len)\n+{\n+\tuint8_t chCRCHi = 0xFF;\n+\tuint8_t chCRCLo = 0xFF;\n+\tuint16_t wIndex;\n+ uint8_t* data=(uint8_t *) dataIn;\n+\n+\twhile (len--)\n+\t{\n+\t\twIndex = chCRCLo ^ *data++ ;\n+\t\tchCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];\n+\t\tchCRCHi = chCRCLTalbe[wIndex] ;\n+\t}\n+\n+\treturn ((chCRCHi << 8) | chCRCLo) ;\n+}\n+\n+/*\n+x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1\n+*/\n+static const uint32_t crc32Tab[256] = {\n+\t0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,\n+\t0xe963a535, 0x9e6495a3,\t0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,\n+\t0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,\n+\t0xf3b97148, 0x84be41de,\t0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,\n+\t0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,\t0x14015c4f, 0x63066cd9,\n+\t0xfa0f3d63, 0x8d080df5,\t0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,\n+\t0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,\t0x35b5a8fa, 0x42b2986c,\n+\t0xdbbbc9d6, 0xacbcf940,\t0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,\n+\t0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,\n+\t0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,\n+\t0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,\t0x76dc4190, 0x01db7106,\n+\t0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,\n+\t0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,\n+\t0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,\n+\t0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,\n+\t0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,\n+\t0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,\n+\t0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,\n+\t0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,\n+\t0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,\n+\t0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,\n+\t0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,\n+\t0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,\n+\t0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,\n+\t0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,\n+\t0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,\n+\t0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,\n+\t0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,\n+\t0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,\n+\t0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,\n+\t0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,\n+\t0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,\n+\t0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,\n+\t0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,\n+\t0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,\n+\t0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,\n+\t0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,\n+\t0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,\n+\t0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,\n+\t0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,\n+\t0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,\n+\t0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,\n+\t0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d\n+};\n+\n+uint32_t utils_crc32(void *dataIn, uint32_t len)\n+{\n+\tuint32_t crc=0;\n+ uint8_t *data=(uint8_t *)dataIn;\n+\n+\tcrc = crc ^ 0xffffffff;\n+\n+\twhile (len--)\n+\t\tcrc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8);\n+\n+\treturn crc ^ 0xffffffff;\n+}\n+\n+void utils_crc32_stream_init(struct crc32_stream_ctx *ctx)\n+{\n+ ctx->crc = 0xffffffff;\n+}\n+\n+void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data)\n+{\n+\tctx->crc = crc32Tab[(ctx->crc ^ data) & 0xFF] ^ (ctx->crc >> 8);\n+}\n+\n+void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len)\n+{\n+ while (len--)\n+\t ctx->crc = crc32Tab[(ctx->crc ^ *data++) & 0xFF] ^ (ctx->crc >> 8);\n+}\n+\n+uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx)\n+{\n+ return ctx->crc ^ 0xffffffff;\n+}\n+\n+#define POLY 0x8408\n+uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len)\n+{\n+ uint8_t *data_p=(uint8_t *)dataIn;\n+ uint8_t i;\n+ uint8_t data;\n+ uint16_t crc;\n+ \n+ crc = 0xFFFF;\n+ \n+ if (len == 0)\n+ return (~crc);\n+ \n+ do {\n+ for (i = 0, data = (unsigned int)0xff & *data_p++;\n+ i < 8;\n+ i++, data >>= 1) {\n+ if ((crc & 0x0001) ^ (data & 0x0001))\n+ crc = (crc >> 1) ^ POLY;\n+ else\n+ crc >>= 1;\n+ }\n+ } while (--len);\n+ \n+ crc = ~crc;\n+ \n+ data = crc;\n+ \n+ return (crc);\n+}\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_dns.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_dns.c b/bsp/bl808/m0/libraries/utils/src/utils_dns.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0228adb6621990a0886d83156dfdc29f884a52c8\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_dns.c\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <utils_dns.h>\n+\n+int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len)\n+{\n+ int i, pos_in, pos_out, size_buf;\n+\n+ size_buf = *len;\n+\n+ pos_in = 0;\n+ pos_out = 0;\n+ i = records[pos_in++];\n+ while (i > 0 && size_buf > 0) {\n+ buf[pos_out++] = records[pos_in++];\n+ i--;\n+ size_buf--;\n+\n+ if (0 == i && size_buf > 0) {\n+ /*current record is empty*/\n+ buf[pos_out++] = '.';\n+ i = records[pos_in++];\n+ }\n+ }\n+ *len = pos_out;\n+\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_fec.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_fec.c b/bsp/bl808/m0/libraries/utils/src/utils_fec.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..cc2efa4999f182323b3d0713a69e3171320b1b4c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_fec.c\n@@ -0,0 +1,880 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+#include <FreeRTOS.h>\n+#include <task.h>\n+#include \"utils_log.h\"\n+#include \"stdio.h\"\n+\n+#include \"utils_fec.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define MSG_CNT 3 /* message-length polynomials count */\n+#define POLY_CNT 14 /* (FEC_ECC_LENGTH*2)-length polynomialc count */\n+\n+typedef struct {\n+ uint8_t _id;\n+ uint8_t _size; /* Size of reserved memory for this polynomial */\n+ uint16_t _offset; /* Offset in memory */\n+ uint8_t* _memory; /* Pointer to pointer to memory */\n+ uint8_t length;\n+} blpoly_t;\n+\n+typedef struct {\n+ blpoly_t g_polynoms[MSG_CNT + POLY_CNT];\n+ uint8_t g_stack_memory[MSG_CNT * FEC_MSG_LENGTH + POLY_CNT * FEC_ECC_LENGTH * 2];\n+ uint8_t g_generator_cache[FEC_ECC_LENGTH + 1];\n+ uint8_t g_generator_cached_flag;/* false */\n+} fec_context_t;\n+\n+enum POLY_ID {\n+ ID_MSG_IN = 0,\n+ ID_MSG_OUT,\n+ ID_GENERATOR,\n+ ID_TPOLY1,\n+ ID_TPOLY2,\n+\n+ ID_MSG_E,\n+\n+ ID_TPOLY3,\n+ ID_TPOLY4,\n+\n+ ID_SYNDROMES,\n+ ID_FORNEY,\n+\n+ ID_ERASURES_LOC,\n+ ID_ERRORS_LOC,\n+\n+ ID_ERASURES,\n+ ID_ERRORS,\n+\n+ ID_COEF_POS,\n+ ID_ERR_EVAL\n+};\n+\n+/* GF tables pre-calculated for 0x11d primitive polynomial */\n+const uint8_t code_exp[512] = {\n+ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c,\n+ 0x98, 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d,\n+ 0x27, 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46,\n+ 0x8c, 0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f,\n+ 0xbe, 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd,\n+ 0xe7, 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9,\n+ 0xaf, 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81,\n+ 0x1f, 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85,\n+ 0x17, 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8,\n+ 0x4d, 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6,\n+ 0xd1, 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3,\n+ 0xdb, 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82,\n+ 0x19, 0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51,\n+ 0xa2, 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12,\n+ 0x24, 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c,\n+ 0x58, 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2,\n+ 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c, 0x98,\n+ 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d, 0x27,\n+ 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46, 0x8c,\n+ 0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f, 0xbe,\n+ 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd, 0xe7,\n+ 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9, 0xaf,\n+ 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81, 0x1f,\n+ 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85, 0x17,\n+ 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8, 0x4d,\n+ 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6, 0xd1,\n+ 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3, 0xdb,\n+ 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82, 0x19,\n+ 0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51, 0xa2,\n+ 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12, 0x24,\n+ 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c, 0x58,\n+ 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2\n+};\n+\n+const uint8_t code_log[256] = {\n+ 0x0, 0x0, 0x1, 0x19, 0x2, 0x32, 0x1a, 0xc6, 0x3, 0xdf, 0x33, 0xee, 0x1b, 0x68, 0xc7, 0x4b, 0x4,\n+ 0x64, 0xe0, 0xe, 0x34, 0x8d, 0xef, 0x81, 0x1c, 0xc1, 0x69, 0xf8, 0xc8, 0x8, 0x4c, 0x71, 0x5,\n+ 0x8a, 0x65, 0x2f, 0xe1, 0x24, 0xf, 0x21, 0x35, 0x93, 0x8e, 0xda, 0xf0, 0x12, 0x82, 0x45, 0x1d,\n+ 0xb5, 0xc2, 0x7d, 0x6a, 0x27, 0xf9, 0xb9, 0xc9, 0x9a, 0x9, 0x78, 0x4d, 0xe4, 0x72, 0xa6, 0x6,\n+ 0xbf, 0x8b, 0x62, 0x66, 0xdd, 0x30, 0xfd, 0xe2, 0x98, 0x25, 0xb3, 0x10, 0x91, 0x22, 0x88, 0x36,\n+ 0xd0, 0x94, 0xce, 0x8f, 0x96, 0xdb, 0xbd, 0xf1, 0xd2, 0x13, 0x5c, 0x83, 0x38, 0x46, 0x40, 0x1e,\n+ 0x42, 0xb6, 0xa3, 0xc3, 0x48, 0x7e, 0x6e, 0x6b, 0x3a, 0x28, 0x54, 0xfa, 0x85, 0xba, 0x3d, 0xca,\n+ 0x5e, 0x9b, 0x9f, 0xa, 0x15, 0x79, 0x2b, 0x4e, 0xd4, 0xe5, 0xac, 0x73, 0xf3, 0xa7, 0x57, 0x7,\n+ 0x70, 0xc0, 0xf7, 0x8c, 0x80, 0x63, 0xd, 0x67, 0x4a, 0xde, 0xed, 0x31, 0xc5, 0xfe, 0x18, 0xe3,\n+ 0xa5, 0x99, 0x77, 0x26, 0xb8, 0xb4, 0x7c, 0x11, 0x44, 0x92, 0xd9, 0x23, 0x20, 0x89, 0x2e, 0x37,\n+ 0x3f, 0xd1, 0x5b, 0x95, 0xbc, 0xcf, 0xcd, 0x90, 0x87, 0x97, 0xb2, 0xdc, 0xfc, 0xbe, 0x61, 0xf2,\n+ 0x56, 0xd3, 0xab, 0x14, 0x2a, 0x5d, 0x9e, 0x84, 0x3c, 0x39, 0x53, 0x47, 0x6d, 0x41, 0xa2, 0x1f,\n+ 0x2d, 0x43, 0xd8, 0xb7, 0x7b, 0xa4, 0x76, 0xc4, 0x17, 0x49, 0xec, 0x7f, 0xc, 0x6f, 0xf6, 0x6c,\n+ 0xa1, 0x3b, 0x52, 0x29, 0x9d, 0x55, 0xaa, 0xfb, 0x60, 0x86, 0xb1, 0xbb, 0xcc, 0x3e, 0x5a, 0xcb,\n+ 0x59, 0x5f, 0xb0, 0x9c, 0xa9, 0xa0, 0x51, 0xb, 0xf5, 0x16, 0xeb, 0x7a, 0x75, 0x2c, 0xd7, 0x4f,\n+ 0xae, 0xd5, 0xe9, 0xe6, 0xe7, 0xad, 0xe8, 0x74, 0xd6, 0xf4, 0xea, 0xa8, 0x50, 0x58, 0xaf\n+};\n+\n+void poly_init(blpoly_t *dev, uint8_t id, uint16_t offset, uint8_t size, uint8_t *memory_ptr)\n+{\n+ bl_assert(memory_ptr && dev);\n+\n+ dev->_id = id;\n+ dev->_size = size;\n+ dev->_offset = offset;\n+ dev->_memory = memory_ptr;\n+ dev->length = 0;\n+}\n+\n+uint8_t *poly_ptr(blpoly_t *dev)\n+{\n+ bl_assert(dev);\n+\n+ return (dev->_memory + dev->_offset);\n+}\n+\n+void poly_reset(blpoly_t *dev)\n+{\n+ bl_assert(dev->_memory && dev);\n+\n+ memset(poly_ptr(dev), 0, dev->_size);\n+}\n+\n+void poly_set(blpoly_t *dev, uint8_t* src, uint8_t len, uint8_t offset)/* offset=0 */\n+{\n+ bl_assert(src && len <= dev->_size - offset);\n+\n+ memcpy(poly_ptr(dev)+offset, src, len * sizeof(uint8_t));\n+\n+ dev->length = len + offset;\n+}\n+\n+uint8_t *poly_at(blpoly_t *dev, uint8_t i)\n+{\n+ uint8_t *pt;\n+\n+ bl_assert(dev);\n+\n+ pt = poly_ptr(dev);\n+\n+ return (pt + i);\n+}\n+\n+uint8_t poly_get_size(blpoly_t *dev)\n+{\n+ bl_assert(dev);\n+\n+ return dev->_size;\n+}\n+\n+uint8_t poly_get_id(blpoly_t *dev)\n+{\n+ bl_assert(dev);\n+\n+ return dev->_id;\n+}\n+\n+void poly_copy(blpoly_t *dev, blpoly_t *src)\n+{\n+ bl_assert(dev && src);\n+\n+ dev->length = ((dev->length) > (src->length) ? (dev->length) : (src->length));\n+ poly_set(dev, poly_ptr(src), dev->length, 0);\n+}\n+\n+uint8_t poly_append(blpoly_t *dev, uint8_t num)\n+{\n+ uint8_t *pt;\n+ bl_assert(dev->length + 1 < dev->_size);\n+\n+ pt = poly_ptr(dev);\n+ pt[dev->length++] = num;\n+\n+ return 1;/* true */\n+}\n+\n+/*****************************************************/\n+uint8_t gf_add(uint8_t x, uint8_t y)\n+{\n+ return x + y;\n+}\n+\n+uint8_t gf_sub(uint8_t x, uint8_t y)\n+{\n+ return x^y;\n+}\n+\n+uint8_t gf_mul(uint16_t x, uint16_t y)\n+{\n+ if (x == 0 || y == 0) {\n+ return 0;\n+ }\n+\n+ return code_exp[code_log[x] + code_log[y]];\n+}\n+\n+uint8_t gf_div(uint8_t x, uint8_t y)\n+{\n+ bl_assert(y != 0);\n+\n+ if (x == 0) {\n+ return 0;\n+ }\n+ return code_exp[(code_log[x] + 255 - code_log[y]) % 255];\n+}\n+\n+uint8_t gf_pow(uint8_t x, intmax_t power)\n+{\n+ intmax_t i = code_log[x];\n+\n+ i *= power;\n+ i %= 255;\n+\n+ if (i < 0) {\n+ i = i + 255;\n+ }\n+\n+ return code_exp[i];\n+}\n+\n+uint8_t gf_inverse(uint8_t x)\n+{\n+ return code_exp[255 - code_log[x]]; /* == div(1, x); */\n+}\n+\n+/* POLYNOMIALS OPERATIONS */\n+void poly_scale(blpoly_t *p, blpoly_t *newp, uint16_t x)\n+{\n+ uint16_t i;\n+\n+ newp->length = p->length;\n+ for (i = 0; i < p->length; i++)\n+ {\n+ *poly_at(newp, i) = gf_mul(*poly_at(p, i), x);\n+ }\n+}\n+\n+void poly_add(blpoly_t *p, blpoly_t *q, blpoly_t *newp)\n+{\n+ uint8_t i;\n+\n+ newp->length = ((p->length) > (q->length) ? (p->length) : (q->length));\n+ memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));\n+\n+ for (i = 0; i < p->length; i++)\n+ {\n+ *poly_at(newp, i + newp->length - p->length) = *poly_at(p, i);\n+ }\n+\n+ for (i = 0; i < q->length; i++)\n+ {\n+ *poly_at(newp, i + newp->length - q->length) ^= *poly_at(q, i);\n+ }\n+}\n+\n+void poly_mul(blpoly_t *p, blpoly_t *q, blpoly_t *newp)\n+{\n+ uint8_t i,j;\n+\n+ newp->length = p->length + q->length - 1;\n+ memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));\n+ /* Compute the polynomial multiplication (just like the outer product of two vectors,\n+ * we multiply each coefficients of p with all coefficients of q) */\n+ for (j = 0; j < q->length; j++) {\n+ for (i = 0; i < p->length; i++) {\n+ *poly_at(newp, i+j) ^= gf_mul(*poly_at(p, i), *poly_at(q, j)); /* == r[i + j] = gf_add(r[i+j], gf_mul(p[i], q[j])) */\n+ }\n+ }\n+}\n+\n+void poly_div(blpoly_t *p, blpoly_t *q, blpoly_t *newp)\n+{\n+ uint8_t coef;\n+ unsigned long sep;\n+ long i;\n+\n+ if (poly_ptr(p) != poly_ptr(newp)) {\n+ memcpy(poly_ptr(newp), poly_ptr(p), p->length*sizeof(uint8_t));\n+ }\n+\n+ newp->length = p->length;\n+\n+ for (i = 0; i < (p->length-(q->length-1)); i++) {\n+ coef = *poly_at(newp, i);\n+ if (coef != 0) {\n+ for (uint8_t j = 1; j < q->length; j++) {\n+ if (*poly_at(q, j) != 0) {\n+ *poly_at(newp, i+j) ^= gf_mul(*poly_at(q, j), coef);\n+ }\n+ }\n+ }\n+ }\n+\n+ sep = p->length-(q->length-1);\n+ memmove(poly_ptr(newp), poly_ptr(newp)+sep, (newp->length-sep) * sizeof(uint8_t));\n+ newp->length = newp->length-sep;\n+}\n+\n+int8_t poly_eval(blpoly_t *p, uint16_t x)\n+{\n+ uint8_t y = *poly_at(p, 0);\n+\n+ for (uint8_t i = 1; i < p->length; i++)\n+ {\n+ y = gf_mul(y, x) ^ (*poly_at(p, i));\n+ }\n+ return y;\n+}\n+\n+/*****************************************************/\n+void generator_poly(fec_context_t *context)\n+{\n+ uint8_t i;\n+ blpoly_t *gen = context->g_polynoms + ID_GENERATOR;\n+ blpoly_t *mulp = context->g_polynoms + ID_TPOLY1;\n+ blpoly_t *temp = context->g_polynoms + ID_TPOLY2;\n+\n+ *poly_at(gen, 0) = 1;\n+ gen->length = 1;\n+\n+ mulp->length = 2;\n+\n+ for (i = 0; i < FEC_ECC_LENGTH; i++)\n+ {\n+ *poly_at(mulp, 0) = 1;\n+ *poly_at(mulp, 1) = gf_pow(2, i);\n+\n+ poly_mul(gen, mulp, temp);\n+ poly_copy(gen, temp);\n+ }\n+}\n+\n+void calc_syndromes(fec_context_t *context, blpoly_t *msg)\n+{\n+ uint8_t i;\n+ blpoly_t *synd = &context->g_polynoms[ID_SYNDROMES];\n+\n+ synd->length = FEC_ECC_LENGTH + 1;\n+ *poly_at(synd, 0) = 0;\n+\n+ for (i = 1; i < FEC_ECC_LENGTH + 1; i++)\n+ {\n+ *poly_at(synd, i) = poly_eval(msg, gf_pow(2, i - 1));\n+ }\n+}\n+\n+void find_errata_locator(fec_context_t *context, blpoly_t *epos)\n+{\n+ blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];\n+ blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];\n+ blpoly_t *addp = &context->g_polynoms[ID_TPOLY2];\n+ blpoly_t *apol = &context->g_polynoms[ID_TPOLY3];\n+ blpoly_t *temp = &context->g_polynoms[ID_TPOLY4];\n+\n+ errata_loc->length = 1;\n+ *poly_at(errata_loc, 0) = 1;\n+\n+ mulp->length = 1;\n+ addp->length = 2;\n+\n+ for (uint8_t i = 0; i < epos->length; i++)\n+ {\n+ *poly_at(mulp, 0) = 1;\n+ *poly_at(addp, 0) = gf_pow(2, *poly_at(epos , i));\n+ *poly_at(addp, 1) = 0;\n+\n+ poly_add(mulp, addp, apol);\n+ poly_mul(errata_loc, apol, temp);\n+\n+ poly_copy(errata_loc, temp);\n+ }\n+}\n+\n+void find_error_evaluator(fec_context_t *context, blpoly_t *synd, blpoly_t *errata_loc, blpoly_t *dst, uint8_t ecclen)\n+{\n+ blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];\n+ poly_mul(synd, errata_loc, mulp);\n+\n+ blpoly_t *divisor = &context->g_polynoms[ID_TPOLY2];\n+ divisor->length = ecclen + 2;\n+\n+ poly_reset(divisor);\n+ *poly_at(divisor, 0) = 1;\n+\n+ poly_div(mulp, divisor, dst);\n+}\n+\n+void correct_errata(fec_context_t *context, blpoly_t *synd, blpoly_t *err_pos, blpoly_t *msg_in)\n+{\n+ uint8_t i;\n+ int8_t s_i;\n+ int16_t l;\n+ uint8_t Xi_inv;\n+ uint8_t err_loc_prime;\n+ uint8_t y;\n+ uint8_t j;\n+\n+ blpoly_t *c_pos = &context->g_polynoms[ID_COEF_POS];\n+ blpoly_t *corrected = &context->g_polynoms[ID_MSG_OUT];\n+ blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];\n+ blpoly_t *rsynd = &context->g_polynoms[ID_TPOLY3];\n+ blpoly_t *re_eval = &context->g_polynoms[ID_TPOLY4];\n+ blpoly_t *e_eval = &context->g_polynoms[ID_ERR_EVAL];\n+ blpoly_t *X = &context->g_polynoms[ID_TPOLY1]; /* this will store errors positions */\n+ blpoly_t *E = &context->g_polynoms[ID_MSG_E];\n+ blpoly_t *err_loc_prime_temp = &context->g_polynoms[ID_TPOLY2];\n+\n+ c_pos->length = err_pos->length;\n+\n+ for (i = 0; i < err_pos->length; i++)\n+ *poly_at(c_pos, i) = msg_in->length - 1 - *poly_at(err_pos, i);\n+\n+ /* uses t_poly 1, 2, 3, 4 */\n+ find_errata_locator(context, c_pos);\n+\n+\n+ /* reversing syndromes */\n+ rsynd->length = synd->length;\n+\n+ for (s_i = synd->length-1, j = 0; s_i >= 0; s_i--, j++)\n+ {\n+ *poly_at(rsynd, j) = *poly_at(synd, s_i);\n+ }\n+\n+ /* getting reversed error evaluator polynomial */\n+\n+ /* uses T_POLY 1, 2 */\n+ find_error_evaluator(context, rsynd, errata_loc, re_eval, errata_loc->length-1);\n+\n+ /* reversing it back */\n+ e_eval->length = re_eval->length;\n+ for (s_i = re_eval->length-1, j = 0; s_i >= 0; s_i--, j++)\n+ {\n+ *poly_at(e_eval, j) = *poly_at(re_eval, s_i);\n+ }\n+\n+\n+ X->length = 0;\n+\n+ for (i = 0; i < c_pos->length; i++)\n+ {\n+ l = 255 - *poly_at(c_pos, i);\n+ poly_append(X, gf_pow(2, -l));\n+ }\n+\n+ /* Magnitude polynomial\n+ Shit just got real */\n+ poly_reset(E);\n+ E->length = msg_in->length;\n+\n+\n+ for (i = 0; i < X->length; i++) {\n+ Xi_inv = gf_inverse(*poly_at(X, i));\n+\n+ err_loc_prime_temp->length = 0;\n+ for (j = 0; j < X->length; j++) {\n+ if (j != i) {\n+ poly_append(err_loc_prime_temp, gf_sub(1, gf_mul(Xi_inv, *poly_at(X, j))));\n+ }\n+ }\n+\n+ err_loc_prime = 1;\n+ for (j = 0; j < err_loc_prime_temp->length; j++) {\n+ err_loc_prime = gf_mul(err_loc_prime, *poly_at(err_loc_prime_temp, j));\n+ }\n+\n+ y = poly_eval(re_eval, Xi_inv);\n+ y = gf_mul(gf_pow(*poly_at(X, i), 1), y);\n+\n+ *poly_at(E, *poly_at(err_pos, i)) = gf_div(y, err_loc_prime);\n+ }\n+\n+ poly_add(msg_in, E, corrected);\n+}\n+\n+uint8_t find_error_locator(fec_context_t *context, blpoly_t *synd, blpoly_t *erase_loc, unsigned long erase_count)\n+{\n+ uint8_t i;\n+ uint8_t synd_shift = 0;\n+ uint8_t K = 0;\n+ uint8_t delta = 0;\n+ uint8_t index;\n+ uint8_t j;\n+ uint32_t shift = 0;\n+ uint32_t errs;\n+\n+ blpoly_t *error_loc = &context->g_polynoms[ID_ERRORS_LOC];\n+ blpoly_t *err_loc = &context->g_polynoms[ID_TPOLY1];\n+ blpoly_t *old_loc = &context->g_polynoms[ID_TPOLY2];\n+ blpoly_t *temp = &context->g_polynoms[ID_TPOLY3];\n+ blpoly_t *temp2 = &context->g_polynoms[ID_TPOLY4];\n+\n+ if (erase_loc != NULL) {\n+ poly_copy(err_loc, erase_loc);\n+ poly_copy(old_loc, erase_loc);\n+ } else {\n+ err_loc->length = 1;\n+ old_loc->length = 1;\n+ *poly_at(err_loc, 0) = 1;\n+ *poly_at(old_loc, 0) = 1;\n+ }\n+\n+\n+ if (synd->length > FEC_ECC_LENGTH) {\n+ synd_shift = synd->length - FEC_ECC_LENGTH;\n+ }\n+\n+ for (i = 0; i < FEC_ECC_LENGTH - erase_count; i++)\n+ {\n+ if (erase_loc != NULL) {\n+ K = erase_count + i + synd_shift;\n+ } else {\n+ K = i + synd_shift;\n+ }\n+\n+ delta = *poly_at(synd, K);\n+ for (j = 1; j < err_loc->length; j++) {\n+ index = err_loc->length - j - 1;\n+ delta ^= gf_mul(*poly_at(err_loc, index), *poly_at(synd, K-j));\n+ }\n+\n+ poly_append(old_loc, 0);\n+\n+ if (delta != 0) {\n+ if (old_loc->length > err_loc->length) {\n+ poly_scale(old_loc, temp, delta);\n+ poly_scale(err_loc, old_loc, gf_inverse(delta));\n+ poly_copy(err_loc, temp);\n+ }\n+ poly_scale(old_loc, temp, delta);\n+ poly_add(err_loc, temp, temp2);\n+ poly_copy(err_loc, temp2);\n+ }\n+ }\n+\n+ while(err_loc->length && *poly_at(err_loc, shift) == 0) shift++;\n+\n+ errs = err_loc->length - shift - 1;\n+ if (((errs - erase_count) * 2 + erase_count) > FEC_ECC_LENGTH) {\n+ return 0;/* false */ /* Error count is greater then we can fix! */\n+ }\n+\n+ memcpy(poly_ptr(error_loc), poly_ptr(err_loc) + shift, (err_loc->length - shift) * sizeof(uint8_t));\n+ error_loc->length = (err_loc->length - shift);\n+ return 1;/* true */\n+}\n+\n+uint8_t find_errors(fec_context_t *context, blpoly_t *error_loc, unsigned long msg_in_size)\n+{\n+ uint8_t i;\n+\n+ blpoly_t *err = &context->g_polynoms[ID_ERRORS];\n+ uint8_t errs = error_loc->length - 1;\n+\n+ err->length = 0;\n+\n+ for (i = 0; i < msg_in_size; i++)\n+ {\n+ if (poly_eval(error_loc, gf_pow(2, i)) == 0)\n+ {\n+ poly_append(err, msg_in_size - 1 - i);\n+ }\n+ }\n+\n+ /* Sanity check:\n+ * the number of err/errata positions found\n+ * should be exactly the same as the length of the errata locator polynomial */\n+ if (err->length != errs) {\n+ /* couldn't find error locations */\n+ return 0;/* false */\n+ }\n+\n+ return 1;/* true */\n+}\n+\n+void calc_forney_syndromes(fec_context_t *context, blpoly_t *synd, blpoly_t *erasures_pos, unsigned long msg_in_size)\n+{\n+ uint8_t i;\n+ uint8_t x;\n+ uint8_t j;\n+\n+ blpoly_t *erase_pos_reversed = &context->g_polynoms[ID_TPOLY1];\n+ blpoly_t *forney_synd = &context->g_polynoms[ID_FORNEY];\n+\n+ erase_pos_reversed->length = 0;\n+\n+ for (i = 0; i < erasures_pos->length; i++)\n+ {\n+ poly_append(erase_pos_reversed, msg_in_size - 1 - *poly_at(erasures_pos, i));\n+ }\n+\n+ poly_reset(forney_synd);\n+ poly_set(forney_synd, poly_ptr(synd)+1, synd->length-1, 0);\n+\n+ for (i = 0; i < erasures_pos->length; i++)\n+ {\n+ x = gf_pow(2, *poly_at(erase_pos_reversed, i));\n+ for (j = 0; j < forney_synd->length - 1; j++)\n+ {\n+ *poly_at(forney_synd, j) = gf_mul(*poly_at(forney_synd, j), x) ^ *poly_at(forney_synd, j+1);\n+ }\n+ }\n+}\n+\n+void reedsolomon_init(void *context)\n+{\n+ fec_context_t *p = (fec_context_t *)context;\n+ uint16_t offset = 0;\n+ uint8_t i;\n+ uint8_t enc_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;\n+ uint8_t poly_len = FEC_ECC_LENGTH * 2;\n+\n+ bl_assert(p);\n+\n+ log_info(\"reedsolomon_init.\\r\\n\");\n+\n+ poly_init(&p->g_polynoms[0], ID_MSG_IN, offset, enc_len, p->g_stack_memory);\n+ offset += enc_len;\n+\n+ poly_init(&p->g_polynoms[1], ID_MSG_OUT, offset, enc_len, p->g_stack_memory);\n+ offset += enc_len;\n+\n+ for (i = ID_GENERATOR; i < ID_MSG_E; i++)\n+ {\n+ poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);\n+ offset += poly_len;\n+ }\n+\n+ poly_init(&p->g_polynoms[5], ID_MSG_E, offset, enc_len, p->g_stack_memory);\n+ offset += enc_len;\n+\n+ for (i = ID_TPOLY3; i < ID_ERR_EVAL+2; i++)\n+ {\n+ poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);\n+ offset += poly_len;\n+ }\n+}\n+\n+void encode_block(fec_context_t *context, void *src, void *dst)\n+{\n+ /* Generator cache, it dosn't change for one template parameters */\n+\n+ uint8_t coef = 0; /* cache */\n+ uint8_t i;\n+ uint32_t j;\n+\n+ uint8_t* src_ptr = (uint8_t*) src;\n+ uint8_t* dst_ptr = (uint8_t*) dst;\n+\n+ blpoly_t *msg_in = &context->g_polynoms[ID_MSG_IN];\n+ blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];\n+ blpoly_t *gen = &context->g_polynoms[ID_GENERATOR];\n+\n+ bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);\n+\n+ poly_reset(msg_in);\n+ poly_reset(msg_out);\n+\n+ if (context->g_generator_cached_flag) {\n+ poly_set(gen, context->g_generator_cache, (FEC_ECC_LENGTH + 1), 0);\n+ } else {\n+ generator_poly(context);\n+ memcpy(context->g_generator_cache, poly_ptr(gen), gen->length);\n+ context->g_generator_cached_flag = 1;/* true */\n+ }\n+\n+ /* Copying input message to internal polynomial */\n+ poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);\n+ poly_set(msg_out, src_ptr, FEC_MSG_LENGTH, 0);\n+ msg_out->length = msg_in->length + FEC_ECC_LENGTH;\n+\n+ /* Here all the magic happens */\n+\n+ for (i = 0; i < FEC_MSG_LENGTH; i++) {\n+ coef = *poly_at(msg_out, i);\n+ if (coef != 0) {\n+ for (j = 1; j < gen->length; j++) {\n+ *poly_at(msg_out, i+j) ^= gf_mul(*poly_at(gen, j), coef);\n+ }\n+ }\n+ }\n+\n+ /* Copying ECC to the output buffer */\n+ memcpy(dst_ptr, poly_ptr(msg_out)+FEC_MSG_LENGTH, FEC_ECC_LENGTH * sizeof(uint8_t));\n+\n+}\n+\n+void reedsolomon_encode(void *context, void* src, void* dst)\n+{\n+ fec_context_t *p = (fec_context_t *)context;\n+ uint8_t* dst_ptr = (uint8_t*) dst;\n+\n+ /* Copying message to the output buffer */\n+ memcpy(dst_ptr, src, FEC_MSG_LENGTH * sizeof(uint8_t));\n+\n+ /* Calling EncodeBlock to write ecc to out[ut buffer */\n+ encode_block(p, src, dst_ptr+FEC_MSG_LENGTH);\n+}\n+\n+char decode_block(fec_context_t *context, void* src, const void* ecc, void* dst, uint8_t* erase_pos, unsigned long erase_count)\n+{\n+ uint8_t i, j;\n+ int8_t s_i;\n+ bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);\n+\n+ uint8_t *src_ptr = (uint8_t*) src;\n+ uint8_t *ecc_ptr = (uint8_t*) ecc;\n+ uint8_t *dst_ptr = (uint8_t*) dst;\n+\n+ uint8_t src_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;\n+ uint8_t dst_len = FEC_MSG_LENGTH;\n+\n+ uint8_t ok;\n+\n+ blpoly_t *msg_in = &context->g_polynoms[ID_MSG_IN];\n+ blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];\n+ blpoly_t *epos = &context->g_polynoms[ID_ERASURES];\n+ blpoly_t *synd = &context->g_polynoms[ID_SYNDROMES];\n+ blpoly_t *eloc = &context->g_polynoms[ID_ERRORS_LOC];\n+ blpoly_t *reloc = &context->g_polynoms[ID_TPOLY1];\n+ blpoly_t *err = &context->g_polynoms[ID_ERRORS];\n+ blpoly_t *forney = &context->g_polynoms[ID_FORNEY];\n+\n+ uint8_t has_errors;\n+\n+ /* Copying message to polynomials memory */\n+ poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);\n+ poly_set(msg_in, ecc_ptr, FEC_ECC_LENGTH, FEC_MSG_LENGTH);\n+ poly_copy(msg_out, msg_in);\n+\n+ /* Copying known errors to polynomial */\n+ if (erase_pos == NULL) {\n+ epos->length = 0;\n+ } else {\n+ poly_set(epos, erase_pos, (uint8_t)erase_count, 0);\n+ for (i = 0; i < epos->length; i++){\n+ *poly_at(msg_in, *poly_at(epos, i)) = 0;\n+ }\n+ }\n+\n+ /* Too many errors */\n+ if (epos->length > FEC_ECC_LENGTH) return 1;\n+\n+\n+ /* Calculating syndrome */\n+ calc_syndromes(context, msg_in);\n+\n+ /* Checking for errors */\n+ has_errors = 0;/* false */\n+ for (i = 0; i < synd->length; i++) {\n+ if (*poly_at(synd, i) != 0) {\n+ has_errors = 1;/* true */\n+ break;\n+ }\n+ }\n+\n+ /* Going to exit if no errors */\n+ if (!has_errors) {\n+ goto return_corrected_msg;\n+ }\n+\n+ calc_forney_syndromes(context, synd, epos, src_len);\n+ find_error_locator(context, forney, NULL, epos->length);\n+\n+ /*\n+ Reversing syndrome\n+ TODO optimize through special Poly flag\n+ */\n+ reloc->length = eloc->length;\n+\n+ for (s_i = eloc->length-1, j = 0; s_i >= 0; s_i--, j++) {\n+ *poly_at(reloc, j) = *poly_at(eloc, s_i);\n+ }\n+\n+ /* Fing errors */\n+ ok = find_errors(context, reloc, src_len);\n+ if (!ok) {\n+ return 1;\n+ }\n+\n+ /* Error happened while finding errors (so helpfull :D) */\n+ if (err->length == 0) {\n+ return 1;\n+ }\n+\n+ /* Adding found errors with known */\n+ for (uint8_t i = 0; i < err->length; i++) {\n+ poly_append(epos, *poly_at(err, i));\n+ }\n+\n+ /* Correcting errors */\n+ correct_errata(context, synd, epos, msg_in);\n+\n+return_corrected_msg:\n+ /* Wrighting corrected message to output buffer */\n+ msg_out->length = dst_len;\n+ memcpy(dst_ptr, poly_ptr(msg_out), msg_out->length * sizeof(uint8_t));\n+ return 0;\n+}\n+\n+/*\n+ old:\n+ reedsolomon_decode(void *context, void* src, void* dst, uint8_t* erase_pos, uint32_t erase_count)\n+ return decode_block(p, src, ecc_ptr, dst, erase_pos, erase_count);\n+*/\n+char reedsolomon_decode(void *context, void* src, void* dst)\n+{\n+ fec_context_t *p = (fec_context_t *)context;\n+ uint8_t *src_ptr = (uint8_t*) src;\n+ uint8_t *ecc_ptr = src_ptr + FEC_MSG_LENGTH;\n+\n+ return decode_block(p, src, ecc_ptr, dst, 0, 0);\n+}\n+\n+/* which compiles with no warnings, and produces no code. */\n+#define BUILD_BUG_ON(condition) ((void)sizeof(char [1 - 2 * !!(condition)]))\n+int reedsolomon_getmemsize(void)\n+{\n+ /*\n+ which compiles with no warnings, and produces no code.\n+ err ? too waste mem ? pleas set fec_t.dummy size to (sizeof(fec_context_t)/sizeof(int) + 1)!\n+ */\n+ BUILD_BUG_ON((sizeof(fec_t) - sizeof(fec_context_t) > 512) ||\n+ (sizeof(fec_t) - sizeof(fec_context_t) < 0));\n+\n+ log_info(\"sizeof(fec_t) = %d sizeof(fec_context_t) = %d\\r\\n\", sizeof(fec_t), sizeof(fec_context_t));\n+ return (int)sizeof(fec_context_t);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+\n+\n+\n+\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_getopt.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_getopt.c b/bsp/bl808/m0/libraries/utils/src/utils_getopt.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7e91ebc7032c0a694be5960f774b158b91880da1\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_getopt.c\n@@ -0,0 +1,142 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdio.h>\n+#include <utils_getopt.h>\n+\n+/*\n+ * This file is derived from musl v1.2.0.\n+ * Modifications are applied.\n+ * Copyright (C) Bouffalo Lab 2016-2020\n+ */\n+\n+/*\n+ * Copyright © 2005-2020 Rich Felker, et al.\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining\n+ * a copy of this software and associated documentation files (the\n+ * \"Software\"), to deal in the Software without restriction, including\n+ * without limitation the rights to use, copy, modify, merge, publish,\n+ * distribute, sublicense, and/or sell copies of the Software, and to\n+ * permit persons to whom the Software is furnished to do so, subject to\n+ * the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be\n+ * included in all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\n+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\n+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\n+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+int utils_getopt_init(getopt_env_t *env, int opterr)\n+{\n+ if (!env) {\n+ return -1;\n+ }\n+ env->optarg = NULL;\n+ env->optind = 1;\n+ env->opterr = opterr;\n+ env->optopt = 0;\n+ env->__optpos = 0;\n+ return 0;\n+}\n+\n+#define NEWLINE \"\\r\\n\"\n+\n+int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring)\n+{\n+ int i;\n+ char c, d;\n+ char *optchar;\n+\n+ if (!env) {\n+ return -1;\n+ }\n+\n+ if (env->optind >= argc || !argv[env->optind])\n+ return -1;\n+\n+ if (argv[env->optind][0] != '-') {\n+ if (optstring[0] == '-') {\n+ env->optarg = argv[env->optind++];\n+ return 1;\n+ }\n+ return -1;\n+ }\n+\n+ if (!argv[env->optind][1])\n+ return -1;\n+\n+ if (argv[env->optind][1] == '-' && !argv[env->optind][2])\n+ return env->optind++, -1;\n+\n+ if (!env->__optpos) env->__optpos++;\n+ c = argv[env->optind][env->__optpos];\n+ optchar = argv[env->optind] + env->__optpos;\n+ env->__optpos += !!c;\n+\n+ if (!argv[env->optind][env->__optpos]) {\n+ env->optind++;\n+ env->__optpos = 0;\n+ }\n+\n+ if (optstring[0] == '-' || optstring[0] == '+')\n+ optstring++;\n+\n+ i = 0;\n+ do d = optstring[i++]; while (d && d != c);\n+\n+ if (d != c || c == ':') {\n+ env->optopt = c;\n+ if (optstring[0] != ':' && env->opterr)\n+ printf(\"%s: unrecognized option: %c\"NEWLINE, argv[0], *optchar);\n+ return '?';\n+ }\n+ if (optstring[i] == ':') {\n+ env->optarg = 0;\n+ if (optstring[i+1] != ':' || env->__optpos) {\n+ env->optarg = argv[env->optind++] + env->__optpos;\n+ env->__optpos = 0;\n+ }\n+ if (env->optind > argc) {\n+ env->optopt = c;\n+ if (optstring[0] == ':') return ':';\n+ if (env->opterr) {\n+ printf(\"%s: option requires an argument: %c\"NEWLINE, argv[0], *optchar);\n+ }\n+ return '?';\n+ }\n+ }\n+ return c;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_hex.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_hex.c b/bsp/bl808/m0/libraries/utils/src/utils_hex.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..377cebabf2a1150ad9eb2fb8bd72435049fbcaad\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_hex.c\n@@ -0,0 +1,104 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <stddef.h>\n+#include <utils_hex.h>\n+\n+const char hex_asc[] = \"0123456789abcdef\";\n+const char hex_asc_upper[] = \"0123456789ABCDEF\";\n+#define hex_asc_lo(x) hex_asc_upper[((x) & 0x0f)]\n+#define hex_asc_hi(x) hex_asc_upper[((x) & 0xf0) >> 4]\n+\n+static inline char *hex_byte_pack(char *buf, uint8_t byte)\n+{\n+ *buf++ = hex_asc_hi(byte);\n+ *buf++ = hex_asc_lo(byte);\n+ return buf;\n+}\n+\n+static int char2hex(char c, uint8_t *x)\n+{\n+\tif (c >= '0' && c <= '9') {\n+\t\t*x = c - '0';\n+\t} else if (c >= 'a' && c <= 'f') {\n+\t\t*x = c - 'a' + 10;\n+\t} else if (c >= 'A' && c <= 'F') {\n+\t\t*x = c - 'A' + 10;\n+\t} else {\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+char *utils_bin2hex(char *dst, const void *src, size_t count)\n+{\n+ const unsigned char *_src = src;\n+\n+ while (count--) {\n+ dst = hex_byte_pack(dst, *_src++);\n+ }\n+\n+ return dst;\n+}\n+\n+size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen)\n+{\n+\tuint8_t dec;\n+\n+\tif (buflen < hexlen / 2 + hexlen % 2) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* if hexlen is uneven, insert leading zero nibble */\n+\tif (hexlen % 2) {\n+\t\tif (char2hex(hex[0], &dec) < 0) {\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbuf[0] = dec;\n+\t\thex++;\n+\t\tbuf++;\n+\t}\n+\n+\t/* regular hex conversion */\n+\tfor (size_t i = 0; i < hexlen / 2; i++) {\n+\t\tif (char2hex(hex[2 * i], &dec) < 0) {\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbuf[i] = dec << 4;\n+\n+\t\tif (char2hex(hex[2 * i + 1], &dec) < 0) {\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbuf[i] += dec;\n+\t}\n+\n+\treturn hexlen / 2 + hexlen % 2;\n+}\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_hexdump.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c b/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..e76e3ca16856d9ee1ec9d0a604618e7b05e17b98\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c\n@@ -0,0 +1,77 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdio.h>\n+#include <ctype.h>\n+\n+#include <utils_hexdump.h>\n+\n+#ifndef HEXDUMP_COLS\n+#define HEXDUMP_COLS 16\n+#endif\n+//FIXME fix putchar\n+extern int bl_putchar(int c);\n+ \n+void utils_hexdump(void *mem, unsigned int len)\n+{\n+ unsigned int i, j;\n+\n+ for (i = 0; i < len + ((len % HEXDUMP_COLS) ? (HEXDUMP_COLS - len % HEXDUMP_COLS) : 0); i++) {\n+ /* print offset */\n+ if (i % HEXDUMP_COLS == 0) {\n+ printf(\"0x%06x: \", i);\n+ }\n+\n+ /* print hex data */\n+ if (i < len) {\n+ printf(\"%02x \", 0xFF & ((char*)mem)[i]);\n+ } else {\n+ /* end of block, just aligning for ASCII dump */\n+ printf(\" \");\n+ }\n+\n+ /* print ASCII dump */\n+ if (i % HEXDUMP_COLS == (HEXDUMP_COLS - 1)) {\n+ for (j = i - (HEXDUMP_COLS - 1); j <= i; j++) {\n+ if (j >= len) {\n+ /* end of block, not really printing */\n+ bl_putchar(' ');\n+ } else if(isprint((int)((char*)mem)[j])) {\n+ /* printable char */\n+ bl_putchar(0xFF & ((char*)mem)[j]);\n+ } else {\n+ /* other char */\n+ bl_putchar('.');\n+ }\n+ }\n+ puts(\"\\r\\n\");\n+ }\n+ }\n+}\n+ \n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_hmac.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ce763397aabca0fa6e729acdf0f31b335722e387\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_hmac.c\n@@ -0,0 +1,239 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <string.h>\n+#include \"iotx_utils_internal.h\"\n+#include \"utils_md5.h\"\n+#include \"utils_sha1.h\"\n+#include \"utils_sha256.h\"\n+#include \"utils_hmac.h\"\n+#include \"utils_base64.h\"\n+\n+#ifdef UTILS_MD5\n+void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len)\n+{\n+ if ((NULL == msg) || (NULL == digest) || (NULL == key)) {\n+ utils_err(\"parameter is Null,failed!\");\n+ return;\n+ }\n+\n+ if (key_len > KEY_IOPAD_SIZE) {\n+ utils_err(\"key_len > size(%d) of array\", KEY_IOPAD_SIZE);\n+ return;\n+ }\n+\n+ iot_md5_context context;\n+ unsigned char k_ipad[KEY_IOPAD_SIZE]; /* inner padding - key XORd with ipad */\n+ unsigned char k_opad[KEY_IOPAD_SIZE]; /* outer padding - key XORd with opad */\n+ unsigned char out[MD5_DIGEST_SIZE];\n+ int i;\n+\n+ /* start out by storing key in pads */\n+ memset(k_ipad, 0, sizeof(k_ipad));\n+ memset(k_opad, 0, sizeof(k_opad));\n+ memcpy(k_ipad, key, key_len);\n+ memcpy(k_opad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < KEY_IOPAD_SIZE; i++) {\n+ k_ipad[i] ^= 0x36;\n+ k_opad[i] ^= 0x5c;\n+ }\n+\n+ /* perform inner MD5 */\n+ utils_md5_init(&context); /* init context for 1st pass */\n+ utils_md5_starts(&context); /* setup context for 1st pass */\n+ utils_md5_update(&context, k_ipad, KEY_IOPAD_SIZE); /* start with inner pad */\n+ utils_md5_update(&context, (unsigned char *) msg, msg_len); /* then text of datagram */\n+ utils_md5_finish(&context, out); /* finish up 1st pass */\n+\n+ /* perform outer MD5 */\n+ utils_md5_init(&context); /* init context for 2nd pass */\n+ utils_md5_starts(&context); /* setup context for 2nd pass */\n+ utils_md5_update(&context, k_opad, KEY_IOPAD_SIZE); /* start with outer pad */\n+ utils_md5_update(&context, out, MD5_DIGEST_SIZE); /* then results of 1st hash */\n+ utils_md5_finish(&context, out); /* finish up 2nd pass */\n+\n+ for (i = 0; i < MD5_DIGEST_SIZE; ++i) {\n+ digest[i * 2] = utils_hb2hex(out[i] >> 4);\n+ digest[i * 2 + 1] = utils_hb2hex(out[i]);\n+ }\n+}\n+#endif /* #ifdef UTILS_MD5 */\n+\n+#ifdef UTILS_SHA256\n+void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len)\n+{\n+ if ((NULL == msg) || (NULL == digest) || (NULL == key)) {\n+ utils_err(\"parameter is Null,failed!\");\n+ return;\n+ }\n+\n+ if (key_len > KEY_IOPAD_SIZE) {\n+ utils_err(\"key_len > size(%d) of array\", KEY_IOPAD_SIZE);\n+ return;\n+ }\n+\n+ iot_sha256_context context;\n+ unsigned char k_ipad[KEY_IOPAD_SIZE]; /* inner padding - key XORd with ipad */\n+ unsigned char k_opad[KEY_IOPAD_SIZE]; /* outer padding - key XORd with opad */\n+ unsigned char out[SHA256_DIGEST_SIZE];\n+ int i;\n+\n+ /* start out by storing key in pads */\n+ memset(k_ipad, 0, sizeof(k_ipad));\n+ memset(k_opad, 0, sizeof(k_opad));\n+ memcpy(k_ipad, key, key_len);\n+ memcpy(k_opad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < KEY_IOPAD_SIZE; i++) {\n+ k_ipad[i] ^= 0x36;\n+ k_opad[i] ^= 0x5c;\n+ }\n+\n+ /* perform inner SHA */\n+ utils_sha256_init(&context); /* init context for 1st pass */\n+ utils_sha256_starts(&context); /* setup context for 1st pass */\n+ utils_sha256_update(&context, k_ipad, KEY_IOPAD_SIZE); /* start with inner pad */\n+ utils_sha256_update(&context, (unsigned char *) msg, msg_len); /* then text of datagram */\n+ utils_sha256_finish(&context, out); /* finish up 1st pass */\n+\n+ /* perform outer SHA */\n+ utils_sha256_init(&context); /* init context for 2nd pass */\n+ utils_sha256_starts(&context); /* setup context for 2nd pass */\n+ utils_sha256_update(&context, k_opad, KEY_IOPAD_SIZE); /* start with outer pad */\n+ utils_sha256_update(&context, out, SHA256_DIGEST_SIZE); /* then results of 1st hash */\n+ utils_sha256_finish(&context, out); /* finish up 2nd pass */\n+\n+ for (i = 0; i < SHA256_DIGEST_SIZE; ++i) {\n+ digest[i * 2] = utils_hb2hex(out[i] >> 4);\n+ digest[i * 2 + 1] = utils_hb2hex(out[i]);\n+ }\n+}\n+#endif /* #ifdef UTILS_SHA256 */\n+\n+#ifdef UTILS_SHA1\n+void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len)\n+{\n+ if ((NULL == msg) || (NULL == digest) || (NULL == key)) {\n+ utils_err(\"parameter is Null,failed!\");\n+ return;\n+ }\n+\n+ if (key_len > KEY_IOPAD_SIZE) {\n+ utils_err(\"key_len > size(%d) of array\", KEY_IOPAD_SIZE);\n+ return;\n+ }\n+\n+ iot_sha1_context context;\n+ unsigned char k_ipad[KEY_IOPAD_SIZE]; /* inner padding - key XORd with ipad */\n+ unsigned char k_opad[KEY_IOPAD_SIZE]; /* outer padding - key XORd with opad */\n+ unsigned char out[SHA1_DIGEST_SIZE];\n+ int i;\n+\n+ /* start out by storing key in pads */\n+ memset(k_ipad, 0, sizeof(k_ipad));\n+ memset(k_opad, 0, sizeof(k_opad));\n+ memcpy(k_ipad, key, key_len);\n+ memcpy(k_opad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < KEY_IOPAD_SIZE; i++) {\n+ k_ipad[i] ^= 0x36;\n+ k_opad[i] ^= 0x5c;\n+ }\n+\n+ /* perform inner SHA */\n+ utils_sha1_init(&context); /* init context for 1st pass */\n+ utils_sha1_starts(&context); /* setup context for 1st pass */\n+ utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE); /* start with inner pad */\n+ utils_sha1_update(&context, (unsigned char *) msg, msg_len); /* then text of datagram */\n+ utils_sha1_finish(&context, out); /* finish up 1st pass */\n+\n+ /* perform outer SHA */\n+ utils_sha1_init(&context); /* init context for 2nd pass */\n+ utils_sha1_starts(&context); /* setup context for 2nd pass */\n+ utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE); /* start with outer pad */\n+ utils_sha1_update(&context, out, SHA1_DIGEST_SIZE); /* then results of 1st hash */\n+ utils_sha1_finish(&context, out); /* finish up 2nd pass */\n+\n+ for (i = 0; i < SHA1_DIGEST_SIZE; ++i) {\n+ digest[i * 2] = utils_hb2hex(out[i] >> 4);\n+ digest[i * 2 + 1] = utils_hb2hex(out[i]);\n+ }\n+}\n+\n+void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len)\n+{\n+ if ((NULL == msg) || (NULL == digest) || (NULL == key)) {\n+ utils_err(\"parameter is Null,failed!\");\n+ return;\n+ }\n+\n+ if (key_len > KEY_IOPAD_SIZE) {\n+ utils_err(\"key_len > size(%d) of array\", KEY_IOPAD_SIZE);\n+ return;\n+ }\n+\n+ iot_sha1_context context;\n+ unsigned char k_ipad[KEY_IOPAD_SIZE]; /* inner padding - key XORd with ipad */\n+ unsigned char k_opad[KEY_IOPAD_SIZE]; /* outer padding - key XORd with opad */\n+ unsigned char out[SHA1_DIGEST_SIZE];\n+ int i;\n+\n+ /* start out by storing key in pads */\n+ memset(k_ipad, 0, sizeof(k_ipad));\n+ memset(k_opad, 0, sizeof(k_opad));\n+ memcpy(k_ipad, key, key_len);\n+ memcpy(k_opad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < KEY_IOPAD_SIZE; i++) {\n+ k_ipad[i] ^= 0x36;\n+ k_opad[i] ^= 0x5c;\n+ }\n+\n+ /* perform inner SHA */\n+ utils_sha1_init(&context); /* init context for 1st pass */\n+ utils_sha1_starts(&context); /* setup context for 1st pass */\n+ utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE); /* start with inner pad */\n+ utils_sha1_update(&context, (unsigned char *) msg, msg_len); /* then text of datagram */\n+ utils_sha1_finish(&context, out); /* finish up 1st pass */\n+\n+ /* perform outer SHA */\n+ utils_sha1_init(&context); /* init context for 2nd pass */\n+ utils_sha1_starts(&context); /* setup context for 2nd pass */\n+ utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE); /* start with outer pad */\n+ utils_sha1_update(&context, out, SHA1_DIGEST_SIZE); /* then results of 1st hash */\n+ utils_sha1_finish(&context, out); /* finish up 2nd pass */\n+ memcpy(digest, out, SHA1_DIGEST_SIZE);\n+}\n+#endif /* #ifdef UTILS_SHA1 */\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4e24d6485ab04728e58e0eaca8108a4046680a3c\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c\n@@ -0,0 +1,113 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <bl_sec.h>\n+#include <utils_hmac_sha1_fast.h>\n+\n+\n+void utils_hmac_sha1_fast(unsigned char ** ppText,\n+ int * pTextLen,\n+ int textNum,\n+ unsigned char *key,\n+ int key_len,\n+ unsigned char *output,\n+ int outputLen)\n+{\n+ uint64_t pBuf[(64 + 20) / 8 + 1]; /*BIG stack*/\n+ bl_sha_ctx_t sha_ctx;\n+ unsigned char *k_pad; /* padding - key XORd with i/opad */\n+ unsigned char *digest;\n+ int i;\n+\n+ /* k_pad start at a UINT32 boundary */\n+ k_pad = (unsigned char *)pBuf;\n+ digest = k_pad + 64;\n+\n+ /* if key is longer than 64 bytes reset it to key=SHA1(key) */\n+ if (key_len > 64)\n+ {\n+ bl_sha_init(&sha_ctx, BL_SHA1);\n+ bl_sha_update(&sha_ctx, key, key_len);\n+ bl_sha_finish(&sha_ctx, key);\n+\n+ key_len = 20;\n+ }\n+\n+ /*\n+ * the HMAC_SHA1 transform looks like:\n+ *\n+ * SHA1(K XOR opad, SHA1(K XOR ipad, text))\n+ *\n+ * where K is an n byte key\n+ * ipad is the byte 0x36 repeated 64 times\n+ * opad is the byte 0x5c repeated 64 times\n+ * and text is the data being protected\n+ */\n+\n+ /* perform inner SHA1*/\n+ /* start out by storing key in pads */\n+ memset(k_pad, 0, 64);\n+ memcpy(k_pad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < 8; i++)\n+ {\n+ ((uint64_t *)k_pad)[i] ^= 0x3636363636363636;\n+ }\n+\n+ bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 1st pass */\n+ bl_sha_update(&sha_ctx, k_pad, 64); /* start with inner pad */\n+ for (i = 0; i < textNum; i++)\n+ {\n+ /* then text of datagram */\n+ bl_sha_update(&sha_ctx, ppText[i], pTextLen[i]);\n+ }\n+\n+ bl_sha_finish(&sha_ctx, digest); /* finish up 1st pass */\n+\n+ /* perform outer SHA1 */\n+ /* start out by storing key in pads */\n+ memset(k_pad, 0, 64);\n+ memcpy(k_pad, key, key_len);\n+\n+ /* XOR key with ipad and opad values */\n+ for (i = 0; i < 8; i++)\n+ {\n+ ((uint64_t *)k_pad)[i] ^= 0x5c5c5c5c5c5c5c5c;\n+ }\n+\n+ bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 2nd pass */\n+ bl_sha_update(&sha_ctx, k_pad, 64); /* start with outer pad */\n+ bl_sha_update(&sha_ctx, digest, 20); /* then results of 1st hash */\n+ bl_sha_finish(&sha_ctx, digest); /* finish up 2nd pass */\n+ memcpy(output, digest, outputLen);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_list.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_list.c b/bsp/bl808/m0/libraries/utils/src/utils_list.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..59c6d3a0a2b60cffa5263932e0bc951ccd644cbf\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_list.c\n@@ -0,0 +1,365 @@\n+\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+#include <string.h>\n+#include <stdint.h>\n+#include <utils_list.h>\n+\n+void utils_list_init(struct utils_list *list)\n+{\n+ list->first = NULL;\n+ list->last = NULL;\n+}\n+\n+void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value)\n+{\n+ unsigned int i;\n+\n+ // initialize the free list relative to the pool\n+ utils_list_init(list);\n+\n+ // Add each element of the pool to this list, and init them one by one\n+ for (i = 0; i < elmt_cnt; i++) {\n+ if (default_value)\n+ {\n+ memcpy(pool, default_value, elmt_size);\n+ }\n+ utils_list_push_back(list, (struct utils_list_hdr *) pool);\n+\n+ // move to the next pool element\n+ pool = (void *)((uint8_t *)pool + (unsigned int)elmt_size);\n+ }\n+}\n+\n+void utils_list_push_back(struct utils_list *list, struct utils_list_hdr *list_hdr)\n+{\n+ // Sanity check\n+ // FIXME assert error here\n+ //ASSERT_ERR(list_hdr != NULL);\n+\n+ // check if list is empty\n+ if (utils_list_is_empty(list))\n+ {\n+ // list empty => pushed element is also head\n+ list->first = list_hdr;\n+ }\n+ else\n+ {\n+ // list not empty => update next of last\n+ list->last->next = list_hdr;\n+ }\n+\n+ // add element at the end of the list\n+ list->last = list_hdr;\n+ list_hdr->next = NULL;\n+}\n+\n+void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr)\n+{\n+ // Sanity check\n+ // FIXME assert error here\n+ //ASSERT_ERR(list_hdr != NULL);\n+\n+ // check if list is empty\n+ if (utils_list_is_empty(list))\n+ {\n+ // list empty => pushed element is also head\n+ list->last = list_hdr;\n+ }\n+\n+ // add element at the beginning of the list\n+ list_hdr->next = list->first;\n+ list->first = list_hdr;\n+}\n+\n+struct utils_list_hdr *utils_list_pop_front(struct utils_list *list)\n+{\n+ struct utils_list_hdr *element;\n+\n+ // check if list is empty\n+ element = list->first;\n+ if (element != NULL)\n+ {\n+ // The list isn't empty : extract the first element\n+ list->first = list->first->next;\n+ }\n+\n+ return element;\n+}\n+\n+void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr)\n+{\n+ struct utils_list_hdr *scan_list;\n+\n+ // sanity check\n+ // FIXME assert error here\n+ //ASSERT_ERR(list != NULL);\n+\n+ scan_list = list->first;\n+\n+ // Check if list is empty or not\n+ if (scan_list == NULL)\n+ return;\n+\n+ // check if searched element is first\n+ if (scan_list == list_hdr)\n+ {\n+ // Extract first element\n+ list->first = scan_list->next;\n+ }\n+ else\n+ {\n+ // Look for the element in the list\n+ while ((scan_list->next != NULL) && (scan_list->next != list_hdr))\n+ {\n+ scan_list = scan_list->next;\n+ }\n+\n+ // Check if element was found in the list\n+ if (scan_list->next != NULL)\n+ {\n+ // check if the removed element is the last in the list\n+ if (list->last == list_hdr)\n+ {\n+ // Last element will be extracted\n+ list->last = scan_list;\n+ }\n+ // Extract the element from the list\n+ scan_list->next = list_hdr->next;\n+ }\n+ }\n+}\n+\n+int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr)\n+{\n+ struct utils_list_hdr *tmp_list_hdr;\n+\n+ // Go through the list to find the element\n+ tmp_list_hdr = list->first;\n+ while((tmp_list_hdr != list_hdr) && (tmp_list_hdr != NULL))\n+ {\n+ tmp_list_hdr = tmp_list_hdr->next;\n+ }\n+\n+ return (tmp_list_hdr == list_hdr);\n+}\n+\n+unsigned int utils_list_cnt(const struct utils_list *const list)\n+{\n+ unsigned int cnt = 0;\n+ struct utils_list_hdr *elt = utils_list_pick(list);\n+\n+ // Go through the list to count the number of elements\n+ while (elt != NULL)\n+ {\n+ cnt++;\n+ elt = utils_list_next(elt);\n+ }\n+\n+ return(cnt);\n+}\n+\n+/**\n+ ****************************************************************************************\n+ * @brief Insert an element in a sorted list.\n+ *\n+ * This primitive use a comparison function from the parameter list to select where the\n+ * element must be inserted.\n+ *\n+ * @param[in] list Pointer to the list.\n+ * @param[in] element Pointer to the element to insert.\n+ * @param[in] cmp Comparison function (return true if first element has to be inserted\n+ * before the second one).\n+ *\n+ * @return Pointer to the element found and removed (NULL otherwise).\n+ ****************************************************************************************\n+ */\n+void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,\n+ int (*cmp)(struct utils_list_hdr const *elementA, struct utils_list_hdr const *elementB))\n+{\n+ struct utils_list_hdr *prev = NULL;\n+ struct utils_list_hdr *scan = list->first;\n+\n+ for(;;)\n+ {\n+ // scan the list until the end or cmp() returns true\n+ if (scan)\n+ {\n+ if (cmp(element, scan))\n+ {\n+ // insert now\n+ break;\n+ }\n+ prev = scan;\n+ scan = scan->next;\n+ }\n+ else\n+ {\n+ // end of list\n+ list->last = element;\n+ break;\n+ }\n+ }\n+\n+ element->next = scan;\n+\n+ if (prev)\n+ {\n+ // second or more\n+ prev->next = element;\n+ }\n+ else\n+ {\n+ // first message\n+ list->first = element;\n+ }\n+}\n+\n+void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element)\n+{\n+ struct utils_list_hdr *scan = list->first;\n+\n+ if (prev_element == NULL)\n+ {\n+ // Insert the element in front on the list\n+ utils_list_push_front(list, element);\n+ }\n+ else\n+ {\n+ // Look for prev_element in the list\n+ while (scan)\n+ {\n+ if (scan == prev_element)\n+ {\n+ break;\n+ }\n+\n+ // Get next element\n+ scan = scan->next;\n+ }\n+\n+ // If prev_element has been found, insert element\n+ if (scan)\n+ {\n+ element->next = prev_element->next;\n+ prev_element->next = element;\n+\n+ if (element->next == NULL)\n+ {\n+ list->last = element;\n+ }\n+ }\n+ }\n+}\n+\n+void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element)\n+{\n+ if (next_element == NULL)\n+ {\n+ // Insert the element at the end of the list\n+ utils_list_push_back(list, element);\n+ }\n+ else if (next_element == list->first)\n+ {\n+ // Insert the element in front of the list\n+ utils_list_push_front(list, element);\n+ }\n+ else\n+ {\n+ struct utils_list_hdr *scan = list->first;\n+\n+ // Look for next_element in the list\n+ while (scan)\n+ {\n+ if (scan->next == next_element)\n+ {\n+ break;\n+ }\n+\n+ // Get next element\n+ scan = scan->next;\n+ }\n+\n+ // Insert element after scan\n+ if (scan)\n+ {\n+ element->next = next_element;\n+ scan->next = element;\n+ }\n+ }\n+}\n+\n+void utils_list_concat(struct utils_list *list1, struct utils_list *list2)\n+{\n+ // If list2 is empty, don't do anything\n+ if (list2->first != NULL)\n+ {\n+ // Check if list1 is empty\n+ if (list1->first == NULL)\n+ {\n+ // If list1 is empty, list1 becomes list2\n+ *list1 = *list2;\n+ }\n+ else\n+ {\n+ // Otherwise, append list2 to list1\n+ list1->last->next = list2->first;\n+ list1->last = list2->last;\n+ }\n+ // Clear list2\n+ list2->first = NULL;\n+ }\n+}\n+\n+\n+void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element)\n+{\n+ // sanity check\n+ // FIXME assert error here\n+ //ASSERT_ERR(list != NULL);\n+ //ASSERT_ERR((prev_element == NULL) || (prev_element->next == element));\n+ //ASSERT_ERR(element != NULL);\n+\n+\n+ if (prev_element == NULL)\n+ {\n+ list->first = element->next;\n+ }\n+ else\n+ {\n+ prev_element->next = element->next;\n+ if (list->last == element)\n+ list->last = prev_element;\n+ }\n+\n+ element->next = NULL;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_log.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_log.c b/bsp/bl808/m0/libraries/utils/src/utils_log.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..73fbeec762c0ae85d2956a5879cc7bb96d04fcd6\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_log.c\n@@ -0,0 +1,184 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <stdint.h>\n+\n+#include \"utils_log.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define ONE_LINE_MAX_NUM (50)/* for print_buf log length */\n+#define MODULE_LOG_LOCK_LOCK /* reserved */\n+#define MODULE_LOG_LOCK_UNLOCK /* reserved */\n+static char log_buf[512];\n+int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type)\n+{\n+ char *buf = (char *)inbuf;\n+ char *pbuffer = NULL;\n+\n+#if defined(BL702) || defined(BL702L)\n+ pbuffer = (char *)pvPortMalloc(sizeof(log_buf));\n+ if(pbuffer == NULL){\n+ return -1;\n+ }\n+#else\n+ pbuffer = (char *)log_buf;\n+#endif\n+ int m = 0, n = 0;\n+ int j = 0, k = 0, tmp = 0;\n+\n+ MODULE_LOG_LOCK_LOCK;\n+\n+ tmp = (sizeof(log_buf))/3;/* 数组最大长度 */\n+ if ((ONE_LINE_MAX_NUM > tmp) || (len < 1))\n+ {\n+ MODULE_LOG_LOCK_UNLOCK;\n+ return -1;\n+ }\n+\n+ m = len / ONE_LINE_MAX_NUM;\n+ n = len % ONE_LINE_MAX_NUM;\n+ if (n > 0) {\n+ m++;\n+ }\n+\n+\n+ if (n > 0) {\n+ /* 非整数倍 */\n+ for (k = 0; k < m; k++) {\n+ if ((k+1) == m) {\n+ /* 最后一帧数据 */\n+ tmp = 0;\n+ for (j = 0; j < n; j++) {\n+ switch (type) {\n+ case LOG_BUF_OUT_DATA_TYPE_INT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3d \", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_UNT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3u \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_HEX:\n+ default:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%02x \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ }\n+ }\n+ log_buf_pri(file, line, \"%.*s\\r\\n\", tmp, pbuffer);\n+ } else {\n+ tmp = 0;\n+ for (j = 0; j < ONE_LINE_MAX_NUM; j++) {\n+ switch (type) {\n+ case LOG_BUF_OUT_DATA_TYPE_INT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3d \", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_UNT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3u \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_HEX:\n+ default:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%02x \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ }\n+ }\n+ log_buf_pri(file, line, \"%.*s\\r\\n\", tmp, pbuffer);\n+ }\n+ }\n+ } else {\n+ /* 整数倍 */\n+ for (k = 0; k < m; k++) {\n+ tmp = 0;\n+ for (j = 0; j < ONE_LINE_MAX_NUM; j++) {\n+ switch (type) {\n+ case LOG_BUF_OUT_DATA_TYPE_INT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3d \", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_UNT8:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%3u \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ break;\n+ case LOG_BUF_OUT_DATA_TYPE_HEX:\n+ default:\n+ {\n+ tmp += sprintf(pbuffer + tmp, \"%02x \", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);\n+ }\n+ }\n+ }\n+ log_buf_pri(file, line, \"%.*s\\r\\n\", tmp, pbuffer);\n+ }\n+ }\n+\n+ MODULE_LOG_LOCK_UNLOCK;\n+\n+#if defined(BL702) || defined(BL702L)\n+ vPortFree(pbuffer);\n+#endif\n+\n+ return 0;\n+}\n+\n+extern void vprint(const char *fmt, va_list argp);\n+\n+extern volatile bool sys_log_all_enable;\n+\n+void bl_printk(const char *format, ...)\n+{\n+ va_list args;\n+\n+ if (sys_log_all_enable) {\n+ /* args point to the first variable parameter */\n+ va_start(args, format);\n+\n+ /* You can add your code under here. */\n+ vprint(format, args);\n+\n+ va_end(args);\n+ }\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_md5.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_md5.c b/bsp/bl808/m0/libraries/utils/src/utils_md5.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..00ff1d1a51e2a5483090a45d8397e1779cb1bf45\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_md5.c\n@@ -0,0 +1,324 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifdef UTILS_MD5\n+\n+\n+#include <stdlib.h>\n+#include <string.h>\n+#include \"iot_import.h\"\n+#include \"iot_export.h\"\n+#include \"iotx_log.h\"\n+#include \"utils_md5.h\"\n+\n+#define MD5_DIGEST_SIZE 16\n+\n+\n+/* Implementation that should never be optimized out by the compiler */\n+static void utils_md5_zeroize(void *v, size_t n)\n+{\n+ volatile unsigned char *p = v;\n+ while (n--) {\n+ *p++ = 0;\n+ }\n+}\n+\n+/*\n+ * 32-bit integer manipulation macros (little endian)\n+ */\n+#ifndef IOT_MD5_GET_UINT32_LE\n+#define IOT_MD5_GET_UINT32_LE(n,b,i) \\\n+ { \\\n+ (n) = ( (uint32_t) (b)[(i) ] ) \\\n+ | ( (uint32_t) (b)[(i) + 1] << 8 ) \\\n+ | ( (uint32_t) (b)[(i) + 2] << 16 ) \\\n+ | ( (uint32_t) (b)[(i) + 3] << 24 ); \\\n+ }\n+#endif\n+\n+#ifndef IOT_MD5_PUT_UINT32_LE\n+#define IOT_MD5_PUT_UINT32_LE(n,b,i) \\\n+ { \\\n+ (b)[(i) ] = (unsigned char) ( ( (n) ) & 0xFF ); \\\n+ (b)[(i) + 1] = (unsigned char) ( ( (n) >> 8 ) & 0xFF ); \\\n+ (b)[(i) + 2] = (unsigned char) ( ( (n) >> 16 ) & 0xFF ); \\\n+ (b)[(i) + 3] = (unsigned char) ( ( (n) >> 24 ) & 0xFF ); \\\n+ }\n+#endif\n+\n+void utils_md5_init(iot_md5_context *ctx)\n+{\n+ memset(ctx, 0, sizeof(iot_md5_context));\n+}\n+\n+void utils_md5_free(iot_md5_context *ctx)\n+{\n+ if (ctx == NULL) {\n+ return;\n+ }\n+\n+ utils_md5_zeroize(ctx, sizeof(iot_md5_context));\n+}\n+\n+void utils_md5_clone(iot_md5_context *dst,\n+ const iot_md5_context *src)\n+{\n+ *dst = *src;\n+}\n+\n+/*\n+ * MD5 context setup\n+ */\n+void utils_md5_starts(iot_md5_context *ctx)\n+{\n+ ctx->total[0] = 0;\n+ ctx->total[1] = 0;\n+\n+ ctx->state[0] = 0x67452301;\n+ ctx->state[1] = 0xEFCDAB89;\n+ ctx->state[2] = 0x98BADCFE;\n+ ctx->state[3] = 0x10325476;\n+}\n+\n+void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64])\n+{\n+ uint32_t X[16], A, B, C, D;\n+\n+ IOT_MD5_GET_UINT32_LE(X[ 0], data, 0);\n+ IOT_MD5_GET_UINT32_LE(X[ 1], data, 4);\n+ IOT_MD5_GET_UINT32_LE(X[ 2], data, 8);\n+ IOT_MD5_GET_UINT32_LE(X[ 3], data, 12);\n+ IOT_MD5_GET_UINT32_LE(X[ 4], data, 16);\n+ IOT_MD5_GET_UINT32_LE(X[ 5], data, 20);\n+ IOT_MD5_GET_UINT32_LE(X[ 6], data, 24);\n+ IOT_MD5_GET_UINT32_LE(X[ 7], data, 28);\n+ IOT_MD5_GET_UINT32_LE(X[ 8], data, 32);\n+ IOT_MD5_GET_UINT32_LE(X[ 9], data, 36);\n+ IOT_MD5_GET_UINT32_LE(X[10], data, 40);\n+ IOT_MD5_GET_UINT32_LE(X[11], data, 44);\n+ IOT_MD5_GET_UINT32_LE(X[12], data, 48);\n+ IOT_MD5_GET_UINT32_LE(X[13], data, 52);\n+ IOT_MD5_GET_UINT32_LE(X[14], data, 56);\n+ IOT_MD5_GET_UINT32_LE(X[15], data, 60);\n+\n+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))\n+\n+#define P(a,b,c,d,k,s,t) \\\n+ { \\\n+ a += F(b,c,d) + X[k] + t; a = S(a,s) + b; \\\n+ }\n+\n+ A = ctx->state[0];\n+ B = ctx->state[1];\n+ C = ctx->state[2];\n+ D = ctx->state[3];\n+\n+#define F(x,y,z) (z ^ (x & (y ^ z)))\n+\n+ P(A, B, C, D, 0, 7, 0xD76AA478);\n+ P(D, A, B, C, 1, 12, 0xE8C7B756);\n+ P(C, D, A, B, 2, 17, 0x242070DB);\n+ P(B, C, D, A, 3, 22, 0xC1BDCEEE);\n+ P(A, B, C, D, 4, 7, 0xF57C0FAF);\n+ P(D, A, B, C, 5, 12, 0x4787C62A);\n+ P(C, D, A, B, 6, 17, 0xA8304613);\n+ P(B, C, D, A, 7, 22, 0xFD469501);\n+ P(A, B, C, D, 8, 7, 0x698098D8);\n+ P(D, A, B, C, 9, 12, 0x8B44F7AF);\n+ P(C, D, A, B, 10, 17, 0xFFFF5BB1);\n+ P(B, C, D, A, 11, 22, 0x895CD7BE);\n+ P(A, B, C, D, 12, 7, 0x6B901122);\n+ P(D, A, B, C, 13, 12, 0xFD987193);\n+ P(C, D, A, B, 14, 17, 0xA679438E);\n+ P(B, C, D, A, 15, 22, 0x49B40821);\n+\n+#undef F\n+\n+#define F(x,y,z) (y ^ (z & (x ^ y)))\n+\n+ P(A, B, C, D, 1, 5, 0xF61E2562);\n+ P(D, A, B, C, 6, 9, 0xC040B340);\n+ P(C, D, A, B, 11, 14, 0x265E5A51);\n+ P(B, C, D, A, 0, 20, 0xE9B6C7AA);\n+ P(A, B, C, D, 5, 5, 0xD62F105D);\n+ P(D, A, B, C, 10, 9, 0x02441453);\n+ P(C, D, A, B, 15, 14, 0xD8A1E681);\n+ P(B, C, D, A, 4, 20, 0xE7D3FBC8);\n+ P(A, B, C, D, 9, 5, 0x21E1CDE6);\n+ P(D, A, B, C, 14, 9, 0xC33707D6);\n+ P(C, D, A, B, 3, 14, 0xF4D50D87);\n+ P(B, C, D, A, 8, 20, 0x455A14ED);\n+ P(A, B, C, D, 13, 5, 0xA9E3E905);\n+ P(D, A, B, C, 2, 9, 0xFCEFA3F8);\n+ P(C, D, A, B, 7, 14, 0x676F02D9);\n+ P(B, C, D, A, 12, 20, 0x8D2A4C8A);\n+\n+#undef F\n+\n+#define F(x,y,z) (x ^ y ^ z)\n+\n+ P(A, B, C, D, 5, 4, 0xFFFA3942);\n+ P(D, A, B, C, 8, 11, 0x8771F681);\n+ P(C, D, A, B, 11, 16, 0x6D9D6122);\n+ P(B, C, D, A, 14, 23, 0xFDE5380C);\n+ P(A, B, C, D, 1, 4, 0xA4BEEA44);\n+ P(D, A, B, C, 4, 11, 0x4BDECFA9);\n+ P(C, D, A, B, 7, 16, 0xF6BB4B60);\n+ P(B, C, D, A, 10, 23, 0xBEBFBC70);\n+ P(A, B, C, D, 13, 4, 0x289B7EC6);\n+ P(D, A, B, C, 0, 11, 0xEAA127FA);\n+ P(C, D, A, B, 3, 16, 0xD4EF3085);\n+ P(B, C, D, A, 6, 23, 0x04881D05);\n+ P(A, B, C, D, 9, 4, 0xD9D4D039);\n+ P(D, A, B, C, 12, 11, 0xE6DB99E5);\n+ P(C, D, A, B, 15, 16, 0x1FA27CF8);\n+ P(B, C, D, A, 2, 23, 0xC4AC5665);\n+\n+#undef F\n+\n+#define F(x,y,z) (y ^ (x | ~z))\n+\n+ P(A, B, C, D, 0, 6, 0xF4292244);\n+ P(D, A, B, C, 7, 10, 0x432AFF97);\n+ P(C, D, A, B, 14, 15, 0xAB9423A7);\n+ P(B, C, D, A, 5, 21, 0xFC93A039);\n+ P(A, B, C, D, 12, 6, 0x655B59C3);\n+ P(D, A, B, C, 3, 10, 0x8F0CCC92);\n+ P(C, D, A, B, 10, 15, 0xFFEFF47D);\n+ P(B, C, D, A, 1, 21, 0x85845DD1);\n+ P(A, B, C, D, 8, 6, 0x6FA87E4F);\n+ P(D, A, B, C, 15, 10, 0xFE2CE6E0);\n+ P(C, D, A, B, 6, 15, 0xA3014314);\n+ P(B, C, D, A, 13, 21, 0x4E0811A1);\n+ P(A, B, C, D, 4, 6, 0xF7537E82);\n+ P(D, A, B, C, 11, 10, 0xBD3AF235);\n+ P(C, D, A, B, 2, 15, 0x2AD7D2BB);\n+ P(B, C, D, A, 9, 21, 0xEB86D391);\n+\n+#undef F\n+\n+ ctx->state[0] += A;\n+ ctx->state[1] += B;\n+ ctx->state[2] += C;\n+ ctx->state[3] += D;\n+}\n+\n+/*\n+ * MD5 process buffer\n+ */\n+void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen)\n+{\n+ size_t fill;\n+ uint32_t left;\n+\n+ if (ilen == 0) {\n+ return;\n+ }\n+\n+ left = ctx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ ctx->total[0] += (uint32_t) ilen;\n+ ctx->total[0] &= 0xFFFFFFFF;\n+\n+ if (ctx->total[0] < (uint32_t) ilen) {\n+ ctx->total[1]++;\n+ }\n+\n+ if (left && ilen >= fill) {\n+ memcpy((void *)(ctx->buffer + left), input, fill);\n+ utils_md5_process(ctx, ctx->buffer);\n+ input += fill;\n+ ilen -= fill;\n+ left = 0;\n+ }\n+\n+ while (ilen >= 64) {\n+ utils_md5_process(ctx, input);\n+ input += 64;\n+ ilen -= 64;\n+ }\n+\n+ if (ilen > 0) {\n+ memcpy((void *)(ctx->buffer + left), input, ilen);\n+ }\n+}\n+\n+static const unsigned char iot_md5_padding[64] = {\n+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\n+};\n+\n+/*\n+ * MD5 final digest\n+ */\n+void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16])\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ unsigned char msglen[8];\n+\n+ high = (ctx->total[0] >> 29)\n+ | (ctx->total[1] << 3);\n+ low = (ctx->total[0] << 3);\n+\n+ IOT_MD5_PUT_UINT32_LE(low, msglen, 0);\n+ IOT_MD5_PUT_UINT32_LE(high, msglen, 4);\n+\n+ last = ctx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ utils_md5_update(ctx, iot_md5_padding, padn);\n+ utils_md5_update(ctx, msglen, 8);\n+\n+ IOT_MD5_PUT_UINT32_LE(ctx->state[0], output, 0);\n+ IOT_MD5_PUT_UINT32_LE(ctx->state[1], output, 4);\n+ IOT_MD5_PUT_UINT32_LE(ctx->state[2], output, 8);\n+ IOT_MD5_PUT_UINT32_LE(ctx->state[3], output, 12);\n+}\n+\n+\n+/*\n+ * output = MD5( input buffer )\n+ */\n+void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16])\n+{\n+ iot_md5_context ctx;\n+\n+ utils_md5_init(&ctx);\n+ utils_md5_starts(&ctx);\n+ utils_md5_update(&ctx, input, ilen);\n+ utils_md5_finish(&ctx, output);\n+ utils_md5_free(&ctx);\n+}\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_memp.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_memp.c b/bsp/bl808/m0/libraries/utils/src/utils_memp.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..72a0b9ce4548ed974c76740a065366aadf8d8100\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_memp.c\n@@ -0,0 +1,180 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <FreeRTOS.h>\n+#include <utils_memp.h>\n+\n+#define UTILS_MEMP_ALLOCED_NODE_PATTERN 0XA5\n+#define MEM_ALIGN(addr, align) (((addr) + (align) -1) & ~((align)-1))\n+\n+int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)\n+{\n+ utils_memp_pool_t *npool;\n+ struct utils_memp_node *node;\n+ struct utils_memp_node *pool_mem;\n+ size_t size;\n+ uint16_t padded_node_size;\n+ uint16_t i;\n+\n+ align_req = MEM_ALIGN(align_req, sizeof(void *));\n+ padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);\n+\n+ size = sizeof(utils_memp_pool_t);\n+ size = MEM_ALIGN(size, align_req);\n+ size += padded_node_size * pool_cap;\n+\n+ npool = pvPortMalloc(size);\n+\n+ if (!npool) {\n+ return -1;\n+ }\n+\n+ node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));\n+ npool->first_node = node;\n+ npool->node_size = node_size;\n+ npool->pool_cap = pool_cap;\n+ npool->pool_size = 0;\n+ npool->align_req = align_req;\n+ npool->padded_node_size = padded_node_size;\n+ npool->mem = NULL;\n+ pool_mem = npool->mem;\n+\n+ for(i = 0; i < pool_cap; ++i) {\n+ node->next = pool_mem;\n+ pool_mem = node;\n+ node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);\n+ }\n+ npool->mem = pool_mem;\n+ npool->last_node = npool->mem;\n+ *pool = npool;\n+\n+ return 0;\n+}\n+\n+int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)\n+{\n+ utils_memp_pool_t *npool = pool;\n+ struct utils_memp_node *node;\n+ struct utils_memp_node *pool_mem;\n+ size_t size;\n+ uint16_t padded_node_size;\n+ uint16_t i;\n+\n+ align_req = MEM_ALIGN(align_req, sizeof(void *));\n+ padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);\n+\n+ size = sizeof(utils_memp_pool_t);\n+ size = MEM_ALIGN(size, align_req);\n+ size += padded_node_size * pool_cap;\n+\n+ node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));\n+ npool->first_node = node;\n+ npool->node_size = node_size;\n+ npool->pool_cap = pool_cap;\n+ npool->pool_size = 0;\n+ npool->align_req = align_req;\n+ npool->padded_node_size = padded_node_size;\n+ npool->mem = NULL;\n+ pool_mem = npool->mem;\n+\n+ for(i = 0; i < pool_cap; ++i) {\n+ node->next = pool_mem;\n+ pool_mem = node;\n+ node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);\n+ }\n+ npool->mem = pool_mem;\n+ npool->last_node = npool->mem;\n+\n+ return 0;\n+}\n+\n+int utils_memp_deinit(utils_memp_pool_t *pool)\n+{\n+ if (!pool) {\n+ return -1;\n+ }\n+ vPortFree(pool);\n+\n+ return 0;\n+}\n+\n+void *utils_memp_malloc(utils_memp_pool_t *pool)\n+{\n+ struct utils_memp_node *node;\n+ uint32_t *pat;\n+ if (!pool) {\n+ return NULL;\n+ }\n+ if (pool->pool_size == pool->pool_cap) {\n+ return NULL;\n+ }\n+ node = pool->mem;\n+ if (node != NULL) {\n+ pool->mem = node->next;\n+ pool->pool_size++;\n+ pat = (uint32_t *)&node->next;\n+ *pat = UTILS_MEMP_ALLOCED_NODE_PATTERN;\n+ return (void *)node + sizeof(struct utils_memp_node);\n+ } else { \n+ return NULL;\n+ }\n+}\n+\n+int utils_memp_free(utils_memp_pool_t *pool, void *node)\n+{\n+ struct utils_memp_node *utils_memp_node;\n+ node = node - sizeof(struct utils_memp_node);\n+ uint32_t *pat;\n+ int diff;\n+\n+ if (!pool || !node) {\n+ return -1;\n+ }\n+ if (pool->pool_size == 0) {\n+ return -1;\n+ }\n+ if (!(node >= pool->first_node && node <= pool->last_node)) {\n+ return -1;\n+ }\n+ diff = node - pool->first_node;\n+ if (diff % pool->padded_node_size) {\n+ return -1;\n+ }\n+\n+ pat = (uint32_t *)(&((struct utils_memp_node *)node)->next);\n+ if (*pat != UTILS_MEMP_ALLOCED_NODE_PATTERN) {\n+ return -1;\n+ }\n+ utils_memp_node = (struct utils_memp_node*)node;\n+ utils_memp_node->next = pool->mem;\n+ pool->mem = utils_memp_node;\n+ pool->pool_size--;\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_notifier.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_notifier.c b/bsp/bl808/m0/libraries/utils/src/utils_notifier.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c6ab60240f5ef08be176d3baf6a6559141062721\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_notifier.c\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include \"utils_notifier.h\"\n+\n+int utils_notifier_chain_init(ntf_list_t *nl)\n+{\n+ utils_list_init((struct utils_list *)nl);\n+\n+ return 0;\n+}\n+\n+int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node)\n+{\n+ if (!nl || !node) {\n+ return -1;\n+ }\n+ utils_list_push_back((struct utils_list *)nl, (struct utils_list_hdr *)node);\n+\n+ return 0;\n+}\n+\n+int utils_notifier_chain_call(ntf_list_t *nl, void *env)\n+{\n+ utils_notifier_t *raw;\n+\n+ if (!nl) {\n+ return 0;\n+ }\n+\n+ raw = (utils_notifier_t *)nl->first;\n+\n+ while (raw) {\n+ if (raw->cb) {\n+ raw->cb(raw->cb_arg, env);\n+ }\n+ raw = (utils_notifier_t *)raw->node.next;\n+ }\n+\n+ return 0;\n+}\n+\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..87485e76a36bd284cebb036f0f4b6b9f51f2c6c9\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c\n@@ -0,0 +1,115 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <bl_sec.h>\n+#include <utils_psk_fast.h>\n+#include <utils_hex.h>\n+#include <utils_hmac_sha1_fast.h>\n+\n+#define A_SHA_DIGEST_LEN 20\n+static void Bl_F_fast(unsigned char digest[36], unsigned char digest1[A_SHA_DIGEST_LEN], char *password, unsigned char *ssid, int ssidlength, int iterations, int count, unsigned char *output)\n+{\n+ int i, j;\n+ int len = strlen(password);\n+ int tmpLen = ssidlength + 4;\n+ unsigned char * pTemp = digest;\n+\n+ /* U1 = PRF(P, S || int(i)) */\n+ memcpy(digest, ssid, ssidlength);\n+ digest[ssidlength] = (unsigned char)((count>>24) & 0xff);\n+ digest[ssidlength+1] = (unsigned char)((count>>16) & 0xff);\n+ digest[ssidlength+2] = (unsigned char)((count>>8) & 0xff);\n+ digest[ssidlength+3] = (unsigned char)(count & 0xff);\n+\n+ bl_sha_mutex_take();\n+ utils_hmac_sha1_fast(&pTemp,\n+ &tmpLen,\n+ 1,\n+ (unsigned char*) password,\n+ len,\n+ digest1,\n+ A_SHA_DIGEST_LEN);\n+\n+ /* output = U1 */\n+ memcpy(output, digest1, A_SHA_DIGEST_LEN);\n+ pTemp = digest1;\n+ for (i = 1; i < iterations; i++)\n+ {\n+ tmpLen = A_SHA_DIGEST_LEN;\n+\n+ /* Un = PRF(P, Un-1) */\n+ utils_hmac_sha1_fast(&pTemp,\n+ &tmpLen,\n+ 1,\n+ (unsigned char*) password,\n+ len,\n+ digest,\n+ A_SHA_DIGEST_LEN);\n+\n+ memcpy(digest1, digest, A_SHA_DIGEST_LEN);\n+\n+ /* output = output xor Un */\n+ for (j = 0; j < A_SHA_DIGEST_LEN; j++)\n+ {\n+ output[j] ^= digest[j];\n+ }\n+ }\n+ bl_sha_mutex_give();\n+}\n+\n+int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output)\n+{\n+ unsigned char digest[36], digest1[A_SHA_DIGEST_LEN];\n+\n+ if ((strlen(password) > 63) || (ssidlength > 32)) {\n+ return -1;\n+ }\n+\n+ Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 2, output);\n+ memcpy(output + A_SHA_DIGEST_LEN, output, 12);\n+ Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 1, output);\n+\n+ return 0;\n+}\n+\n+int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output)\n+{\n+ int ret;\n+ char psk[32];\n+\n+ ret = utils_wifi_psk_cal_fast_bin(password, (unsigned char *)ssid, ssid_len, (unsigned char *)psk);\n+ if (0 == ret) {\n+ utils_bin2hex(output, psk, 32);\n+ }\n+\n+ return ret;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_rbtree.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4d3ece3165a6220032720e30222c76d9bea8f902\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c\n@@ -0,0 +1,526 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <FreeRTOS.h>\n+#include \"utils_rbtree.h\"\n+\n+// rb_node\n+\n+struct rb_node * rb_node_alloc () \n+{\n+ return pvPortMalloc(sizeof(struct rb_node));\n+}\n+\n+struct rb_node * rb_node_init (struct rb_node *self, void *value) \n+{\n+ if (self) {\n+ self->red = 1;\n+ self->link[0] = self->link[1] = NULL;\n+ self->value = value;\n+ }\n+ return self;\n+}\n+\n+struct rb_node * rb_node_create (void *value) \n+{\n+ return rb_node_init(rb_node_alloc(), value);\n+}\n+\n+void rb_node_dealloc (struct rb_node *self) \n+{\n+ if (self) {\n+ vPortFree(self);\n+ }\n+}\n+\n+static int rb_node_is_red (const struct rb_node *self) \n+{\n+ return self ? self->red : 0;\n+}\n+\n+static struct rb_node * rb_node_rotate (struct rb_node *self, int dir) \n+{\n+ struct rb_node *result = NULL;\n+\n+ if (self) {\n+ result = self->link[!dir];\n+ self->link[!dir] = result->link[dir];\n+ result->link[dir] = self;\n+ self->red = 1;\n+ result->red = 0;\n+ }\n+ return result;\n+}\n+\n+static struct rb_node * rb_node_rotate2 (struct rb_node *self, int dir) \n+{\n+ struct rb_node *result = NULL;\n+\n+ if (self) {\n+ self->link[!dir] = rb_node_rotate(self->link[!dir], !dir);\n+ result = rb_node_rotate(self, dir);\n+ }\n+ return result;\n+}\n+\n+// rb_tree - default callbacks\n+int rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b) \n+{\n+ return (a->value > b->value) - (a->value < b->value);\n+}\n+\n+void rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node) \n+{\n+ if (self) {\n+ if (node) {\n+ rb_node_dealloc(node);\n+ }\n+ }\n+}\n+\n+// rb_tree\n+struct rb_tree * rb_tree_alloc () \n+{\n+ return pvPortMalloc(sizeof(struct rb_tree));\n+}\n+\n+struct rb_tree * rb_tree_init (struct rb_tree *self, rb_tree_node_cmp_f node_cmp_cb) \n+{\n+ if (self) {\n+ self->root = NULL;\n+ self->size = 0;\n+ self->cmp = node_cmp_cb ? node_cmp_cb : rb_tree_node_cmp_ptr_cb;\n+ }\n+\n+ return self;\n+}\n+\n+struct rb_tree * rb_tree_create (rb_tree_node_cmp_f node_cb) \n+{\n+ return rb_tree_init(rb_tree_alloc(), node_cb);\n+}\n+\n+void rb_tree_dealloc(struct rb_tree *self, rb_tree_node_f node_cb) \n+{\n+ if (self) {\n+ if (node_cb) {\n+ struct rb_node *node = self->root;\n+ struct rb_node *save = NULL;\n+ \n+ // Rotate away the left links so that\n+ // we can treat this like the destruction\n+ // of a linked list\n+ while (node) {\n+ if (node->link[0] == NULL) {\n+\n+ // No left links, just kill the node and move on\n+ save = node->link[1];\n+ node_cb(self, node);\n+ node = NULL;\n+ } else {\n+ \n+ // Rotate away the left link and check again\n+ save = node->link[0];\n+ node->link[0] = save->link[1];\n+ save->link[1] = node;\n+ }\n+ node = save;\n+ }\n+ }\n+ vPortFree(self);\n+ }\n+}\n+\n+int rb_tree_test(struct rb_tree *self, struct rb_node *root) \n+{\n+ int lh, rh;\n+ \n+ if (NULL == root) {\n+ return 1;\n+ } else {\n+ struct rb_node *ln = root->link[0];\n+ struct rb_node *rn = root->link[1];\n+ \n+ /* Consecutive red links */\n+ if (rb_node_is_red(root)) {\n+ if (rb_node_is_red(ln) || rb_node_is_red(rn)) {\n+ printf(\"Red violation\");\n+ return 0;\n+ }\n+ }\n+ \n+ lh = rb_tree_test(self, ln);\n+ rh = rb_tree_test(self, rn);\n+ \n+ /* Invalid binary search tree */\n+ if ( ( ln != NULL && self->cmp(self, ln, root) >= 0 )\n+ || ( rn != NULL && self->cmp(self, rn, root) <= 0))\n+ {\n+ puts ( \"Binary tree violation\" );\n+ return 0;\n+ }\n+ \n+ /* Black height mismatch */\n+ if ( lh != 0 && rh != 0 && lh != rh ) {\n+ puts ( \"Black violation\" );\n+ return 0;\n+ }\n+ \n+ /* Only count black links */\n+ if ( lh != 0 && rh != 0 )\n+ return rb_node_is_red ( root ) ? lh : lh + 1;\n+ else\n+ return 0;\n+ }\n+}\n+\n+void * rb_tree_find(struct rb_tree *self, void *value) \n+{\n+ void *result = NULL;\n+\n+ if (self) {\n+ struct rb_node node = { .value = value };\n+ struct rb_node *it = self->root;\n+ int cmp = 0;\n+ while (it) {\n+ if ((cmp = self->cmp(self, it, &node))) {\n+\n+ // If the tree supports duplicates, they should be\n+ // chained to the right subtree for this to work\n+ it = it->link[cmp < 0];\n+ } else {\n+ break;\n+ }\n+ }\n+ result = it ? it->value : NULL;\n+ }\n+ return result;\n+}\n+\n+// Creates (malloc'ates) \n+int rb_tree_insert(struct rb_tree *self, void *value) \n+{\n+ struct rb_node *node;\n+\n+ if (NULL == self) {\n+ return 0;\n+ }\n+\n+ node = rb_node_create(value);\n+\n+ if (NULL == node) {\n+ return 0;\n+ }\n+\n+ return rb_tree_insert_node(self, node);\n+}\n+\n+// Returns 1 on success, 0 otherwise.\n+int rb_tree_insert_node (struct rb_tree *self, struct rb_node *node) \n+{\n+ if (self && node) {\n+ if (self->root == NULL) {\n+ self->root = node;\n+ } else {\n+ struct rb_node head = { 0 }; // False tree root\n+ struct rb_node *g, *t; // Grandparent & parent\n+ struct rb_node *p, *q; // Iterator & parent\n+ int dir = 0, last = 0;\n+\n+ // Set up our helpers\n+ t = &head;\n+ g = p = NULL;\n+ q = t->link[1] = self->root;\n+\n+ // Search down the tree for a place to insert\n+ while (1) {\n+ if (q == NULL) {\n+\n+ // Insert node at the first null link.\n+ p->link[dir] = q = node;\n+ } else if (rb_node_is_red(q->link[0]) && rb_node_is_red(q->link[1])) {\n+ \n+ // Simple red violation: color flip\n+ q->red = 1;\n+ q->link[0]->red = 0;\n+ q->link[1]->red = 0;\n+ }\n+\n+ if (rb_node_is_red(q) && rb_node_is_red(p)) {\n+\n+ // Hard red violation: rotations necessary\n+ int dir2 = t->link[1] == g;\n+ if (q == p->link[last]) {\n+ t->link[dir2] = rb_node_rotate(g, !last);\n+ } else {\n+ t->link[dir2] = rb_node_rotate2(g, !last);\n+ }\n+ }\n+ \n+ // Stop working if we inserted a node. This\n+ // check also disallows duplicates in the tree\n+ if (self->cmp(self, q, node) == 0) {\n+ break;\n+ }\n+\n+ last = dir;\n+ dir = self->cmp(self, q, node) < 0;\n+\n+ // Move the helpers down\n+ if (g != NULL) {\n+ t = g;\n+ }\n+\n+ g = p, p = q;\n+ q = q->link[dir];\n+ }\n+\n+ // Update the root (it may be different)\n+ self->root = head.link[1];\n+ }\n+\n+ // Make the root black for simplified logic\n+ self->root->red = 0;\n+ ++self->size;\n+ } else {\n+ return 0;\n+ }\n+ \n+ return 1;\n+}\n+\n+// Returns 1 if the value was removed, 0 otherwise. Optional node callback\n+// can be provided to dealloc node and/or user data. Use rb_tree_node_dealloc\n+// default callback to deallocate node created by rb_tree_insert(...).\n+int rb_tree_remove_with_cb (struct rb_tree *self, void *value, rb_tree_node_f node_cb) \n+{\n+ if (self->root != NULL) {\n+ struct rb_node head = {0}; // False tree root\n+ struct rb_node node = { .value = value }; // Value wrapper node\n+ struct rb_node *q, *p, *g; // Helpers\n+ struct rb_node *f = NULL; // Found item\n+ int dir = 1;\n+\n+ // Set up our helpers\n+ q = &head;\n+ g = p = NULL;\n+ q->link[1] = self->root;\n+ \n+ // Search and push a red node down\n+ // to fix red violations as we go\n+ while (q->link[dir] != NULL) {\n+ int last = dir;\n+\n+ // Move the helpers down\n+ g = p, p = q;\n+ q = q->link[dir];\n+ dir = self->cmp(self, q, &node) < 0;\n+ \n+ // Save the node with matching value and keep\n+ // going; we'll do removal tasks at the end\n+ if (self->cmp(self, q, &node) == 0) {\n+ f = q;\n+ }\n+\n+ // Push the red node down with rotations and color flips\n+ if (!rb_node_is_red(q) && !rb_node_is_red(q->link[dir])) {\n+ if (rb_node_is_red(q->link[!dir])) {\n+ p = p->link[last] = rb_node_rotate(q, dir);\n+ } else if (!rb_node_is_red(q->link[!dir])) {\n+ struct rb_node *s = p->link[!last];\n+ if (s) {\n+ if (!rb_node_is_red(s->link[!last]) && !rb_node_is_red(s->link[last])) {\n+\n+ // Color flip\n+ p->red = 0;\n+ s->red = 1;\n+ q->red = 1;\n+ } else {\n+ int dir2 = g->link[1] == p;\n+ if (rb_node_is_red(s->link[last])) {\n+ g->link[dir2] = rb_node_rotate2(p, last);\n+ } else if (rb_node_is_red(s->link[!last])) {\n+ g->link[dir2] = rb_node_rotate(p, last);\n+ }\n+ \n+ // Ensure correct coloring\n+ q->red = g->link[dir2]->red = 1;\n+ g->link[dir2]->link[0]->red = 0;\n+ g->link[dir2]->link[1]->red = 0;\n+ }\n+ }\n+ }\n+ }\n+ }\n+\n+ // Replace and remove the saved node\n+ if (f) {\n+ void *tmp = f->value;\n+ f->value = q->value;\n+ q->value = tmp;\n+ \n+ p->link[p->link[1] == q] = q->link[q->link[0] == NULL];\n+ \n+ if (node_cb) {\n+ node_cb(self, q);\n+ }\n+ q = NULL;\n+ }\n+\n+ // Update the root (it may be different)\n+ self->root = head.link[1];\n+\n+ // Make the root black for simplified logic\n+ if (self->root != NULL) {\n+ self->root->red = 0;\n+ }\n+\n+ --self->size;\n+ }\n+ return 1;\n+}\n+\n+int rb_tree_remove (struct rb_tree *self, void *value) \n+{\n+ int result = 0;\n+\n+ if (self) {\n+ result = rb_tree_remove_with_cb(self, value, rb_tree_node_dealloc_cb);\n+ }\n+ return result;\n+}\n+\n+size_t rb_tree_size (struct rb_tree *self) \n+{\n+ size_t result = 0;\n+\n+ if (self) {\n+ result = self->size;\n+ }\n+ return result;\n+}\n+\n+// rb_iter\n+struct rb_iter * rb_iter_alloc () \n+{\n+ return pvPortMalloc(sizeof(struct rb_iter));\n+}\n+\n+struct rb_iter * rb_iter_init (struct rb_iter *self) \n+{\n+ if (self) {\n+ self->tree = NULL;\n+ self->node = NULL;\n+ self->top = 0;\n+ }\n+ return self;\n+}\n+\n+struct rb_iter * rb_iter_create () \n+{\n+ return rb_iter_init(rb_iter_alloc());\n+}\n+\n+void rb_iter_dealloc (struct rb_iter *self) \n+{\n+ if (self) {\n+ vPortFree(self);\n+ }\n+}\n+\n+// Internal function, init traversal object, dir determines whether\n+// to begin traversal at the smallest or largest valued node.\n+static void * rb_iter_start (struct rb_iter *self, struct rb_tree *tree, int dir) \n+{\n+ void *result = NULL;\n+\n+ if (self) {\n+ self->tree = tree;\n+ self->node = tree->root;\n+ self->top = 0;\n+\n+ // Save the path for later selfersal\n+ if (self->node != NULL) {\n+ while (self->node->link[dir] != NULL) {\n+ self->path[self->top++] = self->node;\n+ self->node = self->node->link[dir];\n+ }\n+ }\n+ result = self->node == NULL ? NULL : self->node->value;\n+ }\n+\n+ return result;\n+}\n+\n+// Traverse a red black tree in the user-specified direction (0 asc, 1 desc)\n+static void * rb_iter_move(struct rb_iter *self, int dir) \n+{\n+ if (self->node->link[dir] != NULL) {\n+ // Continue down this branch\n+ self->path[self->top++] = self->node;\n+ self->node = self->node->link[dir];\n+ while ( self->node->link[!dir] != NULL ) {\n+ self->path[self->top++] = self->node;\n+ self->node = self->node->link[!dir];\n+ }\n+ } else {\n+ // Move to the next branch\n+ struct rb_node *last = NULL;\n+ do {\n+ if (self->top == 0) {\n+ self->node = NULL;\n+ break;\n+ }\n+ last = self->node;\n+ self->node = self->path[--self->top];\n+ } while (last == self->node->link[dir]);\n+ }\n+ return self->node == NULL ? NULL : self->node->value;\n+}\n+\n+void *rb_iter_first(struct rb_iter *self, struct rb_tree *tree) \n+{\n+ return rb_iter_start(self, tree, 0);\n+}\n+\n+void * rb_iter_last(struct rb_iter *self, struct rb_tree *tree) \n+{\n+ return rb_iter_start(self, tree, 1);\n+}\n+\n+void * rb_iter_next(struct rb_iter *self)\n+{\n+ return rb_iter_move(self, 1);\n+}\n+\n+void * rb_iter_prev(struct rb_iter *self)\n+{\n+ return rb_iter_move(self, 0);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_ringblk.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7a9b3da0473e245880f229c932802f8375804d3b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c\n@@ -0,0 +1,578 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+#include <stdlib.h>\n+#include <assert.h>\n+\n+#include \"FreeRTOS.h\"\n+#include \"utils_list.h\"\n+#include \"utils_ringblk.h\"\n+\n+/**\n+ * ring block buffer object initialization\n+ *\n+ * @param rbb ring block buffer object\n+ * @param buf buffer\n+ * @param buf_size buffer size\n+ * @param block_set block set\n+ * @param blk_max_num max block number\n+ *\n+ * @note When your application need align access, please make the buffer address is aligned.\n+ */\n+void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num)\n+{\n+ uint32_t i;\n+\n+ assert(rbb);\n+ assert(buf);\n+ assert(block_set);\n+\n+ rbb->buf = buf;\n+ rbb->buf_size = buf_size;\n+ rbb->blk_set = block_set;\n+ rbb->blk_max_num = blk_max_num;\n+ utils_slist_init(&rbb->blk_list);\n+ /* initialize block status */\n+ for (i = 0; i < blk_max_num; i++)\n+ {\n+ block_set[i].status = RBB_BLK_UNUSED;\n+ }\n+}\n+\n+\n+/**\n+ * ring block buffer object create\n+ *\n+ * @param buf_size buffer size\n+ * @param blk_max_num max block number\n+ *\n+ * @return != NULL: ring block buffer object\n+ * NULL: create failed\n+ */\n+utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num)\n+{\n+ utils_rbb_t rbb = NULL;\n+ uint8_t *buf;\n+ utils_rbb_blk_t blk_set;\n+\n+ rbb = (utils_rbb_t)pvPortMalloc(sizeof(struct utils_rbb));\n+ if (!rbb)\n+ {\n+ return NULL;\n+ }\n+\n+ buf = (uint8_t *)pvPortMalloc(buf_size);\n+ if (!buf)\n+ {\n+ vPortFree(rbb);\n+ return NULL;\n+ }\n+\n+ blk_set = (utils_rbb_blk_t)pvPortMalloc(sizeof(struct utils_rbb_blk) * blk_max_num);\n+ if (!blk_set)\n+ {\n+ vPortFree(buf);\n+ vPortFree(rbb);\n+ return NULL;\n+ }\n+\n+ utils_rbb_init(rbb, buf, buf_size, blk_set, blk_max_num);\n+\n+ return rbb;\n+}\n+\n+/**\n+ * ring block buffer object destroy\n+ *\n+ * @param rbb ring block buffer object\n+ */\n+void utils_rbb_destroy(utils_rbb_t rbb)\n+{\n+ assert(rbb);\n+\n+ vPortFree(rbb->buf);\n+ vPortFree(rbb->blk_set);\n+ vPortFree(rbb);\n+\n+}\n+\n+utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb)\n+{\n+ uint32_t i;\n+\n+ assert(rbb);\n+\n+ for (i = 0; i < rbb->blk_max_num; i ++)\n+ {\n+ if (rbb->blk_set[i].status != RBB_BLK_UNUSED)\n+ {\n+ return &rbb->blk_set[i];\n+ }\n+ }\n+\n+ return NULL;\n+}\n+\n+utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb)\n+{\n+ uint32_t i;\n+\n+ assert(rbb);\n+\n+ for (i = 0; i < rbb->blk_max_num; i ++)\n+ {\n+ if (rbb->blk_set[i].status == RBB_BLK_UNUSED)\n+ {\n+ return &rbb->blk_set[i];\n+ }\n+ }\n+\n+ return NULL;\n+}\n+\n+/**\n+ * Allocate a block by given size. The block will add to blk_list when allocate success.\n+ *\n+ * @param rbb ring block buffer object\n+ * @param blk_size block size\n+ *\n+ * @note When your application need align access, please make the blk_szie is aligned.\n+ *\n+ * @return != NULL: allocated block\n+ * NULL: allocate failed\n+ */\n+utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size)\n+{\n+ uint32_t empty1 = 0, empty2 = 0;\n+ utils_rbb_blk_t head, tail, new_rbb = NULL;\n+ int list_num = 0;\n+\n+ assert(rbb);\n+ assert(blk_size < (1L << 24));\n+\n+ portENTER_CRITICAL();\n+\n+ new_rbb = utils_rbb_find_empty_blk(rbb);\n+\n+ list_num = utils_slist_entry_number(&rbb->blk_list);\n+\n+ if (list_num < rbb->blk_max_num && new_rbb)\n+ {\n+ if (list_num > 0)\n+ {\n+ head = utils_slist_first_entry(&rbb->blk_list, struct utils_rbb_blk, list);\n+ tail = utils_slist_tail_entry(&rbb->blk_list, struct utils_rbb_blk, list);\n+ if (head->buf <= tail->buf)\n+ {\n+ /**\n+ * head tail\n+ * +--------------------------------------+-----------------+------------------+\n+ * | empty2 | block1 | block2 | block3 | empty1 |\n+ * +--------------------------------------+-----------------+------------------+\n+ * rbb->buf\n+ */\n+ empty1 = (rbb->buf + rbb->buf_size) - (tail->buf + tail->size);\n+ empty2 = head->buf - rbb->buf;\n+\n+ if (empty1 >= blk_size)\n+ {\n+ utils_slist_append(&rbb->blk_list, &new_rbb->list);\n+ new_rbb->status = RBB_BLK_INITED;\n+ new_rbb->buf = tail->buf + tail->size;\n+ new_rbb->size = blk_size;\n+ }\n+ else if (empty2 >= blk_size)\n+ {\n+ utils_slist_append(&rbb->blk_list, &new_rbb->list);\n+ new_rbb->status = RBB_BLK_INITED;\n+ new_rbb->buf = rbb->buf;\n+ new_rbb->size = blk_size;\n+ }\n+ else\n+ {\n+ /* no space */\n+ new_rbb = NULL;\n+ }\n+ }\n+ else\n+ {\n+ /**\n+ * tail head\n+ * +----------------+-------------------------------------+--------+-----------+\n+ * | block3 | empty1 | block1 | block2 |\n+ * +----------------+-------------------------------------+--------+-----------+\n+ * rbb->buf\n+ */\n+ empty1 = head->buf - (tail->buf + tail->size);\n+\n+ if (empty1 >= blk_size)\n+ {\n+ utils_slist_append(&rbb->blk_list, &new_rbb->list);\n+ new_rbb->status = RBB_BLK_INITED;\n+ new_rbb->buf = tail->buf + tail->size;\n+ new_rbb->size = blk_size;\n+ }\n+ else\n+ {\n+ /* no space */\n+ new_rbb = NULL;\n+ }\n+ }\n+ }\n+ else\n+ {\n+ /* the list is empty */\n+ utils_slist_append(&rbb->blk_list, &new_rbb->list);\n+ new_rbb->status = RBB_BLK_INITED;\n+ new_rbb->buf = rbb->buf;\n+ new_rbb->size = blk_size;\n+ }\n+ }\n+ else\n+ {\n+ new_rbb = NULL;\n+ }\n+\n+ portEXIT_CRITICAL();\n+\n+ return new_rbb;\n+}\n+\n+/**\n+ * put a block to ring block buffer object\n+ *\n+ * @param block the block\n+ */\n+void utils_rbb_blk_put(utils_rbb_blk_t block)\n+{\n+ assert(block);\n+ assert(block->status == RBB_BLK_INITED);\n+\n+ block->status = RBB_BLK_PUT;\n+}\n+\n+/**\n+ * get a block from the ring block buffer object\n+ *\n+ * @param rbb ring block buffer object\n+ *\n+ * @return != NULL: block\n+ * NULL: get failed\n+ */\n+utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb)\n+{\n+ utils_rbb_blk_t block = NULL;\n+ utils_slist_t *node;\n+\n+ assert(rbb);\n+\n+ if (utils_slist_empty(&rbb->blk_list))\n+ return 0;\n+\n+ portENTER_CRITICAL();\n+\n+ for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))\n+ {\n+ block = utils_slist_entry(node, struct utils_rbb_blk, list);\n+ if (block->status == RBB_BLK_PUT)\n+ {\n+ block->status = RBB_BLK_GET;\n+ goto __exit;\n+ }\n+ }\n+ /* not found */\n+ block = NULL;\n+\n+__exit:\n+\n+ portEXIT_CRITICAL();\n+\n+ return block;\n+}\n+\n+/**\n+ * return the block size\n+ *\n+ * @param block the block\n+ *\n+ * @return block size\n+ */\n+uint32_t utils_rbb_blk_size(utils_rbb_blk_t block)\n+{\n+ assert(block);\n+\n+ return block->size;\n+}\n+\n+/**\n+ * return the block buffer\n+ *\n+ * @param block the block\n+ *\n+ * @return block buffer\n+ */\n+uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block)\n+{\n+ assert(block);\n+\n+ return block->buf;\n+}\n+\n+/**\n+ * free the block\n+ *\n+ * @param rbb ring block buffer object\n+ * @param block the block\n+ */\n+void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block)\n+{\n+ assert(rbb);\n+ assert(block);\n+ assert(block->status != RBB_BLK_UNUSED);\n+\n+ portENTER_CRITICAL();\n+\n+ /* remove it on rbb block list */\n+ utils_slist_del(&block->list, &rbb->blk_list);\n+\n+ block->status = RBB_BLK_UNUSED;\n+\n+ portEXIT_CRITICAL();\n+}\n+\n+/**\n+ * get a continuous block to queue by given size\n+ *\n+ * tail head\n+ * +------------------+---------------+--------+----------+--------+\n+ * | block3 | empty1 | block1 | block2 |fragment|\n+ * +------------------+------------------------+----------+--------+\n+ * |<-- return_size -->| |\n+ * |<--- queue_data_len --->|\n+ *\n+ * tail head\n+ * +------------------+---------------+--------+----------+--------+\n+ * | block3 | empty1 | block1 | block2 |fragment|\n+ * +------------------+------------------------+----------+--------+\n+ * |<-- return_size -->| out of len(b1+b2+b3) |\n+ * |<-------------------- queue_data_len -------------------->|\n+ *\n+ * @param rbb ring block buffer object\n+ * @param queue_data_len The max queue data size, and the return size must less then it.\n+ * @param queue continuous block queue\n+ *\n+ * @return the block queue data total size\n+ */\n+uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue)\n+{\n+ uint32_t data_total_size = 0;\n+ utils_slist_t *node;\n+ utils_rbb_blk_t last_block = NULL, block;\n+\n+ assert(rbb);\n+ assert(blk_queue);\n+\n+ if (utils_slist_empty(&rbb->blk_list))\n+ return 0;\n+\n+ portENTER_CRITICAL();\n+\n+ for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))\n+ {\n+ if (!last_block)\n+ {\n+ last_block = utils_slist_entry(node, struct utils_rbb_blk, list);\n+ if (last_block->status == RBB_BLK_PUT)\n+ {\n+ /* save the first put status block to queue */\n+ blk_queue->blocks = last_block;\n+ blk_queue->blk_num = 0;\n+ }\n+ else\n+ {\n+ /* the first block must be put status */\n+ last_block = NULL;\n+ continue;\n+ }\n+ }\n+ else\n+ {\n+ block = utils_slist_entry(node, struct utils_rbb_blk, list);\n+ /*\n+ * these following conditions will break the loop:\n+ * 1. the current block is not put status\n+ * 2. the last block and current block is not continuous\n+ * 3. the data_total_size will out of range\n+ */\n+ if (block->status != RBB_BLK_PUT ||\n+ last_block->buf > block->buf ||\n+ data_total_size + block->size > queue_data_len)\n+ {\n+ break;\n+ }\n+ /* backup last block */\n+ last_block = block;\n+ }\n+ /* remove current block */\n+ utils_slist_del(&last_block->list, &rbb->blk_list);\n+ data_total_size += last_block->size;\n+ last_block->status = RBB_BLK_GET;\n+ blk_queue->blk_num++;\n+ }\n+\n+ portEXIT_CRITICAL();\n+\n+ return data_total_size;\n+}\n+\n+/**\n+ * get all block length on block queue\n+ *\n+ * @param blk_queue the block queue\n+ *\n+ * @return total length\n+ */\n+uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue)\n+{\n+ uint32_t i, data_total_size = 0;\n+\n+ assert(blk_queue);\n+\n+ for (i = 0; i < blk_queue->blk_num; i++)\n+ {\n+ data_total_size += blk_queue->blocks[i].size;\n+ }\n+\n+ return data_total_size;\n+}\n+\n+/**\n+ * return the block queue buffer\n+ *\n+ * @param blk_queue the block queue\n+ *\n+ * @return block queue buffer\n+ */\n+uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue)\n+{\n+ assert(blk_queue);\n+\n+ return blk_queue->blocks[0].buf;\n+}\n+\n+/**\n+ * free the block queue\n+ *\n+ * @param rbb ring block buffer object\n+ * @param blk_queue the block queue\n+ */\n+void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue)\n+{\n+ uint32_t i;\n+\n+ assert(rbb);\n+ assert(blk_queue);\n+\n+ for (i = 0; i < blk_queue->blk_num; i++)\n+ {\n+ utils_rbb_blk_free(rbb, &blk_queue->blocks[i]);\n+ }\n+}\n+\n+/**\n+ * The put status and buffer continuous blocks can be make a block queue.\n+ * This function will return the length which from next can be make block queue.\n+ *\n+ * @param rbb ring block buffer object\n+ *\n+ * @return the next can be make block queue's length\n+ */\n+uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb)\n+{\n+ uint32_t data_len = 0;\n+ utils_slist_t *node;\n+ utils_rbb_blk_t last_block = NULL, block;\n+\n+ assert(rbb);\n+\n+ if (utils_slist_empty(&rbb->blk_list))\n+ return 0;\n+\n+ portENTER_CRITICAL();\n+\n+ for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))\n+ {\n+ if (!last_block)\n+ {\n+ last_block = utils_slist_entry(node, struct utils_rbb_blk, list);\n+ if (last_block->status != RBB_BLK_PUT)\n+ {\n+ /* the first block must be put status */\n+ last_block = NULL;\n+ continue;\n+ }\n+ }\n+ else\n+ {\n+ block = utils_slist_entry(node, struct utils_rbb_blk, list);\n+ /*\n+ * these following conditions will break the loop:\n+ * 1. the current block is not put status\n+ * 2. the last block and current block is not continuous\n+ */\n+ if (block->status != RBB_BLK_PUT || last_block->buf > block->buf)\n+ {\n+ break;\n+ }\n+ /* backup last block */\n+ last_block = block;\n+ }\n+ data_len += last_block->size;\n+ }\n+\n+ portEXIT_CRITICAL();\n+\n+ return data_len;\n+}\n+\n+/**\n+ * get the ring block buffer object buffer size\n+ *\n+ * @param rbb ring block buffer object\n+ *\n+ * @return buffer size\n+ */\n+uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb)\n+{\n+ assert(rbb);\n+\n+ return rbb->buf_size;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_sha1.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha1.c b/bsp/bl808/m0/libraries/utils/src/utils_sha1.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..fca165c917920598f75460be2cc96db5156b0fc6\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_sha1.c\n@@ -0,0 +1,355 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifdef UTILS_SHA1\n+\n+\n+#include <stdlib.h>\n+#include <string.h>\n+#include \"iot_import.h\"\n+#include \"iotx_log.h\"\n+#include \"utils_sha1.h\"\n+\n+/* Implementation that should never be optimized out by the compiler */\n+static void utils_sha1_zeroize(void *v, size_t n)\n+{\n+ volatile unsigned char *p = v;\n+ while (n--) {\n+ *p++ = 0;\n+ }\n+}\n+\n+/*\n+ * 32-bit integer manipulation macros (big endian)\n+ */\n+#ifndef IOT_SHA1_GET_UINT32_BE\n+#define IOT_SHA1_GET_UINT32_BE(n,b,i) \\\n+ { \\\n+ (n) = ( (uint32_t) (b)[(i) ] << 24 ) \\\n+ | ( (uint32_t) (b)[(i) + 1] << 16 ) \\\n+ | ( (uint32_t) (b)[(i) + 2] << 8 ) \\\n+ | ( (uint32_t) (b)[(i) + 3] ); \\\n+ }\n+#endif\n+\n+#ifndef IOT_SHA1_PUT_UINT32_BE\n+#define IOT_SHA1_PUT_UINT32_BE(n,b,i) \\\n+ { \\\n+ (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \\\n+ (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \\\n+ (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \\\n+ (b)[(i) + 3] = (unsigned char) ( (n) ); \\\n+ }\n+#endif\n+\n+void utils_sha1_init(iot_sha1_context *ctx)\n+{\n+ memset(ctx, 0, sizeof(iot_sha1_context));\n+}\n+\n+void utils_sha1_free(iot_sha1_context *ctx)\n+{\n+ if (ctx == NULL) {\n+ return;\n+ }\n+\n+ utils_sha1_zeroize(ctx, sizeof(iot_sha1_context));\n+}\n+\n+void utils_sha1_clone(iot_sha1_context *dst,\n+ const iot_sha1_context *src)\n+{\n+ *dst = *src;\n+}\n+\n+/*\n+ * SHA-1 context setup\n+ */\n+void utils_sha1_starts(iot_sha1_context *ctx)\n+{\n+ ctx->total[0] = 0;\n+ ctx->total[1] = 0;\n+\n+ ctx->state[0] = 0x67452301;\n+ ctx->state[1] = 0xEFCDAB89;\n+ ctx->state[2] = 0x98BADCFE;\n+ ctx->state[3] = 0x10325476;\n+ ctx->state[4] = 0xC3D2E1F0;\n+}\n+\n+void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64])\n+{\n+ uint32_t temp, W[16], A, B, C, D, E;\n+\n+ IOT_SHA1_GET_UINT32_BE(W[ 0], data, 0);\n+ IOT_SHA1_GET_UINT32_BE(W[ 1], data, 4);\n+ IOT_SHA1_GET_UINT32_BE(W[ 2], data, 8);\n+ IOT_SHA1_GET_UINT32_BE(W[ 3], data, 12);\n+ IOT_SHA1_GET_UINT32_BE(W[ 4], data, 16);\n+ IOT_SHA1_GET_UINT32_BE(W[ 5], data, 20);\n+ IOT_SHA1_GET_UINT32_BE(W[ 6], data, 24);\n+ IOT_SHA1_GET_UINT32_BE(W[ 7], data, 28);\n+ IOT_SHA1_GET_UINT32_BE(W[ 8], data, 32);\n+ IOT_SHA1_GET_UINT32_BE(W[ 9], data, 36);\n+ IOT_SHA1_GET_UINT32_BE(W[10], data, 40);\n+ IOT_SHA1_GET_UINT32_BE(W[11], data, 44);\n+ IOT_SHA1_GET_UINT32_BE(W[12], data, 48);\n+ IOT_SHA1_GET_UINT32_BE(W[13], data, 52);\n+ IOT_SHA1_GET_UINT32_BE(W[14], data, 56);\n+ IOT_SHA1_GET_UINT32_BE(W[15], data, 60);\n+\n+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))\n+\n+#define R(t) \\\n+ ( \\\n+ temp = W[( t - 3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \\\n+ W[( t - 14 ) & 0x0F] ^ W[ t & 0x0F], \\\n+ ( W[t & 0x0F] = S(temp,1) ) \\\n+ )\n+\n+#define P(a,b,c,d,e,x) \\\n+ { \\\n+ e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \\\n+ }\n+\n+ A = ctx->state[0];\n+ B = ctx->state[1];\n+ C = ctx->state[2];\n+ D = ctx->state[3];\n+ E = ctx->state[4];\n+\n+#define F(x,y,z) (z ^ (x & (y ^ z)))\n+#define K 0x5A827999\n+\n+ P(A, B, C, D, E, W[0]);\n+ P(E, A, B, C, D, W[1]);\n+ P(D, E, A, B, C, W[2]);\n+ P(C, D, E, A, B, W[3]);\n+ P(B, C, D, E, A, W[4]);\n+ P(A, B, C, D, E, W[5]);\n+ P(E, A, B, C, D, W[6]);\n+ P(D, E, A, B, C, W[7]);\n+ P(C, D, E, A, B, W[8]);\n+ P(B, C, D, E, A, W[9]);\n+ P(A, B, C, D, E, W[10]);\n+ P(E, A, B, C, D, W[11]);\n+ P(D, E, A, B, C, W[12]);\n+ P(C, D, E, A, B, W[13]);\n+ P(B, C, D, E, A, W[14]);\n+ P(A, B, C, D, E, W[15]);\n+ P(E, A, B, C, D, R(16));\n+ P(D, E, A, B, C, R(17));\n+ P(C, D, E, A, B, R(18));\n+ P(B, C, D, E, A, R(19));\n+\n+#undef K\n+#undef F\n+\n+#define F(x,y,z) (x ^ y ^ z)\n+#define K 0x6ED9EBA1\n+\n+ P(A, B, C, D, E, R(20));\n+ P(E, A, B, C, D, R(21));\n+ P(D, E, A, B, C, R(22));\n+ P(C, D, E, A, B, R(23));\n+ P(B, C, D, E, A, R(24));\n+ P(A, B, C, D, E, R(25));\n+ P(E, A, B, C, D, R(26));\n+ P(D, E, A, B, C, R(27));\n+ P(C, D, E, A, B, R(28));\n+ P(B, C, D, E, A, R(29));\n+ P(A, B, C, D, E, R(30));\n+ P(E, A, B, C, D, R(31));\n+ P(D, E, A, B, C, R(32));\n+ P(C, D, E, A, B, R(33));\n+ P(B, C, D, E, A, R(34));\n+ P(A, B, C, D, E, R(35));\n+ P(E, A, B, C, D, R(36));\n+ P(D, E, A, B, C, R(37));\n+ P(C, D, E, A, B, R(38));\n+ P(B, C, D, E, A, R(39));\n+\n+#undef K\n+#undef F\n+\n+#define F(x,y,z) ((x & y) | (z & (x | y)))\n+#define K 0x8F1BBCDC\n+\n+ P(A, B, C, D, E, R(40));\n+ P(E, A, B, C, D, R(41));\n+ P(D, E, A, B, C, R(42));\n+ P(C, D, E, A, B, R(43));\n+ P(B, C, D, E, A, R(44));\n+ P(A, B, C, D, E, R(45));\n+ P(E, A, B, C, D, R(46));\n+ P(D, E, A, B, C, R(47));\n+ P(C, D, E, A, B, R(48));\n+ P(B, C, D, E, A, R(49));\n+ P(A, B, C, D, E, R(50));\n+ P(E, A, B, C, D, R(51));\n+ P(D, E, A, B, C, R(52));\n+ P(C, D, E, A, B, R(53));\n+ P(B, C, D, E, A, R(54));\n+ P(A, B, C, D, E, R(55));\n+ P(E, A, B, C, D, R(56));\n+ P(D, E, A, B, C, R(57));\n+ P(C, D, E, A, B, R(58));\n+ P(B, C, D, E, A, R(59));\n+\n+#undef K\n+#undef F\n+\n+#define F(x,y,z) (x ^ y ^ z)\n+#define K 0xCA62C1D6\n+\n+ P(A, B, C, D, E, R(60));\n+ P(E, A, B, C, D, R(61));\n+ P(D, E, A, B, C, R(62));\n+ P(C, D, E, A, B, R(63));\n+ P(B, C, D, E, A, R(64));\n+ P(A, B, C, D, E, R(65));\n+ P(E, A, B, C, D, R(66));\n+ P(D, E, A, B, C, R(67));\n+ P(C, D, E, A, B, R(68));\n+ P(B, C, D, E, A, R(69));\n+ P(A, B, C, D, E, R(70));\n+ P(E, A, B, C, D, R(71));\n+ P(D, E, A, B, C, R(72));\n+ P(C, D, E, A, B, R(73));\n+ P(B, C, D, E, A, R(74));\n+ P(A, B, C, D, E, R(75));\n+ P(E, A, B, C, D, R(76));\n+ P(D, E, A, B, C, R(77));\n+ P(C, D, E, A, B, R(78));\n+ P(B, C, D, E, A, R(79));\n+\n+#undef K\n+#undef F\n+\n+ ctx->state[0] += A;\n+ ctx->state[1] += B;\n+ ctx->state[2] += C;\n+ ctx->state[3] += D;\n+ ctx->state[4] += E;\n+}\n+\n+/*\n+ * SHA-1 process buffer\n+ */\n+void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen)\n+{\n+ size_t fill;\n+ uint32_t left;\n+\n+ if (ilen == 0) {\n+ return;\n+ }\n+\n+ left = ctx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ ctx->total[0] += (uint32_t) ilen;\n+ ctx->total[0] &= 0xFFFFFFFF;\n+\n+ if (ctx->total[0] < (uint32_t) ilen) {\n+ ctx->total[1]++;\n+ }\n+\n+ if (left && ilen >= fill) {\n+ memcpy((void *)(ctx->buffer + left), input, fill);\n+ utils_sha1_process(ctx, ctx->buffer);\n+ input += fill;\n+ ilen -= fill;\n+ left = 0;\n+ }\n+\n+ while (ilen >= 64) {\n+ utils_sha1_process(ctx, input);\n+ input += 64;\n+ ilen -= 64;\n+ }\n+\n+ if (ilen > 0) {\n+ memcpy((void *)(ctx->buffer + left), input, ilen);\n+ }\n+}\n+\n+static const unsigned char iot_sha1_padding[64] = {\n+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\n+};\n+\n+/*\n+ * SHA-1 final digest\n+ */\n+void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20])\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ unsigned char msglen[8];\n+\n+ high = (ctx->total[0] >> 29)\n+ | (ctx->total[1] << 3);\n+ low = (ctx->total[0] << 3);\n+\n+ IOT_SHA1_PUT_UINT32_BE(high, msglen, 0);\n+ IOT_SHA1_PUT_UINT32_BE(low, msglen, 4);\n+\n+ last = ctx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ utils_sha1_update(ctx, iot_sha1_padding, padn);\n+ utils_sha1_update(ctx, msglen, 8);\n+\n+ IOT_SHA1_PUT_UINT32_BE(ctx->state[0], output, 0);\n+ IOT_SHA1_PUT_UINT32_BE(ctx->state[1], output, 4);\n+ IOT_SHA1_PUT_UINT32_BE(ctx->state[2], output, 8);\n+ IOT_SHA1_PUT_UINT32_BE(ctx->state[3], output, 12);\n+ IOT_SHA1_PUT_UINT32_BE(ctx->state[4], output, 16);\n+}\n+\n+\n+/*\n+ * output = SHA-1( input buffer )\n+ */\n+void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20])\n+{\n+ iot_sha1_context ctx;\n+\n+ utils_sha1_init(&ctx);\n+ utils_sha1_starts(&ctx);\n+ utils_sha1_update(&ctx, input, ilen);\n+ utils_sha1_finish(&ctx, output);\n+ utils_sha1_free(&ctx);\n+}\n+\n+#endif\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_sha256.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha256.c b/bsp/bl808/m0/libraries/utils/src/utils_sha256.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..98b4e2d28db731aefbd63f8fa504092548e8ec6b\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_sha256.c\n@@ -0,0 +1,299 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdlib.h>\n+#include <string.h>\n+#include <stdint.h>\n+#include \"utils_sha256.h\"\n+\n+#define SHA256_KEY_IOPAD_SIZE (64)\n+#define SHA256_DIGEST_SIZE (32)\n+\n+/*\n+ * 32-bit integer manipulation macros (big endian)\n+ */\n+#ifndef GET_UINT32_BE\n+#define GET_UINT32_BE(n,b,i) \\\n+ do { \\\n+ (n) = ( (uint32_t) (b)[(i) ] << 24 ) \\\n+ | ( (uint32_t) (b)[(i) + 1] << 16 ) \\\n+ | ( (uint32_t) (b)[(i) + 2] << 8 ) \\\n+ | ( (uint32_t) (b)[(i) + 3] ); \\\n+ } while( 0 )\n+#endif\n+\n+#ifndef PUT_UINT32_BE\n+#define PUT_UINT32_BE(n,b,i) \\\n+ do { \\\n+ (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \\\n+ (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \\\n+ (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \\\n+ (b)[(i) + 3] = (unsigned char) ( (n) ); \\\n+ } while( 0 )\n+#endif\n+\n+\n+static void utils_sha256_zeroize(void *v, uint32_t n)\n+{\n+ volatile unsigned char *p = v;\n+ while (n--) {\n+ *p++ = 0;\n+ }\n+}\n+void utils_sha256_init(iot_sha256_context *ctx)\n+{\n+ memset(ctx, 0, sizeof(iot_sha256_context));\n+}\n+void utils_sha256_free(iot_sha256_context *ctx)\n+{\n+ if (NULL == ctx) {\n+ return;\n+ }\n+\n+ utils_sha256_zeroize(ctx, sizeof(iot_sha256_context));\n+}\n+void utils_sha256_clone(iot_sha256_context *dst,\n+ const iot_sha256_context *src)\n+{\n+ *dst = *src;\n+}\n+void utils_sha256_starts(iot_sha256_context *ctx)\n+{\n+ int is224 = 0;\n+ ctx->total[0] = 0;\n+ ctx->total[1] = 0;\n+\n+ if (is224 == 0) {\n+ /* SHA-256 */\n+ ctx->state[0] = 0x6A09E667;\n+ ctx->state[1] = 0xBB67AE85;\n+ ctx->state[2] = 0x3C6EF372;\n+ ctx->state[3] = 0xA54FF53A;\n+ ctx->state[4] = 0x510E527F;\n+ ctx->state[5] = 0x9B05688C;\n+ ctx->state[6] = 0x1F83D9AB;\n+ ctx->state[7] = 0x5BE0CD19;\n+ }\n+\n+ ctx->is224 = is224;\n+}\n+\n+static const uint32_t K[] = {\n+ 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,\n+ 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,\n+ 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,\n+ 0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,\n+ 0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,\n+ 0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,\n+ 0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,\n+ 0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,\n+ 0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,\n+ 0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,\n+ 0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,\n+ 0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,\n+ 0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,\n+ 0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,\n+ 0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,\n+ 0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,\n+};\n+\n+#define SHR(x,n) ((x & 0xFFFFFFFF) >> n)\n+#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))\n+\n+#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3))\n+#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10))\n+\n+#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))\n+#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))\n+\n+#define F0(x,y,z) ((x & y) | (z & (x | y)))\n+#define F1(x,y,z) (z ^ (x & (y ^ z)))\n+\n+#define R(t) \\\n+ ( \\\n+ W[t] = S1(W[t - 2]) + W[t - 7] + \\\n+ S0(W[t - 15]) + W[t - 16] \\\n+ )\n+\n+#define P(a,b,c,d,e,f,g,h,x,K) \\\n+ { \\\n+ temp1 = h + S3(e) + F1(e,f,g) + K + x; \\\n+ temp2 = S2(a) + F0(a,b,c); \\\n+ d += temp1; h = temp1 + temp2; \\\n+ }\n+\n+void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64])\n+{\n+ uint32_t temp1, temp2, W[64];\n+ uint32_t A[8];\n+ unsigned int i;\n+\n+ for (i = 0; i < 8; i++) {\n+ A[i] = ctx->state[i];\n+ }\n+\n+#if defined(INFRA_SHA256_SMALLER)\n+ for (i = 0; i < 64; i++) {\n+ if (i < 16) {\n+ GET_UINT32_BE(W[i], data, 4 * i);\n+ } else {\n+ R(i);\n+ }\n+\n+ P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i]);\n+\n+ temp1 = A[7];\n+ A[7] = A[6];\n+ A[6] = A[5];\n+ A[5] = A[4];\n+ A[4] = A[3];\n+ A[3] = A[2];\n+ A[2] = A[1];\n+ A[1] = A[0];\n+ A[0] = temp1;\n+ }\n+#else /* INFRA_SHA256_SMALLER */\n+ for (i = 0; i < 16; i++) {\n+ GET_UINT32_BE(W[i], data, 4 * i);\n+ }\n+\n+ for (i = 0; i < 16; i += 8) {\n+ P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i + 0], K[i + 0]);\n+ P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i + 1], K[i + 1]);\n+ P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i + 2], K[i + 2]);\n+ P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i + 3], K[i + 3]);\n+ P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i + 4], K[i + 4]);\n+ P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i + 5], K[i + 5]);\n+ P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i + 6], K[i + 6]);\n+ P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i + 7], K[i + 7]);\n+ }\n+\n+ for (i = 16; i < 64; i += 8) {\n+ P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i + 0), K[i + 0]);\n+ P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i + 1), K[i + 1]);\n+ P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i + 2), K[i + 2]);\n+ P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i + 3), K[i + 3]);\n+ P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i + 4), K[i + 4]);\n+ P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i + 5), K[i + 5]);\n+ P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i + 6), K[i + 6]);\n+ P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i + 7), K[i + 7]);\n+ }\n+#endif /* INFRA_SHA256_SMALLER */\n+\n+ for (i = 0; i < 8; i++) {\n+ ctx->state[i] += A[i];\n+ }\n+}\n+void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen)\n+{\n+ size_t fill;\n+ uint32_t left;\n+\n+ if (ilen == 0) {\n+ return;\n+ }\n+\n+ left = ctx->total[0] & 0x3F;\n+ fill = 64 - left;\n+\n+ ctx->total[0] += (uint32_t) ilen;\n+ ctx->total[0] &= 0xFFFFFFFF;\n+\n+ if (ctx->total[0] < (uint32_t) ilen) {\n+ ctx->total[1]++;\n+ }\n+\n+ if (left && ilen >= fill) {\n+ memcpy((void *)(ctx->buffer + left), input, fill);\n+ utils_sha256_process(ctx, ctx->buffer);\n+ input += fill;\n+ ilen -= fill;\n+ left = 0;\n+ }\n+\n+ while (ilen >= 64) {\n+ utils_sha256_process(ctx, input);\n+ input += 64;\n+ ilen -= 64;\n+ }\n+\n+ if (ilen > 0) {\n+ memcpy((void *)(ctx->buffer + left), input, ilen);\n+ }\n+}\n+\n+static const unsigned char sha256_padding[64] = {\n+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\n+};\n+\n+void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32])\n+{\n+ uint32_t last, padn;\n+ uint32_t high, low;\n+ unsigned char msglen[8];\n+\n+ high = (ctx->total[0] >> 29)\n+ | (ctx->total[1] << 3);\n+ low = (ctx->total[0] << 3);\n+\n+ PUT_UINT32_BE(high, msglen, 0);\n+ PUT_UINT32_BE(low, msglen, 4);\n+\n+ last = ctx->total[0] & 0x3F;\n+ padn = (last < 56) ? (56 - last) : (120 - last);\n+\n+ utils_sha256_update(ctx, sha256_padding, padn);\n+ utils_sha256_update(ctx, msglen, 8);\n+\n+ PUT_UINT32_BE(ctx->state[0], output, 0);\n+ PUT_UINT32_BE(ctx->state[1], output, 4);\n+ PUT_UINT32_BE(ctx->state[2], output, 8);\n+ PUT_UINT32_BE(ctx->state[3], output, 12);\n+ PUT_UINT32_BE(ctx->state[4], output, 16);\n+ PUT_UINT32_BE(ctx->state[5], output, 20);\n+ PUT_UINT32_BE(ctx->state[6], output, 24);\n+\n+ if (ctx->is224 == 0) {\n+ PUT_UINT32_BE(ctx->state[7], output, 28);\n+ }\n+}\n+\n+void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32])\n+{\n+ iot_sha256_context ctx;\n+\n+ utils_sha256_init(&ctx);\n+ utils_sha256_starts(&ctx);\n+ utils_sha256_update(&ctx, input, ilen);\n+ utils_sha256_finish(&ctx, output);\n+ utils_sha256_free(&ctx);\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_string.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_string.c b/bsp/bl808/m0/libraries/utils/src/utils_string.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6e6351264648655be082879822e8051637bfad61\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_string.c\n@@ -0,0 +1,427 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdint.h>\n+#include <stddef.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <utils_string.h>\n+\n+static int params_filter(char** params,uint32_t *r)\n+{\t\n+\tchar *p ;\n+\tuint32_t result=0;\n+\tuint8_t base=0;\n+\t\n+\tp = *params;\n+\t\n+ if((*p == '0') && ((*(p+1) == 'x') || (*(p+1) == 'X')) ){\n+\t\tp = p + 2;\n+\t\tbase = 16;\n+\t\t\n+\t}else{\n+\t\tbase = 10;\n+\t}\n+\t\n+\twhile(*p){\n+\t\tresult *= base;\n+\t if(*p >= '0' && *p<='9')\n+\t\t\tresult += *p-'0';\n+\t\telse if(base==10)\n+\t\t\treturn -1;\n+\t\t\t\n+\t\tif(base==16){\n+\t\t\tif(*p >= 'a' && *p<='f')\n+\t\t\t\tresult += *p-'a' + 10;\n+\t\t\telse if(*p >= 'A' && *p<='F')\n+\t\t\t\tresult += *p-'A' + 10;\n+\t\t\n+\t\t}\n+\t\tp++;\n+\t}\n+\t\t\n+\t*r = result;\n+\treturn 0;\n+\t\n+}\n+\n+\n+void get_bytearray_from_string(char** params, uint8_t *result,int array_size)\n+{\n+ \n+ int i = 0;\n+ char rand[3];\n+\n+ for(i=0; i < array_size; i++){\n+ strncpy(rand, (const char*)*params, 2);\n+ rand[2]='\\0';\n+ result[i] = strtol(rand, NULL, 16);\n+ *params = *params + 2;\n+ }\n+}\n+\n+void get_uint8_from_string(char** params, uint8_t *result)\n+{\n+\tuint32_t p = 0;\n+\tint state=0;\n+\t\n+\tstate = params_filter(params,&p);\n+\tif(!state){\n+\t\t*result = p & 0xff;\n+\t}else\n+\t\t*result = 0;\n+}\n+\n+void get_uint16_from_string(char** params, uint16_t *result)\n+{\n+\tuint32_t p = 0;\n+\tint state=0;\n+\t\n+\tstate = params_filter(params,&p);\n+\tif(!state){\n+\t\t*result = p & 0xffff;\n+\t}else\n+\t\t*result = 0;\n+}\n+\n+void get_uint32_from_string(char** params, uint32_t *result)\n+{\n+ uint32_t p = 0;\n+\tint state=0;\n+\t\n+\tstate = params_filter(params,&p);\n+\tif(!state){\n+\t\t*result = p;\n+\t}else\n+\t\t*result = 0;\n+}\n+\n+void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base)\n+{\n+ int i;\n+ for (i = 0; i < buflen; i++) {\n+ buf[i] = (uint8_t)strtol(str, NULL, base);\n+ str = strchr(str, sep);\n+ if (str == NULL || *str == '\\0') {\n+ break;\n+ }\n+ str++;\n+ }\n+}\n+\n+void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count)\n+{\n+ int i;\n+\n+ for (i = 0; i < buflen; i++) {\n+ buf[i] = (uint8_t)strtol(str, NULL, base);\n+ str = strchr(str, sep);\n+ if (str == NULL || *str == '\\0') {\n+ break;\n+ }\n+ str++;\n+ }\n+ *count = (i + 1);\n+}\n+\n+\n+unsigned long long convert_arrayToU64(uint8_t* inputArray)\n+{\n+ unsigned long long result = 0;\n+ for(uint8_t i = 0; i < 8; i++)\n+ {\n+ result <<= 8;\n+ result |= (unsigned long long)inputArray[7-i];\n+ }\n+\n+ return result;\n+}\n+\n+void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8])\n+{\n+ for(int i = 0; i < 8; i++)\n+ {\n+ result[i] = inputU64>>(i*8);\n+ }\n+}\n+\n+void utils_memcpy8(void *dst, void *src, size_t len)\n+{\n+ uint8_t *d = (uint8_t *)dst;\n+ uint8_t *s = (uint8_t *)src;\n+\n+ while (len--) {\n+ *d++ = *s++;\n+ }\n+}\n+\n+void utils_memcpy16(void *dst, void *src, size_t len)\n+{\n+ uint16_t *d = (uint16_t *)dst;\n+ uint16_t *s = (uint16_t *)src;\n+\n+ len >>= 1;//convert to half words\n+\n+ while (len--) {\n+ *d++ = *s++;\n+ }\n+}\n+\n+void utils_memcpy32(void *dst, void *src, size_t len)\n+{\n+ uint32_t *d = (uint32_t *)dst;\n+ uint32_t *s = (uint32_t *)src;\n+\n+ len >>= 2;//convert to words\n+\n+ while (len--) {\n+ *d++ = *s++;\n+ }\n+}\n+\n+void utils_memcpy64(void *dst, void *src, size_t len)\n+{\n+ uint64_t *d = (uint64_t *)dst;\n+ uint64_t *s = (uint64_t *)src;\n+\n+ len >>= 3;//convert to two words\n+\n+ while (len--) {\n+ *d++ = *s++;\n+ }\n+}\n+\n+void utils_memset8(void *src, uint8_t n, size_t len)\n+{\n+ uint8_t *s = (uint8_t *)src;\n+\n+ while (len--) {\n+ *s++ = n;\n+ }\n+}\n+\n+void utils_memset16(void *src, uint16_t n, size_t len)\n+{\n+ uint16_t *s = (uint16_t *)src;\n+\n+ len >>= 1;//convert to half words\n+\n+ while (len--) {\n+ *s++ = n;\n+ }\n+}\n+\n+void utils_memset32(void *src, uint32_t n, size_t len)\n+{\n+ uint32_t *s = (uint32_t *)src;\n+\n+ len >>= 2;//convert to words\n+\n+ while (len--) {\n+ *s++ = n;\n+ }\n+}\n+\n+void utils_memset64(void *src, uint64_t n, size_t len)\n+{\n+ uint64_t *s = (uint64_t *)src;\n+\n+ len >>= 3;//convert to two words\n+\n+ while (len--) {\n+ *s++ = n;\n+ }\n+}\n+\n+void utils_memset8_with_seq(void *src, uint8_t seq, size_t len)\n+{\n+ uint8_t *s = (uint8_t *)src;\n+\n+ while (len--) {\n+ *s++ = (seq++);\n+ }\n+}\n+\n+void utils_memset16_with_seq(void *src, uint16_t seq, size_t len)\n+{\n+ uint16_t *s = (uint16_t *)src;\n+\n+ len >>= 1;//convert to half words\n+\n+ while (len--) {\n+ *s++ = (seq++);\n+ }\n+}\n+\n+void utils_memset32_with_seq(void *src, uint32_t seq, size_t len)\n+{\n+ uint32_t *s = (uint32_t *)src;\n+\n+ len >>= 2;//convert to words\n+\n+ while (len--) {\n+ *s++ = (seq++);\n+ }\n+}\n+\n+void utils_memset64_with_seq(void *src, uint64_t seq, size_t len)\n+{\n+ uint64_t *s = (uint64_t *)src;\n+\n+ len >>= 3;//convert to two words\n+\n+ while (len--) {\n+ *s++ = (seq++);\n+ }\n+}\n+\n+void utils_memdrain8(void *src, size_t len)\n+{\n+ volatile uint8_t *s = (uint8_t *)src;\n+ uint8_t tmp;\n+\n+ while (len--) {\n+ tmp = *s++;\n+ }\n+\n+ (void)tmp;\n+}\n+\n+void utils_memdrain16(void *src, size_t len)\n+{\n+ volatile uint16_t *s = (uint16_t *)src;\n+ uint16_t tmp;\n+\n+ len >>= 1;//convert to half words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ }\n+ \n+ (void)tmp;\n+}\n+\n+void utils_memdrain32(void *src, size_t len)\n+{\n+ volatile uint32_t *s = (uint32_t *)src;\n+ uint32_t tmp;\n+\n+ len >>= 2;//convert to words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ }\n+ \n+ (void)tmp;\n+}\n+\n+void utils_memdrain64(void *src, size_t len)\n+{\n+ volatile uint64_t *s = (uint64_t *)src;\n+ uint64_t tmp;\n+\n+ len >>= 3;//convert to two words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ }\n+ \n+ (void)tmp;\n+}\n+\n+void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq)\n+{\n+ volatile uint8_t *s = (uint8_t *)src;\n+ uint8_t tmp;\n+\n+ (void)tmp;\n+\n+ while (len--) {\n+ tmp = *s++;\n+ if((seq++) != tmp){\n+ return (uint8_t *)s-1;\n+ }\n+ }\n+\n+ return NULL; \n+}\n+\n+void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq)\n+{\n+ volatile uint16_t *s = (uint16_t *)src;\n+ uint16_t tmp;\n+ (void)tmp;\n+\n+ len >>= 1;//convert to half words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ if((seq++) != tmp){\n+ return (uint16_t *)s-1;\n+ }\n+ }\n+ \n+ return NULL; \n+}\n+\n+void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq)\n+{\n+ volatile uint32_t *s = (uint32_t *)src;\n+ uint32_t tmp;\n+ (void)tmp;\n+\n+ len >>= 2;//convert to words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ if((seq++) != tmp){\n+ return (uint32_t *)s-1;\n+ }\n+ }\n+ \n+ return NULL; \n+}\n+\n+void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq)\n+{\n+ volatile uint64_t *s = (uint64_t *)src;\n+ uint64_t tmp;\n+ (void)tmp;\n+\n+ len >>= 3;//convert to two words\n+\n+ while (len--) {\n+ tmp = *s++;\n+ if((seq++) != tmp){\n+ return (uint64_t *)s-1;\n+ }\n+ }\n+ \n+ return NULL; \n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_time.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_time.c b/bsp/bl808/m0/libraries/utils/src/utils_time.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..6203b8b52bfd80b7a8a3d3a310946a906fa2e74d\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_time.c\n@@ -0,0 +1,96 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <stdlib.h>\n+#include <utils_time.h>\n+//Thu=4, Fri=5, Sat=6, Sun=0, Mon=1, Tue=2, Wed=3\n+\n+int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date)\n+{\n+ int i;\n+ unsigned short temp_days;\n+ unsigned char month_days[12]={31,28,31,30,31,30,31,31,30,31,30,31};\n+ unsigned char week_days[7] = {4,5,6,0,1,2,3};\n+\n+ date->leap_days = 0; \n+ date->leap_year_ind = 0;\n+\n+ // Add or substract time zone here. \n+ //epoch += 19800; //GMT +5:30 = +19800 seconds \n+\n+ date->ntp_second = epoch%60;\n+ epoch /= 60;\n+ date->ntp_minute = epoch%60;\n+ epoch /= 60;\n+ date->ntp_hour = epoch%24;\n+ epoch /= 24;\n+\n+ date->days_since_epoch = epoch; //number of days since epoch\n+ date->ntp_week_day = week_days[date->days_since_epoch%7]; //Calculating WeekDay\n+\n+ date->ntp_year = 1970 + (date->days_since_epoch/365); // ball parking year, may not be accurate!\n+ for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {\n+ // Calculating number of leap days since epoch/1970\n+ if(((i%4==0) && (i%100!=0)) || (i%400==0)) {\n+ date->leap_days++;\n+ }\n+ }\n+\n+ date->ntp_year = 1970 + ((date->days_since_epoch - date->leap_days)/365); // Calculating accurate current year by (days_since_epoch - extra leap days)\n+ if (((date->ntp_year%4==0) && (date->ntp_year%100!=0)) || (date->ntp_year%400==0)) {\n+ month_days[1]=29; //February = 29 days for leap years\n+ date->leap_year_ind = 1; //if current year is leap, set indicator to 1 \n+ } else {\n+ month_days[1]=28; //February = 28 days for non-leap years \n+ date->leap_year_ind = 0; //if current year is leap, set indicator to 1 \n+ }\n+ for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {\n+ // Calculating number of leap days since epoch/1970\n+ if(((i%4==0) && (i%100!=0)) || (i%400==0)) {\n+ date->leap_days++;\n+ }\n+ }\n+ date->day_of_year = date->days_since_epoch - date->leap_days - (date->ntp_year - 1970) * 365 + 1;\n+\n+\n+ temp_days = 0;\n+\n+ for (date->ntp_month = 0; date->ntp_month <= 11; date->ntp_month++) {\n+ //calculating current Month\n+ if (date->day_of_year <= temp_days) {\n+ break; \n+ }\n+ temp_days = temp_days + month_days[date->ntp_month];\n+ }\n+\n+ temp_days = temp_days - month_days[date->ntp_month-1]; //calculating current Date\n+ date->ntp_date = date->day_of_year - temp_days;\n+\n+ return 0;\n+}\n\n<|file_patch|>bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c\ndiff --git a/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c b/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0ec23c4daa830530818b86f1893b576b2675423e\n--- /dev/null\n+++ b/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c\n@@ -0,0 +1,184 @@\n+/*\n+ * Copyright (c) 2016-2022 Bouffalolab.\n+ *\n+ * This file is part of\n+ * *** Bouffalolab Software Dev Kit ***\n+ * (see www.bouffalolab.com).\n+ *\n+ * Redistribution and use in source and binary forms, with or without modification,\n+ * are permitted provided that the following conditions are met:\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ * 3. Neither the name of Bouffalo Lab nor the names of its contributors\n+ * may be used to endorse or promote products derived from this software\n+ * without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include \"utils_tlv_bl.h\"\n+\n+int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val)\n+{\n+ if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {\n+ return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;\n+ }\n+ *buf = val;//XXX caution for unaligned access\n+\n+ return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;\n+}\n+\n+int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val)\n+{\n+ if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {\n+ return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;\n+ }\n+ *buf = val;//XXX caution for unaligned access\n+\n+ return CFG_ELEMENT_TYPE_SIZE_UINT32;\n+}\n+\n+int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val)\n+{\n+ if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {\n+ return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;\n+ }\n+ *val = (*buf) ? true : false;// XXX caution for unaligned access\n+\n+ return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;\n+}\n+\n+int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val)\n+{\n+ if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {\n+ return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;\n+ }\n+ *val = (*buf);//XXX caution for unaligned access\n+\n+ return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;\n+}\n+\n+int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)\n+{\n+ int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;\n+\n+ switch (type) {\n+ case CFG_ELEMENT_TYPE_BOOLEAN:\n+ {\n+ ret = utils_tlv_bl_pack_bool(buf, buf_sz, *(bool*)arg1 ? true : false);\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT8:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT8:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT16:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT16:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT32:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT32:\n+ {\n+ ret = utils_tlv_bl_pack_uint32(buf, buf_sz, *(uint32_t*)arg1);\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_STRING:\n+ {\n+ //TODO\n+ }\n+ break;\n+ default:\n+ {\n+ /*empty*/\n+ }\n+ }\n+\n+ return ret;\n+}\n+\n+int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)\n+{\n+ int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;\n+\n+ switch (type) {\n+ case CFG_ELEMENT_TYPE_BOOLEAN:\n+ {\n+ bool val = true;\n+\n+ ret = utils_tlv_bl_unpack_bool(buf, buf_sz, &val);\n+ *(bool*)arg1 = val;\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT8:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT8:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT16:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT16:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_SINT32:\n+ {\n+ //TODO\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_UINT32:\n+ {\n+ uint32_t val = 0;\n+\n+ ret = utils_tlv_bl_unpack_uint32(buf, buf_sz, &val);\n+ *(uint32_t*)arg1 = val;\n+ }\n+ break;\n+ case CFG_ELEMENT_TYPE_STRING:\n+ {\n+ //TODO\n+ }\n+ break;\n+ default:\n+ {\n+ /*empty*/\n+ }\n+ }\n+\n+ return ret;\n+}\n\n<|file_patch|>bsp/bl808/m0/link_stacksize.lds\ndiff --git a/bsp/bl808/m0/link_stacksize.lds b/bsp/bl808/m0/link_stacksize.lds\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1dd893422c2e9b079747bd857dec99880b056715\n--- /dev/null\n+++ b/bsp/bl808/m0/link_stacksize.lds\n@@ -0,0 +1 @@\n+__STACKSIZE__ = 4096;\n\\ No newline at end of file\n\n<|file_patch|>bsp/bl808/m0/rtconfig.h\ndiff --git a/bsp/bl808/m0/rtconfig.h b/bsp/bl808/m0/rtconfig.h\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..41220bf217e243dc5da858b264a2d5197e1637fa\n--- /dev/null\n+++ b/bsp/bl808/m0/rtconfig.h\n@@ -0,0 +1,236 @@\n+#ifndef RT_CONFIG_H__\n+#define RT_CONFIG_H__\n+\n+/* Automatically generated file; DO NOT EDIT. */\n+/* RT-Thread Project Configuration */\n+\n+/* RT-Thread Kernel */\n+\n+#define RT_NAME_MAX 8\n+#define RT_ALIGN_SIZE 4\n+#define RT_THREAD_PRIORITY_32\n+#define RT_THREAD_PRIORITY_MAX 32\n+#define RT_TICK_PER_SECOND 1000\n+#define RT_USING_OVERFLOW_CHECK\n+#define RT_USING_HOOK\n+#define RT_HOOK_USING_FUNC_PTR\n+#define RT_USING_IDLE_HOOK\n+#define RT_IDLE_HOOK_LIST_SIZE 4\n+#define IDLE_THREAD_STACK_SIZE 1024\n+#define RT_USING_TIMER_SOFT\n+#define RT_TIMER_THREAD_PRIO 4\n+#define RT_TIMER_THREAD_STACK_SIZE 1024\n+\n+/* kservice optimization */\n+\n+#define RT_KSERVICE_USING_STDLIB\n+#define RT_DEBUG\n+\n+/* Inter-Thread communication */\n+\n+#define RT_USING_SEMAPHORE\n+#define RT_USING_MUTEX\n+#define RT_USING_EVENT\n+#define RT_USING_MAILBOX\n+#define RT_USING_MESSAGEQUEUE\n+\n+/* Memory Management */\n+\n+#define RT_USING_SMALL_MEM\n+#define RT_USING_SMALL_MEM_AS_HEAP\n+#define RT_USING_MEMTRACE\n+#define RT_USING_HEAP\n+\n+/* Kernel Device Object */\n+\n+#define RT_USING_DEVICE\n+#define RT_USING_CONSOLE\n+#define RT_CONSOLEBUF_SIZE 128\n+#define RT_CONSOLE_DEVICE_NAME \"uart0\"\n+#define RT_VER_NUM 0x50000\n+#define ARCH_RISCV_FPU\n+#define ARCH_RISCV_FPU_S\n+\n+/* RT-Thread Components */\n+\n+#define RT_USING_COMPONENTS_INIT\n+#define RT_USING_USER_MAIN\n+#define RT_MAIN_THREAD_STACK_SIZE 2048\n+#define RT_MAIN_THREAD_PRIORITY 10\n+#define RT_USING_MSH\n+#define RT_USING_FINSH\n+#define FINSH_USING_MSH\n+#define FINSH_THREAD_NAME \"tshell\"\n+#define FINSH_THREAD_PRIORITY 20\n+#define FINSH_THREAD_STACK_SIZE 4096\n+#define FINSH_USING_HISTORY\n+#define FINSH_HISTORY_LINES 5\n+#define FINSH_USING_SYMTAB\n+#define FINSH_CMD_SIZE 80\n+#define MSH_USING_BUILT_IN_COMMANDS\n+#define FINSH_USING_DESCRIPTION\n+#define FINSH_ARG_MAX 10\n+\n+/* Device Drivers */\n+\n+#define RT_USING_DEVICE_IPC\n+#define RT_UNAMED_PIPE_NUMBER 64\n+#define RT_USING_SERIAL\n+#define RT_USING_SERIAL_V1\n+#define RT_SERIAL_USING_DMA\n+#define RT_SERIAL_RB_BUFSZ 64\n+#define RT_USING_PIN\n+\n+/* Using USB */\n+\n+\n+/* C/C++ and POSIX layer */\n+\n+#define RT_LIBC_DEFAULT_TIMEZONE 8\n+\n+/* POSIX (Portable Operating System Interface) layer */\n+\n+\n+/* Interprocess Communication (IPC) */\n+\n+\n+/* Socket is in the 'Network' category */\n+\n+\n+/* Network */\n+\n+\n+/* Utilities */\n+\n+\n+/* RT-Thread Utestcases */\n+\n+\n+/* RT-Thread online packages */\n+\n+/* IoT - internet of things */\n+\n+\n+/* Wi-Fi */\n+\n+/* Marvell WiFi */\n+\n+\n+/* Wiced WiFi */\n+\n+\n+/* IoT Cloud */\n+\n+\n+/* security packages */\n+\n+\n+/* language packages */\n+\n+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */\n+\n+\n+/* XML: Extensible Markup Language */\n+\n+\n+/* multimedia packages */\n+\n+/* LVGL: powerful and easy-to-use embedded GUI library */\n+\n+\n+/* u8g2: a monochrome graphic library */\n+\n+\n+/* PainterEngine: A cross-platform graphics application framework written in C language */\n+\n+\n+/* tools packages */\n+\n+\n+/* system packages */\n+\n+/* enhanced kernel services */\n+\n+\n+/* acceleration: Assembly language or algorithmic acceleration packages */\n+\n+\n+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */\n+\n+\n+/* Micrium: Micrium software products porting for RT-Thread */\n+\n+\n+/* peripheral libraries and drivers */\n+\n+/* sensors drivers */\n+\n+\n+/* touch drivers */\n+\n+\n+/* Kendryte SDK */\n+\n+\n+/* AI packages */\n+\n+\n+/* Signal Processing and Control Algorithm Packages */\n+\n+\n+/* miscellaneous packages */\n+\n+/* project laboratory */\n+\n+/* samples: kernel and components samples */\n+\n+\n+/* entertainment: terminal games and other interesting software packages */\n+\n+\n+/* Arduino libraries */\n+\n+\n+/* Projects */\n+\n+\n+/* Sensors */\n+\n+\n+/* Display */\n+\n+\n+/* Timing */\n+\n+\n+/* Data Processing */\n+\n+\n+/* Data Storage */\n+\n+/* Communication */\n+\n+\n+/* Device Control */\n+\n+\n+/* Other */\n+\n+/* Signal IO */\n+\n+\n+/* Uncategorized */\n+\n+/* BL808_M0 Hardware Drivers Config */\n+\n+#define SOC_BL808\n+\n+/* On-chip Peripheral Drivers */\n+\n+#define BSP_USING_GPIO\n+#define BSP_USING_UART\n+#define BSP_USING_UART0\n+#define BSP_UART0_TXD_PIN 14\n+#define BSP_UART0_RXD_PIN 15\n+\n+#endif\n\n<|file_patch|>bsp/bl808/m0/rtconfig.py\ndiff --git a/bsp/bl808/m0/rtconfig.py b/bsp/bl808/m0/rtconfig.py\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a9c7ad4d54e450c201541b08053ddb401a972618\n--- /dev/null\n+++ b/bsp/bl808/m0/rtconfig.py\n@@ -0,0 +1,65 @@\n+import os\n+\n+# toolchains options\n+ARCH ='risc-v'\n+VENDOR ='t-head'\n+CPU ='e9xx'\n+CROSS_TOOL ='gcc'\n+\n+if os.getenv('RTT_ROOT'):\n+ RTT_ROOT = os.getenv('RTT_ROOT')\n+else:\n+ RTT_ROOT = r'../../..'\n+\n+if os.getenv('RTT_CC'):\n+ CROSS_TOOL = os.getenv('RTT_CC')\n+\n+if CROSS_TOOL == 'gcc':\n+ PLATFORM = 'gcc'\n+ EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin'\n+else:\n+ print('Please make sure your toolchains is GNU GCC!')\n+ exit(0)\n+\n+if os.getenv('RTT_EXEC_PATH'):\n+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')\n+\n+BUILD = 'debug'\n+\n+if PLATFORM == 'gcc':\n+ # toolchains\n+ PREFIX = 'riscv64-unknown-elf-'\n+ CC = PREFIX + 'gcc'\n+ CXX = PREFIX + 'g++'\n+ AS = PREFIX + 'gcc'\n+ AR = PREFIX + 'ar'\n+ LINK = PREFIX + 'gcc'\n+ TARGET_EXT = 'elf'\n+ SIZE = PREFIX + 'size'\n+ OBJDUMP = PREFIX + 'objdump'\n+ OBJCPY = PREFIX + 'objcopy'\n+\n+ DEVICE = ' -march=rv32imafcxthead -mabi=ilp32f -mtune=e907 -mcmodel=medany'\n+ CFLAGS = DEVICE + ' -Wall -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wextra -Wno-unused-parameter -Wno-sign-compare'\n+ CFLAGS += ' -Wno-old-style-declaration -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fcommon -ffreestanding -fno-strict-aliasing -fno-jump-tables -save-temps=obj'\n+\n+ LINKER_SCRIPTS_PATH = r'libraries/platform/soc/bl808/startup_bl808/evb/ld/'\n+ LINKER_SCRIPTS = 'bl808_flash.ld'\n+\n+ CFLAGS += ' -DCFG_COMPONENT_BLOG_ENABLE=0 -DARCH_RISCV -DBFLB_USE_HAL_DRIVER -DCPU_M0 -DBL808'\n+\n+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'\n+ LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS_PATH + LINKER_SCRIPTS\n+ CPATH = ''\n+ LPATH = ''\n+\n+ if BUILD == 'debug':\n+ CFLAGS += ' -O0 -gdwarf'\n+ AFLAGS += ' -gdwarf'\n+ else:\n+ CFLAGS += ' -O3'\n+\n+ CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'\n+\n+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\\n'\n+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_m0.bin\\n' + SIZE + ' $TARGET \\n'\n\n<|file_patch|>bsp/bl808/partition/partition_cfg_16M_m1sdock.toml\ndiff --git a/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml b/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..7b75961470bf2550ac4b767801cb268dc7258724\n--- /dev/null\n+++ b/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml\n@@ -0,0 +1,85 @@\n+[pt_table]\n+#partition table is 4K in size\n+address0 = 0xE000\n+address1 = 0xF000\n+# If version is 2, It will use dynamic mode.\n+version = 2\n+\n+[[pt_entry]]\n+type = 16\n+name = \"Boot2\"\n+device = 0\n+address0 = 0\n+size0 = 0xE000\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n+\n+[[pt_entry]]\n+type = 0\n+name = \"FW\"\n+device = 0\n+address0 = 0x10000\n+size0 = 0xF0000\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n+\n+[[pt_entry]]\n+type = 2\n+name = \"D0FW\"\n+device = 0\n+address0 = 0x100000\n+size0 = 0x200000\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n+\n+[[pt_entry]]\n+type = 5\n+name = \"media\"\n+device = 0\n+address0 = 0x300000\n+size0 = 0xC00000\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n+\n+[[pt_entry]]\n+type = 11\n+name = \"unused\"\n+device = 0\n+address0 = 0xF00000\n+size0 = 0x100000\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n+\n+[[pt_entry]]\n+type = 8\n+# It shows Dts in DevCube \n+name = \"factory\"\n+device = 0\n+address0 = 0x910000\n+size0 = 0\n+address1 = 0\n+size1 = 0\n+# compressed image must set len,normal image can left it to 0\n+len = 0\n+# If header is 1, it will add the header.\n+header = 1\n\n<|file_patch|>libcpu/risc-v/SConscript\ndiff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript\nindex 206806a3e1aea07d901f8bd2da6812801d430c54..4d74c9aff24afaa538e5a7f85aedd5587aae85c5 100644\n--- a/libcpu/risc-v/SConscript\n+++ b/libcpu/risc-v/SConscript\n@@ -10,9 +10,7 @@ group = []\n list = os.listdir(cwd)\n \n # add common code files\n-if rtconfig.CPU == \"e9xx\" :\n- group = group\n-elif rtconfig.CPU == \"nuclei\" :\n+if rtconfig.CPU == \"nuclei\" :\n group = group\n elif rtconfig.CPU == \"virt64\" :\n group = group\n\n<|file_patch|>libcpu/risc-v/t-head/e9xx/context_gcc.S\ndiff --git a/libcpu/risc-v/t-head/e9xx/context_gcc.S b/libcpu/risc-v/t-head/e9xx/context_gcc.S\ndeleted file mode 100644\nindex 99c63c31de9b1c93723265aa9c0d15b2d96462aa..0000000000000000000000000000000000000000\n--- a/libcpu/risc-v/t-head/e9xx/context_gcc.S\n+++ /dev/null\n@@ -1,350 +0,0 @@\n-/*\n- * Copyright (c) 2006-2018, RT-Thread Development Team\n- * Copyright (c) 2021, Alibaba Group Holding Limited\n- *\n- * SPDX-License-Identifier: Apache-2.0\n- *\n- * Change Logs:\n- * Date Author Notes\n- * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation\n- * 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.\n- */\n-\n-#include \"cpuport.h\"\n-\n-#ifdef RT_USING_SMP\n-#define rt_hw_interrupt_disable rt_hw_local_irq_disable\n-#define rt_hw_interrupt_enable rt_hw_local_irq_enable\n-#endif\n-\n-/*\n- * Functions: vPortYield\n- */\n-.global vPortYield\n-.type vPortYield, %function\n-vPortYield:\n- li t0, 0xE080100C\n- lb t1, (t0)\n- li t2, 0x01\n- or t1, t1, t2\n- sb t1, (t0)\n-\n- ret\n-\n-/*\n- * #ifdef RT_USING_SMP\n- * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);\n- * #else\n- * void rt_hw_context_switch_to(rt_ubase_t to);\n- * #endif\n- * a0 --> to\n- * a1 --> to_thread\n- */\n- .globl rt_hw_context_switch_to\n-rt_hw_context_switch_to:\n- /* save a0 to to_thread */\n- la t0, rt_interrupt_to_thread\n- STORE a0, (t0)\n-\n- /* save 0 to from_thread */\n- la t0, rt_interrupt_from_thread\n- li t1, 0\n- STORE t1, (t0)\n-\n- /* set rt_thread_switch_interrupt_flag=1 */\n- la t0, rt_thread_switch_interrupt_flag\n- li t1, 1\n- STORE t1, (t0)\n-\n- /* enable mexstatus SPUSHEN */\n-#ifdef CONFIG_THEAD_EXT_SPUSHEN\n- li t0, 0x10000\n- csrs mexstatus, t0\n-#endif\n-\n- csrw mscratch, sp\n- /* set software interrupt */\n- li t0, 0xE080100C\n- lb t1, (t0)\n- li t2, 0x01\n- or t1, t1, t2\n- sb t1, (t0)\n-\n- /* enable global interrup */\n- csrsi mstatus, 8\n-\n- ret\n-\n-/*\n- * #ifdef RT_USING_SMP\n- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);\n- * #else\n- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);\n- * #endif\n- *\n- * a0 --> from\n- * a1 --> to\n- * a2 --> to_thread\n- */\n- .globl rt_hw_context_switch\n-rt_hw_context_switch:\n- .globl rt_hw_context_switch_interrupt\n-rt_hw_context_switch_interrupt:\n- /* check rt_thread_switch_interrupt_flag */\n- la t0, rt_thread_switch_interrupt_flag\n- lw t1, (t0)\n- li t2, 1\n- beq t1, t2, .reswitch\n- /* set rt_thread_switch_interrupt_flag=1 */\n- STORE t2, (t0)\n-\n- /* update from_thread */\n- la t0, rt_interrupt_from_thread\n- STORE a0, (t0)\n-\n-.reswitch:\n- /* update to_thread */\n- la t0, rt_interrupt_to_thread\n- STORE a1, (t0)\n- /* set software interrupt */\n- li t0, 0xE080100C\n- lb t1, (t0)\n- li t2, 0x01\n- or t1, t1, t2\n- sb t1, (t0)\n-\n- ret\n-\n-/*\n- * PendSV_Handler\n- */\n-.global PendSV_Handler\n-.type PendSV_Handler, %function\n-PendSV_Handler:\n-\n- /* check rt_thread_switch_interrupt_flag */\n- sw t0, (-4)(sp)\n- sw t1, (-8)(sp)\n- la t0, rt_thread_switch_interrupt_flag\n- lw t1, (t0)\n- beqz t1, .pendsv_exit\n-\n- /* clear rt_thread_switch_interrupt_flag */\n- li t1, 0x0\n- sw t1, (t0)\n-\n- /* check rt_interrupt_from_thread */\n- la t0, rt_interrupt_from_thread\n- lw t1, (t0)\n- beqz t1, .switch_to_thead\n-\n- /* restore from thread context t0,t1 */\n- lw t0, (-4)(sp)\n- lw t1, (-8)(sp)\n-\n-#ifdef ARCH_RISCV_FPU\n- addi sp, sp, -32 * FREGBYTES\n-\n- FSTORE f0, 0 * FREGBYTES(sp)\n- FSTORE f1, 1 * FREGBYTES(sp)\n- FSTORE f2, 2 * FREGBYTES(sp)\n- FSTORE f3, 3 * FREGBYTES(sp)\n- FSTORE f4, 4 * FREGBYTES(sp)\n- FSTORE f5, 5 * FREGBYTES(sp)\n- FSTORE f6, 6 * FREGBYTES(sp)\n- FSTORE f7, 7 * FREGBYTES(sp)\n- FSTORE f8, 8 * FREGBYTES(sp)\n- FSTORE f9, 9 * FREGBYTES(sp)\n- FSTORE f10, 10 * FREGBYTES(sp)\n- FSTORE f11, 11 * FREGBYTES(sp)\n- FSTORE f12, 12 * FREGBYTES(sp)\n- FSTORE f13, 13 * FREGBYTES(sp)\n- FSTORE f14, 14 * FREGBYTES(sp)\n- FSTORE f15, 15 * FREGBYTES(sp)\n- FSTORE f16, 16 * FREGBYTES(sp)\n- FSTORE f17, 17 * FREGBYTES(sp)\n- FSTORE f18, 18 * FREGBYTES(sp)\n- FSTORE f19, 19 * FREGBYTES(sp)\n- FSTORE f20, 20 * FREGBYTES(sp)\n- FSTORE f21, 21 * FREGBYTES(sp)\n- FSTORE f22, 22 * FREGBYTES(sp)\n- FSTORE f23, 23 * FREGBYTES(sp)\n- FSTORE f24, 24 * FREGBYTES(sp)\n- FSTORE f25, 25 * FREGBYTES(sp)\n- FSTORE f26, 26 * FREGBYTES(sp)\n- FSTORE f27, 27 * FREGBYTES(sp)\n- FSTORE f28, 28 * FREGBYTES(sp)\n- FSTORE f29, 29 * FREGBYTES(sp)\n- FSTORE f30, 30 * FREGBYTES(sp)\n- FSTORE f31, 31 * FREGBYTES(sp)\n-#endif\n-\n-#ifdef ARCH_RISCV_DSP\n- addi sp, sp, -33 * REGBYTES\n-#else\n- addi sp, sp, -32 * REGBYTES\n-#endif\n-\n- STORE x1, 1 * REGBYTES(sp)\n- csrr x1, mepc\n- STORE x1, 0 * REGBYTES(sp)\n- csrr x1, mstatus\n- STORE x1, 2 * REGBYTES(sp)\n- /* x3 don't need save */\n- STORE x4, 4 * REGBYTES(sp)\n- STORE x5, 5 * REGBYTES(sp)\n- STORE x6, 6 * REGBYTES(sp)\n- STORE x7, 7 * REGBYTES(sp)\n- STORE x8, 8 * REGBYTES(sp)\n- STORE x9, 9 * REGBYTES(sp)\n- STORE x10, 10 * REGBYTES(sp)\n- STORE x11, 11 * REGBYTES(sp)\n- STORE x12, 12 * REGBYTES(sp)\n- STORE x13, 13 * REGBYTES(sp)\n- STORE x14, 14 * REGBYTES(sp)\n- STORE x15, 15 * REGBYTES(sp)\n- STORE x16, 16 * REGBYTES(sp)\n- STORE x17, 17 * REGBYTES(sp)\n- STORE x18, 18 * REGBYTES(sp)\n- STORE x19, 19 * REGBYTES(sp)\n- STORE x20, 20 * REGBYTES(sp)\n- STORE x21, 21 * REGBYTES(sp)\n- STORE x22, 22 * REGBYTES(sp)\n- STORE x23, 23 * REGBYTES(sp)\n- STORE x24, 24 * REGBYTES(sp)\n- STORE x25, 25 * REGBYTES(sp)\n- STORE x26, 26 * REGBYTES(sp)\n- STORE x27, 27 * REGBYTES(sp)\n- STORE x28, 28 * REGBYTES(sp)\n- STORE x29, 29 * REGBYTES(sp)\n- STORE x30, 30 * REGBYTES(sp)\n- STORE x31, 31 * REGBYTES(sp)\n-#ifdef ARCH_RISCV_DSP\n- csrr t0, vxsat\n- STORE t0, 32 * REGBYTES(sp)\n-#endif\n-\n- /* store from_thread sp */\n- la t0, rt_interrupt_from_thread\n- lw t0, (t0)\n- sw sp, (t0)\n-\n-.switch_to_thead:\n- /* restore to thread context\n- * sp(0) -> epc;\n- * sp(1) -> ra;\n- * sp(i) -> x(i+2)\n- */\n- la t0, rt_interrupt_to_thread\n- lw t0, (t0)\n- LOAD sp, (t0)\n-\n-\n-#ifdef ARCH_RISCV_DSP\n- LOAD a1, 32 * REGBYTES(sp)\n- csrw vxsat, a1\n-#endif\n-\n- /* restore ra to mepc */\n- LOAD a1, 0 * REGBYTES(sp)\n- csrw mepc, a1\n- LOAD x1, 1 * REGBYTES(sp)\n-\n- /* force to machine mode(MPP=11) */\n- LOAD a1, 2 * REGBYTES(sp)\n- csrw mstatus, a1\n- /* x3 don't need restore */\n- LOAD x4, 4 * REGBYTES(sp)\n- LOAD x5, 5 * REGBYTES(sp)\n- LOAD x6, 6 * REGBYTES(sp)\n- LOAD x7, 7 * REGBYTES(sp)\n- LOAD x8, 8 * REGBYTES(sp)\n- LOAD x9, 9 * REGBYTES(sp)\n- LOAD x10, 10 * REGBYTES(sp)\n- LOAD x11, 11 * REGBYTES(sp)\n- LOAD x12, 12 * REGBYTES(sp)\n- LOAD x13, 13 * REGBYTES(sp)\n- LOAD x14, 14 * REGBYTES(sp)\n- LOAD x15, 15 * REGBYTES(sp)\n- LOAD x16, 16 * REGBYTES(sp)\n- LOAD x17, 17 * REGBYTES(sp)\n- LOAD x18, 18 * REGBYTES(sp)\n- LOAD x19, 19 * REGBYTES(sp)\n- LOAD x20, 20 * REGBYTES(sp)\n- LOAD x21, 21 * REGBYTES(sp)\n- LOAD x22, 22 * REGBYTES(sp)\n- LOAD x23, 23 * REGBYTES(sp)\n- LOAD x24, 24 * REGBYTES(sp)\n- LOAD x25, 25 * REGBYTES(sp)\n- LOAD x26, 26 * REGBYTES(sp)\n- LOAD x27, 27 * REGBYTES(sp)\n- LOAD x28, 28 * REGBYTES(sp)\n- LOAD x29, 29 * REGBYTES(sp)\n- LOAD x30, 30 * REGBYTES(sp)\n- LOAD x31, 31 * REGBYTES(sp)\n-\n-#ifdef ARCH_RISCV_DSP\n- addi sp, sp, 33 * REGBYTES\n-#else\n- addi sp, sp, 32 * REGBYTES\n-#endif\n-\n-#ifdef ARCH_RISCV_FPU\n- FLOAD f0, 0 * FREGBYTES(sp)\n- FLOAD f1, 1 * FREGBYTES(sp)\n- FLOAD f2, 2 * FREGBYTES(sp)\n- FLOAD f3, 3 * FREGBYTES(sp)\n- FLOAD f4, 4 * FREGBYTES(sp)\n- FLOAD f5, 5 * FREGBYTES(sp)\n- FLOAD f6, 6 * FREGBYTES(sp)\n- FLOAD f7, 7 * FREGBYTES(sp)\n- FLOAD f8, 8 * FREGBYTES(sp)\n- FLOAD f9, 9 * FREGBYTES(sp)\n- FLOAD f10, 10 * FREGBYTES(sp)\n- FLOAD f11, 11 * FREGBYTES(sp)\n- FLOAD f12, 12 * FREGBYTES(sp)\n- FLOAD f13, 13 * FREGBYTES(sp)\n- FLOAD f14, 14 * FREGBYTES(sp)\n- FLOAD f15, 15 * FREGBYTES(sp)\n- FLOAD f16, 16 * FREGBYTES(sp)\n- FLOAD f17, 17 * FREGBYTES(sp)\n- FLOAD f18, 18 * FREGBYTES(sp)\n- FLOAD f19, 19 * FREGBYTES(sp)\n- FLOAD f20, 20 * FREGBYTES(sp)\n- FLOAD f21, 21 * FREGBYTES(sp)\n- FLOAD f22, 22 * FREGBYTES(sp)\n- FLOAD f23, 23 * FREGBYTES(sp)\n- FLOAD f24, 24 * FREGBYTES(sp)\n- FLOAD f25, 25 * FREGBYTES(sp)\n- FLOAD f26, 26 * FREGBYTES(sp)\n- FLOAD f27, 27 * FREGBYTES(sp)\n- FLOAD f28, 28 * FREGBYTES(sp)\n- FLOAD f29, 29 * FREGBYTES(sp)\n- FLOAD f30, 30 * FREGBYTES(sp)\n- FLOAD f31, 31 * FREGBYTES(sp)\n-\n- addi sp, sp, 32 * FREGBYTES\n-#endif\n-\n-.pendsv_exit:\n- mret\n-\n-/*\n- * rt_base_t rt_hw_interrupt_disable(void);\n- */\n- .globl rt_hw_interrupt_disable\n- .type rt_hw_interrupt_disable, %function\n-rt_hw_interrupt_disable:\n- csrrci a0, mstatus, 8\n- ret\n-\n-\n-/*\n- * void rt_hw_interrupt_enable(rt_base_t level);\n- */\n- .globl rt_hw_interrupt_enable\n- .type rt_hw_interrupt_enable, %function\n-rt_hw_interrupt_enable:\n- csrw mstatus, a0\n- ret\n-\n\n<|file_patch|>libcpu/risc-v/t-head/e9xx/cpuport.c\ndiff --git a/libcpu/risc-v/t-head/e9xx/cpuport.c b/libcpu/risc-v/t-head/e9xx/cpuport.c\ndeleted file mode 100644\nindex 18bb265130ab0cafaca93442e775f5a76e41e361..0000000000000000000000000000000000000000\n--- a/libcpu/risc-v/t-head/e9xx/cpuport.c\n+++ /dev/null\n@@ -1,148 +0,0 @@\n-/*\n- * Copyright (c) 2006-2021, RT-Thread Development Team\n- * Copyright (c) 2021, Alibaba Group Holding Limited\n- *\n- * SPDX-License-Identifier: Apache-2.0\n- *\n- * Change Logs:\n- * Date Author Notes\n- * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code.\n- * 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.\n- */\n-\n-#include <rthw.h>\n-#include <rtthread.h>\n-\n-#include \"cpuport.h\"\n-\n-#ifndef RT_USING_SMP\n-volatile rt_ubase_t rt_interrupt_from_thread = 0;\n-volatile rt_ubase_t rt_interrupt_to_thread = 0;\n-volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;\n-#endif\n-\n-struct rt_hw_stack_frame\n-{\n- rt_ubase_t epc; /* epc - epc - program counter */\n- rt_ubase_t ra; /* x1 - ra - return address for jumps */\n- rt_ubase_t mstatus; /* - machine status register */\n- rt_ubase_t gp; /* x3 - gp - global pointer */\n- rt_ubase_t tp; /* x4 - tp - thread pointer */\n- rt_ubase_t t0; /* x5 - t0 - temporary register 0 */\n- rt_ubase_t t1; /* x6 - t1 - temporary register 1 */\n- rt_ubase_t t2; /* x7 - t2 - temporary register 2 */\n- rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */\n- rt_ubase_t s1; /* x9 - s1 - saved register 1 */\n- rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */\n- rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */\n- rt_ubase_t a2; /* x12 - a2 - function argument 2 */\n- rt_ubase_t a3; /* x13 - a3 - function argument 3 */\n- rt_ubase_t a4; /* x14 - a4 - function argument 4 */\n- rt_ubase_t a5; /* x15 - a5 - function argument 5 */\n- rt_ubase_t a6; /* x16 - a6 - function argument 6 */\n- rt_ubase_t a7; /* x17 - s7 - function argument 7 */\n- rt_ubase_t s2; /* x18 - s2 - saved register 2 */\n- rt_ubase_t s3; /* x19 - s3 - saved register 3 */\n- rt_ubase_t s4; /* x20 - s4 - saved register 4 */\n- rt_ubase_t s5; /* x21 - s5 - saved register 5 */\n- rt_ubase_t s6; /* x22 - s6 - saved register 6 */\n- rt_ubase_t s7; /* x23 - s7 - saved register 7 */\n- rt_ubase_t s8; /* x24 - s8 - saved register 8 */\n- rt_ubase_t s9; /* x25 - s9 - saved register 9 */\n- rt_ubase_t s10; /* x26 - s10 - saved register 10 */\n- rt_ubase_t s11; /* x27 - s11 - saved register 11 */\n- rt_ubase_t t3; /* x28 - t3 - temporary register 3 */\n- rt_ubase_t t4; /* x29 - t4 - temporary register 4 */\n- rt_ubase_t t5; /* x30 - t5 - temporary register 5 */\n- rt_ubase_t t6; /* x31 - t6 - temporary register 6 */\n-#ifdef ARCH_RISCV_DSP\n- rt_ubase_t vxsat; /* P-ext vxsat reg */\n-#endif\n-#ifdef ARCH_RISCV_FPU\n- rv_floatreg_t f0; /* f0 */\n- rv_floatreg_t f1; /* f1 */\n- rv_floatreg_t f2; /* f2 */\n- rv_floatreg_t f3; /* f3 */\n- rv_floatreg_t f4; /* f4 */\n- rv_floatreg_t f5; /* f5 */\n- rv_floatreg_t f6; /* f6 */\n- rv_floatreg_t f7; /* f7 */\n- rv_floatreg_t f8; /* f8 */\n- rv_floatreg_t f9; /* f9 */\n- rv_floatreg_t f10; /* f10 */\n- rv_floatreg_t f11; /* f11 */\n- rv_floatreg_t f12; /* f12 */\n- rv_floatreg_t f13; /* f13 */\n- rv_floatreg_t f14; /* f14 */\n- rv_floatreg_t f15; /* f15 */\n- rv_floatreg_t f16; /* f16 */\n- rv_floatreg_t f17; /* f17 */\n- rv_floatreg_t f18; /* f18 */\n- rv_floatreg_t f19; /* f19 */\n- rv_floatreg_t f20; /* f20 */\n- rv_floatreg_t f21; /* f21 */\n- rv_floatreg_t f22; /* f22 */\n- rv_floatreg_t f23; /* f23 */\n- rv_floatreg_t f24; /* f24 */\n- rv_floatreg_t f25; /* f25 */\n- rv_floatreg_t f26; /* f26 */\n- rv_floatreg_t f27; /* f27 */\n- rv_floatreg_t f28; /* f28 */\n- rv_floatreg_t f29; /* f29 */\n- rv_floatreg_t f30; /* f30 */\n- rv_floatreg_t f31; /* f31 */\n-#endif\n-};\n-\n-/**\n- * This function will initialize thread stack\n- *\n- * @param tentry the entry of thread\n- * @param parameter the parameter of entry\n- * @param stack_addr the beginning stack address\n- * @param texit the function will be called when thread exit\n- *\n- * @return stack address\n- */\n-rt_uint8_t *rt_hw_stack_init(void *tentry,\n- void *parameter,\n- rt_uint8_t *stack_addr,\n- void *texit)\n-{\n- struct rt_hw_stack_frame *frame;\n- rt_uint8_t *stk;\n- int i;\n-\n- stk = stack_addr + sizeof(rt_ubase_t);\n- stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);\n- stk -= sizeof(struct rt_hw_stack_frame);\n-\n- frame = (struct rt_hw_stack_frame *)stk;\n-\n- for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)\n- {\n- ((rt_ubase_t *)frame)[i] = 0xdeadbeef;\n- }\n-\n- frame->ra = (rt_ubase_t)texit;\n- frame->a0 = (rt_ubase_t)parameter;\n- frame->epc = (rt_ubase_t)tentry;\n-\n- /* force to machine mode(MPP=11) and set MPIE to 1 */\n- frame->mstatus = 0x00007880;\n-\n- return stk;\n-}\n-\n-/** shutdown CPU */\n-rt_weak void rt_hw_cpu_shutdown()\n-{\n- rt_base_t level;\n- rt_kprintf(\"shutdown...\\n\");\n-\n- level = rt_hw_interrupt_disable();\n- while (level)\n- {\n- RT_ASSERT(0);\n- }\n-}\n\n<|file_patch|>libcpu/risc-v/t-head/e9xx/cpuport.h\ndiff --git a/libcpu/risc-v/t-head/e9xx/cpuport.h b/libcpu/risc-v/t-head/e9xx/cpuport.h\ndeleted file mode 100644\nindex 4f01d2127c37487946b82bbda812d1f5cda8d3c9..0000000000000000000000000000000000000000\n--- a/libcpu/risc-v/t-head/e9xx/cpuport.h\n+++ /dev/null\n@@ -1,56 +0,0 @@\n-/*\n- * Copyright (c) 2006-2021, RT-Thread Development Team\n- *\n- * SPDX-License-Identifier: Apache-2.0\n- *\n- * Change Logs:\n- * Date Author Notes\n- * 2020-08-20 zx.chen The first version\n- */\n-\n-#ifndef CPUPORT_H__\n-#define CPUPORT_H__\n-\n-#include <rtconfig.h>\n-#include <theadconfig.h>\n-\n-/* bytes of register width */\n-#ifdef ARCH_RISCV_64\n-#define DFSTORE fsd\n-#define DFLOAD fld\n-#define SFSTORE fsw\n-#define SFLOAD flw\n-#define STORE sd\n-#define LOAD ld\n-#define REGBYTES 8\n-#define SFREGBYTES 4\n-#define DFREGBYTES 8\n-#else\n-#define DFSTORE fsd\n-#define DFLOAD fld\n-#define SFSTORE fsw\n-#define SFLOAD flw\n-#define STORE sw\n-#define LOAD lw\n-\n-#define REGBYTES 4\n-#define SFREGBYTES 4\n-#define DFREGBYTES 8\n-#endif\n-\n-#ifdef ARCH_RISCV_FPU\n-#ifdef ARCH_RISCV_FPU_D\n-#define FSTORE fsd\n-#define FLOAD fld\n-#define FREGBYTES 8\n-#define rv_floatreg_t rt_int64_t\n-#endif\n-#ifdef ARCH_RISCV_FPU_S\n-#define FSTORE fsw\n-#define FLOAD flw\n-#define FREGBYTES 4\n-#define rv_floatreg_t rt_int32_t\n-#endif\n-#endif\n-\n-#endif\n\n<|file_patch|>libcpu/risc-v/t-head/e9xx/interrupt_gcc.S\ndiff --git a/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S b/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d727e4df87e60cc3d1082b806e7d41a33748d4d3\n--- /dev/null\n+++ b/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S\n@@ -0,0 +1,224 @@\n+/*\n+ * Copyright (c) 2006-2018, RT-Thread Development Team\n+ *\n+ * SPDX-License-Identifier: Apache-2.0\n+ *\n+ * Change Logs:\n+ * Date Author Notes\n+ * 2022/12/25 flyingcys first version\n+ */\n+#include \"cpuport.h\"\n+\n+.align 2\n+.global IRQ_Handler\n+IRQ_Handler:\n+#ifdef ARCH_RISCV_FPU\n+ addi sp, sp, -32 * FREGBYTES\n+\n+ FSTORE f0, 0 * FREGBYTES(sp)\n+ FSTORE f1, 1 * FREGBYTES(sp)\n+ FSTORE f2, 2 * FREGBYTES(sp)\n+ FSTORE f3, 3 * FREGBYTES(sp)\n+ FSTORE f4, 4 * FREGBYTES(sp)\n+ FSTORE f5, 5 * FREGBYTES(sp)\n+ FSTORE f6, 6 * FREGBYTES(sp)\n+ FSTORE f7, 7 * FREGBYTES(sp)\n+ FSTORE f8, 8 * FREGBYTES(sp)\n+ FSTORE f9, 9 * FREGBYTES(sp)\n+ FSTORE f10, 10 * FREGBYTES(sp)\n+ FSTORE f11, 11 * FREGBYTES(sp)\n+ FSTORE f12, 12 * FREGBYTES(sp)\n+ FSTORE f13, 13 * FREGBYTES(sp)\n+ FSTORE f14, 14 * FREGBYTES(sp)\n+ FSTORE f15, 15 * FREGBYTES(sp)\n+ FSTORE f16, 16 * FREGBYTES(sp)\n+ FSTORE f17, 17 * FREGBYTES(sp)\n+ FSTORE f18, 18 * FREGBYTES(sp)\n+ FSTORE f19, 19 * FREGBYTES(sp)\n+ FSTORE f20, 20 * FREGBYTES(sp)\n+ FSTORE f21, 21 * FREGBYTES(sp)\n+ FSTORE f22, 22 * FREGBYTES(sp)\n+ FSTORE f23, 23 * FREGBYTES(sp)\n+ FSTORE f24, 24 * FREGBYTES(sp)\n+ FSTORE f25, 25 * FREGBYTES(sp)\n+ FSTORE f26, 26 * FREGBYTES(sp)\n+ FSTORE f27, 27 * FREGBYTES(sp)\n+ FSTORE f28, 28 * FREGBYTES(sp)\n+ FSTORE f29, 29 * FREGBYTES(sp)\n+ FSTORE f30, 30 * FREGBYTES(sp)\n+ FSTORE f31, 31 * FREGBYTES(sp)\n+#endif\n+\n+\taddi sp, sp, - (32 * REGBYTES)\n+\tSTORE x1, 1 * REGBYTES( sp )\t\t\t//x1:ra\n+\n+\tSTORE x4, 4 * REGBYTES( sp )\n+\tSTORE x5, 5 * REGBYTES( sp )\n+\tSTORE x6, 6 * REGBYTES( sp )\n+\tSTORE x7, 7 * REGBYTES( sp )\n+\tSTORE x8, 8 * REGBYTES( sp )\n+\tSTORE x9, 9 * REGBYTES( sp )\n+\tSTORE x10, 10 * REGBYTES( sp )\n+\tSTORE x11, 11 * REGBYTES( sp )\n+\tSTORE x12, 12 * REGBYTES( sp )\n+\tSTORE x13, 13 * REGBYTES( sp )\n+\tSTORE x14, 14 * REGBYTES( sp )\n+\tSTORE x15, 15 * REGBYTES( sp )\n+\tSTORE x16, 16 * REGBYTES( sp )\n+\tSTORE x17, 17 * REGBYTES( sp )\n+\tSTORE x18, 18 * REGBYTES( sp )\n+\tSTORE x19, 19 * REGBYTES( sp )\n+\tSTORE x20, 20 * REGBYTES( sp )\n+\tSTORE x21, 21 * REGBYTES( sp )\n+\tSTORE x22, 22 * REGBYTES( sp )\n+\tSTORE x23, 23 * REGBYTES( sp )\n+\tSTORE x24, 24 * REGBYTES( sp )\n+\tSTORE x25, 25 * REGBYTES( sp )\n+\tSTORE x26, 26 * REGBYTES( sp )\n+\tSTORE x27, 27 * REGBYTES( sp )\n+\tSTORE x28, 28 * REGBYTES( sp )\n+\tSTORE x29, 29 * REGBYTES( sp )\n+\tSTORE x30, 30 * REGBYTES( sp )\n+\tSTORE x31, 31 * REGBYTES( sp )\n+\n+ csrr a0, mepc\n+\tSTORE a0, 0 * REGBYTES( sp )\t\t\t//epc\n+\n+ csrr a0, mstatus\n+\tSTORE a0, 2 * REGBYTES( sp )\t\t\t//mstatus\n+\n+ /* Save the thread stack frame base to mscratch */\n+ csrw mscratch, sp\n+\n+ /* switch to interrupt stack */\n+ la sp, __StackTop\n+\n+ /* interrupt handle */\n+\tla a0, rt_interrupt_enter\n+\tjalr a0\n+\n+\tcsrr a0, mcause\n+\tli t0, 0x807FFFFF\n+\tand a0, a0, t0\n+\n+\tsrli a2, a0, __riscv_xlen - 1\t\t/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\n+\tbeq a2, x0, handle_synchronous\t\t/* Branch past interrupt handing if not asynchronous. */\n+\n+\tcsrr t1, mcause\n+\tandi t1, t1, 0x3FF\n+\tslli t1, t1, 2\n+\tla t0, g_irqvector\n+\tadd t0, t0, t1\n+\tlw t2, 0(t0)\n+\tjalr t2\n+\t\n+\tj processed_source\n+\n+handle_synchronous:\n+//\tla t0, exception_entry\n+//\tjalr t0\n+\n+processed_source:\n+\n+\tla a0, rt_interrupt_leave\n+\tjalr a0\n+\n+ /* switch to thread stack */\n+ csrr sp, mscratch\n+\n+ /* need to switch new thread */\n+ la a0, rt_thread_switch_interrupt_flag\n+ lw a1, 0(a0)\n+ beqz a1, interrupt_exit\n+\t\n+\tsw zero, 0(a0)\n+\n+\tla a0, rt_interrupt_from_thread\n+\tLOAD a1, 0(a0)\n+\tSTORE sp, 0(a1)\n+\n+\tla a0, rt_interrupt_to_thread\n+\tLOAD a1, 0(a0)\n+\tLOAD sp, 0(a1)\n+\n+interrupt_exit:\n+ /* resw ra to mepc */\n+ LOAD a0, 0 * REGBYTES(sp)\n+ csrw mepc, a0\n+\n+ LOAD x1, 1 * REGBYTES(sp)\n+\n+ li t0, 0x00007800\n+ csrw mstatus, t0\n+\n+ LOAD a0, 2 * REGBYTES(sp)\n+ csrs mstatus, a0\n+\n+ LOAD x4, 4 * REGBYTES(sp)\n+ LOAD x5, 5 * REGBYTES(sp)\n+ LOAD x6, 6 * REGBYTES(sp)\n+ LOAD x7, 7 * REGBYTES(sp)\n+ LOAD x8, 8 * REGBYTES(sp)\n+ LOAD x9, 9 * REGBYTES(sp)\n+ LOAD x10, 10 * REGBYTES(sp)\n+ LOAD x11, 11 * REGBYTES(sp)\n+ LOAD x12, 12 * REGBYTES(sp)\n+ LOAD x13, 13 * REGBYTES(sp)\n+ LOAD x14, 14 * REGBYTES(sp)\n+ LOAD x15, 15 * REGBYTES(sp)\n+ LOAD x16, 16 * REGBYTES(sp)\n+ LOAD x17, 17 * REGBYTES(sp)\n+ LOAD x18, 18 * REGBYTES(sp)\n+ LOAD x19, 19 * REGBYTES(sp)\n+ LOAD x20, 20 * REGBYTES(sp)\n+ LOAD x21, 21 * REGBYTES(sp)\n+ LOAD x22, 22 * REGBYTES(sp)\n+ LOAD x23, 23 * REGBYTES(sp)\n+ LOAD x24, 24 * REGBYTES(sp)\n+ LOAD x25, 25 * REGBYTES(sp)\n+ LOAD x26, 26 * REGBYTES(sp)\n+ LOAD x27, 27 * REGBYTES(sp)\n+ LOAD x28, 28 * REGBYTES(sp)\n+ LOAD x29, 29 * REGBYTES(sp)\n+ LOAD x30, 30 * REGBYTES(sp)\n+ LOAD x31, 31 * REGBYTES(sp)\n+\n+ addi sp, sp, 32 * REGBYTES\n+#ifdef ARCH_RISCV_FPU\n+ FLOAD f0, 0 * FREGBYTES(sp)\n+ FLOAD f1, 1 * FREGBYTES(sp)\n+ FLOAD f2, 2 * FREGBYTES(sp)\n+ FLOAD f3, 3 * FREGBYTES(sp)\n+ FLOAD f4, 4 * FREGBYTES(sp)\n+ FLOAD f5, 5 * FREGBYTES(sp)\n+ FLOAD f6, 6 * FREGBYTES(sp)\n+ FLOAD f7, 7 * FREGBYTES(sp)\n+ FLOAD f8, 8 * FREGBYTES(sp)\n+ FLOAD f9, 9 * FREGBYTES(sp)\n+ FLOAD f10, 10 * FREGBYTES(sp)\n+ FLOAD f11, 11 * FREGBYTES(sp)\n+ FLOAD f12, 12 * FREGBYTES(sp)\n+ FLOAD f13, 13 * FREGBYTES(sp)\n+ FLOAD f14, 14 * FREGBYTES(sp)\n+ FLOAD f15, 15 * FREGBYTES(sp)\n+ FLOAD f16, 16 * FREGBYTES(sp)\n+ FLOAD f17, 17 * FREGBYTES(sp)\n+ FLOAD f18, 18 * FREGBYTES(sp)\n+ FLOAD f19, 19 * FREGBYTES(sp)\n+ FLOAD f20, 20 * FREGBYTES(sp)\n+ FLOAD f21, 21 * FREGBYTES(sp)\n+ FLOAD f22, 22 * FREGBYTES(sp)\n+ FLOAD f23, 23 * FREGBYTES(sp)\n+ FLOAD f24, 24 * FREGBYTES(sp)\n+ FLOAD f25, 25 * FREGBYTES(sp)\n+ FLOAD f26, 26 * FREGBYTES(sp)\n+ FLOAD f27, 27 * FREGBYTES(sp)\n+ FLOAD f28, 28 * FREGBYTES(sp)\n+ FLOAD f29, 29 * FREGBYTES(sp)\n+ FLOAD f30, 30 * FREGBYTES(sp)\n+ FLOAD f31, 31 * FREGBYTES(sp)\n+\n+ addi sp, sp, 32 * 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windows and python compatibility (#786)\n\n\n<|file_patch|>src/lib/exec.ts\ndiff --git a/src/lib/exec.ts b/src/lib/exec.ts\nindex 88e1507b56d0a09dab9506278809efd606ff6614..425e65ebe205bc36a84b0cf5cfd5825a49ed5ab7 100644\n--- a/src/lib/exec.ts\n+++ b/src/lib/exec.ts\n@@ -2,6 +2,7 @@ import { type SpawnOptions, type SpawnOptionsWithoutStdio, spawn } from 'node:ch\n \n import { normalizeExecutablePath } from './hooks/runtimes/utils.js';\n import { run } from './outputs.js';\n+import { cliDebugPrint } from './utils/cliDebugPrint.js';\n \n const windowsOptions: SpawnOptions = {\n \tshell: true,\n@@ -14,6 +15,8 @@ const windowsOptions: SpawnOptions = {\n const spawnPromised = async (cmd: string, args: string[], opts: SpawnOptionsWithoutStdio) => {\n \tconst escapedCommand = normalizeExecutablePath(cmd);\n \n+\tcliDebugPrint('SpawnPromised', { escapedCommand, args, opts });\n+\n \t// NOTE: Pipes stderr, stdout to main process\n \tconst childProcess = spawn(escapedCommand, args, {\n \t\t...opts,\n\n<|file_patch|>src/lib/hooks/runtimes/javascript.ts\ndiff --git a/src/lib/hooks/runtimes/javascript.ts b/src/lib/hooks/runtimes/javascript.ts\nindex e1d6516bab38218f1502dff99f6f8cc72ced3021..57ccb5f200d4342f6550fce762416faa7914be52 100644\n--- a/src/lib/hooks/runtimes/javascript.ts\n+++ b/src/lib/hooks/runtimes/javascript.ts\n@@ -6,6 +6,7 @@ import which from 'which';\n \n import type { Runtime } from '../useCwdProject.js';\n import { normalizeExecutablePath } from './utils.js';\n+import { cliDebugPrint } from '../../utils/cliDebugPrint.js';\n \n const cwdCache = new Map<string, Option<Runtime>>();\n \n@@ -51,6 +52,7 @@ export async function useJavaScriptRuntime(cwd = process.cwd()): Promise<Option<\n \tconst cached = cwdCache.get(cwd);\n \n \tif (cached) {\n+\t\tcliDebugPrint('useJavaScriptRuntime', { cacheHit: true, cwd, runtime: cached.unwrapOr(null) });\n \t\treturn cached;\n \t}\n \n@@ -86,6 +88,8 @@ export async function useJavaScriptRuntime(cwd = process.cwd()): Promise<Option<\n \n \t\t\t\tcwdCache.set(cwd, some(res));\n \n+\t\t\t\tcliDebugPrint('useJavaScriptRuntime', { cacheHit: false, cwd, runtime: cwdCache.get(cwd)?.unwrap() });\n+\n \t\t\t\treturn some(res);\n \t\t\t}\n \t\t} catch {\n@@ -95,5 +99,7 @@ export async function useJavaScriptRuntime(cwd = process.cwd()): Promise<Option<\n \n \tcwdCache.set(cwd, none);\n \n+\tcliDebugPrint('useJavaScriptRuntime', { cacheHit: false, cwd, runtime: null });\n+\n \treturn none;\n }\n\n<|file_patch|>src/lib/hooks/runtimes/python.ts\ndiff --git a/src/lib/hooks/runtimes/python.ts b/src/lib/hooks/runtimes/python.ts\nindex 82c14d935947f55d8cb64ecfc791e158fbd50060..65a102bdc1538527017257a3107338b6dc0fade6 100644\n--- a/src/lib/hooks/runtimes/python.ts\n+++ b/src/lib/hooks/runtimes/python.ts\n@@ -1,4 +1,3 @@\n-import { access } from 'node:fs/promises';\n import { platform } from 'node:os';\n import { join } from 'node:path';\n import process from 'node:process';\n@@ -9,6 +8,7 @@ import which from 'which';\n \n import type { Runtime } from '../useCwdProject.js';\n import { normalizeExecutablePath } from './utils.js';\n+import { cliDebugPrint } from '../../utils/cliDebugPrint.js';\n \n const cwdCache = new Map<string, Option<Runtime>>();\n \n@@ -44,6 +44,7 @@ export async function usePythonRuntime({\n \tconst cached = cwdCache.get(cwd);\n \n \tif (cached && !force) {\n+\t\tcliDebugPrint('usePythonRuntime', { cacheHit: true, cwd, runtime: cached.unwrapOr(null) });\n \t\treturn cached;\n \t}\n \n@@ -62,8 +63,6 @@ export async function usePythonRuntime({\n \tfullPythonVenvPath = normalizeExecutablePath(fullPythonVenvPath);\n \n \ttry {\n-\t\tawait access(fullPythonVenvPath);\n-\n \t\tconst version = await getPythonVersion(fullPythonVenvPath);\n \n \t\tif (version) {\n@@ -75,10 +74,9 @@ export async function usePythonRuntime({\n \t\t\t\t}),\n \t\t\t);\n \n-\t\t\treturn some({\n-\t\t\t\texecutablePath: fullPythonVenvPath,\n-\t\t\t\tversion,\n-\t\t\t});\n+\t\t\tcliDebugPrint('usePythonRuntime', { cacheHit: false, cwd, runtime: cwdCache.get(cwd)?.unwrap() });\n+\n+\t\t\treturn cwdCache.get(cwd)!;\n \t\t}\n \t} catch {\n \t\t// Ignore errors\n@@ -101,10 +99,9 @@ export async function usePythonRuntime({\n \t\t\t\t\t}),\n \t\t\t\t);\n \n-\t\t\t\treturn some({\n-\t\t\t\t\texecutablePath: fullPath,\n-\t\t\t\t\tversion,\n-\t\t\t\t});\n+\t\t\t\tcliDebugPrint('usePythonRuntime', { cacheHit: false, cwd, runtime: cwdCache.get(cwd)?.unwrap() });\n+\n+\t\t\t\treturn cwdCache.get(cwd)!;\n \t\t\t}\n \t\t} catch {\n \t\t\t// Continue\n@@ -113,5 +110,7 @@ export async function usePythonRuntime({\n \n \tcwdCache.set(cwd, none);\n \n+\tcliDebugPrint('usePythonRuntime', { cacheHit: false, cwd, runtime: null });\n+\n \treturn none;\n }\n\n<|file_patch|>src/lib/hooks/useActorConfig.ts\ndiff --git a/src/lib/hooks/useActorConfig.ts b/src/lib/hooks/useActorConfig.ts\nindex cc8c23f6d7f6d07a2f4c336fcb1efc6054de336b..4d565a72cd3f01a6118474313da49973c29793a7 100644\n--- a/src/lib/hooks/useActorConfig.ts\n+++ b/src/lib/hooks/useActorConfig.ts\n@@ -7,6 +7,7 @@ import { err, ok, type Result } from '@sapphire/result';\n \n import { ACTOR_SPECIFICATION_VERSION, DEPRECATED_LOCAL_CONFIG_NAME } from '../consts.js';\n import { error, info, warning } from '../outputs.js';\n+import { cliDebugPrint } from '../utils/cliDebugPrint.js';\n import { confirmAction } from '../utils/confirm.js';\n import { getJsonFileContent, getLocalConfigPath } from '../utils.js';\n \n@@ -43,6 +44,7 @@ export async function useActorConfig(\n \tconst cached = cwdCache.get(cwd);\n \n \tif (cached) {\n+\t\tcliDebugPrint('useActorConfig', { cacheHit: true, config: cached });\n \t\treturn ok(cached);\n \t}\n \n@@ -100,6 +102,8 @@ export async function useActorConfig(\n \n \tcwdCache.set(cwd, { exists: true, migrated, config: config || deprecatedConfig || {} });\n \n+\tcliDebugPrint('useActorConfig', { cacheHit: false, config: cwdCache.get(cwd) });\n+\n \treturn ok({ exists: true, migrated, config: config || deprecatedConfig || {} });\n }\n \n\n<|file_patch|>src/lib/hooks/useCwdProject.ts\ndiff --git a/src/lib/hooks/useCwdProject.ts b/src/lib/hooks/useCwdProject.ts\nindex 9ee08fe3583cf7de7cdbb9124effe71d12c07698..88b7ab916369602bd2a611a10819966136409af8 100644\n--- a/src/lib/hooks/useCwdProject.ts\n+++ b/src/lib/hooks/useCwdProject.ts\n@@ -7,6 +7,7 @@ import { ok, type Result } from '@sapphire/result';\n import { useJavaScriptRuntime } from './runtimes/javascript.js';\n import { usePythonRuntime } from './runtimes/python.js';\n import { ScrapyProjectAnalyzer } from '../projects/scrapy/ScrapyProjectAnalyzer.js';\n+import { cliDebugPrint } from '../utils/cliDebugPrint.js';\n \n export enum ProjectLanguage {\n \tJavaScript = 0,\n@@ -51,6 +52,7 @@ export async function useCwdProject({\n \tconst cached = cwdCache.get(cwd);\n \n \tif (cached) {\n+\t\tcliDebugPrint('useCwdProject', { cacheHit: true, project: cached });\n \t\treturn ok(cached);\n \t}\n \n@@ -124,9 +126,11 @@ export async function useCwdProject({\n \tconst maybeErr = await check();\n \n \tif (maybeErr?.isErr()) {\n+\t\tcliDebugPrint('useCwdProject', { cacheHit: false, error: maybeErr });\n \t\treturn maybeErr;\n \t}\n \n+\tcliDebugPrint('useCwdProject', { cacheHit: false, project });\n \tcwdCache.set(cwd, project);\n \n \treturn ok(project);\n\n<|file_patch|>src/lib/hooks/useModuleVersion.ts\ndiff --git a/src/lib/hooks/useModuleVersion.ts b/src/lib/hooks/useModuleVersion.ts\nindex 993fb1614d3b5ee7934e7d1f988837c55897a59a..1b6de39b1118fc1a5b02fc6001913ea84ed27cfc 100644\n--- a/src/lib/hooks/useModuleVersion.ts\n+++ b/src/lib/hooks/useModuleVersion.ts\n@@ -2,6 +2,7 @@ import { none, some, type Option } from '@sapphire/result';\n import { execa } from 'execa';\n \n import { ProjectLanguage, type CwdProject } from './useCwdProject.js';\n+import { cliDebugPrint } from '../utils/cliDebugPrint.js';\n \n export interface UseModuleVersionInput {\n \tmoduleName: string;\n@@ -77,6 +78,7 @@ const moduleVersionScripts: Record<string, (mod: string) => string[]> = {\n \n export async function useModuleVersion({ moduleName, project }: UseModuleVersionInput): Promise<Option<string>> {\n \tif (!project.runtime) {\n+\t\tcliDebugPrint('useModuleVersion', { status: 'no_runtime_found', project, moduleName });\n \t\treturn none;\n \t}\n \n@@ -87,12 +89,14 @@ export async function useModuleVersion({ moduleName, project }: UseModuleVersion\n \t} else if (project.type === ProjectLanguage.Python || project.type === ProjectLanguage.Scrapy) {\n \t\tmoduleVersionScriptKey = 'python';\n \t} else {\n+\t\tcliDebugPrint('useModuleVersion', { status: 'unsupported_project_type', project, moduleName });\n \t\treturn none;\n \t}\n \n \tconst args = moduleVersionScripts[moduleVersionScriptKey]?.(moduleName);\n \n \tif (!args) {\n+\t\tcliDebugPrint('useModuleVersion', { status: 'no_version_script_found', project, moduleName });\n \t\treturn none;\n \t}\n \n@@ -103,11 +107,15 @@ export async function useModuleVersion({ moduleName, project }: UseModuleVersion\n \t\t});\n \n \t\tif (result.stdout.trim() === 'n/a') {\n+\t\t\tcliDebugPrint('useModuleVersion', { status: 'no_version_found', project, moduleName });\n \t\t\treturn none;\n \t\t}\n \n+\t\tcliDebugPrint('useModuleVersion', { status: 'success', project, moduleName, version: result.stdout.trim() });\n+\n \t\treturn some(result.stdout.trim());\n-\t} catch {\n+\t} catch (ex) {\n+\t\tcliDebugPrint('useModuleVersion', { status: 'failed_to_run_version_script', project, moduleName, error: ex });\n \t\treturn none;\n \t}\n }\n\n<|file_patch|>src/lib/utils/cliDebugPrint.ts\ndiff --git a/src/lib/utils/cliDebugPrint.ts b/src/lib/utils/cliDebugPrint.ts\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5be03800cba7bf4be6c8a2074e803e8037e87d70\n--- /dev/null\n+++ b/src/lib/utils/cliDebugPrint.ts\n@@ -0,0 +1,7 @@\n+import chalk from 'chalk';\n+\n+export function cliDebugPrint(tag: string, ...args: unknown[]) {\n+\tif (process.env.APIFY_CLI_DEBUG) {\n+\t\tconsole.error(chalk.gray(`[${tag}]`), ...args);\n+\t}\n+}\n\n"},"target_character_start":{"kind":"number","value":66,"string":"66"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-04"},"utf8_bytes":{"kind":"number","value":9588,"string":"9,588"},"document_order_key":{"kind":"number","value":2942070964995831300,"string":"2,942,070,964,995,831,300"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/apify/apify-cli"},"quality_band":{"kind":"string","value":"04"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"typescript"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/apify/apify-cli\",\"commit_oid\":\"eeca37df62461a0ca1fa6f2f72386b18eb65a077\",\"commits_ago_from_head\":589,\"content_sha256\":\"6cb68458f0aa580cf58236a2d59d82e0f2fb537a517eb7ca60c9ff95d9aacfa7\",\"manifest_sha256\":null,\"parent_oid\":\"d46ea671318e98fa00891bedaf6a5160e5efd602\",\"repository_id\":\"github.com/apify/apify-cli\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"04\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":4},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[\"#786\"],\"message_words\":6,\"scope\":null,\"subject_length\":39,\"trailer_names\":[],\"type\":\"fix\"},\"patch_statistics\":{\"added_lines\":43,\"context_bytes\":21331,\"deleted_lines\":12,\"files_changed\":7,\"hunk_count\":24,\"patch_bytes\":9203,\"patch_sha256\":\"cf96a2c4f1919829d6b51892a1f9528eb1b017373e7b50bc64ec074cbc8c0357\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"typescript\",\"path\":\"src/lib/exec.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/hooks/runtimes/javascript.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/hooks/runtimes/python.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/hooks/useActorConfig.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/hooks/useCwdProject.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/hooks/useModuleVersion.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"src/lib/utils/cliDebugPrint.ts\",\"purpose\":\"source\"}],\"primary_language\":\"typescript\"},\"quality_band\":\"04\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":21331,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":7,\"files_kept\":7,\"patch_bytes\":9203},\"commit_oid\":\"eeca37df62461a0ca1fa6f2f72386b18eb65a077\",\"identity\":{\"author_email\":\"me@vladfrangu.dev\",\"author_name\":\"Vlad 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opts.gzip_patterns\n\n<|file_patch|>lib/lactate.js\ndiff --git a/lib/lactate.js b/lib/lactate.js\nindex c80bd23702dab8bb806749c3f5bf1f46a48c6db6..8dccbbdbd2af6220acc9830e1495507b3db5b6ef 100644\n--- a/lib/lactate.js\n+++ b/lib/lactate.js\n@@ -57,24 +57,22 @@ function Lactate(options) {\n , error_pages: true\n \n //Directory options\n-\n , subdirs: true\n , autoindex: false\n , bundle: false\n , rebundle: true\n \n //Caching options\n-\n , cache: true\n , redis_cache: false\n , watch_files: true\n , max_age: 86400 * 2\n \n //Response options\n-\n , headers: {}\n , dynamic_headers: {}\n , gzip: true\n+ , gzip_patterns: []\n , minify: false\n \n , debug: false\n@@ -105,7 +103,14 @@ Lactate.prototype.isHidden = function(fp) {\n };\n \n Lactate.prototype.isText = function(contentType) {\n- return /^text/.test(contentType) || /(\\+|\\/)xml$/.test(contentType);\n+ var patterns = this.get('gzip patterns');\n+\n+ var patternMatch = patterns.length \n+ && patterns.some(function(pattern) {\n+ return pattern.test(contentType)\n+ });\n+\n+ return patternMatch || /^text/.test(contentType);\n };\n \n Lactate.prototype.isCompressible = function(extension) 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unit test for opening/closing RemoteSyslogChannel\n\n<|file_patch|>Net/src/RemoteSyslogChannel.cpp\ndiff --git a/Net/src/RemoteSyslogChannel.cpp b/Net/src/RemoteSyslogChannel.cpp\nindex a33aefd6ad744221dc107775787dc3c2e973e714..37e32153bd011b643f297aa38463f6c9efc129cf 100644\n--- a/Net/src/RemoteSyslogChannel.cpp\n+++ b/Net/src/RemoteSyslogChannel.cpp\n@@ -89,8 +89,8 @@ void RemoteSyslogChannel::open()\n {\n \tif (_open) return;\n \n- // reset socket for the case that it has been previously closed\n- _socket = DatagramSocket();\n+\t// reset socket for the case that it has been previously closed\n+\t_socket = DatagramSocket();\n \n \tif (_logHost.find(':') != std::string::npos)\n \t\t_socketAddress = SocketAddress(_logHost);\n@@ -108,8 +108,8 @@ void RemoteSyslogChannel::open()\n \t\t\t_host = _socket.address().host().toString();\n \t\t}\n \t}\n- \n- _open = true;\n+\n+\t_open = true;\n }\n \n \t\n\n<|file_patch|>Net/testsuite/src/SyslogTest.cpp\ndiff --git a/Net/testsuite/src/SyslogTest.cpp b/Net/testsuite/src/SyslogTest.cpp\nindex 953f6babd0c63679ea6777de80fe721fef1f4b94..a6190e967c6d10fb8f907a4194de735eb39a35b8 100644\n--- a/Net/testsuite/src/SyslogTest.cpp\n+++ b/Net/testsuite/src/SyslogTest.cpp\n@@ -167,6 +167,45 @@ void SyslogTest::testListener()\n }\n \n \n+void SyslogTest::testChannelOpenClose()\n+{\n+\tPoco::AutoPtr<RemoteSyslogChannel> channel = new RemoteSyslogChannel();\n+\tchannel->setProperty(\"loghost\", \"localhost:51400\");\n+\tchannel->open();\n+\tPoco::AutoPtr<RemoteSyslogListener> listener = new RemoteSyslogListener(51400);\n+\tlistener->open();\n+\tCachingChannel cl;\n+\tlistener->addChannel(&cl);\n+\n+\tassert (cl.getCurrentSize() == 0);\n+\tPoco::Message msg1(\"source1\", \"message1\", Poco::Message::PRIO_CRITICAL);\n+\tchannel->log(msg1);\n+\tPoco::Thread::sleep(1000);\n+\tassert (cl.getCurrentSize() == 1);\n+\n+\tchannel->close(); // close and re-open channel\n+\tchannel->open();\n+\n+\tPoco::Message msg2(\"source2\", \"message2\", Poco::Message::PRIO_ERROR);\n+\tchannel->log(msg2);\n+\tPoco::Thread::sleep(1000);\n+\tassert (cl.getCurrentSize() == 2);\n+\n+\tlistener->close();\n+\tstd::vector<Poco::Message> msgs;\n+\tcl.getMessages(msgs, 0, 10);\n+\tassert (msgs.size() == 2);\n+\n+\tassert (msgs[1].getSource() == \"source1\");\n+\tassert (msgs[1].getText() == \"message1\");\n+\tassert (msgs[1].getPriority() == Poco::Message::PRIO_CRITICAL);\n+\n+\tassert (msgs[0].getSource() == \"source2\");\n+\tassert (msgs[0].getText() == \"message2\");\n+\tassert (msgs[0].getPriority() == Poco::Message::PRIO_ERROR);\n+}\n+\n+\n void SyslogTest::testOldBSD()\n {\n \tPoco::AutoPtr<RemoteSyslogChannel> channel = new RemoteSyslogChannel();\n@@ -209,6 +248,7 @@ CppUnit::Test* SyslogTest::suite()\n \tCppUnit::TestSuite* pSuite = new CppUnit::TestSuite(\"SyslogTest\");\n \n \tCppUnit_addTest(pSuite, SyslogTest, testListener);\n+\tCppUnit_addTest(pSuite, SyslogTest, testChannelOpenClose);\n \tCppUnit_addTest(pSuite, SyslogTest, testOldBSD);\n \n \treturn pSuite;\n\n<|file_patch|>Net/testsuite/src/SyslogTest.h\ndiff --git a/Net/testsuite/src/SyslogTest.h b/Net/testsuite/src/SyslogTest.h\nindex a179dcc94f84676decc1a094727bf79930adc922..12d31b8d86b3499f0759fc849e6cb14e5db425e1 100644\n--- a/Net/testsuite/src/SyslogTest.h\n+++ b/Net/testsuite/src/SyslogTest.h\n@@ -47,6 +47,7 @@ public:\n \t~SyslogTest();\n \n \tvoid testListener();\n+\tvoid testChannelOpenClose();\n \tvoid testOldBSD();\n \n \tvoid setUp();\n\n"},"target_character_start":{"kind":"number","value":74,"string":"74"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-03"},"utf8_bytes":{"kind":"number","value":3328,"string":"3,328"},"document_order_key":{"kind":"number","value":2942786076754348000,"string":"2,942,786,076,754,348,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/alleninstitute/poco"},"quality_band":{"kind":"string","value":"03"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"cpp"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/alleninstitute/poco\",\"commit_oid\":\"7f17255ed8a0f90681a05249bc5f7566ae277009\",\"commits_ago_from_head\":2946,\"content_sha256\":\"fbce8b0447a817a842d17458158a76607746acf89a785e939b75106051ca426e\",\"manifest_sha256\":null,\"parent_oid\":\"a9284393b04e58da096520454ee2a91e6eb28b1d\",\"repository_id\":\"github.com/alleninstitute/poco\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"03\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":3},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":6,\"scope\":null,\"subject_length\":53,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":45,\"context_bytes\":16465,\"deleted_lines\":4,\"files_changed\":3,\"hunk_count\":5,\"patch_bytes\":3113,\"patch_sha256\":\"fbb9f7e244f6f8f8ce4656148e8a9928d28ead7001fb220bb5ada225a1c48110\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"cpp\",\"path\":\"Net/src/RemoteSyslogChannel.cpp\",\"purpose\":\"source\"},{\"language\":\"cpp\",\"path\":\"Net/testsuite/src/SyslogTest.cpp\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"Net/testsuite/src/SyslogTest.h\",\"purpose\":\"source\"}],\"primary_language\":\"cpp\"},\"quality_band\":\"03\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":16465,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":3,\"files_kept\":3,\"patch_bytes\":3113},\"commit_oid\":\"7f17255ed8a0f90681a05249bc5f7566ae277009\",\"identity\":{\"author_email\":\"mike.naquin@ncr.com\",\"author_name\":\"Mike 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Naquin\",\"parent_oid\":\"a9284393b04e58da096520454ee2a91e6eb28b1d\",\"tree_oid\":\"89d19021d844ca039075d8fe9a72828a19ee4bb0\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":4815,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"94832726810a3116ce8c9887c17675716dbb6243\",\"oldest_commit\":\"f476bd6b324b6151c6d45a6859735d617e872b38\"},\"recorded_head_commit\":\"94832726810a3116ce8c9887c17675716dbb6243\",\"repository_id\":\"github.com/alleninstitute/poco\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/alleninstitute/poco\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":22727,\"manifest_sha256\":null,\"split\":\"07-of-16\"}},\"parents\":[\"commit:github.com/alleninstitute/poco@7f17255ed8a0f90681a05249bc5f7566ae277009__download_changed_file_contents_636c19244993__render_commit_patches_84f60c50399c\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16033,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/bigmlcom/presto@74d73f1539828524506fccd2ca09e7634fe8f892"},"text":{"kind":"string","value":"<|commit_message|>\nZero out the progress update (bytes and rows per second) for completed stages\n\n<|file_patch|>presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java\ndiff --git a/presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java b/presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java\nindex d6078591fb4fde3f4c680254749460f97eaa3c4f..a5f875e296637e1026fb389aaa7d928b017468ff 100644\n--- a/presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java\n+++ b/presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java\n@@ -4,6 +4,7 @@ import com.facebook.presto.execution.ExecutionStats;\n import com.facebook.presto.execution.QueryInfo;\n import com.facebook.presto.execution.QueryState;\n import com.facebook.presto.execution.StageInfo;\n+import com.facebook.presto.execution.StageState;\n import com.facebook.presto.execution.TaskInfo;\n import com.facebook.presto.server.HttpQueryClient;\n import com.google.common.base.Preconditions;\n@@ -300,15 +301,28 @@ CPU wall: 16.1s 5.12MB/s total, 16.1s 5.12MB/s per node\n nameBuilder.append('.');\n }\n \n+\n+ StageState state = stage.getState();\n+ String bytesPerSecond;\n+ String rowsPerSecond;\n+ if (state.isDone()) {\n+ bytesPerSecond = formatDataRate(new DataSize(0, BYTE), new Duration(0, SECONDS), false);\n+ rowsPerSecond = formatCountRate(0, new Duration(0, SECONDS), false);\n+ }\n+ else {\n+ bytesPerSecond = formatDataRate(executionStats.getCompletedDataSize(), elapsedTime, false);\n+ rowsPerSecond = formatCountRate(executionStats.getInputPositionCount(), elapsedTime, false);\n+ }\n+\n String stageSummary = String.format(\"%10s%1s %5s %6s %5s %7s %5s %5s %5s\",\n nameBuilder.toString(),\n- stage.getState().toString().charAt(0),\n+ state.toString().charAt(0),\n \n formatCount(executionStats.getInputPositionCount()),\n- formatCountRate(executionStats.getInputPositionCount(), elapsedTime, false),\n+ rowsPerSecond,\n \n formatDataSize(executionStats.getInputDataSize(), false),\n- formatDataRate(executionStats.getCompletedDataSize(), elapsedTime, false),\n+ bytesPerSecond,\n \n max(0, executionStats.getSplits() - executionStats.getStartedSplits()),\n max(0, executionStats.getStartedSplits() - executionStats.getCompletedSplits()),\n\n"},"target_character_start":{"kind":"number","value":98,"string":"98"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-05"},"utf8_bytes":{"kind":"number","value":2524,"string":"2,524"},"document_order_key":{"kind":"number","value":2942787312829966000,"string":"2,942,787,312,829,966,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bigmlcom/presto"},"quality_band":{"kind":"string","value":"05"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"java"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bigmlcom/presto\",\"commit_oid\":\"74d73f1539828524506fccd2ca09e7634fe8f892\",\"commits_ago_from_head\":1266,\"content_sha256\":\"575e4993034f47c155c7f9580674a5884d811138b98463683f674e99781ae260\",\"manifest_sha256\":null,\"parent_oid\":\"c8e5230e8194fe6517fbc93f1f4d5e999bbc58a8\",\"repository_id\":\"github.com/bigmlcom/presto\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"05\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":5},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":13,\"scope\":null,\"subject_length\":77,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":17,\"context_bytes\":23075,\"deleted_lines\":3,\"files_changed\":1,\"hunk_count\":2,\"patch_bytes\":2342,\"patch_sha256\":\"ce25ad51ea0be15dcf1280ce84f1119b4a8dbaf66cf43a6e7dbef1a8e2151d58\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"java\",\"path\":\"presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java\",\"purpose\":\"source\"}],\"primary_language\":\"java\"},\"quality_band\":\"05\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":23075,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":2342},\"commit_oid\":\"74d73f1539828524506fccd2ca09e7634fe8f892\",\"identity\":{\"author_email\":\"martint@fb.com\",\"author_name\":\"Martin Traverso\",\"authored_at\":\"2013-01-16T17:33:20-08:00\",\"commit_oid\":\"74d73f1539828524506fccd2ca09e7634fe8f892\",\"commits_ago_from_head\":1266,\"committed_at\":\"2013-01-16T20:26:10-08:00\",\"committer_email\":\"martint@fb.com\",\"committer_name\":\"Martin Traverso\",\"parent_oid\":\"c8e5230e8194fe6517fbc93f1f4d5e999bbc58a8\",\"tree_oid\":\"c556cb408b4692cbc26764a7ca237a2ae58ad9dc\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":2133,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"69d42f2fbf14cc6ee99d7479535a844bc99ac5c5\",\"oldest_commit\":\"d0eb103a660125a53660a7ba2c95e9b8a4d8feb6\"},\"recorded_head_commit\":\"69d42f2fbf14cc6ee99d7479535a844bc99ac5c5\",\"repository_id\":\"github.com/bigmlcom/presto\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/bigmlcom/presto\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":69456,\"manifest_sha256\":null,\"split\":\"00-of-16\"}},\"parents\":[\"commit:github.com/bigmlcom/presto@74d73f1539828524506fccd2ca09e7634fe8f892__download_changed_file_contents_efb642a5d800__render_commit_patches_9c2279df53b0\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16034,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/angular/platform-browser-builds@e5b624432c05aadda06c58e95c399737eaaa5cf3"},"text":{"kind":"string","value":"<|commit_message|>\n141f310 refactor(core): standalone by default for JIT compiled directives (#58236)\n\n<|file_patch|>BUILD_INFO\ndiff --git a/BUILD_INFO b/BUILD_INFO\nindex 1612c97bc3b95cd8f2ecf6d91e2a9fc444ea7c70..3dc958bf4ce48c65fbccfc73546e6c9a561083b0 100644\n--- a/BUILD_INFO\n+++ b/BUILD_INFO\n@@ -1,2 +1,2 @@\n-Thu Oct 17 13:08:06 UTC 2024\n-94bc69aa03d7d380431630f10b795599f8d35985\n+Thu Oct 17 13:32:23 UTC 2024\n+141f3107e13c1ff226435718664d1052c6dea692\n\n<|file_patch|>fesm2022/animations.mjs\ndiff --git a/fesm2022/animations.mjs b/fesm2022/animations.mjs\nindex aa71d25262b5bc1dc0a3e259737c50c314957663..bd0006ffc716a1b1117b2f431fd8271f04606b58 100755\n--- a/fesm2022/animations.mjs\n+++ b/fesm2022/animations.mjs\n@@ -1,5 +1,5 @@\n /**\n- * @license Angular v19.0.0-next.10+sha-94bc69a\n+ * @license Angular v19.0.0-next.10+sha-141f310\n * (c) 2010-2024 Google LLC. https://angular.io/\n * License: MIT\n */\n@@ -22,10 +22,10 @@ class InjectableAnimationEngine extends ɵAnimationEngine {\n ngOnDestroy() {\n this.flush();\n }\n- static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: InjectableAnimationEngine, deps: [{ token: DOCUMENT }, { token: i1.AnimationDriver }, { token: i1.ɵAnimationStyleNormalizer }], target: i0.ɵɵFactoryTarget.Injectable }); }\n- static { this.ɵprov = i0.ɵɵngDeclareInjectable({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: InjectableAnimationEngine }); }\n+ static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: InjectableAnimationEngine, deps: [{ token: DOCUMENT }, { token: i1.AnimationDriver }, { token: i1.ɵAnimationStyleNormalizer }], target: i0.ɵɵFactoryTarget.Injectable }); }\n+ static { this.ɵprov = i0.ɵɵngDeclareInjectable({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: InjectableAnimationEngine }); }\n }\n-i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: InjectableAnimationEngine, decorators: [{\n+i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: InjectableAnimationEngine, decorators: [{\n type: Injectable\n }], ctorParameters: () => [{ type: Document, decorators: [{\n type: Inject,\n@@ -95,11 +95,11 @@ class BrowserAnimationsModule {\n : BROWSER_ANIMATIONS_PROVIDERS,\n };\n }\n- static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserAnimationsModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n- static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserAnimationsModule, exports: [BrowserModule] }); }\n- static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserAnimationsModule, providers: BROWSER_ANIMATIONS_PROVIDERS, imports: [BrowserModule] }); }\n+ static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserAnimationsModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n+ static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserAnimationsModule, exports: [BrowserModule] }); }\n+ static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserAnimationsModule, providers: BROWSER_ANIMATIONS_PROVIDERS, imports: [BrowserModule] }); }\n }\n-i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserAnimationsModule, decorators: [{\n+i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserAnimationsModule, decorators: [{\n type: NgModule,\n args: [{\n exports: [BrowserModule],\n@@ -139,11 +139,11 @@ function provideAnimations() {\n * @publicApi\n */\n class NoopAnimationsModule {\n- static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: NoopAnimationsModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n- static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: NoopAnimationsModule, exports: [BrowserModule] }); }\n- static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: NoopAnimationsModule, providers: BROWSER_NOOP_ANIMATIONS_PROVIDERS, imports: [BrowserModule] }); }\n+ static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: NoopAnimationsModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n+ static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: NoopAnimationsModule, exports: [BrowserModule] }); }\n+ static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: NoopAnimationsModule, providers: BROWSER_NOOP_ANIMATIONS_PROVIDERS, imports: [BrowserModule] }); }\n }\n-i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: NoopAnimationsModule, decorators: [{\n+i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: NoopAnimationsModule, decorators: [{\n type: NgModule,\n args: [{\n exports: [BrowserModule],\n\n<|file_patch|>fesm2022/animations/async.mjs\ndiff --git a/fesm2022/animations/async.mjs b/fesm2022/animations/async.mjs\nindex aa3248f8a5505fdbb2cc520f7df0c920286c82af..a41d7a781ef330ade12a54cde265df1463b9ba11 100755\n--- a/fesm2022/animations/async.mjs\n+++ b/fesm2022/animations/async.mjs\n@@ -1,5 +1,5 @@\n /**\n- * @license Angular v19.0.0-next.10+sha-94bc69a\n+ * @license Angular v19.0.0-next.10+sha-141f310\n * (c) 2010-2024 Google LLC. https://angular.io/\n * License: MIT\n */\n@@ -114,10 +114,10 @@ class AsyncAnimationRendererFactory {\n whenRenderingDone() {\n return this.delegate.whenRenderingDone?.() ?? Promise.resolve();\n }\n- static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: AsyncAnimationRendererFactory, deps: \"invalid\", target: i0.ɵɵFactoryTarget.Injectable }); }\n- static { this.ɵprov = i0.ɵɵngDeclareInjectable({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: AsyncAnimationRendererFactory }); }\n+ static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: AsyncAnimationRendererFactory, deps: \"invalid\", target: i0.ɵɵFactoryTarget.Injectable }); }\n+ static { this.ɵprov = i0.ɵɵngDeclareInjectable({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: AsyncAnimationRendererFactory }); }\n }\n-i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: AsyncAnimationRendererFactory, decorators: [{\n+i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: AsyncAnimationRendererFactory, decorators: [{\n type: Injectable\n }], ctorParameters: () => [{ type: Document }, { type: i0.RendererFactory2 }, { type: i0.NgZone }, { type: undefined }, { type: Promise }] });\n /**\n\n<|file_patch|>fesm2022/testing.mjs\ndiff --git a/fesm2022/testing.mjs b/fesm2022/testing.mjs\nindex b366a7cf0fee1504f5f6a4e69f23f1abccdb9532..c7909a30225af4d80591f1ecd1aa9e2c14c8f918 100755\n--- a/fesm2022/testing.mjs\n+++ b/fesm2022/testing.mjs\n@@ -1,5 +1,5 @@\n /**\n- * @license Angular v19.0.0-next.10+sha-94bc69a\n+ * @license Angular v19.0.0-next.10+sha-141f310\n * (c) 2010-2024 Google LLC. https://angular.io/\n * License: MIT\n */\n@@ -28,16 +28,16 @@ const platformBrowserTesting = createPlatformFactory(platformCore, 'browserTesti\n * @publicApi\n */\n class BrowserTestingModule {\n- static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserTestingModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n- static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserTestingModule, exports: [BrowserModule] }); }\n- static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserTestingModule, providers: [\n+ static { this.ɵfac = i0.ɵɵngDeclareFactory({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserTestingModule, deps: [], target: i0.ɵɵFactoryTarget.NgModule }); }\n+ static { this.ɵmod = i0.ɵɵngDeclareNgModule({ minVersion: \"14.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserTestingModule, exports: [BrowserModule] }); }\n+ static { this.ɵinj = i0.ɵɵngDeclareInjector({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserTestingModule, providers: [\n { provide: APP_ID, useValue: 'a' },\n ɵinternalProvideZoneChangeDetection({}),\n { provide: ɵChangeDetectionScheduler, useExisting: ɵChangeDetectionSchedulerImpl },\n { provide: PlatformLocation, useClass: MockPlatformLocation },\n ], imports: [BrowserModule] }); }\n }\n-i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-94bc69a\", ngImport: i0, type: BrowserTestingModule, decorators: [{\n+i0.ɵɵngDeclareClassMetadata({ minVersion: \"12.0.0\", version: \"19.0.0-next.10+sha-141f310\", ngImport: i0, type: BrowserTestingModule, decorators: [{\n type: NgModule,\n args: [{\n exports: [BrowserModule],\n\n<|file_patch|>package.json\ndiff --git a/package.json b/package.json\nindex edf6b96d5d73a5e772df2ae2c93b21b38618839d..8f3d961e43cd313e8fe64fd6bfb8f574cb3256b7 100755\n--- a/package.json\n+++ b/package.json\n@@ -1,6 +1,6 @@\n {\n \"name\": \"@angular/platform-browser\",\n- \"version\": \"19.0.0-next.10+sha-94bc69a\",\n+ \"version\": \"19.0.0-next.10+sha-141f310\",\n \"description\": \"Angular - library for using Angular in a web browser\",\n \"author\": \"angular\",\n \"license\": \"MIT\",\n@@ -11,9 +11,9 @@\n \"tslib\": \"^2.3.0\"\n },\n \"peerDependencies\": {\n- \"@angular/animations\": \"19.0.0-next.10+sha-94bc69a\",\n- \"@angular/core\": \"19.0.0-next.10+sha-94bc69a\",\n- \"@angular/common\": \"19.0.0-next.10+sha-94bc69a\"\n+ \"@angular/animations\": \"19.0.0-next.10+sha-141f310\",\n+ \"@angular/core\": \"19.0.0-next.10+sha-141f310\",\n+ \"@angular/common\": \"19.0.0-next.10+sha-141f310\"\n },\n \"peerDependenciesMeta\": {\n \"@angular/animations\": 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builder.yaml\n\nSigned-off-by: Maxim Babichev <maksim.babichev95@gmail.com>\n<|file_patch|>.github/workflows/builder.yaml\ndiff --git a/.github/workflows/builder.yaml b/.github/workflows/builder.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0f35111db22178ad7b031b4825b0067963f66d75\n--- /dev/null\n+++ b/.github/workflows/builder.yaml\n@@ -0,0 +1,60 @@\n+name: builder\n+\n+on:\n+ push:\n+ tags:\n+ - \"v*.*.*\"\n+\n+jobs:\n+ docker:\n+ runs-on: ubuntu-latest\n+ steps:\n+ -\n+ name: Checkout\n+ uses: actions/checkout@v4\n+ -\n+ name: Docker meta\n+ id: meta\n+ uses: docker/metadata-action@v5\n+ with:\n+ images: |\n+ bavix/babichev-html\n+ ghcr.io/bavix/babichev-html\n+ tags: |\n+ type=ref,event=branch\n+ type=semver,pattern={{version}}\n+ type=semver,pattern={{major}}.{{minor}}\n+ type=semver,pattern={{major}}\n+ -\n+ name: Set up QEMU\n+ uses: docker/setup-qemu-action@v3\n+ -\n+ name: Set up Docker Buildx\n+ uses: docker/setup-buildx-action@v3\n+ -\n+ name: Login to GitHub Container Registry\n+ if: github.event_name != 'pull_request'\n+ uses: docker/login-action@v3\n+ with:\n+ registry: ghcr.io\n+ username: ${{ github.actor }}\n+ password: ${{ secrets.GITHUB_TOKEN }}\n+ -\n+ name: Login to Dockerhub Container Registry\n+ if: github.event_name != 'pull_request'\n+ uses: docker/login-action@v3\n+ with:\n+ username: ${{ secrets.DOCKERHUB_LOGIN }}\n+ password: ${{ secrets.DOCKERHUB_TOKEN }}\n+ -\n+ name: Build and push\n+ uses: docker/build-push-action@v5\n+ with:\n+ context: .\n+ push: ${{ github.event_name != 'pull_request' }}\n+ tags: ${{ steps.meta.outputs.tags }}\n+ labels: ${{ steps.meta.outputs.labels }}\n+ platforms: linux/amd64,linux/arm64\n+ build-args: |\n+ version=${{ github.ref_name }}\n+ outputs: type=image,name=target,annotation-index.org.opencontainers.image.description=babichev web\n\n"},"target_character_start":{"kind":"number","value":100,"string":"100"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-09"},"utf8_bytes":{"kind":"number","value":2210,"string":"2,210"},"document_order_key":{"kind":"number","value":2942853982750448000,"string":"2,942,853,982,750,448,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bavix/babichev-html"},"quality_band":{"kind":"string","value":"09"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"yaml"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bavix/babichev-html\",\"commit_oid\":\"166da5f4718687b3346c70560a73982b028108ab\",\"commits_ago_from_head\":27,\"content_sha256\":\"3146df5e1ffdb0bbe9a0e0e49f930520702f982585d6cdcd3b44f9871928493a\",\"manifest_sha256\":null,\"parent_oid\":\"66160093910fc938d9e04acb3887f74c94533d59\",\"repository_id\":\"github.com/bavix/babichev-html\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"09\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":9},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":6,\"scope\":null,\"subject_length\":19,\"trailer_names\":[\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":60,\"context_bytes\":0,\"deleted_lines\":0,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":2064,\"patch_sha256\":\"b6f0c4dfd696b64092d1a812fd433245f57085d2ebe67975ddeeab264c2ef44d\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"yaml\",\"path\":\".github/workflows/builder.yaml\",\"purpose\":\"config\"}],\"primary_language\":\"yaml\"},\"quality_band\":\"09\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":0,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":2064},\"commit_oid\":\"166da5f4718687b3346c70560a73982b028108ab\",\"identity\":{\"author_email\":\"maksim.babichev95@gmail.com\",\"author_name\":\"Maxim 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periods added.\n<|file_patch|>addons/map_gestures/stringtable.xml\ndiff --git a/addons/map_gestures/stringtable.xml b/addons/map_gestures/stringtable.xml\nindex 9c61d59292d89d4bc06a9a781ee1b9f57370ce61..0118b4323e5d253a1a6d698e0b3e90b87e6162f3 100644\n--- a/addons/map_gestures/stringtable.xml\n+++ b/addons/map_gestures/stringtable.xml\n@@ -29,7 +29,7 @@\n <Key ID=\"STR_ACE_map_gestures_defaultLeadAlpha_description\">\n <English>Fallback Alpha value for group leaders.</English>\n <Portuguese>Valor de transparência alternativo para líderes de grupo</Portuguese>\n- <Russian>Значение прозрачности для лидеров групп</Russian>\n+ <Russian>Значение прозрачности для лидеров групп.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_defaultAlpha_displayName\">\n <English>Default Alpha</English>\n@@ -39,7 +39,7 @@\n <Key ID=\"STR_ACE_map_gestures_defaultAlpha_descriptions\">\n <English>Fallback Alpha value.</English>\n <Portuguese>Valor alternativo de transparência</Portuguese>\n- <Russian>Значение прозрачности по-умолчанию</Russian>\n+ <Russian>Значение прозрачности по-умолчанию.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_defaultLeadColor_displayName\">\n <English>Lead Default Color</English>\n@@ -49,7 +49,7 @@\n <Key ID=\"STR_ACE_map_gestures_defaultLeadColor_description\">\n <English>Fallback Color value for group leaders.</English>\n <Portuguese>Valor de cor alternativa para líderes de grupo</Portuguese>\n- <Russian>Значение цвета для лидеров групп</Russian>\n+ <Russian>Значение цвета для лидеров групп.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_defaultColor_displayName\">\n <English>Default Color</English>\n@@ -59,7 +59,7 @@\n <Key ID=\"STR_ACE_map_gestures_defaultColor_description\">\n <English>Fallback Color value.</English>\n <Portuguese>Valor alternativo de cor</Portuguese>\n- <Russian>Значение цвета</Russian>\n+ <Russian>Значение цвета.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_leadAlpha_displayName\">\n <English>Lead Alpha</English>\n@@ -124,12 +124,12 @@\n <Key ID=\"STR_ACE_map_gestures_GroupColorConfigurations_description\">\n <English>Group color configuration containing arrays of color pairs ([leadColor, color]).</English>\n <Portuguese>Configuração de cores de grupo contendo arrays com pares de cores ([leadColor, color]).</Portuguese>\n- <Russian>Конфигурация цвета групп содержит массив цветовых пар ([лид. цвет, цвет])</Russian>\n+ <Russian>Конфигурация цвета групп содержит массив цветовых пар ([лид. цвет, цвет]).</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_GroupColorConfigurationMapping_description\">\n <English>Hash of Group ID mapped to the Group color configuration index.</English>\n <Portuguese>Hashes de ID de grupos mapeados para o índice de configuração de cor de grupos.</Portuguese>\n- <Russian>Хеш ID групп, соответствующих индексам конфигурации цвета групп</Russian>\n+ <Russian>Хеш ID групп, соответствующих индексам конфигурации цвета групп.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_GroupColorConfigurationMapping_displayName\">\n <English>GroupID Color configuration mapping</English>\n@@ -139,7 +139,7 @@\n <Key ID=\"STR_ACE_map_gestures_enabled_description\">\n <English>Enables the Map Gestures.</English>\n <Portuguese>Ativa os gestos no mapa</Portuguese>\n- <Russian>Включает указания на карте</Russian>\n+ <Russian>Включает указания на карте.</Russian>\n </Key>\n <Key ID=\"STR_ACE_map_gestures_nameTextColor_displayName\">\n <English>Name Text Color</English>\n@@ -157,4 +157,4 @@\n <Russian>Указания на карте</Russian>\n </Key>\n </Package>\n-</Project>\n\\ No newline at end of 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not import `transformer_engine` on import (#3056)\n\n* Do not import `transformer_engine` on import\r\n\r\n* fix message\r\n\r\n* add test\r\n\r\n* Update test_imports.py\r\n\r\n* resolve comment 1/2\r\n\r\n* resolve comment 1.5/2\r\n\r\n* lint\r\n\r\n* more lint\r\n\r\n* Update tests/test_imports.py\r\n\r\nCo-authored-by: Zach Mueller <muellerzr@gmail.com>\r\n\r\n* fmt\r\n\r\n---------\r\n\r\nCo-authored-by: Zach Mueller <muellerzr@gmail.com>\n<|file_patch|>src/accelerate/utils/transformer_engine.py\ndiff --git a/src/accelerate/utils/transformer_engine.py b/src/accelerate/utils/transformer_engine.py\nindex c5ac0a2e396aa4a3b8dd91e0485a62d8722f803d..0899c463de42cc9e8adf3c842b2cc6fa49b5050f 100644\n--- a/src/accelerate/utils/transformer_engine.py\n+++ b/src/accelerate/utils/transformer_engine.py\n@@ -20,8 +20,7 @@ from .imports import is_fp8_available\n from .operations import GatheredParameters\n \n \n-if is_fp8_available():\n- import transformer_engine.pytorch as te\n+# Do not import `transformer_engine` at package level to avoid potential issues\n \n \n def convert_model(model, to_transformer_engine=True, _convert_linear=True, _convert_ln=True):\n@@ -30,6 +29,8 @@ def convert_model(model, to_transformer_engine=True, _convert_linear=True, _conv\n \"\"\"\n if not is_fp8_available():\n raise ImportError(\"Using `convert_model` requires transformer_engine to be installed.\")\n+ import transformer_engine.pytorch as te\n+\n for name, module in model.named_children():\n if isinstance(module, nn.Linear) and to_transformer_engine and _convert_linear:\n has_bias = module.bias is not None\n@@ -87,6 +88,8 @@ def has_transformer_engine_layers(model):\n \"\"\"\n if not is_fp8_available():\n raise ImportError(\"Using `has_transformer_engine_layers` requires transformer_engine to be installed.\")\n+ import transformer_engine.pytorch as te\n+\n for m in model.modules():\n if isinstance(m, (te.LayerNorm, te.Linear, te.TransformerLayer)):\n return True\n@@ -98,6 +101,8 @@ def contextual_fp8_autocast(model_forward, fp8_recipe, use_during_eval=False):\n Wrapper for a model's forward method to apply FP8 autocast. Is context aware, meaning that by default it will\n disable FP8 autocast during eval mode, which is generally better for more accurate metrics.\n \"\"\"\n+ if not is_fp8_available():\n+ raise ImportError(\"Using `contextual_fp8_autocast` requires transformer_engine to be installed.\")\n from transformer_engine.pytorch import fp8_autocast\n \n def forward(self, *args, **kwargs):\n@@ -115,7 +120,8 @@ def apply_fp8_autowrap(model, fp8_recipe_handler):\n \"\"\"\n Applies FP8 context manager to the model's forward method\n \"\"\"\n- # Import here to keep base imports fast\n+ if not is_fp8_available():\n+ raise ImportError(\"Using `apply_fp8_autowrap` requires transformer_engine to be installed.\")\n import transformer_engine.common.recipe as te_recipe\n \n kwargs = fp8_recipe_handler.to_kwargs() if fp8_recipe_handler is not None else {}\n\n<|file_patch|>tests/test_imports.py\ndiff --git a/tests/test_imports.py b/tests/test_imports.py\nindex d3ad7caa1fadb9121759320d3b146a85c4dab2b6..57e49dcd9a275ff7130c62aba4191512d3ead67d 100644\n--- a/tests/test_imports.py\n+++ b/tests/test_imports.py\n@@ -12,7 +12,9 @@\n # See the License for the specific language governing permissions and\n # limitations under the License.\n import subprocess\n+import sys\n \n+from accelerate.test_utils import require_transformer_engine\n from accelerate.test_utils.testing import TempDirTestCase, require_import_timer\n from accelerate.utils import is_import_timer_available\n \n@@ -31,7 +33,7 @@ def convert_list_to_string(data):\n \n \n def run_import_time(command: str):\n- output = subprocess.run([\"python3\", \"-X\", \"importtime\", \"-c\", command], capture_output=True, text=True)\n+ output = subprocess.run([sys.executable, \"-X\", \"importtime\", \"-c\", command], capture_output=True, text=True)\n return output.stderr\n \n \n@@ -81,3 +83,18 @@ class ImportSpeedTester(TempDirTestCase):\n paths_above_threshold = get_paths_above_threshold(sorted_data, 0.05, max_depth=7)\n err_msg += f\"\\n{convert_list_to_string(paths_above_threshold)}\"\n self.assertLess(pct_more, 20, err_msg)\n+\n+\n+@require_transformer_engine\n+class LazyImportTester(TempDirTestCase):\n+ \"\"\"\n+ Test suite which checks if specific packages are lazy-loaded.\n+\n+ Eager-import will trigger circular import in some case,\n+ e.g. in huggingface/accelerate#3056.\n+ \"\"\"\n+\n+ def test_te_import(self):\n+ output = run_import_time(\"import accelerate, accelerate.utils.transformer_engine\")\n+\n+ self.assertFalse(\" transformer_engine\" in output, \"`transformer_engine` should not be imported on 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docker build (#651)\n\n\n<|file_patch|>.circleci/config.yml\ndiff --git a/.circleci/config.yml b/.circleci/config.yml\nindex 3465a4aab565a4614e4e15824555668aa90344b4..8d2703df6c0acb3ba9b0dead445b8096d79559a2 100644\n--- a/.circleci/config.yml\n+++ b/.circleci/config.yml\n@@ -51,6 +51,10 @@ jobs:\n working_directory: ~/repo\n steps:\n - attach_workspace: *attach_work_dir\n+\n+ - setup_remote_docker:\n+ version: 19.03.13\n+\n # - run:\n # name: Release\n # command: yarn semantic-release\n\n<|file_patch|>Dockerfile\ndiff --git a/Dockerfile b/Dockerfile\nindex d30440745015510bb25d348dd439ef18548c9d62..b82fa8dc25922a41e89bb06dc2bfbad17ef365cd 100644\n--- a/Dockerfile\n+++ b/Dockerfile\n@@ -3,6 +3,9 @@ FROM node:14.16.1-alpine AS base\n \n ENV NODE_ENV production\n \n+# Install dependencies for native deps\n+RUN apk add --no-cache bash python3\n+\n # Setup the app WORKDIR\n WORKDIR /app\n \n\n"},"target_character_start":{"kind":"number","value":46,"string":"46"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-03"},"utf8_bytes":{"kind":"number","value":942,"string":"942"},"document_order_key":{"kind":"number","value":2943692781184088600,"string":"2,943,692,781,184,088,600"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/algolia/npm-search"},"quality_band":{"kind":"string","value":"03"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"dockerfile"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/algolia/npm-search\",\"commit_oid\":\"947058d273bce51103cb117a1f1a25c1d34bacb1\",\"commits_ago_from_head\":433,\"content_sha256\":\"932a48c8d195baf7de2e49a790a4078d5ab33a3369380e9c91b776f30f9b6268\",\"manifest_sha256\":null,\"parent_oid\":\"95587a31832655a98d3de9038e137112f9b51418\",\"repository_id\":\"github.com/algolia/npm-search\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"03\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":3},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[\"#651\"],\"message_words\":4,\"scope\":null,\"subject_length\":19,\"trailer_names\":[],\"type\":\"fix\"},\"patch_statistics\":{\"added_lines\":7,\"context_bytes\":2302,\"deleted_lines\":0,\"files_changed\":2,\"hunk_count\":2,\"patch_bytes\":834,\"patch_sha256\":\"e98486610c14fc845dc667981ad799ecf05b514ddf13c7d418822b95125e77bf\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"yaml\",\"path\":\".circleci/config.yml\",\"purpose\":\"config\"},{\"language\":\"dockerfile\",\"path\":\"Dockerfile\",\"purpose\":\"source\"}],\"primary_language\":\"dockerfile\"},\"quality_band\":\"03\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":2302,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":2,\"patch_bytes\":834},\"commit_oid\":\"947058d273bce51103cb117a1f1a25c1d34bacb1\",\"identity\":{\"author_email\":\"samuel.bodin@algolia.com\",\"author_name\":\"Samuel Bodin\",\"authored_at\":\"2021-07-10T18:05:16+02:00\",\"commit_oid\":\"947058d273bce51103cb117a1f1a25c1d34bacb1\",\"commits_ago_from_head\":433,\"committed_at\":\"2021-07-10T18:05:16+02:00\",\"committer_email\":\"noreply@github.com\",\"committer_name\":\"GitHub\",\"parent_oid\":\"95587a31832655a98d3de9038e137112f9b51418\",\"tree_oid\":\"b1d3eaaafe2290d93c2cf28604adebbc48adc1db\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":1174,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"1fbd06368e8b28901e7a90dce7a1e07c9224a1f6\",\"oldest_commit\":\"14771fa3cd417f47bf3cf2943019b680869ee362\"},\"recorded_head_commit\":\"1fbd06368e8b28901e7a90dce7a1e07c9224a1f6\",\"repository_id\":\"github.com/algolia/npm-search\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/algolia/npm-search\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":19661,\"manifest_sha256\":null,\"split\":\"13-of-16\"}},\"parents\":[\"commit:github.com/algolia/npm-search@947058d273bce51103cb117a1f1a25c1d34bacb1__download_changed_file_contents_70937ad38248__render_commit_patches_42c5b4a7561f\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16040,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/actiontech/tidb@01f132ed39a8c1fc9775d963c7b0b50415f7d024"},"text":{"kind":"string","value":"<|commit_message|>\nstats: fix bug when estimating row count for outdated histograms (#5552)\n\n\r\n\n<|file_patch|>plan/cbo_test.go\ndiff --git a/plan/cbo_test.go b/plan/cbo_test.go\nindex fba76a76d33353dc013703f2e518a4006d748ff7..0219cb6433edb037a5105834aa3e832a2d478835 100644\n--- a/plan/cbo_test.go\n+++ b/plan/cbo_test.go\n@@ -362,6 +362,36 @@ func (s *testAnalyzeSuite) TestAnalyze(c *C) {\n \t}\n }\n \n+func (s *testAnalyzeSuite) TestOutdatedAnalyze(c *C) {\n+\tdefer testleak.AfterTest(c)()\n+\tstore, dom, err := newStoreWithBootstrap()\n+\tc.Assert(err, IsNil)\n+\ttestKit := testkit.NewTestKit(c, store)\n+\tdefer func() {\n+\t\tdom.Close()\n+\t\tstore.Close()\n+\t}()\n+\ttestKit.MustExec(\"use test\")\n+\ttestKit.MustExec(\"create table t (a int, b int, index idx(a))\")\n+\tfor i := 0; i < 10; i++ {\n+\t\ttestKit.MustExec(fmt.Sprintf(\"insert into t values (%d,%d)\", i, i))\n+\t}\n+\th := dom.StatsHandle()\n+\th.DumpStatsDeltaToKV()\n+\ttestKit.MustExec(\"analyze table t\")\n+\ttestKit.MustExec(\"insert into t select * from t\")\n+\ttestKit.MustExec(\"insert into t select * from t\")\n+\ttestKit.MustExec(\"insert into t select * from t\")\n+\th.DumpStatsDeltaToKV()\n+\tc.Assert(h.Update(dom.InfoSchema()), IsNil)\n+\t// FIXME: The count for table scan is wrong.\n+\ttestKit.MustQuery(\"explain select * from t where a <= 5 and b <= 5\").Check(testkit.Rows(\n+\t\t\"TableScan_5 Selection_6 cop table:t, range:(-inf,+inf), keep order:false 28.799999999999997\",\n+\t\t\"Selection_6 TableScan_5 cop le(test.t.a, 5), le(test.t.b, 5) 28.799999999999997\",\n+\t\t\"TableReader_7 root data:Selection_6 28.799999999999997\",\n+\t))\n+}\n+\n func (s *testAnalyzeSuite) TestPreparedNullParam(c *C) {\n \tdefer testleak.AfterTest(c)()\n \tstore, dom, err := newStoreWithBootstrap()\n\n<|file_patch|>statistics/histogram.go\ndiff --git a/statistics/histogram.go b/statistics/histogram.go\nindex cd3f228299e34ae3929f73e65abf47fb8443c626..27ebbc281cd72abe39e5292c86608e84514b6dcf 100644\n--- a/statistics/histogram.go\n+++ b/statistics/histogram.go\n@@ -478,14 +478,13 @@ func (c *Column) equalRowCount(sc *stmtctx.StatementContext, val types.Datum) (f\n }\n \n // getIntColumnRowCount estimates the row count by a slice of IntColumnRange.\n-func (c *Column) getIntColumnRowCount(sc *stmtctx.StatementContext, intRanges []ranger.IntColumnRange,\n-\ttotalRowCount float64) (float64, error) {\n+func (c *Column) getIntColumnRowCount(sc *stmtctx.StatementContext, intRanges []ranger.IntColumnRange) (float64, error) {\n \tvar rowCount float64\n \tfor _, rg := range intRanges {\n \t\tvar cnt float64\n \t\tvar err error\n \t\tif rg.LowVal == math.MinInt64 && rg.HighVal == math.MaxInt64 {\n-\t\t\tcnt = totalRowCount\n+\t\t\tcnt = c.totalRowCount()\n \t\t} else if rg.LowVal == math.MinInt64 {\n \t\t\tcnt, err = c.lessAndEqRowCount(sc, types.NewIntDatum(rg.HighVal))\n \t\t} else if rg.HighVal == math.MaxInt64 {\n@@ -505,8 +504,8 @@ func (c *Column) getIntColumnRowCount(sc *stmtctx.StatementContext, intRanges []\n \t\t}\n \t\trowCount += cnt\n \t}\n-\tif rowCount > totalRowCount {\n-\t\trowCount = totalRowCount\n+\tif rowCount > c.totalRowCount() {\n+\t\trowCount = c.totalRowCount()\n \t}\n \treturn rowCount, nil\n }\n\n<|file_patch|>statistics/selectivity_test.go\ndiff --git a/statistics/selectivity_test.go b/statistics/selectivity_test.go\nindex 986a03e8f0a7ae58ea6b0dc284054270ddac462b..4f001ba51603d9689a06bc75eaa86aac8a297bb1 100644\n--- a/statistics/selectivity_test.go\n+++ b/statistics/selectivity_test.go\n@@ -190,6 +190,12 @@ func (s *testSelectivitySuite) TestSelectivity(c *C) {\n \t\tratio, err := statsTbl.Selectivity(ctx, p.Children()[0].(*plan.LogicalSelection).Conditions)\n \t\tc.Assert(err, IsNil, comment)\n \t\tc.Assert(math.Abs(ratio-tt.selectivity) < eps, IsTrue, Commentf(\"for %s, needed: %v, got: %v\", tt.exprs, tt.selectivity, ratio))\n+\n+\t\tstatsTbl.Count *= 10\n+\t\tratio, err = statsTbl.Selectivity(ctx, p.Children()[0].(*plan.LogicalSelection).Conditions)\n+\t\tc.Assert(err, IsNil, comment)\n+\t\tc.Assert(math.Abs(ratio-tt.selectivity) < eps, IsTrue, Commentf(\"for %s, needed: %v, got: %v\", tt.exprs, tt.selectivity, ratio))\n+\t\tstatsTbl.Count /= 10\n \t}\n }\n \n\n<|file_patch|>statistics/statistics_test.go\ndiff --git a/statistics/statistics_test.go b/statistics/statistics_test.go\nindex 078bbed0cffc0944c87af00f679d5d1a55b82b31..f838550b93feaf4622ce9e4d08e256b92c85c7d7 100644\n--- a/statistics/statistics_test.go\n+++ b/statistics/statistics_test.go\n@@ -589,6 +589,11 @@ func (s *testStatisticsSuite) TestIntColumnRanges(c *C) {\n \tcount, err = tbl.GetRowCountByIntColumnRanges(sc, 0, ran)\n \tc.Assert(err, IsNil)\n \tc.Assert(int(count), Equals, 1)\n+\n+\ttbl.Count *= 10\n+\tcount, err = tbl.GetRowCountByIntColumnRanges(sc, 0, ran)\n+\tc.Assert(err, IsNil)\n+\tc.Assert(int(count), Equals, 10)\n }\n \n func (s *testStatisticsSuite) TestIndexRanges(c *C) {\n\n<|file_patch|>statistics/table.go\ndiff --git a/statistics/table.go b/statistics/table.go\nindex 645fdd038931e7cd64da4e310e73cb2e95c3b949..4dc3850f42c22a8ce5b343cc6bd39710145b0d61 100644\n--- a/statistics/table.go\n+++ b/statistics/table.go\n@@ -307,7 +307,9 @@ func (t *Table) GetRowCountByIntColumnRanges(sc *stmtctx.StatementContext, colID\n \t\treturn getPseudoRowCountByIntRanges(intRanges, float64(t.Count)), nil\n \t}\n \tc := t.Columns[colID]\n-\treturn c.getIntColumnRowCount(sc, intRanges, float64(t.Count))\n+\tresult, err := c.getIntColumnRowCount(sc, intRanges)\n+\tresult *= c.getIncreaseFactor(t.Count)\n+\treturn result, errors.Trace(err)\n }\n \n // GetRowCountByColumnRanges estimates the row count by a slice of NewRange.\n@@ -316,7 +318,9 @@ func (t *Table) GetRowCountByColumnRanges(sc *stmtctx.StatementContext, colID in\n \t\treturn getPseudoRowCountByColumnRanges(sc, float64(t.Count), colRanges, 0)\n \t}\n \tc := t.Columns[colID]\n-\treturn c.getColumnRowCount(sc, colRanges)\n+\tresult, err := c.getColumnRowCount(sc, colRanges)\n+\tresult *= c.getIncreaseFactor(t.Count)\n+\treturn result, errors.Trace(err)\n }\n \n // GetRowCountByIndexRanges estimates the row count by a slice of NewRange.\n\n"},"target_character_start":{"kind":"number","value":96,"string":"96"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-07"},"utf8_bytes":{"kind":"number","value":5875,"string":"5,875"},"document_order_key":{"kind":"number","value":2943753167465780000,"string":"2,943,753,167,465,780,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/actiontech/tidb"},"quality_band":{"kind":"string","value":"07"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"go"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/actiontech/tidb\",\"commit_oid\":\"01f132ed39a8c1fc9775d963c7b0b50415f7d024\",\"commits_ago_from_head\":6173,\"content_sha256\":\"f49ac290b5d45eea435263212d0f3f15bf53a51eef89aa57ce06f303edf0a6bf\",\"manifest_sha256\":null,\"parent_oid\":\"f744c777de06cbc744cb19da17cdec5bd2b1ba86\",\"repository_id\":\"github.com/actiontech/tidb\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"07\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":7},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[\"#5552\"],\"message_words\":11,\"scope\":null,\"subject_length\":72,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":51,\"context_bytes\":76814,\"deleted_lines\":7,\"files_changed\":5,\"hunk_count\":7,\"patch_bytes\":5582,\"patch_sha256\":\"236991b11342e61a943db48c993f8fe36abc65a8c0e096a3adf0e7327b6841d7\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"go\",\"path\":\"plan/cbo_test.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"statistics/histogram.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"statistics/selectivity_test.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"statistics/statistics_test.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"statistics/table.go\",\"purpose\":\"source\"}],\"primary_language\":\"go\"},\"quality_band\":\"07\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":76814,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":5,\"files_kept\":5,\"patch_bytes\":5582},\"commit_oid\":\"01f132ed39a8c1fc9775d963c7b0b50415f7d024\",\"identity\":{\"author_email\":\"lambdax.tyler@gmail.com\",\"author_name\":\"Haibin Xie\",\"authored_at\":\"2018-01-04T14:31:25+08:00\",\"commit_oid\":\"01f132ed39a8c1fc9775d963c7b0b50415f7d024\",\"commits_ago_from_head\":6173,\"committed_at\":\"2018-01-04T14:31:25+08:00\",\"committer_email\":\"coocood@gmail.com\",\"committer_name\":\"Ewan Chou\",\"parent_oid\":\"f744c777de06cbc744cb19da17cdec5bd2b1ba86\",\"tree_oid\":\"9d7d986c152bcdd133c3a93ea263ec88667a7c29\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"c3c3063b66dc847673a842ef43a6cad2201d6f6d\",\"oldest_commit\":\"eba26bd705dea3a1ce836dbedd244a7763a4a484\"},\"recorded_head_commit\":\"c3c3063b66dc847673a842ef43a6cad2201d6f6d\",\"repository_id\":\"github.com/actiontech/tidb\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/actiontech/tidb\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":6287,\"manifest_sha256\":null,\"split\":\"15-of-16\"}},\"parents\":[\"commit:github.com/actiontech/tidb@01f132ed39a8c1fc9775d963c7b0b50415f7d024__download_changed_file_contents_a400db2096b0__render_commit_patches_63465f4d0183\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16041,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/jruby/jruby-openssl@c7cd35d0deccb005e623706b78ac935de8667bf1"},"text":{"kind":"string","value":"<|commit_message|>\nload correct openssl .rb files on Ruby 2.3\n<|file_patch|>lib/openssl/bn.rb\ndiff --git a/lib/openssl/bn.rb b/lib/openssl/bn.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/bn.rb\n+++ b/lib/openssl/bn.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/buffering.rb\ndiff --git a/lib/openssl/buffering.rb b/lib/openssl/buffering.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/buffering.rb\n+++ b/lib/openssl/buffering.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/cipher.rb\ndiff --git a/lib/openssl/cipher.rb b/lib/openssl/cipher.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/cipher.rb\n+++ b/lib/openssl/cipher.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/config.rb\ndiff --git a/lib/openssl/config.rb b/lib/openssl/config.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/config.rb\n+++ b/lib/openssl/config.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/digest.rb\ndiff --git a/lib/openssl/digest.rb b/lib/openssl/digest.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/digest.rb\n+++ b/lib/openssl/digest.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/pkcs7.rb\ndiff --git a/lib/openssl/pkcs7.rb b/lib/openssl/pkcs7.rb\nindex e162ce5eede129cfa6863196a92892d0d4a94219..500d89c510269e59ae5ff46329225395f85078f8 100644\n--- a/lib/openssl/pkcs7.rb\n+++ b/lib/openssl/pkcs7.rb\n@@ -1,9 +1,5 @@\n-if RUBY_VERSION > '2.2'\n- raise LoadError, \"no such library in 2.2: openssl/pkcs7\"\n-elsif RUBY_VERSION > '2.1'\n- raise LoadError, \"no such library in 2.1: openssl/pkcs7\"\n-elsif RUBY_VERSION > '1.9'\n- raise LoadError, \"no such library in 1.9: openssl/pkcs7\"\n+if RUBY_VERSION > '1.9'\n+ raise LoadError, \"no such library in #{RUBY_VERSION}: openssl/pkcs7\"\n else\n load \"jopenssl18/openssl/pkcs7.rb\"\n end\n\\ No newline at end of file\n\n<|file_patch|>lib/openssl/pkey.rb\ndiff --git a/lib/openssl/pkey.rb b/lib/openssl/pkey.rb\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..370bb9d61d2aba07d22d4662703e6a8c0496a4e3\n--- /dev/null\n+++ b/lib/openssl/pkey.rb\n@@ -0,0 +1,5 @@\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+else\n+ raise LoadError, \"no such file to load -- openssl/pkey\"\n+end\n\\ No newline at end of file\n\n<|file_patch|>lib/openssl/ssl-internal.rb\ndiff --git a/lib/openssl/ssl-internal.rb b/lib/openssl/ssl-internal.rb\nindex 77a8a3cc10ca825bae48e1eacc10da28a08cff26..8a82ab37299bcf27ab6db79927dee450caa98484 100644\n--- a/lib/openssl/ssl-internal.rb\n+++ b/lib/openssl/ssl-internal.rb\n@@ -1,7 +1,5 @@\n-if RUBY_VERSION > '2.2'\n- raise LoadError, \"no such library in 2.2: openssl/ssl-internal.rb\"\n-elsif RUBY_VERSION > '2.1'\n- raise LoadError, \"no such library in 2.1: openssl/ssl-internal.rb\"\n+if RUBY_VERSION > '2.1'\n+ raise LoadError, \"no such library in #{RUBY_VERSION}: openssl/ssl-internal.rb\"\n elsif RUBY_VERSION > '1.9'\n load \"jopenssl19/openssl/#{File.basename(__FILE__)}\"\n else\n\n<|file_patch|>lib/openssl/ssl.rb\ndiff --git a/lib/openssl/ssl.rb b/lib/openssl/ssl.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/ssl.rb\n+++ b/lib/openssl/ssl.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load \"jopenssl21/openssl/#{File.basename(__FILE__)}\"\n\n<|file_patch|>lib/openssl/x509-internal.rb\ndiff --git a/lib/openssl/x509-internal.rb b/lib/openssl/x509-internal.rb\nindex 034f94ff18d43b4b5aafdd682b2fd169908850ef..659d526dc54179d1a43ce20b6f9b8269a1e1d0f9 100644\n--- a/lib/openssl/x509-internal.rb\n+++ b/lib/openssl/x509-internal.rb\n@@ -1,7 +1,5 @@\n-if RUBY_VERSION > '2.2'\n- raise LoadError, \"no such library in 2.2: openssl/x509-internal.rb\"\n-elsif RUBY_VERSION > '2.1'\n- raise LoadError, \"no such library in 2.1: openssl/x509-internal.rb\"\n+if RUBY_VERSION > '2.1'\n+ raise LoadError, \"no such library in #{RUBY_VERSION}: openssl/x509-internal.rb\"\n elsif RUBY_VERSION > '1.9'\n load \"jopenssl19/openssl/#{File.basename(__FILE__)}\"\n else\n\n<|file_patch|>lib/openssl/x509.rb\ndiff --git a/lib/openssl/x509.rb b/lib/openssl/x509.rb\nindex 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644\n--- a/lib/openssl/x509.rb\n+++ b/lib/openssl/x509.rb\n@@ -1,4 +1,6 @@\n-if RUBY_VERSION > '2.2'\n+if RUBY_VERSION > '2.3'\n+ load \"jopenssl23/openssl/#{File.basename(__FILE__)}\"\n+elsif RUBY_VERSION > '2.2'\n load \"jopenssl22/openssl/#{File.basename(__FILE__)}\"\n elsif RUBY_VERSION > '2.1'\n load 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documentation\n\n<|file_patch|>modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java\ndiff --git a/modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java b/modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java\nindex 3bdbb4785b95d460aa39ff84ce5121026729c0af..f8ceb698e6c8eab0601967237f0126ec864fd0ff 100644\n--- a/modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java\n+++ b/modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java\n@@ -93,6 +93,10 @@ public class ActivitiEngineConfiguration {\n \tprocessEngineConfiguration.setTransactionManager(annotationDrivenTransactionManager());\n \tprocessEngineConfiguration.setJobExecutorActivate(Boolean.valueOf(\n \t environment.getProperty(\"engine.activate.jobexecutor\", \"false\")));\n+ \tprocessEngineConfiguration.setAsyncExecutorEnabled(Boolean.valueOf(\n+ environment.getProperty(\"engine.asyncexecutor.enabled\", \"true\")));\n+ \tprocessEngineConfiguration.setAsyncExecutorActivate(Boolean.valueOf(\n+ environment.getProperty(\"engine.asyncexecutor.activate\", \"true\")));\n \tprocessEngineConfiguration.setHistory(environment.getProperty(\"engine.history.level\", \"full\"));\n \t\n \tList<AbstractFormType> formTypes = new ArrayList<AbstractFormType>();\n\n<|file_patch|>modules/activiti-webapp-explorer2/src/main/resources/engine.properties\ndiff --git a/modules/activiti-webapp-explorer2/src/main/resources/engine.properties b/modules/activiti-webapp-explorer2/src/main/resources/engine.properties\nindex 94348614aa3842134ac4bcb461175b9d976fe7b0..b772593e7880b563e432fc1c0ca8d1f47ba4366b 100644\n--- a/modules/activiti-webapp-explorer2/src/main/resources/engine.properties\n+++ b/modules/activiti-webapp-explorer2/src/main/resources/engine.properties\n@@ -7,4 +7,6 @@ create.demo.reports=true\n # engine properties\n engine.schema.update=true\n engine.activate.jobexecutor=false\n+engine.asyncexecutor.enabled=true\n+engine.asyncexecutor.activate=true\n engine.history.level=full\n\\ No newline at end of file\n\n<|file_patch|>modules/activiti-webapp-rest2/src/main/java/org/activiti/rest/conf/ActivitiEngineConfiguration.java\ndiff --git a/modules/activiti-webapp-rest2/src/main/java/org/activiti/rest/conf/ActivitiEngineConfiguration.java b/modules/activiti-webapp-rest2/src/main/java/org/activiti/rest/conf/ActivitiEngineConfiguration.java\nindex 4a3f7d357d1659cd12d90d601510c2b1bc8f0d0a..1dd111a5f61a5cf5bdd02ed4ae3794ce917fd4b5 100644\n--- a/modules/activiti-webapp-rest2/src/main/java/org/activiti/rest/conf/ActivitiEngineConfiguration.java\n+++ b/modules/activiti-webapp-rest2/src/main/java/org/activiti/rest/conf/ActivitiEngineConfiguration.java\n@@ -93,6 +93,10 @@ public class ActivitiEngineConfiguration {\n \tprocessEngineConfiguration.setTransactionManager(annotationDrivenTransactionManager());\n \tprocessEngineConfiguration.setJobExecutorActivate(Boolean.valueOf(\n \t environment.getProperty(\"engine.activate.jobexecutor\", \"false\")));\n+ \tprocessEngineConfiguration.setAsyncExecutorEnabled(Boolean.valueOf(\n+ environment.getProperty(\"engine.asyncexecutor.enabled\", \"true\")));\n+ processEngineConfiguration.setAsyncExecutorActivate(Boolean.valueOf(\n+ environment.getProperty(\"engine.asyncexecutor.activate\", \"true\")));\n \tprocessEngineConfiguration.setHistory(environment.getProperty(\"engine.history.level\", \"full\"));\n \t\n \tList<AbstractFormType> formTypes = new ArrayList<AbstractFormType>();\n\n<|file_patch|>modules/activiti-webapp-rest2/src/main/resources/engine.properties\ndiff --git a/modules/activiti-webapp-rest2/src/main/resources/engine.properties b/modules/activiti-webapp-rest2/src/main/resources/engine.properties\nindex 95fec55cbedc16563460417c9aeb5df7a39ecb86..199f49c77d612bd6ad7dfbda321ab875e419d56c 100644\n--- a/modules/activiti-webapp-rest2/src/main/resources/engine.properties\n+++ b/modules/activiti-webapp-rest2/src/main/resources/engine.properties\n@@ -6,4 +6,6 @@ create.demo.models=true\n # engine properties\n engine.schema.update=true\n engine.activate.jobexecutor=false\n+engine.asyncexecutor.enabled=true\n+engine.asyncexecutor.activate=true\n engine.history.level=full\n\\ No newline at end of file\n\n<|file_patch|>userguide/src/en/ch01-Introduction.adoc\ndiff --git a/userguide/src/en/ch01-Introduction.adoc b/userguide/src/en/ch01-Introduction.adoc\nindex 9302a33aa100f6f8ac5a5593205562d31f26777c..ed5f10e4e1728ffb0e2b94bce0e1a3e484012189 100644\n--- a/userguide/src/en/ch01-Introduction.adoc\n+++ b/userguide/src/en/ch01-Introduction.adoc\n@@ -5,7 +5,8 @@\n \n === License\n \n-Activiti is distributed under link:$$http://www.apache.org/licenses/LICENSE-2.0.html$$[the Apache V2 license].\n+Activiti is distributed under link:$$http://www.apache.org/licenses/LICENSE-2.0.html$$[the Apache V2 license]. \n+The Activiti Modeler uses a different license link:$$http://opensource.org/licenses/LGPL-2.1$$[the LGPL 2.1 license].\n \n [[download]]\n \n\n<|file_patch|>userguide/src/en/ch12-Explorer.adoc\ndiff --git a/userguide/src/en/ch12-Explorer.adoc b/userguide/src/en/ch12-Explorer.adoc\nindex 855a098b5529554f62c44d983199e0798d615c6b..e75cfa056e7308b8e71890def5614a2f03dbb90a 100644\n--- a/userguide/src/en/ch12-Explorer.adoc\n+++ b/userguide/src/en/ch12-Explorer.adoc\n@@ -13,6 +13,12 @@ image::images/explorer.tabs.png[align=\"center\"]\n * *Reporting*: generate reports and view previously saved results. See <<explorer.reporting,the section on reporting>> for more details.\n * *Manage*: only visible when the logged in user has administrator rights. Allows to administrate the Activiti engine: manage users and groups, execute and see stuck jobs, see the database and deploy new process definitions. \n \n+=== Configuration\n+\n+The Activiti Explorer is using Spring Java Configuration for starting the Activiti Engine. A small amount of properties can be defined by changing the engine.properties file you can find in the WEB-INF/classes folder.\n+If you need more advanced configuration options there's the possibility to define the Activiti process engine configuration in XML in the activiti-custom-context.xml file you can also find in the WEB-INF/classes folder.\n+An example configuration is already in comments in this file.\n+\n === Process diagram\n \n The Explorer includes functionality to dynamically generate an overview of a process definition using the link:$$http://raphaeljs.com/$$[Raphaël] JavaScript framework. This process image can only be generated when the process definition XML contains BPMN DI information. When there's no BPMN DI information in the process definition XML and the deployment contains a process definition image, that image will be shown.\n\n<|file_patch|>userguide/src/en/ch13-Modeler.adoc\ndiff --git a/userguide/src/en/ch13-Modeler.adoc b/userguide/src/en/ch13-Modeler.adoc\nindex 667ba3fc2e302fd0a750b7e70cb582cb44831f10..6545afe62744c484e31c476d5c003f54c7b626bd 100644\n--- a/userguide/src/en/ch13-Modeler.adoc\n+++ b/userguide/src/en/ch13-Modeler.adoc\n@@ -2,7 +2,11 @@\n \n == Activiti Modeler\n \n-Activiti Modeler is a BPMN web modeler component that's available as part of the <<activitiExplorer,Activiti Explorer>> web application. The Modeler is a fork of the link:$$http://code.google.com/p/signavio-core-components/$$[Signavio Core Components] project. A main difference with the previous Activiti Modeler (Signavio Core Components) is that that the new modeler is maintained and developed as part of the Activiti project. The goal of the Activiti Modeler is to support all the BPMN elements and extension supported by the Activiti Engine.\n+Activiti Modeler is a BPMN web modeler component that's available as part of the <<activitiExplorer,Activiti Explorer>> web application. \n+The Modeler is a fork of the link:$$http://code.google.com/p/signavio-core-components/$$[Signavio Core Components] project. \n+The Activiti Modeler is an Angular JS based application since version 5.17.0 (before it was an Ext-JS based application). The Angular JS part of the Activiti Modeler is released with a LGPL license.\n+A main difference with the previous Activiti Modeler (Signavio Core Components) is that that the new modeler is maintained and developed as part of the Activiti project. \n+The goal of the Activiti Modeler is to support all the BPMN elements and extension supported by the Activiti Engine.\n \n When you run the Activiti Explorer with the default configuration one demo process will be available in the model workspace.\n \n@@ -11,7 +15,8 @@ image::images/modeler.example.process.png[align=\"center\"]\n \n === Model editing\n \n-When you click on the edit button in the model workspace the model will be opened in the modeler. On the left side of the screen the available palette of BPMN elements and Activiti extensions is available. You can drag and drop new elements on the canvas when needed. On the right side of the screen the attributes of a selected element can be filled-in. In the example screenshot a user task is selected and you can fill-in user task attributes like assignment, form properties and due date. To return to the Activiti Explorer you can click the close button at the top right of the screen.\n+When you click on the edit button in the model workspace the model will be opened in the modeler. On the left side of the screen the available palette of BPMN elements and Activiti extensions is available. You can drag and drop new elements on the canvas when needed. On the bottom side of the screen the attributes of a selected element can be filled-in. In the example screenshot a user task is selected and you can fill-in user task attributes like assignment, form properties and due date. \n+To return to the Activiti Explorer you can click the close button at the top right of the screen.\n \n image::images/modeler.editor.canvas.png[align=\"center\"]\n \n\n<|file_patch|>userguide/src/en/ch17-Advanced.adoc\ndiff --git a/userguide/src/en/ch17-Advanced.adoc b/userguide/src/en/ch17-Advanced.adoc\nindex a81db6cfb2e5ac9f40c49ed5050e521d8c7a2979..62e90a9cc3829932eeb65a175888942637f21588 100644\n--- a/userguide/src/en/ch17-Advanced.adoc\n+++ b/userguide/src/en/ch17-Advanced.adoc\n@@ -5,6 +5,80 @@ The following sections cover advanced use cases of using Activiti, that go beyon\n \t\n [[advanced_parseHandlers]]\n \n+=== Async and job executor\n+\n+Starting from version 5.17.0 Activiti provides the Async executor in addition to the existing job executor. Both executors deal with timers and asynchronous jobs in the Activiti Engine, so only one executor can be enabled.\n+This section will explain the difference between the Async executor and the job executor and why we recommend to use the Async executor. Note that by default Activiti uses the existing job executor because we don't want to enable the Async executor without making an explicit configuration for it.\n+\n+==== Async executor design\n+\n+The Async executor contains a thread pool to execute timer and asynchronous jobs. When enabled, the Engine will call the Async executor with a persisted asynchronous job entity and the thread pool will asynchronously execute the job.\n+This is major difference with the old Job executor, because in that case the asynchronous job is persisted and the job executor will poll the database for new jobs.\n+In case a job is found it will lock the job and execute it, which means a lot of additional database traffic. The Async executor will execute the asynchronous job directly without first polling the database.\n+In case the asynchronous job is an exclusive job, the Async executor will first lock the process instance execution and if that succeeds execute the job and unlock the process instance execution again.\n+If the process instance lock fails, it will retry.\n+\n+In the case of timer jobs the logic is different from asynchronous jobs and the implementation is similar between the Async and the Job executor.\n+The Async executor will poll the database for timer jobs which are due to be executed. The job will then be locked and executed.\n+\n+==== Job executor design\n+\n+The job executor also contains a thread pool to execute timer and asynchronous jobs. When activated, the Job executor will poll the database for asynchronous jobs and timer jobs due.\n+In case a job is found it will lock the job and execute it, which means a lot of additional database traffic. On the other side, the Async executor will execute the asynchronous job directly without first polling the database.\n+\n+==== Advantages of the Async executor\n+\n+* Less database queries because asynchronous jobs are executed without polling the database\n+* For non-exclusive jobs there's no chance to run into OptimisticLockingExeptions anymore\n+* Exclusive jobs are now locked at process instance level instead of the cumbersome logic of queuing exclusive jobs in the Job Executor\n+\n+==== Async executor configuration\n+\n+It's possible to define thread pool sizes and other configurations for the Async executor.\n+It's always advised to look into the default settings of the Async executor and validate if they match the requirements of your process instances.\n+\n+To override the default settings of the job executor a new bean needs to be injected into the process engine configuration, like:\n+\n+[source,xml,linenums]\n+----\n+<property name=\"asyncExecutor\" ref=\"asyncExecutor\" />\n+----\n+\n+The default Async executor can be used to override the default settings, but you can of course also extend from the DefaultAsyncJobExecutor class. \n+In the following configuration listing, the DefaultAsyncJobExecutor is used with new values for its properties:\n+\n+[source,xml,linenums]\n+----\n+<bean id=\"asyncExecutor\" class=\"org.activiti.engine.impl.asyncexecutor.DefaultAsyncJobExecutor\">\n+ <property name=\"corePoolSize\" value=\"10\" /> \n+ <property name=\"maxPoolSize\" value=\"50\" />\n+ <property name=\"keepAliveTime\" value=\"3000\" />\n+ <property name=\"queueSize\" value=\"200\" />\n+ <property name=\"maxTimerJobsPerAcquisition\" value=\"2\" />\n+ <property name=\"maxAsyncJobsDuePerAcquisition\" value=\"2\" />\n+ <property name=\"defaultAsyncJobAcquireWaitTimeInMillis\" value=\"1000\" />\n+ <property name=\"defaultTimerJobAcquireWaitTimeInMillis\" value=\"1000\" />\n+ <property name=\"timerLockTimeInMillis\" value=\"60000\" />\n+ <property name=\"asyncJobLockTimeInMillis\" value=\"60000\" />\n+</bean>\n+----\n+\n+.Async executor configuration options\n+[options=\"header\"]\n+|===============\n+|Name|Default value|Description\n+|corePoolSize|2|The minimal number of threads that are kept alive in the thread pool for job execution.\n+|maxPoolSize|10|The maximum number of threads that are kept alive in the thread pool for job execution.\n+|keepAliveTime|5000|The time (in milliseconds) a thread used for job execution must be kept alive before it is destroyed. Default setting is 0. Having a non-default setting of 0 takes resources, but in the case of many job executions it avoids creating new threads all the time.\n+|queueSize|100|The size of the queue on which jobs to be executed are placed.\n+|maxTimerJobsPerAcquisition|1|The number of timer jobs that are fetched from the database in one query.\n+|maxAsyncJobsDuePerAcquisition|1|The number of asynchronous jobs due that are fetched from the database in one query.\n+|defaultAsyncJobAcquireWaitTimeInMillis|10000|The time in milliseconds between asynchronous job due queries being executed.\n+|defaultTimerJobAcquireWaitTimeInMillis|10000|The time in milliseconds between timer job queries being executed.\n+|timerLockTimeInMillis|300000|The time in milliseconds that a timer job is locked before being retried again. The Activiti Engine considers the timer job to have failed after this period of time and will retry.\n+|asyncJobLockTimeInMillis|300000|The time in milliseconds that an asynchronous job is locked before being retried again. The Activiti Engine considers the asynchronous job to have failed after this period of time and will retry.\n+\n+|===============\n \n === Hooking into process parsing\n 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conformance tests for tracers (#191)\n\n* Provide conformance tests for tracers\r\n\r\nThe test harness may be used to ensure that a given tracer behaves\r\naccording to the expectations set by the API.\r\n\r\n* Add `ToMatchError` matcher\r\n\r\n* Use DeepEqual to compare unknown types in matchers\r\n\r\nUnlike basic `==`/`!=`, `reflect.DeepEqual` can compare arbitrary\r\ntypes (e.g., `[]string` to `[]string`)\r\n\r\n* Use struct instead of string for test context key\r\n\n<|file_patch|>api/testharness/harness.go\ndiff --git a/api/testharness/harness.go b/api/testharness/harness.go\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4af4123a7247e1d6dac5a18a3568649f3fea0f1d\n--- /dev/null\n+++ b/api/testharness/harness.go\n@@ -0,0 +1,290 @@\n+// Copyright 2019, OpenTelemetry Authors\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+// http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+package testharness\n+\n+import (\n+\t\"context\"\n+\t\"errors\"\n+\t\"testing\"\n+\n+\t\"go.opentelemetry.io/api/core\"\n+\t\"go.opentelemetry.io/api/trace\"\n+\t\"go.opentelemetry.io/internal/matchers\"\n+)\n+\n+type Harness struct {\n+\tt *testing.T\n+}\n+\n+func NewHarness(t *testing.T) *Harness {\n+\treturn &Harness{\n+\t\tt: t,\n+\t}\n+}\n+\n+func (h *Harness) TestTracer(subjectFactory func() trace.Tracer) {\n+\th.t.Run(\"#Start\", func(t *testing.T) {\n+\t\tt.Run(\"propagates the original context\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tctxKey := testCtxKey{}\n+\t\t\tctxValue := \"ctx value\"\n+\t\t\tctx := context.WithValue(context.Background(), ctxKey, ctxValue)\n+\n+\t\t\tctx, _ = subject.Start(ctx, \"test\")\n+\n+\t\t\te.Expect(ctx.Value(ctxKey)).ToEqual(ctxValue)\n+\t\t})\n+\n+\t\tt.Run(\"returns a span containing the expected properties\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\t_, span := subject.Start(context.Background(), \"test\")\n+\n+\t\t\te.Expect(span).NotToBeNil()\n+\n+\t\t\te.Expect(span.Tracer()).ToEqual(subject)\n+\t\t\te.Expect(span.SpanContext().IsValid()).ToBeTrue()\n+\t\t})\n+\n+\t\tt.Run(\"stores the span on the provided context\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tctx, span := subject.Start(context.Background(), \"test\")\n+\n+\t\t\te.Expect(span).NotToBeNil()\n+\t\t\te.Expect(span.SpanContext()).NotToEqual(core.EmptySpanContext())\n+\t\t\te.Expect(trace.CurrentSpan(ctx)).ToEqual(span)\n+\t\t})\n+\n+\t\tt.Run(\"starts spans with unique trace and span IDs\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\t_, span1 := subject.Start(context.Background(), \"span1\")\n+\t\t\t_, span2 := subject.Start(context.Background(), \"span2\")\n+\n+\t\t\tsc1 := span1.SpanContext()\n+\t\t\tsc2 := span2.SpanContext()\n+\n+\t\t\te.Expect(sc1.TraceID).NotToEqual(sc2.TraceID)\n+\t\t\te.Expect(sc1.SpanID).NotToEqual(sc2.SpanID)\n+\t\t})\n+\n+\t\tt.Run(\"records the span if specified\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\t_, span := subject.Start(context.Background(), \"span\", trace.WithRecord())\n+\n+\t\t\te.Expect(span.IsRecording()).ToBeTrue()\n+\t\t})\n+\n+\t\tt.Run(\"propagates a parent's trace ID through the context\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tctx, parent := subject.Start(context.Background(), \"parent\")\n+\t\t\t_, child := subject.Start(ctx, \"child\")\n+\n+\t\t\tpsc := parent.SpanContext()\n+\t\t\tcsc := child.SpanContext()\n+\n+\t\t\te.Expect(csc.TraceID).ToEqual(psc.TraceID)\n+\t\t\te.Expect(csc.SpanID).NotToEqual(psc.SpanID)\n+\t\t})\n+\n+\t\tt.Run(\"propagates a parent's trace ID through `ChildOf`\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\t_, parent := subject.Start(context.Background(), \"parent\")\n+\t\t\t_, child := subject.Start(context.Background(), \"child\", trace.ChildOf(parent.SpanContext()))\n+\n+\t\t\tpsc := parent.SpanContext()\n+\t\t\tcsc := child.SpanContext()\n+\n+\t\t\te.Expect(csc.TraceID).ToEqual(psc.TraceID)\n+\t\t\te.Expect(csc.SpanID).NotToEqual(psc.SpanID)\n+\t\t})\n+\n+\t\tt.Run(\"propagates a parent's trace ID through `FollowsFrom`\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\t_, parent := subject.Start(context.Background(), \"parent\")\n+\t\t\t_, child := subject.Start(context.Background(), \"child\", trace.FollowsFrom(parent.SpanContext()))\n+\n+\t\t\tpsc := parent.SpanContext()\n+\t\t\tcsc := child.SpanContext()\n+\n+\t\t\te.Expect(csc.TraceID).ToEqual(psc.TraceID)\n+\t\t\te.Expect(csc.SpanID).NotToEqual(psc.SpanID)\n+\t\t})\n+\t})\n+\n+\th.t.Run(\"#WithSpan\", func(t *testing.T) {\n+\t\tt.Run(\"returns nil if the body does not return an error\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\terr := subject.WithSpan(context.Background(), \"test\", func(ctx context.Context) error {\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\t\t})\n+\n+\t\tt.Run(\"propagates the error from the body if the body errors\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\texpectedErr := errors.New(\"test error\")\n+\n+\t\t\terr := subject.WithSpan(context.Background(), \"test\", func(ctx context.Context) error {\n+\t\t\t\treturn expectedErr\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToMatchError(expectedErr)\n+\t\t})\n+\n+\t\tt.Run(\"propagates the original context to the body\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tctxKey := testCtxKey{}\n+\t\t\tctxValue := \"ctx value\"\n+\t\t\tctx := context.WithValue(context.Background(), ctxKey, ctxValue)\n+\n+\t\t\tvar actualCtx context.Context\n+\n+\t\t\terr := subject.WithSpan(ctx, \"test\", func(ctx context.Context) error {\n+\t\t\t\tactualCtx = ctx\n+\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\n+\t\t\te.Expect(actualCtx.Value(ctxKey)).ToEqual(ctxValue)\n+\t\t})\n+\n+\t\tt.Run(\"stores a span containing the expected properties on the context provided to the body function\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tvar span trace.Span\n+\n+\t\t\terr := subject.WithSpan(context.Background(), \"test\", func(ctx context.Context) error {\n+\t\t\t\tspan = trace.CurrentSpan(ctx)\n+\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\n+\t\t\te.Expect(span).NotToBeNil()\n+\n+\t\t\te.Expect(span.Tracer()).ToEqual(subject)\n+\t\t\te.Expect(span.SpanContext().IsValid()).ToBeTrue()\n+\t\t})\n+\n+\t\tt.Run(\"starts spans with unique trace and span IDs\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tvar span1 trace.Span\n+\t\t\tvar span2 trace.Span\n+\n+\t\t\terr := subject.WithSpan(context.Background(), \"span1\", func(ctx context.Context) error {\n+\t\t\t\tspan1 = trace.CurrentSpan(ctx)\n+\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\n+\t\t\terr = subject.WithSpan(context.Background(), \"span2\", func(ctx context.Context) error {\n+\t\t\t\tspan2 = trace.CurrentSpan(ctx)\n+\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\n+\t\t\tsc1 := span1.SpanContext()\n+\t\t\tsc2 := span2.SpanContext()\n+\n+\t\t\te.Expect(sc1.TraceID).NotToEqual(sc2.TraceID)\n+\t\t\te.Expect(sc1.SpanID).NotToEqual(sc2.SpanID)\n+\t\t})\n+\n+\t\tt.Run(\"propagates a parent's trace ID through the context\", func(t *testing.T) {\n+\t\t\tt.Parallel()\n+\n+\t\t\te := matchers.NewExpecter(t)\n+\t\t\tsubject := subjectFactory()\n+\n+\t\t\tctx, parent := subject.Start(context.Background(), \"parent\")\n+\n+\t\t\tvar child trace.Span\n+\n+\t\t\terr := subject.WithSpan(ctx, \"child\", func(ctx context.Context) error {\n+\t\t\t\tchild = trace.CurrentSpan(ctx)\n+\n+\t\t\t\treturn nil\n+\t\t\t})\n+\n+\t\t\te.Expect(err).ToBeNil()\n+\n+\t\t\tpsc := parent.SpanContext()\n+\t\t\tcsc := child.SpanContext()\n+\n+\t\t\te.Expect(csc.TraceID).ToEqual(psc.TraceID)\n+\t\t\te.Expect(csc.SpanID).NotToEqual(psc.SpanID)\n+\t\t})\n+\t})\n+}\n+\n+type testCtxKey struct{}\n\n<|file_patch|>api/testharness/package.go\ndiff --git a/api/testharness/package.go b/api/testharness/package.go\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..37cdeae55a9f7d504b9a0db93792b95fc6f989ce\n--- /dev/null\n+++ b/api/testharness/package.go\n@@ -0,0 +1,15 @@\n+// Copyright 2019, OpenTelemetry Authors\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+// http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+package testharness // import \"go.opentelemetry.io/api/testharness\"\n\n<|file_patch|>internal/matchers/expectation.go\ndiff --git a/internal/matchers/expectation.go b/internal/matchers/expectation.go\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2a8cf211db9d975ffe1d29cee8d4936e1ae3e9b2\n--- /dev/null\n+++ b/internal/matchers/expectation.go\n@@ -0,0 +1,114 @@\n+// Copyright 2019, OpenTelemetry Authors\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+// http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+package matchers\n+\n+import (\n+\t\"reflect\"\n+\t\"testing\"\n+)\n+\n+type Expectation struct {\n+\tt *testing.T\n+\tactual interface{}\n+}\n+\n+func (e *Expectation) ToEqual(expected interface{}) {\n+\te.verifyExpectedNotNil(expected)\n+\n+\tif !reflect.DeepEqual(e.actual, expected) {\n+\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto equal\\n\\t%v\\n\", e.actual, expected)\n+\t}\n+}\n+\n+func (e *Expectation) NotToEqual(expected interface{}) {\n+\te.verifyExpectedNotNil(expected)\n+\n+\tif reflect.DeepEqual(e.actual, expected) {\n+\t\te.t.Fatalf(\"Expected\\n\\t%v\\nnot to equal\\n\\t%v\\n\", e.actual, expected)\n+\t}\n+}\n+\n+func (e *Expectation) ToBeNil() {\n+\tif e.actual != nil {\n+\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto be nil\\n\", e.actual)\n+\t}\n+}\n+\n+func (e *Expectation) NotToBeNil() {\n+\tif e.actual == nil {\n+\t\te.t.Fatalf(\"Expected\\n\\t%v\\nnot to be nil\\n\", e.actual)\n+\t}\n+}\n+\n+func (e *Expectation) ToBeTrue() {\n+\tswitch a := e.actual.(type) {\n+\tcase bool:\n+\t\tif e.actual == false {\n+\t\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto be true\\n\", e.actual)\n+\t\t}\n+\tdefault:\n+\t\te.t.Fatalf(\"Cannot check if non-bool value\\n\\t%v\\nis truthy\\n\", a)\n+\t}\n+}\n+\n+func (e *Expectation) ToBeFalse() {\n+\tswitch a := e.actual.(type) {\n+\tcase bool:\n+\t\tif e.actual == true {\n+\t\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto be false\\n\", e.actual)\n+\t\t}\n+\tdefault:\n+\t\te.t.Fatalf(\"Cannot check if non-bool value\\n\\t%v\\nis truthy\\n\", a)\n+\t}\n+}\n+\n+func (e *Expectation) ToSucceed() {\n+\tswitch actual := e.actual.(type) {\n+\tcase error:\n+\t\tif actual != nil {\n+\t\t\te.t.Fatalf(\"Expected error\\n\\t%v\\nto have succeeded\\n\", actual)\n+\t\t}\n+\tdefault:\n+\t\te.t.Fatalf(\"Cannot check if non-error value\\n\\t%v\\nsucceeded\\n\", actual)\n+\t}\n+}\n+\n+func (e *Expectation) ToMatchError(expected interface{}) {\n+\te.verifyExpectedNotNil(expected)\n+\n+\tactual, ok := e.actual.(error)\n+\tif !ok {\n+\t\te.t.Fatalf(\"Cannot check if non-error value\\n\\t%v\\nmatches error\\n\", e.actual)\n+\t}\n+\n+\tswitch expected := expected.(type) {\n+\tcase error:\n+\t\tif !reflect.DeepEqual(actual, expected) {\n+\t\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto match error\\n\\t%v\\n\", actual, expected)\n+\t\t}\n+\tcase string:\n+\t\tif actual.Error() != expected {\n+\t\t\te.t.Fatalf(\"Expected\\n\\t%v\\nto match error\\n\\t%v\\n\", actual, expected)\n+\t\t}\n+\tdefault:\n+\t\te.t.Fatalf(\"Cannot match\\n\\t%v\\nagainst non-error\\n\\t%v\\n\", actual, expected)\n+\t}\n+}\n+\n+func (e *Expectation) verifyExpectedNotNil(expected interface{}) {\n+\tif expected == nil {\n+\t\te.t.Fatal(\"Refusing to compare with <nil>. Use `ToBeNil` or `NotToBeNil` instead.\")\n+\t}\n+}\n\n<|file_patch|>internal/matchers/expecter.go\ndiff --git a/internal/matchers/expecter.go b/internal/matchers/expecter.go\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..f4df75b6a36bde2613f300adf849d49ff08b2be4\n--- /dev/null\n+++ b/internal/matchers/expecter.go\n@@ -0,0 +1,36 @@\n+// Copyright 2019, OpenTelemetry Authors\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+// http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+package matchers\n+\n+import (\n+\t\"testing\"\n+)\n+\n+type Expecter struct {\n+\tt *testing.T\n+}\n+\n+func NewExpecter(t *testing.T) *Expecter {\n+\treturn &Expecter{\n+\t\tt: t,\n+\t}\n+}\n+\n+func (a *Expecter) Expect(actual interface{}) *Expectation {\n+\treturn &Expectation{\n+\t\tt: a.t,\n+\t\tactual: actual,\n+\t}\n+}\n\n<|file_patch|>internal/matchers/package.go\ndiff --git a/internal/matchers/package.go b/internal/matchers/package.go\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..57eeac75f48f4b286d28b11a226ed04a08d39cb7\n--- /dev/null\n+++ b/internal/matchers/package.go\n@@ -0,0 +1,15 @@\n+// Copyright 2019, OpenTelemetry Authors\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+// http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+package matchers // import \"go.opentelemetry.io/internal/matchers\"\n\n<|file_patch|>sdk/trace/trace_test.go\ndiff --git a/sdk/trace/trace_test.go b/sdk/trace/trace_test.go\nindex 3c25122510029f9ac985d32f684ed24eb07af591..c9e88d27e8d1b96cfabcf54a853ababff81d3648 100644\n--- a/sdk/trace/trace_test.go\n+++ b/sdk/trace/trace_test.go\n@@ -27,6 +27,8 @@ import (\n \n \t\"go.opentelemetry.io/api/core\"\n \t\"go.opentelemetry.io/api/key\"\n+\t\"go.opentelemetry.io/api/testharness\"\n+\t\"go.opentelemetry.io/api/trace\"\n \tapitrace \"go.opentelemetry.io/api/trace\"\n \t\"go.opentelemetry.io/sdk/export\"\n )\n@@ -41,6 +43,15 @@ func init() {\n \tsetupDefaultSamplerConfig()\n }\n \n+func TestTracerFollowsExpectedAPIBehaviour(t *testing.T) {\n+\tharness := testharness.NewHarness(t)\n+\tsubjectFactory := func() trace.Tracer {\n+\t\treturn apitrace.GlobalTracer()\n+\t}\n+\n+\tharness.TestTracer(subjectFactory)\n+}\n+\n func setupDefaultSamplerConfig() {\n \t// no random sampling, but sample children of sampled spans.\n \tApplyConfig(Config{DefaultSampler: ProbabilitySampler(0)})\n@@ -54,14 +65,6 @@ func (t *testExporter) ExportSpan(ctx context.Context, d *export.SpanData) {\n \tt.spans = append(t.spans, d)\n }\n \n-func TestStartSpan(t *testing.T) {\n-\t_, span := apitrace.GlobalTracer().Start(context.Background(), \"StartSpan\")\n-\tdefer span.End()\n-\tif span == nil {\n-\t\tt.Errorf(\"span not started\")\n-\t}\n-}\n-\n func TestSetName(t *testing.T) {\n \tsamplerIsCalled := false\n \tfooSampler := Sampler(func(p SamplingParameters) SamplingDecision {\n\n"},"target_character_start":{"kind":"number","value":476,"string":"476"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":16314,"string":"16,314"},"document_order_key":{"kind":"number","value":2944133273935530500,"string":"2,944,133,273,935,530,500"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/open-telemetry/opentelemetry-go"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":4,"string":"4"},"primary_language":{"kind":"string","value":"go"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/open-telemetry/opentelemetry-go\",\"commit_oid\":\"3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c\",\"commits_ago_from_head\":4831,\"content_sha256\":\"0490a81dfa7750e7c5d0155754b06261a5f34c2f138233716cc48efc3c2f9243\",\"manifest_sha256\":null,\"parent_oid\":\"11bdacf7b9201e6dd878f0bd902c9d4e7fdb94ec\",\"repository_id\":\"github.com/open-telemetry/opentelemetry-go\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":4,\"deductions\":[],\"repo_score\":4,\"repo_score_components\":{\"dependents_reach\":4,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#191\"],\"message_words\":68,\"scope\":null,\"subject_length\":44,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":481,\"context_bytes\":22191,\"deleted_lines\":8,\"files_changed\":6,\"hunk_count\":8,\"patch_bytes\":15578,\"patch_sha256\":\"772b11632f7e62541c29fa4d6751b57376de905c1b7c7225c5d86d0b5114733d\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"go\",\"path\":\"api/testharness/harness.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"api/testharness/package.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"internal/matchers/expectation.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"internal/matchers/expecter.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"internal/matchers/package.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"sdk/trace/trace_test.go\",\"purpose\":\"source\"}],\"primary_language\":\"go\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":22191,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":6,\"files_kept\":6,\"patch_bytes\":15578},\"commit_oid\":\"3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c\",\"identity\":{\"author_email\":\"iredelmeier@gmail.com\",\"author_name\":\"Isobel Redelmeier\",\"authored_at\":\"2019-10-17T11:13:57-07:00\",\"commit_oid\":\"3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c\",\"commits_ago_from_head\":4831,\"committed_at\":\"2019-10-17T11:13:57-07:00\",\"committer_email\":\"rahulpa@google.com\",\"committer_name\":\"rghetia\",\"parent_oid\":\"11bdacf7b9201e6dd878f0bd902c9d4e7fdb94ec\",\"tree_oid\":\"fec556ef2ebb78ec68594fada50b44a7a07ee8b7\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":4937,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"8ed7ef906a3cb81ebccf8c155c471100e897b478\",\"oldest_commit\":\"29caadf076e86abffd53c7fc2570407d7cf33ec3\"},\"recorded_head_commit\":\"8ed7ef906a3cb81ebccf8c155c471100e897b478\",\"repository_id\":\"github.com/open-telemetry/opentelemetry-go\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/open-telemetry/opentelemetry-go\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":98527,\"manifest_sha256\":null,\"split\":\"15-of-16\"}},\"parents\":[\"commit:github.com/open-telemetry/opentelemetry-go@3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c__download_changed_file_contents_bc7520c83162__render_commit_patches_e5f445c10d8b\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16044,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/bloomberg/lucene-solr@a127d61d70d88d3a941613574f40ae310dfb6760"},"text":{"kind":"string","value":"<|commit_message|>\nSOLR-1301: Add some readme files.\n\ngit-svn-id: https://svn.apache.org/repos/asf/lucene/dev/trunk@1568317 13f79535-47bb-0310-9956-ffa450edef68\n\n<|file_patch|>solr/contrib/map-reduce/README.txt\ndiff --git a/solr/contrib/map-reduce/README.txt b/solr/contrib/map-reduce/README.txt\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..a655aca7663ca666e7c88c99736349d7020076d9\n--- /dev/null\n+++ b/solr/contrib/map-reduce/README.txt\n@@ -0,0 +1,20 @@\n+Apache Solr MapReduce\n+\n+*Experimental* - This contrib is currently subject to change in ways that may \n+break back compatibility.\n+\n+The Solr MapReduce contrib provides an a mapreduce job that allows you to build\n+Solr indexes and optionally merge them into a live Solr cluster.\n+\n+Example:\n+\n+# Build an index with map-reduce and deploy it to SolrCloud\n+\n+source $solr_distrib/example/scripts/map-reduce/set-map-reduce-classpath.sh\n+\n+$hadoop_distrib/bin/hadoop --config $hadoop_conf_dir jar \\\n+$solr_distrib/dist/solr-map-reduce-*.jar -D 'mapred.child.java.opts=-Xmx500m' \\\n+-libjars \"$HADOOP_LIBJAR\" --morphline-file readAvroContainer.conf \\\n+--zk-host 127.0.0.1:9983 --output-dir hdfs://127.0.0.1:8020/outdir \\\n+--collection $collection --log4j log4j.properties --go-live \\\n+--verbose \"hdfs://127.0.0.1:8020/indir\"\n\\ No newline at end of file\n\n<|file_patch|>solr/contrib/morphlines-cell/README.txt\ndiff --git a/solr/contrib/morphlines-cell/README.txt b/solr/contrib/morphlines-cell/README.txt\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..210c39fc12f1e1ced18a6ccd921ea370e3ff9c06\n--- /dev/null\n+++ b/solr/contrib/morphlines-cell/README.txt\n@@ -0,0 +1,6 @@\n+Apache Solr Morphlines-Cell\n+\n+*Experimental* - This contrib is currently subject to change in ways that may \n+break back compatibility.\n+\n+This contrib provides a variety of Kite Morphlines features for Solr Cell type funtionality.\n\\ No newline at end of file\n\n<|file_patch|>solr/contrib/morphlines-core/README.txt\ndiff --git a/solr/contrib/morphlines-core/README.txt b/solr/contrib/morphlines-core/README.txt\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0efa4674258b827f2edfd0651cacef4a2b2abf75\n--- /dev/null\n+++ b/solr/contrib/morphlines-core/README.txt\n@@ -0,0 +1,6 @@\n+Apache Solr Morphlines-Core\n+\n+*Experimental* - This contrib is currently subject to change in ways that may \n+break back compatibility.\n+\n+This contrib provides a variety of Kite Morphlines features for Solr.\n\\ No newline at end of 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removal of smvs\n\n\nFormer-commit-id: ae3221aa8b04a376b278176e76f106ed634659d6\n<|file_patch|>README.md\ndiff --git a/README.md b/README.md\nindex 98d4f0a6978169b8b057a3c46f87ec0233e10dd6..1515a69d0116091d8c35aceef79412e6ee7186e4 100644\n--- a/README.md\n+++ b/README.md\n@@ -199,7 +199,7 @@ If you want to get all intermediate outputs, run the following command:\n -v \"$(pwd)/odm_orthophoto:/code/odm_orthophoto\" \\\n -v \"$(pwd)/odm_texturing:/code/odm_texturing\" \\\n -v \"$(pwd)/opensfm:/code/opensfm\" \\\n- -v \"$(pwd)/smvs:/code/smvs\" \\\n+ -v \"$(pwd)/mve:/code/mve\" \\\n opendronemap/opendronemap\n \n To pass in custom parameters to the run.py script, simply pass it as arguments to the `docker run` command. For example:\n\n<|file_patch|>SuperBuild/CMakeLists.txt\ndiff --git a/SuperBuild/CMakeLists.txt b/SuperBuild/CMakeLists.txt\nindex b2a371422b87637d7ae3514e0f1489975c6a4f66..07a82e48924164f779710bcbb524c50a5949aa53 100644\n--- a/SuperBuild/CMakeLists.txt\n+++ b/SuperBuild/CMakeLists.txt\n@@ -128,7 +128,7 @@ foreach(lib ${custom_libs})\n \tSETUP_EXTERNAL_PROJECT_CUSTOM(${lib})\n endforeach()\n \n-## Add smvs Build\n+## Add mve Build\n \n externalproject_add(mve\n GIT_REPOSITORY https://github.com/simonfuhrmann/mve.git\n@@ -141,18 +141,6 @@ externalproject_add(mve\n INSTALL_COMMAND \"\"\n )\n \n-#externalproject_add(smvs\n-# DEPENDS mve\n-# GIT_REPOSITORY https://github.com/flanggut/smvs.git\n-# GIT_TAG 6a7d0c095aa66ab98c5b285c2bc04e34d8993353\n-# UPDATE_COMMAND \"\"\n-# SOURCE_DIR ${SB_SOURCE_DIR}/elibs/smvs\n-# CONFIGURE_COMMAND \"\"\n-# BUILD_IN_SOURCE 1\n-# BUILD_COMMAND make\n-# INSTALL_COMMAND \"\"\n-#)\n-\n externalproject_add(poissonrecon\n GIT_REPOSITORY https://github.com/mkazhdan/PoissonRecon.git\n GIT_TAG ce5005ae3094d902d551a65a8b3131e06f45e7cf\n\n<|file_patch|>opendm/config.py\ndiff --git a/opendm/config.py b/opendm/config.py\nindex 2fdb0e6c222a4ae235f816cb5c0029b7ab5aa5b8..db09d5ba2470db617c2363743c88bfb61af45434 100644\n--- a/opendm/config.py\n+++ b/opendm/config.py\n@@ -211,41 +211,6 @@ def config():\n 'resizes images when necessary, resulting in faster processing and '\n 'lower memory usage. Since GSD is an estimate, sometimes ignoring it can result in slightly better image output quality.')\n \n- parser.add_argument('--smvs-alpha',\n- metavar='<float>',\n- default=1.0,\n- type=float,\n- help='Regularization parameter, a higher alpha leads to '\n- 'smoother surfaces. Default: %(default)s')\n-\n- parser.add_argument('--smvs-output-scale',\n- metavar='<positive integer>',\n- default=1,\n- type=int,\n- help='The scale of the optimization - the '\n- 'finest resolution of the bicubic patches will have the'\n- ' size of the respective power of 2 (e.g. 2 will '\n- 'optimize patches covering down to 4x4 pixels). '\n- 'Default: %(default)s')\n-\n- parser.add_argument('--smvs-enable-shading',\n- action='store_true',\n- default=False,\n- help='Use shading-based optimization. This model cannot '\n- 'handle complex scenes. Try to supply linear images to '\n- 'the reconstruction pipeline that are not tone mapped '\n- 'or altered as this can also have very negative effects '\n- 'on the reconstruction. If you have simple JPGs with SRGB '\n- 'gamma correction you can remove it with the --smvs-gamma-srgb '\n- 'option. Default: %(default)s')\n-\n- parser.add_argument('--smvs-gamma-srgb',\n- action='store_true',\n- default=False,\n- help='Apply inverse SRGB gamma correction. To be used '\n- 'with --smvs-enable-shading when you have simple JPGs with '\n- 'SRGB gamma correction. Default: %(default)s')\n-\n parser.add_argument('--mesh-size',\n metavar='<positive integer>',\n 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prep for 3.1.0 (#1313)\n\n\n<|file_patch|>CHANGELOG.md\ndiff --git a/CHANGELOG.md b/CHANGELOG.md\nindex 7ecf797d29bac47d64331b438e9492d14ad19d6e..764c1738c5963e2714e55b22f69d8b8982b5192a 100644\n--- a/CHANGELOG.md\n+++ b/CHANGELOG.md\n@@ -3,15 +3,17 @@\n This document records all notable changes to [HTTPie](https://httpie.io).\n This project adheres to [Semantic Versioning](https://semver.org/).\n \n-## [3.0.3.dev0](https://github.com/httpie/httpie/compare/3.0.2...HEAD) (Unreleased)\n+## [3.1.0](https://github.com/httpie/httpie/compare/3.0.2...3.1.0) (2022-03-08)\n \n-- Added support for specifying certificate private key passphrases through `--cert-key-pass` and prompts. ([#946](https://github.com/httpie/httpie/issues/946))\n+- **SECURITY** Fixed the [vulnerability](https://github.com/httpie/httpie/security/advisories/GHSA-9w4w-cpc8-h2fq) that caused exposure of cookies on redirects to third party hosts. ([#1312](https://github.com/httpie/httpie/pull/1312))\n - Fixed escaping of integer indexes with multiple backslashes in the nested JSON builder. ([#1285](https://github.com/httpie/httpie/issues/1285))\n - Fixed displaying of status code without a status message on non-`auto` themes. ([#1300](https://github.com/httpie/httpie/issues/1300))\n - Fixed redundant issuance of stdin detection warnings on some rare cases due to underlying implementation. ([#1303](https://github.com/httpie/httpie/pull/1303))\n+- Fixed double `--quiet` so that it will now suppress all python level warnings. ([#1271](https://github.com/httpie/httpie/issues/1271))\n+- Added support for specifying certificate private key passphrases through `--cert-key-pass` and prompts. ([#946](https://github.com/httpie/httpie/issues/946))\n+- Added `httpie cli export-args` command for exposing the parser specification for the `http`/`https` commands. ([#1293](https://github.com/httpie/httpie/pull/1293))\n - Improved regulation of top-level arrays. ([#1292](https://github.com/httpie/httpie/commit/225dccb2186f14f871695b6c4e0bfbcdb2e3aa28))\n - Improved UI layout for standalone invocations. ([#1296](https://github.com/httpie/httpie/pull/1296))\n-- Double `--quiet` flags will now suppress all python level warnings. ([#1271](https://github.com/httpie/httpie/issues/1271))\n \n ## [3.0.2](https://github.com/httpie/httpie/compare/3.0.1...3.0.2) (2022-01-24)\n \n\n<|file_patch|>httpie/__init__.py\ndiff --git a/httpie/__init__.py b/httpie/__init__.py\nindex 683e7b98a7645c8f20465489e1719a454ee88314..90aa2789d28462b1980f5573047494405687cb1a 100644\n--- a/httpie/__init__.py\n+++ b/httpie/__init__.py\n@@ -3,6 +3,6 @@ HTTPie: modern, user-friendly command-line HTTP client for the API era.\n \n \"\"\"\n \n-__version__ = '3.0.3.dev0'\n+__version__ = '3.1.0'\n __author__ = 'Jakub Roztocil'\n __licence__ = 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Beta version 11 to 12\n\n<|file_patch|>README.md\ndiff --git a/README.md b/README.md\nindex de0fd2390f8a212ec1ef0adbfcb3ab777a110906..b7f31cb4c303eb48fa3382a1491201dee3629bb6 100644\n--- a/README.md\n+++ b/README.md\n@@ -24,13 +24,14 @@ The Drupal Console is a suite of tools that you run on a command line interface\n to generate boilerplate code and interact with a Drupal 8 installation.\n \n ## Supported Drupal version\n-\n-Drupal Console is only compatible with [Drupal 8](http://ftp.drupal.org/files/projects/drupal-8.0.0-beta11.tar.gz), some version of which *must* be installed in order to run Drupal Console commands.\n+The Drupal 8 supported version is [Drupal 8 Beta 12](http://ftp.drupal.org/files/projects/drupal-8.0.0-beta12.tar.gz).\n \n ## Drupal Console documentation\n-\n You can read or download the Drupal Console documentation at [bit.ly/console-book](http://bit.ly/console-book).\n \n+## Drupal Console support\n+You can ask for support at Drupal Console gitter chat room [http://bit.ly/console-support](http://bit.ly/console-support).\n+\n ## Installing Drupal Console\n ```\n # Run this in your terminal to get the latest Console version:\n@@ -52,7 +53,6 @@ drupal generate:module\n ```\n \n ## Using Drupal Console\n-\n \n \n ## Supporting organizations\n\n"},"target_character_start":{"kind":"number","value":49,"string":"49"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":1339,"string":"1,339"},"document_order_key":{"kind":"number","value":2944457470363904500,"string":"2,944,457,470,363,904,500"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/hechoendrupal/drupal-console"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"markdown"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/hechoendrupal/drupal-console\",\"commit_oid\":\"1bc213bfd2b5c1ab5723575a68574cb08e59ef2c\",\"commits_ago_from_head\":4719,\"content_sha256\":\"2dc477c1bd46f816530419fbf64d1472a6739c59e5b802dea026939ca1db4b0f\",\"manifest_sha256\":null,\"parent_oid\":\"78c9dd0a97548577de744c3e5dd4f75fe317fd9c\",\"repository_id\":\"github.com/hechoendrupal/drupal-console\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":4,\"repo_score_components\":{\"dependents_reach\":4,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":6,\"scope\":null,\"subject_length\":28,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":4,\"context_bytes\":2837,\"deleted_lines\":4,\"files_changed\":1,\"hunk_count\":2,\"patch_bytes\":1265,\"patch_sha256\":\"00858eb2c4753ab555b689b8e6ddf9effdb0212079416949e6a749bc15640af8\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"markdown\",\"path\":\"README.md\",\"purpose\":\"docs\"}],\"primary_language\":\"markdown\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":2837,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":1265},\"commit_oid\":\"1bc213bfd2b5c1ab5723575a68574cb08e59ef2c\",\"identity\":{\"author_email\":\"jesus.olivas@gmail.com\",\"author_name\":\"Jesus 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variable sized text to the list of things multiplexers break\n\n<|file_patch|>docs/faq.rst\ndiff --git a/docs/faq.rst b/docs/faq.rst\nindex b7419461a456addc8122581ee1a4c9981b13183c..8c059d8e4de481c515c912e9e2765200ea98ad9e 100644\n--- a/docs/faq.rst\n+++ b/docs/faq.rst\n@@ -504,9 +504,10 @@ for tmux refusing to support images.\n \n If you use any of the advanced features that kitty has innovated, such as\n :doc:`styled underlines </underlines>`, :doc:`desktop notifications\n-</desktop-notifications>`, :doc:`extended keyboard support\n-</keyboard-protocol>`, :doc:`file transfer </kittens/transfer>`, :doc:`the ssh\n-kitten </kittens/ssh>`, :doc:`shell integration </shell-integration>` etc. they may or may not work,\n+</desktop-notifications>`, :doc:`variable sized text </text-sizing-protocol>`,\n+:doc:`extended keyboard support </keyboard-protocol>`,\n+:doc:`file transfer </kittens/transfer>`, :doc:`the ssh kitten </kittens/ssh>`,\n+:doc:`shell integration </shell-integration>` etc. they may or may not work,\n depending on the whims of tmux's maintainer, your version of tmux, etc.\n \n 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jenkins/ath Docker tag to v6059 (#9914)\n\nCo-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>\n<|file_patch|>ath.sh\ndiff --git a/ath.sh b/ath.sh\nindex d57b7834ee32e40561a4201328946b9945e5d9f9..c3a56d5fe4f8e463ff68e16e7683aa6db7e6fca6 100644\n--- a/ath.sh\n+++ b/ath.sh\n@@ -6,7 +6,7 @@ set -o xtrace\n cd \"$(dirname \"$0\")\"\n \n # https://github.com/jenkinsci/acceptance-test-harness/releases\n-export ATH_VERSION=6058.v6b_05a_06f312a_\n+export ATH_VERSION=6059.veb_df63f37069\n \n if [[ $# -eq 0 ]]; then\n \texport JDK=17\n\n"},"target_character_start":{"kind":"number","value":147,"string":"147"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":564,"string":"564"},"document_order_key":{"kind":"number","value":2944541359124120000,"string":"2,944,541,359,124,120,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/jenkinsci/jenkins"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"detected_named_ai_or_bot_signal"},"commit_score":{"kind":"number","value":9,"string":"9"},"primary_language":{"kind":"string","value":"shell"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/jenkinsci/jenkins\",\"commit_oid\":\"bd90608a6fef0459d48483bf6652e9097e9ef277\",\"commits_ago_from_head\":3022,\"content_sha256\":\"6b25082bd81b72cd6a165d684d1d7a9669b2a0be016d9f5ae239f7e92bd5728b\",\"manifest_sha256\":null,\"parent_oid\":\"6c0422fcda13ab5bad51a5075a81de1ede4398b4\",\"repository_id\":\"github.com/jenkinsci/jenkins\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":9,\"deductions\":[],\"repo_score\":9,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":2,\"route_family_breadth\":2,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#9914\"],\"message_words\":10,\"scope\":null,\"subject_length\":46,\"trailer_names\":[\"Co-authored-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":1,\"context_bytes\":1769,\"deleted_lines\":1,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":395,\"patch_sha256\":\"916e2fd3009539646b332894e4ff4a5cfd8ff88b27d12391c75796e7c22683b9\"},\"possible_ai_authorship\":{\"matched\":[{\"field\":\"author_name\",\"pattern\":\"renovate\",\"value\":\"renovate[bot]\"},{\"field\":\"author_name\",\"pattern\":\"bot_suffix\",\"value\":\"renovate[bot]\"},{\"field\":\"author_email\",\"pattern\":\"renovate\",\"value\":\"29139614+renovate[bot]@users.noreply.github.com\"},{\"field\":\"author_email\",\"pattern\":\"noreply_bot_email\",\"value\":\"29139614+renovate[bot]@users.noreply.github.com\"},{\"field\":\"co_authored_by_trailer\",\"pattern\":\"renovate\",\"value\":\"renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>\"}],\"pattern_version\":1,\"signal\":\"detected_named_ai_or_bot_signal\"},\"programming_languages\":{\"files\":[{\"language\":\"shell\",\"path\":\"ath.sh\",\"purpose\":\"source\"}],\"primary_language\":\"shell\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":1769,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":395},\"commit_oid\":\"bd90608a6fef0459d48483bf6652e9097e9ef277\",\"identity\":{\"author_email\":\"29139614+renovate[bot]@users.noreply.github.com\",\"author_name\":\"renovate[bot]\",\"authored_at\":\"2024-10-26T11:51:30-07:00\",\"commit_oid\":\"bd90608a6fef0459d48483bf6652e9097e9ef277\",\"commits_ago_from_head\":3022,\"committed_at\":\"2024-10-26T11:51:30-07:00\",\"committer_email\":\"noreply@github.com\",\"committer_name\":\"GitHub\",\"parent_oid\":\"6c0422fcda13ab5bad51a5075a81de1ede4398b4\",\"tree_oid\":\"f5fecc24e2bd554d2f9e7732a0983b5473e99e39\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"2e228ff40b14dbc8b14ffbc6edf0e4383cf744fc\",\"oldest_commit\":\"0831263b271d46d3e37ae78704c031d4eb0f262d\"},\"recorded_head_commit\":\"2e228ff40b14dbc8b14ffbc6edf0e4383cf744fc\",\"repository_id\":\"github.com/jenkinsci/jenkins\",\"snapshot_check\":\"repo_moved_ahead_of_recorded_head\"},\"repository_id\":\"github.com/jenkinsci/jenkins\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":94448,\"manifest_sha256\":null,\"split\":\"00-of-16\"}},\"parents\":[\"commit:github.com/jenkinsci/jenkins@bd90608a6fef0459d48483bf6652e9097e9ef277__download_changed_file_contents_32b528e3cdb9__render_commit_patches_27b2a2548292\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16050,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/love2d/love@c8f549490026aa35a7b48b4c6068da614000e93b"},"text":{"kind":"string","value":"<|commit_message|>\nImages, Canvases, Quads, and Fonts now have the same vertex winding order\n\n<|file_patch|>src/modules/graphics/opengl/Canvas.cpp\ndiff --git a/src/modules/graphics/opengl/Canvas.cpp b/src/modules/graphics/opengl/Canvas.cpp\nindex a5900e7ed21bc7b90ded0e115c854acbf2e2e8d1..0aa4b61cb0c1ab408664d056d5ecf5923f7eea09 100644\n--- a/src/modules/graphics/opengl/Canvas.cpp\n+++ b/src/modules/graphics/opengl/Canvas.cpp\n@@ -376,22 +376,22 @@ Canvas::Canvas(int width, int height, TextureType texture_type)\n \t// world coordinates\n \tvertices[0].x = 0;\n \tvertices[0].y = h;\n-\tvertices[1].x = 0;\n-\tvertices[1].y = 0;\n+\tvertices[1].x = w;\n+\tvertices[1].y = h;\n \tvertices[2].x = w;\n \tvertices[2].y = 0;\n-\tvertices[3].x = w;\n-\tvertices[3].y = h;\n+\tvertices[3].x = 0;\n+\tvertices[3].y = 0;\n \n \t// texture coordinates\n \tvertices[0].s = 0;\n \tvertices[0].t = 0;\n-\tvertices[1].s = 0;\n-\tvertices[1].t = 1;\n+\tvertices[1].s = 1;\n+\tvertices[1].t = 0;\n \tvertices[2].s = 1;\n \tvertices[2].t = 1;\n-\tvertices[3].s = 1;\n-\tvertices[3].t = 0;\n+\tvertices[3].s = 0;\n+\tvertices[3].t = 1;\n \n \tsettings.filter = Image::getDefaultFilter();\n \n\n<|file_patch|>src/modules/graphics/opengl/Font.cpp\ndiff --git a/src/modules/graphics/opengl/Font.cpp b/src/modules/graphics/opengl/Font.cpp\nindex 76686b61f5bf1910bfd6acbb3bf7f42cbe6f4d8c..3fd5acb86f5c495308a0f715134db56b841bd229 100644\n--- a/src/modules/graphics/opengl/Font.cpp\n+++ b/src/modules/graphics/opengl/Font.cpp\n@@ -216,9 +216,9 @@ Font::Glyph *Font::addGlyph(uint32 glyph)\n \n \t\tconst GlyphVertex verts[4] = {\n \t\t\t{ 0.0f, 0.0f, float(textureX)/float(textureWidth), float(textureY)/float(textureHeight)},\n-\t\t\t{float(w), 0.0f, float(textureX+w)/float(textureWidth), float(textureY)/float(textureHeight)},\n-\t\t\t{float(w), float(h), float(textureX+w)/float(textureWidth), float(textureY+h)/float(textureHeight)},\n \t\t\t{ 0.0f, float(h), float(textureX)/float(textureWidth), float(textureY+h)/float(textureHeight)},\n+\t\t\t{float(w), float(h), float(textureX+w)/float(textureWidth), float(textureY+h)/float(textureHeight)},\n+\t\t\t{float(w), 0.0f, float(textureX+w)/float(textureWidth), float(textureY)/float(textureHeight)},\n \t\t};\n \n \t\t// copy vertex data to the glyph and set proper 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Szpakowski\",\"parent_oid\":\"5179ca5655eec9c1a7947d5303346fc9db1723ed\",\"tree_oid\":\"6732e82230c74900affe21330138e15c020f9444\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":5715,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"853f1cad4bb65d63f02dbcd3fa31b0c622d3abbc\",\"oldest_commit\":\"dcb3dfd83d2c275bb2cdb5d88ba62323f16bd979\"},\"recorded_head_commit\":\"853f1cad4bb65d63f02dbcd3fa31b0c622d3abbc\",\"repository_id\":\"github.com/love2d/love\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/love2d/love\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":96150,\"manifest_sha256\":null,\"split\":\"06-of-16\"}},\"parents\":[\"commit:github.com/love2d/love@c8f549490026aa35a7b48b4c6068da614000e93b__download_changed_file_contents_81e08616b41f__render_commit_patches_6e70a01f5349\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16051,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/acquia/travis.rb@ddc2e9801dc7f91182ab53be464814c64886bba9"},"text":{"kind":"string","value":"<|commit_message|>\nAdd cloudControl setup\n\n<|file_patch|>completion/travis.sh\ndiff --git a/completion/travis.sh b/completion/travis.sh\nindex ac3840f06e743aeaaf7f3fed708db49017f90694..96b816ad7353c20cc6df4a43cd498853a4d870f9 100644\n--- a/completion/travis.sh\n+++ b/completion/travis.sh\n@@ -478,6 +478,7 @@ nodejitsu\n sauce_connect\n sauce_labs\n sauce\n+cloudcontrol\n --help\n -h\n --interactive\n@@ -1138,6 +1139,7 @@ nodejitsu\n sauce_connect\n sauce_labs\n sauce\n+cloudcontrol\n --help\n -h\n --interactive\n\n<|file_patch|>lib/travis/cli/setup.rb\ndiff --git a/lib/travis/cli/setup.rb b/lib/travis/cli/setup.rb\nindex 5e8dee2da88ed9ab36b68bb385ded70b717966d8..101a81feafc067ebcdc15b49d8ad0359742c96ef 100644\n--- a/lib/travis/cli/setup.rb\n+++ b/lib/travis/cli/setup.rb\n@@ -90,6 +90,18 @@ module Travis\n alias setup_sauce_labs setup_sauce_connect\n alias setup_sauce setup_sauce_connect\n \n+ def setup_cloudcontrol\n+ configure 'deploy', 'provider' => 'cloudcontrol' do |config|\n+ config['email'] = ask(\"cloudControl email: \").to_s\n+ config['password'] = ask(\"cloudControl password: \") { |q| q.echo = \"*\" }.to_s\n+ app = ask(\"cloudControl application: \").to_s\n+ dep = ask(\"cloudControl deployment: \").to_s\n+ config['deployment'] = \"#{app}/#{dep}\"\n+ config['on'] = { 'repo' => repository.slug } if agree(\"Deploy only from #{repository.slug}? \") { |q| q.default = 'yes' }\n+ encrypt(config, 'password') if agree(\"Encrypt password key? \") { |q| q.default = 'yes' }\n+ end\n+ end\n+ \n private\n \n def encrypt(config, key)\n\n<|file_patch|>spec/cli/setup_spec.rb\ndiff --git a/spec/cli/setup_spec.rb b/spec/cli/setup_spec.rb\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..5a553d5747cd2f12a7ef60b48b23fc01bbe5dab0\n--- /dev/null\n+++ b/spec/cli/setup_spec.rb\n@@ -0,0 +1,25 @@\n+require 'spec_helper'\n+\n+describe Travis::CLI::Setup do\n+ example 'setup cloudcontrol' do\n+ run_cli('setup', 'cloudcontrol') { |i|\n+ i.puts('email')\n+ i.puts('password')\n+ i.puts('application')\n+ i.puts('deployment')\n+ i.puts('yes')\n+ i.puts('yes')}.should be_success\n+ stdout.should be == \"cloudControl email: cloudControl password: ********\\ncloudControl application: cloudControl deployment: Deploy only from rails/rails? |yes| Encrypt password key? |yes| \"\n+ file = File.expand_path('.travis.yml', Dir.pwd.gsub!(/\\/spec/, ''))\n+ config = YAML.load_file(file)\n+ \n+ config['deploy']['provider'].should eql('cloudcontrol')\n+ config['deploy']['email'].should eql('email')\n+ config['deploy']['deployment'].should eql('application/deployment')\n+\n+ config.delete('deploy')\n+ yaml = config.to_yaml\n+ yaml.gsub! /\\A---\\s*\\n/, ''\n+ File.write(file, yaml)\n+ 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to newtonsoft json\n\n<|file_patch|>LenovoLegionToolkit.Lib/Structs.cs\ndiff --git a/LenovoLegionToolkit.Lib/Structs.cs b/LenovoLegionToolkit.Lib/Structs.cs\nindex b2a3148ea208c01370d4eb58ad6e7970f63c25a6..fe41815d54c87e99331e7237733f292ad3df3114 100644\n--- a/LenovoLegionToolkit.Lib/Structs.cs\n+++ b/LenovoLegionToolkit.Lib/Structs.cs\n@@ -1,6 +1,7 @@\n using System;\n using System.Collections.Generic;\n using System.Linq;\n+using Newtonsoft.Json;\n using Octokit;\n \n namespace LenovoLegionToolkit.Lib\n@@ -65,6 +66,7 @@ namespace LenovoLegionToolkit.Lib\n {\n public int Frequency { get; }\n \n+ [JsonIgnore]\n public string DisplayName => $\"{Frequency} Hz\";\n \n public RefreshRate(int frequency)\n\n"},"target_character_start":{"kind":"number","value":45,"string":"45"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":748,"string":"748"},"document_order_key":{"kind":"number","value":2945155192098500000,"string":"2,945,155,192,098,500,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bartoszcichecki/lenovolegiontoolkit"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":5,"string":"5"},"primary_language":{"kind":"string","value":"csharp"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bartoszcichecki/lenovolegiontoolkit\",\"commit_oid\":\"599b66c89920bb38a4f0382a6573b659455bab99\",\"commits_ago_from_head\":2453,\"content_sha256\":\"83403a4753382e79027a50c5d0b5c76f397026715c40a694eb19da6c8b5a1d28\",\"manifest_sha256\":null,\"parent_oid\":\"b6a5c0c48b7bd7546b3a932449381426406f9246\",\"repository_id\":\"github.com/bartoszcichecki/lenovolegiontoolkit\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":5,\"deductions\":[],\"repo_score\":5,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":4,\"scope\":null,\"subject_length\":24,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":2,\"context_bytes\":3282,\"deleted_lines\":0,\"files_changed\":1,\"hunk_count\":2,\"patch_bytes\":653,\"patch_sha256\":\"f1f05645dacd601df7c9c50e8b419b4efc130e1ee31086fecf7be99873118da8\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"csharp\",\"path\":\"LenovoLegionToolkit.Lib/Structs.cs\",\"purpose\":\"source\"}],\"primary_language\":\"csharp\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":3282,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":653},\"commit_oid\":\"599b66c89920bb38a4f0382a6573b659455bab99\",\"identity\":{\"author_email\":\"cichecki.bartosz@gmail.com\",\"author_name\":\"Bartosz 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v0.12.0-beta.2\n\n<|file_patch|>CHANGELOG.md\ndiff --git a/CHANGELOG.md b/CHANGELOG.md\nindex 8f1b2e676aaa76bd27c89190e6314cba1baff66e..0a015e2bb9ce100204743820b8f0fbe4cfaddcde 100644\n--- a/CHANGELOG.md\n+++ b/CHANGELOG.md\n@@ -1,3 +1,8 @@\n+# 0.12-beta.2\n+\n+- [BUGFIX] Focus the trigger when the component is closed\n+- [BUGFIX] Allow to attach `onFocusIn` and `onFocusOut` event the the dropdown content component.\n+\n # 0.12-beta.1\n \n - [BUGFIX] Around half a docen regressions and changes, including add the proper classes to trigger\n\n<|file_patch|>package.json\ndiff --git a/package.json b/package.json\nindex a34dbfe6ecb15f7b7d44bd3b37b6e332a6b70d60..4d58f6e47d135d1da6187ddf873d7ed25ebd20f9 100644\n--- a/package.json\n+++ b/package.json\n@@ -1,6 +1,6 @@\n {\n \"name\": \"ember-basic-dropdown\",\n- \"version\": \"0.12.0-beta.1\",\n+ \"version\": \"0.12.0-beta.2\",\n \"description\": \"The default blueprint for ember-cli addons.\",\n \"directories\": {\n \"doc\": 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changelog.md\n<|file_patch|>changelog.md\ndiff --git a/changelog.md b/changelog.md\nindex d9a35d2a20fb39b08b7016783672e8cd5d41d79a..4b75c7db1b7a449a65f135abca3741423bf34ea7 100644\n--- a/changelog.md\n+++ b/changelog.md\n@@ -5,9 +5,6 @@\n * [Kimundi](https://github.com/Kimundi) fixed an issue that could make `try_zeroed_box` stack overflow for large values at low optimization levels.\n [PR 43](https://github.com/Lokathor/bytemuck/pull/43)\n \n-* [yanchith](https://github.com/yanchith) fixed the derive checks code to make clippy more happy.\n-[PR 45](https://github.com/Lokathor/bytemuck/pull/45)\n-\n ## 1.4.1\n \n * [thomcc](https://github.com/thomcc) fixed up the CI and patched over a soundness hole in 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run-tests.yml\n\n<|file_patch|>.github/workflows/run-tests.yml\ndiff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml\nindex a68c1dc2457e84a24b389481eeb5b9bb423b27a0..2eec514127cd191fd67582c58e0fded9d7b1ffda 100644\n--- a/.github/workflows/run-tests.yml\n+++ b/.github/workflows/run-tests.yml\n@@ -62,5 +62,5 @@ jobs:\n \n - name: Upload coverage\n run: |\n- wget https://scrutinizer-ci.com/ocular.phar\n+ curl -O https://scrutinizer-ci.com/ocular.phar\n php ocular.phar code-coverage:upload --format=php-clover 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encoding bugs in DigestInputStream2Test and MessageDigest2Test for z/OS\n\ngit-svn-id: https://svn.apache.org/repos/asf/harmony/enhanced/classlib/trunk@796991 13f79535-47bb-0310-9956-ffa450edef68\n\n<|file_patch|>modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/DigestInputStream2Test.java\ndiff --git a/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/DigestInputStream2Test.java b/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/DigestInputStream2Test.java\nindex 438e1b43be1661dd9e13a1a39171688307af0e08..d30f3dff1794a7ddf681b85b8a1a3621d30dd942 100644\n--- a/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/DigestInputStream2Test.java\n+++ b/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/DigestInputStream2Test.java\n@@ -19,6 +19,7 @@ package org.apache.harmony.security.tests.java.security;\n \n import java.io.ByteArrayInputStream;\n import java.io.IOException;\n+import java.io.UnsupportedEncodingException;\n import java.security.DigestInputStream;\n import java.security.MessageDigest;\n import java.security.NoSuchAlgorithmException;\n@@ -149,13 +150,14 @@ public class DigestInputStream2Test extends junit.framework.TestCase {\n \t/**\n \t * Sets up the fixture, for example, open a network connection. This method\n \t * is called before a test is executed.\n+\t * @throws UnsupportedEncodingException \n \t */\n-\tprotected void setUp() {\n+\tprotected void setUp() throws UnsupportedEncodingException {\n \t\t// create a ByteArrayInputStream to perform digesting on\n \t\tinStream = new ByteArrayInputStream(\n-\t\t\t\t\"This is a test string for digesting\".getBytes());\n+\t\t\t\t\"This is a test string for digesting\".getBytes(\"UTF-8\"));\n \t\tinStream1 = new ByteArrayInputStream(\n-\t\t\t\t\"This is a test string for digesting\".getBytes());\n+\t\t\t\t\"This is a test string for digesting\".getBytes(\"UTF-8\"));\n \t\ttry {\n \t\t\tdigest = MessageDigest.getInstance(\"SHA-1\");\n \t\t} catch (NoSuchAlgorithmException e) {\n\n<|file_patch|>modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/MessageDigest2Test.java\ndiff --git a/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/MessageDigest2Test.java b/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/MessageDigest2Test.java\nindex 034a0c96a531d0fd6d6e73f005b8ba1c781f2e0d..0f06f9b14f00a96b4cf647eb98068739b1187ad9 100644\n--- a/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/MessageDigest2Test.java\n+++ b/modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/MessageDigest2Test.java\n@@ -20,6 +20,7 @@ package org.apache.harmony.security.tests.java.security;\n import java.io.ByteArrayOutputStream;\n import java.io.DataOutputStream;\n import java.io.IOException;\n+import java.io.UnsupportedEncodingException;\n import java.security.DigestException;\n import java.security.MessageDigest;\n import java.security.NoSuchAlgorithmException;\n@@ -207,9 +208,10 @@ public class MessageDigest2Test extends junit.framework.TestCase {\n \t}\n \n \t/**\n+\t * @throws UnsupportedEncodingException \n \t * @tests java.security.MessageDigest#digest()\n \t */\n-\tpublic void test_digest() {\n+\tpublic void test_digest() throws UnsupportedEncodingException {\n \t\tMessageDigest sha = null;\n \t\ttry {\n \t\t\tsha = MessageDigest.getInstance(\"SHA\");\n@@ -217,7 +219,7 @@ public class MessageDigest2Test extends junit.framework.TestCase {\n \t\t} catch (NoSuchAlgorithmException e) {\n \t\t\tfail(\"getInstance did not find algorithm\");\n \t\t}\n-\t\tsha.update(MESSAGE.getBytes());\n+\t\tsha.update(MESSAGE.getBytes(\"UTF-8\"));\n \t\tbyte[] digest = sha.digest();\n \t\tassertTrue(\"bug in SHA\", MessageDigest.isEqual(digest, MESSAGE_DIGEST));\n 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Disable multiple click on the same case (#13109)\n\n* Checkpoint\n\n* Checkpoint\n\n* Add loading indicator to cases while opening and disable sub mouse clicks\n\n* Add loading indicator to mobile category cards\n\n* Add opening indcator to past cases\n\n* Add loading indicator to mobile cards\n\n* Remove duplicate code\n\n* Cleanup\n\n* Clear timeouts\n\n* Add aria-diabled to mobile cards when loading\n\n* Fix tests\n\n* Minor css fix\n\n---------\n\nCo-authored-by: unakb <una@kolibri.is>\nCo-authored-by: kodiakhq[bot] <49736102+kodiakhq[bot]@users.noreply.github.com>\n<|file_patch|>apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx\ndiff --git a/apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx b/apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx\nindex c8bd191bfafc632b59c84996306dd338635a1ca8..3379a8664723ba94ad4a136a207c5a7bdb21b1fc 100644\n--- a/apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx\n+++ b/apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx\n@@ -1,6 +1,7 @@\n import React, { useMemo } from 'react'\n import { useIntl } from 'react-intl'\n import cn from 'classnames'\n+import { AnimatePresence } from 'framer-motion'\n \n import { Box, Text } from '@island.is/island-ui/core'\n import { theme } from '@island.is/island-ui/theme'\n@@ -27,20 +28,22 @@ import {\n useSortAppealCases,\n useViewport,\n } from '@island.is/judicial-system-web/src/utils/hooks'\n+import useCaseList from '@island.is/judicial-system-web/src/utils/hooks/useCaseList'\n \n import MobileAppealCase from './MobileAppealCase'\n import * as styles from '../Table.css'\n \n interface Props {\n cases: CaseListEntry[]\n- onRowClick: (id: string) => void\n loading: boolean\n showingCompletedCases?: boolean\n }\n \n const AppealCasesTable: React.FC<Props> = (props) => {\n- const { cases, onRowClick, loading, showingCompletedCases } = props\n+ const { cases, loading, showingCompletedCases } = props\n const { formatMessage } = useIntl()\n+ const { isOpeningCaseId, handleOpenCase, LoadingIndicator, showLoading } =\n+ useCaseList()\n const { sortedData, requestSort, getClassNamesFor, isActiveColumn } =\n useSortAppealCases('appealedDate', 'descending', cases)\n const activeCasesData = useMemo(\n@@ -59,7 +62,8 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n <Box marginTop={2} key={theCase.id}>\n <MobileAppealCase\n theCase={theCase}\n- onClick={() => onRowClick(theCase.id)}\n+ onClick={() => handleOpenCase(theCase.id)}\n+ isLoading={isOpeningCaseId === theCase.id && showLoading}\n >\n {showingCompletedCases && (\n <Text fontWeight={'medium'} variant=\"small\">\n@@ -89,7 +93,6 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n />\n </th>\n <TableHeaderText title={formatMessage(tables.type)} />\n-\n <TableHeaderText title={formatMessage(tables.state)} />\n {showingCompletedCases ? (\n <TableHeaderText title={formatMessage(tables.duration)} />\n@@ -104,6 +107,7 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n />\n </th>\n )}\n+ <th></th>\n </>\n }\n >\n@@ -111,7 +115,7 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n return (\n <tr\n className={styles.row}\n- onClick={() => onRowClick(column.id)}\n+ onClick={() => handleOpenCase(column.id)}\n key={column.id}\n >\n <td>\n@@ -131,7 +135,6 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n parentCaseId={column.parentCaseId ?? ''}\n />\n </td>\n-\n <td>\n <TagAppealState\n appealState={column.appealState}\n@@ -159,6 +162,13 @@ const AppealCasesTable: React.FC<Props> = (props) => {\n </Text>\n )}\n </td>\n+ <td className={styles.loadingContainer}>\n+ <AnimatePresence>\n+ {isOpeningCaseId === column.id && showLoading && (\n+ <LoadingIndicator />\n+ )}\n+ </AnimatePresence>\n+ </td>\n </tr>\n )\n })}\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx\ndiff --git a/apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx b/apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx\nindex 2d45c5f7f7332bff2971767181a60c90548de14b..aaa122c8d7da7b23fd5bcad269139977842fc223 100644\n--- a/apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx\n+++ b/apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx\n@@ -7,17 +7,23 @@ import {\n formatDOB,\n } from '@island.is/judicial-system/formatters'\n import { TagAppealState } from '@island.is/judicial-system-web/src/components'\n-import { CategoryCard } from '@island.is/judicial-system-web/src/components/Table'\n import { CaseListEntry } from '@island.is/judicial-system-web/src/graphql/schema'\n+import { CategoryCard } from '@island.is/judicial-system-web/src/routes/Shared/Cases/MobileCase'\n import { displayCaseType } from '@island.is/judicial-system-web/src/routes/Shared/Cases/utils'\n \n interface Props {\n children: React.ReactNode\n theCase: CaseListEntry\n onClick: () => void\n+ isLoading?: boolean\n }\n \n-const MobileAppealCase: React.FC<Props> = ({ theCase, onClick, children }) => {\n+const MobileAppealCase: React.FC<Props> = ({\n+ theCase,\n+ onClick,\n+ children,\n+ isLoading = false,\n+}) => {\n const { formatMessage } = useIntl()\n \n return (\n@@ -35,6 +41,7 @@ const MobileAppealCase: React.FC<Props> = ({ theCase, onClick, children }) => {\n appealCaseNumber={theCase.appealCaseNumber}\n />,\n ]}\n+ isLoading={isLoading}\n >\n {theCase.appealCaseNumber && <Text>{theCase.appealCaseNumber}</Text>}\n <Text title={theCase.policeCaseNumbers.join(', ')}>\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.css.ts\ndiff --git a/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.css.ts b/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.css.ts\ndeleted file mode 100644\nindex 0dc23a343620c4250ccf760c06569d518f787230..0000000000000000000000000000000000000000\n--- a/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.css.ts\n+++ /dev/null\n@@ -1,22 +0,0 @@\n-import { style } from '@vanilla-extract/css'\n-\n-import { theme } from '@island.is/island-ui/theme'\n-\n-export const card = style({\n- display: 'flex',\n- position: 'relative',\n- flexDirection: 'row',\n- padding: `${theme.spacing[2]}px`,\n- textAlign: 'left',\n- backgroundColor: theme.color.white,\n- borderRadius: theme.border.radius.large,\n- borderColor: theme.border.color.blue200,\n- borderWidth: theme.border.width.standard,\n- ':focus': {\n- borderColor: theme.border.color.mint400,\n- borderWidth: theme.border.width.large,\n- },\n- ':hover': {\n- borderColor: theme.color.blue400,\n- },\n-})\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.tsx\ndiff --git a/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.tsx b/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.tsx\ndeleted file mode 100644\nindex e617b425a4ceddc1741a21aa87bb90c170089b1a..0000000000000000000000000000000000000000\n--- a/apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.tsx\n+++ /dev/null\n@@ -1,39 +0,0 @@\n-import React from 'react'\n-\n-import { Box, FocusableBox, Text } from '@island.is/island-ui/core'\n-\n-import * as styles from './CategoryCard.css'\n-\n-interface CategoryCardProps {\n- heading: string | React.ReactNode\n- tags?: React.ReactNode\n- onClick: () => void\n- children: React.ReactNode\n-}\n-\n-const CategoryCard: React.FC<CategoryCardProps> = ({\n- heading,\n- onClick,\n- tags,\n- children,\n-}) => {\n- return (\n- <FocusableBox\n- className={styles.card}\n- height=\"full\"\n- width=\"full\"\n- component=\"button\"\n- onClick={onClick}\n- >\n- <Box>\n- <Text variant=\"h3\" as=\"h3\" color={'blue400'} marginBottom={1}>\n- {heading}\n- </Text>\n- {children}\n- <Box marginTop={3}>{tags}</Box>\n- </Box>\n- </FocusableBox>\n- )\n-}\n-\n-export default CategoryCard\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx\ndiff --git a/apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx b/apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx\nindex af40c49d9d7104326bb00bf2492c7656630afc38..88be2159c66836be438ee321b08a8d248c222cd9 100644\n--- a/apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx\n+++ b/apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx\n@@ -10,7 +10,7 @@ import {\n } from '@island.is/judicial-system/formatters'\n import { tables } from '@island.is/judicial-system-web/messages'\n import { TagCaseState } from '@island.is/judicial-system-web/src/components'\n-import { CategoryCard } from '@island.is/judicial-system-web/src/components/Table'\n+import { CategoryCard } from '@island.is/judicial-system-web/src/routes/Shared/Cases/MobileCase'\n import { displayCaseType } from '@island.is/judicial-system-web/src/routes/Shared/Cases/utils'\n import { TempCaseListEntry as CaseListEntry } from '@island.is/judicial-system-web/src/types'\n \n@@ -19,6 +19,7 @@ interface Props {\n onClick: () => void\n isCourtRole: boolean\n children: React.ReactNode\n+ isLoading?: boolean\n }\n \n const MobilePastCase: React.FC<Props> = ({\n@@ -26,6 +27,7 @@ const MobilePastCase: React.FC<Props> = ({\n onClick,\n isCourtRole,\n children,\n+ isLoading = false,\n }) => {\n const { formatMessage } = useIntl()\n \n@@ -42,6 +44,7 @@ const MobilePastCase: React.FC<Props> = ({\n courtDate={theCase.courtDate}\n />,\n ]}\n+ isLoading={isLoading}\n >\n <Text title={theCase.policeCaseNumbers.join(', ')}>\n {displayFirstPlusRemaining(theCase.policeCaseNumbers)}\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx\ndiff --git a/apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx b/apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx\nindex 486c57ac71d7e7a5b8cd4049925ddce31e271b22..a1e829d004f003be0bc651332763a4fdbdae30ba 100644\n--- a/apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx\n+++ b/apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx\n@@ -1,6 +1,7 @@\n import React, { useContext, useMemo } from 'react'\n import { useIntl } from 'react-intl'\n import cn from 'classnames'\n+import { AnimatePresence } from 'framer-motion'\n \n import { Box, Text } from '@island.is/island-ui/core'\n import { theme } from '@island.is/island-ui/theme'\n@@ -30,21 +31,23 @@ import {\n useSortCases,\n useViewport,\n } from '@island.is/judicial-system-web/src/utils/hooks'\n+import useCaseList from '@island.is/judicial-system-web/src/utils/hooks/useCaseList'\n \n import MobilePastCase from './MobilePastCase'\n import * as styles from '../Table.css'\n \n interface Props {\n cases: CaseListEntry[]\n- onRowClick: (id: string) => void\n loading?: boolean\n testid?: string\n }\n \n const PastCasesTable: React.FC<React.PropsWithChildren<Props>> = (props) => {\n- const { cases, onRowClick, loading = false, testid } = props\n+ const { cases, loading = false, testid } = props\n const { formatMessage } = useIntl()\n const { user } = useContext(UserContext)\n+ const { isOpeningCaseId, handleOpenCase, LoadingIndicator, showLoading } =\n+ useCaseList()\n \n const { sortedData, requestSort, getClassNamesFor, isActiveColumn } =\n useSortCases('createdAt', 'descending', cases)\n@@ -65,8 +68,9 @@ const PastCasesTable: React.FC<React.PropsWithChildren<Props>> = (props) => {\n <Box marginTop={2} key={theCase.id}>\n <MobilePastCase\n theCase={theCase}\n- onClick={() => onRowClick(theCase.id)}\n+ onClick={() => handleOpenCase(theCase.id)}\n isCourtRole={false}\n+ isLoading={isOpeningCaseId === theCase.id && showLoading}\n >\n <DurationDate\n key={`${theCase.id}-duration-date`}\n@@ -109,6 +113,7 @@ const PastCasesTable: React.FC<React.PropsWithChildren<Props>> = (props) => {\n </th>\n <TableHeaderText title={formatMessage(tables.state)} />\n <TableHeaderText title={formatMessage(tables.duration)} />\n+ <th></th>\n </>\n }\n >\n@@ -116,7 +121,7 @@ const PastCasesTable: React.FC<React.PropsWithChildren<Props>> = (props) => {\n return (\n <tr\n className={styles.row}\n- onClick={() => onRowClick(column.id)}\n+ onClick={() => handleOpenCase(column.id)}\n key={column.id}\n >\n <td>\n@@ -165,6 +170,13 @@ const PastCasesTable: React.FC<React.PropsWithChildren<Props>> = (props) => {\n )}\n </Text>\n </td>\n+ <td className={styles.loadingContainer}>\n+ <AnimatePresence>\n+ {isOpeningCaseId === column.id && showLoading && (\n+ <LoadingIndicator />\n+ )}\n+ </AnimatePresence>\n+ </td>\n </tr>\n )\n })}\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/Table.css.ts\ndiff --git a/apps/judicial-system/web/src/components/Table/Table.css.ts b/apps/judicial-system/web/src/components/Table/Table.css.ts\nindex 3b53572e91ad1a95d368bb319beab790036542e6..df3f49d234abfcec11e3aebef2c83e5295a67b5b 100644\n--- a/apps/judicial-system/web/src/components/Table/Table.css.ts\n+++ b/apps/judicial-system/web/src/components/Table/Table.css.ts\n@@ -112,3 +112,7 @@ export const sortDes = style({\n opacity: 1,\n transform: 'rotate(0deg)',\n })\n+\n+export const loadingContainer = style({\n+ minWidth: '67px',\n+})\n\n<|file_patch|>apps/judicial-system/web/src/components/Table/index.ts\ndiff --git a/apps/judicial-system/web/src/components/Table/index.ts b/apps/judicial-system/web/src/components/Table/index.ts\nindex 75b693d0638773214a41304e67b0ca119faa5e74..6e1704d824aa50e5cacd3ddb40498253145d0fd9 100644\n--- a/apps/judicial-system/web/src/components/Table/index.ts\n+++ b/apps/judicial-system/web/src/components/Table/index.ts\n@@ -1,4 +1,3 @@\n-export { default as CategoryCard } from './CategoryCard/CategoryCard'\n export { default as ColumnCaseType } from './ColumnCaseType/ColumnCaseType'\n export { default as CourtCaseNumber } from './CourtCaseNumber/CourtCaseNumber'\n export { default as DefendantInfo } from './DefendantInfo/DefendantInfo'\n\n<|file_patch|>apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx\ndiff --git a/apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx b/apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx\nindex 888a6dce8ead89bcc1d320a7a9020e0249555d8b..8a63c4ab39e6ec06aa9726f8867e398d47d8182b 100644\n--- a/apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx\n+++ b/apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx\n@@ -15,7 +15,6 @@ import {\n CaseAppealState,\n CaseListEntry,\n } from '@island.is/judicial-system-web/src/graphql/schema'\n-import { useCase } from '@island.is/judicial-system-web/src/utils/hooks'\n import { AppealedCasesQuery } from '@island.is/judicial-system-web/src/utils/mutations'\n \n import { courtOfAppealCases as strings } from './Cases.strings'\n@@ -23,7 +22,6 @@ import { logoContainer } from '../../Shared/Cases/Cases.css'\n \n const CourtOfAppealCases = () => {\n const { formatMessage } = useIntl()\n- const { getCaseToOpen } = useCase()\n \n const input = { appealState: ['RECEIVED', 'COMPLETED'] }\n \n@@ -47,9 +45,6 @@ const CourtOfAppealCases = () => {\n <Box marginBottom={7}>\n <AppealCasesTable\n loading={loading}\n- onRowClick={(id) => {\n- getCaseToOpen(id)\n- }}\n cases={\n appealedCasesData?.filter(\n (a) => a.appealState !== CaseAppealState.COMPLETED,\n@@ -60,9 +55,6 @@ const CourtOfAppealCases = () => {\n <SectionHeading title={formatMessage(tables.completedCasesTitle)} />\n <AppealCasesTable\n loading={loading}\n- onRowClick={(id) => {\n- getCaseToOpen(id)\n- }}\n cases={\n appealedCasesData?.filter(\n (a) => a.appealState === CaseAppealState.COMPLETED,\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx b/apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx\nindex 81f92635f94746b9fab4be719f361559b21fec00..8cc9f7e79567a6ab7d59840245a442d1cb988c59 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx\n@@ -38,6 +38,7 @@ import {\n TempCaseListEntry as CaseListEntry,\n } from '@island.is/judicial-system-web/src/types'\n import { useViewport } from '@island.is/judicial-system-web/src/utils/hooks'\n+import useCaseList from '@island.is/judicial-system-web/src/utils/hooks/useCaseList'\n import { compareLocaleIS } from '@island.is/judicial-system-web/src/utils/sortHelper'\n \n import MobileCase from './MobileCase'\n@@ -46,13 +47,12 @@ import * as styles from './Cases.css'\n \n interface Props {\n cases: CaseListEntry[]\n- onRowClick: (id: string) => void\n isDeletingCase: boolean\n onDeleteCase?: (caseToDelete: CaseListEntry) => Promise<void>\n }\n \n const ActiveCases: React.FC<React.PropsWithChildren<Props>> = (props) => {\n- const { cases, onRowClick, isDeletingCase, onDeleteCase } = props\n+ const { cases, isDeletingCase, onDeleteCase } = props\n \n const controls = useAnimation()\n \n@@ -65,6 +65,9 @@ const ActiveCases: React.FC<React.PropsWithChildren<Props>> = (props) => {\n \n const { user } = useContext(UserContext)\n const { formatMessage } = useIntl()\n+ const { width } = useViewport()\n+ const { isOpeningCaseId, showLoading, handleOpenCase, LoadingIndicator } =\n+ useCaseList()\n \n const [sortConfig, setSortConfig] = useState<SortConfig>({\n column: 'createdAt',\n@@ -122,16 +125,15 @@ const ActiveCases: React.FC<React.PropsWithChildren<Props>> = (props) => {\n return sortConfig.column === name ? sortConfig.direction : undefined\n }\n \n- const { width } = useViewport()\n-\n return width < theme.breakpoints.md ? (\n <>\n {cases.map((theCase: CaseListEntry) => (\n <Box marginTop={2} key={theCase.id}>\n <MobileCase\n- onClick={() => onRowClick(theCase.id)}\n+ onClick={() => handleOpenCase(theCase.id)}\n theCase={theCase}\n isCourtRole={isDistrictCourtUser(user)}\n+ isLoading={isOpeningCaseId === theCase.id && showLoading}\n >\n {theCase.courtDate && (\n <Text fontWeight={'medium'} variant=\"small\">\n@@ -217,8 +219,9 @@ const ActiveCases: React.FC<React.PropsWithChildren<Props>> = (props) => {\n data-testid=\"custody-cases-table-row\"\n role=\"button\"\n aria-label=\"Opna kröfu\"\n+ aria-disabled={isDeletingCase || isOpeningCaseId === c.id}\n onClick={() => {\n- user?.role && onRowClick(c.id)\n+ handleOpenCase(c.id)\n }}\n >\n <td className={styles.td}>\n@@ -334,35 +337,48 @@ const ActiveCases: React.FC<React.PropsWithChildren<Props>> = (props) => {\n </>\n )}\n </td>\n-\n <td className={cn(styles.td, 'secondLast')}>\n- {isProsecutionUser(user) &&\n- (c.state === CaseState.NEW ||\n- c.state === CaseState.DRAFT ||\n- c.state === CaseState.SUBMITTED ||\n- c.state === CaseState.RECEIVED) && (\n- <Box\n- data-testid=\"deleteCase\"\n- component=\"button\"\n- aria-label=\"Viltu afturkalla kröfu?\"\n- className={styles.deleteButton}\n- onClick={async (evt) => {\n- evt.stopPropagation()\n+ <AnimatePresence exitBeforeEnter initial={false}>\n+ {isOpeningCaseId === c.id && showLoading ? (\n+ <div className={styles.deleteButtonWrapper}>\n+ <LoadingIndicator />\n+ </div>\n+ ) : (\n+ isProsecutionUser(user) &&\n+ (c.state === CaseState.NEW ||\n+ c.state === CaseState.DRAFT ||\n+ c.state === CaseState.SUBMITTED ||\n+ c.state === CaseState.RECEIVED) && (\n+ <motion.button\n+ key={`${c.id}-delete`}\n+ initial={{ opacity: 0 }}\n+ animate={{ opacity: 1 }}\n+ exit={{ opacity: 0 }}\n+ data-testid=\"deleteCase\"\n+ aria-label=\"Viltu afturkalla kröfu?\"\n+ className={cn(\n+ styles.deleteButton,\n+ styles.deleteButtonWrapper,\n+ )}\n+ onClick={async (evt) => {\n+ evt.stopPropagation()\n \n- await new Promise((resolve) => {\n- setRequestToRemoveIndex(\n- requestToRemoveIndex === i ? undefined : i,\n- )\n+ await new Promise((resolve) => {\n+ setRequestToRemoveIndex(\n+ requestToRemoveIndex === i ? undefined : i,\n+ )\n \n- resolve(true)\n- })\n+ resolve(true)\n+ })\n \n- await controls.start('isDeleting')\n- }}\n- >\n- <Icon icon=\"close\" color=\"blue400\" />\n- </Box>\n+ await controls.start('isDeleting')\n+ }}\n+ >\n+ <Icon icon=\"close\" color=\"blue400\" />\n+ </motion.button>\n+ )\n )}\n+ </AnimatePresence>\n </td>\n <td className={cn(styles.deleteButtonContainer, styles.td)}>\n <Button\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts\nindex dc2debbae166d8f6e210a9d189d2e0ee39e19de7..e2c83dfbdf68616f2c065c9cef59d43d2a97c21a 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts\n@@ -89,14 +89,17 @@ export const td = style({\n },\n })\n \n+export const deleteButtonWrapper = style({\n+ margin: '0 auto',\n+ padding: 10,\n+ width: 44,\n+ height: 44,\n+})\n+\n export const deleteButton = style({\n display: 'flex',\n justifyContent: 'center',\n alignItems: 'center',\n- marginRight: 24,\n- padding: 10,\n- minWidth: 36,\n- minHeight: 36,\n borderRadius: theme.border.radius.circle,\n outline: 'none',\n transition: 'all .4s ease-out',\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx\nindex a21b159b0a8613c90fd44e87e841dc273194cc82..76c1ef4a4fed5684ac215c7dea13d3ecb24803f2 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx\n@@ -219,6 +219,14 @@ const mockPrisonUserCasesQuery = [\n },\n ]\n \n+jest.mock('next/router', () => ({\n+ useRouter() {\n+ return {\n+ pathname: '',\n+ }\n+ },\n+}))\n+\n describe('Cases', () => {\n describe('Prosecutor users', () => {\n test('should not display a button to delete a case that does not have a NEW or DRAFT or SUBMITTED or RECEIVED state', async () => {\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx\nindex 20f1e5e5bb9d60b6e1e960a0793a0fc710aad3fd..ce657814613c14c342f4ae2cdc3d716036782722 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx\n@@ -103,12 +103,8 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n const { user } = useContext(UserContext)\n const [isFiltering, setIsFiltering] = useState<boolean>(false)\n \n- const {\n- transitionCase,\n- isTransitioningCase,\n- isSendingNotification,\n- getCaseToOpen,\n- } = useCase()\n+ const { transitionCase, isTransitioningCase, isSendingNotification } =\n+ useCase()\n \n const { data, error, loading, refetch } = useQuery<{\n cases?: CaseListEntry[]\n@@ -170,10 +166,6 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n }\n }\n \n- const handleRowClick = (id: string) => {\n- getCaseToOpen(id)\n- }\n-\n return (\n <SharedPageLayout>\n <PageHeader title={formatMessage(titles.shared.cases)} />\n@@ -183,7 +175,6 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n <CreateCaseButton user={user} />\n ) : null}\n </div>\n-\n <Box marginBottom={[2, 5, 5]} className={styles.filterContainer}>\n <Select\n name=\"filter-cases\"\n@@ -196,7 +187,6 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n value={filter}\n />\n </Box>\n-\n {error ? (\n <div\n className={styles.infoContainer}\n@@ -217,7 +207,6 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n ) : activeCases.length > 0 ? (\n <ActiveCases\n cases={activeCases}\n- onRowClick={handleRowClick}\n isDeletingCase={isTransitioningCase || isSendingNotification}\n onDeleteCase={deleteCase}\n />\n@@ -238,7 +227,6 @@ export const Cases: React.FC<React.PropsWithChildren<unknown>> = () => {\n {loading || pastCases.length > 0 ? (\n <PastCasesTable\n cases={pastCases}\n- onRowClick={handleRowClick}\n loading={loading || isFiltering}\n testid=\"pastCasesTable\"\n />\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts b/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts\nindex 0dc23a343620c4250ccf760c06569d518f787230..9cef909c902fb27346e6a820f9894ff729a57baf 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts\n@@ -6,6 +6,7 @@ export const card = style({\n display: 'flex',\n position: 'relative',\n flexDirection: 'row',\n+ justifyContent: 'space-between',\n padding: `${theme.spacing[2]}px`,\n textAlign: 'left',\n backgroundColor: theme.color.white,\n@@ -20,3 +21,7 @@ export const card = style({\n borderColor: theme.color.blue400,\n },\n })\n+\n+export const loadingContainer = style({\n+ padding: `0 ${theme.spacing[1]}`,\n+})\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx b/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx\nindex ca705ae08fb705ce564c3a405b87711abde4f0f8..c6110d840f7106d88c953f1bfa3f8411c7482c1d 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx\n@@ -2,6 +2,7 @@ import React from 'react'\n import { useIntl } from 'react-intl'\n import format from 'date-fns/format'\n import parseISO from 'date-fns/parseISO'\n+import { AnimatePresence } from 'framer-motion'\n \n import { Box, FocusableBox, Text } from '@island.is/island-ui/core'\n import {\n@@ -11,6 +12,7 @@ import {\n import { tables } from '@island.is/judicial-system-web/messages'\n import TagCaseState from '@island.is/judicial-system-web/src/components/TagCaseState/TagCaseState'\n import { TempCaseListEntry as CaseListEntry } from '@island.is/judicial-system-web/src/types'\n+import useCaseList from '@island.is/judicial-system-web/src/utils/hooks/useCaseList'\n \n import { displayCaseType } from './utils'\n import * as styles from './MobileCase.css'\n@@ -19,20 +21,21 @@ interface CategoryCardProps {\n heading: string | React.ReactNode\n tags?: React.ReactNode\n onClick: () => void\n+ isLoading?: boolean\n }\n \n-const CategoryCard: React.FC<React.PropsWithChildren<CategoryCardProps>> = ({\n- heading,\n- onClick,\n- tags,\n- children,\n-}) => {\n+export const CategoryCard: React.FC<\n+ React.PropsWithChildren<CategoryCardProps>\n+> = ({ heading, onClick, tags, children, isLoading = false }) => {\n+ const { LoadingIndicator } = useCaseList()\n+\n return (\n <FocusableBox\n className={styles.card}\n height=\"full\"\n width=\"full\"\n component=\"button\"\n+ aria-disabled={isLoading}\n onClick={onClick}\n >\n <Box>\n@@ -42,6 +45,7 @@ const CategoryCard: React.FC<React.PropsWithChildren<CategoryCardProps>> = ({\n {children}\n <Box marginTop={3}>{tags}</Box>\n </Box>\n+ <AnimatePresence>{isLoading && <LoadingIndicator />}</AnimatePresence>\n </FocusableBox>\n )\n }\n@@ -50,6 +54,7 @@ interface Props {\n theCase: CaseListEntry\n onClick: () => void\n isCourtRole: boolean\n+ isLoading?: boolean\n }\n \n const MobileCase: React.FC<React.PropsWithChildren<Props>> = ({\n@@ -57,6 +62,7 @@ const MobileCase: React.FC<React.PropsWithChildren<Props>> = ({\n onClick,\n isCourtRole,\n children,\n+ isLoading = false,\n }) => {\n const { formatMessage } = useIntl()\n \n@@ -73,6 +79,7 @@ const MobileCase: React.FC<React.PropsWithChildren<Props>> = ({\n courtDate={theCase.courtDate}\n />,\n ]}\n+ isLoading={isLoading}\n >\n <Text title={theCase.policeCaseNumbers.join(', ')}>\n {displayFirstPlusRemaining(theCase.policeCaseNumbers)}\n\n<|file_patch|>apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx\ndiff --git a/apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx b/apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx\nindex bf955c5393f990662978673f01ff28c16993bc7d..31b47d136ee5b54974590b267859b3d9fbe75161 100644\n--- a/apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx\n+++ b/apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx\n@@ -15,7 +15,6 @@ import {\n } from '@island.is/judicial-system-web/src/components'\n import { InstitutionType } from '@island.is/judicial-system-web/src/graphql/schema'\n import { TempCaseListEntry as CaseListEntry } from '@island.is/judicial-system-web/src/types'\n-import { useCase } from '@island.is/judicial-system-web/src/utils/hooks'\n import { CasesQuery } from '@island.is/judicial-system-web/src/utils/mutations'\n \n import { cases as m } from './Cases.strings'\n@@ -27,8 +26,6 @@ export const PrisonCases: React.FC = () => {\n \n const isPrisonUser = user?.institution?.type === InstitutionType.PRISON\n \n- const { getCaseToOpen } = useCase()\n-\n const { data, error, loading } = useQuery<{\n cases?: CaseListEntry[]\n }>(CasesQuery, {\n@@ -47,10 +44,6 @@ export const PrisonCases: React.FC = () => {\n return partition(resCases, (c) => !c.isValidToDateInThePast)\n }, [resCases])\n \n- const handleRowClick = (id: string) => {\n- getCaseToOpen(id)\n- }\n-\n return (\n <SharedPageLayout>\n <PageHeader title={formatMessage(titles.shared.cases)} />\n@@ -80,11 +73,7 @@ export const PrisonCases: React.FC = () => {\n />\n <Box marginBottom={[5, 5, 12]}>\n {loading || !user || activeCases.length > 0 ? (\n- <PastCasesTable\n- cases={activeCases}\n- onRowClick={handleRowClick}\n- loading={loading}\n- />\n+ <PastCasesTable cases={activeCases} loading={loading} />\n ) : (\n <div className={styles.infoContainer}>\n <AlertMessage\n@@ -112,7 +101,6 @@ export const PrisonCases: React.FC = () => {\n {loading || pastCases.length > 0 ? (\n <PastCasesTable\n cases={pastCases}\n- onRowClick={handleRowClick}\n loading={loading}\n testid=\"pastCasesTable\"\n />\n\n<|file_patch|>apps/judicial-system/web/src/utils/hooks/useCase/index.ts\ndiff --git a/apps/judicial-system/web/src/utils/hooks/useCase/index.ts b/apps/judicial-system/web/src/utils/hooks/useCase/index.ts\nindex 05a2fdeb157cb5c8cb838f2a989fa820475f7953..0d60e430ffc28af90492fbee4ef0c597a66f42bc 100644\n--- a/apps/judicial-system/web/src/utils/hooks/useCase/index.ts\n+++ b/apps/judicial-system/web/src/utils/hooks/useCase/index.ts\n@@ -4,37 +4,22 @@ import formatISO from 'date-fns/formatISO'\n import isNil from 'lodash/isNil'\n import isUndefined from 'lodash/isUndefined'\n import omitBy from 'lodash/omitBy'\n-import router from 'next/router'\n import { useMutation } from '@apollo/client'\n \n import { toast } from '@island.is/island-ui/core'\n-import * as constants from '@island.is/judicial-system/consts'\n import {\n- CaseState,\n CaseTransition,\n- isDistrictCourtUser,\n- isIndictmentCase,\n- isInvestigationCase,\n- isRestrictionCase,\n NotificationType,\n SendNotificationResponse,\n } from '@island.is/judicial-system/types'\n import { errors } from '@island.is/judicial-system-web/messages'\n import { UserContext } from '@island.is/judicial-system-web/src/components'\n-import {\n- InstitutionType,\n- useCaseLazyQuery,\n- useLimitedAccessCaseLazyQuery,\n- User,\n-} from '@island.is/judicial-system-web/src/graphql/schema'\n import {\n TempCase as Case,\n TempCreateCase as CreateCase,\n TempUpdateCase as UpdateCase,\n } from '@island.is/judicial-system-web/src/types'\n \n-import { findFirstInvalidStep } from '../../formHelper'\n-import { isTrafficViolationCase } from '../../stepHelper'\n import {\n CreateCaseMutation,\n CreateCourtCaseMutation,\n@@ -179,72 +164,8 @@ export const formatDateForServer = (date: Date) => {\n return formatISO(date, { representation: 'complete' })\n }\n \n-const openCase = (caseToOpen: Case, user: User) => {\n- let routeTo = null\n- const isTrafficViolation = isTrafficViolationCase(caseToOpen)\n-\n- if (\n- caseToOpen.state === CaseState.ACCEPTED ||\n- caseToOpen.state === CaseState.REJECTED ||\n- caseToOpen.state === CaseState.DISMISSED\n- ) {\n- if (isIndictmentCase(caseToOpen.type)) {\n- routeTo = constants.CLOSED_INDICTMENT_OVERVIEW_ROUTE\n- } else if (user?.institution?.type === InstitutionType.COURT_OF_APPEALS) {\n- if (\n- findFirstInvalidStep(constants.courtOfAppealRoutes, caseToOpen) ===\n- constants.courtOfAppealRoutes[1]\n- ) {\n- routeTo = constants.COURT_OF_APPEAL_OVERVIEW_ROUTE\n- } else {\n- routeTo = findFirstInvalidStep(\n- constants.courtOfAppealRoutes,\n- caseToOpen,\n- )\n- }\n- } else {\n- routeTo = constants.SIGNED_VERDICT_OVERVIEW_ROUTE\n- }\n- } else if (isDistrictCourtUser(user)) {\n- if (isRestrictionCase(caseToOpen.type)) {\n- routeTo = findFirstInvalidStep(\n- constants.courtRestrictionCasesRoutes,\n- caseToOpen,\n- )\n- } else if (isInvestigationCase(caseToOpen.type)) {\n- routeTo = findFirstInvalidStep(\n- constants.courtInvestigationCasesRoutes,\n- caseToOpen,\n- )\n- } else {\n- // Route to Indictment Overview section since it always a valid step and\n- // would be skipped if we route to the last valid step\n- routeTo = constants.INDICTMENTS_COURT_OVERVIEW_ROUTE\n- }\n- } else {\n- if (isRestrictionCase(caseToOpen.type)) {\n- routeTo = findFirstInvalidStep(\n- constants.prosecutorRestrictionCasesRoutes,\n- caseToOpen,\n- )\n- } else if (isInvestigationCase(caseToOpen.type)) {\n- routeTo = findFirstInvalidStep(\n- constants.prosecutorInvestigationCasesRoutes,\n- caseToOpen,\n- )\n- } else {\n- routeTo = findFirstInvalidStep(\n- constants.prosecutorIndictmentRoutes(isTrafficViolation),\n- caseToOpen,\n- )\n- }\n- }\n-\n- if (routeTo) router.push(`${routeTo}/${caseToOpen.id}`)\n-}\n-\n const useCase = () => {\n- const { limitedAccess, user } = useContext(UserContext)\n+ const { limitedAccess } = useContext(UserContext)\n const { formatMessage } = useIntl()\n \n const [createCaseMutation, { loading: isCreatingCase }] =\n@@ -285,38 +206,6 @@ const useCase = () => {\n const [extendCaseMutation, { loading: isExtendingCase }] =\n useMutation<ExtendCaseMutationResponse>(ExtendCaseMutation)\n \n- const [getLimitedAccessCase] = useLimitedAccessCaseLazyQuery({\n- fetchPolicy: 'no-cache',\n- errorPolicy: 'all',\n- onCompleted: (limitedAccessCaseData) => {\n- if (user && limitedAccessCaseData?.limitedAccessCase) {\n- openCase(limitedAccessCaseData.limitedAccessCase as Case, user)\n- }\n- },\n- onError: () => {\n- toast.error(formatMessage(errors.getCaseToOpen))\n- },\n- })\n-\n- const [getCase] = useCaseLazyQuery({\n- fetchPolicy: 'no-cache',\n- errorPolicy: 'all',\n- onCompleted: (caseData) => {\n- if (user && caseData?.case) {\n- openCase(caseData.case as Case, user)\n- }\n- },\n- onError: () => {\n- toast.error(formatMessage(errors.getCaseToOpen))\n- },\n- })\n-\n- const getCaseToOpen = (id: string) => {\n- limitedAccess\n- ? getLimitedAccessCase({ variables: { input: { id } } })\n- : getCase({ variables: { input: { id } } })\n- }\n-\n const createCase = useMemo(\n () =>\n async (theCase: CreateCase): Promise<Case | undefined> => {\n@@ -567,7 +456,6 @@ const useCase = () => {\n extendCase,\n isExtendingCase,\n setAndSendCaseToServer,\n- getCaseToOpen,\n }\n }\n \n\n<|file_patch|>apps/judicial-system/web/src/utils/hooks/useCaseList/index.tsx\ndiff --git a/apps/judicial-system/web/src/utils/hooks/useCaseList/index.tsx b/apps/judicial-system/web/src/utils/hooks/useCaseList/index.tsx\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..da368ac3b5deeeab1e4e95d2f063531f4b8a4449\n--- /dev/null\n+++ b/apps/judicial-system/web/src/utils/hooks/useCaseList/index.tsx\n@@ -0,0 +1,200 @@\n+import React, { useCallback, useContext, useMemo, useState } from 'react'\n+import { useIntl } from 'react-intl'\n+import { motion } from 'framer-motion'\n+import { useRouter } from 'next/router'\n+\n+import { LoadingDots, toast } from '@island.is/island-ui/core'\n+import { theme } from '@island.is/island-ui/theme'\n+import * as constants from '@island.is/judicial-system/consts'\n+import {\n+ CaseState,\n+ InstitutionType,\n+ isDistrictCourtUser,\n+ isIndictmentCase,\n+ isInvestigationCase,\n+ isRestrictionCase,\n+} from '@island.is/judicial-system/types'\n+import { errors } from '@island.is/judicial-system-web/messages'\n+import { UserContext } from '@island.is/judicial-system-web/src/components'\n+import {\n+ useCaseLazyQuery,\n+ useLimitedAccessCaseLazyQuery,\n+ User,\n+} from '@island.is/judicial-system-web/src/graphql/schema'\n+import { TempCase as Case } from '@island.is/judicial-system-web/src/types'\n+\n+import { findFirstInvalidStep } from '../../formHelper'\n+import { isTrafficViolationCase } from '../../stepHelper'\n+import useCase from '../useCase'\n+\n+const useCaseList = () => {\n+ const timeouts = useMemo<NodeJS.Timeout[]>(() => [], [])\n+ // The id of the case that's about to be opened\n+ const [clickedCase, setClickedCase] = useState<\n+ [id: string | null, showLoading: boolean]\n+ >([null, false])\n+\n+ const { user, limitedAccess } = useContext(UserContext)\n+ const { formatMessage } = useIntl()\n+ const { isTransitioningCase, isSendingNotification } = useCase()\n+ const router = useRouter()\n+\n+ const [getLimitedAccessCase] = useLimitedAccessCaseLazyQuery({\n+ fetchPolicy: 'no-cache',\n+ errorPolicy: 'all',\n+ onCompleted: (limitedAccessCaseData) => {\n+ if (user && limitedAccessCaseData?.limitedAccessCase) {\n+ openCase(limitedAccessCaseData.limitedAccessCase as Case, user)\n+ }\n+ },\n+ onError: () => {\n+ toast.error(formatMessage(errors.getCaseToOpen))\n+ },\n+ })\n+\n+ const [getCase] = useCaseLazyQuery({\n+ fetchPolicy: 'no-cache',\n+ errorPolicy: 'all',\n+ onCompleted: (caseData) => {\n+ if (user && caseData?.case) {\n+ openCase(caseData.case as Case, user)\n+ }\n+ },\n+ onError: () => {\n+ toast.error(formatMessage(errors.getCaseToOpen))\n+ },\n+ })\n+\n+ const openCase = (caseToOpen: Case, user: User) => {\n+ let routeTo = null\n+ const isTrafficViolation = isTrafficViolationCase(caseToOpen)\n+\n+ if (\n+ caseToOpen.state === CaseState.ACCEPTED ||\n+ caseToOpen.state === CaseState.REJECTED ||\n+ caseToOpen.state === CaseState.DISMISSED\n+ ) {\n+ if (isIndictmentCase(caseToOpen.type)) {\n+ routeTo = constants.CLOSED_INDICTMENT_OVERVIEW_ROUTE\n+ } else if (user?.institution?.type === InstitutionType.COURT_OF_APPEALS) {\n+ if (\n+ findFirstInvalidStep(constants.courtOfAppealRoutes, caseToOpen) ===\n+ constants.courtOfAppealRoutes[1]\n+ ) {\n+ routeTo = constants.COURT_OF_APPEAL_OVERVIEW_ROUTE\n+ } else {\n+ routeTo = findFirstInvalidStep(\n+ constants.courtOfAppealRoutes,\n+ caseToOpen,\n+ )\n+ }\n+ } else {\n+ routeTo = constants.SIGNED_VERDICT_OVERVIEW_ROUTE\n+ }\n+ } else if (isDistrictCourtUser(user)) {\n+ if (isRestrictionCase(caseToOpen.type)) {\n+ routeTo = findFirstInvalidStep(\n+ constants.courtRestrictionCasesRoutes,\n+ caseToOpen,\n+ )\n+ } else if (isInvestigationCase(caseToOpen.type)) {\n+ routeTo = findFirstInvalidStep(\n+ constants.courtInvestigationCasesRoutes,\n+ caseToOpen,\n+ )\n+ } else {\n+ // Route to Indictment Overview section since it always a valid step and\n+ // would be skipped if we route to the last valid step\n+ routeTo = constants.INDICTMENTS_COURT_OVERVIEW_ROUTE\n+ }\n+ } else {\n+ if (isRestrictionCase(caseToOpen.type)) {\n+ routeTo = findFirstInvalidStep(\n+ constants.prosecutorRestrictionCasesRoutes,\n+ caseToOpen,\n+ )\n+ } else if (isInvestigationCase(caseToOpen.type)) {\n+ routeTo = findFirstInvalidStep(\n+ constants.prosecutorInvestigationCasesRoutes,\n+ caseToOpen,\n+ )\n+ } else {\n+ routeTo = findFirstInvalidStep(\n+ constants.prosecutorIndictmentRoutes(isTrafficViolation),\n+ caseToOpen,\n+ )\n+ }\n+ }\n+\n+ if (routeTo) router.push(`${routeTo}/${caseToOpen.id}`)\n+ }\n+\n+ const handleOpenCase = useCallback(\n+ (id: string) => {\n+ Promise.all(timeouts.map((timeout) => clearTimeout(timeout)))\n+\n+ setClickedCase([id, false])\n+\n+ timeouts.push(\n+ setTimeout(() => {\n+ setClickedCase([id, true])\n+ }, 2000),\n+ )\n+\n+ const getCaseToOpen = (id: string) => {\n+ limitedAccess\n+ ? getLimitedAccessCase({ variables: { input: { id } } })\n+ : getCase({ variables: { input: { id } } })\n+ }\n+\n+ if (\n+ isTransitioningCase ||\n+ isSendingNotification ||\n+ clickedCase[0] === id ||\n+ !user?.role\n+ ) {\n+ return\n+ }\n+\n+ getCaseToOpen(id)\n+ },\n+ [\n+ clickedCase,\n+ getCase,\n+ getLimitedAccessCase,\n+ isSendingNotification,\n+ isTransitioningCase,\n+ limitedAccess,\n+ timeouts,\n+ user?.role,\n+ ],\n+ )\n+\n+ const LoadingIndicator = () => {\n+ return (\n+ <motion.div\n+ key={`${clickedCase[0]}-loading`}\n+ initial={{ opacity: 0 }}\n+ animate={{ opacity: 1 }}\n+ exit={{ opacity: 0 }}\n+ style={{\n+ display: 'flex',\n+ alignItems: 'center',\n+ justifyContent: 'center',\n+ height: theme.spacing[3],\n+ }}\n+ >\n+ <LoadingDots single />\n+ </motion.div>\n+ )\n+ }\n+\n+ return {\n+ isOpeningCaseId: clickedCase[0],\n+ showLoading: clickedCase[1],\n+ handleOpenCase,\n+ LoadingIndicator,\n+ }\n+}\n+\n+export default useCaseList\n\n"},"target_character_start":{"kind":"number","value":578,"string":"578"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-07"},"utf8_bytes":{"kind":"number","value":45441,"string":"45,441"},"document_order_key":{"kind":"number","value":2945863165424604700,"string":"2,945,863,165,424,604,700"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/14islands/island.is"},"quality_band":{"kind":"string","value":"07"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"typescript"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/14islands/island.is\",\"commit_oid\":\"e39aea94fb9144bb080e3f1082e523fb05cb5861\",\"commits_ago_from_head\":4212,\"content_sha256\":\"d74a1429c1e10122a381e1e35183c77f5c6b6b1518272e9e672ca3eef4a0db10\",\"manifest_sha256\":null,\"parent_oid\":\"5288a2cd500fe0ae44caf99ef81e85f3f0665785\",\"repository_id\":\"github.com/14islands/island.is\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"07\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"candidate_cap_rungs_exceeded\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":7},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#13109\"],\"message_words\":79,\"scope\":\"j-s\",\"subject_length\":48,\"trailer_names\":[\"Co-authored-by\"],\"type\":\"chore\"},\"patch_statistics\":{\"added_lines\":332,\"context_bytes\":88703,\"deleted_lines\":263,\"files_changed\":18,\"hunk_count\":61,\"patch_bytes\":43363,\"patch_sha256\":\"0a20c1548905a68fc763616182382e0d58a68e9c60a80f3691fd02ded0c11d6d\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/AppealCasesTable/AppealCasesTable.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/AppealCasesTable/MobileAppealCase.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.css.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/CategoryCard/CategoryCard.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/PastCasesTable/MobilePastCase.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/PastCasesTable/PastCasesTable.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/Table.css.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/components/Table/index.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/CourtOfAppeal/Cases/Cases.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/ActiveCases.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/Cases.css.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/Cases.spec.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/Cases.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.css.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/MobileCase.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/routes/Shared/Cases/PrisonCases.tsx\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/utils/hooks/useCase/index.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"apps/judicial-system/web/src/utils/hooks/useCaseList/index.tsx\",\"purpose\":\"source\"}],\"primary_language\":\"typescript\"},\"quality_band\":\"07\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":88703,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":18,\"files_kept\":18,\"patch_bytes\":43363},\"commit_oid\":\"e39aea94fb9144bb080e3f1082e523fb05cb5861\",\"identity\":{\"author_email\":\"ivaroddsson@gmail.com\",\"author_name\":\"Ívar Oddsson\",\"authored_at\":\"2023-12-19T11:32:09+00:00\",\"commit_oid\":\"e39aea94fb9144bb080e3f1082e523fb05cb5861\",\"commits_ago_from_head\":4212,\"committed_at\":\"2023-12-19T11:32:09+00:00\",\"committer_email\":\"noreply@github.com\",\"committer_name\":\"GitHub\",\"parent_oid\":\"5288a2cd500fe0ae44caf99ef81e85f3f0665785\",\"tree_oid\":\"93f0385e88853ed5fc1e8eedb50f9d1864c3ff20\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"d6d7839e9f7e820452f6f6b96ea20a55df327a37\",\"oldest_commit\":\"95006b57bed9ae6996f434752c0a1d05fb4c63b4\"},\"recorded_head_commit\":\"d6d7839e9f7e820452f6f6b96ea20a55df327a37\",\"repository_id\":\"github.com/14islands/island.is\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/14islands/island.is\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":559,\"manifest_sha256\":null,\"split\":\"15-of-16\"}},\"parents\":[\"commit:github.com/14islands/island.is@e39aea94fb9144bb080e3f1082e523fb05cb5861__download_changed_file_contents_07b867e7b201__render_commit_patches_56e6e3e9effb\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16060,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/beakerbrowser/js-ipfs-api@2ae09fb28a178a36ab4b5be7cba63f06cf35c15b"},"text":{"kind":"string","value":"<|commit_message|>\nfeat(util): add fsAdd, streamAdd and urlAdd\n\n<|file_patch|>README.md\ndiff --git a/README.md b/README.md\nindex abec73a0358e5e0fa43fc1110222549d068fffa8..516b7bde38b2de4cbd945ff76a1f841ee1c7a81d 100644\n--- a/README.md\n+++ b/README.md\n@@ -116,11 +116,29 @@ Complete documentation for these methods is coming with: https://github.com/ipfs\n \n #### Add files or entire directories from the FileSystem to IPFS\n \n-> `ipfs.util.fsAdd(path, callback)`\n+> `ipfs.util.fsAdd(path, option, callback)`\n \n-Reads path from disk, if it is a directory, will add it recursively, if not, will add the file.\n+Reads path from disk (if directory add an options `{ recursive: true }` and adds it to IPFS.\n \n ```JavaScript\n+ipfs.util.fsAdd(<dirpath>, { recursive: true }, (err, result) => {\n+ if (err) {\n+ throw err\n+ }\n+ console.log(result)\n+})\n+```\n+\n+`files` is an array of objects describing the files that were added, such as:\n+\n+```\n+[{\n+ path: 'test-folder',\n+ hash: 'QmRNjDeKStKGTQXnJ2NFqeQ9oW23WcpbmvCVrpDHgDg3T6',\n+ size: 2278\n+},\n+// ...\n+]\n ```\n \n #### Add a file from a URL to IPFS\n@@ -128,6 +146,13 @@ Reads path from disk, if it is a directory, will add it recursively, if not, wil\n > `ipfs.util.urlAdd(url, callback)`\n \n ```JavaScript\n+ipfs.util.urlAdd('http://example.com/', (err, result) => {\n+ if (err) {\n+ throw err\n+ }\n+ console.log(result)\n+})\n+\n ```\n \n #### Add a file from a stream to IPFS\n@@ -137,6 +162,12 @@ Reads path from disk, if it is a directory, will add it recursively, if not, wil\n This is very similar to `ipfs.files.add({path:'', content: stream})`. It is like the reverse of cat\n \n ```JavaScript\n+ipfs.util.streamAdd(<readable-stream>, (err, result) => {\n+ if (err) {\n+ throw err\n+ }\n+ console.log(result)\n+})\n ```\n \n ### Callbacks and promises\n\n<|file_patch|>src/api/add-files.js\ndiff --git a/src/api/add-files.js b/src/api/add-files.js\ndeleted file mode 100644\nindex b9909be2993105161aa2dce1d7bf503dd058e597..0000000000000000000000000000000000000000\n--- a/src/api/add-files.js\n+++ /dev/null\n@@ -1,31 +0,0 @@\n-'use strict'\n-\n-const isNode = require('detect-node')\n-const addToDagNodesTransform = require('../add-to-dagnode-transform')\n-const promisify = require('promisify-es6')\n-\n-module.exports = (send) => {\n- return promisify((path, opts, callback) => {\n- if (typeof opts === 'function' &&\n- callback === undefined) {\n- callback = opts\n- opts = {}\n- }\n-\n- if (!isNode) {\n- return callback(new Error('Recursive uploads are not supported in the browser'))\n- }\n-\n- if (typeof path !== 'string') {\n- return callback(new Error('\"path\" must be a string'))\n- }\n-\n- const sendWithTransform = send.withTransform(addToDagNodesTransform)\n-\n- sendWithTransform({\n- path: 'add',\n- qs: opts,\n- files: path\n- }, callback)\n- })\n-}\n\n<|file_patch|>src/api/add-stream.js\ndiff --git a/src/api/add-stream.js b/src/api/add-stream.js\ndeleted file mode 100644\nindex 8c40dd1cc05b8bf481dba01598847d228c04e08f..0000000000000000000000000000000000000000\n--- a/src/api/add-stream.js\n+++ /dev/null\n@@ -1,36 +0,0 @@\n-'use strict'\n-\n-const addCmd = require('./add.js')\n-const Duplex = require('stream').Duplex\n-const promisify = require('promisify-es6')\n-\n-module.exports = (send) => {\n- const add = addCmd(send)\n-\n- return promisify((callback) => {\n- const tuples = []\n-\n- const ds = new Duplex({ objectMode: true })\n- ds._read = (n) => {}\n-\n- ds._write = (file, enc, next) => {\n- tuples.push(file)\n- next()\n- }\n-\n- ds.end = () => {\n- add(tuples, (err, res) => {\n- if (err) {\n- return ds.emit('error', err)\n- }\n-\n- res.forEach((tuple) => {\n- ds.push(tuple)\n- })\n-\n- ds.push(null)\n- })\n- }\n- callback(null, ds)\n- })\n-}\n\n<|file_patch|>src/api/add-url.js\ndiff --git a/src/api/add-url.js b/src/api/add-url.js\ndeleted file mode 100644\nindex 11712f7d63794ebd26d1ec83daa12c18094b519e..0000000000000000000000000000000000000000\n--- a/src/api/add-url.js\n+++ /dev/null\n@@ -1,35 +0,0 @@\n-'use strict'\n-\n-const Wreck = require('wreck')\n-const addToDagNodesTransform = require('../add-to-dagnode-transform')\n-\n-const promisify = require('promisify-es6')\n-\n-module.exports = (send) => {\n- return promisify((url, opts, callback) => {\n- if (typeof (opts) === 'function' &&\n- callback === undefined) {\n- callback = opts\n- opts = {}\n- }\n-\n- if (typeof url !== 'string' ||\n- !url.startsWith('http')) {\n- return callback(new Error('\"url\" param must be an http(s) url'))\n- }\n-\n- const sendWithTransform = send.withTransform(addToDagNodesTransform)\n-\n- Wreck.request('GET', url, null, (err, res) => {\n- if (err) {\n- return callback(err)\n- }\n-\n- sendWithTransform({\n- path: 'add',\n- qs: opts,\n- files: res\n- }, callback)\n- })\n- })\n-}\n\n<|file_patch|>src/api/create-add-stream.js\ndiff --git a/src/api/create-add-stream.js b/src/api/create-add-stream.js\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..8c40dd1cc05b8bf481dba01598847d228c04e08f\n--- /dev/null\n+++ b/src/api/create-add-stream.js\n@@ -0,0 +1,36 @@\n+'use strict'\n+\n+const addCmd = require('./add.js')\n+const Duplex = require('stream').Duplex\n+const promisify = require('promisify-es6')\n+\n+module.exports = (send) => {\n+ const add = addCmd(send)\n+\n+ return promisify((callback) => {\n+ const tuples = []\n+\n+ const ds = new Duplex({ objectMode: true })\n+ ds._read = (n) => {}\n+\n+ ds._write = (file, enc, next) => {\n+ tuples.push(file)\n+ next()\n+ }\n+\n+ ds.end = () => {\n+ add(tuples, (err, res) => {\n+ if (err) {\n+ return ds.emit('error', err)\n+ }\n+\n+ res.forEach((tuple) => {\n+ ds.push(tuple)\n+ })\n+\n+ ds.push(null)\n+ })\n+ }\n+ callback(null, ds)\n+ })\n+}\n\n<|file_patch|>src/api/util/fs-add.js\ndiff --git a/src/api/util/fs-add.js b/src/api/util/fs-add.js\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c78dda13a17fcd5afdef519a95d2b4c0d88598e3\n--- /dev/null\n+++ b/src/api/util/fs-add.js\n@@ -0,0 +1,39 @@\n+'use strict'\n+\n+const isNode = require('detect-node')\n+const addToDagNodesTransform = require('./../../add-to-dagnode-transform')\n+const promisify = require('promisify-es6')\n+\n+module.exports = (send) => {\n+ return promisify((path, opts, callback) => {\n+ if (typeof opts === 'function' &&\n+ callback === undefined) {\n+ callback = opts\n+ opts = {}\n+ }\n+\n+ // opts is the real callback --\n+ // 'callback' is being injected by promisify\n+ if (typeof opts === 'function' &&\n+ typeof callback === 'function') {\n+ callback = opts\n+ opts = {}\n+ }\n+\n+ if (!isNode) {\n+ return callback(new Error('fsAdd does not work in the browser'))\n+ }\n+\n+ if (typeof path !== 'string') {\n+ return callback(new Error('\"path\" must be a string'))\n+ }\n+\n+ const sendWithTransform = send.withTransform(addToDagNodesTransform)\n+\n+ sendWithTransform({\n+ path: 'add',\n+ qs: opts,\n+ files: path\n+ }, callback)\n+ })\n+}\n\n<|file_patch|>src/api/util/url-add.js\ndiff --git a/src/api/util/url-add.js b/src/api/util/url-add.js\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..327a7bfc9b47333ce468551c694d7c8065369655\n--- /dev/null\n+++ b/src/api/util/url-add.js\n@@ -0,0 +1,44 @@\n+'use strict'\n+\n+const Wreck = require('wreck')\n+const addToDagNodesTransform = require('./../../add-to-dagnode-transform')\n+\n+const promisify = require('promisify-es6')\n+\n+module.exports = (send) => {\n+ return promisify((url, opts, callback) => {\n+ if (typeof (opts) === 'function' &&\n+ callback === undefined) {\n+ callback = opts\n+ opts = {}\n+ }\n+\n+ // opts is the real callback --\n+ // 'callback' is being injected by promisify\n+ if (typeof opts === 'function' &&\n+ typeof callback === 'function') {\n+ callback = opts\n+ opts = {}\n+ }\n+\n+ if (typeof url !== 'string' ||\n+ !url.startsWith('http')) {\n+ return callback(new Error('\"url\" param must be an http(s) url'))\n+ }\n+\n+ const sendWithTransform = send.withTransform(addToDagNodesTransform)\n+\n+ Wreck.request('GET', url, null, (err, res) => {\n+ if (err) {\n+ return callback(err)\n+ }\n+ console.log('got page back')\n+\n+ sendWithTransform({\n+ path: 'add',\n+ qs: opts,\n+ files: res\n+ }, callback)\n+ })\n+ })\n+}\n\n<|file_patch|>src/load-commands.js\ndiff --git a/src/load-commands.js b/src/load-commands.js\nindex ebd832de7c0d25c1bb87c4dd931ea94ebe4c22eb..724082ec510c9522263871bc1b158457e62be2ef 100644\n--- a/src/load-commands.js\n+++ b/src/load-commands.js\n@@ -2,8 +2,9 @@\n \n function requireCommands () {\n const cmds = {\n- add: require('./api/add'), // add alias\n- createAddStream: require('./api/add-stream'), // add stream alias\n+ // add and createAddStream alias\n+ add: require('./api/add'),\n+ createAddStream: require('./api/create-add-stream'),\n bitswap: require('./api/bitswap'),\n block: require('./api/block'),\n bootstrap: require('./api/bootstrap'),\n@@ -33,7 +34,7 @@ function requireCommands () {\n cmds.files = function (send) {\n const files = require('./api/files')(send)\n files.add = require('./api/add')(send)\n- files.createAddStream = require('./api/add-stream.js')(send)\n+ files.createAddStream = require('./api/create-add-stream.js')(send)\n files.get = require('./api/get')(send)\n \n // aliases\n@@ -46,8 +47,9 @@ function requireCommands () {\n \n cmds.util = function (send) {\n const util = {\n- addFiles: require('./api/add-files')(send),\n- addUrl: require('./api/add-url')(send)\n+ fsAdd: require('./api/util/fs-add')(send),\n+ streamAdd: require('./api/add')(send),\n+ urlAdd: require('./api/util/url-add')(send)\n }\n return util\n }\n\n<|file_patch|>test/ipfs-api/util.spec.js\ndiff --git a/test/ipfs-api/util.spec.js b/test/ipfs-api/util.spec.js\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b302694d768f506bbf5febb93c074830a783410b\n--- /dev/null\n+++ b/test/ipfs-api/util.spec.js\n@@ -0,0 +1,69 @@\n+/* eslint-env mocha */\n+/* eslint max-nested-callbacks: [\"error\", 8] */\n+'use strict'\n+\n+const expect = require('chai').expect\n+const isNode = require('detect-node')\n+const path = require('path')\n+const fs = require('fs')\n+const FactoryClient = require('../factory/factory-client')\n+\n+describe('.util', () => {\n+ if (!isNode) {\n+ return\n+ }\n+ let ipfs\n+ let fc\n+\n+ before(function (done) {\n+ this.timeout(20 * 1000) // slow CI\n+ fc = new FactoryClient()\n+ fc.spawnNode((err, node) => {\n+ expect(err).to.not.exist\n+ ipfs = node\n+ done()\n+ })\n+ })\n+\n+ after((done) => {\n+ fc.dismantle(done)\n+ })\n+\n+ it('.streamAdd', (done) => {\n+ const rs = fs.createReadStream(path.join(__dirname, '/../data/testfile.txt'))\n+ rs.path = '' // clean the path for testing purposes\n+\n+ ipfs.util.streamAdd(rs, (err, result) => {\n+ expect(err).to.not.exist\n+ expect(result.length).to.equal(1)\n+ done()\n+ })\n+ })\n+\n+ it('.fsAdd a directory', (done) => {\n+ const filesPath = path.join(__dirname, '../data/test-folder')\n+ ipfs.util.fsAdd(filesPath, { recursive: true }, (err, result) => {\n+ expect(err).to.not.exist\n+ expect(result.length).to.be.above(8)\n+ done()\n+ })\n+ })\n+\n+ it('.fsAdd a file', (done) => {\n+ const filePath = path.join(__dirname, '../data/testfile.txt')\n+ ipfs.util.fsAdd(filePath, (err, result) => {\n+ expect(err).to.not.exist\n+ expect(result.length).to.be.above(5)\n+\n+ done()\n+ })\n+ })\n+\n+ it('.urlAdd', (done) => {\n+ ipfs.util.urlAdd('http://example.com/', (err, result) => {\n+ expect(err).to.not.exist\n+ expect(result.length).to.equal(1)\n+ done()\n+ })\n+ })\n+})\n\n"},"target_character_start":{"kind":"number","value":64,"string":"64"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-05"},"utf8_bytes":{"kind":"number","value":11942,"string":"11,942"},"document_order_key":{"kind":"number","value":2946005771271003600,"string":"2,946,005,771,271,003,600"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/beakerbrowser/js-ipfs-api"},"quality_band":{"kind":"string","value":"05"},"tests_touched":{"kind":"bool","value":true,"string":"true"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"javascript"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/beakerbrowser/js-ipfs-api\",\"commit_oid\":\"2ae09fb28a178a36ab4b5be7cba63f06cf35c15b\",\"commits_ago_from_head\":147,\"content_sha256\":\"33db1a873dcc64ff8b3d46881d5dcc53e701350d1d741ff4bed107464a6c6455\",\"manifest_sha256\":null,\"parent_oid\":\"4cffb47bef83d1ab16dc4e3da51af664f2ca124a\",\"repository_id\":\"github.com/beakerbrowser/js-ipfs-api\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"05\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":5},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":6,\"scope\":\"util\",\"subject_length\":31,\"trailer_names\":[],\"type\":\"feat\"},\"patch_statistics\":{\"added_lines\":228,\"context_bytes\":12228,\"deleted_lines\":109,\"files_changed\":9,\"hunk_count\":13,\"patch_bytes\":11547,\"patch_sha256\":\"20b3fa576d5017d55290a6d7971609f361c987fca5d53a82d2141777d69743c7\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"markdown\",\"path\":\"README.md\",\"purpose\":\"docs\"},{\"language\":\"javascript\",\"path\":\"src/api/add-files.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/api/add-stream.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/api/add-url.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/api/create-add-stream.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/api/util/fs-add.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/api/util/url-add.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"src/load-commands.js\",\"purpose\":\"source\"},{\"language\":\"javascript\",\"path\":\"test/ipfs-api/util.spec.js\",\"purpose\":\"tests\"}],\"primary_language\":\"javascript\"},\"quality_band\":\"05\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[\"test/ipfs-api/util.spec.js\"],\"touched\":true},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":12228,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":9,\"files_kept\":9,\"patch_bytes\":11547},\"commit_oid\":\"2ae09fb28a178a36ab4b5be7cba63f06cf35c15b\",\"identity\":{\"author_email\":\"daviddias.p@gmail.com\",\"author_name\":\"David Dias\",\"authored_at\":\"2016-08-17T15:12:04+01:00\",\"commit_oid\":\"2ae09fb28a178a36ab4b5be7cba63f06cf35c15b\",\"commits_ago_from_head\":147,\"committed_at\":\"2016-08-17T15:32:40+01:00\",\"committer_email\":\"daviddias.p@gmail.com\",\"committer_name\":\"David Dias\",\"parent_oid\":\"4cffb47bef83d1ab16dc4e3da51af664f2ca124a\",\"tree_oid\":\"80640e8adf3645cc8290d848d42932093743ee5f\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":848,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"d7b40ea4f95f6ae32d5edbd5f8df08beea99b8d5\",\"oldest_commit\":\"cdd4f397ddfcae87a68b44080758470a7c1e77b0\"},\"recorded_head_commit\":\"d7b40ea4f95f6ae32d5edbd5f8df08beea99b8d5\",\"repository_id\":\"github.com/beakerbrowser/js-ipfs-api\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/beakerbrowser/js-ipfs-api\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":66171,\"manifest_sha256\":null,\"split\":\"11-of-16\"}},\"parents\":[\"commit:github.com/beakerbrowser/js-ipfs-api@2ae09fb28a178a36ab4b5be7cba63f06cf35c15b__download_changed_file_contents_6fb6dd9a7eb1__render_commit_patches_42133f827fe7\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16061,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/bloomberg/lucene-solr@1c6508b2841f40e1379b5f4802ff90b3de541cf9"},"text":{"kind":"string","value":"<|commit_message|>\nSOLR-6231: Harden the RollingRestartTest\n\ngit-svn-id: https://svn.apache.org/repos/asf/lucene/dev/trunk@1612499 13f79535-47bb-0310-9956-ffa450edef68\n\n<|file_patch|>solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\ndiff --git a/solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java b/solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\nindex 3118bee4f5eb6bceb2e72c7e8290195c24d76312..0002fd03ec99a0f2bb372077952858709d2068c9 100644\n--- a/solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\n+++ b/solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\n@@ -32,6 +32,8 @@ import java.util.concurrent.TimeUnit;\n public class RollingRestartTest extends AbstractFullDistribZkTestBase {\n public static Logger log = LoggerFactory.getLogger(ChaosMonkeyNothingIsSafeTest.class);\n \n+ private static final long MAX_WAIT_TIME = TimeUnit.NANOSECONDS.convert(300, TimeUnit.SECONDS);\n+\n public RollingRestartTest() {\n fixShardCount = true;\n sliceCount = 2;\n@@ -83,7 +85,7 @@ public class RollingRestartTest extends AbstractFullDistribZkTestBase {\n overseerDesignates.add(cloudJettys.get(n));\n }\n \n- waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, 60);\n+ waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, MAX_WAIT_TIME);\n \n cloudClient.getZkStateReader().getZkClient().printLayoutToStdOut();\n \n@@ -93,18 +95,20 @@ public class RollingRestartTest extends AbstractFullDistribZkTestBase {\n for (CloudJettyRunner cloudJetty : overseerDesignates) {\n log.info(\"Restarting {}\", cloudJetty);\n chaosMonkey.stopJetty(cloudJetty);\n- boolean success = waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, 60);\n+ boolean success = waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, MAX_WAIT_TIME);\n if (!success) {\n leader = OverseerCollectionProcessor.getLeaderNode(cloudClient.getZkStateReader().getZkClient());\n- if(leader == null) log.error(\"NOOVERSEER election queue is :\"+ OverseerCollectionProcessor.getSortedElectionNodes(cloudClient.getZkStateReader().getZkClient()));\n+ if (leader == null)\n+ log.error(\"NOOVERSEER election queue is :\" + OverseerCollectionProcessor.getSortedElectionNodes(cloudClient.getZkStateReader().getZkClient()));\n fail(\"No overseer designate as leader found after restart #\" + (i + 1) + \": \" + leader);\n }\n- assertTrue(\"Unable to restart (#\"+i+\"): \" + cloudJetty, \n- chaosMonkey.start(cloudJetty.jetty));\n- success = waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, 60);\n+ assertTrue(\"Unable to restart (#\" + i + \"): \" + cloudJetty,\n+ ChaosMonkey.start(cloudJetty.jetty));\n+ success = waitUntilOverseerDesignateIsLeader(cloudClient.getZkStateReader().getZkClient(), designates, MAX_WAIT_TIME);\n if (!success) {\n leader = OverseerCollectionProcessor.getLeaderNode(cloudClient.getZkStateReader().getZkClient());\n- if(leader == null) log.error(\"NOOVERSEER election queue is :\"+ OverseerCollectionProcessor.getSortedElectionNodes(cloudClient.getZkStateReader().getZkClient()));\n+ if (leader == null)\n+ log.error(\"NOOVERSEER election queue is :\" + OverseerCollectionProcessor.getSortedElectionNodes(cloudClient.getZkStateReader().getZkClient()));\n fail(\"No overseer leader found after restart #\" + (i + 1) + \": \" + leader);\n }\n }\n@@ -117,24 +121,35 @@ public class RollingRestartTest extends AbstractFullDistribZkTestBase {\n cloudClient.getZkStateReader().getZkClient().printLayoutToStdOut();\n }\n \n- static boolean waitUntilOverseerDesignateIsLeader(SolrZkClient testZkClient, List<String> overseerDesignates, int timeoutInSeconds) throws KeeperException, InterruptedException {\n+ static boolean waitUntilOverseerDesignateIsLeader(SolrZkClient testZkClient, List<String> overseerDesignates, long timeoutInNanos) throws KeeperException, InterruptedException {\n long now = System.nanoTime();\n- long timeout = now + TimeUnit.NANOSECONDS.convert(timeoutInSeconds, TimeUnit.SECONDS);\n+ long maxTimeout = now + timeoutInNanos; // the maximum amount of time we're willing to wait to see the designate as leader\n+ long timeout = now + TimeUnit.NANOSECONDS.convert(60, TimeUnit.SECONDS);\n boolean firstTime = true;\n int stableCheckTimeout = 2000;\n- while (System.nanoTime() < timeout) {\n+ String oldleader = null;\n+ while (System.nanoTime() < timeout && System.nanoTime() < maxTimeout) {\n String newLeader = OverseerCollectionProcessor.getLeaderNode(testZkClient);\n+ if (newLeader != null && !newLeader.equals(oldleader)) {\n+ // the leaders have changed, let's move the timeout further\n+ timeout = System.nanoTime() + TimeUnit.NANOSECONDS.convert(60, TimeUnit.SECONDS);\n+ log.info(\"oldLeader={} newLeader={} - Advancing timeout to: {}\", oldleader, newLeader, timeout);\n+ oldleader = newLeader;\n+ }\n if (!overseerDesignates.contains(newLeader)) {\n Thread.sleep(500);\n } else {\n- if (firstTime) {\n+ if (firstTime) {\n firstTime = false;\n Thread.sleep(stableCheckTimeout);\n- } else {\n+ } else {\n return true;\n }\n }\n }\n+ if (System.nanoTime() < maxTimeout) {\n+ log.error(\"Max wait time exceeded\");\n+ }\n return false;\n }\n }\n\n"},"target_character_start":{"kind":"number","value":169,"string":"169"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-06"},"utf8_bytes":{"kind":"number","value":5661,"string":"5,661"},"document_order_key":{"kind":"number","value":2946087214190613000,"string":"2,946,087,214,190,613,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bloomberg/lucene-solr"},"quality_band":{"kind":"string","value":"06"},"tests_touched":{"kind":"bool","value":true,"string":"true"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"java"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bloomberg/lucene-solr\",\"commit_oid\":\"1c6508b2841f40e1379b5f4802ff90b3de541cf9\",\"commits_ago_from_head\":6946,\"content_sha256\":\"5ed8fda18e5ab13a5762f40f6aef47717db55020eeeb229fe8c3fcdbbfa3386b\",\"manifest_sha256\":null,\"parent_oid\":\"a265a8ab9c12af888dd7acd0c38f745230f5d847\",\"repository_id\":\"github.com/bloomberg/lucene-solr\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"06\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":6},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":7,\"scope\":null,\"subject_length\":40,\"trailer_names\":[\"git-svn-id\"],\"type\":null},\"patch_statistics\":{\"added_lines\":27,\"context_bytes\":5591,\"deleted_lines\":12,\"files_changed\":1,\"hunk_count\":4,\"patch_bytes\":5412,\"patch_sha256\":\"f0266980195ef5eca1969519eb241f65d7fc2a4676f6b5a04b4039a29fde7db8\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"java\",\"path\":\"solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\",\"purpose\":\"tests\"}],\"primary_language\":\"java\"},\"quality_band\":\"06\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[\"solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java\"],\"touched\":true},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":5591,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":5412},\"commit_oid\":\"1c6508b2841f40e1379b5f4802ff90b3de541cf9\",\"identity\":{\"author_email\":\"shalin@apache.org\",\"author_name\":\"Shalin Shekhar Mangar\",\"authored_at\":\"2014-07-22T08:01:39+00:00\",\"commit_oid\":\"1c6508b2841f40e1379b5f4802ff90b3de541cf9\",\"commits_ago_from_head\":6946,\"committed_at\":\"2014-07-22T08:01:39+00:00\",\"committer_email\":\"shalin@apache.org\",\"committer_name\":\"Shalin Shekhar Mangar\",\"parent_oid\":\"a265a8ab9c12af888dd7acd0c38f745230f5d847\",\"tree_oid\":\"f2c22699568d4a1bc532839d09c323f9c0818c38\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"37df64450ee25d48c83a0866ce20ae58d0459770\",\"oldest_commit\":\"cce0cbe5ff8986ede7bd5e64238554a133c71386\"},\"recorded_head_commit\":\"37df64450ee25d48c83a0866ce20ae58d0459770\",\"repository_id\":\"github.com/bloomberg/lucene-solr\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/bloomberg/lucene-solr\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":76048,\"manifest_sha256\":null,\"split\":\"00-of-16\"}},\"parents\":[\"commit:github.com/bloomberg/lucene-solr@1c6508b2841f40e1379b5f4802ff90b3de541cf9__download_changed_file_contents_7c99fa926eeb__render_commit_patches_ba48a0fd0d69\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16062,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/ansible/workshops@d2736ad8601a65646a1dfc896575f8ed1560502d"},"text":{"kind":"string","value":"<|commit_message|>\nRemoving ad hoc commands and replacing with playbooks\n\n<|file_patch|>exercises/ansible_rhel/1.3-playbook/README.md\ndiff --git a/exercises/ansible_rhel/1.3-playbook/README.md b/exercises/ansible_rhel/1.3-playbook/README.md\nindex b05d54588c24d0d859dd9628f08de46c13fbae4c..f8a72b6547d6c584b636ead466aa3f991fd68312 100644\n--- a/exercises/ansible_rhel/1.3-playbook/README.md\n+++ b/exercises/ansible_rhel/1.3-playbook/README.md\n@@ -18,21 +18,17 @@\n \n This exercise covers using Ansible to build two Apache web servers on Red Hat Enterprise Linux. This exercise covers the following Ansible fundamentals:\n \n-* Understanding Ansible Module parameters\n+* Understanding Ansible module parameters\n * Understanding and using the following modules\n * [yum module](https://docs.ansible.com/ansible/latest/modules/yum_module.html)\n * [service module](https://docs.ansible.com/ansible/latest/modules/service_module.html)\n * [copy module](https://docs.ansible.com/ansible/latest/modules/copy_module.html)\n-* Understanding [Idempotence](https://en.wikipedia.org/wiki/Idempotence) and how Ansible Modules can be idempotent\n+* Understanding [Idempotence](https://en.wikipedia.org/wiki/Idempotence) and how Ansible modules can be idempotent\n \n ## Guide\n \n-While Ansible ad hoc commands are useful for simple operations, they are not suited for complex configuration management or orchestration scenarios. For such use cases *playbooks* are the way to go.\n-\n Playbooks are files which describe the desired configurations or steps to implement on managed hosts. Playbooks can change lengthy, complex administrative tasks into easily repeatable routines with predictable and successful outcomes.\n \n-A playbook is where you can take some of those ad-hoc commands you just ran and put them into a repeatable set of *plays* and *tasks*.\n-\n A playbook can have multiple plays and a play can have one or multiple tasks. In a task a *module* is called, like the modules in the previous chapter. The goal of a *play* is to map a group of hosts. The goal of a *task* is to implement modules against those hosts.\n \n > **Tip**\n@@ -51,9 +47,9 @@ There are some important concepts:\n \n * **hosts**: the managed hosts to perform the tasks on\n \n-* **tasks**: the operations to be performed by invoking Ansible modules and passing them the necessary options.\n+* **tasks**: the operations to be performed by invoking Ansible modules and passing them the necessary options\n \n-* **become**: privilege escalation in Playbooks, same as using `-b` in the ad hoc command.\n+* **become**: privilege escalation in playbooks\n \n > **Warning**\n >\n@@ -67,7 +63,7 @@ A Playbook should be **idempotent**, so if a Playbook is run once to put the hos\n \n ### Step 2 - Creating a Directory Structure and File for your Playbook\n \n-Enough theory, it’s time to create your first Ansible Playbook. In this lab you create a playbook to set up an Apache web server in three steps:\n+Enough theory, it’s time to create your first Ansible playbook. In this lab you create a playbook to set up an Apache web server in three steps:\n \n 1. Install httpd package\n 2. Enable/start httpd service\n@@ -139,9 +135,9 @@ Save your playbook and exit your editor.\n \n ### Step 3 - Running the Playbook\n \n-With the introduction of Ansible Automation Platform 2, several new key components are being introduced as a part of the overall developer experience. Execution Environments have been introduced to provide predictable environments to be used during automation runtime. All collection dependencies are contained within the Execution Environment to ensure that automation created in development environments runs the same as in production environments.\n+With the introduction of Ansible Automation Platform 2, several new key components are being introduced as a part of the overall developer experience. Execution environments have been introduced to provide predictable environments to be used during automation runtime. All collection dependencies are contained within the execution environment to ensure that automation created in development environments runs the same as in production environments.\n \n-What do you find within an Execution Environment?\n+What do you find within an execution environment?\n \n * RHEL UBI 8\n * Ansible 2.9 or Ansible Core 2.11\n@@ -149,27 +145,27 @@ What do you find within an Execution Environment?\n * Any content Collections\n * Collection python or binary dependencies.\n \n-Why use Execution Environments?\n+Why use execution environments?\n \n They provide a standardized way to define, build and distribute the environments that the automation runs in. In a nutshell, Automation execution environments are container images that allow for easier administration of Ansible by the platform administrator.\n \n Considering the shift towards containerized execution of automation, automation development workflow and tooling that existed before Ansible Automation Platform 2 have had to be reimagined. In short, `ansible-navigator` replaces `ansible-playbook` and other `ansible-*` command line utilities.\n \n-With this change, Ansible Playbooks are executed using the `ansible-navigator` command on the control node.\n+With this change, Ansible playbooks are executed using the `ansible-navigator` command on the control node.\n \n The prerequisites and best practices for using `ansible-navigator` have been done for you within this lab.\n \n These include:\n * Installing the `ansible-navigator` package\n * Creating a default settings `/home/student<X>/.ansible-navigator.yml` for all your projects (optional)\n-* All Execution Environment (EE) logs are stored within `/home/student<X>/.ansible-navigator/logs/ansible-navigator.log`\n+* All execution environment (EE) logs are stored within `/home/student<X>/.ansible-navigator/logs/ansible-navigator.log`\n * Playbook artifacts are saved under `/tmp/artifact.json`\n \n-For more information on the [Ansible Navigator settings](https://github.com/ansible/ansible-navigator/blob/main/docs/settings.rst)\n+For more information on the [Ansible navigator settings](https://github.com/ansible/ansible-navigator/blob/main/docs/settings.rst)\n \n > **Tip**\n >\n-> The parameters for Ansible Navigator maybe modified for your specific environment. The current settings use a default `ansible-navigator.yml` for all projects, but a specific `ansible-navigator.yml` can be created for each project and is the recommended practice. \n+> The parameters for ansible-navigator maybe modified for your specific environment. The current settings use a default `ansible-navigator.yml` for all projects, but a specific `ansible-navigator.yml` can be created for each project and is the recommended practice. \n \n To run your playbook, use the `ansible-navigator run <playbook>` command as follows:\n \n@@ -220,46 +216,62 @@ Managed by Ansible\n Use the command `rpm -qi httpd` to verify httpd is installed:\n \n ```bash\n-[student<X>@node1 ~]$ rpm -qi httpd\n+[ec2-user@node1 ~]$ rpm -qi httpd\n Name : httpd\n Version : 2.4.37\n [...]\n ```\n \n-Log out of `node1` with the command `exit` so that you are back on the control host, and verify the installed package with an Ansible ad hoc command\\!\n+Log out of `node1` with the command `exit` so that you are back on the control host and verify the installed package with an Ansible playbook labeled package.yml\\!\n+\n+```yaml\n+---\n+- name: Check packages\n+ hosts: node1\n+ become: true\n+ vars:\n+ package: \"httpd\"\n+ \n+ tasks:\n+ - name: Gather the package facts\n+ ansible.builtin.package_facts:\n+ manager: auto\n+\n+ - name: Check whether a {{ package }} is installed\n+ ansible.builtin.debug:\n+ msg: \"{{ package }} {{ ansible_facts.packages[ package ][0].version }} is installed!\"\n+ when: \"package in ansible_facts.packages\"\n+\n+```\n \n ```bash\n-[student<X>@ansible-1 ansible-files]$ ansible node1 -m command -a 'rpm -qi httpd'\n+[student<X>@ansible-1 ~]$ ansible-navigator run package.yml -m stdout \n ```\n+\n ```bash\n-node1 | CHANGED | rc=0 >>\n-Name : httpd\n-Version : 2.4.37\n-Release : 39.module+el8.4.0+9658+b87b2deb\n-Architecture: x86_64\n-Install Date: Tue 27 Jul 2021 08:27:15 PM UTC\n-Group : System Environment/Daemons\n-Size : 4486208\n-License : ASL 2.0\n-Signature : RSA/SHA256, Mon 01 Feb 2021 07:24:18 PM UTC, Key ID 199e2f91fd431d51\n-Source RPM : httpd-2.4.37-39.module+el8.4.0+9658+b87b2deb.src.rpm\n-Build Date : Wed 27 Jan 2021 12:23:38 PM UTC\n-Build Host : x86-vm-07.build.eng.bos.redhat.com\n-Relocations : (not relocatable)\n-Packager : Red Hat, Inc. <http://bugzilla.redhat.com/bugzilla>\n-Vendor : Red Hat, Inc.\n-URL : https://httpd.apache.org/\n-Summary : Apache HTTP Server\n-Description :\n-The Apache HTTP Server is a powerful, efficient, and extensible\n-web server.\n+\n+PLAY [Check packages] **********************************************************\n+\n+TASK [Gathering Facts] *********************************************************\n+ok: [ansible]\n+\n+TASK [Gather the package facts] ************************************************\n+ok: [ansible]\n+\n+TASK [Check whether a httpd is installed] *************************************\n+ok: [ansible] => {\n+ \"msg\": \"httpd 2.4.37 is installed!\"\n+}\n+\n+PLAY RECAP *********************************************************************\n+ansible : ok=3 changed=0 unreachable=0 failed=0 skipped=0 rescued=0 ignored=0 \n ```\n \n-Run the Playbook a second time via the `ansible-navigator run apache.yml`, and compare the output. The output \"CHANGED\" now shows `0` instead of `1` and the color changed from yellow to green. This makes it easier to spot when changes have occured when running the Ansible playbook.\n+Run the the `ansible-navigator run apache.yml` playbook for a second time, and compare the output. The output \"CHANGED\" now shows `0` instead of `1` and the color changed from yellow to green. This makes it easier to spot when changes have occured when running the Ansible playbook.\n \n ### Step 4 - Extend your Playbook: Start & Enable Apache\n \n-The next part of the Ansible Playbook makes sure the Apache application is enabled and started on `node1`.\n+The next part of the Ansible playbook makes sure the Apache application is enabled and started on `node1`.\n \n On the control host, as your student user, edit the file `~/ansible-files/apache.yml` to add a second task using the `service` module. The Playbook should now look like this:\n \n@@ -290,27 +302,60 @@ What exactly did we do?\n Thus with the second task we make sure the Apache server is indeed running on the target machine. Run your extended Playbook:\n \n ```bash\n-[student<X>@ansible-1 ansible-files]$ ansible-navigator run apache.yml\n+[student<X>@ansible-1 ~]$ ansible-navigator run apache.yml\n ```\n \n Notice in the output, we see the play had `1` \"CHANGED\" shown in yellow and if we press `0` to enter the play output, you can see that task 2, \"Apache enabled and running\", was the task that incorporated the latest change by the \"CHANGED\" value being set to True and highlighted in yellow. \n \n \n+* Run the playbook a second time using `ansible-navigator` to get used to the change in the output.\n \n-* Use an Ansible ad hoc command again to make sure Apache has been enabled and started on `node1`, e.g. with: `systemctl status httpd`.\n+* Use an Ansible playbook labeled service_state.yml to make sure the Apache (httpd) service is running on `node1`, e.g. with: `systemctl status httpd`.\n \n-* Run the Playbook a second time using `ansible-navigator` to get used to the change in the output.\n+```yaml\n+---\n+- name: Check Status\n+ hosts: node1\n+ become: true\n+ vars:\n+ package: \"httpd\"\n+ \n+ tasks:\n+ - name: Check status of {{ package }} service\n+ service_facts:\n+ register: service_state\n+\n+ - debug:\n+ var: service_state.ansible_facts.services[\"{{ package }}.service\"].state\n+```\n+\n+```bash\n+[student<X>@ansible-1 ~]$ ansible-navigator run service_state.yml\n+```\n \n ### Step 5 - Extend your Playbook: Create an web.html\n \n-Check that the tasks were executed correctly and Apache is accepting connections: Make an HTTP request using Ansible’s `uri` module in an ad hoc command from the control node. Make sure to replace the **\\<IP\\>** with the IP for the `node1` from the inventory.\n+Check that the tasks were executed correctly and Apache is accepting connections: Make an HTTP request using Ansible’s `uri` module in a playbook named check_httpd.yml from the control node. Make sure to replace the **\\<IP\\>** with the IP for the `node1` from the inventory.\n+\n+```yaml\n+---\n+- name: Check URL\n+ hosts: control\n+ vars:\n+ IP: \"IP_OF_NODE1\"\n+ \n+ tasks:\n+ - name: Check that you can connect (GET) to a page and it returns a status 200\n+ uri:\n+ url: \"http://{{ IP }}\"\n+```\n \n > **Warning**\n >\n > **Expect a lot of red lines and a 403 status\\!**\n \n ```bash\n-[student<X>@ansible-1 ansible-files]$ ansible localhost -m uri -a \"url=http://<IP>\"\n+[student<X>@ansible-1 ~]$ ansible-navigator run check_httpd.yml -m stdout \n ```\n \n There are a lot of red lines and an error: As long as there is not at least an `web.html` file to be served by Apache, it will throw an ugly \"HTTP Error 403: Forbidden\" status and Ansible will report an error.\n@@ -359,12 +404,12 @@ What does this new copy task do? The new task uses the `copy` module and defines\n Run your extended Playbook:\n \n ```bash\n-[student<X>@ansible-1 ansible-files]$ ansible-navigator run apache.yml\n+[student<X>@ansible-1 ansible-files]$ ansible-navigator run apache.yml -m stdout\n ```\n \n * Have a good look at the output, notice the changes of \"CHANGED\" and the tasks associated with that change. \n \n-* Run the ad hoc command using the \"uri\" module from above again to test Apache. The command should now return a friendly green \"status: 200\" line, amongst other information.\n+* Run the Ansible playbook check_httpd.yml using the \"uri\" module from above again to test Apache. The command should now return a friendly green \"status: 200\" line, amongst other information.\n \n ### Step 6 - Practice: Apply to Multiple Host\n \n@@ -411,18 +456,14 @@ Change the playbook `hosts` parameter to point to `web` instead of `node1`:\n Now run the playbook:\n \n ```bash\n-[student<X>@ansible-1 ansible-files]$ ansible-navigator run apache.yml\n+[student<X>@ansible-1 ansible-files]$ ansible-navigator run apache.yml -m stdout\n ```\n \n-Verify if Apache is now running on all web servers (node1, node2, node3). Identify the IP addresses of the nodes in your inventory first, and afterwards use them each in the ad hoc command with the uri module as we already did with the `node1` above. All output should be green.\n-\n-> **Tip**\n->\n-> Alternatively, verify that Apache is running on all web servers use the command `ansible web -m uri -a \"url=http://localhost/\"`.\n+Verify if Apache is now running on all web servers (node1, node2, node3). All output should be green.\n \n ---\n **Navigation**\n <br>\n-[Previous Exercise](../1.2-adhoc) - [Next Exercise](../1.4-variables)\n+[Previous Exercise](../1.2-thebasics) - [Next Exercise](../1.4-variables)\n \n [Click here to return to the Ansible for Red Hat Enterprise Linux Workshop](../README.md#section-1---ansible-engine-exercises)\n\n"},"target_character_start":{"kind":"number","value":74,"string":"74"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-08"},"utf8_bytes":{"kind":"number","value":15258,"string":"15,258"},"document_order_key":{"kind":"number","value":2946323365074111000,"string":"2,946,323,365,074,111,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/ansible/workshops"},"quality_band":{"kind":"string","value":"08"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"markdown"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/ansible/workshops\",\"commit_oid\":\"d2736ad8601a65646a1dfc896575f8ed1560502d\",\"commits_ago_from_head\":2971,\"content_sha256\":\"22766b40452d6fade380d08c6236da0489cb3dfc6d9c3cb1c31a0f176d27739a\",\"manifest_sha256\":null,\"parent_oid\":\"7dd1b4f5f9bd0ea3a709e07499fc8eb9b5d4dd1b\",\"repository_id\":\"github.com/ansible/workshops\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"08\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":8},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":8,\"scope\":null,\"subject_length\":53,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":97,\"context_bytes\":19435,\"deleted_lines\":56,\"files_changed\":1,\"hunk_count\":9,\"patch_bytes\":15123,\"patch_sha256\":\"dd43f4345a9b4242d32608ad639210784c76fa2c5b4c081559cc36373656971b\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"markdown\",\"path\":\"exercises/ansible_rhel/1.3-playbook/README.md\",\"purpose\":\"docs\"}],\"primary_language\":\"markdown\"},\"quality_band\":\"08\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":19435,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":15123},\"commit_oid\":\"d2736ad8601a65646a1dfc896575f8ed1560502d\",\"identity\":{\"author_email\":\"rlopez@redhat.com\",\"author_name\":\"Roger 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\"Update jackson2-api to v2.19.0-404.vb_b_0fd2fea_e10\" (#10699)\n\nThe kubernetes client has issues with Jackson 2.19.0.\n\nOriginal pull request that updated to 2.19.0 was:\n\n* https://github.com/jenkinsci/jenkins/pull/10677\n\nReverted from the Jenkins plugin BOM in pull request:\n\n* https://github.com/jenkinsci/bom/pull/5114\n\nDistribution suspended from Jenkins update center in:\n\n* https://github.com/jenkins-infra/update-center2/pull/869\n\nRefer to the following Kubernetes client API issues:\n\n* https://github.com/fabric8io/kubernetes-client/issues/7036\n* https://github.com/fabric8io/kubernetes-client/issues/7106\n\nBackport of the Jackson 2.19.0 change to Kubernetes client 6.x has been requested at:\n\n* https://github.com/fabric8io/kubernetes-client/issues/7107\n\nAlso described in detail in Spring Cloud issue report:\n\n* https://github.com/spring-cloud/spring-cloud-kubernetes/issues/1923\n\nAlso described in Jenkins issue report:\n\n* https://issues.jenkins.io/browse/JENKINS-75712\n\nAlso verified as failing in kubernetes plugin pull request:\n\n* https://github.com/jenkinsci/kubernetes-plugin/pull/1702\n\nAlso mentioned in Kubernetes client API upgrade pull request:\n\n* https://github.com/jenkinsci/kubernetes-client-api-plugin/pull/292\n\nThis reverts commit 11e5d5c7a6f8cf1a0ef4ddd3ae90f233b330d5ec.\n<|file_patch|>.github/renovate.json\ndiff --git a/.github/renovate.json b/.github/renovate.json\nindex 69b1a7e0c312a9b2928529853026779bb7800338..4283f31d8b4848508f824d0248cc8cfc3af5cabf 100644\n--- a/.github/renovate.json\n+++ b/.github/renovate.json\n@@ -175,6 +175,16 @@\n ],\n \"depNameTemplate\": \"org.apache.maven.skins:maven-fluido-skin\",\n \"datasourceTemplate\": \"maven\"\n+ },\n+ {\n+ \"description\": \"Jackson 2.19.0 causes issues with Kubernetes client. See https://github.com/jenkinsci/bom/pull/5114\",\n+ \"matchManagers\": [\n+ \"maven\"\n+ ],\n+ \"allowedVersions\": \"<2.19.0\",\n+ \"matchPackageNames\": [\n+ \"org.jenkins-ci.plugins:jackson2-api\"\n+ ]\n }\n ],\n \"labels\": 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Launchy link\n\nCloses #497.\n<|file_patch|>_data/patterns.yml\ndiff --git a/_data/patterns.yml b/_data/patterns.yml\nindex bfec42e287e2c1433d078ba9a189fc9021344474..be13f79a3afd51cdf12292e8eeade1378d9efc33 100644\n--- a/_data/patterns.yml\n+++ b/_data/patterns.yml\n@@ -65,6 +65,8 @@\n title: \"The Incredible Accessible Modal Window, Version 3\"\n - url: \"http://codepen.io/scottohara/pen/lIdfv\"\n title: \"An accessible Modal Window with JavaScript & CSS\"\n+ - url: \"https://codepen.io/svinkle/pen/pjVepz\"\n+ title: \"Launchy: An Accessible Modal Window\"\n \n - pattern-category: Tables\n section-id: tables\n\n"},"target_character_start":{"kind":"number","value":52,"string":"52"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-07"},"utf8_bytes":{"kind":"number","value":643,"string":"643"},"document_order_key":{"kind":"number","value":2946562526503953000,"string":"2,946,562,526,503,953,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/a11yproject/a11yproject.com"},"quality_band":{"kind":"string","value":"07"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"yaml"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/a11yproject/a11yproject.com\",\"commit_oid\":\"0ababb5dba67ab23735b339ae4cce8dbf8885020\",\"commits_ago_from_head\":1640,\"content_sha256\":\"b0f3d029ba85b238969061b5889b0fa45f7a3e7258b38a89be7220596f034c7d\",\"manifest_sha256\":null,\"parent_oid\":\"0d2a9d7bb36d2e61483312f7b74fd4263aefe8a9\",\"repository_id\":\"github.com/a11yproject/a11yproject.com\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"07\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":7},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#497\"],\"message_words\":5,\"scope\":null,\"subject_length\":18,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":2,\"context_bytes\":3581,\"deleted_lines\":0,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":557,\"patch_sha256\":\"7d66b59304d093e4229286ee42cba5a7fb1fa2763f6a674e5dd35f14b807c4a8\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"yaml\",\"path\":\"_data/patterns.yml\",\"purpose\":\"config\"}],\"primary_language\":\"yaml\"},\"quality_band\":\"07\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":3581,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":557},\"commit_oid\":\"0ababb5dba67ab23735b339ae4cce8dbf8885020\",\"identity\":{\"author_email\":\"svinkle@users.noreply.github.com\",\"author_name\":\"Scott Vinkle\",\"authored_at\":\"2017-08-17T23:29:08-04:00\",\"commit_oid\":\"0ababb5dba67ab23735b339ae4cce8dbf8885020\",\"commits_ago_from_head\":1640,\"committed_at\":\"2017-08-17T23:29:08-04:00\",\"committer_email\":\"noreply@github.com\",\"committer_name\":\"GitHub\",\"parent_oid\":\"0d2a9d7bb36d2e61483312f7b74fd4263aefe8a9\",\"tree_oid\":\"c624304eb37f8f2ba7473d47850a988e7612ccba\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":2438,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"710f5a5bd48fe726f7adec67a47ea89efa003272\",\"oldest_commit\":\"fcb20f28b3f9f32e9234fcc063ae6f5649ae2a0b\"},\"recorded_head_commit\":\"710f5a5bd48fe726f7adec67a47ea89efa003272\",\"repository_id\":\"github.com/a11yproject/a11yproject.com\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/a11yproject/a11yproject.com\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":4206,\"manifest_sha256\":null,\"split\":\"14-of-16\"}},\"parents\":[\"commit:github.com/a11yproject/a11yproject.com@0ababb5dba67ab23735b339ae4cce8dbf8885020__download_changed_file_contents_05472882e0b6__render_commit_patches_961594e81634\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16065,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/alibaba/mongo@31716d2ae526d82d7d36464f6c9fae8b9f38542f"},"text":{"kind":"string","value":"<|commit_message|>\nSERVER-19855 Do not perform shard version checking where not necessary\n\nThe code in RangeDeleter and sharding migration and split uses\nAutoGetCollectionForRead, which has the side effect of checking for shard\nversion, based on the context. This causes problems in the cases where we\nare transmitting shard version information as part of the context, in\nparticular during the migration cases.\n\nThis change gets rid of these checks and replaces them with plain lock\nretrieval.\n\n<|file_patch|>src/mongo/db/db_raii.cpp\ndiff --git a/src/mongo/db/db_raii.cpp b/src/mongo/db/db_raii.cpp\nindex c7634052710f17197ca5febc0e1ae018b69f1bf1..a987062b11bcb68c89c7e719c04ed80e110d6f19 100644\n--- a/src/mongo/db/db_raii.cpp\n+++ b/src/mongo/db/db_raii.cpp\n@@ -32,6 +32,7 @@\n \n #include \"mongo/db/catalog/database_holder.h\"\n #include \"mongo/db/catalog/collection.h\"\n+#include \"mongo/db/catalog/database.h\"\n #include \"mongo/db/client.h\"\n #include \"mongo/db/curop.h\"\n #include \"mongo/db/repl/replication_coordinator_global.h\"\n@@ -43,6 +44,13 @@ namespace mongo {\n AutoGetDb::AutoGetDb(OperationContext* txn, StringData ns, LockMode mode)\n : _dbLock(txn->lockState(), ns, mode), _db(dbHolder().get(txn, ns)) {}\n \n+AutoGetCollection::AutoGetCollection(OperationContext* txn,\n+ const NamespaceString& nss,\n+ LockMode mode)\n+ : _autoDb(txn, nss.db(), mode),\n+ _collLock(txn->lockState(), nss.ns(), mode),\n+ _coll(_autoDb.getDb() ? _autoDb.getDb()->getCollection(nss) : nullptr) {}\n+\n AutoGetOrCreateDb::AutoGetOrCreateDb(OperationContext* txn, StringData ns, LockMode mode)\n : _transaction(txn, MODE_IX),\n _dbLock(txn->lockState(), ns, mode),\n@@ -60,48 +68,31 @@ AutoGetOrCreateDb::AutoGetOrCreateDb(OperationContext* txn, StringData ns, LockM\n }\n \n AutoGetCollectionForRead::AutoGetCollectionForRead(OperationContext* txn, const std::string& ns)\n- : _txn(txn),\n- _transaction(txn, MODE_IS),\n- _db(_txn, nsToDatabaseSubstring(ns), MODE_IS),\n- _collLock(_txn->lockState(), ns, MODE_IS),\n- _coll(NULL) {\n- _init(ns, nsToCollectionSubstring(ns));\n-}\n+ : AutoGetCollectionForRead(txn, NamespaceString(ns)) {}\n \n AutoGetCollectionForRead::AutoGetCollectionForRead(OperationContext* txn,\n const NamespaceString& nss)\n- : _txn(txn),\n- _transaction(txn, MODE_IS),\n- _db(_txn, nss.db(), MODE_IS),\n- _collLock(_txn->lockState(), nss.toString(), MODE_IS),\n- _coll(NULL) {\n- _init(nss.toString(), nss.coll());\n-}\n-\n-void AutoGetCollectionForRead::_init(const std::string& ns, StringData coll) {\n- massert(28535, \"need a non-empty collection name\", !coll.empty());\n-\n+ : _txn(txn), _transaction(txn, MODE_IS), _autoColl(txn, nss, MODE_IS) {\n // We have both the DB and collection locked, which the prerequisite to do a stable shard\n- // version check.\n- ensureShardVersionOKOrThrow(_txn, ns);\n+ // version check\n+ ensureShardVersionOKOrThrow(_txn, nss.ns());\n \n auto curOp = CurOp::get(_txn);\n stdx::lock_guard<Client> lk(*_txn->getClient());\n+\n // TODO: OldClientContext legacy, needs to be removed\n curOp->ensureStarted();\n- curOp->setNS_inlock(ns);\n+ curOp->setNS_inlock(nss.ns());\n \n // At this point, we are locked in shared mode for the database by the DB lock in the\n // constructor, so it is safe to load the DB pointer.\n- if (_db.getDb()) {\n+ if (_autoColl.getDb()) {\n // TODO: OldClientContext legacy, needs to be removed\n- curOp->enter_inlock(ns.c_str(), _db.getDb()->getProfilingLevel());\n-\n- _coll = _db.getDb()->getCollection(ns);\n+ curOp->enter_inlock(nss.ns().c_str(), _autoColl.getDb()->getProfilingLevel());\n }\n \n- if (_coll) {\n- if (auto minSnapshot = _coll->getMinimumVisibleSnapshot()) {\n+ if (getCollection()) {\n+ if (auto minSnapshot = getCollection()->getMinimumVisibleSnapshot()) {\n if (auto mySnapshot = _txn->recoveryUnit()->getMajorityCommittedSnapshot()) {\n while (mySnapshot < minSnapshot) {\n // Wait until a snapshot is available.\n\n<|file_patch|>src/mongo/db/db_raii.h\ndiff --git a/src/mongo/db/db_raii.h b/src/mongo/db/db_raii.h\nindex b37112cb26752744f444c573a56eb65b20c53abb..b6522caad2bcda19434d9872e8a676af2c3e5230 100644\n--- a/src/mongo/db/db_raii.h\n+++ b/src/mongo/db/db_raii.h\n@@ -45,7 +45,7 @@ class Collection;\n * RAII-style class, which acquires a lock on the specified database in the requested mode and\n * obtains a reference to the database. Used as a shortcut for calls to dbHolder().get().\n *\n- * It is guaranteed that locks will be released when this object goes out of scope, therefore\n+ * It is guaranteed that the lock will be released when this object goes out of scope, therefore\n * the database reference returned by this class should not be retained.\n */\n class AutoGetDb {\n@@ -63,6 +63,33 @@ private:\n Database* const _db;\n };\n \n+/**\n+ * RAII-style class, which acquires a locks on the specified database and collection in the\n+ * requested mode and obtains references to both.\n+ *\n+ * It is guaranteed that locks will be released when this object goes out of scope, therefore\n+ * the database and the collection references returned by this class should not be retained.\n+ */\n+class AutoGetCollection {\n+ MONGO_DISALLOW_COPYING(AutoGetCollection);\n+\n+public:\n+ AutoGetCollection(OperationContext* txn, const NamespaceString& nss, LockMode mode);\n+\n+ Database* getDb() const {\n+ return _autoDb.getDb();\n+ }\n+\n+ Collection* getCollection() const {\n+ return _coll;\n+ }\n+\n+private:\n+ const AutoGetDb _autoDb;\n+ const Lock::CollectionLock _collLock;\n+ Collection* const _coll;\n+};\n+\n /**\n * RAII-style class, which acquires a lock on the specified database in the requested mode and\n * obtains a reference to the database, creating it was non-existing. Used as a shortcut for\n@@ -100,7 +127,9 @@ private:\n \n /**\n * RAII-style class, which would acquire the appropritate hierarchy of locks for obtaining\n- * a particular collection and would retrieve a reference to the collection.\n+ * a particular collection and would retrieve a reference to the collection. In addition, this\n+ * utility validates the shard version for the specified namespace and sets the current operation's\n+ * namespace for the duration while this object is alive.\n *\n * It is guaranteed that locks will be released when this object goes out of scope, therefore\n * database and collection references returned by this class should not be retained.\n@@ -114,11 +143,11 @@ public:\n ~AutoGetCollectionForRead();\n \n Database* getDb() const {\n- return _db.getDb();\n+ return _autoColl.getDb();\n }\n \n Collection* getCollection() const {\n- return _coll;\n+ return _autoColl.getCollection();\n }\n \n private:\n@@ -127,10 +156,7 @@ private:\n const Timer _timer;\n OperationContext* const _txn;\n const ScopedTransaction _transaction;\n- const AutoGetDb _db;\n- const Lock::CollectionLock _collLock;\n-\n- Collection* _coll;\n+ const AutoGetCollection _autoColl;\n };\n \n /**\n\n<|file_patch|>src/mongo/db/namespace_string.h\ndiff --git a/src/mongo/db/namespace_string.h b/src/mongo/db/namespace_string.h\nindex 28037eb24b4c77b7141c6ce15f0006e64444f04e..9078fa2f7e4c8e4c3e10d08b5e3599590eef3938 100644\n--- a/src/mongo/db/namespace_string.h\n+++ b/src/mongo/db/namespace_string.h\n@@ -269,6 +269,10 @@ private:\n size_t _dotIndex;\n };\n \n+template <typename StreamType>\n+StreamType& operator<<(StreamType& stream, const NamespaceString& value) {\n+ return stream << value.ns();\n+}\n \n // \"database.a.b.c\" -> \"database\"\n inline StringData nsToDatabaseSubstring(StringData ns) {\n@@ -350,7 +354,7 @@ struct NamespaceDBEquals {\n return nsDBEquals(a, b);\n }\n };\n-}\n \n+} // namespace mongo\n \n #include \"mongo/db/namespace_string-inl.h\"\n\n<|file_patch|>src/mongo/db/range_deleter_db_env.cpp\ndiff --git a/src/mongo/db/range_deleter_db_env.cpp b/src/mongo/db/range_deleter_db_env.cpp\nindex b9971f54b039763ef4747e64dfd0f6adb1092384..35279d0e58bc4f071be35642b64feb56fb3918a0 100644\n--- a/src/mongo/db/range_deleter_db_env.cpp\n+++ b/src/mongo/db/range_deleter_db_env.cpp\n@@ -46,7 +46,6 @@\n \n namespace mongo {\n \n-using std::endl;\n using std::string;\n \n /**\n@@ -75,44 +74,43 @@ bool RangeDeleterDBEnv::deleteRange(OperationContext* txn,\n \n *deletedDocs = 0;\n ShardForceVersionOkModeBlock forceVersion(txn->getClient());\n- {\n- Helpers::RemoveSaver removeSaver(\"moveChunk\", ns, taskDetails.options.removeSaverReason);\n- Helpers::RemoveSaver* removeSaverPtr = NULL;\n- if (serverGlobalParams.moveParanoia && !taskDetails.options.removeSaverReason.empty()) {\n- removeSaverPtr = &removeSaver;\n- }\n \n- // log the opId so the user can use it to cancel the delete using killOp.\n- unsigned int opId = txn->getOpID();\n- log() << \"Deleter starting delete for: \" << ns << \" from \" << inclusiveLower << \" -> \"\n- << exclusiveUpper << \", with opId: \" << opId << endl;\n-\n- try {\n- *deletedDocs =\n- Helpers::removeRange(txn,\n- KeyRange(ns, inclusiveLower, exclusiveUpper, keyPattern),\n- false, /*maxInclusive*/\n- writeConcern,\n- removeSaverPtr,\n- fromMigrate,\n- onlyRemoveOrphans);\n-\n- if (*deletedDocs < 0) {\n- *errMsg = \"collection or index dropped before data could be cleaned\";\n- warning() << *errMsg << endl;\n-\n- return false;\n- }\n-\n- log() << \"rangeDeleter deleted \" << *deletedDocs << \" documents for \" << ns << \" from \"\n- << inclusiveLower << \" -> \" << exclusiveUpper << endl;\n- } catch (const DBException& ex) {\n- *errMsg = str::stream() << \"Error encountered while deleting range: \"\n- << \"ns\" << ns << \" from \" << inclusiveLower << \" -> \"\n- << exclusiveUpper << \", cause by:\" << causedBy(ex);\n+ Helpers::RemoveSaver removeSaver(\"moveChunk\", ns, taskDetails.options.removeSaverReason);\n+ Helpers::RemoveSaver* removeSaverPtr = NULL;\n+ if (serverGlobalParams.moveParanoia && !taskDetails.options.removeSaverReason.empty()) {\n+ removeSaverPtr = &removeSaver;\n+ }\n+\n+ // log the opId so the user can use it to cancel the delete using killOp.\n+ unsigned int opId = txn->getOpID();\n+ log() << \"Deleter starting delete for: \" << ns << \" from \" << inclusiveLower << \" -> \"\n+ << exclusiveUpper << \", with opId: \" << opId;\n+\n+ try {\n+ *deletedDocs =\n+ Helpers::removeRange(txn,\n+ KeyRange(ns, inclusiveLower, exclusiveUpper, keyPattern),\n+ false, /*maxInclusive*/\n+ writeConcern,\n+ removeSaverPtr,\n+ fromMigrate,\n+ onlyRemoveOrphans);\n+\n+ if (*deletedDocs < 0) {\n+ *errMsg = \"collection or index dropped before data could be cleaned\";\n+ warning() << *errMsg;\n \n return false;\n }\n+\n+ log() << \"rangeDeleter deleted \" << *deletedDocs << \" documents for \" << ns << \" from \"\n+ << inclusiveLower << \" -> \" << exclusiveUpper;\n+ } catch (const DBException& ex) {\n+ *errMsg = str::stream() << \"Error encountered while deleting range: \"\n+ << \"ns\" << ns << \" from \" << inclusiveLower << \" -> \"\n+ << exclusiveUpper << \", cause by:\" << causedBy(ex);\n+\n+ return false;\n }\n \n return true;\n@@ -121,12 +119,11 @@ bool RangeDeleterDBEnv::deleteRange(OperationContext* txn,\n void RangeDeleterDBEnv::getCursorIds(OperationContext* txn,\n StringData ns,\n std::set<CursorId>* openCursors) {\n- AutoGetCollectionForRead ctx(txn, ns.toString());\n- Collection* collection = ctx.getCollection();\n- if (!collection) {\n+ AutoGetCollection autoColl(txn, NamespaceString(ns), MODE_IS);\n+ if (!autoColl.getCollection())\n return;\n- }\n \n- collection->getCursorManager()->getCursorIds(openCursors);\n-}\n+ autoColl.getCollection()->getCursorManager()->getCursorIds(openCursors);\n }\n+\n+} // namespace mongo\n\n<|file_patch|>src/mongo/db/s/migration_source_manager.cpp\ndiff --git a/src/mongo/db/s/migration_source_manager.cpp b/src/mongo/db/s/migration_source_manager.cpp\nindex d2e61cc402af5ad16591a141414449b74361c6f7..34a978ae083d36ea772d9899a5eb9030fc911394 100644\n--- a/src/mongo/db/s/migration_source_manager.cpp\n+++ b/src/mongo/db/s/migration_source_manager.cpp\n@@ -180,7 +180,7 @@ bool MigrationSourceManager::start(OperationContext* txn,\n return false;\n }\n \n- _ns = ns;\n+ _nss = NamespaceString(ns);\n _min = min;\n _max = max;\n _shardKeyPattern = shardKeyPattern;\n@@ -242,7 +242,7 @@ void MigrationSourceManager::logOp(OperationContext* txn,\n if (!_active)\n return;\n \n- if (_ns != ns)\n+ if (_nss != ns)\n return;\n \n // no need to log if this is not an insertion, an update, or an actual deletion\n@@ -270,8 +270,8 @@ void MigrationSourceManager::logOp(OperationContext* txn,\n \n if (op == 'u') {\n BSONObj fullDoc;\n- OldClientContext ctx(txn, _ns, false);\n- if (!Helpers::findById(txn, ctx.db(), _ns.c_str(), idObj, fullDoc)) {\n+ OldClientContext ctx(txn, _nss.ns(), false);\n+ if (!Helpers::findById(txn, ctx.db(), _nss.ns().c_str(), idObj, fullDoc)) {\n warning() << \"logOpForSharding couldn't find: \" << idObj << \" even though should have\"\n << migrateLog;\n dassert(false); // TODO: Abort the migration.\n@@ -303,8 +303,8 @@ bool MigrationSourceManager::transferMods(OperationContext* txn,\n }\n \n // TODO: fix SERVER-16540 race\n- _xfer(txn, _ns, ctx.getDb(), &_deleted, b, \"deleted\", size, false);\n- _xfer(txn, _ns, ctx.getDb(), &_reload, b, \"reload\", size, true);\n+ _xfer(txn, _nss.ns(), ctx.getDb(), &_deleted, b, \"deleted\", size, false);\n+ _xfer(txn, _nss.ns(), ctx.getDb(), &_reload, b, \"reload\", size, true);\n }\n \n b.append(\"size\", size);\n@@ -316,9 +316,9 @@ bool MigrationSourceManager::storeCurrentLocs(OperationContext* txn,\n long long maxChunkSize,\n string& errmsg,\n BSONObjBuilder& result) {\n- AutoGetCollectionForRead ctx(txn, _getNS());\n+ AutoGetCollection autoColl(txn, _getNS(), MODE_IS);\n \n- Collection* collection = ctx.getCollection();\n+ Collection* collection = autoColl.getCollection();\n if (!collection) {\n errmsg = \"ns not found, should be impossible\";\n return false;\n@@ -333,7 +333,7 @@ bool MigrationSourceManager::storeCurrentLocs(OperationContext* txn,\n \n if (idx == NULL) {\n errmsg = str::stream() << \"can't find index with prefix \" << _shardKeyPattern\n- << \" in storeCurrentLocs for \" << _ns;\n+ << \" in storeCurrentLocs for \" << _nss;\n return false;\n }\n \n@@ -420,7 +420,7 @@ bool MigrationSourceManager::storeCurrentLocs(OperationContext* txn,\n << maxRecsWhenFull << \" , the maximum chunk size is \" << maxChunkSize\n << \" , average document size is \" << avgRecSize << \". Found \" << recCount\n << \" documents in chunk \"\n- << \" ns: \" << _ns << \" \" << _min << \" -> \" << _max << migrateLog;\n+ << \" ns: \" << _nss << \" \" << _min << \" -> \" << _max << migrateLog;\n \n result.appendBool(\"chunkTooBig\", true);\n result.appendNumber(\"estimatedChunkSize\", (long long)(recCount * avgRecSize));\n@@ -440,7 +440,7 @@ bool MigrationSourceManager::clone(OperationContext* txn, string& errmsg, BSONOb\n int allocSize = 0;\n \n {\n- AutoGetCollectionForRead ctx(txn, _getNS());\n+ AutoGetCollection autoColl(txn, _getNS(), MODE_IS);\n \n stdx::lock_guard<stdx::mutex> sl(_mutex);\n if (!_active) {\n@@ -448,9 +448,9 @@ bool MigrationSourceManager::clone(OperationContext* txn, string& errmsg, BSONOb\n return false;\n }\n \n- Collection* collection = ctx.getCollection();\n+ Collection* collection = autoColl.getCollection();\n if (!collection) {\n- errmsg = str::stream() << \"collection \" << _ns << \" does not exist\";\n+ errmsg = str::stream() << \"collection \" << _nss << \" does not exist\";\n return false;\n }\n \n@@ -462,7 +462,7 @@ bool MigrationSourceManager::clone(OperationContext* txn, string& errmsg, BSONOb\n bool isBufferFilled = false;\n BSONArrayBuilder clonedDocsArrayBuilder(allocSize);\n while (!isBufferFilled) {\n- AutoGetCollectionForRead ctx(txn, _getNS());\n+ AutoGetCollection autoColl(txn, _getNS(), MODE_IS);\n \n stdx::lock_guard<stdx::mutex> sl(_mutex);\n if (!_active) {\n@@ -471,9 +471,9 @@ bool MigrationSourceManager::clone(OperationContext* txn, string& errmsg, BSONOb\n }\n \n // TODO: fix SERVER-16540 race\n- Collection* collection = ctx.getCollection();\n+ Collection* collection = autoColl.getCollection();\n if (!collection) {\n- errmsg = str::stream() << \"collection \" << _ns << \" does not exist\";\n+ errmsg = str::stream() << \"collection \" << _nss << \" does not exist\";\n return false;\n }\n \n@@ -597,9 +597,9 @@ void MigrationSourceManager::_xfer(OperationContext* txn,\n arr.done();\n }\n \n-std::string MigrationSourceManager::_getNS() const {\n+NamespaceString MigrationSourceManager::_getNS() const {\n stdx::lock_guard<stdx::mutex> lk(_mutex);\n- return _ns;\n+ return _nss;\n }\n \n } // namespace mongo\n\n<|file_patch|>src/mongo/db/s/migration_source_manager.h\ndiff --git a/src/mongo/db/s/migration_source_manager.h b/src/mongo/db/s/migration_source_manager.h\nindex 0475e771fcdf125a4d7f235de25cee7e5273fe47..4921610332d3ee1b5cb08241ee2c92e76f6a8745 100644\n--- a/src/mongo/db/s/migration_source_manager.h\n+++ b/src/mongo/db/s/migration_source_manager.h\n@@ -34,6 +34,7 @@\n \n #include \"mongo/base/disallow_copying.h\"\n #include \"mongo/bson/bsonobj.h\"\n+#include \"mongo/db/namespace_string.h\"\n #include \"mongo/stdx/condition_variable.h\"\n \n namespace mongo {\n@@ -131,7 +132,7 @@ private:\n long long& size,\n bool explode);\n \n- std::string _getNS() const;\n+ NamespaceString _getNS() const;\n \n // All member variables are labeled with one of the following codes indicating the\n // synchronization rules for accessing them.\n@@ -166,7 +167,7 @@ private:\n // If a migration is currently active.\n bool _active{false}; // (MG)\n \n- std::string _ns; // (MG)\n+ NamespaceString _nss; // (MG)\n BSONObj _min; // (MG)\n BSONObj _max; // (MG)\n BSONObj _shardKeyPattern; // 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repository URL\n\n<|file_patch|>Readme.md\ndiff --git a/Readme.md b/Readme.md\nindex 072c6a8abf99aa263d83632ae2d24ea6e2af5959..abc7a06bd55881c494ce414b149116955166c074 100644\n--- a/Readme.md\n+++ b/Readme.md\n@@ -5,7 +5,7 @@\n Clone the repository, install needed gems and run Jekyll ;)\r\n \r\n ```bash\r\n-git clone git@github.com:mlocher/documentation.git\r\n+git clone git@github.com:codeship/documentation.git\r\n cd documentation\r\n bundle install\r\n bundle exec guard\r\n\n"},"target_character_start":{"kind":"number","value":42,"string":"42"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-08"},"utf8_bytes":{"kind":"number","value":484,"string":"484"},"document_order_key":{"kind":"number","value":2947099425834032000,"string":"2,947,099,425,834,032,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/apiaryio/documentation"},"quality_band":{"kind":"string","value":"08"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"markdown"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/apiaryio/documentation\",\"commit_oid\":\"7bbe8513ed00fe779d7874fe3052a539b9eeecf0\",\"commits_ago_from_head\":257,\"content_sha256\":\"9374b79c3d06d296af43e98644328987c1f4eb3de639e7b5bc73759a1e6284cd\",\"manifest_sha256\":null,\"parent_oid\":\"84dfdb144aeb027a4280210978bf9638fa12dac0\",\"repository_id\":\"github.com/apiaryio/documentation\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"08\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":2,\"reason\":\"throwaway_message\"},{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":8},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":3,\"scope\":null,\"subject_length\":21,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":1,\"context_bytes\":936,\"deleted_lines\":1,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":417,\"patch_sha256\":\"acc84e6aa07592e69ede4ad346a5a056ebe83e968ad6c26178c7e6768a424784\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"markdown\",\"path\":\"Readme.md\",\"purpose\":\"docs\"}],\"primary_language\":\"markdown\"},\"quality_band\":\"08\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":936,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":417},\"commit_oid\":\"7bbe8513ed00fe779d7874fe3052a539b9eeecf0\",\"identity\":{\"author_email\":\"marko@locher.at\",\"author_name\":\"Marko Locher\",\"authored_at\":\"2014-08-28T11:17:33+02:00\",\"commit_oid\":\"7bbe8513ed00fe779d7874fe3052a539b9eeecf0\",\"commits_ago_from_head\":257,\"committed_at\":\"2014-08-28T11:17:33+02:00\",\"committer_email\":\"marko@locher.at\",\"committer_name\":\"Marko Locher\",\"parent_oid\":\"84dfdb144aeb027a4280210978bf9638fa12dac0\",\"tree_oid\":\"32560daab9975aa0b21ab659e243c479c77e201d\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":287,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"10193c7e43d26397e6cc3cc049252e0abb3c564b\",\"oldest_commit\":\"91a3c4f443d0c45334960b98f863ba6f2588301e\"},\"recorded_head_commit\":\"10193c7e43d26397e6cc3cc049252e0abb3c564b\",\"repository_id\":\"github.com/apiaryio/documentation\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/apiaryio/documentation\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":38322,\"manifest_sha256\":null,\"split\":\"02-of-16\"}},\"parents\":[\"commit:github.com/apiaryio/documentation@7bbe8513ed00fe779d7874fe3052a539b9eeecf0__download_changed_file_contents_26e401ad2a61__render_commit_patches_1e0652d35a51\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16067,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/agilebits/golang-net@e354193b05bb6b1826eabcb5ef03f4e46175fd2e"},"text":{"kind":"string","value":"<|commit_message|>\nFix embarassing typo bug in ReadFrameHeader.\n\nThanks to Qi Zhao for the find.\n\nAdded new tests as penance.\n\n<|file_patch|>frame.go\ndiff --git a/frame.go b/frame.go\nindex 48bfdfbe0e6e8150ce736d57f20e50425513207d..345d571ecccd5caeca2ed7001fee16293f2fcf79 100644\n--- a/frame.go\n+++ b/frame.go\n@@ -239,7 +239,7 @@ func readFrameHeader(buf []byte, r io.Reader) (FrameHeader, error) {\n \t\treturn FrameHeader{}, err\n \t}\n \treturn FrameHeader{\n-\t\tLength: (uint32(buf[0])<<16 | uint32(buf[1])<<7 | uint32(buf[2])),\n+\t\tLength: (uint32(buf[0])<<16 | uint32(buf[1])<<8 | uint32(buf[2])),\n \t\tType: FrameType(buf[3]),\n \t\tFlags: Flags(buf[4]),\n \t\tStreamID: binary.BigEndian.Uint32(buf[5:]) & (1<<31 - 1),\n@@ -303,10 +303,15 @@ func (f *Framer) startWrite(ftype FrameType, flags Flags, streamID uint32) {\n \t\tbyte(streamID))\n }\n \n+var errFrameTooLarge = errors.New(\"http2: frame too large\")\n+\n func (f *Framer) endWrite() error {\n \t// Now that we know the final size, fill in the FrameHeader in\n \t// the space previously reserved for it. Abuse append.\n \tlength := len(f.wbuf) - frameHeaderLen\n+\tif length >= (1 << 24) {\n+\t\treturn errFrameTooLarge\n+\t}\n \t_ = append(f.wbuf[:0],\n \t\tbyte(length>>16),\n \t\tbyte(length>>8),\n@@ -319,6 +324,7 @@ func (f *Framer) endWrite() error {\n }\n \n func (f *Framer) writeByte(v byte) { f.wbuf = append(f.wbuf, v) }\n+func (f *Framer) writeBytes(v []byte) { f.wbuf = append(f.wbuf, v...) }\n func (f *Framer) writeUint16(v uint16) { f.wbuf = append(f.wbuf, byte(v>>8), byte(v)) }\n func (f *Framer) writeUint32(v uint32) {\n \tf.wbuf = append(f.wbuf, byte(v>>24), byte(v>>16), byte(v>>8), byte(v))\n\n<|file_patch|>frame_test.go\ndiff --git a/frame_test.go b/frame_test.go\nindex 832be02bd6fe6f6b683364963dc5a68e08f87003..01e6d578f6d6630bd6a7a3c92f8d03e8f95d3b9f 100644\n--- a/frame_test.go\n+++ b/frame_test.go\n@@ -382,3 +382,51 @@ func TestWriteWindowUpdate(t *testing.T) {\n \t\tt.Errorf(\"parsed back %#v; want %#v\", f, want)\n \t}\n }\n+\n+func TestReadFrameHeader(t *testing.T) {\n+\ttests := []struct {\n+\t\tlen uint32\n+\t\ttyp FrameType\n+\t\tflags Flags\n+\t\tstreamID uint32\n+\t}{\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 0},\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 1},\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 255},\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 256},\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 65535},\n+\t\t{len: 0, typ: 255, flags: 1, streamID: 65536},\n+\n+\t\t{len: 0, typ: 1, flags: 255, streamID: 1},\n+\t\t{len: 255, typ: 1, flags: 255, streamID: 1},\n+\t\t{len: 256, typ: 1, flags: 255, streamID: 1},\n+\t\t{len: 65535, typ: 1, flags: 255, streamID: 1},\n+\t\t{len: 65536, typ: 1, flags: 255, streamID: 1},\n+\t\t{len: 16777215, typ: 1, flags: 255, streamID: 1},\n+\t}\n+\tfor _, tt := range tests {\n+\t\tfr, buf := testFramer()\n+\t\tfr.startWrite(tt.typ, tt.flags, tt.streamID)\n+\t\tfr.writeBytes(make([]byte, tt.len))\n+\t\tfr.endWrite()\n+\t\tfh, err := ReadFrameHeader(buf)\n+\t\tif err != nil {\n+\t\t\tt.Errorf(\"ReadFrameHeader(%+v) = %v\", tt, err)\n+\t\t\tcontinue\n+\t\t}\n+\t\tif fh.Type != tt.typ || fh.Flags != tt.flags || fh.Length != tt.len || fh.StreamID != tt.streamID {\n+\t\t\tt.Errorf(\"ReadFrameHeader(%+v) = %+v; mismatch\", tt, fh)\n+\t\t}\n+\t}\n+\n+}\n+\n+func TestWriteTooLargeFrame(t *testing.T) {\n+\tfr, _ := testFramer()\n+\tfr.startWrite(0, 1, 1)\n+\tfr.writeBytes(make([]byte, 1<<24))\n+\terr := fr.endWrite()\n+\tif err != errFrameTooLarge {\n+\t\tt.Errorf(\"endWrite = %v; want errFrameTooLarge\", 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Logger updated, only streaming is logged\n\n<|file_patch|>flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java\ndiff --git a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java\nindex e73b03ada4c35d1f556275024fc37fb303c5eee3..0ae5aa53778a76692c83aebe8aa622f0bbf52d2c 100644\n--- a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java\n+++ b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java\n@@ -49,7 +49,7 @@ public abstract class StreamInvokableComponent {\n \t\ttry {\n \t\t\tfor (RecordWriter<StreamRecord> output : outputs) {\n \t\t\t\toutput.emit(record);\n-\t\t\t\tlog.debug(\"EMITTED: \" + record.getId() + \" -- \" + name);\n+\t\t\t\tlog.info(\"EMITTED: \" + record.getId() + \" -- \" + name);\n \t\t\t}\n \t\t} catch (Exception e) {\n \t\t\tlog.warn(\"EMIT ERROR: \" + e.getMessage() + \" -- \" + name);\n\n<|file_patch|>flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/batch/BatchForwardLocal.java\ndiff --git a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/batch/BatchForwardLocal.java b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/batch/BatchForwardLocal.java\nindex ca0917e489f5f258db49b22dbc4c6d0c76a6e3ba..ca69b72adb0384d3e0b1260076d92ab9586d0cd9 100644\n--- a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/batch/BatchForwardLocal.java\n+++ b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/batch/BatchForwardLocal.java\n@@ -78,7 +78,7 @@ public class BatchForwardLocal {\n \t\t\t\tClient client = new Client(new InetSocketAddress(\n \t\t\t\t\t\t\"hadoop02.ilab.sztaki.hu\", 6123), configuration);\n \n-\t\t\t\tclient.run(null, jG, true);\n+\t\t\t\tclient.run( jG, true);\n \n \t\t\t}\n \n\n<|file_patch|>flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/wordcount/WordCountLocal.java\ndiff --git a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/wordcount/WordCountLocal.java b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/wordcount/WordCountLocal.java\nindex 7cf946cc75dda85c7d5b25b689f7efe29d194613..a81fb1b671438e32ad98f6c1924d2af1da4461a8 100644\n--- a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/wordcount/WordCountLocal.java\n+++ b/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/test/wordcount/WordCountLocal.java\n@@ -46,15 +46,23 @@ public class WordCountLocal {\n \t\treturn graphBuilder.getJobGraph();\n \t}\n \n-\tpublic static void main(String[] args) {\n-\n-\t\tLogger root = Logger.getRootLogger();\n-\t\troot.removeAllAppenders();\n+\tpublic static void setLogger() {\n+\t\tLogger logger = Logger.getLogger(\"eu.stratosphere.streaming\");\n+\t\tlogger.removeAllAppenders();\n \t\tPatternLayout layout = new PatternLayout(\n \t\t\t\t\"%d{HH:mm:ss,SSS} %-5p %-60c %x - %m%n\");\n \t\tConsoleAppender appender = new ConsoleAppender(layout, \"System.err\");\n+\t\tlogger.addAppender(appender);\n+\t\tlogger.setLevel(Level.DEBUG);\n+\t\t\n+\t\tLogger root = Logger.getRootLogger();\n+\t\troot.removeAllAppenders();\n \t\troot.addAppender(appender);\n-\t\troot.setLevel(Level.DEBUG);\n+\t\troot.setLevel(Level.ERROR);\n+\t}\n+\t\n+\tpublic static void main(String[] args) {\n+\t\tsetLogger();\n \n \t\ttry {\n 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Next development version 3.5.12-SNAPSHOT\n\nSigned-off-by: Oleh Dokuka <odokuka@vmware.com>\n\n<|file_patch|>gradle.properties\ndiff --git a/gradle.properties b/gradle.properties\nindex f9a378b2626a7c15c2dfb703425ee1899b610913..9865d37b2fee75043e37349dd19273b4b1b332a0 100644\n--- a/gradle.properties\n+++ b/gradle.properties\n@@ -1,3 +1,3 @@\n-version=3.5.11\n+version=3.5.12-SNAPSHOT\n bomVersion=2022.0.12\n-metricsMicrometerVersion=1.0.11\n+metricsMicrometerVersion=1.0.12-SNAPSHOT\n\n<|file_patch|>gradle/libs.versions.toml\ndiff --git a/gradle/libs.versions.toml b/gradle/libs.versions.toml\nindex 7ce8cdbe830dab3e87590c6eacd5a4cbb590b3cd..0343893154ecc4f6cd8e8e0f6ff1f36b52f32063 100644\n--- a/gradle/libs.versions.toml\n+++ b/gradle/libs.versions.toml\n@@ -7,8 +7,8 @@\n \n [versions]\n # Baselines, should be updated on every release\n-baseline-core-api = \"3.5.10\"\n-baselinePerfCore = \"3.5.10\"\n+baseline-core-api = \"3.5.11\"\n+baselinePerfCore = \"3.5.11\"\n baselinePerfExtra = \"3.5.1\"\n \n # Other shared versions\n\n"},"target_character_start":{"kind":"number","value":120,"string":"120"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":1023,"string":"1,023"},"document_order_key":{"kind":"number","value":2947455426971485700,"string":"2,947,455,426,971,485,700"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/reactor/reactor-core"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":10,"string":"10"},"primary_language":{"kind":"string","value":"toml"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/reactor/reactor-core\",\"commit_oid\":\"7dff05d5629dc29f0e6dd6d2aaafe65bcc99f9ae\",\"commits_ago_from_head\":1075,\"content_sha256\":\"ff44626f91e1590d239aa9afd716cdc6deb04212950ccfc203af7aef09fd6980\",\"manifest_sha256\":null,\"parent_oid\":\"c6b7f8778bd398ba38f019f6e43977cafb0a68e5\",\"repository_id\":\"github.com/reactor/reactor-core\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":10,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":11,\"repo_score_components\":{\"dependents_reach\":4,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":2,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":9,\"scope\":null,\"subject_length\":50,\"trailer_names\":[\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":4,\"context_bytes\":3215,\"deleted_lines\":4,\"files_changed\":2,\"hunk_count\":2,\"patch_bytes\":829,\"patch_sha256\":\"4a02d2ab56258dea39e5418286c9e00cecadcbb8c39cc0b2114e3b39f6950282\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":null,\"path\":\"gradle.properties\",\"purpose\":\"other\"},{\"language\":\"toml\",\"path\":\"gradle/libs.versions.toml\",\"purpose\":\"config\"}],\"primary_language\":\"toml\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":3215,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":2,\"patch_bytes\":829},\"commit_oid\":\"7dff05d5629dc29f0e6dd6d2aaafe65bcc99f9ae\",\"identity\":{\"author_email\":\"odokuka@vmware.com\",\"author_name\":\"Oleh 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NPE check\n\ngit-svn-id: https://svn.apache.org/repos/asf/activemq/trunk@550793 13f79535-47bb-0310-9956-ffa450edef68\n\n<|file_patch|>activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java\ndiff --git a/activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java b/activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java\nindex a22baf8ab808960f7f8c3928123888064c0ea6d6..82f2466d6cb94b1e15a95a8feb35482d516bf71d 100755\n--- a/activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java\n+++ b/activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java\n@@ -115,13 +115,13 @@ public class FanoutTransport implements CompositeTransport {\n if( rc != null ) {\n if( rc.ackCount.decrementAndGet() <= 0 ) {\n requestMap.remove(id);\n- transportListener.onCommand(command);\n+ transportListenerOnCommand(command);\n }\n } else {\n- transportListener.onCommand(command);\n+ transportListenerOnCommand(command);\n }\n } else {\n- transportListener.onCommand(command);\n+ transportListenerOnCommand(command);\n }\n }\n \n@@ -144,7 +144,9 @@ public class FanoutTransport implements CompositeTransport {\n }\n catch (InterruptedException e) {\n Thread.currentThread().interrupt();\n- transportListener.onException(new InterruptedIOException());\n+ if (transportListener != null) {\n+ transportListener.onException(new InterruptedIOException());\n+ }\n }\n } \n }\n@@ -532,4 +534,9 @@ public class FanoutTransport implements CompositeTransport {\n \t\treturn null;\n \t}\n \n+ protected void transportListenerOnCommand(Command command) {\n+ if (transportListener != null) {\n+ transportListener.onCommand(command);\n+ }\n+ }\n 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Strachan\",\"authored_at\":\"2007-06-26T12:56:08+00:00\",\"commit_oid\":\"f6e1ac7f979baff434d2ff06f5d2e562becc8a45\",\"commits_ago_from_head\":5722,\"committed_at\":\"2007-06-26T12:56:08+00:00\",\"committer_email\":\"jstrachan@apache.org\",\"committer_name\":\"James Strachan\",\"parent_oid\":\"8068c5e1551bed9e0003806cb7b463bd1c058473\",\"tree_oid\":\"dfaffc41d41090d1b13403cde20d5666b786f906\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"trunk\",\"history_collected\":{\"commits_read\":8181,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"0b148ade32e58b83ed6ec9a1d04ff606b717d158\",\"oldest_commit\":\"40a7d3b6ac35d2ecb34e85fc3403d2e48e33874e\"},\"recorded_head_commit\":\"0b148ade32e58b83ed6ec9a1d04ff606b717d158\",\"repository_id\":\"github.com/alteryx/activemq-5-12\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/alteryx/activemq-5-12\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":23546,\"manifest_sha256\":null,\"split\":\"10-of-16\"}},\"parents\":[\"commit:github.com/alteryx/activemq-5-12@f6e1ac7f979baff434d2ff06f5d2e562becc8a45__download_changed_file_contents_bc43d54bd59b__render_commit_patches_0e4dc9adb5b8\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16071,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/davemorrissey/subsampling-scale-image-view@5049478cd8edae804503f3ca2df3c8724ece8bfb"},"text":{"kind":"string","value":"<|commit_message|>\nMigrate to AndroidX (#447 @vfishv)\n\n\n<|file_patch|>.travis.yml\ndiff --git a/.travis.yml b/.travis.yml\nindex 69effa023b4007ce1133e916f3cea65b4399c88b..7dec1a51392c462a3c591a7b9eec83413011ed65 100644\n--- a/.travis.yml\n+++ b/.travis.yml\n@@ -5,7 +5,7 @@ before_cache:\n - rm -fr $HOME/.gradle/caches/*/plugin-resolution/\n \n before_install:\n- - yes | sdkmanager \"platforms;android-27\"\n+ - yes | sdkmanager \"platforms;android-28\"\n \n cache:\n directories:\n@@ -16,8 +16,8 @@ cache:\n android:\n components:\n - tools\n- - build-tools-26.0.2\n- - android-27\n+ - build-tools-28.0.3\n+ - android-28\n - platform-tools\n licenses:\n - 'android-sdk-license-.+'\n\n<|file_patch|>build.gradle\ndiff --git a/build.gradle b/build.gradle\nold mode 100644\nnew mode 100755\nindex 8e05d42400bfad73c1f82b929b88474127d021c2..6b74aefe3693482ba516a6dfd764ecc210b89064\n--- a/build.gradle\n+++ b/build.gradle\n@@ -14,6 +14,6 @@ buildscript {\n google()\n }\n dependencies {\n- classpath 'com.android.tools.build:gradle:3.0.1'\n+ classpath 'com.android.tools.build:gradle:3.4.2'\n }\n }\n\n<|file_patch|>gradle.properties\ndiff --git a/gradle.properties b/gradle.properties\nindex aac7c9b4614ccfde6c721f24994cf30885a791d0..9e6fce102d11ffba5aae545fe7b688386407e699 100644\n--- a/gradle.properties\n+++ b/gradle.properties\n@@ -9,6 +9,8 @@\n \n # Specifies the JVM arguments used for the daemon process.\n # The setting is particularly useful for tweaking memory settings.\n+android.enableJetifier=true\n+android.useAndroidX=true\n org.gradle.jvmargs=-Xmx1536m\n \n # When configured, Gradle will run in incubating parallel mode.\n\n<|file_patch|>gradle/wrapper/gradle-wrapper.properties\ndiff --git a/gradle/wrapper/gradle-wrapper.properties b/gradle/wrapper/gradle-wrapper.properties\nindex 590f0e81da2faff9c4440e06dec0380940f523fe..3f0f9be633f5a4b6eb6468473b1c38ef26e3cf87 100644\n--- a/gradle/wrapper/gradle-wrapper.properties\n+++ b/gradle/wrapper/gradle-wrapper.properties\n@@ -2,4 +2,4 @@ distributionBase=GRADLE_USER_HOME\n distributionPath=wrapper/dists\n zipStoreBase=GRADLE_USER_HOME\n zipStorePath=wrapper/dists\n-distributionUrl=https\\://services.gradle.org/distributions/gradle-4.3-all.zip\n+distributionUrl=https\\://services.gradle.org/distributions/gradle-4.6-all.zip\n\n<|file_patch|>library/build.gradle\ndiff --git a/library/build.gradle b/library/build.gradle\nold mode 100644\nnew mode 100755\nindex 60d7171002c4f343110297fd370fbe10f3322ca4..2c8ae825f29614502581cebd3e243be280a7f9ec\n--- a/library/build.gradle\n+++ b/library/build.gradle\n@@ -5,9 +5,11 @@ archivesBaseName = 'subsampling-scale-image-view'\n version = '3.10.0'\n \n android {\n- compileSdkVersion 27\n+ compileSdkVersion 29\n \n defaultConfig {\n+ minSdkVersion 14\n+ targetSdkVersion 27\n consumerProguardFiles 'proguard-rules.txt'\n }\n }\n@@ -17,10 +19,11 @@ configurations {\n }\n \n dependencies {\n- javadocs 'com.android.support:support-annotations:27.1.0'\n- javadocs 'com.android.support:exifinterface:27.1.0'\n- implementation 'com.android.support:support-annotations:27.1.0'\n- implementation 'com.android.support:exifinterface:27.1.0'\n+ implementation \"androidx.appcompat:appcompat:1.0.2\"\n+ javadocs 'androidx.annotation:annotation:1.0.0'\n+ javadocs 'androidx.exifinterface:exifinterface:1.0.0'\n+ implementation 'androidx.annotation:annotation:1.0.0'\n+ implementation 'androidx.exifinterface:exifinterface:1.0.0'\n }\n \n task javadoc(type: Javadoc) {\n\n<|file_patch|>library/src/main/AndroidManifest.xml\ndiff --git a/library/src/main/AndroidManifest.xml b/library/src/main/AndroidManifest.xml\nindex 203f218b4906a2d8923ea74134cc65a71fc215c0..2c0ee9bf1f09860f998f16eb60a9c62096c3d438 100644\n--- a/library/src/main/AndroidManifest.xml\n+++ b/library/src/main/AndroidManifest.xml\n@@ -2,6 +2,4 @@\n <manifest xmlns:android=\"http://schemas.android.com/apk/res/android\"\n package=\"com.davemorrissey.labs.subscaleview\"\n android:versionCode=\"1\"\n- android:versionName=\"1.0\">\n- <uses-sdk android:minSdkVersion=\"14\" android:targetSdkVersion=\"27\"/>\n-</manifest>\n+ android:versionName=\"1.0\"></manifest>\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/ImageSource.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageSource.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageSource.java\nold mode 100644\nnew mode 100755\nindex 1314073eb491295ae6fb074c88733c9c19d56297..89bdfb63d3c00b8b7b01139a98b0b10288b969e3\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageSource.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageSource.java\n@@ -3,7 +3,7 @@ package com.davemorrissey.labs.subscaleview;\n import android.graphics.Bitmap;\n import android.graphics.Rect;\n import android.net.Uri;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n import java.io.File;\n import java.io.UnsupportedEncodingException;\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/ImageViewState.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageViewState.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageViewState.java\nold mode 100644\nnew mode 100755\nindex 4b463c995e8b769e2da802a16d1ba0d399b29a6d..b9b55b1e192f517ad1be852325b36b1b9177d52b\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageViewState.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/ImageViewState.java\n@@ -1,7 +1,7 @@\n package com.davemorrissey.labs.subscaleview;\n \n import android.graphics.PointF;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n import java.io.Serializable;\n \n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/CompatDecoderFactory.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/CompatDecoderFactory.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/CompatDecoderFactory.java\nold mode 100644\nnew mode 100755\nindex d829c9d6b862c455ce8bf7f836da7579d972c9d6..cf894a222ff327e77c163e11e6ca525f47f61a4e\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/CompatDecoderFactory.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/CompatDecoderFactory.java\n@@ -1,7 +1,7 @@\n package com.davemorrissey.labs.subscaleview.decoder;\n \n import android.graphics.Bitmap;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n import java.lang.reflect.Constructor;\n import java.lang.reflect.InvocationTargetException;\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/DecoderFactory.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/DecoderFactory.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/DecoderFactory.java\nold mode 100644\nnew mode 100755\nindex 0df8be85174a5fd49cf9c66c8351b6578b1ed75e..a324df6033b62753874a406e06222d041300cbd1\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/DecoderFactory.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/DecoderFactory.java\n@@ -1,6 +1,6 @@\n package com.davemorrissey.labs.subscaleview.decoder;\n \n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n import java.lang.reflect.InvocationTargetException;\n \n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageDecoder.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageDecoder.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageDecoder.java\nold mode 100644\nnew mode 100755\nindex d5ba62343c74ba9e35f4a40aece24681775bd658..13cb15f8fee5c99370be13e207716c58666e8e9a\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageDecoder.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageDecoder.java\n@@ -3,7 +3,7 @@ package com.davemorrissey.labs.subscaleview.decoder;\n import android.content.Context;\n import android.graphics.Bitmap;\n import android.net.Uri;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n /**\n * Interface for image decoding classes, allowing the default {@link android.graphics.BitmapFactory}\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageRegionDecoder.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageRegionDecoder.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageRegionDecoder.java\nold mode 100644\nnew mode 100755\nindex a9bdeb571d029413a39d7ec1f0e719d18fd43c77..e9b11f165404b2bb006827e05fe19b2136e71d17\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageRegionDecoder.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/ImageRegionDecoder.java\n@@ -5,7 +5,7 @@ import android.graphics.Bitmap;\n import android.graphics.Point;\n import android.graphics.Rect;\n import android.net.Uri;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n \n /**\n * Interface for image decoding classes, allowing the default {@link android.graphics.BitmapRegionDecoder}\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageDecoder.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageDecoder.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageDecoder.java\nold mode 100644\nnew mode 100755\nindex 4e9124b38237393b67ee71fe11cdac8614152b2b..45f96cc06c7d17a80ab9f500c8edb13077b2724f\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageDecoder.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageDecoder.java\n@@ -7,9 +7,9 @@ import android.content.res.Resources;\n import android.graphics.Bitmap;\n import android.graphics.BitmapFactory;\n import android.net.Uri;\n-import android.support.annotation.Keep;\n-import android.support.annotation.NonNull;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Keep;\n+import androidx.annotation.NonNull;\n+import androidx.annotation.Nullable;\n import android.text.TextUtils;\n \n import com.davemorrissey.labs.subscaleview.SubsamplingScaleImageView;\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageRegionDecoder.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageRegionDecoder.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageRegionDecoder.java\nold mode 100644\nnew mode 100755\nindex d2634c24a3f652ccd4ae1dfb52acd871dfc91005..a771eceb7cac43c7d04a0b84aeeda423c485bfa0\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageRegionDecoder.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaImageRegionDecoder.java\n@@ -8,9 +8,9 @@ import android.content.res.Resources;\n import android.graphics.*;\n import android.net.Uri;\n import android.os.Build;\n-import android.support.annotation.Keep;\n-import android.support.annotation.NonNull;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Keep;\n+import androidx.annotation.NonNull;\n+import androidx.annotation.Nullable;\n import android.text.TextUtils;\n \n import com.davemorrissey.labs.subscaleview.SubsamplingScaleImageView;\n\n<|file_patch|>library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaPooledImageRegionDecoder.java\ndiff --git a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaPooledImageRegionDecoder.java b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaPooledImageRegionDecoder.java\nold mode 100644\nnew mode 100755\nindex b1e9678d043e70a03e8637f7ffe2788c1f68b286..1f009dc77659340dd9ad1a05b2156615cc3f9299\n--- a/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaPooledImageRegionDecoder.java\n+++ b/library/src/main/java/com/davemorrissey/labs/subscaleview/decoder/SkiaPooledImageRegionDecoder.java\n@@ -14,9 +14,9 @@ import android.graphics.Point;\n import android.graphics.Rect;\n import android.net.Uri;\n import android.os.Build;\n-import android.support.annotation.Keep;\n-import android.support.annotation.NonNull;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Keep;\n+import androidx.annotation.NonNull;\n+import androidx.annotation.Nullable;\n import android.text.TextUtils;\n import android.util.Log;\n \n\n<|file_patch|>sample/build.gradle\ndiff --git a/sample/build.gradle b/sample/build.gradle\nold mode 100644\nnew mode 100755\nindex 8e536fceb35ef28da8a1b1737aade356aee249a2..c21a80c3c5fb7676be413a5cb17256eb07de065e\n--- a/sample/build.gradle\n+++ b/sample/build.gradle\n@@ -1,8 +1,10 @@\n apply plugin: 'com.android.application'\n \n android {\n- compileSdkVersion 27\n+ compileSdkVersion 29\n defaultConfig {\n+ minSdkVersion 17\n+ targetSdkVersion 27\n applicationId \"com.davemorrissey.labs.subscaleview.test\"\n }\n \n@@ -15,5 +17,5 @@ android {\n \n dependencies {\n implementation project(':library')\n- implementation 'com.android.support:support-v4:27.1.0'\n+ implementation 'androidx.legacy:legacy-support-v4:1.0.0'\n }\n\n<|file_patch|>sample/src/main/AndroidManifest.xml\ndiff --git a/sample/src/main/AndroidManifest.xml b/sample/src/main/AndroidManifest.xml\nindex f49b08f491583fb63497d9e5e844dcf421db1c43..c573e0bab301cff2768806446fc9d44cc9e203a3 100644\n--- a/sample/src/main/AndroidManifest.xml\n+++ b/sample/src/main/AndroidManifest.xml\n@@ -5,8 +5,8 @@\n android:versionCode=\"4\"\n android:versionName=\"3.1.0\"\n android:hardwareAccelerated=\"true\">\n-<uses-sdk android:minSdkVersion=\"17\" android:targetSdkVersion=\"27\"/>\n-<uses-permission android:name=\"android.permission.READ_PHONE_STATE\" tools:node=\"remove\"/>\n+\n+ <uses-permission android:name=\"android.permission.READ_PHONE_STATE\" tools:node=\"remove\"/>\n <uses-permission android:name=\"android.permission.READ_EXTERNAL_STORAGE\" tools:node=\"remove\"/>\n <uses-permission android:name=\"android.permission.WRITE_EXTERNAL_STORAGE\" tools:node=\"remove\"/>\n <application android:label=\"@string/app.name\" android:theme=\"@style/sampleTheme\" android:icon=\"@mipmap/ic_launcher\" android:allowBackup=\"false\" tools:ignore=\"GoogleAppIndexingWarning\">\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractFragmentsActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractFragmentsActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractFragmentsActivity.java\nindex 154c2e48701a30069da1e9c4a3bc45295c04429c..fc5166d5de1ad93679d37b5e23cbc622c266c49d 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractFragmentsActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractFragmentsActivity.java\n@@ -2,8 +2,8 @@ package com.davemorrissey.labs.subscaleview.test;\n \n import android.app.ActionBar;\n import android.os.Bundle;\n-import android.support.annotation.Nullable;\n-import android.support.v4.app.FragmentActivity;\n+import androidx.annotation.Nullable;\n+import androidx.fragment.app.FragmentActivity;\n import android.view.MenuItem;\n \n import java.util.List;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractPagesActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractPagesActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractPagesActivity.java\nindex 4ce36de5b35ba89ddbf125a3800dfbf96463496a..b5b711c8fde1fa1f8cf6c17a965bb224c8d9fe40 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractPagesActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/AbstractPagesActivity.java\n@@ -2,8 +2,8 @@ package com.davemorrissey.labs.subscaleview.test;\n \n import android.app.ActionBar;\n import android.os.Bundle;\n-import android.support.annotation.Nullable;\n-import android.support.v4.app.FragmentActivity;\n+import androidx.annotation.Nullable;\n+import androidx.fragment.app.FragmentActivity;\n import android.view.MenuItem;\n import android.view.View;\n import android.widget.TextView;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/animation/AnimationActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/animation/AnimationActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/animation/AnimationActivity.java\nindex 41666987e7d3ccf67821645b2b3eba6f5bba52a4..98c9ba05c832da79456e9c10f24a6a65ee39d6f1 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/animation/AnimationActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/animation/AnimationActivity.java\n@@ -2,7 +2,7 @@ package com.davemorrissey.labs.subscaleview.test.animation;\n \n import android.graphics.PointF;\n import android.os.Bundle;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Nullable;\n import android.view.View;\n \n import com.davemorrissey.labs.subscaleview.ImageSource;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/basicfeatures/BasicFeaturesActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/basicfeatures/BasicFeaturesActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/basicfeatures/BasicFeaturesActivity.java\nindex ad8b60068344104526453ac1e722569fee79e6f9..0a2fa3edd4540697ba1c9f44e27cc203ac5b7385 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/basicfeatures/BasicFeaturesActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/basicfeatures/BasicFeaturesActivity.java\n@@ -1,7 +1,7 @@\n package com.davemorrissey.labs.subscaleview.test.basicfeatures;\n \n import android.os.Bundle;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Nullable;\n \n import com.davemorrissey.labs.subscaleview.ImageSource;\n import com.davemorrissey.labs.subscaleview.SubsamplingScaleImageView;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/configuration/ConfigurationActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/configuration/ConfigurationActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/configuration/ConfigurationActivity.java\nindex 22965815a2151075b04082afa9474394b744d425..66973a40d0764fcf026ca4062e8516cbb782a131 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/configuration/ConfigurationActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/configuration/ConfigurationActivity.java\n@@ -2,7 +2,7 @@ package com.davemorrissey.labs.subscaleview.test.configuration;\n \n import android.graphics.PointF;\n import android.os.Bundle;\n-import android.support.annotation.Nullable;\n+import androidx.annotation.Nullable;\n \n import com.davemorrissey.labs.subscaleview.ImageSource;\n import com.davemorrissey.labs.subscaleview.SubsamplingScaleImageView;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionActivity.java\nindex 89b4344c5486076fbeee99ffc71b2f31d82bfdb1..b05e96d1bdd9cddf48e389c3d1ab2d66b26f9ee6 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionActivity.java\n@@ -1,6 +1,6 @@\n package com.davemorrissey.labs.subscaleview.test.extension;\n \n-import android.support.v4.app.Fragment;\n+import androidx.fragment.app.Fragment;\n import android.util.Log;\n \n import com.davemorrissey.labs.subscaleview.test.AbstractFragmentsActivity;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionCircleFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionCircleFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionCircleFragment.java\nindex 47edf074dcb2a441d6bee5818a59bb7faa973e39..a60f7f398c87b3ad26ec6b1cd1ef3e717c2ce564 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionCircleFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionCircleFragment.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.extension;\n \n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionFreehandFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionFreehandFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionFreehandFragment.java\nindex 5ea14679e2c6f62b61cf8591927eddacc3df9c72..98acade51911f1eff391c990e4a8e3b2423cccef 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionFreehandFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionFreehandFragment.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.extension;\n \n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionPinFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionPinFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionPinFragment.java\nindex c7f52f148537e98b846bc2338a0cb1e88e5116bd..cfe9d3dca5ed5e972618f9423c01d55f870b75de 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionPinFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/ExtensionPinFragment.java\n@@ -2,8 +2,8 @@ package com.davemorrissey.labs.subscaleview.test.extension;\n \n import android.graphics.PointF;\n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/views/FreehandView.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/views/FreehandView.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/views/FreehandView.java\nindex f4f14035fd5e40b04d78ce040efcea565d32d71f..a0c92a9eb92722f927a88190febdb565628525bd 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/views/FreehandView.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/extension/views/FreehandView.java\n@@ -4,7 +4,7 @@ import android.content.Context;\n import android.graphics.*;\n import android.graphics.Paint.Cap;\n import android.graphics.Paint.Style;\n-import android.support.annotation.NonNull;\n+import androidx.annotation.NonNull;\n import android.util.AttributeSet;\n import android.view.MotionEvent;\n import android.view.View;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayActivity.java\nindex 9900e34a534a01c139467d25cae7cd2870e4b5a6..06ff52865dc6543b5a3c7810e61f49bc35fc3575 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayActivity.java\n@@ -1,6 +1,6 @@\n package com.davemorrissey.labs.subscaleview.test.imagedisplay;\n \n-import android.support.v4.app.Fragment;\n+import androidx.fragment.app.Fragment;\n import android.util.Log;\n \n import com.davemorrissey.labs.subscaleview.test.AbstractFragmentsActivity;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayLargeFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayLargeFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayLargeFragment.java\nindex 70d34459baf025c0b6d4c3557bddde86f64311fc..c53da11a749e527fc75809da3b8913e72d78d251 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayLargeFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayLargeFragment.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.imagedisplay;\n \n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRegionFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRegionFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRegionFragment.java\nindex 566e144ee0f166cde9fbbee820b370da4b213d31..d1798137257d3d1d12f57544c7cd5d35d795e744 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRegionFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRegionFragment.java\n@@ -3,8 +3,8 @@ package com.davemorrissey.labs.subscaleview.test.imagedisplay;\n import android.graphics.Bitmap;\n import android.graphics.Rect;\n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRotateFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRotateFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRotateFragment.java\nindex 46465c41c967621ba25f77573c99b4d331711fe7..d9ecd56455748f95e35d1570677a2267cee600e9 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRotateFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/imagedisplay/ImageDisplayRotateFragment.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.imagedisplay;\n \n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/VerticalViewPager.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/VerticalViewPager.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/VerticalViewPager.java\nindex 71131ea350c43cba69a528dae010348011a563c8..5bccd9ba9f82ef43be63f7fd0c1f8ea54486fabf 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/VerticalViewPager.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/VerticalViewPager.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.viewpager;\n \n import android.content.Context;\n-import android.support.annotation.NonNull;\n-import android.support.v4.view.ViewPager;\n+import androidx.annotation.NonNull;\n+import androidx.viewpager.widget.ViewPager;\n import android.util.AttributeSet;\n import android.view.MotionEvent;\n import android.view.View;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerActivity.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerActivity.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerActivity.java\nindex 3f9a79d02f0f8bb5171bdbd8b2d5e40e03370f43..307c6d3829f3959aec5343eee8684d9abbc631e7 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerActivity.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerActivity.java\n@@ -1,10 +1,10 @@\n package com.davemorrissey.labs.subscaleview.test.viewpager;\n \n import android.os.Bundle;\n-import android.support.v4.app.Fragment;\n-import android.support.v4.app.FragmentManager;\n-import android.support.v4.app.FragmentStatePagerAdapter;\n-import android.support.v4.view.ViewPager;\n+import androidx.fragment.app.Fragment;\n+import androidx.fragment.app.FragmentManager;\n+import androidx.fragment.app.FragmentStatePagerAdapter;\n+import androidx.viewpager.widget.ViewPager;\n import android.view.View;\n \n import com.davemorrissey.labs.subscaleview.test.AbstractPagesActivity;\n\n<|file_patch|>sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerFragment.java\ndiff --git a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerFragment.java b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerFragment.java\nindex 03e7155e3eb15462806f9e9be62abc05de4ab59a..d33bcaaa2201e677397e5ceda9bcfb10d8b52a54 100644\n--- a/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerFragment.java\n+++ b/sample/src/main/java/com/davemorrissey/labs/subscaleview/test/viewpager/ViewPagerFragment.java\n@@ -1,8 +1,8 @@\n package com.davemorrissey.labs.subscaleview.test.viewpager;\n \n import android.os.Bundle;\n-import android.support.annotation.NonNull;\n-import android.support.v4.app.Fragment;\n+import androidx.annotation.NonNull;\n+import androidx.fragment.app.Fragment;\n import android.view.LayoutInflater;\n import android.view.View;\n import android.view.ViewGroup;\n\n<|file_patch|>sample/src/main/res/layout/view_pager.xml\ndiff --git a/sample/src/main/res/layout/view_pager.xml b/sample/src/main/res/layout/view_pager.xml\nindex 61880970422993697be6d917eaced290318012e7..88567cc6ef4c76c38809ab61f55055058bba6fa5 100644\n--- a/sample/src/main/res/layout/view_pager.xml\n+++ b/sample/src/main/res/layout/view_pager.xml\n@@ -13,7 +13,7 @@\n \n </RelativeLayout>\n \n- <android.support.v4.view.ViewPager style=\"@style/mainPanel\" android:id=\"@+id/horizontal_pager\" android:visibility=\"gone\" />\n+ <androidx.viewpager.widget.ViewPager style=\"@style/mainPanel\" android:id=\"@+id/horizontal_pager\" android:visibility=\"gone\" />\n \n <com.davemorrissey.labs.subscaleview.test.viewpager.VerticalViewPager style=\"@style/mainPanel\" android:id=\"@+id/vertical_pager\" android:visibility=\"gone\"/>\n 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Added PressEnter and WakeUp device actions\n\n<|file_patch|>android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java\ndiff --git a/android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java b/android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java\nindex d18a0a38a48ebc6e9572930e798253e6141ff28b..823f24e8acb3b000fa0fbac89b7b786bd62f0c9d 100644\n--- a/android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java\n+++ b/android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java\n@@ -45,6 +45,8 @@ public class ActionsExecutor {\n actionClasses.add(LaunchApp.class);\n actionClasses.add(LaunchHome.class);\n actionClasses.add(PressBack.class);\n+ actionClasses.add(PressEnter.class);\n+ actionClasses.add(WakeUp.class);\n actionClasses.add(IsTextPresent.class);\n actionClasses.add(IsButtonPresent.class);\n actionClasses.add(IsElementWithNestedTextPresent.class);\n\n<|file_patch|>android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/PressEnter.java\ndiff --git a/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/PressEnter.java b/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/PressEnter.java\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..c2908c39711d9b0bafcc0495bdf2a01efd1f1e08\n--- /dev/null\n+++ b/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/PressEnter.java\n@@ -0,0 +1,19 @@\n+package com.uiautomator_cucumber.android_server.actions;\n+\n+import com.android.uiautomator.core.*;\n+import com.uiautomator_cucumber.android_server.Action;\n+import com.uiautomator_cucumber.android_server.Result;\n+\n+import java.util.Map;\n+\n+public class PressEnter extends Action {\n+ public PressEnter(UiDevice uiDevice) {\n+ super(uiDevice);\n+ }\n+\n+ @Override\n+ public Result execute(Map<String, Object> arguments) throws UiObjectNotFoundException {\n+ getUiDevice().pressEnter();\n+ return Result.OK;\n+ }\n+}\n\\ No newline at end of file\n\n<|file_patch|>android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/WakeUp.java\ndiff --git a/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/WakeUp.java b/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/WakeUp.java\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..54666dab7060f6d3432408ca9e180d4b0319a7e3\n--- /dev/null\n+++ b/android-server/src/main/java/com/uiautomator_cucumber/android_server/actions/WakeUp.java\n@@ -0,0 +1,24 @@\n+package com.uiautomator_cucumber.android_server.actions;\n+\n+import com.android.uiautomator.core.*;\n+import com.uiautomator_cucumber.android_server.Action;\n+import com.uiautomator_cucumber.android_server.Result;\n+import android.os.RemoteException;\n+\n+import java.util.Map;\n+\n+public class WakeUp extends Action {\n+ public WakeUp(UiDevice uiDevice) {\n+ super(uiDevice);\n+ }\n+\n+ @Override\n+ public Result execute(Map<String, Object> arguments) throws UiObjectNotFoundException {\n+ try {\n+ getUiDevice().wakeUp();\n+ } catch (RemoteException e) {\n+ return Result.FAILURE;\n+ }\n+ return Result.OK;\n+ }\n+}\n\\ No newline at end of file\n\n<|file_patch|>lib/honeydew/device_actions.rb\ndiff --git a/lib/honeydew/device_actions.rb b/lib/honeydew/device_actions.rb\nindex 7a15f534f6914ba846704f525f71a398eedeff99..cce64296f9a6fef53bd2676bb3b19ce5ce09022d 100644\n--- a/lib/honeydew/device_actions.rb\n+++ b/lib/honeydew/device_actions.rb\n@@ -65,10 +65,18 @@ module Honeydew\n perform_action :action => 'press_back'\n end\n \n+ def press_enter\n+ perform_action :action => 'press_enter'\n+ end\n+\n def unlock\n perform_action :action => 'unlock'\n end\n \n+ def wake_up\n+ perform_action :action => 'wake_up'\n+ end\n+\n def perform_action(options)\n ensure_tablet_ready\n \n\n<|file_patch|>lib/honeydew/version.rb\ndiff --git a/lib/honeydew/version.rb b/lib/honeydew/version.rb\nindex 366ce8bfdfeac7feba4aadf40184b7ff4f60dace..eb99364aec4a3cbd4715516f6381b890949f96b3 100644\n--- a/lib/honeydew/version.rb\n+++ b/lib/honeydew/version.rb\n@@ -1,3 +1,3 @@\n module Honeydew\n- VERSION = \"0.1.1\"\n+ VERSION = \"0.1.2\"\n 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protobuf changes\n\nPiperOrigin-RevId: 527076622\n\n<|file_patch|>src/google/protobuf/port_undef.inc\ndiff --git a/src/google/protobuf/port_undef.inc b/src/google/protobuf/port_undef.inc\nindex 03b216c4221629d3004ff2d4f9ec6ae4f20c4367..d56614765eabab9e72b945544e9c2f25d5b3020e 100644\n--- a/src/google/protobuf/port_undef.inc\n+++ b/src/google/protobuf/port_undef.inc\n@@ -127,6 +127,11 @@\n #undef PROTOBUF_DID_UNDEF_PACKAGE\n #endif\n \n+#ifdef PROTOBUF_DID_UNDEF_PACKED\n+#pragma pop_macro(\"PACKED\")\n+#undef PROTOBUF_DID_UNDEF_PACKED\n+#endif\n+\n #ifdef PROTOBUF_DID_UNDEF_LINUX\n #pragma pop_macro(\"linux\")\n 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Zhang\",\"authored_at\":\"2023-04-25T14:31:44-07:00\",\"commit_oid\":\"7dbe742e6c4bea916c54713e31811412d2076351\",\"commits_ago_from_head\":5834,\"committed_at\":\"2023-04-25T14:33:12-07:00\",\"committer_email\":\"copybara-worker@google.com\",\"committer_name\":\"Copybara-Service\",\"parent_oid\":\"b26afb5a86cd9f764e35795c41c0f94a012db19e\",\"tree_oid\":\"301e9cdc8f66a3d018078e929ad47877c444c2e7\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"src/google/protobuf/descriptor.proto\",\"reason\":\"file_too_long\"},{\"path\":\"src/google/protobuf/port_def.inc\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"2d9c00cceca5e5465b04909362829e14f90c87b2\",\"oldest_commit\":\"f9a1f161635951b587298aca91dbd40f9a69f991\"},\"recorded_head_commit\":\"2d9c00cceca5e5465b04909362829e14f90c87b2\",\"repository_id\":\"github.com/akylas/protobuf\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/akylas/protobuf\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":17486,\"manifest_sha256\":null,\"split\":\"14-of-16\"}},\"parents\":[\"commit:github.com/akylas/protobuf@7dbe742e6c4bea916c54713e31811412d2076351__download_changed_file_contents_c5904989bfb9__drop_changed_files_over_maximum_character_count_067c32d711a3__render_commit_patches_8f86488f8e20\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16075,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/ardupilot/pidcodes.github.com@3706846b8a4c7f58c7a5cb229ec9e89107b1a391"},"text":{"kind":"string","value":"<|commit_message|>\nEnable initial Travis CI workflow (#183)\n\n* Remove errant .DS_Store file\r\n\r\n* Ignore .DS_Store\r\n\r\n* Create a list of organisations\r\n\r\n* Add an org list\r\n\r\n* Show number of PIDs per org\r\n\r\n* Fix HTML issue, sort orgs by title\r\n\r\n* Try and fix the PID count\r\n\r\n* Try and fix issues\r\n\r\n* Try again to fix issues\r\n\r\n* Try yet again to fix issues\r\n\r\n* Correct the urlpart\r\n\r\n* Change to sort_natural, minor code tidy\r\n\r\n* Try and fix the sorting\r\n\r\n* Try again to fix the sorting\r\n\r\n* Remove debugging\r\n\r\n* Add a link to orgs page\r\n\r\n* Install dependencies for Travis\r\n\r\n* Create .travis.yml\r\n\r\n* Add the Travis script\r\n\r\n* Update the Ruby version\r\n\r\n* Bump the Ruby version some more\r\n\r\n* Switch back to the documented version\r\n\r\n* Add the exclude\r\n\r\n* Update based on https://github.com/jekyll/jekyll/pull/5413\r\n\r\n* Add github-pages Gem\r\n\r\n* Add missing gems\r\n\r\n* Add redcarpet\r\n\r\n* Switch to tasks so we can run multiple CI tasks\r\n\r\n* Switch to tasks\r\n\r\n* Fix the matrix\r\n\r\n* More matrix fixing\r\n\r\n* Turn on more htmlproofer options\r\n\r\n* Make the check less strict\r\n\r\n* Don't bother complaining about extra jekyll tags\r\n\r\n* Escape HTML entities\r\n\r\n* Fix the email link\r\n\r\n* Fix the link within the 404 page!\r\n\r\n* Escape more HTML entities\r\n\r\n* Remove an invalid site URL\r\n\r\n* Cache ruby bundles\r\n\r\n* Escape even more HTML entities\r\n\r\n* Escape yet more HTML entities\r\n\r\n* Escape more HTML entities and switch to a div\r\n\r\n* Try and fix the errant paragraph item\r\n\r\n* Add a Travis badge to the readme\r\n\r\n* Update Gemfile\r\n\r\nAdapted from https://github.com/lunaryorn/lunaryorn.github.io\r\n\r\n* Update _config.yml\r\n\r\n* Add some more checks to Travis\r\n\r\n* Report GH Pages versions\r\n\r\n* Tidy up, add redcarpet back in\r\n\r\n* Try and stop the spurious paragraph tags\r\n\n<|file_patch|>.travis-ci.sh\ndiff --git a/.travis-ci.sh b/.travis-ci.sh\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..b46f488def0c832508ddda7ad43980ea5ffa2065\n--- /dev/null\n+++ b/.travis-ci.sh\n@@ -0,0 +1,16 @@\n+#!/bin/bash\n+set -e # halt script on error\n+\n+HTMLPROOFER_OPTIONS=\"./_site --check-html --report-missing-names --log-level=:debug\"\n+\n+bundle exec jekyll doctor\n+bundle exec jekyll build\n+\n+if [[ $TASK = 'htmlproofer' ]]; then\n+ bundle exec htmlproofer $HTMLPROOFER_OPTIONS --disable-external\n+elif [[ $TASK = 'htmlproofer-external' ]]; then\n+ bundle exec htmlproofer $HTMLPROOFER_OPTIONS\n+fi\n+\n+# Validate GH Pages DNS setup\n+bundle exec github-pages health-check\n\n<|file_patch|>.travis.yml\ndiff --git a/.travis.yml b/.travis.yml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..0584cfda87d9ee40a841a673e939c36717e6026a\n--- /dev/null\n+++ b/.travis.yml\n@@ -0,0 +1,28 @@\n+sudo: false # route your build to the container-based infrastructure for a faster build\n+\n+language: ruby\n+\n+# Cache Ruby bundles\n+cache: bundler\n+\n+before_script:\n+ - bundle exec github-pages versions\n+\n+# Assume bundler is being used, therefore\n+# the `install` step will run `bundle install` by default.\n+script: \"bash -ex .travis-ci.sh\"\n+\n+env:\n+ global:\n+ - NOKOGIRI_USE_SYSTEM_LIBRARIES=true # speeds up installation of html-proofer\n+\n+matrix:\n+ fast_finish: true\n+ include:\n+ - rvm: 2.2.5\n+ env: TASK='htmlproofer'\n+ - rvm: 2.2.5\n+ env: TASK='htmlproofer-external'\n+ allow_failures:\n+ - rvm: 2.2.5\n+ env: TASK='htmlproofer-external'\n\n<|file_patch|>1209/E500/index.md\ndiff --git a/1209/E500/index.md b/1209/E500/index.md\nindex 688416db31081b597abe5a947ba2591dcc10eb7b..5e2553a986886c22f16366f1c1e612a0c73e296a 100644\n--- a/1209/E500/index.md\n+++ b/1209/E500/index.md\n@@ -3,7 +3,6 @@ layout: pid\n title: Helios Laser DAC\n owner: GitleMikkelsen\n license: Creative Commons Attribution-NonCommercial 4.0 International\n-site: TBD\n source: https://github.com/Grix/helios_dac\n ---\n-Open source, low cost USB DAC for the ISP-DB25 laser projector protocol.\n\\ No newline at end of file\n+Open source, low cost USB DAC for the ISP-DB25 laser projector protocol.\n\n<|file_patch|>404.md\ndiff --git a/404.md b/404.md\nindex ab7c9f6b117ad37519bd491baabe0783ffa6a318..4f2e8a6b4b8e0e3a34c38498d8a6e92d167d2b85 100755\n--- a/404.md\n+++ b/404.md\n@@ -9,5 +9,5 @@ Sorry, we can't seem to find this page's pixylls.\n \n <div class=\"mt3\">\n <a href=\"{{ site.baseurl }}/\" class=\"button button-blue button-big\">Home</a>\n- <a href=\"{{ site.baseurl }}/contact/\" class=\"button button-blue button-big\">Contact</a>\n+ <a href=\"{{ site.baseurl }}/about/\" class=\"button button-blue button-big\">About</a>\n </div>\n\n<|file_patch|>Gemfile\ndiff --git a/Gemfile b/Gemfile\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..88c9b37ca62dcebf1f2726c3e0bc359e7c0b30b3\n--- /dev/null\n+++ b/Gemfile\n@@ -0,0 +1,14 @@\n+require \"json\"\n+require \"open-uri\"\n+\n+source \"https://rubygems.org\"\n+\n+versions = open(\"https://pages.github.com/versions.json\") do |source|\n+ JSON.parse(source.read)\n+end\n+\n+# Github Pages environment\n+gem \"github-pages\", versions['github-pages']\n+gem \"redcarpet\"\n+\n+gem \"html-proofer\"\n\n<|file_patch|>README.md\ndiff --git a/README.md b/README.md\nindex 54f07a073c54b7d2220e3f8e481ac6a356fc15c8..a81cbc1c31d03c4f3cd6d3709195fa5d49c2d910 100644\n--- a/README.md\n+++ b/README.md\n@@ -1,4 +1,4 @@\n-\n # pid.codes\n-Website for pid.codes\n+[](https://travis-ci.org/pidcodes/pidcodes.github.com)\n \n+Website for [pid.codes](http://pid.codes)\n\n<|file_patch|>_config.yml\ndiff --git a/_config.yml b/_config.yml\nindex 5c327b0fe68b6f91b093c75038a38672003f782b..388ec024d1ec5c201f7aa6831d4827f01988a788 100644\n--- a/_config.yml\n+++ b/_config.yml\n@@ -44,6 +44,10 @@ share_reddit: false\n share_stumbleupon: false\n \n # Build settings\n+exclude: [vendor]\n+gems:\n+ - jekyll-paginate\n+ - redcarpet\n markdown: redcarpet\n redcarpet:\n extensions: ['smart', 'tables', 'with_toc_data']\n\n<|file_patch|>_includes/head.html\ndiff --git a/_includes/head.html b/_includes/head.html\nindex 676fac8492ce658d14750273995ec90f2d16c36c..13bc629d79c30a9f8d15e9bfa57c6b8e72e79d3e 100644\n--- a/_includes/head.html\n+++ b/_includes/head.html\n@@ -1,11 +1,11 @@\n <head>\n <meta charset=\"utf-8\">\n <meta http-equiv=\"X-UA-Compatible\" content=\"IE=edge\">\n- <title>{% if include.title %}{{ include.title }} – {% elsif page.title %}{{ page.title }} – {% endif %}{{ site.title }}</title>\n+ <title>{% if include.title %}{{ include.title | xml_escape }} – {% elsif page.title %}{{ page.title | xml_escape }} – {% endif %}{{ site.title | xml_escape }}</title>\n <meta name=\"viewport\" content=\"width=device-width, initial-scale=1\">\n- <meta name=\"description\" content=\"{% if page.summary %}{{ page.summary }}{% else %}{{ site.description }}{% endif %}\">\n- <meta name=\"author\" content=\"{{ site.author }}\">\n- {% if page.categories %}<meta name=\"keywords\" content=\"{{ page.categories | join: ', ' }}\">{% endif %}\n+ <meta name=\"description\" content=\"{% if page.summary %}{{ page.summary | xml_escape }}{% else %}{{ site.description | xml_escape }}{% endif %}\">\n+ <meta name=\"author\" content=\"{{ site.author | xml_escape }}\">\n+ {% if page.categories %}<meta name=\"keywords\" content=\"{{ page.categories | join: ', ' | xml_escape }}\">{% endif %}\n <link rel=\"canonical\" href=\"{{ page.url | replace:'index.html','' | prepend: site.baseurl | prepend: site.url }}\">\n \n <!-- Custom CSS -->\n@@ -23,9 +23,9 @@\n <!-- From: https://github.com/mmistakes/hpstr-jekyll-theme/blob/master/_includes/head.html -->\n <meta property=\"og:locale\" content=\"en_US\">\n <meta property=\"og:type\" content=\"article\">\n- <meta property=\"og:title\" content=\"{% if page.title %}{{ page.title }}{% else %}{{ site.title }}{% endif %}\">\n- <meta property=\"og:description\" content=\"{% if page.description %}{{ page.description }}{% else %}{{ site.description }}{% endif %}\">\n+ <meta property=\"og:title\" content=\"{% if page.title %}{{ page.title | xml_escape }}{% else %}{{ site.title | xml_escape }}{% endif %}\">\n+ <meta property=\"og:description\" content=\"{% if page.description %}{{ page.description | xml_escape }}{% else %}{{ site.description | xml_escape }}{% endif %}\">\n <meta property=\"og:url\" content=\"{{ site.url }}{{ page.url }}\">\n- <meta property=\"og:site_name\" content=\"{{ site.title }}\">\n+ <meta property=\"og:site_name\" content=\"{{ site.title | xml_escape }}\">\n \n </head>\n\n<|file_patch|>_includes/pidtable.html\ndiff --git a/_includes/pidtable.html b/_includes/pidtable.html\nindex dce11c7093c620592f629f6062861f4a97cc01bc..2f23385be793c82791f9651fe33c4e83990fbf22 100644\n--- a/_includes/pidtable.html\n+++ b/_includes/pidtable.html\n@@ -10,7 +10,7 @@\n {% assign org = orgs|where:\"url\",orgpath|first %}\n <tr>\n <th><a href=\"{{pid.url}}\">{{urlparts[2]|upcase}}</a></th>\n- <td>{{org.title}} {{pid.title}}</td>\n+ <td>{{org.title|xml_escape}} {{pid.title|xml_escape}}</td>\n </tr>\n {% endif %}\n {% endfor %}\n\n<|file_patch|>_layouts/org.html\ndiff --git a/_layouts/org.html b/_layouts/org.html\nindex fc88afd26f39f65ef25a33bd2778470754bf1a50..015fa15318841b72802f3719c519b01c9736870e 100644\n--- a/_layouts/org.html\n+++ b/_layouts/org.html\n@@ -13,7 +13,7 @@\n <div class=\"measure\">\n <div class=\"post\">\n <header class=\"post-header\">\n- <h1 class=\"h2\">{{page.title}}</h1>\n+ <h1 class=\"h2\">{{page.title|xml_escape}}</h1>\n </header>\n <article class=\"post-content\">\n {{ content }}\n@@ -28,7 +28,7 @@\n <tr>\n <th><a href=\"/{{pidurlparts[1]}}/\">{{pidurlparts[1]}}</a></th>\n <th><a href=\"{{pid.url}}\">{{pidurlparts[2]}}</a></th>\n- <td>{{page.title}} {{pid.title}}</td>\n+ <td>{{page.title|xml_escape}} {{pid.title|xml_escape}}</td>\n </tr>\n {% endfor %}\n </table>\n\n<|file_patch|>_layouts/pid.html\ndiff --git a/_layouts/pid.html b/_layouts/pid.html\nindex f71bb49a9e24f60de671c2ff93dbc02279cdd6bc..326b443d8cdf5a7328dce6da39f381df58c93632 100644\n--- a/_layouts/pid.html\n+++ b/_layouts/pid.html\n@@ -17,22 +17,22 @@\n <div class=\"post\">\n <header class=\"post-header\">\n <h1 class=\"h2\">\n- \t<a href=\"/{{vid}}/\">{{vid}}</a> /\n+ \t<a href=\"/{{vid}}/\">{{vid|upcase}}</a> /\n {{pid|upcase}} -\n- {{page.title}}\n+ {{page.title|xml_escape}}\n </h1>\n </header>\n <article class=\"post-content\">\n <table>\n- <tr><th>VID</th><td>0x{{vid}}</td></tr>\n+ <tr><th>VID</th><td>0x{{vid|upcase}}</td></tr>\n <tr><th>PID</th><td>0x{{pid|upcase}}</td></tr>\n- <tr><th>Owner</th><td><a href=\"{{org.url}}\">{{org.title}}</a></td></tr>\n- <tr><th>License</th><td>{{page.license}}</td></tr>\n+ <tr><th>Owner</th><td><a href=\"{{org.url}}\">{{org.title|xml_escape}}</a></td></tr>\n+ <tr><th>License</th><td>{{page.license|xml_escape}}</td></tr>\n {% if page.site %}\n- <tr><th>Site</th><td><a href=\"{{page.site}}\">{{page.site}}</a></td></tr>\n+ <tr><th>Site</th><td><a href=\"{{page.site}}\">{{page.site|xml_escape}}</a></td></tr>\n {% endif %}\n {% if page.source %}\n- <tr><th>Source</th><td><a href=\"{{page.source}}\">{{page.source}}</a></td></tr>\n+ <tr><th>Source</th><td><a href=\"{{page.source}}\">{{page.source|xml_escape}}</a></td></tr>\n {% endif %}\n </table>\n {{ content }}\n\n<|file_patch|>about.md\ndiff --git a/about.md b/about.md\nindex 4f87eeaa079ecc89205bda8707c03689f415caf6..dc3b58e79da9597c9b0a5440136f06eff28bd193 100644\n--- a/about.md\n+++ b/about.md\n@@ -12,6 +12,6 @@ pid.codes seeks to solve this issue for anyone producing open-source hardware. W\n \n pid.codes will assign PIDs on any VID we own to any open-source hardware project needing one. To learn how to get a PID or PIDs for your project, see the [how to get a PID](/howto/) page.\n \n-pid.codes will also gladly accept donations of Vendor IDs from other organisations that no longer require them, and take responsibility for administering them. If you have a VID code that is no longer in use, please contact us at [admin@pid.codes](admin@pid.codes).\n+pid.codes will also gladly accept donations of Vendor IDs from other organisations that no longer require them, and take responsibility for administering them. If you have a VID code that is no longer in use, please contact us at [admin@pid.codes](mailto:admin@pid.codes).\n \n This site is in no way supported or endorsed by [USB-IF](http://www.usb.org/).\n\n<|file_patch|>index.html\ndiff --git a/index.html b/index.html\nindex 369852bffb53f6c8e1849cbc707283b6bcfaa85e..7ba1f1c6eb7b8d80a05b23743901ec2429b42a41 100644\n--- a/index.html\n+++ b/index.html\n@@ -16,15 +16,15 @@ layout: default\n <div class=\"post\">\n <a href=\"{{ post.url | prepend: site.baseurl }}\" class=\"post-link\">\n <p class=\"post-meta\">{{ post.date | date: \"%b %-d, %Y\" }}</p>\n- <h3 class=\"h2 post-title\">{{ post.title }}</h3>\n+ <h3 class=\"h2 post-title\">{{ post.title | xml_escape }}</h3>\n </a>\n- <p class=\"post-summary\">\n+ <div class=\"post-summary\">\n {% if post.summary %}\n {{ post.summary }}\n {% else %}\n {{ post.excerpt }}\n {% endif %}\n- </p>\n+ </div>\n </div>\n {% endfor %}\n </div>\n\n<|file_patch|>pids.md\ndiff --git a/pids.md b/pids.md\nindex d81b1767a5b512be0a868348cac43ad0dde80443..74097ad5e9897fedc230b0750e6c9802bb4129b7 100644\n--- a/pids.md\n+++ b/pids.md\n@@ -7,6 +7,6 @@ permalink: /pids/\n {% for vid in vids %}\n {% assign urlparts = vid.url|split:\"/\" %}\n {% assign vidno = urlparts[1] %}\n- <h3><a href=\"{{vid.url}}\">0x{{urlparts[1]}}</a></h3>\n+<h3><a href=\"{{vid.url}}\">0x{{vidno}}</a></h3>\n {%include pidtable.html vid=vidno %}\n {% endfor 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i18n dependency\n\n<|file_patch|>Gemfile\ndiff --git a/Gemfile b/Gemfile\nindex bbbdd53295e19add1f69053676a7c9afbafa5165..c3cef93cb7e158f8839cdacad3eff45d78b44a41 100644\n--- a/Gemfile\n+++ b/Gemfile\n@@ -12,6 +12,7 @@ group :runtime do # Runtime dependencies (as in the gemspec)\n if ENV['EXTLIB']\n gem 'extlib', '~> 0.9.15', SOURCE => \"#{DATAMAPPER}/extlib#{REPO_POSTFIX}\", :require => nil\n else\n+ gem 'i18n', '~> 0.5.0'\n gem 'activesupport', '~> 3.0.4', :require => nil\n end\n \n\n<|file_patch|>dm-migrations.gemspec\ndiff --git a/dm-migrations.gemspec b/dm-migrations.gemspec\nindex 4c02790e79a0df40dbd270801ba74687d336e3c4..37d3b1b1be065129baabeab28124991a35598c3c 100644\n--- a/dm-migrations.gemspec\n+++ b/dm-migrations.gemspec\n@@ -9,7 +9,7 @@ Gem::Specification.new do |s|\n \n s.required_rubygems_version = Gem::Requirement.new(\">= 0\") if s.respond_to? :required_rubygems_version=\n s.authors = [\"Paul Sadauskas\"]\n- s.date = %q{2011-02-18}\n+ s.date = %q{2011-02-19}\n s.description = %q{DataMapper plugin for writing and speccing migrations}\n s.email = %q{psadauskas [a] gmail [d] com}\n s.extra_rdoc_files = [\n@@ -104,12 +104,14 @@ Gem::Specification.new do |s|\n s.specification_version = 3\n \n if Gem::Version.new(Gem::VERSION) >= Gem::Version.new('1.2.0') then\n+ s.add_runtime_dependency(%q<i18n>, [\"~> 0.5.0\"])\n s.add_runtime_dependency(%q<activesupport>, [\"~> 3.0.4\"])\n s.add_runtime_dependency(%q<dm-core>, [\"~> 1.0.2\"])\n s.add_development_dependency(%q<rake>, [\"~> 0.8.7\"])\n s.add_development_dependency(%q<rspec>, [\"~> 1.3.1\"])\n s.add_development_dependency(%q<jeweler>, [\"~> 1.5.2\"])\n else\n+ s.add_dependency(%q<i18n>, [\"~> 0.5.0\"])\n s.add_dependency(%q<activesupport>, [\"~> 3.0.4\"])\n s.add_dependency(%q<dm-core>, [\"~> 1.0.2\"])\n s.add_dependency(%q<rake>, [\"~> 0.8.7\"])\n@@ -117,6 +119,7 @@ Gem::Specification.new do |s|\n s.add_dependency(%q<jeweler>, [\"~> 1.5.2\"])\n end\n else\n+ s.add_dependency(%q<i18n>, [\"~> 0.5.0\"])\n s.add_dependency(%q<activesupport>, [\"~> 3.0.4\"])\n s.add_dependency(%q<dm-core>, [\"~> 1.0.2\"])\n s.add_dependency(%q<rake>, [\"~> 0.8.7\"])\n\n"},"target_character_start":{"kind":"number","value":42,"string":"42"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":2223,"string":"2,223"},"document_order_key":{"kind":"number","value":2949258016549512000,"string":"2,949,258,016,549,512,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/datamapper/dm-migrations"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":1,"string":"1"},"primary_language":{"kind":"string","value":"ruby"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/datamapper/dm-migrations\",\"commit_oid\":\"9a3446f2cd8ce570c36df3fcfd04067a2de1f59d\",\"commits_ago_from_head\":113,\"content_sha256\":\"e6160b35c3627856c088326534aa3c52205ad7a9b1f20b8b2b45a2f4bf6b2ac1\",\"manifest_sha256\":null,\"parent_oid\":\"0c8b6088310ab9177f5ff4219bc9d0674b67b9c7\",\"repository_id\":\"github.com/datamapper/dm-migrations\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":1,\"deductions\":[{\"points\":2,\"reason\":\"throwaway_message\"},{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":4,\"repo_score_components\":{\"dependents_reach\":4,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":3,\"scope\":null,\"subject_length\":21,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":5,\"context_bytes\":6915,\"deleted_lines\":1,\"files_changed\":2,\"hunk_count\":4,\"patch_bytes\":2121,\"patch_sha256\":\"917f314a6179485ae074fe72df2d0560e84b865fcd09d770b67be27c133d2c87\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"ruby\",\"path\":\"Gemfile\",\"purpose\":\"dependency\"},{\"language\":null,\"path\":\"dm-migrations.gemspec\",\"purpose\":\"other\"}],\"primary_language\":\"ruby\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":6915,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":2,\"patch_bytes\":2121},\"commit_oid\":\"9a3446f2cd8ce570c36df3fcfd04067a2de1f59d\",\"identity\":{\"author_email\":\"dan.kubb@gmail.com\",\"author_name\":\"Dan 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Kubb\",\"parent_oid\":\"0c8b6088310ab9177f5ff4219bc9d0674b67b9c7\",\"tree_oid\":\"f524885875ad5a6772151e308b0a90c736f44041\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":396,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"ca96baac4072b7a4bf442c11da099c7f1461346d\",\"oldest_commit\":\"4f16b4be2a5087699b6d2dabcfd7c547a201628d\"},\"recorded_head_commit\":\"ca96baac4072b7a4bf442c11da099c7f1461346d\",\"repository_id\":\"github.com/datamapper/dm-migrations\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/datamapper/dm-migrations\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":89765,\"manifest_sha256\":null,\"split\":\"05-of-16\"}},\"parents\":[\"commit:github.com/datamapper/dm-migrations@9a3446f2cd8ce570c36df3fcfd04067a2de1f59d__download_changed_file_contents_bb985ea19f4c__render_commit_patches_5a0f8ab63137\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16077,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/alerta/docker-alerta@f716a98b8212436968229e6a5cdbdc97a2ca0ffe"},"text":{"kind":"string","value":"<|commit_message|>\nMove docker-compose tests to unit test dir\n\n<|file_patch|>Makefile\ndiff --git a/Makefile b/Makefile\nindex bf51964278daf7b6f2d175fc803ea2fc26265983..150981be1ae4cee700195f0cfa302e7c7b70170e 100644\n--- a/Makefile\n+++ b/Makefile\n@@ -23,12 +23,24 @@ all:\thelp\n lint:\n \tdocker run --rm -i hadolint/hadolint < Dockerfile\n \n-## test\t\t\t- Run integration tests.\n-test: env\n+## test.postgres\t\t- Run unit tests (Postgres).\n+test.postgres:\n \t@echo \"IMAGE_NAME=${IMAGE_NAME}\" >.env\n \t@echo \"VCS_REF=${VCS_REF}\" >>.env\n \t@echo \"VERSION=${VERSION}\" >>.env\n-\t$(DOCKER_COMPOSE) -f docker-compose.test.yml up \\\n+\t$(DOCKER_COMPOSE) -f tests/unit/docker-compose.postgres.yml up \\\n+\t--build \\\n+\t--renew-anon-volumes \\\n+\t--no-color \\\n+\t--exit-code-from tester\n+\t@echo \"IMAGE_NAME=${IMAGE_NAME}\" >.env\n+\n+## test.mongodb\t\t- Run unit tests (MongoDB).\n+test.mongodb:\n+\t@echo \"IMAGE_NAME=${IMAGE_NAME}\" >.env\n+\t@echo \"VCS_REF=${VCS_REF}\" >>.env\n+\t@echo \"VERSION=${VERSION}\" >>.env\n+\t$(DOCKER_COMPOSE) -f tests/unit/docker-compose.mongodb.yml up \\\n \t--build \\\n \t--renew-anon-volumes \\\n \t--no-color \\\n\n<|file_patch|>docker-compose.test.yml\ndiff --git a/docker-compose.test.yml b/docker-compose.test.yml\ndeleted file mode 100644\nindex d14023854a83135f83d71c621690142290cbed3d..0000000000000000000000000000000000000000\n--- a/docker-compose.test.yml\n+++ /dev/null\n@@ -1,51 +0,0 @@\n-version: '3'\n-\n-services:\n- sut:\n- build:\n- context: .\n- args:\n- VCS_REF: ${VCS_REF}\n- VERSION: ${VERSION}\n- # image: alerta/alerta-web\n- ports:\n- - 8080\n- depends_on:\n- - db\n- environment:\n- # - DEBUG=1 # remove this line to turn DEBUG off\n- - LOG_LEVEL=error # debug, info, warn (default), or error\n- - SECRET_KEY=super-secret\n- - DATABASE_URL=postgres://postgres:postgres@db:5432/monitoring\n- - AUTH_REQUIRED=tRuE\n- - ADMIN_USERS=admin@alerta.io,devops@alerta.io # default password: alerta\n- - ADMIN_KEY=demo-key\n- - ADMIN_KEY_MAXAGE=31536000 # 1 year in seconds\n- - PLUGINS=reject,blackout,normalise,enhance\n- - HK_EXPIRED_DELETE_HRS=39\n- - HK_INFO_DELETE_HRS=17\n- - HEARTBEAT_SEVERITY=warning\n- # Disable Housekeeping by setting one or both of HK env vars to a empty string\n- # - HK_EXPIRED_DELETE_HRS=\n- # - HK_INFO_DELETE_HRS=\n- # Disable hearbeat alerts by setting below env var to empty string\n- # - HEARTBEAT_SEVERITY=\n-\n- tester:\n- image: curlimages/curl:latest\n- volumes:\n- - ./wait-for:/wait-for\n- - ./tests.sh:/tests.sh\n- depends_on:\n- - sut\n- command: sh -c './wait-for sut:8080 -t 240 -- ./tests.sh'\n-\n- db:\n- image: postgres\n- volumes:\n- - ./pg-data:/var/lib/postgresql/data\n- environment:\n- POSTGRES_DB: monitoring\n- POSTGRES_USER: postgres\n- POSTGRES_PASSWORD: postgres\n-\n\n<|file_patch|>tests/unit/docker-compose.mongo.yml\ndiff --git a/tests/unit/docker-compose.mongo.yml b/tests/unit/docker-compose.mongo.yml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1c76759583c89d8a8efac604669a7603ea9a6bb7\n--- /dev/null\n+++ b/tests/unit/docker-compose.mongo.yml\n@@ -0,0 +1,46 @@\n+version: '3'\n+\n+services:\n+ sut:\n+ build:\n+ context: ../..\n+ args:\n+ VCS_REF: ${VCS_REF}\n+ VERSION: ${VERSION}\n+ ports:\n+ - 8080\n+ depends_on:\n+ - db\n+ environment:\n+ # - DEBUG=1 # remove this line to turn DEBUG off\n+ - LOG_LEVEL=error # debug, info, warn (default), or error\n+ - SECRET_KEY=super-secret\n+ - DATABASE_URL=mongodb://db:27017/monitoring\n+ - AUTH_REQUIRED=tRuE\n+ - ADMIN_USERS=admin@alerta.io,devops@alerta.io # default password: alerta\n+ - ADMIN_KEY=demo-key\n+ - ADMIN_KEY_MAXAGE=31536000 # 1 year in seconds\n+ - PLUGINS=reject,blackout,normalise,enhance\n+ - HK_EXPIRED_DELETE_HRS=39\n+ - HK_INFO_DELETE_HRS=17\n+ - HEARTBEAT_SEVERITY=warning\n+ # Disable Housekeeping by setting one or both of HK env vars to a empty string\n+ # - HK_EXPIRED_DELETE_HRS=\n+ # - HK_INFO_DELETE_HRS=\n+ # Disable hearbeat alerts by setting below env var to empty string\n+ # - HEARTBEAT_SEVERITY=\n+\n+ tester:\n+ image: curlimages/curl:latest\n+ volumes:\n+ - ./wait-for:/wait-for\n+ - ./tests.sh:/tests.sh\n+ depends_on:\n+ - sut\n+ command: sh -c './wait-for sut:8080 -t 240 -- ./tests.sh'\n+\n+ db:\n+ image: mongo\n+ volumes:\n+ - ./mongodb:/data/db\n+ restart: always\n\n<|file_patch|>tests/unit/docker-compose.postgres.yml\ndiff --git a/tests/unit/docker-compose.postgres.yml b/tests/unit/docker-compose.postgres.yml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..ac29b60a9fb0052609bf7adb3b0541dd5f572ce9\n--- /dev/null\n+++ b/tests/unit/docker-compose.postgres.yml\n@@ -0,0 +1,51 @@\n+version: '3'\n+\n+services:\n+ sut:\n+ build:\n+ context: ../..\n+ args:\n+ VCS_REF: ${VCS_REF}\n+ VERSION: ${VERSION}\n+ # image: alerta/alerta-web\n+ ports:\n+ - 8080\n+ depends_on:\n+ - db\n+ environment:\n+ # - DEBUG=1 # remove this line to turn DEBUG off\n+ - LOG_LEVEL=error # debug, info, warn (default), or error\n+ - SECRET_KEY=super-secret\n+ - DATABASE_URL=postgres://postgres:postgres@db:5432/monitoring\n+ - AUTH_REQUIRED=tRuE\n+ - ADMIN_USERS=admin@alerta.io,devops@alerta.io # default password: alerta\n+ - ADMIN_KEY=demo-key\n+ - ADMIN_KEY_MAXAGE=31536000 # 1 year in seconds\n+ - PLUGINS=reject,blackout,normalise,enhance\n+ - HK_EXPIRED_DELETE_HRS=39\n+ - HK_INFO_DELETE_HRS=17\n+ - HEARTBEAT_SEVERITY=warning\n+ # Disable Housekeeping by setting one or both of HK env vars to a empty string\n+ # - HK_EXPIRED_DELETE_HRS=\n+ # - HK_INFO_DELETE_HRS=\n+ # Disable hearbeat alerts by setting below env var to empty string\n+ # - HEARTBEAT_SEVERITY=\n+\n+ tester:\n+ image: curlimages/curl:latest\n+ volumes:\n+ - ./wait-for:/wait-for\n+ - ./tests.sh:/tests.sh\n+ depends_on:\n+ - sut\n+ command: sh -c './wait-for sut:8080 -t 240 -- ./tests.sh'\n+\n+ db:\n+ image: postgres\n+ volumes:\n+ - ./pg-data:/var/lib/postgresql/data\n+ environment:\n+ POSTGRES_DB: monitoring\n+ POSTGRES_USER: postgres\n+ POSTGRES_PASSWORD: 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Satterly\",\"authored_at\":\"2021-11-24T21:05:10+01:00\",\"commit_oid\":\"f716a98b8212436968229e6a5cdbdc97a2ca0ffe\",\"commits_ago_from_head\":63,\"committed_at\":\"2021-11-24T21:05:10+01:00\",\"committer_email\":\"nfsatterly@gmail.com\",\"committer_name\":\"Nick Satterly\",\"parent_oid\":\"2d75b249b272947c96d7a348b83af5c8e27bf9d0\",\"tree_oid\":\"12732c7bf986f75b7b0e4e7aa485b90801ecd7ea\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":435,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"b255b1f11e48221395f8ecaf6a1dbbd4c8366cb0\",\"oldest_commit\":\"6dca87984864d8131015ab5f7cc8aea6ed310bb7\"},\"recorded_head_commit\":\"b255b1f11e48221395f8ecaf6a1dbbd4c8366cb0\",\"repository_id\":\"github.com/alerta/docker-alerta\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/alerta/docker-alerta\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":18587,\"manifest_sha256\":null,\"split\":\"11-of-16\"}},\"parents\":[\"commit:github.com/alerta/docker-alerta@f716a98b8212436968229e6a5cdbdc97a2ca0ffe__download_changed_file_contents_2cf56c167909__render_commit_patches_12a781beec7d\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16078,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/angr/angr@14bfe7d52ac7033b070ad2873e8d1303f430dc3f"},"text":{"kind":"string","value":"<|commit_message|>\nz3 interrupts, threading, suggestions, and other fixes (#3462)\n\n* Add state option to control AUTO_REFS and stuff; disable by default\r\n\r\n* Fix LAZY_SOLVES\r\n\r\n* Add integration for new claripy error with 'interrupted' stash\r\n\r\n* remove deprecated exploration technique compatibility layer\r\n\r\n* fix threading exploration technique\r\n\r\n* Add suggestions technique; Make explorer find/avoid priority better\r\n\r\n* Make simgr locks picklable\r\n\r\n* lint\r\n\r\n* Fix preconstrainer expecting unsat timeout\r\n\r\n* Fix test_actions\n<|file_patch|>angr/engines/__init__.py\ndiff --git a/angr/engines/__init__.py b/angr/engines/__init__.py\nindex f37dbd48249bb02729ed5c0438d1829743278031..93ead0b7fbcbd2350f32218c6e32e89003abc31f 100644\n--- a/angr/engines/__init__.py\n+++ b/angr/engines/__init__.py\n@@ -1,5 +1,5 @@\n from .successors import SimSuccessors\n-from .engine import SimEngine, SuccessorsMixin\n+from .engine import SimEngine, SuccessorsMixin, TLSMixin\n \n from .vex import HeavyVEXMixin, TrackActionsMixin, SimInspectMixin, HeavyResilienceMixin, SuperFastpathMixin\n from .procedure import ProcedureMixin, ProcedureEngine\n@@ -23,7 +23,8 @@ class UberEngine(\n SimInspectMixin,\n HeavyResilienceMixin,\n SootMixin,\n- HeavyVEXMixin\n+ HeavyVEXMixin,\n+ TLSMixin,\n ):\n pass\n \n\n<|file_patch|>angr/engines/engine.py\ndiff --git a/angr/engines/engine.py b/angr/engines/engine.py\nindex 87ac525a9a6656c0ceff6f4a776e39044a8c05b3..31ed814ee33fc298382b4e618c044caeed58b32b 100644\n--- a/angr/engines/engine.py\n+++ b/angr/engines/engine.py\n@@ -1,3 +1,5 @@\n+# pylint: disable=no-self-use,unused-private-member\n+\n import abc\n import sys\n import logging\n@@ -25,7 +27,7 @@ class SimEngineBase:\n __tls = ('state',)\n \n def __getstate__(self):\n- return self.project,\n+ return (self.project,)\n \n def __setstate__(self, state):\n self.project = state[0]\n@@ -62,7 +64,7 @@ class TLSMixin:\n \"\"\"\n \n def __new__(cls, *args, **kwargs):\n- obj = super().__new__(cls, *args, **kwargs)\n+ obj = super().__new__(cls)\n obj.__local = threading.local()\n return obj\n \n\n<|file_patch|>angr/engines/procedure.py\ndiff --git a/angr/engines/procedure.py b/angr/engines/procedure.py\nindex 2d9de1976f416f9bc253150adf6e17aaee5e2d7f..0cda474c29ed6c8463d40b26ab4802a266ee68de 100644\n--- a/angr/engines/procedure.py\n+++ b/angr/engines/procedure.py\n@@ -28,7 +28,7 @@ class ProcedureMixin:\n if procedure.is_syscall:\n state._inspect('syscall', BP_BEFORE, syscall_name=procedure.display_name)\n \n- cleanup_options = o.AUTO_REFS not in state.options\n+ cleanup_options = o.AUTO_REFS not in state.options and o.ADD_AUTO_REFS in state.options\n if cleanup_options:\n state.options.add(o.AST_DEPS)\n state.options.add(o.AUTO_REFS)\n\n<|file_patch|>angr/exploration_techniques/__init__.py\ndiff --git a/angr/exploration_techniques/__init__.py b/angr/exploration_techniques/__init__.py\nindex 25501547415d42e359b059cbd87265d9dd1a16c7..2b0d04e7b2f0906f897fcc178aadbd3cdef12334 100644\n--- a/angr/exploration_techniques/__init__.py\n+++ b/angr/exploration_techniques/__init__.py\n@@ -1,42 +1,5 @@\n-import angr # type annotations; pylint:disable=unused-import,missing-class-docstring,wrong-import-position\n-\n-# 8<----------------- Compatibility layer -----------------\n-class ExplorationTechniqueMeta(type):\n- def __new__(cls, name, bases, attrs):\n- import inspect # pylint:disable=import-outside-toplevel\n- if name != 'ExplorationTechniqueCompat':\n- if 'step' in attrs and not inspect.getfullargspec(attrs['step']).defaults:\n- attrs['step'] = cls._step_factory(attrs['step'])\n- if 'filter' in attrs and inspect.getfullargspec(attrs['filter']).args[1] != 'simgr':\n- attrs['filter'] = cls._filter_factory(attrs['filter'])\n- if 'step_state' in attrs and inspect.getfullargspec(attrs['step_state']).args[1] != 'simgr':\n- attrs['step_state'] = cls._step_state_factory(attrs['step_state'])\n- return type.__new__(cls, name, bases, attrs)\n-\n- @staticmethod\n- def _step_factory(step):\n- def step_wrapped(self, simgr, stash='active', **kwargs):\n- return step(self, simgr, stash, **kwargs)\n- return step_wrapped\n-\n- @staticmethod\n- def _filter_factory(func): # pylint:disable=redefined-builtin\n- def filter_wrapped(self, simgr, state, filter_func=None):\n- result = func(self, state) # pylint:disable=no-value-for-parameter\n- if result is None:\n- result = simgr.filter(state, filter_func=filter_func)\n- return result\n- return filter_wrapped\n-\n- @staticmethod\n- def _step_state_factory(step_state):\n- def step_state_wrapped(self, simgr, state, successor_func=None, **kwargs):\n- result = step_state(self, state, **kwargs)\n- if result is None:\n- result = simgr.step_state(state, successor_func=successor_func, **kwargs)\n- return result\n- return step_state_wrapped\n-# ------------------- Compatibility layer --------------->8\n+# pylint:disable=unused-import,missing-class-docstring,wrong-import-position\n+import angr # type annotations\n \n \n class ExplorationTechnique:\n@@ -48,14 +11,7 @@ class ExplorationTechnique:\n \n Any number of these methods may be overridden by a subclass.\n To use an exploration technique, call ``simgr.use_technique`` with an *instance* of the technique.\n-\n- .. warning:: There is currently installed a compatibility layer for the previous version of this API. This\n- layer requires that implementations of ExplorationTechnique use the same argument names as the\n- original methods, or else it will mangle the behvior.\n \"\"\"\n- # 8<----------------- Compatibility layer -----------------\n- __metaclass__ = ExplorationTechniqueMeta\n- # ------------------- Compatibility layer --------------->8\n \n # this is the master list of hook functinos\n _hook_list = ('step', 'filter', 'selector', 'step_state', 'successors')\n@@ -190,3 +146,4 @@ from .memory_watcher import MemoryWatcher\n from .bucketizer import Bucketizer\n from .local_loop_seer import LocalLoopSeer\n from .timeout import Timeout\n+from .suggestions import Suggestions\n\n<|file_patch|>angr/exploration_techniques/explorer.py\ndiff --git a/angr/exploration_techniques/explorer.py b/angr/exploration_techniques/explorer.py\nindex 56cee6314ad061b863748ea8d3dbecde97ed1aa6..b26d8557bc05821ebb91aea821f07f9de902ee03 100644\n--- a/angr/exploration_techniques/explorer.py\n+++ b/angr/exploration_techniques/explorer.py\n@@ -1,13 +1,17 @@\n+import logging\n+import claripy\n+\n from . import ExplorationTechnique\n from .common import condition_to_lambda\n from .. import sim_options\n+from ..state_plugins.sim_event import resource_event\n \n-import logging\n l = logging.getLogger(name=__name__)\n \n class Explorer(ExplorationTechnique):\n \"\"\"\n- Search for up to \"num_find\" paths that satisfy condition \"find\", avoiding condition \"avoid\". Stashes found paths into \"find_stash' and avoided paths into \"avoid_stash\".\n+ Search for up to \"num_find\" paths that satisfy condition \"find\", avoiding condition \"avoid\". Stashes found paths\n+ into \"find_stash' and avoided paths into \"avoid_stash\".\n \n The \"find\" and \"avoid\" parameters may be any of:\n \n@@ -19,10 +23,20 @@ class Explorer(ExplorationTechnique):\n any paths which cannot possibly reach a success state without going through a failure state will be\n preemptively avoided.\n \n- If either the \"find\" or \"avoid\" parameter is a function returning a boolean, and a path triggers both conditions, it will be added to the find stash, unless \"avoid_priority\" is set to True.\n+ If either the \"find\" or \"avoid\" parameter is a function returning a boolean, and a path triggers both conditions,\n+ it will be added to the find stash, unless \"avoid_priority\" is set to True.\n \"\"\"\n- def __init__(self, find=None, avoid=None, find_stash='found', avoid_stash='avoid', cfg=None, num_find=1, avoid_priority=False):\n- super(Explorer, self).__init__()\n+ def __init__(\n+ self,\n+ find=None,\n+ avoid=None,\n+ find_stash='found',\n+ avoid_stash='avoid',\n+ cfg=None,\n+ num_find=1,\n+ avoid_priority=False\n+ ):\n+ super().__init__()\n self.find, static_find = condition_to_lambda(find)\n self.avoid, static_avoid = condition_to_lambda(avoid)\n self.find_stash = find_stash\n@@ -38,7 +52,7 @@ class Explorer(ExplorationTechnique):\n self._warned_unicorn = False\n \n # TODO: This is a hack for while CFGFast doesn't handle procedure continuations\n- from .. import analyses\n+ from .. import analyses # pylint: disable=import-outside-toplevel\n if isinstance(cfg, analyses.CFGFast):\n l.error(\"CFGFast is currently inappropriate for use with Explorer.\")\n l.error(\"Usage of the CFG has been disabled for this explorer.\")\n@@ -49,7 +63,7 @@ class Explorer(ExplorationTechnique):\n \n # we need the find addresses to be determined statically\n if not static_find:\n- l.error(\"You must provide at least one 'find' address as a number, set, list, or tuple if you provide a CFG.\")\n+ l.error(\"You must provide at least one numeric 'find' address if you provide a CFG.\")\n l.error(\"Usage of the CFG has been disabled for this explorer.\")\n self.cfg = None\n return\n@@ -88,26 +102,15 @@ class Explorer(ExplorationTechnique):\n l.warning(\"Providing an incomplete CFG can cause viable paths to be discarded!\")\n \n def setup(self, simgr):\n- if not self.find_stash in simgr.stashes: simgr.stashes[self.find_stash] = []\n- if not self.avoid_stash in simgr.stashes: simgr.stashes[self.avoid_stash] = []\n+ if not self.find_stash in simgr.stashes:\n+ simgr.stashes[self.find_stash] = []\n+ if not self.avoid_stash in simgr.stashes:\n+ simgr.stashes[self.avoid_stash] = []\n \n def step(self, simgr, stash='active', **kwargs):\n base_extra_stop_points = set(kwargs.pop(\"extra_stop_points\", []))\n return simgr.step(stash=stash, extra_stop_points=base_extra_stop_points | self._extra_stop_points, **kwargs)\n \n- def _classify(self, addr, findable, avoidable):\n- if self.avoid_priority:\n- if avoidable and (avoidable is True or addr in avoidable):\n- return self.avoid_stash\n- elif findable and (findable is True or addr in findable):\n- return self.find_stash\n- else:\n- if findable and (findable is True or addr in findable):\n- return self.find_stash\n- elif avoidable and (avoidable is True or addr in avoidable):\n- return self.avoid_stash\n- return None\n-\n # make it more natural to deal with the intended dataflow\n def filter(self, simgr, state, **kwargs):\n stash = self._filter_inner(state)\n@@ -121,18 +124,25 @@ class Explorer(ExplorationTechnique):\n l.warning(\"Unicorn may step over states that match the condition (find or avoid) without stopping.\")\n self._warned_unicorn = True\n \n- findable = self.find(state)\n- avoidable = self.avoid(state)\n-\n- if not findable and not avoidable:\n- if self.cfg is not None and self.cfg.model.get_any_node(state.addr) is not None:\n- if state.addr not in self.ok_blocks:\n+ try:\n+ if self.avoid_priority:\n+ avoidable = self.avoid(state)\n+ if avoidable and (avoidable is True or state.addr in avoidable):\n return self.avoid_stash\n- return None\n+ findable = self.find(state)\n+ if findable and (findable is True or state.addr in findable):\n+ return self.find_stash\n+ if not self.avoid_priority:\n+ avoidable = self.avoid(state)\n+ if avoidable and (avoidable is True or state.addr in avoidable):\n+ return self.avoid_stash\n+ except claripy.errors.ClaripySolverInterruptError as e:\n+ resource_event(state, e)\n+ return 'interrupted'\n \n- stash = self._classify(state.addr, findable, avoidable)\n- if stash is not None:\n- return stash\n+ if self.cfg is not None and self.cfg.model.get_any_node(state.addr) is not None:\n+ if state.addr not in self.ok_blocks:\n+ return self.avoid_stash\n \n return None\n \n\n<|file_patch|>angr/exploration_techniques/suggestions.py\ndiff --git a/angr/exploration_techniques/suggestions.py b/angr/exploration_techniques/suggestions.py\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..cd955a24c09b2c69542389ef862416300c506195\n--- /dev/null\n+++ b/angr/exploration_techniques/suggestions.py\n@@ -0,0 +1,157 @@\n+import logging\n+import claripy\n+\n+from . import ExplorationTechnique\n+from ..misc.ux import once\n+from ..misc.picklable_lock import PicklableLock\n+from ..state_plugins.sim_action import SimActionConstraint\n+from ..state_plugins.sim_action_object import SimActionObject\n+\n+l = logging.getLogger(__name__)\n+\n+def ast_weight(ast, memo=None):\n+ if isinstance(ast, SimActionObject):\n+ ast = ast.ast\n+ if not isinstance(ast, claripy.ast.Base):\n+ return 0\n+\n+ if memo is None:\n+ memo = {}\n+\n+ result = memo.get(ast.cache_key, None)\n+ if result is not None:\n+ return result\n+\n+ result = 1 + sum(ast_weight(arg, memo) for arg in ast.args)\n+ memo[ast.cache_key] = result\n+ return result\n+\n+\n+class Suggestions(ExplorationTechnique):\n+ \"\"\"\n+ An exploration technique which analyzes failure cases and logs suggestions for how to mitigate them in future\n+ analyses.\n+ \"\"\"\n+ def __init__(self):\n+ super().__init__()\n+ self.suggested = set()\n+ self.lock = PicklableLock()\n+\n+ def step(self, simgr, stash='active', **kwargs):\n+ simgr = simgr.step(stash=stash, **kwargs)\n+\n+ for state in simgr.stashes.get('interrupted', []):\n+ if id(state) in self.suggested:\n+ continue\n+ self.suggested.add(id(state))\n+\n+ try:\n+ event = state.history.events[-1]\n+ except IndexError:\n+ continue\n+ if event.type != 'insufficient_resources':\n+ continue\n+\n+ with self.lock: # do not interleave logs\n+ self.report(state, event)\n+\n+ return simgr\n+\n+ @staticmethod\n+ def report(state, event):\n+ if once('suggestion_technique'):\n+ l.warning(\"Some of your states hit a resource limit. set logger %s to INFO for suggestions.\", __name__)\n+ l.info(\"Create your simulation manager with `suggestions=False` to disable this.\")\n+\n+ if event.objects['type'] is claripy.errors.ClaripySolverInterruptError:\n+ if event.objects['reason'][0] == 'timeout':\n+ limit_number = state.solver._solver.timeout\n+ limit_kind = 'hit a solver timeout of %s ms.' % limit_number\n+ limit_minimum = 60 * 1000\n+ elif event.objects['reason'][0] == 'max. memory exceeded':\n+ limit_number = state.solver._solver.max_memory\n+ limit_kind = 'hit a solver memory limit of %s MB.' % limit_number\n+ limit_minimum = 1024\n+ else:\n+ limit_number = None\n+ limit_kind = 'hit an unknown resource limit. are you manually mucking with the z3 backend?'\n+ limit_minimum = None\n+ l.info('%s %s', state, limit_kind)\n+ if limit_number is not None and limit_minimum is not None and limit_number < limit_minimum:\n+ l.info(\"The minimum recommended limit is %s. Consider turning it up?\", limit_minimum)\n+\n+ log = []\n+ for history in state.history.lineage:\n+ for constraint_event in history.recent_events:\n+ if isinstance(constraint_event, SimActionConstraint):\n+ constraint = constraint_event.constraint.ast\n+ if constraint is history.jump_guard:\n+ src_addr = history.jump_source\n+ dst_addr = history.jump_target\n+ transition_type = 'jumping'\n+ else:\n+ if constraint_event.sim_procedure is None:\n+ src_addr = constraint_event.ins_addr\n+ else:\n+ src_addr = constraint_event.sim_procedure.addr\n+ block = state.block(src_addr, num_inst=2)\n+ try:\n+ dst_addr = block.instruction_addrs[1]\n+ except IndexError:\n+ dst_addr = history.jump_target\n+ transition_type = 'stepping'\n+ if type(dst_addr) is int:\n+ dst_addr = claripy.BVV(dst_addr, state.arch.bits)\n+ log.append((constraint, ast_weight(constraint), src_addr, dst_addr, transition_type, len(log)))\n+\n+ log.sort(key=lambda t: t[1], reverse=True)\n+ max_delta_idx = None\n+ if len(log) > 1:\n+ deltas = [b[1] - a[1] for a, b in zip(log, log[1:])]\n+ max_delta_idx, max_delta = max(enumerate(deltas))\n+ if max_delta < 2**10:\n+ max_delta_idx = None\n+ if max_delta_idx is None and log and log[0][1] >= 2**16:\n+ for max_delta_idx, t in enumerate(log):\n+ if t[1] < 2**16:\n+ max_delta_idx -= 1\n+ break\n+ if max_delta_idx is not None:\n+ l.info(\n+ \"%d constraint%s abnormally complex.\",\n+ max_delta_idx + 1,\n+ 's are' if max_delta_idx > 0 else ' is'\n+ )\n+ descriptions = []\n+ for t in sorted(log[:max_delta_idx+1], key=lambda t: t[5]):\n+ if max_delta_idx < 10:\n+ l.info(\n+ \"...generated %s from %s to %s\",\n+ t[4],\n+ state.project.loader.describe_addr(t[2]),\n+ state.project.loader.describe_addr(t[3].args[0])\n+ if t[3].op == 'BVV' else '<symbol>'\n+ )\n+ descriptions.extend(state.solver.describe_variables(t[0]))\n+ descriptions = set(descriptions)\n+ seen_apis = set()\n+ for description in descriptions:\n+ if description[0] == 'api':\n+ if description[1] not in seen_apis:\n+ seen_apis.add(description[1])\n+ l.info(\"...using variables originating in %s (hook it?)\", description[1])\n+ elif description[0] == 'mem':\n+ if '##mem' not in seen_apis:\n+ seen_apis.add('##mem')\n+ l.info(\"...using unconstrained memory (add ZERO_FILL_UNCONSTRAINED_MEMORY?)\")\n+ elif description[0] == 'reg':\n+ if '##reg' not in seen_apis:\n+ seen_apis.add('##reg')\n+ l.info(\"...using unconstrained registers (add ZERO_FILL_UNCONSTRAINED_REGISTERS?)\")\n+ elif description[0] == 'file':\n+ api = 'file##' + description[1]\n+ if api not in seen_apis:\n+ seen_apis.add(api)\n+ l.info(\"...using variables from file %s\", description[1])\n+ else:\n+ l.info(\"...using uncategorized variable %s\", description)\n\n<|file_patch|>angr/exploration_techniques/threading.py\ndiff --git a/angr/exploration_techniques/threading.py b/angr/exploration_techniques/threading.py\nindex b3c1c20a2c96846305403a7485c3c3d955c65c0b..acf708f39194b8ed7a270316293b810355c46046 100644\n--- a/angr/exploration_techniques/threading.py\n+++ b/angr/exploration_techniques/threading.py\n@@ -1,7 +1,12 @@\n # pylint: disable=cell-var-from-loop\n import concurrent.futures\n+import logging\n \n from . import ExplorationTechnique\n+from ..engines.engine import TLSMixin\n+from ..misc.ux import once\n+\n+l = logging.getLogger(__name__)\n \n class Threading(ExplorationTechnique):\n \"\"\"\n@@ -10,31 +15,63 @@ class Threading(ExplorationTechnique):\n This is only useful in paths where a lot of time is taken inside z3, doing constraint solving.\n This is because of python's GIL, which says that only one thread at a time may be executing python code.\n \"\"\"\n- def __init__(self, threads=8):\n+ def __init__(self, threads=8, local_stash='thread_local'):\n super(Threading, self).__init__()\n self.threads = threads\n+ self.queued = set()\n+ self.tasks = set()\n self.executor = concurrent.futures.ThreadPoolExecutor(max_workers=threads)\n+ self.local_stash = local_stash\n+\n+ def step(self, simgr, stash='active', error_list=None, target_stash=None, **kwargs):\n+ target_stash = target_stash or stash\n+ if error_list is not None:\n+ raise ValueError(\"Can't pass error_list to step with threading enabled. Did you install threading twice?\")\n+\n+ l.info(\"Thread-stepping %s of %s\", stash, simgr)\n \n- def step(self, simgr, stash='active', **kwargs):\n- counts = [0]*self.threads\n- def counts_of(i):\n- out = counts[i]\n- counts[i] = out + 1\n- return out\n-\n- tasks = {}\n- for x in range(self.threads):\n- # construct new simgr with lists w/ object identity\n- # move every nth thread into a unique thread-local list\n- # this means that threads won't trample each other's hooks\n+ for state in simgr.stashes[stash]:\n+ if state in self.queued:\n+ continue\n+\n+ # construct new simgr with new lists\n+ # this means that threads won't trample each other's hook stacks\n # but can still negotiate over shared resources\n+ tsimgr = simgr.copy()\n+ tsimgr._stashes = {self.local_stash: [state]}\n+ tsimgr._errored = []\n+ self.tasks.add(self.executor.submit(self.inner_step, state, tsimgr, target_stash=target_stash, **kwargs))\n+ self.queued.add(state)\n \n- tsimgr = simgr.copy(stashes=dict(simgr.stashes))\n- tsimgr.stashes['threadlocal'] = []\n- tsimgr.move(stash, 'threadlocal', lambda path: counts_of(x) % self.threads == x)\n- tasks[self.executor.submit(tsimgr.step, stash='threadlocal', **kwargs)] = tsimgr\n+ timeout = None\n+ while True:\n+ done, self.tasks = concurrent.futures.wait(\n+ self.tasks,\n+ timeout=timeout,\n+ return_when=concurrent.futures.FIRST_COMPLETED\n+ )\n+ if not done:\n+ break\n \n- for f in concurrent.futures.as_completed(tasks):\n- simgr.populate(stash, tasks[f].threadlocal)\n+ for done_future in done:\n+ done_future: concurrent.futures.Future\n+ state, error_list, tsimgr = done_future.result()\n+ simgr.absorb(tsimgr)\n+ simgr.errored.extend(error_list)\n+ simgr.stashes[stash].remove(state)\n+ self.queued.remove(state)\n+ timeout = 0\n \n return simgr\n+\n+ def inner_step(self, state, simgr, **kwargs):\n+ error_list = []\n+ simgr.step(stash=self.local_stash, error_list=error_list, **kwargs)\n+ return state, error_list, simgr\n+\n+ def successors(self, simgr, state, engine=None, **kwargs):\n+ engine = engine or self.project.factory.default_engine\n+ if not isinstance(engine, TLSMixin) and once(\"tls_engine\"):\n+ l.error(\"Using Threading exploration technique but your engine is not thread-safe.\")\n+ l.error(\"Do you want to add the TLSMixin to your engine?\")\n+ return simgr.successors(state, engine=engine, **kwargs)\n\n<|file_patch|>angr/misc/hookset.py\ndiff --git a/angr/misc/hookset.py b/angr/misc/hookset.py\nindex 18e51f35ee98d6aa4e497d2176833a2009eb5810..4114dd0612ecd35f7a1b7d73e0f9cfde8b98171c 100644\n--- a/angr/misc/hookset.py\n+++ b/angr/misc/hookset.py\n@@ -45,6 +45,21 @@ class HookSet:\n if not hooked.pending:\n setattr(target, name, hooked.func)\n \n+ @staticmethod\n+ def copy_hooks(source, target, domain):\n+ \"\"\"\n+ Copy the hooks from source onto target.\n+\n+ If the current callstack includes hooked methods from source, the already-called methods will not be included in\n+ the copy.\n+\n+ ``domain`` is a list of names that might be hooked.\n+ \"\"\"\n+ for name in domain:\n+ hooked = getattr(source, name)\n+ if isinstance(hooked, HookedMethod):\n+ setattr(target, name, hooked.copy_to(getattr(target, name)))\n+\n \n class HookedMethod:\n \"\"\"\n@@ -78,3 +93,8 @@ class HookedMethod:\n return result\n else:\n return self.func(*args, **kwargs)\n+\n+ def copy_to(self, new_func):\n+ new_hooked = HookedMethod(new_func)\n+ new_hooked.pending = list(self.pending)\n+ return new_hooked\n\n<|file_patch|>angr/misc/picklable_lock.py\ndiff --git a/angr/misc/picklable_lock.py b/angr/misc/picklable_lock.py\nindex 9067e1554d8def2c46b46c7a638f9a443331cbbb..2f3aab75720369ca70b91c855931979f24eb2f56 100644\n--- a/angr/misc/picklable_lock.py\n+++ b/angr/misc/picklable_lock.py\n@@ -1,8 +1,14 @@\n import threading\n \n class PicklableLock:\n- def __init__(self):\n- self._lock = threading.Lock()\n+ \"\"\"\n+ Normal thread-locks are not pickleable. This provides a pickleable lock by mandating that the lock is unlocked\n+ during serialization.\n+ \"\"\"\n+ _LOCK = threading.Lock\n+\n+ def __init__(self, *args, **kwargs):\n+ self._lock = self._LOCK(*args, **kwargs) # pylint: disable=too-many-function-args\n \n def __enter__(self):\n return self._lock.__enter__()\n@@ -10,8 +16,8 @@ class PicklableLock:\n def __exit__(self, exc_type, exc_val, exc_tb):\n return self._lock.__exit__(exc_type, exc_val, exc_tb)\n \n- def acquire(self, blocking, timeout):\n- return self._lock.acquire(blocking, timeout)\n+ def acquire(self, *args, **kwargs):\n+ return self._lock.acquire(*args, **kwargs)\n \n def locked(self):\n return self._lock.locked()\n@@ -23,3 +29,13 @@ class PicklableLock:\n if self.locked():\n raise TypeError(\"Why are you pickling a locked lock\")\n return type(self), ()\n+\n+class PicklableRLock(PicklableLock):\n+ \"\"\"\n+ Same as above, but uses RLock instead of Lock for locking. Note that RLock does not provide an interface to tell\n+ whether is it presently held by any thread, and thus this class will lie about whether it is locked.\n+ \"\"\"\n+ _LOCK = threading.RLock\n+\n+ def locked(self):\n+ return False # ummmmmmmmmmmmmmmm\n\n<|file_patch|>angr/sim_options.py\ndiff --git a/angr/sim_options.py b/angr/sim_options.py\nindex 1b1dad9d68b8ce95c82478b3588a2aae15d69bf8..a423a007ba6feefdbbc4be61682966eae3a5267d 100644\n--- a/angr/sim_options.py\n+++ b/angr/sim_options.py\n@@ -112,6 +112,7 @@ CONSTRAINT_TRACKING_IN_SOLVER = \"CONSTRAINT_TRACKING_IN_SOLVER\"\n \n # this is an internal option to automatically track dependencies in SimProcedures\n AUTO_REFS = \"AUTO_REFS\"\n+ADD_AUTO_REFS = \"ADD_AUTO_REFS\"\n \n # Whether we should track dependencies in SimActions\n # If none of the ref options above exist, this option does nothing\n\n<|file_patch|>angr/state_hierarchy.py\ndiff --git a/angr/state_hierarchy.py b/angr/state_hierarchy.py\nindex 649f4f7fc86d14fb4c0d0bd5be6c7a7931708514..a3255c0d2d8abe2dffc549022169749fe28456dd 100644\n--- a/angr/state_hierarchy.py\n+++ b/angr/state_hierarchy.py\n@@ -7,6 +7,8 @@ import networkx\n \n import claripy\n \n+from .misc.picklable_lock import PicklableRLock\n+\n l = logging.getLogger(name=__name__)\n \n \n@@ -26,6 +28,7 @@ class StateHierarchy:\n self._reverse_weakref_cache = {} # map from weakref to object id\n self._pending_cleanup = set()\n self._defer_cleanup = False\n+ self._lock = PicklableRLock()\n \n def __getstate__(self):\n gc.collect()\n@@ -71,20 +74,22 @@ class StateHierarchy:\n @contextmanager\n def defer_cleanup(self):\n old_defer, self._defer_cleanup = self._defer_cleanup, True\n- yield\n- self._defer_cleanup = old_defer\n- if not self._defer_cleanup:\n- toclean = list(self._pending_cleanup)\n- self._pending_cleanup.clear()\n- for ref in toclean:\n- self._cleanup_ref(ref)\n+ try:\n+ yield\n+ finally:\n+ self._defer_cleanup = old_defer\n+ if not self._defer_cleanup:\n+ toclean = list(self._pending_cleanup)\n+ self._pending_cleanup.clear()\n+ for ref in toclean:\n+ self._cleanup_ref(ref)\n \n #\n # Graph management\n #\n \n def _remove_history(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n try:\n predecessors = self._graph.predecessors(h)\n successors = self._graph.successors(h)\n@@ -107,7 +112,7 @@ class StateHierarchy:\n self.add_history(h)\n \n def add_history(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n cur_node = self.get_ref(h)\n self._graph.add_node(cur_node)\n if h.parent is not None:\n@@ -123,13 +128,12 @@ class StateHierarchy:\n self._leaves.add(cur_node)\n \n def simplify(self):\n- tw = self._twigs\n- self._twigs = set()\n+ tw, self._twigs = self._twigs, set()\n for h in tw:\n self._remove_history(h)\n \n def full_simplify(self):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n for h in self._graph.nodes():\n if self._graph.out_degree(h) == 1:\n self._remove_history(h)\n@@ -139,7 +143,7 @@ class StateHierarchy:\n Returns the lineage of histories leading up to `h`.\n \"\"\"\n \n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n lineage = [ ]\n \n predecessors = list(self._graph.predecessors(h))\n@@ -151,21 +155,21 @@ class StateHierarchy:\n return lineage\n \n def all_successors(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n nodes = list(networkx.algorithms.dfs_postorder_nodes(self._graph, h))[:-1]\n nodes.reverse()\n return nodes\n \n def history_successors(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n return [ ref() for ref in self._graph.successors(self.get_ref(h)) ]\n \n def history_predecessors(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n return [ ref() for ref in self._graph.predecessors(self.get_ref(h)) ]\n \n def history_contains(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n return self.get_ref(h) in self._graph\n \n #\n@@ -199,7 +203,7 @@ class StateHierarchy:\n bad = cur\n \n def _prune_subtree(self, h):\n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n ph = list(self._graph.predecessors(h))\n if len(ph) == 1 and len(list(self._graph.successors(ph[0]))) == 1:\n self._twigs.add(ph[0])\n@@ -207,8 +211,11 @@ class StateHierarchy:\n all_children = list(networkx.algorithms.dfs_postorder_nodes(self._graph, h))\n for n in all_children:\n n()._satisfiable = False\n- if n().state is not None:\n- n().state.add_constraints(claripy.false)\n+ try:\n+ if n().state is not None:\n+ n().state.add_constraints(claripy.false)\n+ except ReferenceError:\n+ pass\n self._graph.remove_nodes_from(all_children)\n \n def unreachable_state(self, state):\n@@ -217,14 +224,15 @@ class StateHierarchy:\n def unreachable_history(self, h):\n href = self.get_ref(h)\n \n- try:\n- l.debug(\"Pruning tree given unreachable %s\", h)\n- root = self._find_root_unreachable(href)\n- except networkx.NetworkXError:\n- l.debug(\"... not present in graph\")\n- else:\n- l.debug(\"... root is %s\", root)\n- self._prune_subtree(root)\n+ with self._lock:\n+ try:\n+ l.debug(\"Pruning tree given unreachable %s\", h)\n+ root = self._find_root_unreachable(href)\n+ except networkx.NetworkXError:\n+ l.debug(\"... not present in graph\")\n+ else:\n+ l.debug(\"... root is %s\", root)\n+ self._prune_subtree(root)\n \n #\n # Smart merging support\n@@ -238,7 +246,7 @@ class StateHierarchy:\n :returns: a tuple of: (list of states to merge, those states' common history, list of states to not merge yet)\n \"\"\"\n \n- with self.defer_cleanup():\n+ with self.defer_cleanup(), self._lock:\n histories = set(self.get_ref(s.history) for s in states)\n \n for n in networkx.algorithms.dfs_postorder_nodes(self._graph):\n\n<|file_patch|>angr/state_plugins/history.py\ndiff --git a/angr/state_plugins/history.py b/angr/state_plugins/history.py\nindex a99dc87d3dc2e5e3d29619e4863bcdf18f8e1803..5cd589cb71d7d6f38362a70d8744a1c8dc761bd2 100644\n--- a/angr/state_plugins/history.py\n+++ b/angr/state_plugins/history.py\n@@ -322,13 +322,18 @@ class SimStateHistory(SimStatePlugin):\n \n def reachable(self):\n if self._satisfiable is not None:\n- pass\n- elif self.state is not None:\n- self._satisfiable = self.state.solver.satisfiable()\n- else:\n- solver = claripy.Solver()\n- solver.add(self._all_constraints)\n- self._satisfiable = solver.satisfiable()\n+ return self._satisfiable\n+\n+ if self.state is not None:\n+ try:\n+ self._satisfiable = self.state.solver.satisfiable()\n+ return self._satisfiable\n+ except ReferenceError:\n+ pass\n+\n+ solver = claripy.Solver()\n+ solver.add(self._all_constraints)\n+ self._satisfiable = solver.satisfiable()\n \n return self._satisfiable\n \n\n<|file_patch|>angr/state_plugins/preconstrainer.py\ndiff --git a/angr/state_plugins/preconstrainer.py b/angr/state_plugins/preconstrainer.py\nindex d0c9c07b9642b1cd81dfe48d5a0bb3489bd26860..09d06a621652dd0d4f2cc82e9d0346cbd308c3c3 100644\n--- a/angr/state_plugins/preconstrainer.py\n+++ b/angr/state_plugins/preconstrainer.py\n@@ -145,7 +145,7 @@ class SimStatePreconstrainer(SimStatePlugin):\n if o.REPLACEMENT_SOLVER in self.state.options:\n new_constraints = self.state.solver.constraints\n else:\n- new_constraints = list(filter(lambda x: x.cache_key not in precon_cache_keys, self.state.solver.constraints))\n+ new_constraints = [x for x in self.state.solver.constraints if x.cache_key not in precon_cache_keys]\n \n \n if self.state.has_plugin(\"zen_plugin\"):\n@@ -175,7 +175,9 @@ class SimStatePreconstrainer(SimStatePlugin):\n \n for solver in subsolvers:\n solver.timeout = 1000 * 10 # 10 seconds\n- if not solver.satisfiable():\n+ try:\n+ solver.satisfiable()\n+ except claripy.errors.ClaripySolverInterruptError:\n for var in solver.variables:\n if var in self.variable_map:\n self.state.add_constraints(self.variable_map[var])\n\n<|file_patch|>angr/state_plugins/sim_event.py\ndiff --git a/angr/state_plugins/sim_event.py b/angr/state_plugins/sim_event.py\nindex 38fad3cbaff476ad165d247b74dc65168dd37950..d045491c696d63177efb422fbef82a55d09f7924 100644\n--- a/angr/state_plugins/sim_event.py\n+++ b/angr/state_plugins/sim_event.py\n@@ -1,7 +1,14 @@\n+import traceback\n import itertools\n event_id_count = itertools.count()\n \n-class SimEvent(object):\n+class SimEvent:\n+ \"\"\"\n+ A SimEvent is a log entry for some notable event during symbolic execution. It logs the location it was generated\n+ (ins_addr, bbl_addr, stmt_idx, and sim_procedure) as well as arbitrary tags (objects).\n+\n+ You may also be interested in SimAction, which is a specialization of SimEvent for CPU events.\n+ \"\"\"\n #def __init__(self, address=None, stmt_idx=None, message=None, exception=None, traceback=None):\n def __init__(self, state, event_type, **kwargs):\n self.id = next(event_id_count)\n@@ -14,7 +21,7 @@ class SimEvent(object):\n self.arch = state.arch\n \n def __repr__(self):\n- return \"<SimEvent %s %d, with fields %s>\" % (self.type, self.id, self.objects.keys())\n+ return \"<SimEvent %s %d, with fields %s>\" % (self.type, self.id, ', '.join(self.objects.keys()))\n \n def _copy_event(self):\n c = self.__class__.__new__(self.__class__)\n@@ -26,3 +33,20 @@ class SimEvent(object):\n c.objects = dict(self.objects)\n \n return c\n+\n+def resource_event(state, exception):\n+ for frame, lineno in reversed(list(traceback.walk_tb(exception.__traceback__))):\n+ module = frame.f_globals.get('__name__', '').split('.')\n+ function = frame.f_code.co_name\n+ if module[0] == 'claripy' or \\\n+ module in (['angr', 'state_plugins', 'solver'], ['angr', 'state_plugins', 'sim_action_object']):\n+ continue\n+ state.history.add_event(\n+ \"insufficient_resources\",\n+ module=module,\n+ function=function,\n+ lineno=lineno,\n+ type=type(exception),\n+ reason=exception.args\n+ )\n+ break\n\n<|file_patch|>tests/test_actions.py\ndiff --git a/tests/test_actions.py b/tests/test_actions.py\nindex 9a1d71d3213ed914d8173a9a8ee2507946f9d67e..6cf10d2684883c843c718ffc9ba842048bd9406e 100644\n--- a/tests/test_actions.py\n+++ b/tests/test_actions.py\n@@ -11,7 +11,7 @@ FAKE_ADDR = 0x100000\n # pylint: disable=no-self-use\n class TestActions(unittest.TestCase):\n def test_procedure_actions(self):\n- s = SimState(arch='AMD64')\n+ s = SimState(arch='AMD64', add_options={angr.options.ADD_AUTO_REFS})\n \n s.registers.store('rbx', 2)\n proc = SIM_PROCEDURES['testing']['retreg'](reg='rbx')\n\n"},"target_character_start":{"kind":"number","value":533,"string":"533"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":39471,"string":"39,471"},"document_order_key":{"kind":"number","value":2949982828531449300,"string":"2,949,982,828,531,449,300"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/angr/angr"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":true,"string":"true"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":6,"string":"6"},"primary_language":{"kind":"string","value":"python"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/angr/angr\",\"commit_oid\":\"14bfe7d52ac7033b070ad2873e8d1303f430dc3f\",\"commits_ago_from_head\":3240,\"content_sha256\":\"92aa0fd17a833d87256b9cbd9cb14275dc62775c968f744ba3da17df3019e204\",\"manifest_sha256\":null,\"parent_oid\":\"195c8abe2b6c67e3e22fc118f1b048b760046225\",\"repository_id\":\"github.com/angr/angr\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":6,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"}],\"repo_score\":7,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":2,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#3462\"],\"message_words\":70,\"scope\":null,\"subject_length\":62,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":387,\"context_bytes\":87741,\"deleted_lines\":147,\"files_changed\":15,\"hunk_count\":42,\"patch_bytes\":38261,\"patch_sha256\":\"83c54e4496e41479299eb87384f958da77a258943f689eb643013475ce6c0d28\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"python\",\"path\":\"angr/engines/__init__.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/engines/engine.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/engines/procedure.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/exploration_techniques/__init__.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/exploration_techniques/explorer.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/exploration_techniques/suggestions.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/exploration_techniques/threading.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/misc/hookset.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/misc/picklable_lock.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/sim_options.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/state_hierarchy.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/state_plugins/history.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/state_plugins/preconstrainer.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"angr/state_plugins/sim_event.py\",\"purpose\":\"source\"},{\"language\":\"python\",\"path\":\"tests/test_actions.py\",\"purpose\":\"tests\"}],\"primary_language\":\"python\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[\"tests/test_actions.py\"],\"touched\":true},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":87741,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":16,\"files_kept\":15,\"patch_bytes\":38261},\"commit_oid\":\"14bfe7d52ac7033b070ad2873e8d1303f430dc3f\",\"identity\":{\"author_email\":\"audrey@rhelmot.io\",\"author_name\":\"Audrey Dutcher\",\"authored_at\":\"2022-07-29T16:32:18-07:00\",\"commit_oid\":\"14bfe7d52ac7033b070ad2873e8d1303f430dc3f\",\"commits_ago_from_head\":3240,\"committed_at\":\"2022-07-29T16:32:18-07:00\",\"committer_email\":\"noreply@github.com\",\"committer_name\":\"GitHub\",\"parent_oid\":\"195c8abe2b6c67e3e22fc118f1b048b760046225\",\"tree_oid\":\"e5ec07bbf94e958f2281bb004a71c1d5c451c0fd\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"angr/sim_manager.py\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"503b1be0663e65de225194eeb8e2cee6fa20d8d3\",\"oldest_commit\":\"d6b83cd402acbd884761f9d1dadff6f0942091b8\"},\"recorded_head_commit\":\"503b1be0663e65de225194eeb8e2cee6fa20d8d3\",\"repository_id\":\"github.com/angr/angr\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/angr/angr\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":28416,\"manifest_sha256\":null,\"split\":\"06-of-10\"}},\"parents\":[\"commit:github.com/angr/angr@14bfe7d52ac7033b070ad2873e8d1303f430dc3f__download_changed_file_contents_626a439e0370__drop_changed_files_over_maximum_character_count_285e6fcc1bd6__render_commit_patches_399339e2fa98\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16079,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/alex-d/trumbowyg@617b374e35cdebebe1be43c1e518cae5e76d9918"},"text":{"kind":"string","value":"<|commit_message|>\ndocs: upgrade used Trumbowyg version to v2.27.2\n\n<|file_patch|>docs/demos/js/loader.js\ndiff --git a/docs/demos/js/loader.js b/docs/demos/js/loader.js\nindex 80cb3abd02b97beba3d1dec381fc612688585089..bbf3356b51d9567db53efe3e44ff3ce98c83e81f 100644\n--- a/docs/demos/js/loader.js\n+++ b/docs/demos/js/loader.js\n@@ -1,5 +1,5 @@\n var isOnline = window.location.hostname.indexOf('github.io') !== -1;\n-var baseURL = isOnline ? '//rawcdn.githack.com/Alex-D/Trumbowyg/v2.27.1/' : '../../../';\n+var baseURL = isOnline ? '//rawcdn.githack.com/Alex-D/Trumbowyg/v2.27.2/' : '../../../';\n var styleLoadingContainer = document.querySelector('.loading-head');\n var scriptLoadingContainer = document.querySelector('.loading-body');\n \n\n"},"target_character_start":{"kind":"number","value":68,"string":"68"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":735,"string":"735"},"document_order_key":{"kind":"number","value":2950031279388649500,"string":"2,950,031,279,388,649,500"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/alex-d/trumbowyg"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"javascript"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/alex-d/trumbowyg\",\"commit_oid\":\"617b374e35cdebebe1be43c1e518cae5e76d9918\",\"commits_ago_from_head\":86,\"content_sha256\":\"f21570912912c21b8bc90bfaf5c9b38a7182e6adbf04dbf5869d8dd4417af191\",\"manifest_sha256\":null,\"parent_oid\":\"c9aaa6d1b56e8c552bf069f037c5e9a423f6adcd\",\"repository_id\":\"github.com/alex-d/trumbowyg\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"},{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":5,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":7,\"scope\":null,\"subject_length\":41,\"trailer_names\":[],\"type\":\"docs\"},\"patch_statistics\":{\"added_lines\":1,\"context_bytes\":1502,\"deleted_lines\":1,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":628,\"patch_sha256\":\"51495ba585f77e4d0390ef9164d0f0ac0a8a81ecc3aeaafd8b076fc689c1f345\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"javascript\",\"path\":\"docs/demos/js/loader.js\",\"purpose\":\"docs\"}],\"primary_language\":\"javascript\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":1502,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":1,\"patch_bytes\":628},\"commit_oid\":\"617b374e35cdebebe1be43c1e518cae5e76d9918\",\"identity\":{\"author_email\":\"contact@alex-d.fr\",\"author_name\":\"Alex-D\",\"authored_at\":\"2023-02-27T18:40:34+01:00\",\"commit_oid\":\"617b374e35cdebebe1be43c1e518cae5e76d9918\",\"commits_ago_from_head\":86,\"committed_at\":\"2023-02-27T18:40:34+01:00\",\"committer_email\":\"contact@alex-d.fr\",\"committer_name\":\"Alex-D\",\"parent_oid\":\"c9aaa6d1b56e8c552bf069f037c5e9a423f6adcd\",\"tree_oid\":\"cfb887f466a5fdd5068b049a159a5effe56af5ee\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"docs/index.html\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"develop\",\"history_collected\":{\"commits_read\":1461,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"c3ae7d60409a9f20478eb9d5e24ba50882b328b5\",\"oldest_commit\":\"d65f8c4e2a98436e40d2b7fed0d68f1d1d3f8c7d\"},\"recorded_head_commit\":\"c3ae7d60409a9f20478eb9d5e24ba50882b328b5\",\"repository_id\":\"github.com/alex-d/trumbowyg\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/alex-d/trumbowyg\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":18637,\"manifest_sha256\":null,\"split\":\"13-of-16\"}},\"parents\":[\"commit:github.com/alex-d/trumbowyg@617b374e35cdebebe1be43c1e518cae5e76d9918__download_changed_file_contents_61c42dbad5e6__drop_changed_files_over_maximum_character_count_25c096d1da1d__render_commit_patches_7efb0b13fde5\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16080,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/buglabs/android_external_busybox@4662de0511487b4da965c4b2158bae318f3d80a8"},"text":{"kind":"string","value":"<|commit_message|>\nreplace APP_xxDHCPxx with xxDHCPxx, it's more consistent with the rest\n\nSigned-off-by: Denys Vlasenko <vda.linux@googlemail.com>\n\n<|file_patch|>TODO_config_nommu\ndiff --git a/TODO_config_nommu b/TODO_config_nommu\nindex 1835b6e80b6cc1ee74f2e18942c5c13748ac545e..d5ee7bebd03c9ae22f8c6ae5239c254566ec96ec 100644\n--- a/TODO_config_nommu\n+++ b/TODO_config_nommu\n@@ -743,12 +743,12 @@ CONFIG_TRACEROUTE=y\n CONFIG_FEATURE_TRACEROUTE_VERBOSE=y\n CONFIG_FEATURE_TRACEROUTE_SOURCE_ROUTE=y\n CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y\n-CONFIG_APP_UDHCPD=y\n-CONFIG_APP_DHCPRELAY=y\n-CONFIG_APP_DUMPLEASES=y\n+CONFIG_UDHCPD=y\n+CONFIG_DHCPRELAY=y\n+CONFIG_DUMPLEASES=y\n CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y\n CONFIG_DHCPD_LEASES_FILE=\"/var/lib/misc/udhcpd.leases\"\n-CONFIG_APP_UDHCPC=y\n+CONFIG_UDHCPC=y\n CONFIG_FEATURE_UDHCPC_ARPING=y\n CONFIG_FEATURE_UDHCP_PORT=y\n CONFIG_UDHCP_DEBUG=9\n\n<|file_patch|>docs/ifupdown_design.txt\ndiff --git a/docs/ifupdown_design.txt b/docs/ifupdown_design.txt\nindex 9df579289f881b5b2dac6128f8141a3a03a5bc75..8008e4507d4852eab105496fe1f012f5c5c58857 100644\n--- a/docs/ifupdown_design.txt\n+++ b/docs/ifupdown_design.txt\n@@ -26,7 +26,7 @@ static int dhcp_down(struct interface_defn_t *ifd, execfn *exec)\n }\n bb_error_msg(\"no dhcp clients found, using static interface shutdown\");\n return static_down(ifd, exec);\n-#elif ENABLE_APP_UDHCPC\n+#elif ENABLE_UDHCPC\n return execute(\"kill \"\n \"`cat /var/run/udhcpc.%iface%.pid` 2>/dev/null\", ifd, exec);\n #else\n\n<|file_patch|>include/applets.h\ndiff --git a/include/applets.h b/include/applets.h\nindex 69dcdc002560b565de89b6def8526c1ea46777d8..2d784bd84c5d337074e65866abff2f4905dc0b31 100644\n--- a/include/applets.h\n+++ b/include/applets.h\n@@ -123,7 +123,7 @@ IF_MODPROBE_SMALL(APPLET_ODDNAME(depmod, modprobe, _BB_DIR_SBIN, _BB_SUID_DROP,\n IF_DEVFSD(APPLET(devfsd, _BB_DIR_SBIN, _BB_SUID_DROP))\n IF_DEVMEM(APPLET(devmem, _BB_DIR_SBIN, _BB_SUID_DROP))\n IF_DF(APPLET(df, _BB_DIR_BIN, _BB_SUID_DROP))\n-IF_APP_DHCPRELAY(APPLET(dhcprelay, _BB_DIR_USR_SBIN, _BB_SUID_DROP))\n+IF_DHCPRELAY(APPLET(dhcprelay, _BB_DIR_USR_SBIN, _BB_SUID_DROP))\n IF_DIFF(APPLET(diff, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n IF_DIRNAME(APPLET_NOFORK(dirname, dirname, _BB_DIR_USR_BIN, _BB_SUID_DROP, dirname))\n IF_DMESG(APPLET(dmesg, _BB_DIR_BIN, _BB_SUID_DROP))\n@@ -134,7 +134,7 @@ IF_DPKG(APPLET(dpkg, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n IF_DPKG_DEB(APPLET_ODDNAME(dpkg-deb, dpkg_deb, _BB_DIR_USR_BIN, _BB_SUID_DROP, dpkg_deb))\n IF_DU(APPLET(du, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n IF_DUMPKMAP(APPLET(dumpkmap, _BB_DIR_BIN, _BB_SUID_DROP))\n-IF_APP_DUMPLEASES(APPLET(dumpleases, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n+IF_DUMPLEASES(APPLET(dumpleases, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n //IF_E2FSCK(APPLET(e2fsck, _BB_DIR_SBIN, _BB_SUID_DROP))\n //IF_E2LABEL(APPLET_ODDNAME(e2label, tune2fs, _BB_DIR_SBIN, _BB_SUID_DROP, e2label))\n IF_ECHO(APPLET_NOFORK(echo, echo, _BB_DIR_BIN, _BB_SUID_DROP, echo))\n@@ -403,8 +403,8 @@ IF_TTY(APPLET(tty, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n IF_TTYSIZE(APPLET(ttysize, _BB_DIR_USR_BIN, _BB_SUID_DROP))\n IF_TUNCTL(APPLET(tunctl, _BB_DIR_SBIN, _BB_SUID_DROP))\n IF_MKFS_EXT2(APPLET(tune2fs, _BB_DIR_SBIN, _BB_SUID_DROP))\n-IF_APP_UDHCPC(APPLET(udhcpc, _BB_DIR_SBIN, _BB_SUID_DROP))\n-IF_APP_UDHCPD(APPLET(udhcpd, _BB_DIR_USR_SBIN, _BB_SUID_DROP))\n+IF_UDHCPC(APPLET(udhcpc, _BB_DIR_SBIN, _BB_SUID_DROP))\n+IF_UDHCPD(APPLET(udhcpd, _BB_DIR_USR_SBIN, _BB_SUID_DROP))\n IF_UDPSVD(APPLET_ODDNAME(udpsvd, tcpudpsvd, _BB_DIR_USR_BIN, _BB_SUID_DROP, udpsvd))\n IF_UMOUNT(APPLET(umount, _BB_DIR_BIN, _BB_SUID_DROP))\n IF_UNAME(APPLET(uname, _BB_DIR_BIN, _BB_SUID_DROP))\n\n<|file_patch|>networking/Config.in\ndiff --git a/networking/Config.in b/networking/Config.in\nindex 668823784ef0257df7b02db3aa708a1d36538078..5222b78d465b3a020f83ce293034af3a26fd7d8d 100644\n--- a/networking/Config.in\n+++ b/networking/Config.in\n@@ -923,7 +923,7 @@ source networking/udhcp/Config.in\n config IFUPDOWN_UDHCPC_CMD_OPTIONS\n \tstring \"ifup udhcpc command line options\"\n \tdefault \"-R -n\"\n-\tdepends on IFUPDOWN && APP_UDHCPC\n+\tdepends on IFUPDOWN && UDHCPC\n \thelp\n \t Command line options to pass to udhcpc from ifup.\n \t Intended to alter options not available in /etc/network/interfaces.\n\n<|file_patch|>networking/udhcp/Config.in\ndiff --git a/networking/udhcp/Config.in b/networking/udhcp/Config.in\nindex 5f76dd8d449c69048f0a407829cad5a1754a3167..fd2a61cc0685e5d69b1f38b0acc641b003657ab1 100644\n--- a/networking/udhcp/Config.in\n+++ b/networking/udhcp/Config.in\n@@ -3,26 +3,26 @@\n # see scripts/kbuild/config-language.txt.\n #\n \n-config APP_UDHCPD\n+config UDHCPD\n \tbool \"udhcp server (udhcpd)\"\n \tdefault n\n \thelp\n \t udhcpd is a DHCP server geared primarily toward embedded systems,\n \t while striving to be fully functional and RFC compliant.\n \n-config APP_DHCPRELAY\n+config DHCPRELAY\n \tbool \"dhcprelay\"\n \tdefault n\n-\tdepends on APP_UDHCPD\n+\tdepends on UDHCPD\n \thelp\n \t dhcprelay listens for dhcp requests on one or more interfaces\n \t and forwards these requests to a different interface or dhcp\n \t server.\n \n-config APP_DUMPLEASES\n+config DUMPLEASES\n \tbool \"Lease display utility (dumpleases)\"\n \tdefault n\n-\tdepends on APP_UDHCPD\n+\tdepends on UDHCPD\n \thelp\n \t dumpleases displays the leases written out by the udhcpd server.\n \t Lease times are stored in the file by time remaining in lease, or\n@@ -31,7 +31,7 @@ config APP_DUMPLEASES\n config FEATURE_UDHCPD_WRITE_LEASES_EARLY\n \tbool \"Rewrite the lease file at every new acknowledge\"\n \tdefault n\n-\tdepends on APP_UDHCPD\n+\tdepends on UDHCPD\n \thelp\n \t If selected, udhcpd will write a new file with leases every\n \t time a new lease has been accepted, thus eliminating the need\n@@ -41,12 +41,12 @@ config FEATURE_UDHCPD_WRITE_LEASES_EARLY\n config DHCPD_LEASES_FILE\n \tstring \"Absolute path to lease file\"\n \tdefault \"/var/lib/misc/udhcpd.leases\"\n-\tdepends on APP_UDHCPD\n+\tdepends on UDHCPD\n \thelp\n \t udhcpd stores addresses in a lease file. This is the absolute path\n \t of the file. Normally it is safe to leave it untouched.\n \n-config APP_UDHCPC\n+config UDHCPC\n \tbool \"udhcp client (udhcpc)\"\n \tdefault n\n \thelp\n@@ -59,7 +59,7 @@ config APP_UDHCPC\n config FEATURE_UDHCPC_ARPING\n \tbool \"Verify that the offered address is free, using ARP ping\"\n \tdefault y\n-\tdepends on APP_UDHCPC\n+\tdepends on UDHCPC\n \thelp\n \t If selected, udhcpc will send ARP probes and make sure\n \t the offered address is really not in use by anyone. The client\n@@ -69,7 +69,7 @@ config FEATURE_UDHCPC_ARPING\n config FEATURE_UDHCP_PORT\n \tbool \"Enable '-P port' option for udhcpd and udhcpc\"\n \tdefault n\n-\tdepends on APP_UDHCPD || APP_UDHCPC\n+\tdepends on UDHCPD || UDHCPC\n \thelp\n \t At the cost of ~300 bytes, enables -P port option.\n \t This feature is typically not needed.\n@@ -78,7 +78,7 @@ config UDHCP_DEBUG\n \tint \"Maximum verbosity level for udhcp applets (0..9)\"\n \tdefault 0\n \trange 0 9\n-\tdepends on APP_UDHCPD || APP_UDHCPC || APP_DHCPRELAY\n+\tdepends on UDHCPD || UDHCPC || DHCPRELAY\n \thelp\n \t Verbosity can be increased with multiple -v options.\n \t This options controls how high it can be cranked up.\n@@ -89,7 +89,7 @@ config UDHCP_DEBUG\n config FEATURE_UDHCP_RFC3397\n \tbool \"Support for RFC3397 domain search (experimental)\"\n \tdefault n\n-\tdepends on APP_UDHCPD || APP_UDHCPC\n+\tdepends on UDHCPD || UDHCPC\n \thelp\n \t If selected, both client and server will support passing of domain\n \t search lists via option 119, specified in RFC3397.\n@@ -97,7 +97,7 @@ config FEATURE_UDHCP_RFC3397\n config UDHCPC_DEFAULT_SCRIPT\n \tstring \"Absolute path to config script\"\n \tdefault \"/usr/share/udhcpc/default.script\"\n-\tdepends on APP_UDHCPC\n+\tdepends on UDHCPC\n \thelp\n \t This script is called after udhcpc receives an answer. See\n \t examples/udhcp for a working example. Normally it is safe\n@@ -107,7 +107,7 @@ config UDHCPC_SLACK_FOR_BUGGY_SERVERS\n \tint \"DHCP options slack buffer size\"\n \tdefault 80\n \trange 0 924\n-\tdepends on APP_UDHCPD || APP_UDHCPC\n+\tdepends on UDHCPD || UDHCPC\n \thelp\n \t Some buggy DHCP servers send DHCP offer packets with option\n \t field larger than we expect (which might also be considered a\n\n<|file_patch|>networking/udhcp/Kbuild\ndiff --git a/networking/udhcp/Kbuild b/networking/udhcp/Kbuild\nindex e938076f768e96d0b4c5abcdabc99b2feb508f3d..d1d35670fb5253046f65aef8d806314b78ae8764 100644\n--- a/networking/udhcp/Kbuild\n+++ b/networking/udhcp/Kbuild\n@@ -6,20 +6,20 @@\n #\n \n lib-y:=\n-lib-$(CONFIG_APP_UDHCPC) += common.o options.o packet.o \\\n+lib-$(CONFIG_UDHCPC) += common.o options.o packet.o \\\n signalpipe.o socket.o\n-lib-$(CONFIG_APP_UDHCPD) += common.o options.o packet.o \\\n+lib-$(CONFIG_UDHCPD) += common.o options.o packet.o \\\n signalpipe.o socket.o\n \n-lib-$(CONFIG_APP_UDHCPC) += dhcpc.o clientpacket.o clientsocket.o \\\n+lib-$(CONFIG_UDHCPC) += dhcpc.o clientpacket.o clientsocket.o \\\n script.o\n \n UDHCPC_NEEDS_ARPING-$(CONFIG_FEATURE_UDHCPC_ARPING) = y\n lib-$(UDHCPC_NEEDS_ARPING-y) += arpping.o\n \n-lib-$(CONFIG_APP_UDHCPD) += dhcpd.o arpping.o files.o leases.o \\\n+lib-$(CONFIG_UDHCPD) += dhcpd.o arpping.o files.o leases.o \\\n serverpacket.o static_leases.o\n \n-lib-$(CONFIG_APP_DUMPLEASES) += dumpleases.o\n-lib-$(CONFIG_APP_DHCPRELAY) += dhcprelay.o\n+lib-$(CONFIG_DUMPLEASES) += dumpleases.o\n+lib-$(CONFIG_DHCPRELAY) += dhcprelay.o\n lib-$(CONFIG_FEATURE_UDHCP_RFC3397) += domain_codec.o\n\n<|file_patch|>scripts/defconfig\ndiff --git a/scripts/defconfig b/scripts/defconfig\nindex f8a92d4c30a0d6857d507a580f570585c27fd0fd..a98c7b6faea64a1b5025473a23a35b4138c53c22 100644\n--- a/scripts/defconfig\n+++ b/scripts/defconfig\n@@ -744,12 +744,12 @@ CONFIG_TRACEROUTE=y\n CONFIG_FEATURE_TRACEROUTE_VERBOSE=y\n # CONFIG_FEATURE_TRACEROUTE_SOURCE_ROUTE is not set\n # CONFIG_FEATURE_TRACEROUTE_USE_ICMP is not set\n-CONFIG_APP_UDHCPD=y\n-CONFIG_APP_DHCPRELAY=y\n-CONFIG_APP_DUMPLEASES=y\n+CONFIG_UDHCPD=y\n+CONFIG_DHCPRELAY=y\n+CONFIG_DUMPLEASES=y\n CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y\n CONFIG_DHCPD_LEASES_FILE=\"/var/lib/misc/udhcpd.leases\"\n-CONFIG_APP_UDHCPC=y\n+CONFIG_UDHCPC=y\n CONFIG_FEATURE_UDHCPC_ARPING=y\n CONFIG_FEATURE_UDHCP_PORT=y\n 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Polish entry (#5018)\n\nhttps://i.gyazo.com/c7557980d7d4c36709be78ef1f2c2a8f.png\n<|file_patch|>addons/tagging/stringtable.xml\ndiff --git a/addons/tagging/stringtable.xml b/addons/tagging/stringtable.xml\nindex 8b0782c32e3eb1843d7abecd9efecd219a3d7c5e..7d66f99e22d16986edc454e891f8ecd84d4c0bec 100644\n--- a/addons/tagging/stringtable.xml\n+++ b/addons/tagging/stringtable.xml\n@@ -68,7 +68,6 @@\n <English>Tag</English>\n <German>Markieren</German>\n <Spanish>Marcar</Spanish>\n- <Polish>Taguj</Polish>\n <French>Tag</French>\n <Polish>Oznakuj</Polish>\n <French>Marque</French>\n\n"},"target_character_start":{"kind":"number","value":109,"string":"109"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-07"},"utf8_bytes":{"kind":"number","value":680,"string":"680"},"document_order_key":{"kind":"number","value":2950083512014741500,"string":"2,950,083,512,014,741,500"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/acemod/ace3"},"quality_band":{"kind":"string","value":"07"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"null"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/acemod/ace3\",\"commit_oid\":\"5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84\",\"commits_ago_from_head\":5325,\"content_sha256\":\"186a9dd9a9073adcaf34117edd3882376f0cfae4ceb6d797550b0e9af01377f7\",\"manifest_sha256\":null,\"parent_oid\":\"bb228fa2b3a8b8cedc2ffc7c5093d57107041abc\",\"repository_id\":\"github.com/acemod/ace3\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"07\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":7},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#5018\"],\"message_words\":5,\"scope\":null,\"subject_length\":31,\"trailer_names\":[\"https\"],\"type\":null},\"patch_statistics\":{\"added_lines\":0,\"context_bytes\":9495,\"deleted_lines\":1,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":525,\"patch_sha256\":\"8c981a05a8a075ff7dca38266569da7002f525ba9e2bfbc9bd0b20dcab65bca7\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":null,\"path\":\"addons/tagging/stringtable.xml\",\"purpose\":\"other\"}],\"primary_language\":null},\"quality_band\":\"07\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":9495,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":525},\"commit_oid\":\"5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84\",\"identity\":{\"author_email\":\"loupvert@11rdp.fr\",\"author_name\":\"11RDP-LoupVert\",\"authored_at\":\"2017-03-22T17:05:43+01:00\",\"commit_oid\":\"5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84\",\"commits_ago_from_head\":5325,\"committed_at\":\"2017-03-22T11:05:43-05:00\",\"committer_email\":\"pabstmirror@gmail.com\",\"committer_name\":\"PabstMirror\",\"parent_oid\":\"bb228fa2b3a8b8cedc2ffc7c5093d57107041abc\",\"tree_oid\":\"3b64ff2cb6c56a4376e5eb2de5de8a2422059402\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"bbf353b84583b7ba9d3b5706b04ecff1e004a2ce\",\"oldest_commit\":\"d8084e20d7dec155d6d64ce1c5a882688f241261\"},\"recorded_head_commit\":\"bbf353b84583b7ba9d3b5706b04ecff1e004a2ce\",\"repository_id\":\"github.com/acemod/ace3\",\"snapshot_check\":\"repo_moved_ahead_of_recorded_head\"},\"repository_id\":\"github.com/acemod/ace3\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":5482,\"manifest_sha256\":null,\"split\":\"10-of-16\"}},\"parents\":[\"commit:github.com/acemod/ace3@5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84__download_changed_file_contents_6ef5f4522e97__render_commit_patches_651701f651db\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16082,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/carbon-language/carbon-lang@e26bc323434195d008bd35de6068f42a0ac08104"},"text":{"kind":"string","value":"<|commit_message|>\nChange remaining uses of `Bool` to `bool`, following #750. (#1901)\n\nThe most significant change here is that explorer now uses the chosen spelling\r\nrather than the old `Bool` spelling. Also update a few documentation examples\r\nand some skeletal design docs to use the chosen spelling.\n<|file_patch|>common/fuzzing/proto_to_carbon.cpp\ndiff --git a/common/fuzzing/proto_to_carbon.cpp b/common/fuzzing/proto_to_carbon.cpp\nindex 6f9caf64a77a60a7dd449fe2542e7fe5ca661d3f..8185c62d09f5cf7ad4d9226917078b77e083de70 100644\n--- a/common/fuzzing/proto_to_carbon.cpp\n+++ b/common/fuzzing/proto_to_carbon.cpp\n@@ -321,7 +321,7 @@ static auto ExpressionToCarbon(const Fuzzing::Expression& expression,\n }\n \n case Fuzzing::Expression::kBoolTypeLiteral:\n- out << \"Bool\";\n+ out << \"bool\";\n break;\n \n case Fuzzing::Expression::kBoolLiteral: {\n\n<|file_patch|>docs/design/generics/overview.md\ndiff --git a/docs/design/generics/overview.md b/docs/design/generics/overview.md\nindex 449a6155b3447b4727e356bad9d0a85b11b70320..7f24b985840a2ff16f509b377a51eeb3396ec495 100644\n--- a/docs/design/generics/overview.md\n+++ b/docs/design/generics/overview.md\n@@ -159,7 +159,7 @@ Example:\n ```\n interface Comparable {\n // `Less` is an associated method.\n- fn Less[me: Self](rhs: Self) -> Bool;\n+ fn Less[me: Self](rhs: Self) -> bool;\n }\n ```\n \n@@ -218,7 +218,7 @@ class Song {\n // the library defining `Song` or `Comparable`.\n external impl Song as Comparable {\n // Could use either `Self` or `Song` here.\n- fn Less[me: Self](rhs: Self) -> Bool { ... }\n+ fn Less[me: Self](rhs: Self) -> bool { ... }\n }\n ```\n \n@@ -350,7 +350,7 @@ Interfaces can require other interfaces be implemented:\n \n ```\n interface Equatable {\n- fn IsEqual[me: Self](rhs: Self) -> Bool;\n+ fn IsEqual[me: Self](rhs: Self) -> bool;\n }\n \n // `Iterable` requires that `Equatable` is implemented.\n@@ -386,7 +386,7 @@ methods in the implementation of the derived interface.\n class Key {\n // ...\n impl as Hashable {\n- fn IsEqual[me: Key](rhs: Key) -> Bool { ... }\n+ fn IsEqual[me: Key](rhs: Key) -> bool { ... }\n fn Hash[me: Key]() -> u64 { ... }\n }\n // No need to separately implement `Equatable`.\n@@ -535,7 +535,7 @@ interface Stack {\n let ElementType:! Movable;\n fn Push[addr me: Self*](value: ElementType);\n fn Pop[addr me: Self*]() -> ElementType;\n- fn IsEmpty[addr me: Self*]() -> Bool;\n+ fn IsEmpty[addr me: Self*]() -> bool;\n }\n ```\n \n@@ -561,7 +561,7 @@ those types to be different. An element in a hash map might have type\n \n ```\n interface Equatable(T:! Type) {\n- fn IsEqual[me: Self](compare_to: T) -> Bool;\n+ fn IsEqual[me: Self](compare_to: T) -> bool;\n }\n ```\n \n\n<|file_patch|>docs/design/name_lookup.md\ndiff --git a/docs/design/name_lookup.md b/docs/design/name_lookup.md\nindex e82d2323ace8c58cab482c7f7cc4f3ee9d3a2e80..1b392f5c96b400934a6fa7dc6078abd302730769 100644\n--- a/docs/design/name_lookup.md\n+++ b/docs/design/name_lookup.md\n@@ -76,12 +76,12 @@ the package scope for unqualified name lookup.\n \n The Carbon standard library is in the `Carbon` package. A very small subset of\n this standard library is provided implicitly in every file's scope. This is\n-called the \"prelude\" package.\n+called the \"prelude\".\n \n-Names in the prelude package will be available without scoping names. For\n-example, `Bool` will be the commonly used name in code, even though the\n-underlying type may be `Carbon::Bool`. Also, no `import` will be necessary to\n-use `Bool`.\n+Names in the prelude will be available without a package qualifier. For example,\n+the name `Type` can be directly used in code without a `Carbon.` qualifier, even\n+though it belongs to the `Carbon` package, and no import is necessary to use the\n+name `Type`.\n \n ## Open questions\n \n\n<|file_patch|>docs/design/primitive_types.md\ndiff --git a/docs/design/primitive_types.md b/docs/design/primitive_types.md\nindex b503271c2a4b14c92382187fae404cb4efb23dff..1307f817fd125b85cb9b545884d0e1d1454f035d 100644\n--- a/docs/design/primitive_types.md\n+++ b/docs/design/primitive_types.md\n@@ -37,33 +37,37 @@ modifying other types. They also have semantics that are defined from first\n principles rather than in terms of other operations. These will be made\n available through the [prelude package](README.md#name-lookup-for-common-types).\n \n-- `Bool` - a boolean type with two possible values: `True` and `False`.\n-- `Int` and `UInt` - signed and unsigned 64-bit integer types.\n+- `bool` - a boolean type with two possible values: `true` and `false`.\n+- Signed and unsigned 64-bit integer types:\n - Standard sizes are available, both signed and unsigned, including `i8`,\n- `i16`, `i32`, `i64`, `i128`, and `i256`.\n- - Overflow in either direction is an error.\n-- `Float64` - a floating point type with semantics based on IEEE-754.\n- - Standard sizes are available, including `f16`, `f32`, and `f128`.\n+ `i16`, `i32`, `i64`, and `i128`, and `u8`, `u16`, `u32`, `u64`, and\n+ `u128`.\n+ - Signed overflow in either direction is an error.\n+- Floating points type with semantics based on IEEE-754.\n+ - Standard sizes are available, including `f16`, `f32`, and `f64`.\n - [`BFloat16`](primitive_types.md#bfloat16) is also provided.\n - `String` - a byte sequence treated as containing UTF-8 encoded text.\n - `StringView` - a read-only reference to a byte sequence treated as\n containing UTF-8 encoded text.\n \n+The names `bool`, `true`, and `false` are keywords, and identifiers of the form\n+`i[0-9]*`, `u[0-9]*`, and `f[0-9*]` are _type literals_, resulting in the\n+corresponding type.\n+\n ### Integers\n \n Integer types can be either signed or unsigned, much like in C++. Signed\n integers are represented using 2's complement and notionally modeled as\n-unbounded natural numbers. Overflow in either direction is an error. That\n-includes unsigned integers, differing from C++. The default size for both is\n-64-bits: `Int` and `UInt`. Specific sizes are also available, for example:\n-`Int8`, `Int16`, `Int32`, `Int128`, `UInt256`. Arbitrary powers of two above `8`\n-are supported for both (although perhaps we'll want to avoid _huge_ values for\n-implementation simplicity).\n+unbounded natural numbers. Signed overflow in either direction is an error.\n+Specific sizes are available, for example: `i8`, `u16`, `i32`, and `u128`.\n+\n+There is an upper bound on the size of an integer, most likely initially set to\n+128 bits due to LLVM limitations.\n \n ### Floats\n \n Floating point types are based on the binary floating point formats provided by\n-IEEE-754. `Float16`, `Float32`, `Float64` and `Float128` correspond exactly to\n+IEEE-754. `f16`, `f32`, `f64` and, if available, `f128` correspond exactly to\n those sized IEEE-754 formats, and have the semantics defined by IEEE-754.\n \n ### BFloat16\n\n<|file_patch|>docs/project/principles/error_handling.md\ndiff --git a/docs/project/principles/error_handling.md b/docs/project/principles/error_handling.md\nindex 01b38da83c33ee7cf470d0c67780045eafac21dc..8df946f2309819722e73d77d57913898470a47e1 100644\n--- a/docs/project/principles/error_handling.md\n+++ b/docs/project/principles/error_handling.md\n@@ -32,7 +32,7 @@ way that enables the program to continue running.\n \n A Carbon function that needs to report recoverable failures should return a sum\n type whose alternatives represent the success case and failure cases, such as\n-`Optional(T)`, `Result(T, Error)`, or `Bool`. The function's successful return\n+`Optional(T)`, `Result(T, Error)`, or `bool`. The function's successful return\n value, and any metadata about the failure, should be embedded in the\n alternatives of the sum type, rather than reported by way of output parameters\n or other side channels. Carbon's design will prioritize making this form of\n\n<|file_patch|>docs/project/principles/library_apis_only.md\ndiff --git a/docs/project/principles/library_apis_only.md b/docs/project/principles/library_apis_only.md\nindex 7029b4a49e681cfbe0cc7387344eaf8c67c3fabf..a32b9b95e13da79a5497bf207c51a42f7a0255c1 100644\n--- a/docs/project/principles/library_apis_only.md\n+++ b/docs/project/principles/library_apis_only.md\n@@ -61,7 +61,7 @@ lookup as well.\n \n According to the resolutions of\n [#543](https://github.com/carbon-language/carbon-lang/issues/543) and\n-[#750](https://github.com/carbon-language/carbon-lang/issues/543), Carbon will\n+[#750](https://github.com/carbon-language/carbon-lang/issues/750), Carbon will\n have a substantial number of type keywords, such as `i32`, `f64`, and `bool`.\n However, these keywords will all be aliases for ordinary type names, such as\n `Carbon.Int(32)`, `Carbon.Float(64)`, and `Carbon.Bool`. Furthermore, all\n\n<|file_patch|>explorer/ast/expression.cpp\ndiff --git a/explorer/ast/expression.cpp b/explorer/ast/expression.cpp\nindex 0a1cbcc640f12540f39b51da3acbf88524222152..7a7bf933abcd2383215e26b1a14a881708fe2ef8 100644\n--- a/explorer/ast/expression.cpp\n+++ b/explorer/ast/expression.cpp\n@@ -288,7 +288,7 @@ void Expression::PrintID(llvm::raw_ostream& out) const {\n out << (cast<BoolLiteral>(*this).value() ? \"true\" : \"false\");\n break;\n case ExpressionKind::BoolTypeLiteral:\n- out << \"Bool\";\n+ out << \"bool\";\n break;\n case ExpressionKind::IntTypeLiteral:\n out << \"i32\";\n\n<|file_patch|>explorer/data/prelude.carbon\ndiff --git a/explorer/data/prelude.carbon b/explorer/data/prelude.carbon\nindex 59cfe6a26fcd7369f1decd4437d7b7f3ca5d1106..542244259862123b1a62d483d451f86bad09eb83 100644\n--- a/explorer/data/prelude.carbon\n+++ b/explorer/data/prelude.carbon\n@@ -58,7 +58,7 @@ impl forall [U1:! Type, U2:! Type, U3:! Type,\n // ----------------------\n \n interface EqWith(U:! Type) {\n- fn Equal[me: Self](other: U) -> Bool;\n+ fn Equal[me: Self](other: U) -> bool;\n // TODO: NotEqual with default impl\n }\n // TODO: constraint Eq { ... }\n@@ -67,7 +67,7 @@ interface EqWith(U:! Type) {\n // TODO: Simplify this once we have variadics\n impl forall [T2:! Type, U2:! Type, T1:! EqWith(T2), U1:! EqWith(U2)]\n (T1, U1) as EqWith((T2, U2)) {\n- fn Equal[me: Self](other: (T2, U2)) -> Bool {\n+ fn Equal[me: Self](other: (T2, U2)) -> bool {\n let (l1: T1, l2: U1) = me;\n let (r1: T2, r2: U2) = other;\n return l1 == r1 and l2 == r2;\n@@ -75,13 +75,13 @@ impl forall [T2:! Type, U2:! Type, T1:! EqWith(T2), U1:! EqWith(U2)]\n }\n \n impl i32 as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return __intrinsic_int_eq(me, other);\n }\n }\n \n impl String as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return __intrinsic_str_eq(me, other);\n }\n }\n\n<|file_patch|>explorer/syntax/lexer.lpp\ndiff --git a/explorer/syntax/lexer.lpp b/explorer/syntax/lexer.lpp\nindex 1fa891e19f9cdbe23f276dc22acb211e1c1e7f97..6c1ee2b204a3fefbd14d6bf10d9eb423f8f5d670 100644\n--- a/explorer/syntax/lexer.lpp\n+++ b/explorer/syntax/lexer.lpp\n@@ -42,7 +42,7 @@ AS \"as\"\n AUTO \"auto\"\n AWAIT \"__await\"\n BASE \"base\"\n-BOOL \"Bool\"\n+BOOL \"bool\"\n BREAK \"break\"\n CARET \"^\"\n CASE \"case\"\n\n<|file_patch|>explorer/testdata/basic_syntax/not_compare_precedence.carbon\ndiff --git a/explorer/testdata/basic_syntax/not_compare_precedence.carbon b/explorer/testdata/basic_syntax/not_compare_precedence.carbon\nindex 3639bb5be7c92ab8c1397bd6a6466dd4e82fa09c..6c5ca091a5efe0f699e5a7259652d6c9b32bac81 100644\n--- a/explorer/testdata/basic_syntax/not_compare_precedence.carbon\n+++ b/explorer/testdata/basic_syntax/not_compare_precedence.carbon\n@@ -10,7 +10,7 @@\n \n package ExplorerTest api;\n \n-fn CompareBools(a: Bool, b: Bool) -> Bool {\n+fn CompareBools(a: bool, b: bool) -> bool {\n // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/basic_syntax/not_compare_precedence.carbon:[[@LINE+1]]: syntax error, unexpected EQUAL_EQUAL, expecting SEMICOLON\n return not a == b;\n }\n\n<|file_patch|>explorer/testdata/comparison/custom_equality.carbon\ndiff --git a/explorer/testdata/comparison/custom_equality.carbon b/explorer/testdata/comparison/custom_equality.carbon\nindex 90ed478ba092e95d1dff4363266d1049de9bd736..0cf3e8909480adb651ffb523bdf9da6cf33510d2 100644\n--- a/explorer/testdata/comparison/custom_equality.carbon\n+++ b/explorer/testdata/comparison/custom_equality.carbon\n@@ -16,7 +16,7 @@ class MyType {\n var value: i32;\n \n impl as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return me.value == other.value;\n }\n }\n\n<|file_patch|>explorer/testdata/comparison/fail_empty_struct.carbon\ndiff --git a/explorer/testdata/comparison/fail_empty_struct.carbon b/explorer/testdata/comparison/fail_empty_struct.carbon\nindex c3620e6be14544c3c7f6c78581b3895a0addfb70..5e701cca79e3492b689544fc7cea33b5694cd980 100644\n--- a/explorer/testdata/comparison/fail_empty_struct.carbon\n+++ b/explorer/testdata/comparison/fail_empty_struct.carbon\n@@ -10,7 +10,7 @@ package ExplorerTest api;\n // TODO: This should work\n // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/comparison/fail_empty_struct.carbon:[[@LINE+1]]: type error in call: '{}' is not implicitly convertible to 'Type'\n external impl {} as EqWith({}) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return true;\n }\n }\n\n<|file_patch|>explorer/testdata/function/auto_return/fail_direct_recurse.carbon\ndiff --git a/explorer/testdata/function/auto_return/fail_direct_recurse.carbon b/explorer/testdata/function/auto_return/fail_direct_recurse.carbon\nindex 92fefab0dcc5c44a99788ddc2fc701af75e2d06a..f2805ed324600213d38d34c58cc157be09ee34a4 100644\n--- a/explorer/testdata/function/auto_return/fail_direct_recurse.carbon\n+++ b/explorer/testdata/function/auto_return/fail_direct_recurse.carbon\n@@ -12,7 +12,7 @@ package ExplorerTest api;\n \n // This is required to fail even though the Recurse() call's return value isn't\n // used.\n-fn Recurse(x: i32, do_recurse: Bool) -> auto {\n+fn Recurse(x: i32, do_recurse: bool) -> auto {\n if (do_recurse) {\n // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/function/auto_return/fail_direct_recurse.carbon:[[@LINE+1]]: Function calls itself, but has a deduced return type\n Recurse(x, false);\n\n<|file_patch|>explorer/testdata/generic_class/fail_argument_deduction.carbon\ndiff --git a/explorer/testdata/generic_class/fail_argument_deduction.carbon b/explorer/testdata/generic_class/fail_argument_deduction.carbon\nindex 4157657ef361feef20c585bebc9d9215c38ac1a3..5ad7276d4b52b865850ce0bce83dc0a81536ec7c 100644\n--- a/explorer/testdata/generic_class/fail_argument_deduction.carbon\n+++ b/explorer/testdata/generic_class/fail_argument_deduction.carbon\n@@ -21,9 +21,9 @@ fn FirstOfTwoPoints[T:! Type](a: Point(T), b: Point(T)) -> Point(T) {\n \n fn Main() -> i32 {\n var p: Point(i32) = {.x = 0, .y = 1};\n- var q: Point(Bool) = {.x = true, .y = false};\n+ var q: Point(bool) = {.x = true, .y = false};\n // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/generic_class/fail_argument_deduction.carbon:[[@LINE+3]]: deduced multiple different values for T:! Type:\n // CHECK: i32\n- // CHECK: Bool\n+ // CHECK: bool\n return FirstOfTwoPoints(p, q).x;\n }\n\n<|file_patch|>explorer/testdata/generic_class/fail_point_equal.carbon\ndiff --git a/explorer/testdata/generic_class/fail_point_equal.carbon b/explorer/testdata/generic_class/fail_point_equal.carbon\nindex c165f62ab96df27fa00208b201bc571ffd4dc921..442704d45813b8400a447c2cab34cdee88582701 100644\n--- a/explorer/testdata/generic_class/fail_point_equal.carbon\n+++ b/explorer/testdata/generic_class/fail_point_equal.carbon\n@@ -17,7 +17,7 @@ class Point(T:! Type) {\n \n fn Main() -> i32 {\n var p: Point(i32) = {.x = 0, .y = 0};\n- // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/generic_class/fail_point_equal.carbon:[[@LINE+1]]: type error in name binding: 'class Point(T = i32)' is not implicitly convertible to 'class Point(T = Bool)'\n- var q: Point(Bool) = p;\n+ // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/generic_class/fail_point_equal.carbon:[[@LINE+1]]: type error in name binding: 'class Point(T = i32)' is not implicitly convertible to 'class Point(T = bool)'\n+ var q: Point(bool) = p;\n return 0;\n }\n\n<|file_patch|>explorer/testdata/generic_function/apply.carbon\ndiff --git a/explorer/testdata/generic_function/apply.carbon b/explorer/testdata/generic_function/apply.carbon\nindex 1800ecc5dab0edc0012a73143bce62353749bc78..23adb60b3c55ec10032d04221a67dc1abcf0592a 100644\n--- a/explorer/testdata/generic_function/apply.carbon\n+++ b/explorer/testdata/generic_function/apply.carbon\n@@ -15,7 +15,7 @@ fn apply[T:! Type, U:! Type](f: __Fn (T) -> U, x: T) -> U {\n return f(x);\n }\n \n-fn positive(x: Bool) -> i32 {\n+fn positive(x: bool) -> i32 {\n if (x) {\n return 2;\n } else {\n\n<|file_patch|>explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon\ndiff --git a/explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon b/explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon\nindex 88204d99535976f8d6178b0f84cd830ab9433a4e..95908dc0016c000c790690009a1d7cdfd33b1d3c 100644\n--- a/explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon\n+++ b/explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon\n@@ -17,6 +17,6 @@ fn fst[T:! Type](x: T, y: T) -> T {\n fn Main() -> i32 {\n // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon:[[@LINE+3]]: deduced multiple different values for T:! Type:\n // CHECK: i32\n- // CHECK: Bool\n+ // CHECK: bool\n return fst(0, true);\n }\n\n<|file_patch|>explorer/testdata/global_variable/fail_init_type_mismatch.carbon\ndiff --git a/explorer/testdata/global_variable/fail_init_type_mismatch.carbon b/explorer/testdata/global_variable/fail_init_type_mismatch.carbon\nindex 559c51983b6cc993c94270805e607417280e13d5..0f941d8a5c5b3f18ac1ea7767486e5540b2151c7 100644\n--- a/explorer/testdata/global_variable/fail_init_type_mismatch.carbon\n+++ b/explorer/testdata/global_variable/fail_init_type_mismatch.carbon\n@@ -12,7 +12,7 @@ package ExplorerTest api;\n \n // Test type checking of global variable. Error expected.\n \n-// CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/global_variable/fail_init_type_mismatch.carbon:[[@LINE+1]]: type error in initializer of variable: 'Bool' is not implicitly convertible to 'i32'\n+// CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/global_variable/fail_init_type_mismatch.carbon:[[@LINE+1]]: type error in initializer of variable: 'bool' is not implicitly convertible to 'i32'\n var flag: i32 = true;\n \n fn Main() -> i32 {\n\n<|file_patch|>explorer/testdata/if_else/convert_condition.carbon\ndiff --git a/explorer/testdata/if_else/convert_condition.carbon b/explorer/testdata/if_else/convert_condition.carbon\nindex 44c8d7e160e80ac3851ed91a1af789636448e3d5..63e34fa09f0fb9c66fa5e6f1189500ed2aa8e212 100644\n--- a/explorer/testdata/if_else/convert_condition.carbon\n+++ b/explorer/testdata/if_else/convert_condition.carbon\n@@ -14,8 +14,8 @@ package ExplorerTest api;\n class LazyEq {\n var v1: i32;\n var v2: i32;\n- impl as ImplicitAs(Bool) {\n- fn Convert[me: Self]() -> Bool {\n+ impl as ImplicitAs(bool) {\n+ fn Convert[me: Self]() -> bool {\n return me.v1 == me.v2;\n }\n }\n\n<|file_patch|>explorer/testdata/if_expression/convert_condition.carbon\ndiff --git a/explorer/testdata/if_expression/convert_condition.carbon b/explorer/testdata/if_expression/convert_condition.carbon\nindex 34c0337747bcc34c6fccddb77aef22c36dfdbfa1..3bc3fa124eaf14c8573b2e613c6d598248886d5c 100644\n--- a/explorer/testdata/if_expression/convert_condition.carbon\n+++ b/explorer/testdata/if_expression/convert_condition.carbon\n@@ -14,8 +14,8 @@ package ExplorerTest api;\n class LazyEq {\n var v1: i32;\n var v2: i32;\n- impl as ImplicitAs(Bool) {\n- fn Convert[me: Self]() -> Bool {\n+ impl as ImplicitAs(bool) {\n+ fn Convert[me: Self]() -> bool {\n return me.v1 == me.v2;\n }\n }\n\n<|file_patch|>explorer/testdata/if_expression/if_then_else.carbon\ndiff --git a/explorer/testdata/if_expression/if_then_else.carbon b/explorer/testdata/if_expression/if_then_else.carbon\nindex a95f0fabee2d1070239214bf009b08cf96927008..aa32a1aed16f0d99ad0c6a7f1da03d55b2d7785c 100644\n--- a/explorer/testdata/if_expression/if_then_else.carbon\n+++ b/explorer/testdata/if_expression/if_then_else.carbon\n@@ -12,7 +12,7 @@\n package ExplorerTest api;\n \n fn Main() -> i32 {\n- var cond: if true then Bool else i32 = true;\n+ var cond: if true then bool else i32 = true;\n if (if cond then true else false) {}\n while (if cond then false else true) {}\n return if if cond then true or false else false and true\n\n<|file_patch|>explorer/testdata/impl/fail_ambiguous_impl_generic.carbon\ndiff --git a/explorer/testdata/impl/fail_ambiguous_impl_generic.carbon b/explorer/testdata/impl/fail_ambiguous_impl_generic.carbon\nindex f24ed3c64a2a72fd066b5f4e87663933eb5641e4..0854a76a6d03c35ec7d9a57b6e649d19d1cc6c36 100644\n--- a/explorer/testdata/impl/fail_ambiguous_impl_generic.carbon\n+++ b/explorer/testdata/impl/fail_ambiguous_impl_generic.carbon\n@@ -17,10 +17,10 @@ external impl forall [T:! Type] A(T) as B(i32) {}\n external impl forall [T:! Type] A(i32) as B(T) {}\n \n fn F[T:! B(i32)](x: T) {}\n-fn G[T:! B(Bool)](x: T) {}\n+fn G[T:! B(bool)](x: T) {}\n \n fn Main() -> i32 {\n- let a: A(Bool) = {};\n+ let a: A(bool) = {};\n let b: A(i32) = {};\n F(a);\n G(b);\n\n<|file_patch|>explorer/testdata/impl/fail_param_interface_in_impl.carbon\ndiff --git a/explorer/testdata/impl/fail_param_interface_in_impl.carbon b/explorer/testdata/impl/fail_param_interface_in_impl.carbon\nindex 01e77cec361b7e4712683e343d923254de946716..1baa85dbb07d7c1c7dad549f121b6d7c4e85cbe7 100644\n--- a/explorer/testdata/impl/fail_param_interface_in_impl.carbon\n+++ b/explorer/testdata/impl/fail_param_interface_in_impl.carbon\n@@ -21,7 +21,7 @@ fn Main() -> i32 {\n let n: i32 = 0;\n CheckSimilar(true, false);\n CheckSimilar(true, n);\n- // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/impl/fail_param_interface_in_impl.carbon:[[@LINE+1]]: could not find implementation of interface Similar(T = i32) for Bool\n+ // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/impl/fail_param_interface_in_impl.carbon:[[@LINE+1]]: could not find implementation of interface Similar(T = i32) for bool\n CheckSimilar(n, false);\n return 0;\n }\n\n<|file_patch|>explorer/testdata/operators/shortcircuit_and.carbon\ndiff --git a/explorer/testdata/operators/shortcircuit_and.carbon b/explorer/testdata/operators/shortcircuit_and.carbon\nindex 2773859a9021b90aaf2562ea48d24f7dcacd3384..0f789bbdc7194264e6d9aa8956817606cf79238e 100644\n--- a/explorer/testdata/operators/shortcircuit_and.carbon\n+++ b/explorer/testdata/operators/shortcircuit_and.carbon\n@@ -12,12 +12,12 @@\n package ExplorerTest api;\n \n var call_count: i32 = 0;\n-fn ReturnFalse() -> Bool {\n+fn ReturnFalse() -> bool {\n call_count = call_count + 1;\n return false;\n }\n \n fn Main() -> i32 {\n- var result: Bool = ReturnFalse() and ReturnFalse();\n+ var result: bool = ReturnFalse() and ReturnFalse();\n return if not result then call_count else -1;\n }\n\n<|file_patch|>explorer/testdata/operators/shortcircuit_and_no_shortcircuit.carbon\ndiff --git a/explorer/testdata/operators/shortcircuit_and_no_shortcircuit.carbon b/explorer/testdata/operators/shortcircuit_and_no_shortcircuit.carbon\nindex f29fc72177135dd767228a3eea3671895b84627a..2d97faa60db9912b1558f0779602f74c9faa4023 100644\n--- a/explorer/testdata/operators/shortcircuit_and_no_shortcircuit.carbon\n+++ b/explorer/testdata/operators/shortcircuit_and_no_shortcircuit.carbon\n@@ -12,12 +12,12 @@\n package ExplorerTest api;\n \n var call_count: i32 = 0;\n-fn ReturnTrue() -> Bool {\n+fn ReturnTrue() -> bool {\n call_count = call_count + 1;\n return true;\n }\n \n fn Main() -> i32 {\n- var result: Bool = ReturnTrue() and ReturnTrue();\n+ var result: bool = ReturnTrue() and ReturnTrue();\n return if result then call_count else -1;\n }\n\n<|file_patch|>explorer/testdata/operators/shortcircuit_or.carbon\ndiff --git a/explorer/testdata/operators/shortcircuit_or.carbon b/explorer/testdata/operators/shortcircuit_or.carbon\nindex 8ee8c4004d23fad610fdb97139ef67995b1d3e9c..1f1e4427e4a28440ee3e7b55a4a4a2d3728e309a 100644\n--- a/explorer/testdata/operators/shortcircuit_or.carbon\n+++ b/explorer/testdata/operators/shortcircuit_or.carbon\n@@ -12,12 +12,12 @@\n package ExplorerTest api;\n \n var call_count: i32 = 0;\n-fn ReturnTrue() -> Bool {\n+fn ReturnTrue() -> bool {\n call_count = call_count + 1;\n return true;\n }\n \n fn Main() -> i32 {\n- var result: Bool = ReturnTrue() or ReturnTrue();\n+ var result: bool = ReturnTrue() or ReturnTrue();\n return if result then call_count else -1;\n }\n\n<|file_patch|>explorer/testdata/operators/shortcircuit_or_no_shortcircuit.carbon\ndiff --git a/explorer/testdata/operators/shortcircuit_or_no_shortcircuit.carbon b/explorer/testdata/operators/shortcircuit_or_no_shortcircuit.carbon\nindex 374878926ce6964e1b3438f696e18ff0c9a84e55..d9de7b61770a3f2c979480f9bfa4e3f9b6212759 100644\n--- a/explorer/testdata/operators/shortcircuit_or_no_shortcircuit.carbon\n+++ b/explorer/testdata/operators/shortcircuit_or_no_shortcircuit.carbon\n@@ -12,12 +12,12 @@\n package ExplorerTest api;\n \n var call_count: i32 = 0;\n-fn ReturnFalse() -> Bool {\n+fn ReturnFalse() -> bool {\n call_count = call_count + 1;\n return false;\n }\n \n fn Main() -> i32 {\n- var result: Bool = ReturnFalse() or ReturnFalse();\n+ var result: bool = ReturnFalse() or ReturnFalse();\n return if not result then call_count else -1;\n }\n\n<|file_patch|>explorer/testdata/random/random.carbon\ndiff --git a/explorer/testdata/random/random.carbon b/explorer/testdata/random/random.carbon\nindex 3fd0d095ad6b51eee75fa86c64b007355cee619d..6080b1c90718f8276a40b9847d45924b7d8fb82a 100644\n--- a/explorer/testdata/random/random.carbon\n+++ b/explorer/testdata/random/random.carbon\n@@ -10,7 +10,7 @@\n // CHECK: result: 0\n \n package ExplorerTest api;\n-fn test(para: i32)->Bool{\n+fn test(para: i32)->bool{\n return true;\n }\n fn Main() -> i32 {\n\n<|file_patch|>explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon\ndiff --git a/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon b/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon\nindex 9020f65815fbee205d9698c8602a7ab461aa943a..8c95bd40d33036a23b5b29e3bd44305f3989dd53 100644\n--- a/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon\n+++ b/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon\n@@ -11,8 +11,8 @@\n package ExplorerTest api;\n \n fn AddInt(a: i32, b: i32) -> i32 {\n- // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon:[[@LINE+1]]: type of returned var `Bool` does not match return type `i32`\n- returned var ret: Bool = true;\n+ // CHECK: COMPILATION ERROR: {{.*}}/explorer/testdata/returned_var/fail_returned_var_type_mismatch.carbon:[[@LINE+1]]: type of returned var `bool` does not match return type `i32`\n+ returned var ret: bool = true;\n return var;\n }\n \n\n<|file_patch|>explorer/testdata/struct/equality.carbon\ndiff --git a/explorer/testdata/struct/equality.carbon b/explorer/testdata/struct/equality.carbon\nindex 073cd4eabdac4031eea04dc3c4f033f15bce2474..af3fe31727540e90f0e58bd3590612eab9fc0a8a 100644\n--- a/explorer/testdata/struct/equality.carbon\n+++ b/explorer/testdata/struct/equality.carbon\n@@ -13,7 +13,7 @@ package ExplorerTest api;\n \n // TODO: Implement this with some kind of reflection?\n external impl {.x: i32, .y: i32} as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return me.x == other.x and me.y == other.y;\n }\n }\n\n<|file_patch|>explorer/testdata/struct/equality_false.carbon\ndiff --git a/explorer/testdata/struct/equality_false.carbon b/explorer/testdata/struct/equality_false.carbon\nindex bf354b571708995acc4d9853274ff5f0faddc4dc..6d0e769dd9c9bd59a593eddb07e65dfc25607211 100644\n--- a/explorer/testdata/struct/equality_false.carbon\n+++ b/explorer/testdata/struct/equality_false.carbon\n@@ -13,7 +13,7 @@ package ExplorerTest api;\n \n // TODO: Implement this with some kind of reflection?\n external impl {.x: i32, .y: i32} as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return me.x == other.x and me.y == other.y;\n }\n }\n\n<|file_patch|>explorer/testdata/struct/fail_equality_type.carbon\ndiff --git a/explorer/testdata/struct/fail_equality_type.carbon b/explorer/testdata/struct/fail_equality_type.carbon\nindex 1b90a0e46730f7e4da0f1b5483da9ae61920c8d7..6807318fdcc0780f01ef0860926ba355e820b9ff 100644\n--- a/explorer/testdata/struct/fail_equality_type.carbon\n+++ b/explorer/testdata/struct/fail_equality_type.carbon\n@@ -9,7 +9,7 @@ package ExplorerTest api;\n \n // TODO: Implement this with some kind of reflection?\n external impl {.x: i32, .y: i32} as EqWith(Self) {\n- fn Equal[me: Self](other: Self) -> Bool {\n+ fn Equal[me: Self](other: Self) -> bool {\n return me.x == other.x and me.y == other.y;\n }\n }\n\n<|file_patch|>explorer/testdata/while/convert_condition.carbon\ndiff --git a/explorer/testdata/while/convert_condition.carbon b/explorer/testdata/while/convert_condition.carbon\nindex bf3b3a07bab444671c3e7e0525a510a0dd5d12ea..30218d99dbc96588c298db3c9fec559607b6f2e6 100644\n--- a/explorer/testdata/while/convert_condition.carbon\n+++ b/explorer/testdata/while/convert_condition.carbon\n@@ -14,8 +14,8 @@ package ExplorerTest api;\n class LazyNe {\n var v1: i32;\n var v2: i32;\n- impl as ImplicitAs(Bool) {\n- fn Convert[me: Self]() -> Bool {\n+ impl as ImplicitAs(bool) {\n+ fn Convert[me: Self]() -> bool {\n return not (me.v1 == me.v2);\n }\n }\n\n"},"target_character_start":{"kind":"number","value":304,"string":"304"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-10"},"utf8_bytes":{"kind":"number","value":29890,"string":"29,890"},"document_order_key":{"kind":"number","value":2950191395428974600,"string":"2,950,191,395,428,974,600"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/carbon-language/carbon-lang"},"quality_band":{"kind":"string","value":"10"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"markdown"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/carbon-language/carbon-lang\",\"commit_oid\":\"e26bc323434195d008bd35de6068f42a0ac08104\",\"commits_ago_from_head\":4479,\"content_sha256\":\"70b51d6735a0d9ed4fcf74c493bcfe6d7d992c7764fb4e716e6c150784ec5932\",\"manifest_sha256\":null,\"parent_oid\":\"72d3d3c75cc4a78d80a09d18178b2cd6a9a9dd94\",\"repository_id\":\"github.com/carbon-language/carbon-lang\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"10\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"},{\"points\":2,\"reason\":\"candidate_cap_rungs_exceeded\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":10},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[\"#750\",\"#1901\"],\"message_words\":45,\"scope\":null,\"subject_length\":66,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":72,\"context_bytes\":117318,\"deleted_lines\":68,\"files_changed\":33,\"hunk_count\":40,\"patch_bytes\":27447,\"patch_sha256\":\"8b22fdafc1c7bd79f5c398ea0db64fa138ff26b798515c21a351c0227d84d370\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"cpp\",\"path\":\"common/fuzzing/proto_to_carbon.cpp\",\"purpose\":\"source\"},{\"language\":\"markdown\",\"path\":\"docs/design/generics/overview.md\",\"purpose\":\"docs\"},{\"language\":\"markdown\",\"path\":\"docs/design/name_lookup.md\",\"purpose\":\"docs\"},{\"language\":\"markdown\",\"path\":\"docs/design/primitive_types.md\",\"purpose\":\"docs\"},{\"language\":\"markdown\",\"path\":\"docs/project/principles/error_handling.md\",\"purpose\":\"docs\"},{\"language\":\"markdown\",\"path\":\"docs/project/principles/library_apis_only.md\",\"purpose\":\"docs\"},{\"language\":\"cpp\",\"path\":\"explorer/ast/expression.cpp\",\"purpose\":\"source\"},{\"language\":null,\"path\":\"explorer/data/prelude.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/syntax/lexer.lpp\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/basic_syntax/not_compare_precedence.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/comparison/custom_equality.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/comparison/fail_empty_struct.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/function/auto_return/fail_direct_recurse.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/generic_class/fail_argument_deduction.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/generic_class/fail_point_equal.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/generic_function/apply.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/generic_function/fail_type_deduction_mismatch.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/global_variable/fail_init_type_mismatch.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/if_else/convert_condition.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/if_expression/convert_condition.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/if_expression/if_then_else.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/impl/fail_ambiguous_impl_generic.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/impl/fail_param_interface_in_impl.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer/testdata/operators/shortcircuit_and.carbon\",\"purpose\":\"other\"},{\"language\":null,\"path\":\"explorer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definition of temperature offsets for extruder and bed\n\nSession based temperature offsets that are only applied to temperature definitions in GCODE files being printed, in order to quickly experiment with temperature settings.\n\nCloses #97\n\n<|file_patch|>octoprint/printer.py\ndiff --git a/octoprint/printer.py b/octoprint/printer.py\nindex d5fc445f67d08419c329e8fc00c9d3660c206d08..323546add591b050c01461310b7b3b3ca7337735 100644\n--- a/octoprint/printer.py\n+++ b/octoprint/printer.py\n@@ -171,9 +171,19 @@ class Printer():\n \t\t\"\"\"\n \t\t Sends multiple gcode commands (provided as a list) to the printer.\n \t\t\"\"\"\n+\t\tif self._comm is None:\n+\t\t\treturn\n+\n \t\tfor command in commands:\n \t\t\tself._comm.sendCommand(command)\n \n+\tdef setTemperatureOffset(self, extruder, bed):\n+\t\tif self._comm is None:\n+\t\t\treturn\n+\n+\t\tself._comm.setTemperatureOffset(extruder, bed)\n+\t\tself._stateMonitor.setTempOffsets(extruder, bed)\n+\n \tdef selectFile(self, filename, sd, printAfterSelect=False):\n \t\tif self._comm is None or (self._comm.isBusy() or self._comm.isStreaming()):\n \t\t\treturn\n@@ -503,14 +513,22 @@ class Printer():\n \t\treturn currentData[\"job\"]\n \n \tdef getCurrentTemperatures(self):\n+\t\tif self._comm is not None:\n+\t\t\t(tempOffset, bedTempOffset) = self._comm.getOffsets()\n+\t\telse:\n+\t\t\ttempOffset = 0\n+\t\t\tbedTempOffset = 0\n+\n \t\treturn {\n \t\t\t\"extruder\": {\n \t\t\t\t\"current\": self._temp,\n-\t\t\t\t\"target\": self._targetTemp\n+\t\t\t\t\"target\": self._targetTemp,\n+\t\t\t\t\"offset\": tempOffset\n \t\t\t},\n \t\t\t\"bed\": {\n \t\t\t\t\"current\": self._bedTemp,\n-\t\t\t\t\"target\": self._targetBedTemp\n+\t\t\t\t\"target\": self._targetBedTemp,\n+\t\t\t\t\"offset\": bedTempOffset\n \t\t\t}\n \t\t}\n \n@@ -627,6 +645,9 @@ class StateMonitor(object):\n \t\tself._currentZ = None\n \t\tself._progress = None\n \n+\t\tself._tempOffset = 0\n+\t\tself._bedTempOffset = 0\n+\n \t\tself._changeEvent = threading.Event()\n \n \t\tself._lastUpdate = time.time()\n@@ -668,6 +689,13 @@ class StateMonitor(object):\n \t\tself._progress = progress\n \t\tself._changeEvent.set()\n \n+\tdef setTempOffsets(self, tempOffset, bedTempOffset):\n+\t\tif tempOffset is not None:\n+\t\t\tself._tempOffset = tempOffset\n+\t\tif bedTempOffset is not None:\n+\t\t\tself._bedTempOffset = bedTempOffset\n+\t\tself._changeEvent.set()\n+\n \tdef _work(self):\n \t\twhile True:\n \t\t\tself._changeEvent.wait()\n@@ -688,6 +716,7 @@ class StateMonitor(object):\n \t\t\t\"state\": self._state,\n \t\t\t\"job\": self._jobData,\n \t\t\t\"currentZ\": self._currentZ,\n-\t\t\t\"progress\": self._progress\n+\t\t\t\"progress\": self._progress,\n+\t\t\t\"offsets\": (self._tempOffset, self._bedTempOffset)\n \t\t}\n \n\n<|file_patch|>octoprint/static/js/app/viewmodels/temperature.js\ndiff --git a/octoprint/static/js/app/viewmodels/temperature.js b/octoprint/static/js/app/viewmodels/temperature.js\nindex 4698e7c5fc96c925d6a062d2275351634db1a68b..6890914e4a4f09c08845f24b61bf9b4be684b906 100644\n--- a/octoprint/static/js/app/viewmodels/temperature.js\n+++ b/octoprint/static/js/app/viewmodels/temperature.js\n@@ -11,6 +11,11 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n self.newTemp = ko.observable(undefined);\n self.newBedTemp = ko.observable(undefined);\n \n+ self.newTempOffset = ko.observable(undefined);\n+ self.tempOffset = ko.observable(0);\n+ self.newBedTempOffset = ko.observable(undefined);\n+ self.bedTempOffset = ko.observable(0);\n+\n self.isErrorOrClosed = ko.observable(undefined);\n self.isOperational = ko.observable(undefined);\n self.isPrinting = ko.observable(undefined);\n@@ -78,11 +83,13 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n self.fromCurrentData = function(data) {\n self._processStateData(data.state);\n self._processTemperatureUpdateData(data.temperatures);\n+ self._processOffsetData(data.offsets);\n }\n \n self.fromHistoryData = function(data) {\n self._processStateData(data.state);\n self._processTemperatureHistoryData(data.temperatureHistory);\n+ self._processOffsetData(data.offsets);\n }\n \n self._processStateData = function(data) {\n@@ -138,6 +145,11 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n self.updatePlot();\n }\n \n+ self._processOffsetData = function(data) {\n+ self.tempOffset(data[0]);\n+ self.bedTempOffset(data[1]);\n+ }\n+\n self.updatePlot = function() {\n var graph = $(\"#temperature-graph\");\n if (graph.length) {\n@@ -166,6 +178,10 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n self._updateTemperature(0, \"temp\", function(){self.targetTemp(0); self.newTemp(\"\");});\n }\n \n+ self.setTempOffset = function() {\n+ self._updateTemperature(self.newTempOffset(), \"tempOffset\", function() {self.tempOffset(self.newTempOffset()); self.newTempOffset(\"\");});\n+ }\n+\n self.setBedTempFromProfile = function(profile) {\n self._updateTemperature(profile.bed, \"bedTemp\");\n }\n@@ -178,6 +194,10 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n self._updateTemperature(0, \"bedTemp\", function() {self.bedTargetTemp(0); self.newBedTemp(\"\");});\n }\n \n+ self.setBedTempOffset = function() {\n+ self._updateTemperature(self.newBedTempOffset(), \"bedTempOffset\", function() {self.bedTempOffset(self.newBedTempOffset()); self.newBedTempOffset(\"\");});\n+ }\n+\n self._updateTemperature = function(temp, type, callback) {\n var data = {};\n data[type] = temp;\n@@ -185,10 +205,9 @@ function TemperatureViewModel(loginStateViewModel, settingsViewModel) {\n $.ajax({\n url: AJAX_BASEURL + \"control/temperature\",\n type: \"POST\",\n- dataType: \"json\",\n data: data,\n success: function() { if (callback !== undefined) callback(); }\n- })\n+ });\n }\n \n self.handleEnter = function(event, type) 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`clip_grad_norm` to use torch.linalg.vector_norm (#102429)\n\nDone in this PR:\n - Use `torch.linalg.vector_norm` instead of `torch.norm`\n - Reduce bandwidth boundary of clip_grad_norm when used with `inf`, ie no need to get the returned tensor after `abs`\n\nWhat I'm slightly unsure:\n - I don't know if `inf` support `torch._foreach` API\n\nPull Request resolved: https://github.com/pytorch/pytorch/pull/102429\nApproved by: https://github.com/lezcano\n\n<|file_patch|>torch/nn/utils/clip_grad.py\ndiff --git a/torch/nn/utils/clip_grad.py b/torch/nn/utils/clip_grad.py\nindex 900d042abefd2dc5a1c7955033610dcf20e1021a..a28e6cb23f961db80ebfa16df430bc7fb0a75d74 100644\n--- a/torch/nn/utils/clip_grad.py\n+++ b/torch/nn/utils/clip_grad.py\n@@ -46,7 +46,7 @@ def clip_grad_norm_(\n = _group_tensors_by_device_and_dtype([[g.detach() for g in grads]]) # type: ignore[assignment]\n \n if norm_type == inf:\n- norms = [g.detach().abs().max().to(first_device) for g in grads]\n+ norms = [torch.linalg.vector_norm(g.detach(), inf).to(first_device) for g in grads]\n total_norm = norms[0] if len(norms) == 1 else torch.max(torch.stack(norms))\n else:\n norms = []\n@@ -56,9 +56,9 @@ def clip_grad_norm_(\n elif foreach:\n raise RuntimeError(f'foreach=True was passed, but can\\'t use the foreach API on {device.type} tensors')\n else:\n- norms.extend([torch.norm(g, norm_type) for g in grads])\n+ norms.extend([torch.linalg.vector_norm(g, norm_type) for g in grads])\n \n- total_norm = torch.norm(torch.stack([norm.to(first_device) for norm in norms]), norm_type)\n+ total_norm = torch.linalg.vector_norm(torch.stack([norm.to(first_device) for norm in norms]), norm_type)\n \n if error_if_nonfinite and torch.logical_or(total_norm.isnan(), total_norm.isinf()):\n raise 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update to v3.1.1\n\n<|file_patch|>CHANGELOG.md\ndiff --git a/CHANGELOG.md b/CHANGELOG.md\nindex 66ae4209b9830a21e7bfd4ac94a440f1af5ebed9..c671d446653869a4769c9402516484d2f36ca8f2 100644\n--- a/CHANGELOG.md\n+++ b/CHANGELOG.md\n@@ -6,6 +6,10 @@ All notable changes to [tiny-svg](https://github.com/bpmn-io/tiny-svg) are docum\n \n ___Note:__ Yet to be released changes appear here._\n \n+## 3.1.1\n+\n+* `CHORE`: rever to basic `clear`\n+\n ## 4.1.0\n \n * `FEAT`: use optimized `clear`\n\n"},"target_character_start":{"kind":"number","value":55,"string":"55"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-06"},"utf8_bytes":{"kind":"number","value":507,"string":"507"},"document_order_key":{"kind":"number","value":2950677268360528000,"string":"2,950,677,268,360,528,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bpmn-io/tiny-svg"},"quality_band":{"kind":"string","value":"06"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"markdown"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bpmn-io/tiny-svg\",\"commit_oid\":\"6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b\",\"commits_ago_from_head\":25,\"content_sha256\":\"e7f59ca20631f88ba93bc8421e4aea1e8bce04800b8390bcf722432be69f2a59\",\"manifest_sha256\":null,\"parent_oid\":\"86a56f5ff5a4c90f409255e71fd9dd1c3a9d3652\",\"repository_id\":\"github.com/bpmn-io/tiny-svg\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"06\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":6},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":4,\"scope\":\"CHANGELOG\",\"subject_length\":16,\"trailer_names\":[],\"type\":\"chore\"},\"patch_statistics\":{\"added_lines\":4,\"context_bytes\":2080,\"deleted_lines\":0,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":424,\"patch_sha256\":\"bbd3f2839e79ef2cb01a54e62dbc01f2bb2f358683d780f5e7c87fdca4fb175f\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"markdown\",\"path\":\"CHANGELOG.md\",\"purpose\":\"docs\"}],\"primary_language\":\"markdown\"},\"quality_band\":\"06\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":2080,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":424},\"commit_oid\":\"6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b\",\"identity\":{\"author_email\":\"nico.rehwaldt@camunda.com\",\"author_name\":\"Nico Rehwaldt\",\"authored_at\":\"2024-05-29T22:49:44+02:00\",\"commit_oid\":\"6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b\",\"commits_ago_from_head\":25,\"committed_at\":\"2024-05-29T22:56:51+02:00\",\"committer_email\":\"nico.rehwaldt@camunda.com\",\"committer_name\":\"Nico Rehwaldt\",\"parent_oid\":\"86a56f5ff5a4c90f409255e71fd9dd1c3a9d3652\",\"tree_oid\":\"e7f7f2da92ce62d6054510e11ca1c6f3f3f71540\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"main\",\"history_collected\":{\"commits_read\":137,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"8016fa1351833a668307dc5a4a586a5f1f259f8b\",\"oldest_commit\":\"908613dcc310e8dab40aeaadad1d9d0850ae553a\"},\"recorded_head_commit\":\"8016fa1351833a668307dc5a4a586a5f1f259f8b\",\"repository_id\":\"github.com/bpmn-io/tiny-svg\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/bpmn-io/tiny-svg\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":79680,\"manifest_sha256\":null,\"split\":\"00-of-16\"}},\"parents\":[\"commit:github.com/bpmn-io/tiny-svg@6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b__download_changed_file_contents_eb3080c31631__render_commit_patches_5830561f004a\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16086,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/bitrise-io/backstage@33333c94169e1d349f0568516c74143e7d9ddd9a"},"text":{"kind":"string","value":"<|commit_message|>\ncatalog-backend: implement caching in the processing orchestrator\n\nCo-authored-by: Johan Haals <johan.haals@gmail.com>\nCo-authored-by: Fredrik Adelöw <freben@gmail.com>\nCo-authored-by: blam <ben@blam.sh>\nSigned-off-by: Patrik Oldsberg <poldsberg@gmail.com>\n\n<|file_patch|>plugins/catalog-backend/src/ingestion/LocationReaders.ts\ndiff --git a/plugins/catalog-backend/src/ingestion/LocationReaders.ts b/plugins/catalog-backend/src/ingestion/LocationReaders.ts\nindex 624c7aaa612d74bbec5d7ec85cfa72c0b0c01330..b8c9125893cd999cb414c84d59f14a5d73688d68 100644\n--- a/plugins/catalog-backend/src/ingestion/LocationReaders.ts\n+++ b/plugins/catalog-backend/src/ingestion/LocationReaders.ts\n@@ -52,6 +52,13 @@ type Options = {\n policy: EntityPolicy;\n };\n \n+const noopCache = {\n+ async get() {\n+ return undefined;\n+ },\n+ async set() {},\n+};\n+\n /**\n * Implements the reading of a location through a series of processor tasks.\n */\n@@ -167,6 +174,7 @@ export class LocationReaders implements LocationReader {\n item.optional,\n validatedEmit,\n this.options.parser,\n+ noopCache,\n )\n ) {\n return;\n@@ -215,6 +223,7 @@ export class LocationReaders implements LocationReader {\n item.location,\n emit,\n originLocation,\n+ noopCache,\n );\n } catch (e) {\n const message = `Processor ${\n@@ -285,6 +294,7 @@ export class LocationReaders implements LocationReader {\n current,\n item.location,\n emit,\n+ noopCache,\n );\n } catch (e) {\n const message = `Processor ${\n\n<|file_patch|>plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts\ndiff --git a/plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts b/plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts\nindex 34ddb544ea3edb998363a2d7cb8627ae714bee5e..67bd0715df741734c9d34fb599639c312ccb2527 100644\n--- a/plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts\n+++ b/plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts\n@@ -44,6 +44,10 @@ type CacheItem = {\n export class UrlReaderProcessor implements CatalogProcessor {\n constructor(private readonly options: Options) {}\n \n+ getProcessorName() {\n+ return 'url-reader';\n+ }\n+\n async readLocation(\n location: LocationSpec,\n optional: boolean,\n@@ -74,13 +78,11 @@ export class UrlReaderProcessor implements CatalogProcessor {\n }\n }\n \n- const isOnlyEntities = parseResults.every(\n- (r): r is CatalogProcessorEntityResult => r.type === 'entity',\n- );\n+ const isOnlyEntities = parseResults.every(r => r.type === 'entity');\n if (newEtag && isOnlyEntities) {\n await cache.set<CacheItem>(CACHE_KEY, {\n etag: newEtag,\n- value: parseResults,\n+ value: parseResults as CatalogProcessorEntityResult[],\n });\n }\n } catch (error) {\n@@ -121,7 +123,7 @@ export class UrlReaderProcessor implements CatalogProcessor {\n \n // Otherwise do a plain read, prioritizing readUrl if available\n if (this.options.reader.readUrl) {\n- const data = await this.options.reader.readUrl(location);\n+ const data = await this.options.reader.readUrl(location, { etag });\n return [[{ url: location, data: await data.buffer() }], data.etag];\n }\n \n\n<|file_patch|>plugins/catalog-backend/src/ingestion/processors/types.ts\ndiff --git a/plugins/catalog-backend/src/ingestion/processors/types.ts b/plugins/catalog-backend/src/ingestion/processors/types.ts\nindex 6e1488a36e1112f8edb2940c0df147b8018c33bd..752789703f85c3edd3ad1026a6419bcb72400d1a 100644\n--- a/plugins/catalog-backend/src/ingestion/processors/types.ts\n+++ b/plugins/catalog-backend/src/ingestion/processors/types.ts\n@@ -22,6 +22,12 @@ import {\n import { JsonValue } from '@backstage/config';\n \n export type CatalogProcessor = {\n+ /**\n+ * A unique identifier for the Catalog Processor.\n+ * It's strongly recommended implement getProcessorName as this method will be required in the future.\n+ */\n+ getProcessorName?(): string;\n+\n /**\n * Reads the contents of a location.\n *\n\n<|file_patch|>plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\ndiff --git a/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts b/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\nindex f7dede4adb0397196fb5f5f566f1fb5c00e49dce..b4b309beeffe3b0b3387df16b6ee1811e8befd54 100644\n--- a/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\n+++ b/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\n@@ -55,7 +55,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n relations: [],\n errors: [],\n deferredEntities: [],\n- state: new Map(),\n+ state: {},\n });\n const engine = new DefaultCatalogProcessingEngine(\n getVoidLogger(),\n@@ -84,7 +84,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n metadata: { name: 'test' },\n },\n resultHash: '',\n- state: new Map(),\n+ state: {},\n nextUpdateAt: DateTime.now(),\n lastDiscoveryAt: DateTime.now(),\n },\n@@ -117,7 +117,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n relations: [],\n errors: [],\n deferredEntities: [],\n- state: new Map(),\n+ state: {},\n });\n const engine = new DefaultCatalogProcessingEngine(\n getVoidLogger(),\n@@ -147,7 +147,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n metadata: { name: 'test' },\n },\n resultHash: '',\n- state: new Map(),\n+ state: {},\n nextUpdateAt: DateTime.now(),\n lastDiscoveryAt: DateTime.now(),\n },\n@@ -181,7 +181,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n entityRef: '',\n unprocessedEntity: entity,\n resultHash: 'the matching hash',\n- state: new Map(),\n+ state: {},\n nextUpdateAt: DateTime.now(),\n lastDiscoveryAt: DateTime.now(),\n };\n@@ -194,7 +194,7 @@ describe('DefaultCatalogProcessingEngine', () => {\n relations: [],\n errors: [],\n deferredEntities: [],\n- state: new Map(),\n+ state: {},\n });\n \n const engine = new DefaultCatalogProcessingEngine(\n\n<|file_patch|>plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts\ndiff --git a/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts b/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts\nindex 4d2d74f05b65d082667aba4a5554c2b3e3bc3888..bbdac66b5835b3d4c0eb6a42a6cc3c637fc64cf4 100644\n--- a/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts\n+++ b/plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts\n@@ -167,8 +167,7 @@ export class DefaultCatalogProcessingEngine implements CatalogProcessingEngine {\n hashBuilder = hashBuilder\n .update(stableStringify({ ...result.completedEntity }))\n .update(stableStringify([...result.deferredEntities]))\n- .update(stableStringify([...result.relations]))\n- .update(stableStringify(Object.fromEntries(result.state)));\n+ .update(stableStringify([...result.relations]));\n }\n \n const resultHash = hashBuilder.digest('hex');\n\n<|file_patch|>plugins/catalog-backend/src/next/DefaultLocationService.test.ts\ndiff --git a/plugins/catalog-backend/src/next/DefaultLocationService.test.ts b/plugins/catalog-backend/src/next/DefaultLocationService.test.ts\nindex 939f54e793668a9e2fc787a1e65d5d5ad86b9875..10c9a742c514fc765daed3b10bb965aaab40712a 100644\n--- a/plugins/catalog-backend/src/next/DefaultLocationService.test.ts\n+++ b/plugins/catalog-backend/src/next/DefaultLocationService.test.ts\n@@ -39,7 +39,7 @@ describe('DefaultLocationServiceTest', () => {\n store.listLocations.mockResolvedValueOnce([]);\n orchestrator.process.mockResolvedValueOnce({\n ok: true,\n- state: new Map(),\n+ state: {},\n completedEntity: {\n apiVersion: 'backstage.io/v1alpha1',\n kind: 'Location',\n@@ -65,7 +65,7 @@ describe('DefaultLocationServiceTest', () => {\n \n orchestrator.process.mockResolvedValueOnce({\n ok: true,\n- state: new Map(),\n+ state: {},\n completedEntity: {\n apiVersion: 'backstage.io/v1alpha1',\n kind: 'Component',\n\n<|file_patch|>plugins/catalog-backend/src/next/DefaultLocationService.ts\ndiff --git a/plugins/catalog-backend/src/next/DefaultLocationService.ts b/plugins/catalog-backend/src/next/DefaultLocationService.ts\nindex 7d485bea40df81d6e21282c7e193dfc4f97e23c6..678ce9791c783b0d65327a07ff6070b9c344f655 100644\n--- a/plugins/catalog-backend/src/next/DefaultLocationService.ts\n+++ b/plugins/catalog-backend/src/next/DefaultLocationService.ts\n@@ -87,7 +87,6 @@ export class DefaultLocationService implements LocationService {\n { entity, locationKey: `${spec.type}:${spec.target}` },\n ];\n const entities: Entity[] = [];\n- const state = new Map(); // ignored\n while (unprocessedEntities.length) {\n const currentEntity = unprocessedEntities.pop();\n if (!currentEntity) {\n@@ -95,7 +94,7 @@ export class DefaultLocationService implements LocationService {\n }\n const processed = await this.orchestrator.process({\n entity: currentEntity.entity,\n- state,\n+ state: {}, // we process without the existing cache\n });\n \n if (processed.ok) {\n\n<|file_patch|>plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\ndiff --git a/plugins/catalog-backend/src/next/DefaultRefreshService.test.ts b/plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\nindex 5df57c6897af32dfffefe981c36ec6289222a75d..79ced3ea430dba702c0b60f07a3db2f1d1bc67d9 100644\n--- a/plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\n+++ b/plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\n@@ -138,7 +138,7 @@ describe('Refresh integration', () => {\n relations: [],\n errors: [],\n deferredEntities,\n- state: new Map(),\n+ state: {},\n };\n },\n },\n\n<|file_patch|>plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts\ndiff --git a/plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts b/plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts\nindex 8ba9d54b8fa7564c5b0af2866ce75e6bcb035ffd..263ba1bdfd3dca4be9e18e4feb877e20e9ca3337 100644\n--- a/plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts\n+++ b/plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts\n@@ -15,7 +15,6 @@\n */\n \n import { Entity, stringifyEntityRef } from '@backstage/catalog-model';\n-import { JsonObject } from '@backstage/config';\n import { ConflictError, NotFoundError } from '@backstage/errors';\n import { Knex } from 'knex';\n import lodash from 'lodash';\n@@ -80,7 +79,7 @@ export class DefaultProcessingDatabase implements ProcessingDatabase {\n .update({\n processed_entity: JSON.stringify(processedEntity),\n result_hash: resultHash,\n- cache: JSON.stringify(Object.fromEntries(state || [])),\n+ cache: JSON.stringify(state),\n errors,\n location_key: locationKey,\n })\n@@ -508,9 +507,7 @@ export class DefaultProcessingDatabase implements ProcessingDatabase {\n resultHash: i.result_hash || '',\n nextUpdateAt: timestampToDateTime(i.next_update_at),\n lastDiscoveryAt: timestampToDateTime(i.last_discovery_at),\n- state: i.cache\n- ? JSON.parse(i.cache)\n- : new Map<string, JsonObject>(),\n+ state: i.cache ? JSON.parse(i.cache) : undefined,\n errors: i.errors,\n locationKey: i.location_key,\n } as RefreshStateItem),\n\n<|file_patch|>plugins/catalog-backend/src/next/database/types.ts\ndiff --git a/plugins/catalog-backend/src/next/database/types.ts b/plugins/catalog-backend/src/next/database/types.ts\nindex 3dfe8e5592884062c1b482a90a66f264e9de2280..ab449c8a7abba4550753df7ab4861ad622cb9e8c 100644\n--- a/plugins/catalog-backend/src/next/database/types.ts\n+++ b/plugins/catalog-backend/src/next/database/types.ts\n@@ -15,7 +15,7 @@\n */\n \n import { Entity, EntityRelationSpec } from '@backstage/catalog-model';\n-import { JsonObject } from '@backstage/config';\n+import { JsonValue } from '@backstage/config';\n import { DateTime } from 'luxon';\n import { Transaction } from '../../database/types';\n import { DeferredEntity } from '../processing/types';\n@@ -36,7 +36,7 @@ export type UpdateProcessedEntityOptions = {\n id: string;\n processedEntity: Entity;\n resultHash: string;\n- state?: Map<string, JsonObject>;\n+ state?: JsonValue;\n errors?: string;\n relations: EntityRelationSpec[];\n deferredEntities: DeferredEntity[];\n@@ -57,7 +57,7 @@ export type RefreshStateItem = {\n resultHash: string;\n nextUpdateAt: DateTime;\n lastDiscoveryAt: DateTime; // remove?\n- state: Map<string, JsonObject>;\n+ state?: JsonValue;\n errors?: string;\n locationKey?: string;\n };\n\n<|file_patch|>plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts\ndiff --git a/plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts b/plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts\nindex 384060125e261aad8018ae9df632f210f4d9be23..e94c34a660929601179d1780a12b239639c924b8 100644\n--- a/plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts\n+++ b/plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts\n@@ -24,6 +24,7 @@ import {\n stringifyLocationReference,\n } from '@backstage/catalog-model';\n import { ConflictError, InputError, NotAllowedError } from '@backstage/errors';\n+import { JsonObject, JsonValue } from '@backstage/config';\n import { ScmIntegrationRegistry } from '@backstage/integration';\n import path from 'path';\n import { Logger } from 'winston';\n@@ -32,6 +33,7 @@ import {\n CatalogProcessorParser,\n } from '../../ingestion/processors';\n import * as results from '../../ingestion/processors/results';\n+import { CatalogProcessorCache } from '../../ingestion/processors/types';\n import {\n CatalogProcessingOrchestrator,\n EntityProcessingRequest,\n@@ -53,8 +55,70 @@ type Context = {\n location: LocationSpec;\n originLocation: LocationSpec;\n collector: ProcessorOutputCollector;\n+ cache: ProcessorCache;\n };\n \n+function isObject(value: JsonValue | undefined): value is JsonObject {\n+ return typeof value === 'object' && value !== null && !Array.isArray(value);\n+}\n+\n+class DefaultCatalogProcessorCache implements CatalogProcessorCache {\n+ private newState?: JsonObject;\n+ constructor(private readonly existingState: JsonObject) {}\n+\n+ async get<ItemType extends JsonValue>(\n+ key: string,\n+ ): Promise<ItemType | undefined> {\n+ return this.existingState[key] as ItemType | undefined;\n+ }\n+\n+ async set<ItemType extends JsonValue>(\n+ key: string,\n+ value: ItemType,\n+ ): Promise<void> {\n+ if (!this.newState) {\n+ this.newState = {};\n+ }\n+\n+ this.newState[key] = value;\n+ }\n+\n+ collect(): JsonObject | undefined {\n+ return this.newState;\n+ }\n+}\n+\n+class ProcessorCache {\n+ private caches = new Map<string, DefaultCatalogProcessorCache>();\n+\n+ constructor(private readonly existingState: JsonObject) {}\n+ forProcessor(processor: CatalogProcessor): CatalogProcessorCache {\n+ // constructor name will be deprecated in the future when we make `getProcessorName` required in the implementation\n+ const name = processor.getProcessorName?.() ?? processor.constructor.name;\n+ const cache = this.caches.get(name);\n+ if (cache) {\n+ return cache;\n+ }\n+\n+ const existing = this.existingState[name];\n+\n+ const newCache = new DefaultCatalogProcessorCache(\n+ isObject(existing) ? existing : {},\n+ );\n+ this.caches.set(name, newCache);\n+ return newCache;\n+ }\n+\n+ collect(): JsonObject {\n+ const result: JsonObject = {};\n+ for (const [key, value] of this.caches.entries()) {\n+ result[key] = value.collect();\n+ }\n+\n+ return result;\n+ }\n+}\n+\n export class DefaultCatalogProcessingOrchestrator\n implements CatalogProcessingOrchestrator\n {\n@@ -72,17 +136,23 @@ export class DefaultCatalogProcessingOrchestrator\n async process(\n request: EntityProcessingRequest,\n ): Promise<EntityProcessingResult> {\n- return this.processSingleEntity(request.entity);\n+ return this.processSingleEntity(request.entity, request.state);\n }\n \n private async processSingleEntity(\n unprocessedEntity: Entity,\n+ state: JsonValue | undefined,\n ): Promise<EntityProcessingResult> {\n const collector = new ProcessorOutputCollector(\n this.options.logger,\n unprocessedEntity,\n );\n \n+ // Cache that is scoped to the entity and processor\n+ const cache = new ProcessorCache(\n+ isObject(state) && isObject(state.cache) ? state.cache : {},\n+ );\n+\n try {\n // This will be checked and mutated step by step below\n let entity: Entity = unprocessedEntity;\n@@ -108,6 +178,7 @@ export class DefaultCatalogProcessingOrchestrator\n originLocation: parseLocationReference(\n getEntityOriginLocationRef(entity),\n ),\n+ cache,\n collector,\n };\n \n@@ -145,7 +216,7 @@ export class DefaultCatalogProcessingOrchestrator\n return {\n ...collectorResults,\n completedEntity: entity,\n- state: new Map(),\n+ state: { cache: cache.collect() },\n ok: true,\n };\n } catch (error) {\n@@ -173,6 +244,7 @@ export class DefaultCatalogProcessingOrchestrator\n context.location,\n context.collector.onEmit,\n context.originLocation,\n+ context.cache.forProcessor(processor),\n );\n } catch (e) {\n throw new InputError(\n@@ -306,6 +378,7 @@ export class DefaultCatalogProcessingOrchestrator\n false,\n context.collector.onEmit,\n this.options.parser,\n+ context.cache.forProcessor(processor),\n );\n if (read) {\n didRead = true;\n@@ -343,6 +416,7 @@ export class DefaultCatalogProcessingOrchestrator\n result,\n context.location,\n context.collector.onEmit,\n+ context.cache.forProcessor(processor),\n );\n } catch (e) {\n throw new InputError(\n\n<|file_patch|>plugins/catalog-backend/src/next/processing/types.ts\ndiff --git a/plugins/catalog-backend/src/next/processing/types.ts b/plugins/catalog-backend/src/next/processing/types.ts\nindex 9e30d0740484f387eb73078f0dfe0738c15a3a0d..59a10c084f5dfaf09abe745a1e91bf917cb5d78d 100644\n--- a/plugins/catalog-backend/src/next/processing/types.ts\n+++ b/plugins/catalog-backend/src/next/processing/types.ts\n@@ -15,17 +15,17 @@\n */\n \n import { Entity, EntityRelationSpec } from '@backstage/catalog-model';\n-import { JsonObject } from '@backstage/config';\n+import { JsonValue } from '@backstage/config';\n \n export type EntityProcessingRequest = {\n entity: Entity;\n- state: Map<string, JsonObject>; // Versions for multiple deployments etc\n+ state?: JsonValue; // Versions for multiple deployments etc\n };\n \n export type EntityProcessingResult =\n | {\n ok: true;\n- state: Map<string, JsonObject>;\n+ state: JsonValue;\n completedEntity: Entity;\n deferredEntities: DeferredEntity[];\n relations: EntityRelationSpec[];\n\n"},"target_character_start":{"kind":"number","value":277,"string":"277"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-06"},"utf8_bytes":{"kind":"number","value":19827,"string":"19,827"},"document_order_key":{"kind":"number","value":2950828702940838400,"string":"2,950,828,702,940,838,400"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/bitrise-io/backstage"},"quality_band":{"kind":"string","value":"06"},"tests_touched":{"kind":"bool","value":true,"string":"true"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"typescript"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/bitrise-io/backstage\",\"commit_oid\":\"33333c94169e1d349f0568516c74143e7d9ddd9a\",\"commits_ago_from_head\":8458,\"content_sha256\":\"4f9c6a1aecc1e4a416f57cd8f0ffc6f8e9058f7fb9d3b0faf00dcc5f336bd40e\",\"manifest_sha256\":null,\"parent_oid\":\"ec2cc1ec56854fb4067a6a873662df01f50719e1\",\"repository_id\":\"github.com/bitrise-io/backstage\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"06\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":6},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":22,\"scope\":null,\"subject_length\":65,\"trailer_names\":[\"Co-authored-by\",\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":118,\"context_bytes\":93586,\"deleted_lines\":31,\"files_changed\":12,\"hunk_count\":36,\"patch_bytes\":18599,\"patch_sha256\":\"1eed74bbd5b33ff5f6ff95226bd59c8fd9cd3929c8b227beb35ec341e9cc6557\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/ingestion/LocationReaders.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/ingestion/processors/UrlReaderProcessor.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/ingestion/processors/types.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\",\"purpose\":\"tests\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/DefaultLocationService.test.ts\",\"purpose\":\"tests\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/DefaultLocationService.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\",\"purpose\":\"tests\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/database/types.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/processing/DefaultCatalogProcessingOrchestrator.ts\",\"purpose\":\"source\"},{\"language\":\"typescript\",\"path\":\"plugins/catalog-backend/src/next/processing/types.ts\",\"purpose\":\"source\"}],\"primary_language\":\"typescript\"},\"quality_band\":\"06\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[\"plugins/catalog-backend/src/next/DefaultCatalogProcessingEngine.test.ts\",\"plugins/catalog-backend/src/next/DefaultLocationService.test.ts\",\"plugins/catalog-backend/src/next/DefaultRefreshService.test.ts\"],\"touched\":true},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":93586,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":13,\"files_kept\":12,\"patch_bytes\":18599},\"commit_oid\":\"33333c94169e1d349f0568516c74143e7d9ddd9a\",\"identity\":{\"author_email\":\"poldsberg@gmail.com\",\"author_name\":\"Patrik Oldsberg\",\"authored_at\":\"2021-09-20T16:14:45+02:00\",\"commit_oid\":\"33333c94169e1d349f0568516c74143e7d9ddd9a\",\"commits_ago_from_head\":8458,\"committed_at\":\"2021-09-23T14:42:52+02:00\",\"committer_email\":\"johan.haals@gmail.com\",\"committer_name\":\"Johan Haals\",\"parent_oid\":\"ec2cc1ec56854fb4067a6a873662df01f50719e1\",\"tree_oid\":\"49daa5d90d1340fb0ae4116b122d90ee6e37d0fe\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"plugins/catalog-backend/src/next/database/DefaultProcessingDatabase.test.ts\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"6237784730ec7cb965e081f7738bd2f93f8aa6a3\",\"oldest_commit\":\"07410d1e9b4bcaa07c2922dfdaf04810827b41c3\"},\"recorded_head_commit\":\"6237784730ec7cb965e081f7738bd2f93f8aa6a3\",\"repository_id\":\"github.com/bitrise-io/backstage\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/bitrise-io/backstage\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":73463,\"manifest_sha256\":null,\"split\":\"07-of-16\"}},\"parents\":[\"commit:github.com/bitrise-io/backstage@33333c94169e1d349f0568516c74143e7d9ddd9a__download_changed_file_contents_297cf79d262f__drop_changed_files_over_maximum_character_count_32e9efb06a0c__render_commit_patches_94d304eb7ebe\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16087,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/aospa/android_kernel_samsung_tuna@4ea6b8974ad3b39b14bd30746229b3a2978e8512"},"text":{"kind":"string","value":"<|commit_message|>\nipv6: updates to privacy addresses per RFC 4941\n\nUpdate the code to handle some of the differences between\nRFC 3041 and RFC 4941, which obsoletes it. Also a couple\nof janitorial fixes.\n\n- Allow router advertisements to increase the lifetime of\n temporary addresses. This was not allowed by RFC 3041,\n but is specified by RFC 4941. It is useful when RA\n lifetimes are lower than TEMP_{VALID,PREFERRED}_LIFETIME:\n in this case, the previous code would delete or deprecate\n addresses prematurely.\n\n- Change the default of MAX_RETRY to 3 per RFC 4941.\n\n- Add a comment to clarify that the preferred and valid\n lifetimes in inet6_ifaddr are relative to the timestamp.\n\n- Shorten lines to 80 characters in a couple of places.\n\nChange-Id: I4da097664d4b1de7c1cebf410895319601c7f1cc\nSigned-off-by: Lorenzo Colitti <lorenzo@google.com>\nSigned-off-by: JP Abgrall <jpa@google.com>\n\n<|file_patch|>include/net/addrconf.h\ndiff --git a/include/net/addrconf.h b/include/net/addrconf.h\nindex 582e4ae707530f45df3f3a513dc1e1a418e89784..cbc6bb0a68386da58ec539fe19fa3cc7356fdfdc 100644\n--- a/include/net/addrconf.h\n+++ b/include/net/addrconf.h\n@@ -8,7 +8,7 @@\n \n #define TEMP_VALID_LIFETIME\t\t(7*86400)\n #define TEMP_PREFERRED_LIFETIME\t\t(86400)\n-#define REGEN_MAX_RETRY\t\t\t(5)\n+#define REGEN_MAX_RETRY\t\t\t(3)\n #define MAX_DESYNC_FACTOR\t\t(600)\n \n #define ADDR_CHECK_FREQUENCY\t\t(120*HZ)\n\n<|file_patch|>include/net/if_inet6.h\ndiff --git a/include/net/if_inet6.h b/include/net/if_inet6.h\nindex 11cf373970a960d248a3c7d240c62e9f20f3512c..51a7031b4aa379463a56fca35f69f97dfdf4ffa8 100644\n--- a/include/net/if_inet6.h\n+++ b/include/net/if_inet6.h\n@@ -41,6 +41,7 @@ struct inet6_ifaddr {\n \tstruct in6_addr\t\taddr;\n \t__u32\t\t\tprefix_len;\n \t\n+\t/* In seconds, relative to tstamp. Expiry is at tstamp + HZ * lft. */\n \t__u32\t\t\tvalid_lft;\n \t__u32\t\t\tprefered_lft;\n \tatomic_t\t\trefcnt;\n\n"},"target_character_start":{"kind":"number","value":895,"string":"895"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-03"},"utf8_bytes":{"kind":"number","value":1866,"string":"1,866"},"document_order_key":{"kind":"number","value":2951115893635471000,"string":"2,951,115,893,635,471,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/aospa/android_kernel_samsung_tuna"},"quality_band":{"kind":"string","value":"03"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"c"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/aospa/android_kernel_samsung_tuna\",\"commit_oid\":\"4ea6b8974ad3b39b14bd30746229b3a2978e8512\",\"commits_ago_from_head\":6289,\"content_sha256\":\"a73aafccafbdfecdc649890c7bea585367167f2d3ea3f68eb5f8d64d6a779072\",\"manifest_sha256\":null,\"parent_oid\":\"f44baeb72a29a1a7c6e9cfb626e1798184396a03\",\"repository_id\":\"github.com/aospa/android_kernel_samsung_tuna\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"03\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":3},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":129,\"scope\":null,\"subject_length\":47,\"trailer_names\":[\"Change-Id\",\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":2,\"context_bytes\":15060,\"deleted_lines\":1,\"files_changed\":2,\"hunk_count\":2,\"patch_bytes\":895,\"patch_sha256\":\"539c0c40ec4ff0a6f6565169f0405eac7b4713bc9b007db2f0a1c9e77f86abfe\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"c\",\"path\":\"include/net/addrconf.h\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"include/net/if_inet6.h\",\"purpose\":\"source\"}],\"primary_language\":\"c\"},\"quality_band\":\"03\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":15060,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":3,\"files_kept\":2,\"patch_bytes\":895},\"commit_oid\":\"4ea6b8974ad3b39b14bd30746229b3a2978e8512\",\"identity\":{\"author_email\":\"jpa@google.com\",\"author_name\":\"JP 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Abgrall\",\"parent_oid\":\"f44baeb72a29a1a7c6e9cfb626e1798184396a03\",\"tree_oid\":\"9d8cd9c325d09c62abc9a317c856d6bfa2b466c1\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"net/ipv6/addrconf.c\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"kitkat\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"296447aff3342b95c17ee93f6b393127f0bd4f5e\",\"oldest_commit\":\"b779260b097dec295e8798277ed08ec5ecd3b2c1\"},\"recorded_head_commit\":\"296447aff3342b95c17ee93f6b393127f0bd4f5e\",\"repository_id\":\"github.com/aospa/android_kernel_samsung_tuna\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/aospa/android_kernel_samsung_tuna\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":32786,\"manifest_sha256\":null,\"split\":\"02-of-16\"}},\"parents\":[\"commit:github.com/aospa/android_kernel_samsung_tuna@4ea6b8974ad3b39b14bd30746229b3a2978e8512__download_changed_file_contents_cfd5d4c0920b__drop_changed_files_over_maximum_character_count_3c7fa3c52989__render_commit_patches_fa1c42d5b911\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16088,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/appleseedhq/appleseed@0cb0da1c42451609db2232e1c95eaf92282d9fb7"},"text":{"kind":"string","value":"<|commit_message|>\nRemove get / set render layer indices from python bindings.\n\n<|file_patch|>src/appleseed.python/bindentity.cpp\ndiff --git a/src/appleseed.python/bindentity.cpp b/src/appleseed.python/bindentity.cpp\nindex cce69b616332ff9bcf5392d9215651aedc770cec..25170759bdb7099566db44019299f4755a7fe08a 100644\n--- a/src/appleseed.python/bindentity.cpp\n+++ b/src/appleseed.python/bindentity.cpp\n@@ -86,9 +86,6 @@ void bind_entity()\n \n .def(\"get_parameters\", entity_get_parameters)\n .def(\"set_parameters\", entity_set_parameters)\n-\n- .def(\"set_render_layer_index\", &Entity::set_render_layer_index)\n- .def(\"get_render_layer_index\", &Entity::get_render_layer_index)\n ;\n \n bpy::class_<ConnectableEntity, auto_release_ptr<ConnectableEntity>, bpy::bases<Entity>, boost::noncopyable>(\"ConnectableEntity\", bpy::no_init);\n\n"},"target_character_start":{"kind":"number","value":80,"string":"80"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-04"},"utf8_bytes":{"kind":"number","value":857,"string":"857"},"document_order_key":{"kind":"number","value":2951520343500545000,"string":"2,951,520,343,500,545,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/appleseedhq/appleseed"},"quality_band":{"kind":"string","value":"04"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"cpp"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/appleseedhq/appleseed\",\"commit_oid\":\"0cb0da1c42451609db2232e1c95eaf92282d9fb7\",\"commits_ago_from_head\":3114,\"content_sha256\":\"4965b9ddf82ca40d090160fc18e26437d150128bd4c9d345aac02fa2291725e2\",\"manifest_sha256\":null,\"parent_oid\":\"51a54ee855e55c0df2b666fe9d22f65145c99136\",\"repository_id\":\"github.com/appleseedhq/appleseed\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"04\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":4},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":10,\"scope\":null,\"subject_length\":59,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":0,\"context_bytes\":3919,\"deleted_lines\":3,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":726,\"patch_sha256\":\"138170b20755d44dbdc0d912890366174aa43693a1a09ffbea99062058146036\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"cpp\",\"path\":\"src/appleseed.python/bindentity.cpp\",\"purpose\":\"source\"}],\"primary_language\":\"cpp\"},\"quality_band\":\"04\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":3919,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":726},\"commit_oid\":\"0cb0da1c42451609db2232e1c95eaf92282d9fb7\",\"identity\":{\"author_email\":\"ramenhdr@gmail.com\",\"author_name\":\"est77\",\"authored_at\":\"2017-02-26T12:38:53+01:00\",\"commit_oid\":\"0cb0da1c42451609db2232e1c95eaf92282d9fb7\",\"commits_ago_from_head\":3114,\"committed_at\":\"2017-03-10T11:54:01+01:00\",\"committer_email\":\"ramenhdr@gmail.com\",\"committer_name\":\"est77\",\"parent_oid\":\"51a54ee855e55c0df2b666fe9d22f65145c99136\",\"tree_oid\":\"6571125cea67d8a6e9c7f693181bd2bc348d0f7d\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"c4ba82893febd711befb194f905e955d3ee143a3\",\"oldest_commit\":\"1bd7c7a7b6ed68b7b23660c60bcb5c02d969e32b\"},\"recorded_head_commit\":\"c4ba82893febd711befb194f905e955d3ee143a3\",\"repository_id\":\"github.com/appleseedhq/appleseed\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/appleseedhq/appleseed\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":42087,\"manifest_sha256\":null,\"split\":\"07-of-16\"}},\"parents\":[\"commit:github.com/appleseedhq/appleseed@0cb0da1c42451609db2232e1c95eaf92282d9fb7__download_changed_file_contents_e22918dc4af2__render_commit_patches_84ad2d8be76a\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16089,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/ckan/ckan@3d944d4bbf0f816dd61923227df5a5231e0cba5a"},"text":{"kind":"string","value":"<|commit_message|>\nFix tests\n\n<|file_patch|>ckan/tests/lib/dictization/test_dictization.py\ndiff --git a/ckan/tests/lib/dictization/test_dictization.py b/ckan/tests/lib/dictization/test_dictization.py\nindex acbaeb6ba08bb5d2651871d2e564145f176eb927..7405fb1700f361fa0b981dc989125aece6d1788e 100644\n--- a/ckan/tests/lib/dictization/test_dictization.py\n+++ b/ckan/tests/lib/dictization/test_dictization.py\n@@ -22,6 +22,16 @@ from ckan.lib.dictization.model_save import (\n package_tag_list_save,\n )\n \n+from sqlalchemy import inspect\n+\n+\n+@pytest.fixture(autouse=True, scope=\"function\")\n+@pytest.mark.ckan_config(\"ckan.plugins\", \"activity\")\n+def apply_activity_migrations(clean_db, with_plugins, migrate_db_for):\n+ migrate_db_for(\"activity\")\n+ columns = inspect(model.Session.bind).get_columns(\"activity\")\n+ assert \"permission_labels\" in [c[\"name\"] for c in columns]\n+\n \n @pytest.mark.usefixtures(\"clean_db\")\n class TestBasicDictize:\n\n<|file_patch|>ckanext/activity/tests/logic/test_functional.py\ndiff --git a/ckanext/activity/tests/logic/test_functional.py b/ckanext/activity/tests/logic/test_functional.py\nindex e0531331cc44162a0b725e4714d3a530a12d6b1f..c0a26350c16ac3e852e67ffb70bc83b66972b86b 100644\n--- a/ckanext/activity/tests/logic/test_functional.py\n+++ b/ckanext/activity/tests/logic/test_functional.py\n@@ -4,10 +4,21 @@ import pytest\n \n from bs4 import BeautifulSoup\n \n+from ckan import model\n import ckan.plugins.toolkit as tk\n import ckan.tests.helpers as helpers\n import ckan.tests.factories as factories\n \n+from sqlalchemy import inspect\n+\n+\n+@pytest.fixture(autouse=True, scope=\"function\")\n+@pytest.mark.ckan_config(\"ckan.plugins\", \"activity\")\n+def apply_activity_migrations(clean_db, with_plugins, migrate_db_for):\n+ migrate_db_for(\"activity\")\n+ columns = inspect(model.Session.bind).get_columns(\"activity\")\n+ assert \"permission_labels\" in [c[\"name\"] for c in columns]\n+\n \n @pytest.mark.ckan_config(\"ckan.plugins\", \"activity\")\n @pytest.mark.usefixtures(\"clean_db\", \"with_plugins\", \"reset_index\")\n\n"},"target_character_start":{"kind":"number","value":30,"string":"30"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":2029,"string":"2,029"},"document_order_key":{"kind":"number","value":2951699239668202500,"string":"2,951,699,239,668,202,500"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/ckan/ckan"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":true,"string":"true"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"python"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/ckan/ckan\",\"commit_oid\":\"3d944d4bbf0f816dd61923227df5a5231e0cba5a\",\"commits_ago_from_head\":3163,\"content_sha256\":\"382d2a5c4517f70205e2788fdf9566dee90f39186c02b6ecd79b25ab281c31b8\",\"manifest_sha256\":null,\"parent_oid\":\"221f8b9f6cf3e74cde63867259d37682160a1904\",\"repository_id\":\"github.com/ckan/ckan\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":2,\"reason\":\"throwaway_message\"},{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":5,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":2,\"scope\":null,\"subject_length\":9,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":21,\"context_bytes\":14641,\"deleted_lines\":0,\"files_changed\":2,\"hunk_count\":2,\"patch_bytes\":1874,\"patch_sha256\":\"b065e479ab5840f60c3fee1e908568c2d7625ad7c14a647db5fa9e08632da9d4\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"python\",\"path\":\"ckan/tests/lib/dictization/test_dictization.py\",\"purpose\":\"tests\"},{\"language\":\"python\",\"path\":\"ckanext/activity/tests/logic/test_functional.py\",\"purpose\":\"tests\"}],\"primary_language\":\"python\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[\"ckan/tests/lib/dictization/test_dictization.py\",\"ckanext/activity/tests/logic/test_functional.py\"],\"touched\":true},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":14641,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":2,\"patch_bytes\":1874},\"commit_oid\":\"3d944d4bbf0f816dd61923227df5a5231e0cba5a\",\"identity\":{\"author_email\":\"viktoria.georgieva@cst-bg.net\",\"author_name\":\"Viktoria Georgieva\",\"authored_at\":\"2023-07-29T15:37:15+03:00\",\"commit_oid\":\"3d944d4bbf0f816dd61923227df5a5231e0cba5a\",\"commits_ago_from_head\":3163,\"committed_at\":\"2023-07-29T15:37:15+03:00\",\"committer_email\":\"viktoria.georgieva@cst-bg.net\",\"committer_name\":\"Viktoria Georgieva\",\"parent_oid\":\"221f8b9f6cf3e74cde63867259d37682160a1904\",\"tree_oid\":\"3103816cc6b5d3978ab2421d66af7dd4f71d1c41\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"960ce25ceddd97a3490a9d07def685ac09346c90\",\"oldest_commit\":\"7600b9cf6522680503ba27cc33f3d9d9a7109c71\"},\"recorded_head_commit\":\"960ce25ceddd97a3490a9d07def685ac09346c90\",\"repository_id\":\"github.com/ckan/ckan\",\"snapshot_check\":\"repo_moved_ahead_of_recorded_head\"},\"repository_id\":\"github.com/ckan/ckan\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":88974,\"manifest_sha256\":null,\"split\":\"14-of-16\"}},\"parents\":[\"commit:github.com/ckan/ckan@3d944d4bbf0f816dd61923227df5a5231e0cba5a__download_changed_file_contents_987a9ce52df9__render_commit_patches_ed80d4364995\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16090,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/coolsnowwolf/lede@39ee2e1f98dc4868f8ab770e27c04c3fb26e2822"},"text":{"kind":"string","value":"<|commit_message|>\nlibcap: update to 2.68\n\nRelease Notes:\nhttps://sites.google.com/site/fullycapable/release-notes-for-libcap#h.vdh3d47czmle\n\nSigned-off-by: Nick Hainke <vincent@systemli.org>\n\n<|file_patch|>package/libs/libcap/Makefile\ndiff --git a/package/libs/libcap/Makefile b/package/libs/libcap/Makefile\nindex a35b5e394fa56b85b5468e4abfff78718a1fb7db..6f51b5d5edd991ca63aa1bee3eb02b64a1f0c7f4 100644\n--- a/package/libs/libcap/Makefile\n+++ b/package/libs/libcap/Makefile\n@@ -6,12 +6,12 @@\n include $(TOPDIR)/rules.mk\n \n PKG_NAME:=libcap\n-PKG_VERSION:=2.67\n+PKG_VERSION:=2.68\n PKG_RELEASE:=1\n \n PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\n PKG_SOURCE_URL:=@KERNEL/linux/libs/security/linux-privs/libcap2\n-PKG_HASH:=ce9b22fdc271beb6dae7543da5f74cf24cb82e6848cfd088a5a069dec5ea5198\n+PKG_HASH:=90be3b6d41be5f81ae4b03ec76012b0d27c829293684f6c05b65d5f9cce724b2\n \n PKG_MAINTAINER:=Paul Wassi <p.wassi@gmx.at>\n PKG_LICENSE:=GPL-2.0-only\n\n"},"target_character_start":{"kind":"number","value":193,"string":"193"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-10"},"utf8_bytes":{"kind":"number","value":936,"string":"936"},"document_order_key":{"kind":"number","value":2951881708735571000,"string":"2,951,881,708,735,571,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/coolsnowwolf/lede"},"quality_band":{"kind":"string","value":"10"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":0,"string":"0"},"primary_language":{"kind":"string","value":"makefile"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/coolsnowwolf/lede\",\"commit_oid\":\"39ee2e1f98dc4868f8ab770e27c04c3fb26e2822\",\"commits_ago_from_head\":1970,\"content_sha256\":\"9774df7c411ccd4f798a6828a87bd6808c7212412c68614976cab377eb76ae63\",\"manifest_sha256\":null,\"parent_oid\":\"4bba40608bd2b9c05ee33cff62277a4efe7ebda7\",\"repository_id\":\"github.com/coolsnowwolf/lede\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"10\",\"commit_quality_score\":{\"commit_score\":0,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":0,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":0},\"rubric_version\":2,\"tier\":10},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":11,\"scope\":null,\"subject_length\":22,\"trailer_names\":[\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":2,\"context_bytes\":3407,\"deleted_lines\":2,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":699,\"patch_sha256\":\"70523cdd85802fc205672a32fb89ca3f19eb3f174e2887804c2e1f25a856c086\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"makefile\",\"path\":\"package/libs/libcap/Makefile\",\"purpose\":\"build\"}],\"primary_language\":\"makefile\"},\"quality_band\":\"10\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":3407,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":699},\"commit_oid\":\"39ee2e1f98dc4868f8ab770e27c04c3fb26e2822\",\"identity\":{\"author_email\":\"vincent@systemli.org\",\"author_name\":\"Nick Hainke\",\"authored_at\":\"2023-04-02T23:38:57+02:00\",\"commit_oid\":\"39ee2e1f98dc4868f8ab770e27c04c3fb26e2822\",\"commits_ago_from_head\":1970,\"committed_at\":\"2023-04-18T23:59:16+08:00\",\"committer_email\":\"42570690+AmadeusGhost@users.noreply.github.com\",\"committer_name\":\"AmadeusGhost\",\"parent_oid\":\"4bba40608bd2b9c05ee33cff62277a4efe7ebda7\",\"tree_oid\":\"e2e775d466074116f2d494a38c7503c80a010868\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":7873,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"433524bdafcec7744fd8b3a6b4d9ba8a4ed1a29f\",\"oldest_commit\":\"97a4ffcc125611dd5f307d54570373832a73e62d\"},\"recorded_head_commit\":\"433524bdafcec7744fd8b3a6b4d9ba8a4ed1a29f\",\"repository_id\":\"github.com/coolsnowwolf/lede\",\"snapshot_check\":\"repo_moved_ahead_of_recorded_head\"},\"repository_id\":\"github.com/coolsnowwolf/lede\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":89355,\"manifest_sha256\":null,\"split\":\"11-of-16\"}},\"parents\":[\"commit:github.com/coolsnowwolf/lede@39ee2e1f98dc4868f8ab770e27c04c3fb26e2822__download_changed_file_contents_1c999c4693bd__render_commit_patches_247cd0f5e36b\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16091,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/adafruit/esp-idf@4bfd180a943970736d7dd447b41f143e5bdfcf7c"},"text":{"kind":"string","value":"<|commit_message|>\nfix(i2c): only call esp_pm APIs when CONFIG_PM_ENABLE is enabled\n\n<|file_patch|>components/esp_driver_i2c/i2c_common.c\ndiff --git a/components/esp_driver_i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c\nindex 9c8b06288dd6c61e12a9e4641a83cd10afd23822..c8da8c554de4ce1148b974f88ed43d230d7e800d 100644\n--- a/components/esp_driver_i2c/i2c_common.c\n+++ b/components/esp_driver_i2c/i2c_common.c\n@@ -211,9 +211,11 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)\n if (i2c_bus->intr_handle) {\n ESP_RETURN_ON_ERROR(esp_intr_free(i2c_bus->intr_handle), TAG, \"delete interrupt service failed\");\n }\n+#if CONFIG_PM_ENABLE\n if (i2c_bus->pm_lock) {\n ESP_RETURN_ON_ERROR(esp_pm_lock_delete(i2c_bus->pm_lock), TAG, \"delete pm_lock failed\");\n }\n+#endif\n // Disable I2C module\n if (!i2c_bus->is_lp_i2c) {\n I2C_RCC_ATOMIC() {\n@@ -306,8 +308,7 @@ esp_err_t i2c_select_periph_clock(i2c_bus_handle_t handle, soc_module_clk_t clk_\n }\n \n if (need_pm_lock) {\n- sprintf(handle->pm_lock_name, \"I2C_%d\", handle->port_num); // e.g. PORT_0\n- ret = esp_pm_lock_create(pm_lock_type, 0, handle->pm_lock_name, &handle->pm_lock);\n+ ret = esp_pm_lock_create(pm_lock_type, 0, i2c_periph_signal[handle->port_num].module_name, &handle->pm_lock);\n ESP_RETURN_ON_ERROR(ret, TAG, \"create pm lock failed\");\n }\n #endif // CONFIG_PM_ENABLE\n\n<|file_patch|>components/esp_driver_i2c/i2c_private.h\ndiff --git a/components/esp_driver_i2c/i2c_private.h b/components/esp_driver_i2c/i2c_private.h\nindex 5a043b263ae7720595736a11c8d6356f8cd1875a..bc8b6aef3867e7a4107b8bf81797bf093b7ca659 100644\n--- a/components/esp_driver_i2c/i2c_private.h\n+++ b/components/esp_driver_i2c/i2c_private.h\n@@ -66,7 +66,6 @@ extern \"C\" {\n \n #define I2C_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED\n \n-#define I2C_PM_LOCK_NAME_LEN_MAX 16\n #define I2C_STATIC_OPERATION_ARRAY_MAX SOC_I2C_CMD_REG_NUM\n \n #define I2C_TRANS_READ_COMMAND(ack_value) {.ack_val = (ack_value), .op_code = I2C_LL_CMD_READ}\n@@ -116,9 +115,8 @@ struct i2c_bus_t {\n int scl_num; // SCL pin number\n bool pull_up_enable; // Enable pull-ups\n intr_handle_t intr_handle; // I2C interrupt handle\n- esp_pm_lock_handle_t pm_lock; // power manage lock\n #if CONFIG_PM_ENABLE\n- char pm_lock_name[I2C_PM_LOCK_NAME_LEN_MAX]; // pm lock name\n+ esp_pm_lock_handle_t pm_lock; // power manage lock\n #endif\n i2c_bus_mode_t bus_mode; // I2C bus mode\n #if SOC_I2C_SUPPORT_SLEEP_RETENTION\n\n<|file_patch|>components/soc/esp32/i2c_periph.c\ndiff --git a/components/soc/esp32/i2c_periph.c b/components/soc/esp32/i2c_periph.c\nindex daecec7beec5988fb092b3381af2e95c0bf91324..4a440fca4df50e8772614265e438454ab466afb2 100644\n--- a/components/soc/esp32/i2c_periph.c\n+++ b/components/soc/esp32/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -19,6 +20,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2CEXT1_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT1_SDA_IN_IDX,\n .scl_out_sig = I2CEXT1_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32c2/i2c_periph.c\ndiff --git a/components/soc/esp32c2/i2c_periph.c b/components/soc/esp32c2/i2c_periph.c\nindex 00872524784df53c5300b5c6f46a7964d59e7d27..4df019865be53de89704ca6d589af66b2ed85382 100644\n--- a/components/soc/esp32c2/i2c_periph.c\n+++ b/components/soc/esp32c2/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32c3/i2c_periph.c\ndiff --git a/components/soc/esp32c3/i2c_periph.c b/components/soc/esp32c3/i2c_periph.c\nindex 2402f6aeaed41adc9ec6566b6d9550fb95d03951..6f18557a3ac6f99eea14b45fe7011971345117f6 100644\n--- a/components/soc/esp32c3/i2c_periph.c\n+++ b/components/soc/esp32c3/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32c5/i2c_periph.c\ndiff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c\nindex 6ae52cb0cfab8b25937aa8fee6b2c12f20139497..4436a046c5a6e79ae27d3031ed99cce871676a8a 100644\n--- a/components/soc/esp32c5/i2c_periph.c\n+++ b/components/soc/esp32c5/i2c_periph.c\n@@ -14,6 +14,7 @@ static_assert(SOC_I2C_NUM == (SOC_HP_I2C_NUM + SOC_LP_I2C_NUM));\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n /* I2C_NUM_0*/\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -22,6 +23,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n },\n /* LP_I2C_NUM_0*/\n {\n+ .module_name = \"LP_I2C0\",\n .sda_out_sig = 0,\n .sda_in_sig = 0,\n .scl_out_sig = 0,\n\n<|file_patch|>components/soc/esp32c6/i2c_periph.c\ndiff --git a/components/soc/esp32c6/i2c_periph.c b/components/soc/esp32c6/i2c_periph.c\nindex 96e46a6529ddbbb52c5b2ced5278e86bf70d9045..2d03a38dbe7c38b2fd2f391afc93bf1ebba8775c 100644\n--- a/components/soc/esp32c6/i2c_periph.c\n+++ b/components/soc/esp32c6/i2c_periph.c\n@@ -16,6 +16,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -23,6 +24,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"LP_I2C0\",\n .sda_out_sig = 0,\n .sda_in_sig = 0,\n .scl_out_sig = 0,\n\n<|file_patch|>components/soc/esp32c61/i2c_periph.c\ndiff --git a/components/soc/esp32c61/i2c_periph.c b/components/soc/esp32c61/i2c_periph.c\nindex 960fb131a5e59a8724980bfe9b4e27763209efde..63369e2810aff20db9c6f5e9b86f496150d56855 100644\n--- a/components/soc/esp32c61/i2c_periph.c\n+++ b/components/soc/esp32c61/i2c_periph.c\n@@ -13,6 +13,7 @@\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n /* I2C_NUM_0*/\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32h2/i2c_periph.c\ndiff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c\nindex ffda3bf9f88ea60c8b923b158b0d3be2fad0cf12..7c629655b5a0dbda4af4e524a67c2a13b4c5253b 100644\n--- a/components/soc/esp32h2/i2c_periph.c\n+++ b/components/soc/esp32h2/i2c_periph.c\n@@ -14,6 +14,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -21,6 +22,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2CEXT1_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT1_SDA_IN_IDX,\n .scl_out_sig = I2CEXT1_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32h21/i2c_periph.c\ndiff --git a/components/soc/esp32h21/i2c_periph.c b/components/soc/esp32h21/i2c_periph.c\nindex ab14022496358654b608ccbf9de21cc521e13c5e..5633761438d986edcf18ad6bdfe3a12e9896c326 100644\n--- a/components/soc/esp32h21/i2c_periph.c\n+++ b/components/soc/esp32h21/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -19,6 +20,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2CEXT1_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT1_SDA_IN_IDX,\n .scl_out_sig = I2CEXT1_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32p4/i2c_periph.c\ndiff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c\nindex b895c9f3622476ea6e319965862cac17428fe0cf..6bf7b354821e35fbc100fda07a8d85bba8763d1c 100644\n--- a/components/soc/esp32p4/i2c_periph.c\n+++ b/components/soc/esp32p4/i2c_periph.c\n@@ -13,6 +13,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2C0_SDA_PAD_OUT_IDX,\n .sda_in_sig = I2C0_SDA_PAD_IN_IDX,\n .scl_out_sig = I2C0_SCL_PAD_OUT_IDX,\n@@ -20,6 +21,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2C1_SDA_PAD_OUT_IDX,\n .sda_in_sig = I2C1_SDA_PAD_IN_IDX,\n .scl_out_sig = I2C1_SCL_PAD_OUT_IDX,\n@@ -27,6 +29,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C1_INTR_SOURCE,\n },\n {\n+ .module_name = \"LP_I2C0\",\n .sda_out_sig = LP_I2C_SDA_PAD_OUT_IDX,\n .sda_in_sig = LP_I2C_SDA_PAD_IN_IDX,\n .scl_out_sig = LP_I2C_SCL_PAD_OUT_IDX,\n\n<|file_patch|>components/soc/esp32s2/i2c_periph.c\ndiff --git a/components/soc/esp32s2/i2c_periph.c b/components/soc/esp32s2/i2c_periph.c\nindex daecec7beec5988fb092b3381af2e95c0bf91324..4a440fca4df50e8772614265e438454ab466afb2 100644\n--- a/components/soc/esp32s2/i2c_periph.c\n+++ b/components/soc/esp32s2/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -19,6 +20,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2CEXT1_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT1_SDA_IN_IDX,\n .scl_out_sig = I2CEXT1_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/esp32s3/i2c_periph.c\ndiff --git a/components/soc/esp32s3/i2c_periph.c b/components/soc/esp32s3/i2c_periph.c\nindex daecec7beec5988fb092b3381af2e95c0bf91324..4a440fca4df50e8772614265e438454ab466afb2 100644\n--- a/components/soc/esp32s3/i2c_periph.c\n+++ b/components/soc/esp32s3/i2c_periph.c\n@@ -12,6 +12,7 @@\n */\n const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n {\n+ .module_name = \"I2C0\",\n .sda_out_sig = I2CEXT0_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT0_SDA_IN_IDX,\n .scl_out_sig = I2CEXT0_SCL_OUT_IDX,\n@@ -19,6 +20,7 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {\n .irq = ETS_I2C_EXT0_INTR_SOURCE,\n },\n {\n+ .module_name = \"I2C1\",\n .sda_out_sig = I2CEXT1_SDA_OUT_IDX,\n .sda_in_sig = I2CEXT1_SDA_IN_IDX,\n .scl_out_sig = I2CEXT1_SCL_OUT_IDX,\n\n<|file_patch|>components/soc/include/soc/i2c_periph.h\ndiff --git a/components/soc/include/soc/i2c_periph.h b/components/soc/include/soc/i2c_periph.h\nindex c1fbb0fbc8dc320cab0058c65213abe80724d0d5..23ceea1d1c2166cb2857c6453ce17dfc3487edda 100644\n--- a/components/soc/include/soc/i2c_periph.h\n+++ b/components/soc/include/soc/i2c_periph.h\n@@ -20,6 +20,7 @@ extern \"C\" {\n #endif\n \n typedef struct {\n+ const char *module_name;\n const uint8_t sda_out_sig;\n const uint8_t sda_in_sig;\n const uint8_t scl_out_sig;\n\n"},"target_character_start":{"kind":"number","value":85,"string":"85"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-02"},"utf8_bytes":{"kind":"number","value":12089,"string":"12,089"},"document_order_key":{"kind":"number","value":2952475284116504000,"string":"2,952,475,284,116,504,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/adafruit/esp-idf"},"quality_band":{"kind":"string","value":"02"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"c"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/adafruit/esp-idf\",\"commit_oid\":\"4bfd180a943970736d7dd447b41f143e5bdfcf7c\",\"commits_ago_from_head\":5428,\"content_sha256\":\"bbf93ed487574e4463ad8444c45c70abfaf53bcee898b0f42e420e66733c6a03\",\"manifest_sha256\":null,\"parent_oid\":\"6397820d0b2c67d34aed11bd1b4a2a8627942cd8\",\"repository_id\":\"github.com/adafruit/esp-idf\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"02\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"junk_file_receipts_alongside_kept_files\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":2},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":9,\"scope\":\"i2c\",\"subject_length\":54,\"trailer_names\":[],\"type\":\"fix\"},\"patch_statistics\":{\"added_lines\":25,\"context_bytes\":52918,\"deleted_lines\":5,\"files_changed\":14,\"hunk_count\":25,\"patch_bytes\":11279,\"patch_sha256\":\"e70b863033f8aa24f7e25a834b79c3fc63d3740b0c28a01fc84636e89c95379d\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"c\",\"path\":\"components/esp_driver_i2c/i2c_common.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/esp_driver_i2c/i2c_private.h\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32c2/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32c3/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32c5/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32c6/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32c61/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32h2/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32h21/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32p4/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32s2/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/esp32s3/i2c_periph.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"components/soc/include/soc/i2c_periph.h\",\"purpose\":\"source\"}],\"primary_language\":\"c\"},\"quality_band\":\"02\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":52918,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":15,\"files_kept\":14,\"patch_bytes\":11279},\"commit_oid\":\"4bfd180a943970736d7dd447b41f143e5bdfcf7c\",\"identity\":{\"author_email\":\"chenjichang@espressif.com\",\"author_name\":\"Chen Jichang\",\"authored_at\":\"2025-05-16T18:24:04+08:00\",\"commit_oid\":\"4bfd180a943970736d7dd447b41f143e5bdfcf7c\",\"commits_ago_from_head\":5428,\"committed_at\":\"2025-05-22T17:27:18+08:00\",\"committer_email\":\"chenjichang@espressif.com\",\"committer_name\":\"Chen Jichang\",\"parent_oid\":\"6397820d0b2c67d34aed11bd1b4a2a8627942cd8\",\"tree_oid\":\"0b2be1bd9a572fb4facf916cf3e585ee06a0277a\"},\"pipeline_log\":[{\"dropped\":[{\"path\":\"components/esp_driver_i2c/i2c_master.c\",\"reason\":\"file_too_long\"}],\"step\":\"drop_changed_files_over_maximum_character_count\"}],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"circuitpython-v6.0.1\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"2b900d1222cfce5dfa340ed99375af69ec1ee192\",\"oldest_commit\":\"39872a55753f5b512670af90e7d5d029e4984ccd\"},\"recorded_head_commit\":\"2b900d1222cfce5dfa340ed99375af69ec1ee192\",\"repository_id\":\"github.com/adafruit/esp-idf\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/adafruit/esp-idf\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":8916,\"manifest_sha256\":null,\"split\":\"04-of-16\"}},\"parents\":[\"commit:github.com/adafruit/esp-idf@4bfd180a943970736d7dd447b41f143e5bdfcf7c__download_changed_file_contents_c2e3e2197f0d__drop_changed_files_over_maximum_character_count_87e7a3e759eb__render_commit_patches_cdae7b7b122d\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16092,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/buildkite/gha-to-buildkite@791384c5ce129929be4b5baea7ddd3905d1ec24c"},"text":{"kind":"string","value":"<|commit_message|>\nanthropic force tool (#681)\n\n\n<|file_patch|>instructor/process_response.py\ndiff --git a/instructor/process_response.py b/instructor/process_response.py\nindex 16c24ad940b6264f631883809aa1de1e255459e9..e7c6e1da3aa6e21571feb524e07f243a03958138 100644\n--- a/instructor/process_response.py\n+++ b/instructor/process_response.py\n@@ -280,6 +280,7 @@ def handle_response_model(\n elif mode == Mode.ANTHROPIC_TOOLS:\n tool_descriptions = response_model.anthropic_schema\n new_kwargs[\"tools\"] = [tool_descriptions]\n+ new_kwargs[\"tool_choice\"] = {\"type\": \"tool\", \"name\": response_model.__name__}\n \n system_messages = [\n m[\"content\"] for m in new_kwargs[\"messages\"] if m[\"role\"] == \"system\"\n\n<|file_patch|>pyproject.toml\ndiff --git a/pyproject.toml b/pyproject.toml\nindex 64fd29f9ed09b7b678e18ea16fa73ae05f35612f..9345602aff0d9e32f6e50ea7e520101667e55a70 100644\n--- a/pyproject.toml\n+++ b/pyproject.toml\n@@ -27,7 +27,7 @@ pandas = { version = \"^2.2.0\", optional = true }\n tabulate = { version = \"^0.9.0\", optional = true }\n pydantic_extra_types = { version = \"^2.6.0\", optional = true }\n litellm = { version = \"^1.35.31\", optional = true }\n-anthropic = { version = \"^0.23.1\", optional = true }\n+anthropic = { version = \"^0.26.0\", optional = true }\n xmltodict = { version = \"^0.13.0\", optional = true }\n groq = { version = \"^0.4.2\", optional = true }\n cohere = { version = \"^5.1.8\", optional = true }\n@@ -62,7 +62,7 @@ mkdocs-minify-plugin = \"^0.8.0\"\n mkdocs-redirects = \"^1.2.1\"\n \n [tool.poetry.group.anthropic.dependencies]\n-anthropic = \"^0.23.1\"\n+anthropic = \"^0.26.0\"\n \n [tool.poetry.group.test-docs.dependencies]\n fastapi = \"^0.109.2\"\n@@ -72,7 +72,7 @@ pandas = \"^2.2.0\"\n tabulate = \"^0.9.0\"\n pydantic_extra_types = \"^2.6.0\"\n litellm = \"^1.35.31\"\n-anthropic = \"^0.23.1\"\n+anthropic = \"^0.26.0\"\n xmltodict = \"^0.13.0\"\n groq = \"^0.4.2\"\n phonenumbers = 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line number reporting optional via config.h\n\n<|file_patch|>config.h\ndiff --git a/config.h b/config.h\nindex dbf37e31dcc00c18a07d5c4e9d83ab83a25e9673..ddaddcbab7b30f864af9db8b47e8b043e3e86f52 100644\n--- a/config.h\n+++ b/config.h\n@@ -28,6 +28,10 @@\n #ifndef config_h\n #define config_h\n \n+// Allows GRBL to tranck and report gcode line numbers. Enabling this means that the planning buffer\n+// goes from 18 or 16 to make room for the additional line number data in the plan_block_t struct\n+#define USE_LINE_NUMBERS\n+\n // Default settings. Used when resetting EEPROM. Change to desired name in defaults.h\n #define DEFAULTS_SHERLINE_5400\n \n\n<|file_patch|>planner.c\ndiff --git a/planner.c b/planner.c\nindex f167522344783b9c2306ad0530b14e376b12b2e7..dfc56dba60bba1266c3a3ee375272d566c625370 100644\n--- a/planner.c\n+++ b/planner.c\n@@ -280,8 +280,9 @@ void plan_buffer_line(float *target, float feed_rate, uint8_t invert_feed_rate,\n block->millimeters = 0;\n block->direction_bits = 0;\n block->acceleration = SOME_LARGE_VALUE; // Scaled down to maximum acceleration later\n+#ifdef USE_LINE_NUMBERS\n block->line_number = line_number;\n-\n+#endif\n // Compute and store initial move distance data.\n // TODO: After this for-loop, we don't touch the stepper algorithm data. Might be a good idea\n // to try to keep these types of things completely separate from the planner for portability.\n\n<|file_patch|>planner.h\ndiff --git a/planner.h b/planner.h\nindex e7ae71660a7cf2c411c9179c9c01c9ca98b86106..7a255bed89cf8116a55078634317aff214947f45 100644\n--- a/planner.h\n+++ b/planner.h\n@@ -26,7 +26,11 @@\n \n // The number of linear motions that can be in the plan at any give time\n #ifndef BLOCK_BUFFER_SIZE\n- #define BLOCK_BUFFER_SIZE 16\n+ #ifdef USE_LINE_NUMBERS\n+ #define BLOCK_BUFFER_SIZE 16\n+ #else\n+ #define BLOCK_BUFFER_SIZE 18\n+ #endif\n #endif\n \n // This struct stores a linear movement of a g-code block motion with its critical \"nominal\" values\n@@ -47,7 +51,9 @@ typedef struct {\n float acceleration; // Axis-limit adjusted line acceleration in (mm/min^2)\n float millimeters; // The remaining distance for this block to be executed in (mm)\n // uint8_t max_override; // Maximum override value based on axis speed limits\n+#ifdef USE_LINE_NUMBERS\n uint32_t line_number;\n+#endif\n } plan_block_t;\n \n \n\n<|file_patch|>report.c\ndiff --git a/report.c b/report.c\nindex d62ed49e75a92985aeaf4ade2ff18c430c2fd1e8..5b97dc16b01954d0882962628d8d329b2683dbcf 100644\n--- a/report.c\n+++ b/report.c\n@@ -350,6 +350,7 @@ void report_realtime_status()\n if (i < (N_AXIS-1)) { printPgmString(PSTR(\",\")); }\n }\n \n+#ifdef USE_LINE_NUMBERS\n // Report current line number\n printPgmString(PSTR(\",\"));\n printPgmString(PSTR(\"Ln:\")); \n@@ -359,7 +360,7 @@ void report_realtime_status()\n ln = pb->line_number;\n } \n printInteger(ln);\n-\n+#endif\n \n printPgmString(PSTR(\">\\r\\n\"));\n }\n\n"},"target_character_start":{"kind":"number","value":69,"string":"69"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-01"},"utf8_bytes":{"kind":"number","value":2946,"string":"2,946"},"document_order_key":{"kind":"number","value":2952512721233691600,"string":"2,952,512,721,233,691,600"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/gnea/grbl"},"quality_band":{"kind":"string","value":"01"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":5,"string":"5"},"primary_language":{"kind":"string","value":"c"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/gnea/grbl\",\"commit_oid\":\"cd71a90ce8a770e0030ed6c9bac805b89724e275\",\"commits_ago_from_head\":317,\"content_sha256\":\"b0f79f3a69a8cb3dc7490f5165d599a99568d3a3f574862f7f45ea480e092fc1\",\"manifest_sha256\":null,\"parent_oid\":\"6fdb35a7dad3e4ef027260aa30aef1fb0e55c554\",\"repository_id\":\"github.com/gnea/grbl\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"01\",\"commit_quality_score\":{\"commit_score\":5,\"deductions\":[],\"repo_score\":5,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":2,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":1},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":7,\"scope\":null,\"subject_length\":48,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":15,\"context_bytes\":57788,\"deleted_lines\":3,\"files_changed\":4,\"hunk_count\":6,\"patch_bytes\":2779,\"patch_sha256\":\"e3a17da6ca2555d79fde5552049392b97d9bd9b9bd093903c0c20144017775bd\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"c\",\"path\":\"config.h\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"planner.c\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"planner.h\",\"purpose\":\"source\"},{\"language\":\"c\",\"path\":\"report.c\",\"purpose\":\"source\"}],\"primary_language\":\"c\"},\"quality_band\":\"01\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":57788,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":4,\"files_kept\":4,\"patch_bytes\":2779},\"commit_oid\":\"cd71a90ce8a770e0030ed6c9bac805b89724e275\",\"identity\":{\"author_email\":\"robert@robgrz.com\",\"author_name\":\"Robert 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tag patterns again\n\n<|file_patch|>daemon/images.go\ndiff --git a/daemon/images.go b/daemon/images.go\nindex acc8c26c4d2c0c24a5ad863456e0f5cacd3eed81..7d877ed4c4b3766de7c9dc115b575a22b7f49033 100644\n--- a/daemon/images.go\n+++ b/daemon/images.go\n@@ -2,6 +2,7 @@ package daemon\n \n import (\n \t\"fmt\"\n+\t\"strings\"\n \n \t\"github.com/go-kit/kit/log\"\n \t\"github.com/pkg/errors\"\n@@ -25,24 +26,18 @@ func (d *Daemon) PollImages(logger log.Logger) {\n \t\tlogger.Log(\"msg\", \"no automated services\")\n \t\treturn\n \t}\n-\tlogger.Log(\"candidates\", fmt.Sprintf(\"%#v\", candidateServices))\n-\n \t// Find images to check\n \tservices, err := d.Cluster.SomeServices(candidateServices.ToSlice())\n \tif err != nil {\n \t\tlogger.Log(\"error\", errors.Wrap(err, \"checking services for new images\"))\n \t\treturn\n \t}\n-\tlogger.Log(\"services\", fmt.Sprintf(\"%#v\", services))\n-\n \t// Check the latest available image(s) for each service\n \timageMap, err := release.CollectAvailableImages(d.Registry, services)\n \tif err != nil {\n \t\tlogger.Log(\"error\", errors.Wrap(err, \"fetching image updates\"))\n \t\treturn\n \t}\n-\tlogger.Log(\"imageMap\", fmt.Sprintf(\"%#v\", imageMap))\n-\n \t// Update image for each container\n \tfor _, service := range services {\n \t\tfor _, container := range service.ContainersOrNil() {\n@@ -54,8 +49,7 @@ func (d *Daemon) PollImages(logger log.Logger) {\n \t\t\t\tcontinue\n \t\t\t}\n \n-\t\t\tpattern := \"*\"\n-\n+\t\t\tpattern := getTagPattern(candidateServices, service.ID, container.Name, logger)\n \t\t\trepo := currentImageID.Repository()\n \t\t\tlogger.Log(\"repo\", repo, \"pattern\", pattern)\n \n@@ -68,6 +62,14 @@ func (d *Daemon) PollImages(logger log.Logger) {\n \t}\n }\n \n+func getTagPattern(services policy.ServiceMap, service flux.ServiceID, container string, logger log.Logger) string {\n+\tpolicies := services[service]\n+\tif pattern, ok := policies.Get(policy.Policy(\"tag.\" + container)); ok {\n+\t\treturn strings.TrimPrefix(pattern, \"glob:\")\n+\t}\n+\treturn \"*\"\n+}\n+\n func (d *Daemon) unlockedAutomatedServices() (policy.ServiceMap, error) {\n \tautomatedServices, err := d.Manifests.ServicesWithPolicy(d.Checkout.ManifestDir(), policy.Automated)\n \tif err != nil {\n\n<|file_patch|>policy/policy.go\ndiff --git a/policy/policy.go b/policy/policy.go\nindex 94a08a5962d4f55001e47dc7b61583c3f18997fe..9b4e4cc41d08d2610e7e3d5f4b4932a839f54495 100644\n--- a/policy/policy.go\n+++ b/policy/policy.go\n@@ -78,6 +78,11 @@ func (s Set) Contains(needle Policy) bool {\n \treturn false\n }\n \n+func (s Set) Get(p Policy) (string, bool) {\n+\tv, ok := s[p]\n+\treturn v, ok\n+}\n+\n type ServiceMap map[flux.ServiceID]Set\n \n func (s ServiceMap) ToSlice() []flux.ServiceID {\n\n"},"target_character_start":{"kind":"number","value":48,"string":"48"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-05"},"utf8_bytes":{"kind":"number","value":2599,"string":"2,599"},"document_order_key":{"kind":"number","value":2952871545106236400,"string":"2,952,871,545,106,236,400"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/babylonhealth/flux"},"quality_band":{"kind":"string","value":"05"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":3,"string":"3"},"primary_language":{"kind":"string","value":"go"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/babylonhealth/flux\",\"commit_oid\":\"47dade92a8d7981f7a7e07413471c9563ebfdf72\",\"commits_ago_from_head\":2072,\"content_sha256\":\"f9cda3545c5f7466de6c419685607bff154e2d8c1cd98c53208a229432763399\",\"manifest_sha256\":null,\"parent_oid\":\"b0c2edcf375944f7ed6c58cc2d287c39c5abc26a\",\"repository_id\":\"github.com/babylonhealth/flux\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"05\",\"commit_quality_score\":{\"commit_score\":3,\"deductions\":[],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":5},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":false,\"issue_references\":[],\"message_words\":4,\"scope\":null,\"subject_length\":27,\"trailer_names\":[],\"type\":null},\"patch_statistics\":{\"added_lines\":15,\"context_bytes\":4823,\"deleted_lines\":8,\"files_changed\":2,\"hunk_count\":5,\"patch_bytes\":2487,\"patch_sha256\":\"90461cadfea66cc34e6619aa0b795998abe7b6464300e7e3d3eb7b404c720e38\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"go\",\"path\":\"daemon/images.go\",\"purpose\":\"source\"},{\"language\":\"go\",\"path\":\"policy/policy.go\",\"purpose\":\"source\"}],\"primary_language\":\"go\"},\"quality_band\":\"05\",\"tests_touched\":{\"source_files_also_touched\":true,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":4823,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":2,\"files_kept\":2,\"patch_bytes\":2487},\"commit_oid\":\"47dade92a8d7981f7a7e07413471c9563ebfdf72\",\"identity\":{\"author_email\":\"sam@weave.works\",\"author_name\":\"Sam Broughton\",\"authored_at\":\"2017-06-14T11:41:46+01:00\",\"commit_oid\":\"47dade92a8d7981f7a7e07413471c9563ebfdf72\",\"commits_ago_from_head\":2072,\"committed_at\":\"2017-06-28T11:48:26+01:00\",\"committer_email\":\"sam@weave.works\",\"committer_name\":\"Sam Broughton\",\"parent_oid\":\"b0c2edcf375944f7ed6c58cc2d287c39c5abc26a\",\"tree_oid\":\"eb9d239234131b330e05f4931324363da9053d50\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":3189,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"8f588b0318d4ecabdd635dc4e79e7cc42128e05e\",\"oldest_commit\":\"a6fbd68a967846f8c8b62ed0ae3482af1120b58c\"},\"recorded_head_commit\":\"8f588b0318d4ecabdd635dc4e79e7cc42128e05e\",\"repository_id\":\"github.com/babylonhealth/flux\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/babylonhealth/flux\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":60379,\"manifest_sha256\":null,\"split\":\"11-of-16\"}},\"parents\":[\"commit:github.com/babylonhealth/flux@47dade92a8d7981f7a7e07413471c9563ebfdf72__download_changed_file_contents_d134711828af__render_commit_patches_11aa7ce464e0\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16095,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/buglabs/dragonfly@503ede30dfaaa7e2467e10d8e7c1ecce520f3af1"},"text":{"kind":"string","value":"<|commit_message|>\nupdated for new pages\n\ngit-svn-id: svn://bugcamp.net/dragonfly/trunk/com.buglabs.dragonfly.help@6843 35ad6e01-222d-0410-b96a-b41bba574936\n\n<|file_patch|>build.properties\ndiff --git a/build.properties b/build.properties\nindex 50a980b6a3a70f0f8b71b9b749a04de646499861..b9baf5a37da9990ba8ab769b2fa6d0e12c434220 100644\n--- a/build.properties\n+++ b/build.properties\n@@ -10,7 +10,17 @@ bin.includes = plugin.xml,\\\n toc.xml,\\\n tocAPI.xml,\\\n tocGettingStarted.xml,\\\n- toctasks.xml\n+ toctasks.xml,\\\n+ tocAnatomyOfBUGApplication.xml,\\\n+ tocCallWebServicesApp.xml,\\\n+ tocCreateBUGProject.xml,\\\n+ tocDebugAnApp.xml,\\\n+ tocDownloadAppToBUG.xml,\\\n+ tocInteractingWithBUGnetView.xml,\\\n+ tocInteractingWithMyBUGsView.xml,\\\n+ tocLaunchConfiguration.xml,\\\n+ tocUploadApplication.xml,\\\n+ tocUsingVirtualBug.xml\n src.includes = src/,\\\n toc.xml,\\\n tocAPI.xml,\\\n@@ -18,6 +28,15 @@ src.includes = src/,\\\n toctasks.xml,\\\n plugin.xml,\\\n html/,\\\n- book.css\n-bin.excludes = html/tipsAndTricks/\n-src.excludes = html/tipsAndTricks/\n+ book.css,\\\n+ tocAnatomyOfBUGApplication.xml,\\\n+ tocCallWebServicesApp.xml,\\\n+ tocCreateBUGProject.xml,\\\n+ tocDebugAnApp.xml,\\\n+ tocDownloadAppToBUG.xml,\\\n+ tocInteractingWithBUGnetView.xml,\\\n+ tocInteractingWithMyBUGsView.xml,\\\n+ tocLaunchConfiguration.xml,\\\n+ tocUploadApplication.xml,\\\n+ tocUsingVirtualBug.xml,\\\n+ build.properties\n\n"},"target_character_start":{"kind":"number","value":158,"string":"158"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-06"},"utf8_bytes":{"kind":"number","value":1829,"string":"1,829"},"document_order_key":{"kind":"number","value":2952956876604439600,"string":"2,952,956,876,604,439,600"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/buglabs/dragonfly"},"quality_band":{"kind":"string","value":"06"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"null"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/buglabs/dragonfly\",\"commit_oid\":\"503ede30dfaaa7e2467e10d8e7c1ecce520f3af1\",\"commits_ago_from_head\":715,\"content_sha256\":\"7e8184dd378d1acf9bfaddfd2aaa41b84bad763458e0fd1d372bbba075250be8\",\"manifest_sha256\":null,\"parent_oid\":\"b8a489912c3103157ec6733c75191f4f52f85f24\",\"repository_id\":\"github.com/buglabs/dragonfly\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"06\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":6},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":7,\"scope\":null,\"subject_length\":21,\"trailer_names\":[\"git-svn-id\"],\"type\":null},\"patch_statistics\":{\"added_lines\":23,\"context_bytes\":620,\"deleted_lines\":4,\"files_changed\":1,\"hunk_count\":2,\"patch_bytes\":1639,\"patch_sha256\":\"442a729b196e091a18ea3318665fc130d9666f7f023a135423839371bf958348\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":null,\"path\":\"build.properties\",\"purpose\":\"other\"}],\"primary_language\":null},\"quality_band\":\"06\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":620,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":1639},\"commit_oid\":\"503ede30dfaaa7e2467e10d8e7c1ecce520f3af1\",\"identity\":{\"author_email\":\"akravets@35ad6e01-222d-0410-b96a-b41bba574936\",\"author_name\":\"akravets\",\"authored_at\":\"2008-11-04T17:12:42+00:00\",\"commit_oid\":\"503ede30dfaaa7e2467e10d8e7c1ecce520f3af1\",\"commits_ago_from_head\":715,\"committed_at\":\"2008-11-04T17:12:42+00:00\",\"committer_email\":\"akravets@35ad6e01-222d-0410-b96a-b41bba574936\",\"committer_name\":\"akravets\",\"parent_oid\":\"b8a489912c3103157ec6733c75191f4f52f85f24\",\"tree_oid\":\"38cdafb9d7c2293fc0ee3a2d4c2695c987489a35\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":1242,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"b9fea4b4b13e01bf68adea1e7bbc42e289711cee\",\"oldest_commit\":\"181d32ca07ed894b92881afd52df2faacd2d16b4\"},\"recorded_head_commit\":\"b9fea4b4b13e01bf68adea1e7bbc42e289711cee\",\"repository_id\":\"github.com/buglabs/dragonfly\",\"snapshot_check\":\"matches_recorded_head\"},\"repository_id\":\"github.com/buglabs/dragonfly\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":83005,\"manifest_sha256\":null,\"split\":\"13-of-16\"}},\"parents\":[\"commit:github.com/buglabs/dragonfly@503ede30dfaaa7e2467e10d8e7c1ecce520f3af1__download_changed_file_contents_5b892b457413__render_commit_patches_f874a252beeb\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16096,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/boinc/boinc@2767e686e635044d27e5e85bc989e5cc09b7f5b5"},"text":{"kind":"string","value":"<|commit_message|>\n[ci] update actions\n\nSigned-off-by: Vitalii Koshura <lestat.de.lionkur@gmail.com>\n\n<|file_patch|>.github/workflows/android.yml\ndiff --git a/.github/workflows/android.yml b/.github/workflows/android.yml\nindex a5100f8d9e481bc500b931737260ef034044c1ed..508e0e0e860d892336ee75a1fb8e467be01eff7f 100644\n--- a/.github/workflows/android.yml\n+++ b/.github/workflows/android.yml\n@@ -139,7 +139,7 @@ jobs:\n path: android/BOINC/app/src/main/assets/\n \n - name: Setup Java\n- uses: actions/setup-java@0f481fcb613427c0f801b606911222b5b6f3083a\n+ uses: actions/setup-java@03ad4de0992f5dab5e18fcb136590ce7c4a0ac95\n with:\n distribution: 'zulu'\n java-version: \"17\"\n\n"},"target_character_start":{"kind":"number","value":102,"string":"102"},"source_name":{"kind":"string","value":"code.commit.baseline"},"source_stratum":{"kind":"string","value":"band-06"},"utf8_bytes":{"kind":"number","value":723,"string":"723"},"document_order_key":{"kind":"number","value":2953556778622656000,"string":"2,953,556,778,622,656,000"},"health_band":{"kind":"null"},"has_tests":{"kind":"null"},"is_fork":{"kind":"null"},"repository_name":{"kind":"string","value":"github.com/boinc/boinc"},"quality_band":{"kind":"string","value":"06"},"tests_touched":{"kind":"bool","value":false,"string":"false"},"ai_authorship_signal":{"kind":"string","value":"no_named_signal_detected"},"commit_score":{"kind":"number","value":2,"string":"2"},"primary_language":{"kind":"string","value":"yaml"},"verification_state":{"kind":"string","value":"parent_reconstructed"},"provenance_json":{"kind":"string","value":"{\"clone_url\":\"https://github.com/boinc/boinc\",\"commit_oid\":\"2767e686e635044d27e5e85bc989e5cc09b7f5b5\",\"commits_ago_from_head\":46,\"content_sha256\":\"290f4939abd1e9321ff76a17c13f50eb3477ca5df199bd4dea7c482c6228beb8\",\"manifest_sha256\":null,\"parent_oid\":\"848ebeadb01511b9eb34eb60cb8faaa4a665a2d5\",\"repository_id\":\"github.com/boinc/boinc\",\"shape\":\"commit\"}"},"source_metadata_json":{"kind":"string","value":"{\"annotations\":{\"commit_quality_band\":\"06\",\"commit_quality_score\":{\"commit_score\":2,\"deductions\":[{\"points\":1,\"reason\":\"no_source_code_purpose\"}],\"repo_score\":3,\"repo_score_components\":{\"dependents_reach\":0,\"gitstar_rank_present\":0,\"gitstar_rank_top_1000\":0,\"route_family_breadth\":0,\"route_language_top10\":3},\"rubric_version\":2,\"tier\":6},\"conventional_commit_type\":{\"breaking\":false,\"has_body\":true,\"issue_references\":[],\"message_words\":7,\"scope\":null,\"subject_length\":19,\"trailer_names\":[\"Signed-off-by\"],\"type\":null},\"patch_statistics\":{\"added_lines\":1,\"context_bytes\":10004,\"deleted_lines\":1,\"files_changed\":1,\"hunk_count\":1,\"patch_bytes\":576,\"patch_sha256\":\"0723ace6f3e3c23d0ee9f573bacaa66e2ebdcccf5fb13a95f0b926d34ca10d08\"},\"possible_ai_authorship\":{\"matched\":[],\"pattern_version\":1,\"signal\":\"no_named_signal_detected\"},\"programming_languages\":{\"files\":[{\"language\":\"yaml\",\"path\":\".github/workflows/android.yml\",\"purpose\":\"config\"}],\"primary_language\":\"yaml\"},\"quality_band\":\"06\",\"tests_touched\":{\"source_files_also_touched\":false,\"test_files\":[],\"touched\":false},\"verification_state\":\"parent_reconstructed\"},\"meta\":{\"change_summary\":{\"before_state_bytes\":10004,\"coverage\":\"all_files_of_the_commit_seen\",\"files_in_original_commit\":1,\"files_kept\":1,\"patch_bytes\":576},\"commit_oid\":\"2767e686e635044d27e5e85bc989e5cc09b7f5b5\",\"identity\":{\"author_email\":\"lestat.de.lionkur@gmail.com\",\"author_name\":\"Vitalii Koshura\",\"authored_at\":\"2026-07-19T07:21:47+02:00\",\"commit_oid\":\"2767e686e635044d27e5e85bc989e5cc09b7f5b5\",\"commits_ago_from_head\":46,\"committed_at\":\"2026-07-19T07:21:47+02:00\",\"committer_email\":\"lestat.de.lionkur@gmail.com\",\"committer_name\":\"Vitalii Koshura\",\"parent_oid\":\"848ebeadb01511b9eb34eb60cb8faaa4a665a2d5\",\"tree_oid\":\"36f41716ea50c551d279dcb07d4a1e971836f7bf\"},\"pipeline_log\":[],\"proof\":{\"replay_audit\":{\"failed_paths\":[],\"outcome\":\"not_sampled\",\"sampled\":false},\"verification_state\":\"parent_reconstructed\"},\"repository\":{\"default_branch\":\"master\",\"history_collected\":{\"commits_read\":10000,\"commits_skipped_parent_beyond_cutoff\":null,\"merge_commits_skipped\":null,\"newest_commit\":\"d498cd24c27462786977947f9d0315663fe46be9\",\"oldest_commit\":\"c8ae1d8439790c58cb1a96fba1809046d3a75871\"},\"recorded_head_commit\":\"d498cd24c27462786977947f9d0315663fe46be9\",\"repository_id\":\"github.com/boinc/boinc\",\"snapshot_check\":\"repo_moved_ahead_of_recorded_head\"},\"repository_id\":\"github.com/boinc/boinc\",\"shape\":\"commit\",\"source\":{\"discovery_routes\":null,\"manifest_position\":77488,\"manifest_sha256\":null,\"split\":\"00-of-16\"}},\"parents\":[\"commit:github.com/boinc/boinc@2767e686e635044d27e5e85bc989e5cc09b7f5b5__download_changed_file_contents_6dcc0115c7f8__render_commit_patches_96ccfa79d19f\"],\"schema_version\":\"locus.item/v1\"}"}}},{"rowIdx":16097,"cells":{"document_id":{"kind":"string","value":"commit-doc:github.com/acquia/ceres@22278ffc0cd5e5a03a7baab8b4234084e5fc09a7"},"text":{"kind":"string","value":"<|commit_message|>\nAdd sphinx docstring processing\n\n<|file_patch|>.gitignore\ndiff --git a/.gitignore b/.gitignore\nindex 553bad4c0a60f6871e748b7670e3ef65c51b9981..cea07721d176c5bf62deb3a29e6a1b383bd10faa 100644\n--- a/.gitignore\n+++ b/.gitignore\n@@ -1,5 +1,6 @@\n MANIFEST\n build\n+docs/_build\n dist\n *.log\n *.pyc\n\n<|file_patch|>ceres.py\ndiff --git a/ceres.py b/ceres.py\nindex e736388a557cc28d134c1c17c1a87a33eb2c51ca..d46a020a501557c9dd0d696a18c4ec242946161e 100644\n--- a/ceres.py\n+++ b/ceres.py\n@@ -38,7 +38,15 @@ DEFAULT_SLICE_CACHING_BEHAVIOR = 'none'\n SLICE_PERMS = 0644\n DIR_PERMS = 0755\n \n+\n class CeresTree:\n+ \"\"\"Represents a tree of Ceres metrics contained within a single path on disk\n+ This is the primary Ceres API.\n+\n+ :param root: The directory root of the Ceres tree\n+\n+ See :func:`setDefaultSliceCachingBehavior` to adjust caching behavior\n+ \"\"\"\n def __init__(self, root):\n if isdir(root):\n self.root = abspath(root)\n@@ -52,6 +60,14 @@ class CeresTree:\n \n @classmethod\n def createTree(cls, root, **props):\n+ \"\"\"Create and returns a new Ceres tree with the given properties\n+\n+ :param root: The root directory of the new Ceres tree\n+ :keyword \\*\\*props: Arbitrary key-value properties to store as tree metadata\n+\n+ :returns: :class:`CeresTree`\n+ \"\"\"\n+\n ceresDir = join(root, '.ceres-tree')\n if not isdir(ceresDir):\n os.makedirs(ceresDir, DIR_PERMS)\n@@ -59,32 +75,47 @@ class CeresTree:\n for prop,value in props.items():\n propFile = join(ceresDir, prop)\n fh = open(propFile, 'w')\n- fh.write( str(value) )\n+ fh.write(str(value))\n fh.close()\n \n return cls(root)\n \n def walk(self, **kwargs):\n+ \"\"\"Iterate through the nodes contained in this :class:`CeresTree`\n+\n+ :keyword \\*\\*kwargs: Options to pass to `os.walk`\n+\n+ :returns: An iterator yielding :class:`CeresNode` objects\n+ \"\"\"\n for (fsPath, subdirs, filenames) in os.walk(self.root, **kwargs):\n if CeresNode.isNodeDir(fsPath):\n nodePath = self.getNodePath(fsPath)\n yield CeresNode(self, nodePath, fsPath)\n \n def getFilesystemPath(self, nodePath):\n- return join(self.root, nodePath.replace('.', '/'))\n+ \"\"\"Get the on-disk path of a Ceres node given a metric name\"\"\"\n+ return join(self.root, nodePath.replace('.', os.sep))\n \n def getNodePath(self, fsPath):\n+ \"\"\"Get the metric name of a Ceres node given the on-disk path\"\"\"\n fsPath = abspath(fsPath)\n if not fsPath.startswith(self.root):\n raise ValueError(\"path '%s' not beneath tree root '%s'\" % (fsPath, self.root))\n \n- nodePath = fsPath[len(self.root):].strip('/').replace('/', '.')\n+ nodePath = fsPath[len(self.root):].strip(os.sep).replace(os.sep, '.')\n return nodePath\n \n def hasNode(self, nodePath):\n+ \"\"\"Returns whether the Ceres tree contains the given metric\"\"\"\n return isdir(self.getFilesystemPath(nodePath))\n \n def getNode(self, nodePath):\n+ \"\"\"Returns a Ceres node given a metric name\n+\n+ :param nodePath: A metric name\n+\n+ :returns: :class:`CeresNode` or `None`\n+ \"\"\"\n if nodePath not in self.nodeCache:\n fsPath = self.getFilesystemPath(nodePath)\n if CeresNode.isNodeDir(fsPath):\n@@ -95,6 +126,15 @@ class CeresTree:\n return self.nodeCache[nodePath]\n \n def find(self, nodePattern, fromTime=None, untilTime=None):\n+ \"\"\"Find nodes which match a wildcard pattern, optionally filtering on\n+ a time range\n+\n+ :keyword nodePattern: A glob-style metric wildcard\n+ :keyword fromTime: Optional interval start time in unix-epoch.\n+ :keyword untilTime: Optional interval end time in unix-epoch.\n+\n+ :returns: An iterator yielding :class:`CeresNode` objects\n+ \"\"\"\n for fsPath in glob(self.getFilesystemPath(nodePattern)):\n if CeresNode.isNodeDir(fsPath):\n nodePath = self.getNodePath(fsPath)\n@@ -106,9 +146,19 @@ class CeresTree:\n yield node\n \n def createNode(self, nodePath, **properties):\n+ \"\"\"Creates a new metric given a new metric name and optional per-node metadata\n+ :keyword nodePath: The new metric name.\n+ :keyword \\*\\*properties: Arbitrary key-value properties to store as metric metadata.\n+\n+ :returns: :class:`CeresNode`\n+ \"\"\"\n return CeresNode.create(self, nodePath, **properties)\n \n def store(self, nodePath, datapoints):\n+ \"\"\"Store a list of datapoints associated with a metric\n+ :keyword nodePath: The metric name to write to\n+ :keyword datapoints: A list of datapoint tuples: (timestamp, value)\n+ \"\"\"\n node = self.getNode(nodePath)\n \n if node is None:\n@@ -117,6 +167,15 @@ class CeresTree:\n node.write(datapoints)\n \n def fetch(self, nodePath, fromTime, untilTime):\n+ \"\"\"Fetch data within a given interval from the given metric\n+\n+ :keyword nodePath: The metric name to fetch from\n+ :keyword fromTime: Requested interval start time in unix-epoch.\n+ :keyword untilTime: Requested interval end time in unix-epoch.\n+\n+ :returns: :class:`TimeSeriesData`\n+ :raises: :class:`NodeNotFound`, :class:`InvalidRequest`, :class:`NoData`\n+ \"\"\"\n node = self.getNode(nodePath)\n \n if not node:\n\n<|file_patch|>docs/Makefile\ndiff --git a/docs/Makefile b/docs/Makefile\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d6fd8ac8dd6afb6299a3cb28327624149a2dde2b\n--- /dev/null\n+++ b/docs/Makefile\n@@ -0,0 +1,153 @@\n+# Makefile for Sphinx documentation\n+#\n+\n+# You can set these variables from the command line.\n+SPHINXOPTS =\n+SPHINXBUILD = sphinx-build\n+PAPER =\n+BUILDDIR = _build\n+\n+# Internal variables.\n+PAPEROPT_a4 = -D latex_paper_size=a4\n+PAPEROPT_letter = -D latex_paper_size=letter\n+ALLSPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .\n+# the i18n builder cannot share the environment and doctrees with the others\n+I18NSPHINXOPTS = $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) .\n+\n+.PHONY: help clean html dirhtml singlehtml pickle json htmlhelp qthelp devhelp epub latex latexpdf text man changes linkcheck doctest gettext\n+\n+help:\n+\t@echo \"Please use \\`make <target>' where <target> is one of\"\n+\t@echo \" html to make standalone HTML files\"\n+\t@echo \" dirhtml to make HTML files named index.html in directories\"\n+\t@echo \" singlehtml to make a single large HTML file\"\n+\t@echo \" pickle to make pickle files\"\n+\t@echo \" json to make JSON files\"\n+\t@echo \" htmlhelp to make HTML files and a HTML help project\"\n+\t@echo \" qthelp to make HTML files and a qthelp project\"\n+\t@echo \" devhelp to make HTML files and a Devhelp project\"\n+\t@echo \" epub to make an epub\"\n+\t@echo \" latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter\"\n+\t@echo \" latexpdf to make LaTeX files and run them through pdflatex\"\n+\t@echo \" text to make text files\"\n+\t@echo \" man to make manual pages\"\n+\t@echo \" texinfo to make Texinfo files\"\n+\t@echo \" info to make Texinfo files and run them through makeinfo\"\n+\t@echo \" gettext to make PO message catalogs\"\n+\t@echo \" changes to make an overview of all changed/added/deprecated items\"\n+\t@echo \" linkcheck to check all external links for integrity\"\n+\t@echo \" doctest to run all doctests embedded in the documentation (if enabled)\"\n+\n+clean:\n+\t-rm -rf $(BUILDDIR)/*\n+\n+html:\n+\t$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html\n+\t@echo\n+\t@echo \"Build finished. The HTML pages are in $(BUILDDIR)/html.\"\n+\n+dirhtml:\n+\t$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml\n+\t@echo\n+\t@echo \"Build finished. The HTML pages are in $(BUILDDIR)/dirhtml.\"\n+\n+singlehtml:\n+\t$(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(BUILDDIR)/singlehtml\n+\t@echo\n+\t@echo \"Build finished. The HTML page is in $(BUILDDIR)/singlehtml.\"\n+\n+pickle:\n+\t$(SPHINXBUILD) -b pickle $(ALLSPHINXOPTS) $(BUILDDIR)/pickle\n+\t@echo\n+\t@echo \"Build finished; now you can process the pickle files.\"\n+\n+json:\n+\t$(SPHINXBUILD) -b json $(ALLSPHINXOPTS) $(BUILDDIR)/json\n+\t@echo\n+\t@echo \"Build finished; now you can process the JSON files.\"\n+\n+htmlhelp:\n+\t$(SPHINXBUILD) -b htmlhelp $(ALLSPHINXOPTS) $(BUILDDIR)/htmlhelp\n+\t@echo\n+\t@echo \"Build finished; now you can run HTML Help Workshop with the\" \\\n+\t \".hhp project file in $(BUILDDIR)/htmlhelp.\"\n+\n+qthelp:\n+\t$(SPHINXBUILD) -b qthelp $(ALLSPHINXOPTS) $(BUILDDIR)/qthelp\n+\t@echo\n+\t@echo \"Build finished; now you can run \"qcollectiongenerator\" with the\" \\\n+\t \".qhcp project file in $(BUILDDIR)/qthelp, like this:\"\n+\t@echo \"# qcollectiongenerator $(BUILDDIR)/qthelp/ceres.qhcp\"\n+\t@echo \"To view the help file:\"\n+\t@echo \"# assistant -collectionFile $(BUILDDIR)/qthelp/ceres.qhc\"\n+\n+devhelp:\n+\t$(SPHINXBUILD) -b devhelp $(ALLSPHINXOPTS) $(BUILDDIR)/devhelp\n+\t@echo\n+\t@echo \"Build finished.\"\n+\t@echo \"To view the help file:\"\n+\t@echo \"# mkdir -p $$HOME/.local/share/devhelp/ceres\"\n+\t@echo \"# ln -s $(BUILDDIR)/devhelp $$HOME/.local/share/devhelp/ceres\"\n+\t@echo \"# devhelp\"\n+\n+epub:\n+\t$(SPHINXBUILD) -b epub $(ALLSPHINXOPTS) $(BUILDDIR)/epub\n+\t@echo\n+\t@echo \"Build finished. The epub file is in $(BUILDDIR)/epub.\"\n+\n+latex:\n+\t$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex\n+\t@echo\n+\t@echo \"Build finished; the LaTeX files are in $(BUILDDIR)/latex.\"\n+\t@echo \"Run \\`make' in that directory to run these through (pdf)latex\" \\\n+\t \"(use \\`make latexpdf' here to do that automatically).\"\n+\n+latexpdf:\n+\t$(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(BUILDDIR)/latex\n+\t@echo \"Running LaTeX files through pdflatex...\"\n+\t$(MAKE) -C $(BUILDDIR)/latex all-pdf\n+\t@echo \"pdflatex finished; the PDF files are in $(BUILDDIR)/latex.\"\n+\n+text:\n+\t$(SPHINXBUILD) -b text $(ALLSPHINXOPTS) $(BUILDDIR)/text\n+\t@echo\n+\t@echo \"Build finished. The text files are in $(BUILDDIR)/text.\"\n+\n+man:\n+\t$(SPHINXBUILD) -b man $(ALLSPHINXOPTS) $(BUILDDIR)/man\n+\t@echo\n+\t@echo \"Build finished. The manual pages are in $(BUILDDIR)/man.\"\n+\n+texinfo:\n+\t$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo\n+\t@echo\n+\t@echo \"Build finished. The Texinfo files are in $(BUILDDIR)/texinfo.\"\n+\t@echo \"Run \\`make' in that directory to run these through makeinfo\" \\\n+\t \"(use \\`make info' here to do that automatically).\"\n+\n+info:\n+\t$(SPHINXBUILD) -b texinfo $(ALLSPHINXOPTS) $(BUILDDIR)/texinfo\n+\t@echo \"Running Texinfo files through makeinfo...\"\n+\tmake -C $(BUILDDIR)/texinfo info\n+\t@echo \"makeinfo finished; the Info files are in $(BUILDDIR)/texinfo.\"\n+\n+gettext:\n+\t$(SPHINXBUILD) -b gettext $(I18NSPHINXOPTS) $(BUILDDIR)/locale\n+\t@echo\n+\t@echo \"Build finished. The message catalogs are in $(BUILDDIR)/locale.\"\n+\n+changes:\n+\t$(SPHINXBUILD) -b changes $(ALLSPHINXOPTS) $(BUILDDIR)/changes\n+\t@echo\n+\t@echo \"The overview file is in $(BUILDDIR)/changes.\"\n+\n+linkcheck:\n+\t$(SPHINXBUILD) -b linkcheck $(ALLSPHINXOPTS) $(BUILDDIR)/linkcheck\n+\t@echo\n+\t@echo \"Link check complete; look for any errors in the above output \" \\\n+\t \"or in $(BUILDDIR)/linkcheck/output.txt.\"\n+\n+doctest:\n+\t$(SPHINXBUILD) -b doctest $(ALLSPHINXOPTS) $(BUILDDIR)/doctest\n+\t@echo \"Testing of doctests in the sources finished, look at the \" \\\n+\t \"results in $(BUILDDIR)/doctest/output.txt.\"\n\n<|file_patch|>docs/_static/default.css\ndiff --git a/docs/_static/default.css b/docs/_static/default.css\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..485606664ddfa3a3ac09540e42a166408ed87906\n--- /dev/null\n+++ b/docs/_static/default.css\n@@ -0,0 +1,795 @@\n+/*\n+ * rtd.css\n+ * ~~~~~~~~~~~~~~~\n+ *\n+ * Sphinx stylesheet -- sphinxdoc theme. Originally created by\n+ * Armin Ronacher for Werkzeug.\n+ *\n+ * Customized for ReadTheDocs by Eric Pierce & Eric Holscher\n+ *\n+ * :copyright: Copyright 2007-2010 by the Sphinx team, see AUTHORS.\n+ * :license: BSD, see LICENSE for details.\n+ *\n+ */\n+\n+/* RTD colors\n+ * light blue: #e8ecef\n+ * medium blue: #8ca1af\n+ * dark blue: #465158\n+ * dark grey: #444444\n+ *\n+ * white hover: #d1d9df;\n+ * medium blue hover: #697983;\n+ * green highlight: #8ecc4c\n+ * light blue (project bar): #e8ecef\n+ */\n+\n+@import url(\"basic.css\");\n+\n+/* PAGE LAYOUT -------------------------------------------------------------- */\n+\n+body {\n+ font: 100%/1.5 \"ff-meta-web-pro-1\",\"ff-meta-web-pro-2\",Arial,\"Helvetica Neue\",sans-serif; \n+ text-align: center;\n+ color: black;\n+ background-color: #465158;\n+ padding: 0;\n+ margin: 0;\n+}\n+\n+div.document {\n+ text-align: left;\n+ background-color: #e8ecef;\n+}\n+\n+div.bodywrapper {\n+ background-color: #ffffff;\n+ border-left: 1px solid #ccc;\n+ border-bottom: 1px solid #ccc;\n+ margin: 0 0 0 16em;\n+}\n+\n+div.body {\n+ margin: 0;\n+ padding: 0.5em 1.3em;\n+ min-width: 20em;\n+}\n+\n+div.related {\n+ font-size: 1em;\n+ background-color: #465158;\n+}\n+\n+div.documentwrapper {\n+ float: left;\n+ width: 100%;\n+ background-color: #e8ecef;\n+}\n+\n+\n+/* HEADINGS --------------------------------------------------------------- */\n+\n+h1 {\n+ margin: 0;\n+ padding: 0.7em 0 0.3em 0;\n+ font-size: 1.5em;\n+ line-height: 1.15;\n+ color: #111;\n+ clear: both;\n+}\n+\n+h2 {\n+ margin: 2em 0 0.2em 0;\n+ font-size: 1.35em;\n+ padding: 0;\n+ color: #465158;\n+}\n+\n+h3 {\n+ margin: 1em 0 -0.3em 0;\n+ font-size: 1.2em;\n+ color: #6c818f;\n+}\n+\n+div.body h1 a, div.body h2 a, div.body h3 a, div.body h4 a, div.body h5 a, div.body h6 a {\n+ color: black;\n+}\n+\n+h1 a.anchor, h2 a.anchor, h3 a.anchor, h4 a.anchor, h5 a.anchor, h6 a.anchor {\n+ display: none;\n+ margin: 0 0 0 0.3em;\n+ padding: 0 0.2em 0 0.2em;\n+ color: #aaa !important;\n+}\n+\n+h1:hover a.anchor, h2:hover a.anchor, h3:hover a.anchor, h4:hover a.anchor,\n+h5:hover a.anchor, h6:hover a.anchor {\n+ display: inline;\n+}\n+\n+h1 a.anchor:hover, h2 a.anchor:hover, h3 a.anchor:hover, h4 a.anchor:hover,\n+h5 a.anchor:hover, h6 a.anchor:hover {\n+ color: #777;\n+ background-color: #eee;\n+}\n+\n+\n+/* LINKS ------------------------------------------------------------------ */\n+\n+/* Normal links get a pseudo-underline */\n+a {\n+ color: #444;\n+ text-decoration: none;\n+ border-bottom: 1px solid #ccc;\n+}\n+\n+/* Links in sidebar, TOC, index trees and tables have no underline */\n+.sphinxsidebar a,\n+.toctree-wrapper a,\n+.indextable a,\n+#indices-and-tables a {\n+ color: #444;\n+ text-decoration: none;\n+ border-bottom: none;\n+}\n+\n+/* Most links get an underline-effect when hovered */\n+a:hover,\n+div.toctree-wrapper a:hover,\n+.indextable a:hover,\n+#indices-and-tables a:hover {\n+ color: #111;\n+ text-decoration: none;\n+ border-bottom: 1px solid #111;\n+}\n+\n+/* Footer links */\n+div.footer a {\n+ color: #86989B;\n+ text-decoration: none;\n+ border: none;\n+}\n+div.footer a:hover {\n+ color: #a6b8bb;\n+ text-decoration: underline;\n+ border: none;\n+}\n+\n+/* Permalink anchor (subtle grey with a red hover) */\n+div.body a.headerlink {\n+ color: #ccc;\n+ font-size: 1em;\n+ margin-left: 6px;\n+ padding: 0 4px 0 4px;\n+ text-decoration: none;\n+ border: none;\n+}\n+div.body a.headerlink:hover {\n+ color: #c60f0f;\n+ border: none;\n+}\n+\n+\n+/* NAVIGATION BAR --------------------------------------------------------- */\n+\n+div.related ul {\n+ height: 2.5em;\n+}\n+\n+div.related ul li {\n+ margin: 0;\n+ padding: 0.65em 0;\n+ float: left;\n+ display: block;\n+ color: white; /* For the >> separators */\n+ font-size: 0.8em;\n+}\n+\n+div.related ul li.right {\n+ float: right;\n+ margin-right: 5px;\n+ color: transparent; /* Hide the | separators */\n+}\n+\n+/* \"Breadcrumb\" links in nav bar */\n+div.related ul li a {\n+ order: none;\n+ background-color: inherit;\n+ font-weight: bold;\n+ margin: 6px 0 6px 4px;\n+ line-height: 1.75em;\n+ color: #ffffff;\n+ padding: 0.4em 0.8em;\n+ border: none;\n+ border-radius: 3px;\n+}\n+/* previous / next / modules / index links look more like buttons */\n+div.related ul li.right a {\n+ margin: 0.375em 0;\n+ background-color: #697983;\n+ text-shadow: 0 1px rgba(0, 0, 0, 0.5);\n+ border-radius: 3px;\n+ -webkit-border-radius: 3px;\n+ -moz-border-radius: 3px;\n+}\n+/* All navbar links light up as buttons when hovered */\n+div.related ul li a:hover {\n+ background-color: #8ca1af;\n+ color: #ffffff;\n+ text-decoration: none;\n+ border-radius: 3px;\n+ -webkit-border-radius: 3px;\n+ -moz-border-radius: 3px;\n+}\n+/* Take extra precautions for tt within links */\n+a tt,\n+div.related ul li a tt {\n+ background: inherit !important;\n+ color: inherit !important;\n+}\n+\n+\n+/* SIDEBAR ---------------------------------------------------------------- */\n+\n+div.sphinxsidebarwrapper {\n+ padding: 0;\n+}\n+\n+div.sphinxsidebar {\n+ margin: 0;\n+ margin-left: -100%;\n+ float: left;\n+ top: 3em;\n+ left: 0;\n+ padding: 0 1em;\n+ width: 14em;\n+ font-size: 1em;\n+ text-align: left;\n+ background-color: #e8ecef;\n+}\n+\n+div.sphinxsidebar img {\n+ max-width: 12em;\n+}\n+\n+div.sphinxsidebar h3,\n+div.sphinxsidebar h4,\n+div.sphinxsidebar p.logo {\n+ margin: 1.2em 0 0.3em 0;\n+ font-size: 1em;\n+ padding: 0;\n+ color: #222222;\n+ font-family: \"ff-meta-web-pro-1\", \"ff-meta-web-pro-2\", \"Arial\", \"Helvetica Neue\", sans-serif;\n+}\n+\n+div.sphinxsidebar h3 a {\n+ color: #444444;\n+}\n+\n+div.sphinxsidebar ul,\n+div.sphinxsidebar p {\n+ margin-top: 0;\n+ padding-left: 0;\n+ line-height: 130%;\n+ background-color: #e8ecef;\n+}\n+\n+/* No bullets for nested lists, but a little extra indentation */\n+div.sphinxsidebar ul ul {\n+ list-style-type: none;\n+ margin-left: 1.5em;\n+ padding: 0;\n+}\n+\n+/* A little top/bottom padding to prevent adjacent links' borders\n+ * from overlapping each other */\n+div.sphinxsidebar ul li {\n+ padding: 1px 0;\n+}\n+\n+/* A little left-padding to make these align with the ULs */\n+div.sphinxsidebar p.topless {\n+ padding-left: 0 0 0 1em;\n+}\n+\n+/* Make these into hidden one-liners */\n+div.sphinxsidebar ul li,\n+div.sphinxsidebar p.topless {\n+ white-space: nowrap;\n+ overflow: hidden;\n+}\n+/* ...which become visible when hovered */\n+div.sphinxsidebar ul li:hover,\n+div.sphinxsidebar p.topless:hover {\n+ overflow: visible;\n+}\n+\n+/* Search text box and \"Go\" button */\n+#searchbox {\n+ margin-top: 2em;\n+ margin-bottom: 1em;\n+ background: #ddd;\n+ padding: 0.5em;\n+ border-radius: 6px;\n+ -moz-border-radius: 6px;\n+ -webkit-border-radius: 6px;\n+}\n+#searchbox h3 {\n+ margin-top: 0;\n+}\n+\n+/* Make search box and button abut and have a border */\n+input,\n+div.sphinxsidebar input {\n+ border: 1px solid #999;\n+ float: left;\n+}\n+\n+/* Search textbox */\n+input[type=\"text\"] {\n+ margin: 0;\n+ padding: 0 3px;\n+ height: 20px;\n+ width: 144px;\n+ border-top-left-radius: 3px;\n+ border-bottom-left-radius: 3px;\n+ -moz-border-radius-topleft: 3px;\n+ -moz-border-radius-bottomleft: 3px;\n+ -webkit-border-top-left-radius: 3px;\n+ -webkit-border-bottom-left-radius: 3px;\n+}\n+/* Search button */\n+input[type=\"submit\"] {\n+ margin: 0 0 0 -1px; /* -1px prevents a double-border with textbox */\n+ height: 22px;\n+ color: #444;\n+ background-color: #e8ecef;\n+ padding: 1px 4px;\n+ font-weight: bold;\n+ border-top-right-radius: 3px;\n+ border-bottom-right-radius: 3px;\n+ -moz-border-radius-topright: 3px;\n+ -moz-border-radius-bottomright: 3px;\n+ -webkit-border-top-right-radius: 3px;\n+ -webkit-border-bottom-right-radius: 3px;\n+}\n+input[type=\"submit\"]:hover {\n+ color: #ffffff;\n+ background-color: #8ecc4c;\n+}\n+\n+div.sphinxsidebar p.searchtip {\n+ clear: both;\n+ padding: 0.5em 0 0 0;\n+ background: #ddd;\n+ color: #666;\n+ font-size: 0.9em;\n+}\n+\n+/* Sidebar links are unusual */\n+div.sphinxsidebar li a,\n+div.sphinxsidebar p a {\n+ background: #e8ecef; /* In case links overlap main content */\n+ border-radius: 3px;\n+ -moz-border-radius: 3px;\n+ -webkit-border-radius: 3px;\n+ border: 1px solid transparent; /* To prevent things jumping around on hover */\n+ padding: 0 5px 0 5px;\n+}\n+div.sphinxsidebar li a:hover,\n+div.sphinxsidebar p a:hover {\n+ color: #111;\n+ text-decoration: none;\n+ border: 1px solid #888;\n+}\n+div.sphinxsidebar p.logo a {\n+ border: 0;\n+}\n+\n+/* Tweak any link appearing in a heading */\n+div.sphinxsidebar h3 a {\n+}\n+\n+\n+\n+\n+/* OTHER STUFF ------------------------------------------------------------ */\n+\n+cite, code, tt {\n+ font-family: 'Consolas', 'Deja Vu Sans Mono',\n+ 'Bitstream Vera Sans Mono', monospace;\n+ font-size: 0.95em;\n+ letter-spacing: 0.01em;\n+}\n+\n+tt {\n+ background-color: #f2f2f2;\n+ color: #444;\n+}\n+\n+tt.descname, tt.descclassname, tt.xref {\n+ border: 0;\n+}\n+\n+hr {\n+ border: 1px solid #abc;\n+ margin: 2em;\n+}\n+\n+\n+pre, #_fontwidthtest {\n+ font-family: 'Consolas', 'Deja Vu Sans Mono',\n+ 'Bitstream Vera Sans Mono', monospace;\n+ margin: 1em 2em;\n+ font-size: 0.95em;\n+ letter-spacing: 0.015em;\n+ line-height: 120%;\n+ padding: 0.5em;\n+ border: 1px solid #ccc;\n+ background-color: #eee;\n+ border-radius: 6px;\n+ -moz-border-radius: 6px;\n+ -webkit-border-radius: 6px;\n+}\n+\n+pre a {\n+ color: inherit;\n+ text-decoration: underline;\n+}\n+\n+td.linenos pre {\n+ margin: 1em 0em;\n+}\n+\n+td.code pre {\n+ margin: 1em 0em;\n+}\n+\n+div.quotebar {\n+ background-color: #f8f8f8;\n+ max-width: 250px;\n+ float: right;\n+ padding: 2px 7px;\n+ border: 1px solid #ccc;\n+}\n+\n+div.topic {\n+ background-color: #f8f8f8;\n+}\n+\n+table {\n+ border-collapse: collapse;\n+ margin: 0 -0.5em 0 -0.5em;\n+}\n+\n+table td, table th {\n+ padding: 0.2em 0.5em 0.2em 0.5em;\n+}\n+\n+\n+/* ADMONITIONS AND WARNINGS ------------------------------------------------- */\n+\n+/* Shared by admonitions, warnings and sidebars */\n+div.admonition,\n+div.warning,\n+div.sidebar {\n+ font-size: 0.9em;\n+ margin: 2em;\n+ padding: 0;\n+ /*\n+ border-radius: 6px;\n+ -moz-border-radius: 6px;\n+ -webkit-border-radius: 6px;\n+ */\n+}\n+div.admonition p,\n+div.warning p,\n+div.sidebar p {\n+ margin: 0.5em 1em 0.5em 1em;\n+ padding: 0;\n+}\n+div.admonition pre,\n+div.warning pre,\n+div.sidebar pre {\n+ margin: 0.4em 1em 0.4em 1em;\n+}\n+div.admonition p.admonition-title,\n+div.warning p.admonition-title,\n+div.sidebar p.sidebar-title {\n+ margin: 0;\n+ padding: 0.1em 0 0.1em 0.5em;\n+ color: white;\n+ font-weight: bold;\n+ font-size: 1.1em;\n+ text-shadow: 0 1px rgba(0, 0, 0, 0.5);\n+}\n+div.admonition ul, div.admonition ol,\n+div.warning ul, div.warning ol,\n+div.sidebar ul, div.sidebar ol {\n+ margin: 0.1em 0.5em 0.5em 3em;\n+ padding: 0;\n+}\n+\n+\n+/* Admonitions and sidebars only */\n+div.admonition, div.sidebar {\n+ border: 1px solid #609060;\n+ background-color: #e9ffe9;\n+}\n+div.admonition p.admonition-title,\n+div.sidebar p.sidebar-title {\n+ background-color: #70A070;\n+ border-bottom: 1px solid #609060;\n+}\n+\n+\n+/* Warnings only */\n+div.warning {\n+ border: 1px solid #900000;\n+ background-color: #ffe9e9;\n+}\n+div.warning p.admonition-title {\n+ background-color: #b04040;\n+ border-bottom: 1px solid #900000;\n+}\n+\n+\n+/* Sidebars only */\n+div.sidebar {\n+ max-width: 30%;\n+}\n+\n+\n+\n+div.versioninfo {\n+ margin: 1em 0 0 0;\n+ border: 1px solid #ccc;\n+ background-color: #DDEAF0;\n+ padding: 8px;\n+ line-height: 1.3em;\n+ font-size: 0.9em;\n+}\n+\n+.viewcode-back {\n+ font-family: 'Lucida Grande', 'Lucida Sans Unicode', 'Geneva',\n+ 'Verdana', sans-serif;\n+}\n+\n+div.viewcode-block:target {\n+ background-color: #f4debf;\n+ border-top: 1px solid #ac9;\n+ border-bottom: 1px solid #ac9;\n+}\n+\n+dl {\n+ margin: 1em 0 2.5em 0;\n+}\n+\n+/* Highlight target when you click an internal link */\n+dt:target {\n+ background: #ffe080;\n+}\n+/* Don't highlight whole divs */\n+div.highlight {\n+ background: transparent;\n+}\n+/* But do highlight spans (so search results can be highlighted) */\n+span.highlight {\n+ background: #ffe080;\n+}\n+\n+div.footer {\n+ background-color: #465158;\n+ color: #eeeeee;\n+ padding: 0 2em 2em 2em;\n+ clear: both;\n+ font-size: 0.8em;\n+ text-align: center;\n+}\n+\n+p {\n+ margin: 0.8em 0 0.5em 0;\n+}\n+\n+.section p img.math {\n+ margin: 0;\n+}\n+\n+\n+.section p img {\n+ margin: 1em 2em;\n+}\n+\n+\n+/* MOBILE LAYOUT -------------------------------------------------------------- */\n+\n+@media screen and (max-width: 600px) {\n+ \n+ h1, h2, h3, h4, h5 {\n+ position: relative;\n+ }\n+\n+ ul {\n+ padding-left: 1.25em;\n+ }\n+\n+ div.bodywrapper a.headerlink, #indices-and-tables h1 a {\n+ color: #e6e6e6;\n+ font-size: 80%;\n+ float: right;\n+ line-height: 1.8;\n+ position: absolute;\n+ right: -0.7em;\n+ visibility: inherit;\n+ }\n+\n+ div.bodywrapper h1 a.headerlink, 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padding: 1em;\n+ }\n+\n+ .rtd_doc_footer .rtd-badge {\n+ float: none;\n+ margin: 1em auto;\n+ position: static;\n+ }\n+\n+ .rtd_doc_footer .rtd-badge.revsys-inline {\n+ margin-right: auto;\n+ margin-bottom: 2em;\n+ }\n+\n+ table.indextable {\n+ display: block;\n+ width: auto; \n+ }\n+\n+ .indextable tr {\n+ display: block;\n+ }\n+\n+ .indextable td {\n+ display: block;\n+ padding: 0;\n+ width: auto !important;\n+ }\n+\n+ .indextable td dt {\n+ margin: 1em 0;\n+ }\n+\n+ ul.search {\n+ margin-left: 0.25em;\n+ }\n+\n+ ul.search li div.context {\n+ font-size: 90%;\n+ line-height: 1.1;\n+ margin-bottom: 1;\n+ margin-left: 0;\n+ }\n+\n+}\n\n<|file_patch|>docs/ceres.rst\ndiff --git a/docs/ceres.rst b/docs/ceres.rst\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..2fbce2c9bd36aa1adc6bc243a097ad4e06de5031\n--- /dev/null\n+++ b/docs/ceres.rst\n@@ -0,0 +1,10 @@\n+============================================\n+ceres\n+============================================\n+\n+.. contents::\n+ :local:\n+\n+.. automodule:: ceres\n+ :members:\n+ :undoc-members:\n\n<|file_patch|>docs/conf.py\ndiff --git a/docs/conf.py b/docs/conf.py\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..58264f083968a69d20062b10d5338f6b9c0f02af\n--- /dev/null\n+++ b/docs/conf.py\n@@ -0,0 +1,246 @@\n+# -*- coding: utf-8 -*-\n+#\n+# ceres documentation build configuration file, created by\n+# sphinx-quickstart on Thu Jan 3 04:15:28 2013.\n+#\n+# This file is execfile()d with the current directory set to its containing dir.\n+#\n+# Note that not all possible configuration values are present in this\n+# autogenerated file.\n+#\n+# All configuration values have a default; values that are commented out\n+# serve to show the default.\n+\n+import sys, os\n+\n+# If extensions (or modules to document with autodoc) are in another directory,\n+# add these directories to sys.path here. If the directory is relative to the\n+# documentation root, use os.path.abspath to make it absolute, like shown here.\n+sys.path.insert(0, os.path.abspath('..'))\n+\n+# -- General configuration -----------------------------------------------------\n+\n+# If your documentation needs a minimal Sphinx version, state it here.\n+#needs_sphinx = '1.0'\n+\n+# Add any Sphinx extension module names here, as strings. They can be extensions\n+# coming with Sphinx (named 'sphinx.ext.*') or your custom ones.\n+extensions = ['sphinx.ext.autodoc', 'sphinx.ext.intersphinx', 'sphinx.ext.coverage', 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode']\n+\n+# Add any paths that contain templates here, relative to this directory.\n+templates_path = ['.templates']\n+\n+# The suffix of source filenames.\n+source_suffix = '.rst'\n+\n+# The encoding of source files.\n+#source_encoding = 'utf-8-sig'\n+\n+# The master toctree document.\n+master_doc = 'index'\n+\n+# General information about the project.\n+project = u'ceres'\n+copyright = u'2011, Chris Davis'\n+\n+# The version info for the project you're documenting, acts as replacement for\n+# |version| and |release|, also used in various other places throughout the\n+# built documents.\n+#\n+# The short X.Y version.\n+version = '0.10.0'\n+# The full version, including alpha/beta/rc tags.\n+release = '0.10.0'\n+\n+# The language for content autogenerated by Sphinx. Refer to documentation\n+# for a list of supported languages.\n+#language = None\n+\n+# There are two options for replacing |today|: either, you set today to some\n+# non-false value, then it is used:\n+#today = ''\n+# Else, today_fmt is used as the format for a strftime call.\n+#today_fmt = '%B %d, %Y'\n+\n+# List of patterns, relative to source directory, that match files and\n+# directories to ignore when looking for source files.\n+exclude_patterns = ['_build']\n+\n+# The reST default role (used for this markup: `text`) to use for all documents.\n+#default_role = None\n+\n+# If true, '()' will be appended to :func: etc. cross-reference text.\n+#add_function_parentheses = True\n+\n+# If true, the current module name will be prepended to all description\n+# unit titles (such as .. function::).\n+#add_module_names = True\n+\n+# If true, sectionauthor and moduleauthor directives will be shown in the\n+# output. They are ignored by default.\n+#show_authors = False\n+\n+# The name of the Pygments (syntax highlighting) style to use.\n+pygments_style = 'sphinx'\n+\n+# A list of ignored prefixes for module index sorting.\n+#modindex_common_prefix = []\n+\n+\n+# -- Options for HTML output ---------------------------------------------------\n+\n+# The theme to use for HTML and HTML Help pages. See the documentation for\n+# a list of builtin themes.\n+html_theme = 'default'\n+\n+# Theme options are theme-specific and customize the look and feel of a theme\n+# further. For a list of options available for each theme, see the\n+# documentation.\n+#html_theme_options = {}\n+\n+# Add any paths that contain custom themes here, relative to this directory.\n+#html_theme_path = []\n+\n+# The name for this set of Sphinx documents. If None, it defaults to\n+# \"<project> v<release> documentation\".\n+#html_title = None\n+\n+# A shorter title for the navigation bar. Default is the same as html_title.\n+#html_short_title = None\n+\n+# The name of an image file (relative to this directory) to place at the top\n+# of the sidebar.\n+#html_logo = None\n+\n+# The name of an image file (within the static path) to use as favicon of the\n+# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32\n+# pixels large.\n+#html_favicon = None\n+\n+# Add any paths that contain custom static files (such as style sheets) here,\n+# relative to this directory. They are copied after the builtin static files,\n+# so a file named \"default.css\" will overwrite the builtin \"default.css\".\n+html_static_path = ['_static']\n+\n+# If not '', a 'Last updated on:' timestamp is inserted at every page bottom,\n+# using the given strftime format.\n+#html_last_updated_fmt = '%b %d, %Y'\n+\n+# If true, SmartyPants will be used to convert quotes and dashes to\n+# typographically correct entities.\n+#html_use_smartypants = True\n+\n+# Custom sidebar templates, maps document names to template names.\n+#html_sidebars = {}\n+\n+# Additional templates that should be rendered to pages, maps page names to\n+# template names.\n+#html_additional_pages = {}\n+\n+# If false, no module index is generated.\n+#html_domain_indices = True\n+\n+# If false, no index is generated.\n+#html_use_index = True\n+\n+# If true, the index is split into individual pages for each letter.\n+#html_split_index = False\n+\n+# If true, links to the reST sources are added to the pages.\n+#html_show_sourcelink = True\n+\n+# If true, \"Created using Sphinx\" is shown in the HTML footer. Default is True.\n+#html_show_sphinx = True\n+\n+# If true, \"(C) Copyright ...\" is shown in the HTML footer. Default is True.\n+#html_show_copyright = True\n+\n+# If true, an OpenSearch description file will be output, and all pages will\n+# contain a <link> tag referring to it. The value of this option must be the\n+# base URL from which the finished HTML is served.\n+#html_use_opensearch = ''\n+\n+# This is the file name suffix for HTML files (e.g. \".xhtml\").\n+#html_file_suffix = None\n+\n+# Output file base name for HTML help builder.\n+htmlhelp_basename = 'ceresdoc'\n+\n+\n+# -- Options for LaTeX output --------------------------------------------------\n+\n+latex_elements = {\n+# The paper size ('letterpaper' or 'a4paper').\n+#'papersize': 'letterpaper',\n+\n+# The font size ('10pt', '11pt' or '12pt').\n+#'pointsize': '10pt',\n+\n+# Additional stuff for the LaTeX preamble.\n+#'preamble': '',\n+}\n+\n+# Grouping the document tree into LaTeX files. List of tuples\n+# (source start file, target name, title, author, documentclass [howto/manual]).\n+latex_documents = [\n+ ('index', 'ceres.tex', u'ceres Documentation',\n+ u'Chris Davis', 'manual'),\n+]\n+\n+# The name of an image file (relative to this directory) to place at the top of\n+# the title page.\n+#latex_logo = None\n+\n+# For \"manual\" documents, if this is true, then toplevel headings are parts,\n+# not chapters.\n+#latex_use_parts = False\n+\n+# If true, show page references after internal links.\n+#latex_show_pagerefs = False\n+\n+# If true, show URL addresses after external links.\n+#latex_show_urls = False\n+\n+# Documents to append as an appendix to all manuals.\n+#latex_appendices = []\n+\n+# If false, no module index is generated.\n+#latex_domain_indices = True\n+\n+\n+# -- Options for manual page output --------------------------------------------\n+\n+# One entry per manual page. List of tuples\n+# (source start file, name, description, authors, manual section).\n+man_pages = [\n+ ('index', 'ceres', u'ceres Documentation',\n+ [u'Chris Davis'], 1)\n+]\n+\n+# If true, show URL addresses after external links.\n+#man_show_urls = False\n+\n+\n+# -- Options for Texinfo output ------------------------------------------------\n+\n+# Grouping the document tree into Texinfo files. List of tuples\n+# (source start file, target name, title, author,\n+# dir menu entry, description, category)\n+texinfo_documents = [\n+ ('index', 'ceres', u'ceres Documentation',\n+ u'Chris Davis', 'ceres', 'One line description of project.',\n+ 'Miscellaneous'),\n+]\n+\n+# Documents to append as an appendix to all manuals.\n+#texinfo_appendices = []\n+\n+# If false, no module index is generated.\n+#texinfo_domain_indices = True\n+\n+# How to display URL addresses: 'footnote', 'no', or 'inline'.\n+#texinfo_show_urls = 'footnote'\n+\n+\n+# Example configuration for intersphinx: refer to the Python standard library.\n+intersphinx_mapping = {'http://docs.python.org/': None}\n\n<|file_patch|>docs/index.rst\ndiff --git a/docs/index.rst b/docs/index.rst\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1b5bad8907a4e1463191e8bbb560a1826e2de91c\n--- /dev/null\n+++ b/docs/index.rst\n@@ -0,0 +1,7 @@\n+Ceres\n+=====\n+\n+* :ref:`genindex`\n+* :ref:`modindex`\n+* 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container base image to Ubuntu 22.04\n\n<|file_patch|>src/Dockerfile\ndiff --git a/src/Dockerfile b/src/Dockerfile\nindex 08fb8d77aba908f8aec70a35effe07cfd7d139e0..0c8ec2dcdce12b7e1399f289ae53eb4530bb2c0b 100644\n--- a/src/Dockerfile\n+++ b/src/Dockerfile\n@@ -1,4 +1,4 @@\n-FROM ubuntu:20.04 AS builder\n+FROM ubuntu:22.04 AS builder\n \n ENV DEBIAN_FRONTEND=noninteractive\n \n@@ -25,7 +25,9 @@ RUN git clone https://github.com/awslabs/aws-iot-device-client.git && \\\n && \\\n cmake --build . --target aws-iot-device-client\n \n-FROM ubuntu:20.04\n+################################################################################\n+\n+FROM ubuntu:22.04\n \n ENV DEBIAN_FRONTEND=noninteractive\n ENV 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support for fake cursor\n\n<|file_patch|>internal/display/bufwindow.go\ndiff --git a/internal/display/bufwindow.go b/internal/display/bufwindow.go\nindex ccbe2d983ac104d00fe0514143a582e96b25db81..0b4391ae09c88e9e4eefa111ee9db814f14e1e15 100644\n--- a/internal/display/bufwindow.go\n+++ b/internal/display/bufwindow.go\n@@ -1,7 +1,6 @@\n package display\n \n import (\n-\t\"runtime\"\n \t\"strconv\"\n \t\"unicode/utf8\"\n \n@@ -340,11 +339,10 @@ func (w *BufWindow) getStyle(style tcell.Style, bloc buffer.Loc, r rune) (tcell.\n \n func (w *BufWindow) showCursor(x, y int, main bool) {\n \tif w.active {\n-\t\tif main && runtime.GOOS != \"windows\" {\n-\t\t\tscreen.Screen.ShowCursor(x, y)\n+\t\tif main {\n+\t\t\tscreen.ShowCursor(x, y)\n \t\t} else {\n-\t\t\tr, _, _, _ := screen.Screen.GetContent(x, y)\n-\t\t\tscreen.Screen.SetContent(x, y, r, nil, config.DefStyle.Reverse(true))\n+\t\t\tscreen.ShowFakeCursor(x, y)\n \t\t}\n \t}\n }\n@@ -596,13 +594,7 @@ func (w *BufWindow) displayBuffer() {\n \t\t\tscreen.Screen.SetContent(i+w.X, vloc.Y+w.Y, ' ', nil, curStyle)\n \t\t}\n \n-\t\tfor _, c := range cursors {\n-\t\t\tif c.X == bloc.X && c.Y == bloc.Y && !c.HasSelection() {\n-\t\t\t\tw.showCursor(w.X+vloc.X, w.Y+vloc.Y, c.Num == 0)\n-\t\t\t}\n-\t\t}\n-\n-\t\tdraw(' ', curStyle, false)\n+\t\tdraw(' ', curStyle, true)\n \n \t\tbloc.X = w.StartCol\n \t\tbloc.Y++\n\n<|file_patch|>internal/display/infowindow.go\ndiff --git a/internal/display/infowindow.go b/internal/display/infowindow.go\nindex b179c81e941978ca808573975866c81a9a8a13df..45dc2c6569fb76a8bc4560ab6a5f5d9872e8c846 100644\n--- a/internal/display/infowindow.go\n+++ b/internal/display/infowindow.go\n@@ -121,7 +121,7 @@ func (i *InfoWindow) displayBuffer() {\n \ttotalwidth := blocX - nColsBeforeStart\n \tfor len(line) > 0 {\n \t\tif activeC.X == blocX {\n-\t\t\tscreen.Screen.ShowCursor(vlocX, i.Y)\n+\t\t\tscreen.ShowCursor(vlocX, i.Y)\n \t\t}\n \n \t\tr, size := utf8.DecodeRune(line)\n@@ -155,7 +155,7 @@ func (i *InfoWindow) displayBuffer() {\n \t\t}\n \t}\n \tif activeC.X == blocX {\n-\t\tscreen.Screen.ShowCursor(vlocX, i.Y)\n+\t\tscreen.ShowCursor(vlocX, i.Y)\n \t}\n }\n \n\n<|file_patch|>internal/display/termwindow.go\ndiff --git a/internal/display/termwindow.go b/internal/display/termwindow.go\nindex 95a9003764064f5aade804ebbcc2e202b0bb40e1..23ae1dbeb6789b39e016deea73919432705132f0 100644\n--- a/internal/display/termwindow.go\n+++ b/internal/display/termwindow.go\n@@ -111,6 +111,6 @@ func (w *TermWindow) Display() {\n \t}\n \tif w.State.CursorVisible() && w.active {\n \t\tcurx, cury := w.State.Cursor()\n-\t\tscreen.Screen.ShowCursor(curx+w.X, cury+w.Y)\n+\t\tscreen.ShowCursor(curx+w.X, cury+w.Y)\n \t}\n }\n\n<|file_patch|>internal/screen/screen.go\ndiff --git a/internal/screen/screen.go b/internal/screen/screen.go\nindex ec3fbdd013d965e34ced6c51b29eed6f7eaabe88..cca9036d6c0e35534b958f191fdbbf5e96e667d3 100644\n--- a/internal/screen/screen.go\n+++ b/internal/screen/screen.go\n@@ -6,6 +6,7 @@ import (\n \t\"sync\"\n \n \t\"github.com/zyedidia/micro/internal/config\"\n+\t\"github.com/zyedidia/micro/internal/util\"\n \t\"github.com/zyedidia/tcell\"\n )\n \n@@ -31,6 +32,19 @@ func Redraw() {\n \tDrawChan <- true\n }\n \n+func ShowFakeCursor(x, y int) {\n+\tr, _, _, _ := Screen.GetContent(x, y)\n+\tScreen.SetContent(x, y, r, nil, config.DefStyle.Reverse(true))\n+}\n+\n+func ShowCursor(x, y int) {\n+\tif util.FakeCursor {\n+\t\tShowFakeCursor(x, y)\n+\t} else {\n+\t\tScreen.ShowCursor(x, y)\n+\t}\n+}\n+\n // TempFini shuts the screen down temporarily\n func TempFini() bool {\n \tscreenWasNil := Screen == nil\n\n<|file_patch|>internal/util/util.go\ndiff --git a/internal/util/util.go b/internal/util/util.go\nindex 92af3bce969b5228af2e7a60369bfcb03637dcec..9bc3f7e1f6df1f9ad51584db839968a3127dd1e7 100644\n--- a/internal/util/util.go\n+++ b/internal/util/util.go\n@@ -7,6 +7,7 @@ import (\n \t\"os/user\"\n \t\"path/filepath\"\n \t\"regexp\"\n+\t\"runtime\"\n \t\"strconv\"\n \t\"strings\"\n \t\"time\"\n@@ -30,6 +31,9 @@ var (\n \tCompileDate = \"Unknown\"\n \t// Debug logging\n \tDebug = \"ON\"\n+\t// FakeCursor is used to disable the terminal cursor and have micro\n+\t// draw its own (enabled for windows consoles where the cursor is slow)\n+\tFakeCursor = true\n )\n \n func init() {\n@@ -38,6 +42,10 @@ func init() {\n \tif err != nil {\n \t\tfmt.Println(\"Invalid version: \", Version, err)\n \t}\n+\n+\tif runtime.GOOS == \"windows\" {\n+\t\tFakeCursor = true\n+\t}\n }\n \n // SliceEnd returns a byte slice where the index is a rune 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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
commit-doc:github.com/mingrammer/diagrams@7c18dd6965e3334cb3cccd11a478ba1675111378 | <|commit_message|>
feat: autolabel flag in diagrams that modifies label (#482)
* autolabel flag in diagrams that modifies label
* update based on review
<|file_patch|>diagrams/__init__.py
diff --git a/diagrams/__init__.py b/diagrams/__init__.py
index 2d16ca6dec759ecc37d61c54b2516d408c2c2401..690a8a0b5e7e4b8d0352a6e... | 157 | code.commit.baseline | band-01 | 2,994 | 2,932,890,561,242,270,700 | null | null | null | github.com/mingrammer/diagrams | 01 | true | no_named_signal_detected | 7 | python | parent_reconstructed | {"clone_url":"https://github.com/mingrammer/diagrams","commit_oid":"7c18dd6965e3334cb3cccd11a478ba1675111378","commits_ago_from_head":224,"content_sha256":"16f35fa7e05bc19596b958518973d76b108123f6eca3e1c935a0070f42af1291","manifest_sha256":null,"parent_oid":"0ca9385a628b24f576d7ff220feb17ca7d1c80ed","repository_id":"gi... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":7,"deductions":[],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/octoprint/octoprint@7ea6969e13c9843b858a3d31535db73bcf448595 | <|commit_message|>
Prevent script error in build setup
<|file_patch|>docs/development/environment.rst
diff --git a/docs/development/environment.rst b/docs/development/environment.rst
index 93756517b3f3dab10db8f87021c7136cad16da2f..9f3e05d6b3ebccd718253b8cdd87e28243c02156 100644
--- a/docs/development/environment.rst
+... | 56 | code.commit.baseline | band-01 | 3,015 | 2,933,355,506,169,339,000 | null | null | null | github.com/octoprint/octoprint | 01 | false | no_named_signal_detected | 4 | null | parent_reconstructed | {"clone_url":"https://github.com/octoprint/octoprint","commit_oid":"7ea6969e13c9843b858a3d31535db73bcf448595","commits_ago_from_head":2606,"content_sha256":"8665038fd169c919c4a0b2fec4694f6ec609766fd7403d7a26eb8dfc2d87be7c","manifest_sha256":null,"parent_oid":"b5b1e8a812570b23ce3adc1f972744b59cb21982","repository_id":"g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/darkflippers/unleashed-firmware@82f77edc702f5631c806a7f7b9f250b721628ab9 | <|commit_message|>
Fix file browser back history
<|file_patch|>applications/main/archive/helpers/archive_browser.c
diff --git a/applications/main/archive/helpers/archive_browser.c b/applications/main/archive/helpers/archive_browser.c
index 97c68545e1cacbf7328fb3244f75757b5c8d6a02..b37c550bdcd213802dc102ca7935c4d8e22e6... | 50 | code.commit.baseline | band-10 | 6,954 | 2,934,620,670,761,707,000 | null | null | null | github.com/darkflippers/unleashed-firmware | 10 | false | no_named_signal_detected | 0 | c | parent_reconstructed | {"clone_url":"https://github.com/darkflippers/unleashed-firmware","commit_oid":"82f77edc702f5631c806a7f7b9f250b721628ab9","commits_ago_from_head":4544,"content_sha256":"35c529e5fc91d534efd73906fb01ee6bafa55bc78b1567c9ac76de193c2b957f","manifest_sha256":null,"parent_oid":"80b8a0dddbf351506526328d816ce28108726089","repos... | {"annotations":{"commit_quality_band":"10","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":10},"conventional_commit_type":... |
commit-doc:github.com/reactor/reactor-core@7793e2e7bdd56a8310f2460a3f13e3684de8495f | <|commit_message|>
fix #1025 Avoid using only hashcode as default distinct*() criteria
This commit replaces the default `distinct()` method (as well as
`distinctUntilChanged()`) to use the full object as the key instead of
just the `hashcode`. The later would be too susceptible to hashcode
collisions (2 equal obj... | 737 | code.commit.baseline | band-01 | 8,085 | 2,934,804,850,355,516,400 | null | null | null | github.com/reactor/reactor-core | 01 | true | no_named_signal_detected | 9 | java | parent_reconstructed | {"clone_url":"https://github.com/reactor/reactor-core","commit_oid":"7793e2e7bdd56a8310f2460a3f13e3684de8495f","commits_ago_from_head":3336,"content_sha256":"54c43674c8271c0677131fec167f0acaa065c375cac04dd22fa8996b64306f5d","manifest_sha256":null,"parent_oid":"f4da436bd9e7b37f46b422e0d53451b92b10fae8","repository_id":"... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":9,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":11,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000"... |
commit-doc:github.com/babylonjs/documentation@091a69277cb4775838fb51c2cee5fc3e724b361f | <|commit_message|>
Add "Creating an audio engine" section
<|file_patch|>content/features/featuresDeepDive/audio/v2/playingSoundsMusic.md
diff --git a/content/features/featuresDeepDive/audio/v2/playingSoundsMusic.md b/content/features/featuresDeepDive/audio/v2/playingSoundsMusic.md
index fdd7f1710989162caaa163b0483d85c... | 59 | code.commit.baseline | band-05 | 2,358 | 2,934,809,389,175,954,000 | null | null | null | github.com/babylonjs/documentation | 05 | false | no_named_signal_detected | 2 | markdown | parent_reconstructed | {"clone_url":"https://github.com/babylonjs/documentation","commit_oid":"091a69277cb4775838fb51c2cee5fc3e724b361f","commits_ago_from_head":433,"content_sha256":"3ad36b05a92a26f7d22a35052e1f3d88e23f84053d2deed153fdfc9a7796c214","manifest_sha256":null,"parent_oid":"cc46256c178f9833f6e089d4694f59449300dc50","repository_id"... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/paddlepaddle/paddle@da8431569798c2d155f866f4fa6a6980e4097d2a | <|commit_message|>
optimize pir:: in paddle/fluid/pir/transforms/general/ [fluid_ops] (#77404)
* Fix
* Fix
<|file_patch|>paddle/fluid/pir/dialect/kernel/ir/kernel_op.h
diff --git a/paddle/fluid/pir/dialect/kernel/ir/kernel_op.h b/paddle/fluid/pir/dialect/kernel/ir/kernel_op.h
index 56abb10f16189d3cae76f228a2f853700f8... | 109 | code.commit.baseline | band-01 | 112,323 | 2,934,922,965,761,156,000 | null | null | null | github.com/paddlepaddle/paddle | 01 | false | no_named_signal_detected | 5 | cpp | parent_reconstructed | {"clone_url":"https://github.com/paddlepaddle/paddle","commit_oid":"da8431569798c2d155f866f4fa6a6980e4097d2a","commits_ago_from_head":1059,"content_sha256":"dc169c950fe3ee3f2b1357a5a195638d2ae62fe1c3fbd73f2c897e4f738226ce","manifest_sha256":null,"parent_oid":"c50a00c61a2e45a414d4837b2ab3e741ac17ab78","repository_id":"g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[{"points":2,"reason":"candidate_cap_rungs_exceeded"}],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top10":3},"rubr... |
commit-doc:github.com/alcideio/azure-sdk-for-go@ffa1f75e62a8b14e6f1a7c598f46a04064733b7d | <|commit_message|>
Generated from f4847630d0ac480f6c18a43cc92d3e5798ab14bb (#3835)
Fix duplicate path in old Network API version
<|file_patch|>services/network/mgmt/2015-06-15/network/networkapi/interfaces.go
diff --git a/services/network/mgmt/2015-06-15/network/networkapi/interfaces.go b/services/network/mgmt/2015-06... | 130 | code.commit.baseline | band-03 | 6,006 | 2,935,596,073,140,026,400 | null | null | null | github.com/alcideio/azure-sdk-for-go | 03 | false | no_named_signal_detected | 3 | go | parent_reconstructed | {"clone_url":"https://github.com/alcideio/azure-sdk-for-go","commit_oid":"ffa1f75e62a8b14e6f1a7c598f46a04064733b7d","commits_ago_from_head":568,"content_sha256":"31308d3ff1730ddf275784182c1d721eaaf6cd1a47fcd524ea346a532e3e07e1","manifest_sha256":null,"parent_oid":"90e4afacbf247a9988c0a24871c18bddffd67cec","repository_i... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/2ndquadrant/ansible@a95c76855dca5c9f85cf684253e2c957cc64c3f5 | <|commit_message|>
Fix broken links in crypto, docker and hetzner modules. (#67360) (#67363)
(cherry picked from commit 11e75b0af256f9f09c54365282a4969a5fe0390e)
<|file_patch|>lib/ansible/modules/crypto/acme/acme_certificate_revoke.py
diff --git a/lib/ansible/modules/crypto/acme/acme_certificate_revoke.py b/lib/ansibl... | 163 | code.commit.baseline | band-02 | 3,259 | 2,935,654,469,180,089,000 | null | null | null | github.com/2ndquadrant/ansible | 02 | false | no_named_signal_detected | 3 | python | parent_reconstructed | {"clone_url":"https://github.com/2ndquadrant/ansible","commit_oid":"a95c76855dca5c9f85cf684253e2c957cc64c3f5","commits_ago_from_head":673,"content_sha256":"3d28856d683213f24383ba07013bb25052cab8a70c8e401b150db35cc8917930","manifest_sha256":null,"parent_oid":"227f498314eb5d0189fa6fb128825c859ce38739","repository_id":"gi... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":2},"conventional_commit_type":{... |
commit-doc:github.com/appwrite/sdk-generator@9bacbb57dd4fcc7f348da75bb6b8b518a178ab58 | <|commit_message|>
try fix java
<|file_patch|>templates/android/docs/java/example.md.twig
diff --git a/templates/android/docs/java/example.md.twig b/templates/android/docs/java/example.md.twig
index 2dab9aa78d9b32e0e174104f5db5ae39de6dc352..11350375c2c05c4f7007621111b075eec4f49dcf 100644
--- a/templates/android/docs/j... | 33 | code.commit.baseline | band-09 | 1,050 | 2,935,892,167,889,505,300 | null | null | null | github.com/appwrite/sdk-generator | 09 | false | no_named_signal_detected | 0 | markdown | parent_reconstructed | {"clone_url":"https://github.com/appwrite/sdk-generator","commit_oid":"9bacbb57dd4fcc7f348da75bb6b8b518a178ab58","commits_ago_from_head":2130,"content_sha256":"320444aa0c47f72b33c67374bd3482bdda14d2ccb367ff1bc03a91c51413e917","manifest_sha256":null,"parent_oid":"d552c639a9b4c025cffde3c5361a086574adfe7b","repository_id"... | {"annotations":{"commit_quality_band":"09","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/microsoft/vscode-copilot-chat@05d669024187f476f25e6c36d4384acc2f6786ab | <|commit_message|>
Ship copilot shim that installs and then launches copilot for user (#1315)
* Ship copilot shim that installs and launches copilot for user
* Updates
* Updates
* Updates
<|file_patch|>resources/scripts/copilot
diff --git a/resources/scripts/copilot b/resources/scripts/copilot
new file mode 100755
... | 192 | code.commit.baseline | band-01 | 62,341 | 2,935,915,867,601,721,300 | null | null | null | github.com/microsoft/vscode-copilot-chat | 01 | false | no_named_signal_detected | 4 | typescript | parent_reconstructed | {"clone_url":"https://github.com/microsoft/vscode-copilot-chat","commit_oid":"05d669024187f476f25e6c36d4384acc2f6786ab","commits_ago_from_head":2682,"content_sha256":"2d728a2f12502e668131386a43cefda05fba21fcf9d6d33389bc5d6c7b5ee5a3","manifest_sha256":null,"parent_oid":"0358cfb5f8db04d7594492adad65d444d6cb5f4f","reposit... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/10up/simple-podcasting@6e981240ea7d582dd3460d36b718feb9267c22a2 | <|commit_message|>
Internationalize the rest of the strings
<|file_patch|>includes/datatypes.php
diff --git a/includes/datatypes.php b/includes/datatypes.php
index 2be3213b4deea9b3b1dc64f69f54c692ff2defc9..386cc8e952d0a0cf69c27d17a0c8c8fda7789ec9 100644
--- a/includes/datatypes.php
+++ b/includes/datatypes.php
@@ -28,... | 61 | code.commit.baseline | band-02 | 13,017 | 2,936,038,281,485,300,000 | null | null | null | github.com/10up/simple-podcasting | 02 | false | no_named_signal_detected | 3 | php | parent_reconstructed | {"clone_url":"https://github.com/10up/simple-podcasting","commit_oid":"6e981240ea7d582dd3460d36b718feb9267c22a2","commits_ago_from_head":1113,"content_sha256":"aebe982180a00136261c237bdd164fccfee8654b521ccb67ad95aa57d70679b9","manifest_sha256":null,"parent_oid":"0de1d3a312f143b1f6e8a8138fe79520424efa59","repository_id"... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":2},"conventional_commit_type":{... |
commit-doc:github.com/aio-libs/janus@8ed256d1c95418a855ae796478c78c2e7812f660 | <|commit_message|>
Bump tox from 3.18.0 to 3.18.1
Bumps [tox](https://github.com/tox-dev/tox) from 3.18.0 to 3.18.1.
- [Release notes](https://github.com/tox-dev/tox/releases)
- [Changelog](https://github.com/tox-dev/tox/blob/master/docs/changelog.rst)
- [Commits](https://github.com/tox-dev/tox/compare/3.18.0...3.18.1... | 387 | code.commit.baseline | band-02 | 758 | 2,936,386,516,462,756,400 | null | null | null | github.com/aio-libs/janus | 02 | false | detected_named_ai_or_bot_signal | 2 | null | parent_reconstructed | {"clone_url":"https://github.com/aio-libs/janus","commit_oid":"8ed256d1c95418a855ae796478c78c2e7812f660","commits_ago_from_head":572,"content_sha256":"fd681bd953524390043091c78ef829f19236d1428e1aec7e13c48b54bc4bd134","manifest_sha256":null,"parent_oid":"85f49c1811a25d5bdf520b2fdab2ad66adc69987","repository_id":"github.... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/balena-io/renovate-config@44ed343e46536215b70f74d9916d294189513e89 | <|commit_message|>
Update actions/checkout digest to 692973e
Update actions/checkout
Change-type: patch
<|file_patch|>.github/workflows/renovate.yml
diff --git a/.github/workflows/renovate.yml b/.github/workflows/renovate.yml
index 9db9dcaa980b72c9f19b36abcbeee9704fa1db5e..bc2476bc75e193b47eb259f92e2c1743913d5886 10... | 107 | code.commit.baseline | band-05 | 779 | 2,936,595,154,055,625,000 | null | null | null | github.com/balena-io/renovate-config | 05 | false | detected_named_ai_or_bot_signal | 2 | yaml | parent_reconstructed | {"clone_url":"https://github.com/balena-io/renovate-config","commit_oid":"44ed343e46536215b70f74d9916d294189513e89","commits_ago_from_head":2383,"content_sha256":"f3c6979d9d5cdc016d54ade25cb2d7a975bf9c8b315dd09f71f40c092d102767","manifest_sha256":null,"parent_oid":"6b1b2290de73e325f21474fca0de860c462b667f","repository_... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/buglabs/dragonfly@77f9a24503c56bcffb5d34e89383daf5d332db99 | <|commit_message|>
com.buglabs.dragonfly: version bump for RC 2.0.12
git-svn-id: svn://bugcamp.net/dragonfly/trunk/com.buglabs.dragonfly.cdt@12246 35ad6e01-222d-0410-b96a-b41bba574936
<|file_patch|>META-INF/MANIFEST.MF
diff --git a/META-INF/MANIFEST.MF b/META-INF/MANIFEST.MF
index c3974fef910da228e50196f53db70122ed54... | 186 | code.commit.baseline | band-06 | 782 | 2,937,453,417,323,808,300 | null | null | null | github.com/buglabs/dragonfly | 06 | false | no_named_signal_detected | 2 | null | parent_reconstructed | {"clone_url":"https://github.com/buglabs/dragonfly","commit_oid":"77f9a24503c56bcffb5d34e89383daf5d332db99","commits_ago_from_head":954,"content_sha256":"7cae1d8cd3fd8b5423887203b5e08459a89f4a1861e48c9ac84650006c0614cf","manifest_sha256":null,"parent_oid":"99c0b3c2ec3e58056ba983048ebf68757b847193","repository_id":"gith... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/apache/dolphinscheduler@c1cad902a986872fd022da6ba3c4628626241cd0 | <|commit_message|>
[Fix-18338] Check task if it's waiting for TaskGroup slot when pause/kill (#18414)
<|file_patch|>dolphinscheduler-dao/src/main/java/org/apache/dolphinscheduler/dao/mapper/TaskGroupQueueMapper.java
diff --git a/dolphinscheduler-dao/src/main/java/org/apache/dolphinscheduler/dao/mapper/TaskGroupQueueMap... | 102 | code.commit.baseline | band-01 | 31,207 | 2,937,957,461,923,882,500 | null | null | null | github.com/apache/dolphinscheduler | 01 | true | no_named_signal_detected | 7 | java | parent_reconstructed | {"clone_url":"https://github.com/apache/dolphinscheduler","commit_oid":"c1cad902a986872fd022da6ba3c4628626241cd0","commits_ago_from_head":8,"content_sha256":"608690e0236f457a51cef981835c5828668513f1901a80f89308632f093df232","manifest_sha256":null,"parent_oid":"1f71cfcbd9f983ccaed48f2ffeb849f7e0eb2fd6","repository_id":"... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":7,"deductions":[],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/octoprint/octoprint@786497d883bc1d3b3d821903119cddeb12d8da15 | <|commit_message|>
ci: add permissions advisor workflow
<|file_patch|>.github/workflows/permissions_advisor.yml
diff --git a/.github/workflows/permissions_advisor.yml b/.github/workflows/permissions_advisor.yml
new file mode 100644
index 0000000000000000000000000000000000000000..b02774f4c1046cac53fd782ebf63c30305cc223... | 57 | code.commit.baseline | band-01 | 1,043 | 2,938,616,952,211,948,500 | null | null | null | github.com/octoprint/octoprint | 01 | false | no_named_signal_detected | 4 | yaml | parent_reconstructed | {"clone_url":"https://github.com/octoprint/octoprint","commit_oid":"786497d883bc1d3b3d821903119cddeb12d8da15","commits_ago_from_head":360,"content_sha256":"80b3f29608f4c80941c11e8aa230bbfb7b8b5d05094831ed3dc0bab967dcdda3","manifest_sha256":null,"parent_oid":"538a072eb8bfe58f6c62f8ac1eb597bcecc5f201","repository_id":"gi... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/awsdocs/aws-doc-sdk-examples@b20415ed0dd2552e3b2a175bdc7426fea23928ec | <|commit_message|>
Added snippet tags and SOS data for EMR examples.
Update README to latest standards.
<|file_patch|>.doc_gen/cross-content/usage_EmrLongLivedCluster_Python_block.xml
diff --git a/.doc_gen/cross-content/usage_EmrLongLivedCluster_Python_block.xml b/.doc_gen/cross-content/usage_EmrLongLivedCluster_Pytho... | 105 | code.commit.baseline | band-01 | 16,986 | 2,939,132,561,811,263,500 | null | null | null | github.com/awsdocs/aws-doc-sdk-examples | 01 | false | no_named_signal_detected | 7 | python | parent_reconstructed | {"clone_url":"https://github.com/awsdocs/aws-doc-sdk-examples","commit_oid":"b20415ed0dd2552e3b2a175bdc7426fea23928ec","commits_ago_from_head":7348,"content_sha256":"dcddda2e3ff74a7070c8360e6f6c5ce8f52186ecf8ffcf0581357c68a0c5297c","manifest_sha256":null,"parent_oid":"87d44f673b8b2e34960e885746bd769b1b62ef3d","reposito... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":7,"deductions":[],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/apache/servicemix3@f983671314ed77cf62114420a15bff38696be8d0 | <|commit_message|>
SM-245: Support URIs to address a JBI exchange and resolution of WS-Addressing EPR
git-svn-id: https://svn.apache.org/repos/asf/incubator/servicemix/trunk@399877 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>servicemix-core/src/main/java/org/apache/servicemix/jbi/resolver/URIResolver.java
diff... | 220 | code.commit.baseline | band-04 | 8,890 | 2,939,265,381,685,374,000 | null | null | null | github.com/apache/servicemix3 | 04 | true | no_named_signal_detected | 3 | java | parent_reconstructed | {"clone_url":"https://github.com/apache/servicemix3","commit_oid":"f983671314ed77cf62114420a15bff38696be8d0","commits_ago_from_head":2128,"content_sha256":"8c3df2079d6ed094c7d032f327a0dfa2dbe9861dfeba965f9f2cd3563bed3615","manifest_sha256":null,"parent_oid":"9bafb87e5ba930ed1409ceaf015c0354710cdc3c","repository_id":"gi... | {"annotations":{"commit_quality_band":"04","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":4},"conventional_commit_type":{... |
commit-doc:github.com/pytorch/tutorials@f1e682ea90391bf1d35f011736b55b62d5b864b4 | <|commit_message|>
Fix typo "asynchronizely" -> "asynchronously" (#1154)
<|file_patch|>intermediate_source/model_parallel_tutorial.py
diff --git a/intermediate_source/model_parallel_tutorial.py b/intermediate_source/model_parallel_tutorial.py
index df43f6fa5f977d8582bf181bda0661339242f94c..62ca66db2bc63d6026fbdeeca1f... | 75 | code.commit.baseline | band-01 | 845 | 2,939,329,353,203,513,000 | null | null | null | github.com/pytorch/tutorials | 01 | false | no_named_signal_detected | 5 | python | parent_reconstructed | {"clone_url":"https://github.com/pytorch/tutorials","commit_oid":"f1e682ea90391bf1d35f011736b55b62d5b864b4","commits_ago_from_head":1592,"content_sha256":"ba6fbfa3d5f9914e8bbc2eda4a63e1651e041ad4f9fcf2f2054690c390937159","manifest_sha256":null,"parent_oid":"cba6b85051c3aa404c9b77d28f4ee9a5b2d38266","repository_id":"git... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/brightdigit/homebrew-speculid@c7d47a867b7f6865ebb3170ad3f634297b9ddaf7 | <|commit_message|>
rtv 1.10.0
Closes #2925.
Signed-off-by: ilovezfs <ilovezfs@icloud.com>
<|file_patch|>Formula/rtv.rb
diff --git a/Formula/rtv.rb b/Formula/rtv.rb
index 8cb36fe75adb9684eee7c1e9118f5b23d9565066..ebcc7e990b25eb0d4ffa0782eaa80b3bea4c4506 100644
--- a/Formula/rtv.rb
+++ b/Formula/rtv.rb
@@ -1,8 +1,8 @@... | 93 | code.commit.baseline | band-10 | 3,828 | 2,939,817,765,686,085,600 | null | null | null | github.com/brightdigit/homebrew-speculid | 10 | false | no_named_signal_detected | 0 | ruby | parent_reconstructed | {"clone_url":"https://github.com/brightdigit/homebrew-speculid","commit_oid":"c7d47a867b7f6865ebb3170ad3f634297b9ddaf7","commits_ago_from_head":7427,"content_sha256":"47d4c0af6fd6c6c7b2dc1c1dccb99d51487cc8c2517c471a1b62cc7f84602a02","manifest_sha256":null,"parent_oid":"6fed7effd0c0b24fd340e6e02a19cbf929371f05","reposit... | {"annotations":{"commit_quality_band":"10","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":10},"conventional_commit_type":... |
commit-doc:github.com/blazemeter/jmeter@0debe40a7f02f3ac194d34b920690dc6678a476d | <|commit_message|>
Add missing svn:eol-style native properties
git-svn-id: https://svn.apache.org/repos/asf/jakarta/jmeter/branches/rel-2-2@522082 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>src/core/org/apache/jmeter/util/Calculator.java
diff --git a/src/core/org/apache/jmeter/util/Calculator.java b/src/core/... | 186 | code.commit.baseline | band-06 | 11,096 | 2,940,006,264,181,042,000 | null | null | null | github.com/blazemeter/jmeter | 06 | false | no_named_signal_detected | 3 | java | parent_reconstructed | {"clone_url":"https://github.com/blazemeter/jmeter","commit_oid":"0debe40a7f02f3ac194d34b920690dc6678a476d","commits_ago_from_head":8469,"content_sha256":"cf5d5e20be97df8c84d9e485d4353d66969c9f565607610ec980dba337586b04","manifest_sha256":null,"parent_oid":"533903bf168f1a5831b774240bcce6a70a397a79","repository_id":"git... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":6},"conventional_commit_type":{... |
commit-doc:github.com/acados/acados@2360c6966f2ed7dcce14fae010927a6a477d8c81 | <|commit_message|>
C: add alignment for d_dense_qp_ipm_arg
<|file_patch|>acados/dense_qp/dense_qp_hpipm.c
diff --git a/acados/dense_qp/dense_qp_hpipm.c b/acados/dense_qp/dense_qp_hpipm.c
index e3fb4c70d82981b812bd3ea2d732a7297898d012..7d2a7820d1a8da3f1f46ef0eb1d07a20d0896311 100644
--- a/acados/dense_qp/dense_qp_hpipm... | 60 | code.commit.baseline | band-02 | 1,342 | 2,940,306,096,767,156,000 | null | null | null | github.com/acados/acados | 02 | false | no_named_signal_detected | 3 | c | parent_reconstructed | {"clone_url":"https://github.com/acados/acados","commit_oid":"2360c6966f2ed7dcce14fae010927a6a477d8c81","commits_ago_from_head":1181,"content_sha256":"b85fb317264cb18b88ba36b88d48129b3783c5b9583ca35658a39fb7e0836f8e","manifest_sha256":null,"parent_oid":"4be3da0de013c9094646dd43d2e1873575d11333","repository_id":"github.... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":2},"conventional_commit_type":{... |
commit-doc:github.com/activestate/openldap@ae47797cc884167529599d884e2bb922cec60ed5 | <|commit_message|>
Send common request controls with extended request.
Only bitch about missing genPassword in success response.
<|file_patch|>clients/tools/ldappasswd.c
diff --git a/clients/tools/ldappasswd.c b/clients/tools/ldappasswd.c
index 36b148de5b038ed6c86e9536b9aa062f111773fe..5d676e399ed6dc703f963825069f5223... | 130 | code.commit.baseline | band-07 | 926 | 2,940,354,076,630,733,300 | null | null | null | github.com/activestate/openldap | 07 | false | no_named_signal_detected | 0 | c | parent_reconstructed | {"clone_url":"https://github.com/activestate/openldap","commit_oid":"ae47797cc884167529599d884e2bb922cec60ed5","commits_ago_from_head":8243,"content_sha256":"808a25ad949b4d662972df5640f58bf5a5dda70ba03cd4520db17a3cd7b9d782","manifest_sha256":null,"parent_oid":"8c4582e29fd098df5c06e7db7147a103d6d73d85","repository_id":"... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":7},"conventional_commit_type":{... |
commit-doc:github.com/fontforge/fontforge@cab04592d6dcf8b3cf3ad59dce9cd5cb07b2a47a | <|commit_message|>
Fixes for misc recent coverity problems (#4032)
* Fixes for Coverity 1407699 1407697 1407696(maybe) 1407695
1407694/1407693 1407691 1407690 1407689
* Add comment explaining ApproximateSplineSetFromGen()
<|file_patch|>fontforge/splinefit.h
diff --git a/fontforge/splinefit.h b/f... | 246 | code.commit.baseline | band-01 | 3,381 | 2,940,636,966,098,401,300 | null | null | null | github.com/fontforge/fontforge | 01 | false | no_named_signal_detected | 3 | c | parent_reconstructed | {"clone_url":"https://github.com/fontforge/fontforge","commit_oid":"cab04592d6dcf8b3cf3ad59dce9cd5cb07b2a47a","commits_ago_from_head":686,"content_sha256":"e0b253cbc1214f9609ea5cc97398fa59b22985db3cd3f69ef81ccb8b37c76947","manifest_sha256":null,"parent_oid":"52716a614e41e2706e91a1a23f1fda987e457af4","repository_id":"gi... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":3,"deductions":[{"points":2,"reason":"most_changed_files_screened_away"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"... |
commit-doc:github.com/apsl/resource-agents@f062838115ff5aa7abe14b445ab542228a39df2d | <|commit_message|>
o continue instead of breaking on errors in scan_inode_list()
o Clear inode's metadata bitmaps when clearing the inode itself
o Make sure the variable you're using for the block number is valid
<|file_patch|>gfs/gfs_fsck/metawalk.c
diff --git a/gfs/gfs_fsck/metawalk.c b/gfs/gfs_fsck/metawalk.c
in... | 217 | code.commit.baseline | band-09 | 7,410 | 2,941,018,158,270,593,500 | null | null | null | github.com/apsl/resource-agents | 09 | false | no_named_signal_detected | 0 | c | parent_reconstructed | {"clone_url":"https://github.com/apsl/resource-agents","commit_oid":"f062838115ff5aa7abe14b445ab542228a39df2d","commits_ago_from_head":5516,"content_sha256":"3d21f5309deacf7b858d4cb73b7871b49d4355376ddd4ad3e77553bfda5cb013","manifest_sha256":null,"parent_oid":"6609c3599da9ce6bfb171c7dd709487d64a4456a","repository_id":"... | {"annotations":{"commit_quality_band":"09","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/doctrine/orm@8afb644a185064200c222ce02fe731a5353b757f | <|commit_message|>
Ignore PropertyNotSetInConstructor (#10218)
Inside the Query\AST namespace, many classes use public properties that
are supposed to be set from outside the class. Let us ignore
PropertyNotSetInConstructor for that entire namespace instead of doing
it on a case by case basis.
<|file_patch|>psalm.x... | 299 | code.commit.baseline | band-01 | 915 | 2,941,194,555,240,346,600 | null | null | null | github.com/doctrine/orm | 01 | false | no_named_signal_detected | 9 | null | parent_reconstructed | {"clone_url":"https://github.com/doctrine/orm","commit_oid":"8afb644a185064200c222ce02fe731a5353b757f","commits_ago_from_head":2139,"content_sha256":"636add35beacebf1698c85083dbe4511311b4fb0390bbc60f110002f6f2117bb","manifest_sha256":null,"parent_oid":"953e42d0591bf4982881d970b68ac70d1be40660","repository_id":"github.c... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":9,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":11,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000"... |
commit-doc:github.com/500px/homebrew-core@648efa90f79b74fbd02ca68241d38e2c1065c353 | <|commit_message|>
caf: update 0.17.0 bottle.
<|file_patch|>Formula/caf.rb
diff --git a/Formula/caf.rb b/Formula/caf.rb
index 8c200ac5aa90e26b43b19b0b97110e5373a99bc2..ce75badc39b742dbbe6cad6797b14f1d4c5092d6 100644
--- a/Formula/caf.rb
+++ b/Formula/caf.rb
@@ -8,9 +8,9 @@ class Caf < Formula
bottle do
cella... | 47 | code.commit.baseline | band-07 | 919 | 2,941,627,705,641,258,500 | null | null | null | github.com/500px/homebrew-core | 07 | false | detected_named_ai_or_bot_signal | 0 | ruby | parent_reconstructed | {"clone_url":"https://github.com/500px/homebrew-core","commit_oid":"648efa90f79b74fbd02ca68241d38e2c1065c353","commits_ago_from_head":1924,"content_sha256":"4b2d8c257f197a6e2971f3c3c7c29d5224280c84780b65d957eb6cd1b9676c17","manifest_sha256":null,"parent_oid":"b6a58ef70d4e127ac0de786a734f75049119db0c","repository_id":"g... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":7},"conventional_commit_type":{... |
commit-doc:github.com/apache/cordova-lib@546612060bdab16ea88ed3a6e3ee8c1f29ffab3d | <|commit_message|>
CB-12787: Fix plugin installation with --link option
This closes #557
<|file_patch|>cordova-fetch/index.js
diff --git a/cordova-fetch/index.js b/cordova-fetch/index.js
index 21c2f421d9b9aa97176ced52ee742c1d5d7c737e..3ef0bf0ad874d2e8cc088c7571fa504f025d7884 100644
--- a/cordova-fetch/index.js
+++ b... | 92 | code.commit.baseline | band-03 | 2,257 | 2,941,702,790,313,920,000 | null | null | null | github.com/apache/cordova-lib | 03 | false | no_named_signal_detected | 3 | javascript | parent_reconstructed | {"clone_url":"https://github.com/apache/cordova-lib","commit_oid":"546612060bdab16ea88ed3a6e3ee8c1f29ffab3d","commits_ago_from_head":596,"content_sha256":"7dbae78397a4f1bd792f578c385ffffb2ac746b26345f515b995b5754a71c066","manifest_sha256":null,"parent_oid":"a7b5433f47f09546a8024948d0d8935281e944de","repository_id":"git... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/composer/package-versions-deprecated@7dea49e89fbe98c310fbfacb82e376e3fcd238bb | <|commit_message|>
Remove double registration of the event listeners
Composer already registers listeners when the plugin class implements EventSubscriberInterface
<|file_patch|>src/PackageVersions/Installer.php
diff --git a/src/PackageVersions/Installer.php b/src/PackageVersions/Installer.php
index 6d6dfcf976e65ec9b... | 166 | code.commit.baseline | band-01 | 2,031 | 2,941,797,367,632,614,000 | null | null | null | github.com/composer/package-versions-deprecated | 01 | true | no_named_signal_detected | 4 | php | parent_reconstructed | {"clone_url":"https://github.com/composer/package-versions-deprecated","commit_oid":"7dea49e89fbe98c310fbfacb82e376e3fcd238bb","commits_ago_from_head":234,"content_sha256":"8cd6ca1f5fe9ecfaecf1ebb43626bd6ac8969e9a465e8dd18136215c13d4aaca","manifest_sha256":null,"parent_oid":"b300ac2022f793a1ed92a79942566f8f9af1d40c","r... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/rt-thread/rt-thread@98a997c57eeefcd8c8941ff144e817125a2f720c | <|commit_message|>
[bsp]add new bsp-bl808 (#6824)
* add new bsp-bl808
* support ARCH_RISCV_FPU_S && update rtconfig.py
<|file_patch|>bsp/bl808/README.md
diff --git a/bsp/bl808/README.md b/bsp/bl808/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..64f2aa0d98b7840035ef07d7dc9b9fb1ea7ba01... | 123 | code.commit.baseline | band-01 | 13,397,047 | 2,941,986,714,935,408,000 | null | null | null | github.com/rt-thread/rt-thread | 01 | true | no_named_signal_detected | 1 | c | parent_reconstructed | {"clone_url":"https://github.com/rt-thread/rt-thread","commit_oid":"98a997c57eeefcd8c8941ff144e817125a2f720c","commits_ago_from_head":3688,"content_sha256":"d2caf3381fd6bf384a17e4fe848a5a1224bdc574de89059de5e8ea80653e61a9","manifest_sha256":null,"parent_oid":"3dffc78f3958f40577be44b93231402e04186b7f","repository_id":"g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":1,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":3,"reason":"candidate_cap_rungs_exceeded"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_... |
commit-doc:github.com/apify/apify-cli@eeca37df62461a0ca1fa6f2f72386b18eb65a077 | <|commit_message|>
fix: windows and python compatibility (#786)
<|file_patch|>src/lib/exec.ts
diff --git a/src/lib/exec.ts b/src/lib/exec.ts
index 88e1507b56d0a09dab9506278809efd606ff6614..425e65ebe205bc36a84b0cf5cfd5825a49ed5ab7 100644
--- a/src/lib/exec.ts
+++ b/src/lib/exec.ts
@@ -2,6 +2,7 @@ import { type SpawnOp... | 66 | code.commit.baseline | band-04 | 9,588 | 2,942,070,964,995,831,300 | null | null | null | github.com/apify/apify-cli | 04 | false | no_named_signal_detected | 3 | typescript | parent_reconstructed | {"clone_url":"https://github.com/apify/apify-cli","commit_oid":"eeca37df62461a0ca1fa6f2f72386b18eb65a077","commits_ago_from_head":589,"content_sha256":"6cb68458f0aa580cf58236a2d59d82e0f2fb537a517eb7ca60c9ff95d9aacfa7","manifest_sha256":null,"parent_oid":"d46ea671318e98fa00891bedaf6a5160e5efd602","repository_id":"github... | {"annotations":{"commit_quality_band":"04","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":4},"conventional_commit_type":{... |
commit-doc:github.com/activestate/lactate@9d070f5f74021821b92d2920fb1220a04d14dea6 | <|commit_message|>
Add opts.gzip_patterns
<|file_patch|>lib/lactate.js
diff --git a/lib/lactate.js b/lib/lactate.js
index c80bd23702dab8bb806749c3f5bf1f46a48c6db6..8dccbbdbd2af6220acc9830e1495507b3db5b6ef 100644
--- a/lib/lactate.js
+++ b/lib/lactate.js
@@ -57,24 +57,22 @@ function Lactate(options) {
, error_page... | 43 | code.commit.baseline | band-02 | 1,344 | 2,942,179,598,269,896,700 | null | null | null | github.com/activestate/lactate | 02 | false | no_named_signal_detected | 1 | javascript | parent_reconstructed | {"clone_url":"https://github.com/activestate/lactate","commit_oid":"9d070f5f74021821b92d2920fb1220a04d14dea6","commits_ago_from_head":80,"content_sha256":"2d08fbbc059f0ab3edcc5c5fc6220215d521676860bd6336c107d460ce756324","manifest_sha256":null,"parent_oid":"99a8b52414ac2e45d513d12452d931153ebe0bbf","repository_id":"git... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":1,"deductions":[{"points":2,"reason":"throwaway_message"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version"... |
commit-doc:github.com/alleninstitute/poco@7f17255ed8a0f90681a05249bc5f7566ae277009 | <|commit_message|>
Add unit test for opening/closing RemoteSyslogChannel
<|file_patch|>Net/src/RemoteSyslogChannel.cpp
diff --git a/Net/src/RemoteSyslogChannel.cpp b/Net/src/RemoteSyslogChannel.cpp
index a33aefd6ad744221dc107775787dc3c2e973e714..37e32153bd011b643f297aa38463f6c9efc129cf 100644
--- a/Net/src/RemoteSyslo... | 74 | code.commit.baseline | band-03 | 3,328 | 2,942,786,076,754,348,000 | null | null | null | github.com/alleninstitute/poco | 03 | false | no_named_signal_detected | 3 | cpp | parent_reconstructed | {"clone_url":"https://github.com/alleninstitute/poco","commit_oid":"7f17255ed8a0f90681a05249bc5f7566ae277009","commits_ago_from_head":2946,"content_sha256":"fbce8b0447a817a842d17458158a76607746acf89a785e939b75106051ca426e","manifest_sha256":null,"parent_oid":"a9284393b04e58da096520454ee2a91e6eb28b1d","repository_id":"g... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/bigmlcom/presto@74d73f1539828524506fccd2ca09e7634fe8f892 | <|commit_message|>
Zero out the progress update (bytes and rows per second) for completed stages
<|file_patch|>presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java
diff --git a/presto-main/src/main/java/com/facebook/presto/cli/StatusPrinter.java b/presto-main/src/main/java/com/facebook/presto/cli/Statu... | 98 | code.commit.baseline | band-05 | 2,524 | 2,942,787,312,829,966,000 | null | null | null | github.com/bigmlcom/presto | 05 | false | no_named_signal_detected | 3 | java | parent_reconstructed | {"clone_url":"https://github.com/bigmlcom/presto","commit_oid":"74d73f1539828524506fccd2ca09e7634fe8f892","commits_ago_from_head":1266,"content_sha256":"575e4993034f47c155c7f9580674a5884d811138b98463683f674e99781ae260","manifest_sha256":null,"parent_oid":"c8e5230e8194fe6517fbc93f1f4d5e999bbc58a8","repository_id":"githu... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":5},"conventional_commit_type":{... |
commit-doc:github.com/angular/platform-browser-builds@e5b624432c05aadda06c58e95c399737eaaa5cf3 | <|commit_message|>
141f310 refactor(core): standalone by default for JIT compiled directives (#58236)
<|file_patch|>BUILD_INFO
diff --git a/BUILD_INFO b/BUILD_INFO
index 1612c97bc3b95cd8f2ecf6d91e2a9fc444ea7c70..3dc958bf4ce48c65fbccfc73546e6c9a561083b0 100644
--- a/BUILD_INFO
+++ b/BUILD_INFO
@@ -1,2 +1,2 @@
-Thu Oct... | 104 | code.commit.baseline | band-03 | 11,354 | 2,942,804,481,662,880,000 | null | null | null | github.com/angular/platform-browser-builds | 03 | false | no_named_signal_detected | 1 | javascript | parent_reconstructed | {"clone_url":"https://github.com/angular/platform-browser-builds","commit_oid":"e5b624432c05aadda06c58e95c399737eaaa5cf3","commits_ago_from_head":2760,"content_sha256":"4e70450c0ad444e6bf47e583f557cc6183284591d73cb77365a997cdcbd57529","manifest_sha256":null,"parent_oid":"40ee0ad43bbecd253c88f6c6065b1608a5609ebf","repos... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":1,"deductions":[{"points":2,"reason":"most_changed_files_screened_away"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"... |
commit-doc:github.com/bavix/babichev-html@166da5f4718687b3346c70560a73982b028108ab | <|commit_message|>
Create builder.yaml
Signed-off-by: Maxim Babichev <maksim.babichev95@gmail.com>
<|file_patch|>.github/workflows/builder.yaml
diff --git a/.github/workflows/builder.yaml b/.github/workflows/builder.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..0f35111db22178ad7b031b4825b00... | 100 | code.commit.baseline | band-09 | 2,210 | 2,942,853,982,750,448,000 | null | null | null | github.com/bavix/babichev-html | 09 | false | no_named_signal_detected | 0 | yaml | parent_reconstructed | {"clone_url":"https://github.com/bavix/babichev-html","commit_oid":"166da5f4718687b3346c70560a73982b028108ab","commits_ago_from_head":27,"content_sha256":"3146df5e1ffdb0bbe9a0e0e49f930520702f982585d6cdcd3b44f9871928493a","manifest_sha256":null,"parent_oid":"66160093910fc938d9e04acb3887f74c94533d59","repository_id":"git... | {"annotations":{"commit_quality_band":"09","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/acemod/ace3@59b9e9a7df79cb3575a2af71761f205ff93efbf3 | <|commit_message|>
Missing periods added.
<|file_patch|>addons/map_gestures/stringtable.xml
diff --git a/addons/map_gestures/stringtable.xml b/addons/map_gestures/stringtable.xml
index 9c61d59292d89d4bc06a9a781ee1b9f57370ce61..0118b4323e5d253a1a6d698e0b3e90b87e6162f3 100644
--- a/addons/map_gestures/stringtable.xml
+++... | 42 | code.commit.baseline | band-07 | 4,632 | 2,943,249,804,567,464,400 | null | null | null | github.com/acemod/ace3 | 07 | false | no_named_signal_detected | 0 | null | parent_reconstructed | {"clone_url":"https://github.com/acemod/ace3","commit_oid":"59b9e9a7df79cb3575a2af71761f205ff93efbf3","commits_ago_from_head":8685,"content_sha256":"8176215a6d36e7bceba0f9f6636d27bb1ff94f1cbf524d74d388779f7e830ba4","manifest_sha256":null,"parent_oid":"e2763dde2738d9854316bd6851490a51c201a210","repository_id":"github.co... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/huggingface/accelerate@3fcc9461c4fcb7228df5e5246809ba09cfbb232e | <|commit_message|>
Do not import `transformer_engine` on import (#3056)
* Do not import `transformer_engine` on import
* fix message
* add test
* Update test_imports.py
* resolve comment 1/2
* resolve comment 1.5/2
* lint
* more lint
* Update tests/test_imports.py
Co-authored-by: Zach Muelle... | 420 | code.commit.baseline | band-01 | 4,755 | 2,943,337,581,124,524,500 | null | null | null | github.com/huggingface/accelerate | 01 | true | no_named_signal_detected | 11 | python | parent_reconstructed | {"clone_url":"https://github.com/huggingface/accelerate","commit_oid":"3fcc9461c4fcb7228df5e5246809ba09cfbb232e","commits_ago_from_head":458,"content_sha256":"ef6826cd9f46c0ff51e386c985442dd3f0171945e2a9290fc8fe9fc00d94a6af","manifest_sha256":null,"parent_oid":"939ce400cbc0478fd281b9fcc9a2a85691ba9f7d","repository_id":... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":11,"deductions":[],"repo_score":11,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type"... |
commit-doc:github.com/mcollina/autocannon@7674dec8486858501612f63dee7ceb7d60a2f922 | <|commit_message|>
bumped v0.9.1.
<|file_patch|>package.json
diff --git a/package.json b/package.json
index fa3600404adcd011a0ab92cd0c3d55e046d77e7c..a527ea6536aef279be0a319e29f6ee5429f65035 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "autocannon",
- "version": "0.9.0",
+ "version": "0... | 35 | code.commit.baseline | band-01 | 436 | 2,943,395,866,838,017,500 | null | null | null | github.com/mcollina/autocannon | 01 | false | no_named_signal_detected | 2 | json | parent_reconstructed | {"clone_url":"https://github.com/mcollina/autocannon","commit_oid":"7674dec8486858501612f63dee7ceb7d60a2f922","commits_ago_from_head":523,"content_sha256":"c0ed638b96d997400e8913966ad46c2c99bc265221320ba8c1187c64f2829970","manifest_sha256":null,"parent_oid":"d861dd00161808526d206a5a11337fc0860865f4","repository_id":"gi... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":2,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/algolia/npm-search@947058d273bce51103cb117a1f1a25c1d34bacb1 | <|commit_message|>
fix: docker build (#651)
<|file_patch|>.circleci/config.yml
diff --git a/.circleci/config.yml b/.circleci/config.yml
index 3465a4aab565a4614e4e15824555668aa90344b4..8d2703df6c0acb3ba9b0dead445b8096d79559a2 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -51,6 +51,10 @@ jobs:
wo... | 46 | code.commit.baseline | band-03 | 942 | 2,943,692,781,184,088,600 | null | null | null | github.com/algolia/npm-search | 03 | false | no_named_signal_detected | 3 | dockerfile | parent_reconstructed | {"clone_url":"https://github.com/algolia/npm-search","commit_oid":"947058d273bce51103cb117a1f1a25c1d34bacb1","commits_ago_from_head":433,"content_sha256":"932a48c8d195baf7de2e49a790a4078d5ab33a3369380e9c91b776f30f9b6268","manifest_sha256":null,"parent_oid":"95587a31832655a98d3de9038e137112f9b51418","repository_id":"git... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/actiontech/tidb@01f132ed39a8c1fc9775d963c7b0b50415f7d024 | <|commit_message|>
stats: fix bug when estimating row count for outdated histograms (#5552)
<|file_patch|>plan/cbo_test.go
diff --git a/plan/cbo_test.go b/plan/cbo_test.go
index fba76a76d33353dc013703f2e518a4006d748ff7..0219cb6433edb037a5105834aa3e832a2d478835 100644
--- a/plan/cbo_test.go
+++ b/plan/cbo_test.go
@@... | 96 | code.commit.baseline | band-07 | 5,875 | 2,943,753,167,465,780,000 | null | null | null | github.com/actiontech/tidb | 07 | false | no_named_signal_detected | 0 | go | parent_reconstructed | {"clone_url":"https://github.com/actiontech/tidb","commit_oid":"01f132ed39a8c1fc9775d963c7b0b50415f7d024","commits_ago_from_head":6173,"content_sha256":"f49ac290b5d45eea435263212d0f3f15bf53a51eef89aa57ce06f303edf0a6bf","manifest_sha256":null,"parent_oid":"f744c777de06cbc744cb19da17cdec5bd2b1ba86","repository_id":"githu... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":7},"conventional_commit_type":{... |
commit-doc:github.com/jruby/jruby-openssl@c7cd35d0deccb005e623706b78ac935de8667bf1 | <|commit_message|>
load correct openssl .rb files on Ruby 2.3
<|file_patch|>lib/openssl/bn.rb
diff --git a/lib/openssl/bn.rb b/lib/openssl/bn.rb
index 599374189b5ea1793c3c70f6d414cff658e8385f..da1c6653ef516e726cc6e5431e3415cf9d843872 100644
--- a/lib/openssl/bn.rb
+++ b/lib/openssl/bn.rb
@@ -1,4 +1,6 @@
-if RUBY_VERSIO... | 62 | code.commit.baseline | band-01 | 6,303 | 2,943,832,561,429,705,000 | null | null | null | github.com/jruby/jruby-openssl | 01 | false | no_named_signal_detected | 4 | ruby | parent_reconstructed | {"clone_url":"https://github.com/jruby/jruby-openssl","commit_oid":"c7cd35d0deccb005e623706b78ac935de8667bf1","commits_ago_from_head":1150,"content_sha256":"72ce3a96f3901b4bd77dc13459bd748982ea3316d35a3e07e3d5c4d99f6fbbb2","manifest_sha256":null,"parent_oid":"12a79807590875986a504f50c014a68e0ee66738","repository_id":"g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/apachecn/activiti@605847be0add73c1f9cbe584a2759b0755071cf9 | <|commit_message|>
Updated documentation
<|file_patch|>modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java
diff --git a/modules/activiti-webapp-explorer2/src/main/java/org/activiti/explorer/conf/ActivitiEngineConfiguration.java b/modules/activiti-webapp-explorer2... | 42 | code.commit.baseline | band-08 | 16,123 | 2,943,918,222,664,260,000 | null | null | null | github.com/apachecn/activiti | 08 | false | no_named_signal_detected | 0 | java | parent_reconstructed | {"clone_url":"https://github.com/apachecn/activiti","commit_oid":"605847be0add73c1f9cbe584a2759b0755071cf9","commits_ago_from_head":5514,"content_sha256":"5f7cc7f10fce90080a0d9e81d7a2158f93eafaca0afd530db2500dc48cfff8e4","manifest_sha256":null,"parent_oid":"b8f3c372cb08d4dd72c9222bc3bd6f33137df2dd","repository_id":"git... | {"annotations":{"commit_quality_band":"08","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"ro... |
commit-doc:github.com/open-telemetry/opentelemetry-go@3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c | <|commit_message|>
Provide conformance tests for tracers (#191)
* Provide conformance tests for tracers
The test harness may be used to ensure that a given tracer behaves
according to the expectations set by the API.
* Add `ToMatchError` matcher
* Use DeepEqual to compare unknown types in matchers
Unlike ... | 476 | code.commit.baseline | band-01 | 16,314 | 2,944,133,273,935,530,500 | null | null | null | github.com/open-telemetry/opentelemetry-go | 01 | false | no_named_signal_detected | 4 | go | parent_reconstructed | {"clone_url":"https://github.com/open-telemetry/opentelemetry-go","commit_oid":"3a9c80c56fb23bbc92af52aa3e5afea5c11f2d1c","commits_ago_from_head":4831,"content_sha256":"0490a81dfa7750e7c5d0155754b06261a5f34c2f138233716cc48efc3c2f9243","manifest_sha256":null,"parent_oid":"11bdacf7b9201e6dd878f0bd902c9d4e7fdb94ec","repos... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/bloomberg/lucene-solr@a127d61d70d88d3a941613574f40ae310dfb6760 | <|commit_message|>
SOLR-1301: Add some readme files.
git-svn-id: https://svn.apache.org/repos/asf/lucene/dev/trunk@1568317 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>solr/contrib/map-reduce/README.txt
diff --git a/solr/contrib/map-reduce/README.txt b/solr/contrib/map-reduce/README.txt
new file mode 100644
ind... | 162 | code.commit.baseline | band-06 | 2,501 | 2,944,144,248,323,368,400 | null | null | null | github.com/bloomberg/lucene-solr | 06 | false | no_named_signal_detected | 2 | null | parent_reconstructed | {"clone_url":"https://github.com/bloomberg/lucene-solr","commit_oid":"a127d61d70d88d3a941613574f40ae310dfb6760","commits_ago_from_head":8188,"content_sha256":"7c303279f77bb6d5f5b75461a27f1e6f9413ff96ae15b638206328493b306110","manifest_sha256":null,"parent_oid":"f378045b2cbdea1b394543a6007f6a55696c0b78","repository_id":... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/opendronemap/odm@32322161ebbc94303a3cf3752e637fd142f25d8b | <|commit_message|>
full removal of smvs
Former-commit-id: ae3221aa8b04a376b278176e76f106ed634659d6
<|file_patch|>README.md
diff --git a/README.md b/README.md
index 98d4f0a6978169b8b057a3c46f87ec0233e10dd6..1515a69d0116091d8c35aceef79412e6ee7186e4 100644
--- a/README.md
+++ b/README.md
@@ -199,7 +199,7 @@ If you want ... | 101 | code.commit.baseline | band-01 | 4,424 | 2,944,231,836,854,587,000 | null | null | null | github.com/opendronemap/odm | 01 | false | no_named_signal_detected | 5 | markdown | parent_reconstructed | {"clone_url":"https://github.com/opendronemap/odm","commit_oid":"32322161ebbc94303a3cf3752e637fd142f25d8b","commits_ago_from_head":2131,"content_sha256":"15ec1009ecc3154abac54893f80db121a35413eae1bb856a84aa23da55108215","manifest_sha256":null,"parent_oid":"e923bae976d5bd50009bcb2319278fd110e83cd2","repository_id":"gith... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/httpie/cli@266c6375c6d687c3aad07962cb3f5bef7d39bbbf | <|commit_message|>
Release prep for 3.1.0 (#1313)
<|file_patch|>CHANGELOG.md
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 7ecf797d29bac47d64331b438e9492d14ad19d6e..764c1738c5963e2714e55b22f69d8b8982b5192a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -3,15 +3,17 @@
This document records all notable changes to [H... | 52 | code.commit.baseline | band-01 | 2,784 | 2,944,395,558,987,584,500 | null | null | null | github.com/httpie/cli | 01 | false | no_named_signal_detected | 12 | markdown | parent_reconstructed | {"clone_url":"https://github.com/httpie/cli","commit_oid":"266c6375c6d687c3aad07962cb3f5bef7d39bbbf","commits_ago_from_head":130,"content_sha256":"ad160d239a03900642d157b1fff17107fef474c184fec128585de2e17c613bb3","manifest_sha256":null,"parent_oid":"77af4c7a5cb3d0b3e813c7f678099014c94ff6aa","repository_id":"github.com/... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":12,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":13,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":2,"route_language_to... |
commit-doc:github.com/hechoendrupal/drupal-console@1bc213bfd2b5c1ab5723575a68574cb08e59ef2c | <|commit_message|>
Update Beta version 11 to 12
<|file_patch|>README.md
diff --git a/README.md b/README.md
index de0fd2390f8a212ec1ef0adbfcb3ab777a110906..b7f31cb4c303eb48fa3382a1491201dee3629bb6 100644
--- a/README.md
+++ b/README.md
@@ -24,13 +24,14 @@ The Drupal Console is a suite of tools that you run on a command... | 49 | code.commit.baseline | band-01 | 1,339 | 2,944,457,470,363,904,500 | null | null | null | github.com/hechoendrupal/drupal-console | 01 | false | no_named_signal_detected | 3 | markdown | parent_reconstructed | {"clone_url":"https://github.com/hechoendrupal/drupal-console","commit_oid":"1bc213bfd2b5c1ab5723575a68574cb08e59ef2c","commits_ago_from_head":4719,"content_sha256":"2dc477c1bd46f816530419fbf64d1472a6739c59e5b802dea026939ca1db4b0f","manifest_sha256":null,"parent_oid":"78c9dd0a97548577de744c3e5dd4f75fe317fd9c","reposito... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":3,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/kovidgoyal/kitty@ac4c12b3e1911805147244d0e69749b568e8d8c4 | <|commit_message|>
Add variable sized text to the list of things multiplexers break
<|file_patch|>docs/faq.rst
diff --git a/docs/faq.rst b/docs/faq.rst
index b7419461a456addc8122581ee1a4c9981b13183c..8c059d8e4de481c515c912e9e2765200ea98ad9e 100644
--- a/docs/faq.rst
+++ b/docs/faq.rst
@@ -504,9 +504,10 @@ for tmux ref... | 85 | code.commit.baseline | band-01 | 1,106 | 2,944,486,484,824,845,300 | null | null | null | github.com/kovidgoyal/kitty | 01 | false | no_named_signal_detected | 6 | null | parent_reconstructed | {"clone_url":"https://github.com/kovidgoyal/kitty","commit_oid":"ac4c12b3e1911805147244d0e69749b568e8d8c4","commits_ago_from_head":3568,"content_sha256":"952835d5ed00ec52d67bde23e5c8c6a7c1fc300a5bf9460df7f952aaa9b0d1a0","manifest_sha256":null,"parent_oid":"2c078d9d6f255343434d7ec243ab40ac3e2b224f","repository_id":"gith... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":6,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/jenkinsci/jenkins@bd90608a6fef0459d48483bf6652e9097e9ef277 | <|commit_message|>
Update jenkins/ath Docker tag to v6059 (#9914)
Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
<|file_patch|>ath.sh
diff --git a/ath.sh b/ath.sh
index d57b7834ee32e40561a4201328946b9945e5d9f9..c3a56d5fe4f8e463ff68e16e7683aa6db7e6fca6 100644
--- a/ath.sh
+++ b/ath.sh
@... | 147 | code.commit.baseline | band-01 | 564 | 2,944,541,359,124,120,000 | null | null | null | github.com/jenkinsci/jenkins | 01 | false | detected_named_ai_or_bot_signal | 9 | shell | parent_reconstructed | {"clone_url":"https://github.com/jenkinsci/jenkins","commit_oid":"bd90608a6fef0459d48483bf6652e9097e9ef277","commits_ago_from_head":3022,"content_sha256":"6b25082bd81b72cd6a165d684d1d7a9669b2a0be016d9f5ae239f7e92bd5728b","manifest_sha256":null,"parent_oid":"6c0422fcda13ab5bad51a5075a81de1ede4398b4","repository_id":"git... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":9,"deductions":[],"repo_score":9,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/love2d/love@c8f549490026aa35a7b48b4c6068da614000e93b | <|commit_message|>
Images, Canvases, Quads, and Fonts now have the same vertex winding order
<|file_patch|>src/modules/graphics/opengl/Canvas.cpp
diff --git a/src/modules/graphics/opengl/Canvas.cpp b/src/modules/graphics/opengl/Canvas.cpp
index a5900e7ed21bc7b90ded0e115c854acbf2e2e8d1..0aa4b61cb0c1ab408664d056d5ecf592... | 94 | code.commit.baseline | band-01 | 2,230 | 2,944,782,922,418,843,000 | null | null | null | github.com/love2d/love | 01 | false | no_named_signal_detected | 5 | cpp | parent_reconstructed | {"clone_url":"https://github.com/love2d/love","commit_oid":"c8f549490026aa35a7b48b4c6068da614000e93b","commits_ago_from_head":3932,"content_sha256":"109f5a858b7d7768d3cc36fca366b3d98b8b01f09019991e3ca98eb075fdea03","manifest_sha256":null,"parent_oid":"5179ca5655eec9c1a7947d5303346fc9db1723ed","repository_id":"github.co... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/acquia/travis.rb@ddc2e9801dc7f91182ab53be464814c64886bba9 | <|commit_message|>
Add cloudControl setup
<|file_patch|>completion/travis.sh
diff --git a/completion/travis.sh b/completion/travis.sh
index ac3840f06e743aeaaf7f3fed708db49017f90694..96b816ad7353c20cc6df4a43cd498853a4d870f9 100644
--- a/completion/travis.sh
+++ b/completion/travis.sh
@@ -478,6 +478,7 @@ nodejitsu
sauc... | 43 | code.commit.baseline | band-07 | 2,821 | 2,944,981,629,566,764,500 | null | null | null | github.com/acquia/travis.rb | 07 | false | no_named_signal_detected | 0 | ruby | parent_reconstructed | {"clone_url":"https://github.com/acquia/travis.rb","commit_oid":"ddc2e9801dc7f91182ab53be464814c64886bba9","commits_ago_from_head":843,"content_sha256":"953c39dfb62d6df25aca79b47a086e010d3bc0c18e12a027ba029cec762a3ba6","manifest_sha256":null,"parent_oid":"34b9aa888799411b2145cd53fa88d89a532f86c8","repository_id":"githu... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"ro... |
commit-doc:github.com/bartoszcichecki/lenovolegiontoolkit@599b66c89920bb38a4f0382a6573b659455bab99 | <|commit_message|>
Moved to newtonsoft json
<|file_patch|>LenovoLegionToolkit.Lib/Structs.cs
diff --git a/LenovoLegionToolkit.Lib/Structs.cs b/LenovoLegionToolkit.Lib/Structs.cs
index b2a3148ea208c01370d4eb58ad6e7970f63c25a6..fe41815d54c87e99331e7237733f292ad3df3114 100644
--- a/LenovoLegionToolkit.Lib/Structs.cs
+++ ... | 45 | code.commit.baseline | band-01 | 748 | 2,945,155,192,098,500,000 | null | null | null | github.com/bartoszcichecki/lenovolegiontoolkit | 01 | false | no_named_signal_detected | 5 | csharp | parent_reconstructed | {"clone_url":"https://github.com/bartoszcichecki/lenovolegiontoolkit","commit_oid":"599b66c89920bb38a4f0382a6573b659455bab99","commits_ago_from_head":2453,"content_sha256":"83403a4753382e79027a50c5d0b5c76f397026715c40a694eb19da6c8b5a1d28","manifest_sha256":null,"parent_oid":"b6a5c0c48b7bd7546b3a932449381426406f9246","r... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/altschool/ember-basic-dropdown@928ef8e9f987949424180be22f5c479da53d30c3 | <|commit_message|>
Released v0.12.0-beta.2
<|file_patch|>CHANGELOG.md
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8f1b2e676aaa76bd27c89190e6314cba1baff66e..0a015e2bb9ce100204743820b8f0fbe4cfaddcde 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,3 +1,8 @@
+# 0.12-beta.2
+
+- [BUGFIX] Focus the trigger when the co... | 44 | code.commit.baseline | band-03 | 981 | 2,945,169,799,199,484,000 | null | null | null | github.com/altschool/ember-basic-dropdown | 03 | false | no_named_signal_detected | 0 | json | parent_reconstructed | {"clone_url":"https://github.com/altschool/ember-basic-dropdown","commit_oid":"928ef8e9f987949424180be22f5c479da53d30c3","commits_ago_from_head":227,"content_sha256":"be4d9c4e78d6f5fa87e5fd534253e0db5f2f3fb2c9fb4c1f34fc39072d06a404","manifest_sha256":null,"parent_oid":"1c1073cc926873cbe7efa838c991bb3866b35695","reposit... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/arduino/lmp-manifest@d0aed4d00f1f1ac463f13c1fcc99caa4faed7cc8 | <|commit_message|>
lmp-base: update meta-lmp layer
Relevant changes:
- e9290895 base: lmp: sota: build and deploy ota-ext4.gz
- 69d430da base: lmp: reduce IMAGE_FSTYPES options
- c926e26d base: non-clangable: drop cboot
- f033a6bc bsp: lmp-machine-custom: tegra: move back to l4tlauncher
- 8b939908 bsp: tegra: edk2-fir... | 990 | code.commit.baseline | band-09 | 1,938 | 2,945,570,276,882,106,000 | null | null | null | github.com/arduino/lmp-manifest | 09 | false | no_named_signal_detected | 0 | null | parent_reconstructed | {"clone_url":"https://github.com/arduino/lmp-manifest","commit_oid":"d0aed4d00f1f1ac463f13c1fcc99caa4faed7cc8","commits_ago_from_head":660,"content_sha256":"87bcf906deeb7c7e8ec06566d8c32bcee666c4458dd83ea77a203e99025c350a","manifest_sha256":null,"parent_oid":"dc9871d6e3301233d0dc6931833fd7d7d501551a","repository_id":"g... | {"annotations":{"commit_quality_band":"09","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/moment/moment@4211bfc8f15746be4019bba557e29a7ba83d54c5 | <|commit_message|>
[bugfix] Avoid loading path-looking locales from fs
<|file_patch|>src/lib/locale/locales.js
diff --git a/src/lib/locale/locales.js b/src/lib/locale/locales.js
index 0d082327545c67c3f872b348aab64d8397d896e1..b329b83b3a335a696a81b6a0c858cd81e31fc42e 100644
--- a/src/lib/locale/locales.js
+++ b/src/lib... | 72 | code.commit.baseline | band-01 | 966 | 2,945,584,426,554,025,000 | null | null | null | github.com/moment/moment | 01 | false | no_named_signal_detected | 13 | javascript | parent_reconstructed | {"clone_url":"https://github.com/moment/moment","commit_oid":"4211bfc8f15746be4019bba557e29a7ba83d54c5","commits_ago_from_head":129,"content_sha256":"e19c82dabd79d93392c579200dfde2a07c19be865fb321b8173ef9255425192e","manifest_sha256":null,"parent_oid":"f2a813afcfd0dd6e63812ea74c46ecc627f6a6a6","repository_id":"github.c... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":13,"deductions":[],"repo_score":13,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type"... |
commit-doc:github.com/lokathor/bytemuck@93d8e53509d4973de8a624e27ebb89cb60405d03 | <|commit_message|>
Update changelog.md
<|file_patch|>changelog.md
diff --git a/changelog.md b/changelog.md
index d9a35d2a20fb39b08b7016783672e8cd5d41d79a..4b75c7db1b7a449a65f135abca3741423bf34ea7 100644
--- a/changelog.md
+++ b/changelog.md
@@ -5,9 +5,6 @@
* [Kimundi](https://github.com/Kimundi) fixed an issue that co... | 39 | code.commit.baseline | band-01 | 738 | 2,945,652,484,449,588,700 | null | null | null | github.com/lokathor/bytemuck | 01 | false | no_named_signal_detected | 1 | markdown | parent_reconstructed | {"clone_url":"https://github.com/lokathor/bytemuck","commit_oid":"93d8e53509d4973de8a624e27ebb89cb60405d03","commits_ago_from_head":335,"content_sha256":"df00c53c0aa9f9848f4ec0d73ea1f66ec01640d639ce8cb72a4c6313132a89b8","manifest_sha256":null,"parent_oid":"45bafba41c801dac190048ca423a2ec493835dc2","repository_id":"gith... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":1,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/area17/laravel-translatable@57ec347958527105481e731de0e03c2b5f98e968 | <|commit_message|>
wip run-tests.yml
<|file_patch|>.github/workflows/run-tests.yml
diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml
index a68c1dc2457e84a24b389481eeb5b9bb423b27a0..2eec514127cd191fd67582c58e0fded9d7b1ffda 100644
--- a/.github/workflows/run-tests.yml
+++ b/.github/workflows... | 38 | code.commit.baseline | band-04 | 606 | 2,945,658,675,589,660,000 | null | null | null | github.com/area17/laravel-translatable | 04 | false | no_named_signal_detected | 0 | yaml | parent_reconstructed | {"clone_url":"https://github.com/area17/laravel-translatable","commit_oid":"57ec347958527105481e731de0e03c2b5f98e968","commits_ago_from_head":117,"content_sha256":"42a597df7e8e7ecb268df9eec7946e59dd31e15883ed3bb5e6fb71753d026a63","manifest_sha256":null,"parent_oid":"99205ca47f3cf71ed44e517e3a812cbef30a915e","repository... | {"annotations":{"commit_quality_band":"04","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/apache/harmony-classlib@30d8b21b19b816991ccad519325bdf82e3ebb68f | <|commit_message|>
Fix encoding bugs in DigestInputStream2Test and MessageDigest2Test for z/OS
git-svn-id: https://svn.apache.org/repos/asf/harmony/enhanced/classlib/trunk@796991 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>modules/security/src/test/api/java/org/apache/harmony/security/tests/java/security/Diges... | 218 | code.commit.baseline | band-04 | 3,830 | 2,945,714,428,949,794,000 | null | null | null | github.com/apache/harmony-classlib | 04 | true | no_named_signal_detected | 2 | java | parent_reconstructed | {"clone_url":"https://github.com/apache/harmony-classlib","commit_oid":"30d8b21b19b816991ccad519325bdf82e3ebb68f","commits_ago_from_head":494,"content_sha256":"a9884cec3c5332c191e1f379194bc37dafd2568c684a1fada793a9e99ea5ed7a","manifest_sha256":null,"parent_oid":"5e3d5fd5f4f0a7376b763c9ac79c959cc7dea903","repository_id"... | {"annotations":{"commit_quality_band":"04","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/14islands/island.is@e39aea94fb9144bb080e3f1082e523fb05cb5861 | <|commit_message|>
chore(j-s): Disable multiple click on the same case (#13109)
* Checkpoint
* Checkpoint
* Add loading indicator to cases while opening and disable sub mouse clicks
* Add loading indicator to mobile category cards
* Add opening indcator to past cases
* Add loading indicator to mobile cards
* Rem... | 578 | code.commit.baseline | band-07 | 45,441 | 2,945,863,165,424,604,700 | null | null | null | github.com/14islands/island.is | 07 | false | no_named_signal_detected | 0 | typescript | parent_reconstructed | {"clone_url":"https://github.com/14islands/island.is","commit_oid":"e39aea94fb9144bb080e3f1082e523fb05cb5861","commits_ago_from_head":4212,"content_sha256":"d74a1429c1e10122a381e1e35183c77f5c6b6b1518272e9e672ca3eef4a0db10","manifest_sha256":null,"parent_oid":"5288a2cd500fe0ae44caf99ef81e85f3f0665785","repository_id":"g... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"candidate_cap_rungs_exceeded"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubr... |
commit-doc:github.com/beakerbrowser/js-ipfs-api@2ae09fb28a178a36ab4b5be7cba63f06cf35c15b | <|commit_message|>
feat(util): add fsAdd, streamAdd and urlAdd
<|file_patch|>README.md
diff --git a/README.md b/README.md
index abec73a0358e5e0fa43fc1110222549d068fffa8..516b7bde38b2de4cbd945ff76a1f841ee1c7a81d 100644
--- a/README.md
+++ b/README.md
@@ -116,11 +116,29 @@ Complete documentation for these methods is com... | 64 | code.commit.baseline | band-05 | 11,942 | 2,946,005,771,271,003,600 | null | null | null | github.com/beakerbrowser/js-ipfs-api | 05 | true | no_named_signal_detected | 3 | javascript | parent_reconstructed | {"clone_url":"https://github.com/beakerbrowser/js-ipfs-api","commit_oid":"2ae09fb28a178a36ab4b5be7cba63f06cf35c15b","commits_ago_from_head":147,"content_sha256":"33db1a873dcc64ff8b3d46881d5dcc53e701350d1d741ff4bed107464a6c6455","manifest_sha256":null,"parent_oid":"4cffb47bef83d1ab16dc4e3da51af664f2ca124a","repository_i... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":5},"conventional_commit_type":{... |
commit-doc:github.com/bloomberg/lucene-solr@1c6508b2841f40e1379b5f4802ff90b3de541cf9 | <|commit_message|>
SOLR-6231: Harden the RollingRestartTest
git-svn-id: https://svn.apache.org/repos/asf/lucene/dev/trunk@1612499 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>solr/core/src/test/org/apache/solr/cloud/RollingRestartTest.java
diff --git a/solr/core/src/test/org/apache/solr/cloud/RollingRestartTest... | 169 | code.commit.baseline | band-06 | 5,661 | 2,946,087,214,190,613,000 | null | null | null | github.com/bloomberg/lucene-solr | 06 | true | no_named_signal_detected | 2 | java | parent_reconstructed | {"clone_url":"https://github.com/bloomberg/lucene-solr","commit_oid":"1c6508b2841f40e1379b5f4802ff90b3de541cf9","commits_ago_from_head":6946,"content_sha256":"5ed8fda18e5ab13a5762f40f6aef47717db55020eeeb229fe8c3fcdbbfa3386b","manifest_sha256":null,"parent_oid":"a265a8ab9c12af888dd7acd0c38f745230f5d847","repository_id":... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/ansible/workshops@d2736ad8601a65646a1dfc896575f8ed1560502d | <|commit_message|>
Removing ad hoc commands and replacing with playbooks
<|file_patch|>exercises/ansible_rhel/1.3-playbook/README.md
diff --git a/exercises/ansible_rhel/1.3-playbook/README.md b/exercises/ansible_rhel/1.3-playbook/README.md
index b05d54588c24d0d859dd9628f08de46c13fbae4c..f8a72b6547d6c584b636ead466aa3f9... | 74 | code.commit.baseline | band-08 | 15,258 | 2,946,323,365,074,111,000 | null | null | null | github.com/ansible/workshops | 08 | false | no_named_signal_detected | 0 | markdown | parent_reconstructed | {"clone_url":"https://github.com/ansible/workshops","commit_oid":"d2736ad8601a65646a1dfc896575f8ed1560502d","commits_ago_from_head":2971,"content_sha256":"22766b40452d6fade380d08c6236da0489cb3dfc6d9c3cb1c31a0f176d27739a","manifest_sha256":null,"parent_oid":"7dd1b4f5f9bd0ea3a709e07499fc8eb9b5d4dd1b","repository_id":"git... | {"annotations":{"commit_quality_band":"08","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/jenkinsci/jenkins@31a2956c8989306661c9c7bc1e6532bc12b029b4 | <|commit_message|>
Revert "Update jackson2-api to v2.19.0-404.vb_b_0fd2fea_e10" (#10699)
The kubernetes client has issues with Jackson 2.19.0.
Original pull request that updated to 2.19.0 was:
* https://github.com/jenkinsci/jenkins/pull/10677
Reverted from the Jenkins plugin BOM in pull request:
* https://github.c... | 1,323 | code.commit.baseline | band-01 | 2,053 | 2,946,535,974,345,478,000 | null | null | null | github.com/jenkinsci/jenkins | 01 | false | no_named_signal_detected | 7 | json | parent_reconstructed | {"clone_url":"https://github.com/jenkinsci/jenkins","commit_oid":"31a2956c8989306661c9c7bc1e6532bc12b029b4","commits_ago_from_head":1691,"content_sha256":"4b9cfaac34daf54747fe84044276a045f0e57665073acf588dca680cb9469fc4","manifest_sha256":null,"parent_oid":"33978746ca9944498409689cbf2cbb0141ff5571","repository_id":"git... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":7,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":9,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":... |
commit-doc:github.com/a11yproject/a11yproject.com@0ababb5dba67ab23735b339ae4cce8dbf8885020 | <|commit_message|>
Added Launchy link
Closes #497.
<|file_patch|>_data/patterns.yml
diff --git a/_data/patterns.yml b/_data/patterns.yml
index bfec42e287e2c1433d078ba9a189fc9021344474..be13f79a3afd51cdf12292e8eeade1378d9efc33 100644
--- a/_data/patterns.yml
+++ b/_data/patterns.yml
@@ -65,6 +65,8 @@
title: "The... | 52 | code.commit.baseline | band-07 | 643 | 2,946,562,526,503,953,000 | null | null | null | github.com/a11yproject/a11yproject.com | 07 | false | no_named_signal_detected | 0 | yaml | parent_reconstructed | {"clone_url":"https://github.com/a11yproject/a11yproject.com","commit_oid":"0ababb5dba67ab23735b339ae4cce8dbf8885020","commits_ago_from_head":1640,"content_sha256":"b0f3d029ba85b238969061b5889b0fa45f7a3e7258b38a89be7220596f034c7d","manifest_sha256":null,"parent_oid":"0d2a9d7bb36d2e61483312f7b74fd4263aefe8a9","repositor... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/alibaba/mongo@31716d2ae526d82d7d36464f6c9fae8b9f38542f | <|commit_message|>
SERVER-19855 Do not perform shard version checking where not necessary
The code in RangeDeleter and sharding migration and split uses
AutoGetCollectionForRead, which has the side effect of checking for shard
version, based on the context. This causes problems in the cases where we
are transmitting s... | 495 | code.commit.baseline | band-03 | 19,516 | 2,947,056,185,575,329,300 | null | null | null | github.com/alibaba/mongo | 03 | false | no_named_signal_detected | 2 | c | parent_reconstructed | {"clone_url":"https://github.com/alibaba/mongo","commit_oid":"31716d2ae526d82d7d36464f6c9fae8b9f38542f","commits_ago_from_head":1678,"content_sha256":"38248dc7fea6478eefdb5ab55351cc42de5efb2dcda06a65ca1ca0447323f362","manifest_sha256":null,"parent_oid":"0c695aa1e879af482dc3aea4768dbda223ff4592","repository_id":"github.... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/apiaryio/documentation@7bbe8513ed00fe779d7874fe3052a539b9eeecf0 | <|commit_message|>
Update repository URL
<|file_patch|>Readme.md
diff --git a/Readme.md b/Readme.md
index 072c6a8abf99aa263d83632ae2d24ea6e2af5959..abc7a06bd55881c494ce414b149116955166c074 100644
--- a/Readme.md
+++ b/Readme.md
@@ -5,7 +5,7 @@
Clone the repository, install needed gems and run Jekyll ;)
```bash
... | 42 | code.commit.baseline | band-08 | 484 | 2,947,099,425,834,032,000 | null | null | null | github.com/apiaryio/documentation | 08 | false | no_named_signal_detected | 0 | markdown | parent_reconstructed | {"clone_url":"https://github.com/apiaryio/documentation","commit_oid":"7bbe8513ed00fe779d7874fe3052a539b9eeecf0","commits_ago_from_head":257,"content_sha256":"9374b79c3d06d296af43e98644328987c1f4eb3de639e7b5bc73759a1e6284cd","manifest_sha256":null,"parent_oid":"84dfdb144aeb027a4280210978bf9638fa12dac0","repository_id":... | {"annotations":{"commit_quality_band":"08","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/agilebits/golang-net@e354193b05bb6b1826eabcb5ef03f4e46175fd2e | <|commit_message|>
Fix embarassing typo bug in ReadFrameHeader.
Thanks to Qi Zhao for the find.
Added new tests as penance.
<|file_patch|>frame.go
diff --git a/frame.go b/frame.go
index 48bfdfbe0e6e8150ce736d57f20e50425513207d..345d571ecccd5caeca2ed7001fee16293f2fcf79 100644
--- a/frame.go
+++ b/frame.go
@@ -239,7 +... | 127 | code.commit.baseline | band-02 | 3,418 | 2,947,228,397,487,928,000 | null | null | null | github.com/agilebits/golang-net | 02 | false | no_named_signal_detected | 3 | go | parent_reconstructed | {"clone_url":"https://github.com/agilebits/golang-net","commit_oid":"e354193b05bb6b1826eabcb5ef03f4e46175fd2e","commits_ago_from_head":1108,"content_sha256":"d1e9c738a9cd820a2e720428671d36bcb48a056b6f2e7f0492f7891caf81aba2","manifest_sha256":null,"parent_oid":"1552131519c24eeb958c50c168b9505d6158e3e5","repository_id":"... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":2},"conventional_commit_type":{... |
commit-doc:github.com/alibaba/flink@77b7dccd3a30719a8d0bac82fa0ae49f2e9ac889 | <|commit_message|>
[streaming] Logger updated, only streaming is logged
<|file_patch|>flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvokableComponent.java
diff --git a/flink-addons/flink-streaming/src/main/java/eu/stratosphere/streaming/api/streamcomponent/StreamInvoka... | 73 | code.commit.baseline | band-03 | 3,551 | 2,947,275,733,442,465,000 | null | null | null | github.com/alibaba/flink | 03 | true | no_named_signal_detected | 3 | java | parent_reconstructed | {"clone_url":"https://github.com/alibaba/flink","commit_oid":"77b7dccd3a30719a8d0bac82fa0ae49f2e9ac889","commits_ago_from_head":5586,"content_sha256":"dba6264d227b190071a88da22e39cdc1de7b51925b693ea4c04d2ad79a164369","manifest_sha256":null,"parent_oid":"976bc5730fba3d623debab3316dc74cf0f2394a8","repository_id":"github.... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/reactor/reactor-core@7dff05d5629dc29f0e6dd6d2aaafe65bcc99f9ae | <|commit_message|>
[release] Next development version 3.5.12-SNAPSHOT
Signed-off-by: Oleh Dokuka <odokuka@vmware.com>
<|file_patch|>gradle.properties
diff --git a/gradle.properties b/gradle.properties
index f9a378b2626a7c15c2dfb703425ee1899b610913..9865d37b2fee75043e37349dd19273b4b1b332a0 100644
--- a/gradle.properti... | 120 | code.commit.baseline | band-01 | 1,023 | 2,947,455,426,971,485,700 | null | null | null | github.com/reactor/reactor-core | 01 | false | no_named_signal_detected | 10 | toml | parent_reconstructed | {"clone_url":"https://github.com/reactor/reactor-core","commit_oid":"7dff05d5629dc29f0e6dd6d2aaafe65bcc99f9ae","commits_ago_from_head":1075,"content_sha256":"ff44626f91e1590d239aa9afd716cdc6deb04212950ccfc203af7aef09fd6980","manifest_sha256":null,"parent_oid":"c6b7f8778bd398ba38f019f6e43977cafb0a68e5","repository_id":"... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":10,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":11,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top10":3},"rubric_v... |
commit-doc:github.com/alteryx/activemq-5-12@f6e1ac7f979baff434d2ff06f5d2e562becc8a45 | <|commit_message|>
added NPE check
git-svn-id: https://svn.apache.org/repos/asf/activemq/trunk@550793 13f79535-47bb-0310-9956-ffa450edef68
<|file_patch|>activemq-core/src/main/java/org/apache/activemq/transport/fanout/FanoutTransport.java
diff --git a/activemq-core/src/main/java/org/apache/activemq/transport/fanout/F... | 141 | code.commit.baseline | band-08 | 2,157 | 2,947,629,008,172,264,000 | null | null | null | github.com/alteryx/activemq-5-12 | 08 | false | no_named_signal_detected | 0 | java | parent_reconstructed | {"clone_url":"https://github.com/alteryx/activemq-5-12","commit_oid":"f6e1ac7f979baff434d2ff06f5d2e562becc8a45","commits_ago_from_head":5722,"content_sha256":"01435c4c4d59ba59ca6f16137699e31620e65f0daccd0c9c58c88ca17e655095","manifest_sha256":null,"parent_oid":"8068c5e1551bed9e0003806cb7b463bd1c058473","repository_id":... | {"annotations":{"commit_quality_band":"08","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":8},"conventional_commit_type":{... |
commit-doc:github.com/davemorrissey/subsampling-scale-image-view@5049478cd8edae804503f3ca2df3c8724ece8bfb | <|commit_message|>
Migrate to AndroidX (#447 @vfishv)
<|file_patch|>.travis.yml
diff --git a/.travis.yml b/.travis.yml
index 69effa023b4007ce1133e916f3cea65b4399c88b..7dec1a51392c462a3c591a7b9eec83413011ed65 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -5,7 +5,7 @@ before_cache:
- rm -fr $HOME/.gradle/caches/*/pl... | 56 | code.commit.baseline | band-01 | 32,288 | 2,947,657,328,966,508,500 | null | null | null | github.com/davemorrissey/subsampling-scale-image-view | 01 | true | no_named_signal_detected | 2 | java | parent_reconstructed | {"clone_url":"https://github.com/davemorrissey/subsampling-scale-image-view","commit_oid":"5049478cd8edae804503f3ca2df3c8724ece8bfb","commits_ago_from_head":10,"content_sha256":"dde6174cf80b64e96aa732c605b88eac85c08433ee208ffc0668d7fe6a974f1f","manifest_sha256":null,"parent_oid":"b61c59eb6681f53a412db42aa62d401973c6abc... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":2,"reason":"candidate_cap_rungs_exceeded"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_... |
commit-doc:github.com/amplify-education/honeydew@77faab63980e875a4922aa11d370a663026fccbf | <|commit_message|>
[Rex] Added PressEnter and WakeUp device actions
<|file_patch|>android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java
diff --git a/android-server/src/main/java/com/uiautomator_cucumber/android_server/ActionsExecutor.java b/android-server/src/main/java/com/uiautomat... | 69 | code.commit.baseline | band-03 | 4,452 | 2,947,722,212,727,718,000 | null | null | null | github.com/amplify-education/honeydew | 03 | false | no_named_signal_detected | 3 | java | parent_reconstructed | {"clone_url":"https://github.com/amplify-education/honeydew","commit_oid":"77faab63980e875a4922aa11d370a663026fccbf","commits_ago_from_head":108,"content_sha256":"87ad2d892872b07a85c4968725e841cb278ec90d04325e1bbd98623770f81db1","manifest_sha256":null,"parent_oid":"cdfe01d7fb738113ba060c3a58c7328a8e40278b","repository_... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/prisma/prisma-examples@b8cba3dbb16048150493a498af39f10f66f16872 | <|commit_message|>
chore(deps): update typescript-eslint monorepo to v8.9.0
<|file_patch|>accelerate/remix-starter/package.json
diff --git a/accelerate/remix-starter/package.json b/accelerate/remix-starter/package.json
index 1ec60b50ac1dc1f3e35450a4809c811835a8a91f..630e17c2c4d4e5dc3d1f6790560165782a10f614 100644
--- a... | 76 | code.commit.baseline | band-01 | 4,513 | 2,948,005,736,227,531,300 | null | null | null | github.com/prisma/prisma-examples | 01 | false | detected_named_ai_or_bot_signal | 4 | json | parent_reconstructed | {"clone_url":"https://github.com/prisma/prisma-examples","commit_oid":"b8cba3dbb16048150493a498af39f10f66f16872","commits_ago_from_head":1553,"content_sha256":"3510ef4bbfb6a3e8f37c9231d745272b04ddd97a15392e5f3079fe71996dceee","manifest_sha256":null,"parent_oid":"24b55ecf83c919352807a3ab2c60abd99d67b357","repository_id"... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":4,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/akylas/protobuf@7dbe742e6c4bea916c54713e31811412d2076351 | <|commit_message|>
Internal protobuf changes
PiperOrigin-RevId: 527076622
<|file_patch|>src/google/protobuf/port_undef.inc
diff --git a/src/google/protobuf/port_undef.inc b/src/google/protobuf/port_undef.inc
index 03b216c4221629d3004ff2d4f9ec6ae4f20c4367..d56614765eabab9e72b945544e9c2f25d5b3020e 100644
--- a/src/goog... | 76 | code.commit.baseline | band-07 | 631 | 2,948,664,631,150,901,000 | null | null | null | github.com/akylas/protobuf | 07 | false | no_named_signal_detected | 0 | null | parent_reconstructed | {"clone_url":"https://github.com/akylas/protobuf","commit_oid":"7dbe742e6c4bea916c54713e31811412d2076351","commits_ago_from_head":5834,"content_sha256":"6aab641c31840edfb6954a2672342a831e709f9bb531caeb112b4712de5d8f43","manifest_sha256":null,"parent_oid":"b26afb5a86cd9f764e35795c41c0f94a012db19e","repository_id":"githu... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":2,"reason":"most_changed_files_screened_away"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"rout... |
commit-doc:github.com/ardupilot/pidcodes.github.com@3706846b8a4c7f58c7a5cb229ec9e89107b1a391 | <|commit_message|>
Enable initial Travis CI workflow (#183)
* Remove errant .DS_Store file
* Ignore .DS_Store
* Create a list of organisations
* Add an org list
* Show number of PIDs per org
* Fix HTML issue, sort orgs by title
* Try and fix the PID count
* Try and fix issues
* Try again to fix... | 1,774 | code.commit.baseline | band-09 | 14,054 | 2,949,122,895,333,498,400 | null | null | null | github.com/ardupilot/pidcodes.github.com | 09 | false | no_named_signal_detected | 0 | html | parent_reconstructed | {"clone_url":"https://github.com/ardupilot/pidcodes.github.com","commit_oid":"3706846b8a4c7f58c7a5cb229ec9e89107b1a391","commits_ago_from_head":117,"content_sha256":"77b4150a93c5f5496693b0697e8e8c9ff9903ed85db102b976026d798e125496","manifest_sha256":null,"parent_oid":"c54c8582baa1b8bad16b49517be552d6ed455dd6","reposito... | {"annotations":{"commit_quality_band":"09","commit_quality_score":{"commit_score":0,"deductions":[],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_version":2,"tier":9},"conventional_commit_type":{... |
commit-doc:github.com/datamapper/dm-migrations@9a3446f2cd8ce570c36df3fcfd04067a2de1f59d | <|commit_message|>
Added i18n dependency
<|file_patch|>Gemfile
diff --git a/Gemfile b/Gemfile
index bbbdd53295e19add1f69053676a7c9afbafa5165..c3cef93cb7e158f8839cdacad3eff45d78b44a41 100644
--- a/Gemfile
+++ b/Gemfile
@@ -12,6 +12,7 @@ group :runtime do # Runtime dependencies (as in the gemspec)
if ENV['EXTLIB']
... | 42 | code.commit.baseline | band-01 | 2,223 | 2,949,258,016,549,512,000 | null | null | null | github.com/datamapper/dm-migrations | 01 | false | no_named_signal_detected | 1 | ruby | parent_reconstructed | {"clone_url":"https://github.com/datamapper/dm-migrations","commit_oid":"9a3446f2cd8ce570c36df3fcfd04067a2de1f59d","commits_ago_from_head":113,"content_sha256":"e6160b35c3627856c088326534aa3c52205ad7a9b1f20b8b2b45a2f4bf6b2ac1","manifest_sha256":null,"parent_oid":"0c8b6088310ab9177f5ff4219bc9d0674b67b9c7","repository_id... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":1,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":4,"repo_score_components":{"dependents_reach":4,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/alerta/docker-alerta@f716a98b8212436968229e6a5cdbdc97a2ca0ffe | <|commit_message|>
Move docker-compose tests to unit test dir
<|file_patch|>Makefile
diff --git a/Makefile b/Makefile
index bf51964278daf7b6f2d175fc803ea2fc26265983..150981be1ae4cee700195f0cfa302e7c7b70170e 100644
--- a/Makefile
+++ b/Makefile
@@ -23,12 +23,24 @@ all: help
lint:
docker run --rm -i hadolint/hadolint... | 63 | code.commit.baseline | band-08 | 6,328 | 2,949,632,148,287,664,600 | null | null | null | github.com/alerta/docker-alerta | 08 | true | no_named_signal_detected | 0 | yaml | parent_reconstructed | {"clone_url":"https://github.com/alerta/docker-alerta","commit_oid":"f716a98b8212436968229e6a5cdbdc97a2ca0ffe","commits_ago_from_head":63,"content_sha256":"33ed1206bcca7dd699f978b12f5e838c1dbe7bd761b5ac1ead776a2ad6047850","manifest_sha256":null,"parent_oid":"2d75b249b272947c96d7a348b83af5c8e27bf9d0","repository_id":"gi... | {"annotations":{"commit_quality_band":"08","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/angr/angr@14bfe7d52ac7033b070ad2873e8d1303f430dc3f | <|commit_message|>
z3 interrupts, threading, suggestions, and other fixes (#3462)
* Add state option to control AUTO_REFS and stuff; disable by default
* Fix LAZY_SOLVES
* Add integration for new claripy error with 'interrupted' stash
* remove deprecated exploration technique compatibility layer
* fix thre... | 533 | code.commit.baseline | band-01 | 39,471 | 2,949,982,828,531,449,300 | null | null | null | github.com/angr/angr | 01 | true | no_named_signal_detected | 6 | python | parent_reconstructed | {"clone_url":"https://github.com/angr/angr","commit_oid":"14bfe7d52ac7033b070ad2873e8d1303f430dc3f","commits_ago_from_head":3240,"content_sha256":"92aa0fd17a833d87256b9cbd9cb14275dc62775c968f744ba3da17df3019e204","manifest_sha256":null,"parent_oid":"195c8abe2b6c67e3e22fc118f1b048b760046225","repository_id":"github.com/... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":6,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":7,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":2,"route_language_top1... |
commit-doc:github.com/alex-d/trumbowyg@617b374e35cdebebe1be43c1e518cae5e76d9918 | <|commit_message|>
docs: upgrade used Trumbowyg version to v2.27.2
<|file_patch|>docs/demos/js/loader.js
diff --git a/docs/demos/js/loader.js b/docs/demos/js/loader.js
index 80cb3abd02b97beba3d1dec381fc612688585089..bbf3356b51d9567db53efe3e44ff3ce98c83e81f 100644
--- a/docs/demos/js/loader.js
+++ b/docs/demos/js/loade... | 68 | code.commit.baseline | band-01 | 735 | 2,950,031,279,388,649,500 | null | null | null | github.com/alex-d/trumbowyg | 01 | false | no_named_signal_detected | 3 | javascript | parent_reconstructed | {"clone_url":"https://github.com/alex-d/trumbowyg","commit_oid":"617b374e35cdebebe1be43c1e518cae5e76d9918","commits_ago_from_head":86,"content_sha256":"f21570912912c21b8bc90bfaf5c9b38a7182e6adbf04dbf5869d8dd4417af191","manifest_sha256":null,"parent_oid":"c9aaa6d1b56e8c552bf069f037c5e9a423f6adcd","repository_id":"github... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":3,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":... |
commit-doc:github.com/buglabs/android_external_busybox@4662de0511487b4da965c4b2158bae318f3d80a8 | <|commit_message|>
replace APP_xxDHCPxx with xxDHCPxx, it's more consistent with the rest
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>
<|file_patch|>TODO_config_nommu
diff --git a/TODO_config_nommu b/TODO_config_nommu
index 1835b6e80b6cc1ee74f2e18942c5c13748ac545e..d5ee7bebd03c9ae22f8c6ae5239c254566ec96ec... | 149 | code.commit.baseline | band-06 | 10,303 | 2,950,053,113,846,062,600 | null | null | null | github.com/buglabs/android_external_busybox | 06 | false | no_named_signal_detected | 2 | c | parent_reconstructed | {"clone_url":"https://github.com/buglabs/android_external_busybox","commit_oid":"4662de0511487b4da965c4b2158bae318f3d80a8","commits_ago_from_head":202,"content_sha256":"c26c729a185a10ee7f390b567aaf05698bc883a64e13e9d2d87cb52bbee920c9","manifest_sha256":null,"parent_oid":"8656676a2199e2701e7e5656ef3d2092dedd9ba5","repos... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/acemod/ace3@5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84 | <|commit_message|>
Dupplicate Polish entry (#5018)
https://i.gyazo.com/c7557980d7d4c36709be78ef1f2c2a8f.png
<|file_patch|>addons/tagging/stringtable.xml
diff --git a/addons/tagging/stringtable.xml b/addons/tagging/stringtable.xml
index 8b0782c32e3eb1843d7abecd9efecd219a3d7c5e..7d66f99e22d16986edc454e891f8ecd84d4c0bec ... | 109 | code.commit.baseline | band-07 | 680 | 2,950,083,512,014,741,500 | null | null | null | github.com/acemod/ace3 | 07 | false | no_named_signal_detected | 0 | null | parent_reconstructed | {"clone_url":"https://github.com/acemod/ace3","commit_oid":"5d8cf43199ab8efb9e1ac6e6377e4965e6eaaf84","commits_ago_from_head":5325,"content_sha256":"186a9dd9a9073adcaf34117edd3882376f0cfae4ceb6d797550b0e9af01377f7","manifest_sha256":null,"parent_oid":"bb228fa2b3a8b8cedc2ffc7c5093d57107041abc","repository_id":"github.co... | {"annotations":{"commit_quality_band":"07","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/carbon-language/carbon-lang@e26bc323434195d008bd35de6068f42a0ac08104 | <|commit_message|>
Change remaining uses of `Bool` to `bool`, following #750. (#1901)
The most significant change here is that explorer now uses the chosen spelling
rather than the old `Bool` spelling. Also update a few documentation examples
and some skeletal design docs to use the chosen spelling.
<|file_patch|>co... | 304 | code.commit.baseline | band-10 | 29,890 | 2,950,191,395,428,974,600 | null | null | null | github.com/carbon-language/carbon-lang | 10 | false | no_named_signal_detected | 0 | markdown | parent_reconstructed | {"clone_url":"https://github.com/carbon-language/carbon-lang","commit_oid":"e26bc323434195d008bd35de6068f42a0ac08104","commits_ago_from_head":4479,"content_sha256":"70b51d6735a0d9ed4fcf74c493bcfe6d7d992c7764fb4e716e6c150784ec5932","manifest_sha256":null,"parent_oid":"72d3d3c75cc4a78d80a09d18178b2cd6a9a9dd94","repositor... | {"annotations":{"commit_quality_band":"10","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"},{"points":2,"reason":"candidate_cap_rungs_exceeded"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_... |
commit-doc:github.com/octoprint/octoprint@8ad20a0168417de77a0c3d41fa1b930dab3f9b11 | <|commit_message|>
Allow definition of temperature offsets for extruder and bed
Session based temperature offsets that are only applied to temperature definitions in GCODE files being printed, in order to quickly experiment with temperature settings.
Closes #97
<|file_patch|>octoprint/printer.py
diff --git a/octopri... | 265 | code.commit.baseline | band-01 | 5,839 | 2,950,457,267,684,942,300 | null | null | null | github.com/octoprint/octoprint | 01 | false | no_named_signal_detected | 3 | javascript | parent_reconstructed | {"clone_url":"https://github.com/octoprint/octoprint","commit_oid":"8ad20a0168417de77a0c3d41fa1b930dab3f9b11","commits_ago_from_head":9012,"content_sha256":"41c060534176328275704eddb36ea37147ca892bdbb69f3c6aa6457e024cfa7b","manifest_sha256":null,"parent_oid":"b2587579baa876a1ba0bd5e81e7a698d31503c6e","repository_id":"g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":3,"deductions":[{"points":2,"reason":"most_changed_files_screened_away"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"... |
commit-doc:github.com/amd/zendnn-pytorch@704283d61ffd5578b73dbf52859acbbae85d13a4 | <|commit_message|>
Improve `clip_grad_norm` to use torch.linalg.vector_norm (#102429)
Done in this PR:
- Use `torch.linalg.vector_norm` instead of `torch.norm`
- Reduce bandwidth boundary of clip_grad_norm when used with `inf`, ie no need to get the returned tensor after `abs`
What I'm slightly unsure:
- I don't ... | 475 | code.commit.baseline | band-03 | 1,910 | 2,950,670,662,777,528,000 | null | null | null | github.com/amd/zendnn-pytorch | 03 | false | no_named_signal_detected | 3 | python | parent_reconstructed | {"clone_url":"https://github.com/amd/zendnn-pytorch","commit_oid":"704283d61ffd5578b73dbf52859acbbae85d13a4","commits_ago_from_head":3789,"content_sha256":"0e09666e5b08df9ab9e9b48744fb4c19964196a2dd1ca7f33449311d6fadca3a","manifest_sha256":null,"parent_oid":"e71ab214226af1f9dbded944e939c6447e0e8f09","repository_id":"gi... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":3},"conventional_commit_type":{... |
commit-doc:github.com/bpmn-io/tiny-svg@6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b | <|commit_message|>
chore(CHANGELOG): update to v3.1.1
<|file_patch|>CHANGELOG.md
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 66ae4209b9830a21e7bfd4ac94a440f1af5ebed9..c671d446653869a4769c9402516484d2f36ca8f2 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -6,6 +6,10 @@ All notable changes to [tiny-svg](https://gith... | 55 | code.commit.baseline | band-06 | 507 | 2,950,677,268,360,528,000 | null | null | null | github.com/bpmn-io/tiny-svg | 06 | false | no_named_signal_detected | 2 | markdown | parent_reconstructed | {"clone_url":"https://github.com/bpmn-io/tiny-svg","commit_oid":"6934e5e8f5807fd3aa98fd4edd9f73c617a2df4b","commits_ago_from_head":25,"content_sha256":"e7f59ca20631f88ba93bc8421e4aea1e8bce04800b8390bcf722432be69f2a59","manifest_sha256":null,"parent_oid":"86a56f5ff5a4c90f409255e71fd9dd1c3a9d3652","repository_id":"github... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/bitrise-io/backstage@33333c94169e1d349f0568516c74143e7d9ddd9a | <|commit_message|>
catalog-backend: implement caching in the processing orchestrator
Co-authored-by: Johan Haals <johan.haals@gmail.com>
Co-authored-by: Fredrik Adelöw <freben@gmail.com>
Co-authored-by: blam <ben@blam.sh>
Signed-off-by: Patrik Oldsberg <poldsberg@gmail.com>
<|file_patch|>plugins/catalog-backend/src/i... | 277 | code.commit.baseline | band-06 | 19,827 | 2,950,828,702,940,838,400 | null | null | null | github.com/bitrise-io/backstage | 06 | true | no_named_signal_detected | 2 | typescript | parent_reconstructed | {"clone_url":"https://github.com/bitrise-io/backstage","commit_oid":"33333c94169e1d349f0568516c74143e7d9ddd9a","commits_ago_from_head":8458,"content_sha256":"4f9c6a1aecc1e4a416f57cd8f0ffc6f8e9058f7fb9d3b0faf00dcc5f336bd40e","manifest_sha256":null,"parent_oid":"ec2cc1ec56854fb4067a6a873662df01f50719e1","repository_id":"... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/aospa/android_kernel_samsung_tuna@4ea6b8974ad3b39b14bd30746229b3a2978e8512 | <|commit_message|>
ipv6: updates to privacy addresses per RFC 4941
Update the code to handle some of the differences between
RFC 3041 and RFC 4941, which obsoletes it. Also a couple
of janitorial fixes.
- Allow router advertisements to increase the lifetime of
temporary addresses. This was not allowed by RFC 3041,
... | 895 | code.commit.baseline | band-03 | 1,866 | 2,951,115,893,635,471,000 | null | null | null | github.com/aospa/android_kernel_samsung_tuna | 03 | false | no_named_signal_detected | 2 | c | parent_reconstructed | {"clone_url":"https://github.com/aospa/android_kernel_samsung_tuna","commit_oid":"4ea6b8974ad3b39b14bd30746229b3a2978e8512","commits_ago_from_head":6289,"content_sha256":"a73aafccafbdfecdc649890c7bea585367167f2d3ea3f68eb5f8d64d6a779072","manifest_sha256":null,"parent_oid":"f44baeb72a29a1a7c6e9cfb626e1798184396a03","rep... | {"annotations":{"commit_quality_band":"03","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/appleseedhq/appleseed@0cb0da1c42451609db2232e1c95eaf92282d9fb7 | <|commit_message|>
Remove get / set render layer indices from python bindings.
<|file_patch|>src/appleseed.python/bindentity.cpp
diff --git a/src/appleseed.python/bindentity.cpp b/src/appleseed.python/bindentity.cpp
index cce69b616332ff9bcf5392d9215651aedc770cec..25170759bdb7099566db44019299f4755a7fe08a 100644
--- a/s... | 80 | code.commit.baseline | band-04 | 857 | 2,951,520,343,500,545,000 | null | null | null | github.com/appleseedhq/appleseed | 04 | false | no_named_signal_detected | 3 | cpp | parent_reconstructed | {"clone_url":"https://github.com/appleseedhq/appleseed","commit_oid":"0cb0da1c42451609db2232e1c95eaf92282d9fb7","commits_ago_from_head":3114,"content_sha256":"4965b9ddf82ca40d090160fc18e26437d150128bd4c9d345aac02fa2291725e2","manifest_sha256":null,"parent_oid":"51a54ee855e55c0df2b666fe9d22f65145c99136","repository_id":... | {"annotations":{"commit_quality_band":"04","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":4},"conventional_commit_type":{... |
commit-doc:github.com/ckan/ckan@3d944d4bbf0f816dd61923227df5a5231e0cba5a | <|commit_message|>
Fix tests
<|file_patch|>ckan/tests/lib/dictization/test_dictization.py
diff --git a/ckan/tests/lib/dictization/test_dictization.py b/ckan/tests/lib/dictization/test_dictization.py
index acbaeb6ba08bb5d2651871d2e564145f176eb927..7405fb1700f361fa0b981dc989125aece6d1788e 100644
--- a/ckan/tests/lib/dic... | 30 | code.commit.baseline | band-01 | 2,029 | 2,951,699,239,668,202,500 | null | null | null | github.com/ckan/ckan | 01 | true | no_named_signal_detected | 2 | python | parent_reconstructed | {"clone_url":"https://github.com/ckan/ckan","commit_oid":"3d944d4bbf0f816dd61923227df5a5231e0cba5a","commits_ago_from_head":3163,"content_sha256":"382d2a5c4517f70205e2788fdf9566dee90f39186c02b6ecd79b25ab281c31b8","manifest_sha256":null,"parent_oid":"221f8b9f6cf3e74cde63867259d37682160a1904","repository_id":"github.com/... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":2,"deductions":[{"points":2,"reason":"throwaway_message"},{"points":1,"reason":"no_source_code_purpose"}],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadt... |
commit-doc:github.com/coolsnowwolf/lede@39ee2e1f98dc4868f8ab770e27c04c3fb26e2822 | <|commit_message|>
libcap: update to 2.68
Release Notes:
https://sites.google.com/site/fullycapable/release-notes-for-libcap#h.vdh3d47czmle
Signed-off-by: Nick Hainke <vincent@systemli.org>
<|file_patch|>package/libs/libcap/Makefile
diff --git a/package/libs/libcap/Makefile b/package/libs/libcap/Makefile
index a35b5... | 193 | code.commit.baseline | band-10 | 936 | 2,951,881,708,735,571,000 | null | null | null | github.com/coolsnowwolf/lede | 10 | false | no_named_signal_detected | 0 | makefile | parent_reconstructed | {"clone_url":"https://github.com/coolsnowwolf/lede","commit_oid":"39ee2e1f98dc4868f8ab770e27c04c3fb26e2822","commits_ago_from_head":1970,"content_sha256":"9774df7c411ccd4f798a6828a87bd6808c7212412c68614976cab377eb76ae63","manifest_sha256":null,"parent_oid":"4bba40608bd2b9c05ee33cff62277a4efe7ebda7","repository_id":"git... | {"annotations":{"commit_quality_band":"10","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":0},"rubric_ver... |
commit-doc:github.com/adafruit/esp-idf@4bfd180a943970736d7dd447b41f143e5bdfcf7c | <|commit_message|>
fix(i2c): only call esp_pm APIs when CONFIG_PM_ENABLE is enabled
<|file_patch|>components/esp_driver_i2c/i2c_common.c
diff --git a/components/esp_driver_i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c
index 9c8b06288dd6c61e12a9e4641a83cd10afd23822..c8da8c554de4ce1148b974f88ed43d230d7e800d ... | 85 | code.commit.baseline | band-02 | 12,089 | 2,952,475,284,116,504,000 | null | null | null | github.com/adafruit/esp-idf | 02 | false | no_named_signal_detected | 2 | c | parent_reconstructed | {"clone_url":"https://github.com/adafruit/esp-idf","commit_oid":"4bfd180a943970736d7dd447b41f143e5bdfcf7c","commits_ago_from_head":5428,"content_sha256":"bbf93ed487574e4463ad8444c45c70abfaf53bcee898b0f42e420e66733c6a03","manifest_sha256":null,"parent_oid":"6397820d0b2c67d34aed11bd1b4a2a8627942cd8","repository_id":"gith... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/buildkite/gha-to-buildkite@791384c5ce129929be4b5baea7ddd3905d1ec24c | <|commit_message|>
anthropic force tool (#681)
<|file_patch|>instructor/process_response.py
diff --git a/instructor/process_response.py b/instructor/process_response.py
index 16c24ad940b6264f631883809aa1de1e255459e9..e7c6e1da3aa6e21571feb524e07f243a03958138 100644
--- a/instructor/process_response.py
+++ b/instructor... | 49 | code.commit.baseline | band-10 | 1,939 | 2,952,494,854,511,990,000 | null | null | null | github.com/buildkite/gha-to-buildkite | 10 | false | no_named_signal_detected | 0 | python | parent_reconstructed | {"clone_url":"https://github.com/buildkite/gha-to-buildkite","commit_oid":"791384c5ce129929be4b5baea7ddd3905d1ec24c","commits_ago_from_head":737,"content_sha256":"194e2fc41f979179ad466b33a5aadeab4ca9d4aa2b36c4a8001df941b3278392","manifest_sha256":null,"parent_oid":"cd5169e8b6d263220bf9a8a29a8235f7268ea02e","repository_... | {"annotations":{"commit_quality_band":"10","commit_quality_score":{"commit_score":0,"deductions":[{"points":1,"reason":"junk_file_receipts_alongside_kept_files"}],"repo_score":0,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top1... |
commit-doc:github.com/gnea/grbl@cd71a90ce8a770e0030ed6c9bac805b89724e275 | <|commit_message|>
Made line number reporting optional via config.h
<|file_patch|>config.h
diff --git a/config.h b/config.h
index dbf37e31dcc00c18a07d5c4e9d83ab83a25e9673..ddaddcbab7b30f864af9db8b47e8b043e3e86f52 100644
--- a/config.h
+++ b/config.h
@@ -28,6 +28,10 @@
#ifndef config_h
#define config_h
+// Allows G... | 69 | code.commit.baseline | band-01 | 2,946 | 2,952,512,721,233,691,600 | null | null | null | github.com/gnea/grbl | 01 | false | no_named_signal_detected | 5 | c | parent_reconstructed | {"clone_url":"https://github.com/gnea/grbl","commit_oid":"cd71a90ce8a770e0030ed6c9bac805b89724e275","commits_ago_from_head":317,"content_sha256":"b0f79f3a69a8cb3dc7490f5165d599a99568d3a3f574862f7f45ea480e092fc1","manifest_sha256":null,"parent_oid":"6fdb35a7dad3e4ef027260aa30aef1fb0e55c554","repository_id":"github.com/g... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":5,"deductions":[],"repo_score":5,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |
commit-doc:github.com/babylonhealth/flux@47dade92a8d7981f7a7e07413471c9563ebfdf72 | <|commit_message|>
Retrieve tag patterns again
<|file_patch|>daemon/images.go
diff --git a/daemon/images.go b/daemon/images.go
index acc8c26c4d2c0c24a5ad863456e0f5cacd3eed81..7d877ed4c4b3766de7c9dc115b575a22b7f49033 100644
--- a/daemon/images.go
+++ b/daemon/images.go
@@ -2,6 +2,7 @@ package daemon
import (
"fmt"... | 48 | code.commit.baseline | band-05 | 2,599 | 2,952,871,545,106,236,400 | null | null | null | github.com/babylonhealth/flux | 05 | false | no_named_signal_detected | 3 | go | parent_reconstructed | {"clone_url":"https://github.com/babylonhealth/flux","commit_oid":"47dade92a8d7981f7a7e07413471c9563ebfdf72","commits_ago_from_head":2072,"content_sha256":"f9cda3545c5f7466de6c419685607bff154e2d8c1cd98c53208a229432763399","manifest_sha256":null,"parent_oid":"b0c2edcf375944f7ed6c58cc2d287c39c5abc26a","repository_id":"gi... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":5},"conventional_commit_type":{... |
commit-doc:github.com/buglabs/dragonfly@503ede30dfaaa7e2467e10d8e7c1ecce520f3af1 | <|commit_message|>
updated for new pages
git-svn-id: svn://bugcamp.net/dragonfly/trunk/com.buglabs.dragonfly.help@6843 35ad6e01-222d-0410-b96a-b41bba574936
<|file_patch|>build.properties
diff --git a/build.properties b/build.properties
index 50a980b6a3a70f0f8b71b9b749a04de646499861..b9baf5a37da9990ba8ab769b2fa6d0e12c... | 158 | code.commit.baseline | band-06 | 1,829 | 2,952,956,876,604,439,600 | null | null | null | github.com/buglabs/dragonfly | 06 | false | no_named_signal_detected | 2 | null | parent_reconstructed | {"clone_url":"https://github.com/buglabs/dragonfly","commit_oid":"503ede30dfaaa7e2467e10d8e7c1ecce520f3af1","commits_ago_from_head":715,"content_sha256":"7e8184dd378d1acf9bfaddfd2aaa41b84bad763458e0fd1d372bbba075250be8","manifest_sha256":null,"parent_oid":"b8a489912c3103157ec6733c75191f4f52f85f24","repository_id":"gith... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/boinc/boinc@2767e686e635044d27e5e85bc989e5cc09b7f5b5 | <|commit_message|>
[ci] update actions
Signed-off-by: Vitalii Koshura <lestat.de.lionkur@gmail.com>
<|file_patch|>.github/workflows/android.yml
diff --git a/.github/workflows/android.yml b/.github/workflows/android.yml
index a5100f8d9e481bc500b931737260ef034044c1ed..508e0e0e860d892336ee75a1fb8e467be01eff7f 100644
---... | 102 | code.commit.baseline | band-06 | 723 | 2,953,556,778,622,656,000 | null | null | null | github.com/boinc/boinc | 06 | false | no_named_signal_detected | 2 | yaml | parent_reconstructed | {"clone_url":"https://github.com/boinc/boinc","commit_oid":"2767e686e635044d27e5e85bc989e5cc09b7f5b5","commits_ago_from_head":46,"content_sha256":"290f4939abd1e9321ff76a17c13f50eb3477ca5df199bd4dea7c482c6228beb8","manifest_sha256":null,"parent_oid":"848ebeadb01511b9eb34eb60cb8faaa4a665a2d5","repository_id":"github.com/... | {"annotations":{"commit_quality_band":"06","commit_quality_score":{"commit_score":2,"deductions":[{"points":1,"reason":"no_source_code_purpose"}],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_ver... |
commit-doc:github.com/acquia/ceres@22278ffc0cd5e5a03a7baab8b4234084e5fc09a7 | <|commit_message|>
Add sphinx docstring processing
<|file_patch|>.gitignore
diff --git a/.gitignore b/.gitignore
index 553bad4c0a60f6871e748b7670e3ef65c51b9981..cea07721d176c5bf62deb3a29e6a1b383bd10faa 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,6 @@
MANIFEST
build
+docs/_build
dist
*.log
*.pyc
<|file_pa... | 52 | code.commit.baseline | band-02 | 36,992 | 2,953,557,043,068,050,400 | null | null | null | github.com/acquia/ceres | 02 | false | no_named_signal_detected | 3 | python | parent_reconstructed | {"clone_url":"https://github.com/acquia/ceres","commit_oid":"22278ffc0cd5e5a03a7baab8b4234084e5fc09a7","commits_ago_from_head":11,"content_sha256":"314a5002d2deda68cc7a74f1d2b9b9409e3b9058eb296aaed6e90cd8e4a453dc","manifest_sha256":null,"parent_oid":"9bca9426da726dc5cce7f11c6943c8eed39a45d3","repository_id":"github.com... | {"annotations":{"commit_quality_band":"02","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":2},"conventional_commit_type":{... |
commit-doc:github.com/awslabs/aws-greengrass-labs-containerized-secure-tunneling@26fdd5df6d825602cef145f74389ce9d5653412b | <|commit_message|>
update container base image to Ubuntu 22.04
<|file_patch|>src/Dockerfile
diff --git a/src/Dockerfile b/src/Dockerfile
index 08fb8d77aba908f8aec70a35effe07cfd7d139e0..0c8ec2dcdce12b7e1399f289ae53eb4530bb2c0b 100644
--- a/src/Dockerfile
+++ b/src/Dockerfile
@@ -1,4 +1,4 @@
-FROM ubuntu:20.04 AS builde... | 64 | code.commit.baseline | band-05 | 738 | 2,953,896,960,597,740,000 | null | null | null | github.com/awslabs/aws-greengrass-labs-containerized-secure-tunneling | 05 | false | no_named_signal_detected | 3 | dockerfile | parent_reconstructed | {"clone_url":"https://github.com/awslabs/aws-greengrass-labs-containerized-secure-tunneling","commit_oid":"26fdd5df6d825602cef145f74389ce9d5653412b","commits_ago_from_head":25,"content_sha256":"84d73deed69e6c8711cd64fd728226ac53169eeb397002c6c94ea59aa814caf0","manifest_sha256":null,"parent_oid":"de7a9368e379191bf000651... | {"annotations":{"commit_quality_band":"05","commit_quality_score":{"commit_score":3,"deductions":[],"repo_score":3,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":0,"gitstar_rank_top_1000":0,"route_family_breadth":0,"route_language_top10":3},"rubric_version":2,"tier":5},"conventional_commit_type":{... |
commit-doc:github.com/micro-editor/micro@d6dd838abd6e61f0fdd857d4d5911065737b4352 | <|commit_message|>
Better support for fake cursor
<|file_patch|>internal/display/bufwindow.go
diff --git a/internal/display/bufwindow.go b/internal/display/bufwindow.go
index ccbe2d983ac104d00fe0514143a582e96b25db81..0b4391ae09c88e9e4eefa111ee9db814f14e1e15 100644
--- a/internal/display/bufwindow.go
+++ b/internal/dis... | 51 | code.commit.baseline | band-01 | 4,268 | 2,954,281,714,384,379,000 | null | null | null | github.com/micro-editor/micro | 01 | false | no_named_signal_detected | 9 | go | parent_reconstructed | {"clone_url":"https://github.com/micro-editor/micro","commit_oid":"d6dd838abd6e61f0fdd857d4d5911065737b4352","commits_ago_from_head":1456,"content_sha256":"530d8bfb48f1444602f34e492207d5df4e21dddf64edf9173a8afcfe0165444c","manifest_sha256":null,"parent_oid":"938fb7983a22dc8668a564da210c2db51c15dd7e","repository_id":"gi... | {"annotations":{"commit_quality_band":"01","commit_quality_score":{"commit_score":9,"deductions":[],"repo_score":9,"repo_score_components":{"dependents_reach":0,"gitstar_rank_present":2,"gitstar_rank_top_1000":2,"route_family_breadth":2,"route_language_top10":3},"rubric_version":2,"tier":1},"conventional_commit_type":{... |