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A seal for a sensor element of a gas sensor is known, for example, from German Published Patent Application No. 195 32 090 A1, in which the sensor is mounted into a longitudinal bore of a housing by way of at least two sealing members and a deformable auxiliary seal arranged between the sealing members. The two sealing members are made of magnesium aluminum silicate (steatite), and the sealing member mounted between those sealing members is made of the hexagonal allotrope of boron nitride. | {
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The present invention relates to cleaning brushes for electrostatic copiers of the type utilizing photoreceptors, usually in the form of a rotatable drum or film type belts, zinc oxide, mylar, cadmium, etc., onto which toner particles are electrostatically deposited and which must be removed after each copy has been produced.
In the prior art relating to electrostatic copying machines, it has long been known that adequate means must be provided in the apparatus for removing toner particles from the photoconductive surface in a development station of such copiers and printers. For the most part, such stations employ rotating drums or belts onto which the toner particles are electrostatically deposited and carried through a printing cycle. The surface of such drums or belts have come to be made from a highly polished photosensitive material such as silenium, copper, etc., for drums and zinc oxide, mylar, cadmium, etc., for belts. Extreme care must be taken to keep the surfaces of these drums and belts very clean and protect them from fogging or scratching to insure good reproduction of copies through a large number of printing cycles. Thus, it is important that, after each printing cycle, any remaining toner particles be completely removed from the photosensitive surface without causing any damage or similarly introducing any contaminants to affect the surface of the photoreceptor.
To this end, the prior art has suggested a number of cleaning devices which have employed elaborate air venting and vacuuming implements as well as various types of brushes, many of which have been electrically or magnetically treated with chemicals, sprays, or the like, etc., to assist in the pick-up and removal of toner particles. While such devices have been useful in electrostatic copiers, the efficiency of the cleaning cycle has required improvement so as to minimize the downtime for the copying machine and reduce the frequency of required product maintenance changes.
To this end, the present invention provides an improved cleaning brush for the removal of toner and other particles from a photosensitive surface where, in a preferred embodiment, the brush is formed with two or more kinds of bristles. One kind is a conductive material while the others are compatible non-conductive materials wherein the conductive material fibers may be of shorter or comparable length relative to the non-conductive bristles. Also, in the preferred embodiment, the conductive and non-conductive bristles are intermingled and are supported to extend radially from a cylindrical core which is at least partially conductive or capable of transferring electrical charge throughout. Means may be provided to change the polarity of the conductive bristles to positive or negative alternately while cycling if necessary by connecting the core to a direct current source of the desired polarity or to ground or apply an alternating potential ( ) to the brush which would in effect neutralize the surrounding air to encourage the cleaning process.
The combination of conductive and non-conductive bristles, where the conductive bristles are shorter or of comparable length relative to the non-conductive fibers, will provide an optimum cleaning process and result in a reduction in the frequency of required machine maintenance. | {
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The present invention relates to color-separating prism systems for video cameras, and is, in part, an improvement of the prism system set forth in the copending application of Arthur Cox and Rudolf Hartmann, Ser. No. 06/005,187 filed on even date herewith and assigned to the assignee of the present invention, now abandoned.
The Cox and Hartmann application discloses a very small color-separating prism system uniquely adapted for use with very small solid-state detector devices, such as charge injection devices (CID's), in portable video color cameras suitable for private home use, preferably in conjunction with a video tape recording system.
Conventional color-separating prism systems for video cameras consist of prism components which have dichroic coatings applied directly to the prism faces. This requires careful handling of the components during the coating process to prevent damage from chipping, and also requires custom-made, expensive tooling for the handling of the prism during the coating thereof. Also, since the surfaces to be coated must be laid into holders, some margins of the surfaces will not receive coating. If coatings turn out to be unacceptable, the prisms must be stripped and recoated, a procedure which is quite expensive and subjects the prisms to additional danger of damage.
Additionally, it is imperative in video color cameras that the individual color detectors be very accurately positioned with respect to the associated prism output faces. More particularly, each detector must be carefully positioned without tilt with respect to a certain optical axis of the optical system, must be carefully positioned in directions parallel to and perpendicular to that axis, and the three detectors must be positioned without rotation relative to each other. This positioning is particularly critical and delicate in connection with very small solid-state detectors such as charge-injection devices. In conventional video cameras expensive and complicated detector mountings have been necessary to insure maintenance of each detector in its predetermined position. | {
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This invention is directed to apparatus having successively accessible images in memory and, in particular, to the spatial scanning of a laser beam by successively accessing gratings with different line spacings.
Apparatus, in which successive images may be accessed simply and rapidly, can have complex applications such as the projection of motion pictures by scanning two or three dimension holographic images, or it can have simple applications such as the spatial scanning of a laser beam.
The spatial scanning of a laser beam finds application in imaging or printing devices, optical memories, such as described in U.S. Pat. No. 3,896,420 which issued July 22, 1975 to A. Szabo, optical radars, and many other optical devices. At present, three main methods exist for spatially scanning laser beams. These are generally categorized as mechanical, acousto-optical or electro-optical scanning. The mechanical scanners which include devices such as rotating mirrors, have the limitation of a low scan speed because of mechanical inertia, as well as poor reliability because of mechanical wear. In acousto-optic scanning, the beam is diffracted off an acoustic grating generated in a media such as glass. The scan time between spots is limited, typically, to the range 1-10 .mu.sec due to the grating formation time as determined by the speed of sound in the material. Electro-optic scanning is faster than acoustooptic scanning since it is only limited by the speed of light in the material and quite reliabe since it is non-mechanical. However, it is complex and lossy due to the large number of crystals required-one for each resolvable spot. | {
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The present invention relates generally semiconductor fabrication and, in particular, to systems and methods of forming electroless conductive layers in semiconductor polymer memory devices.
The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful, new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Generally, memory devices are employed in computer and electronic devices to store and maintain this information. Memory devices are typically formed on a semiconductor material such as silicon via a plurality of semiconductor fabrication processes such as layering, doping, heat treatments and patterning. Layering is an operation that adds thin layers to the wafer surface. Layers can be, for example, insulators, semiconductors and/or conductors and are grown or deposited via a variety of processes. Some common deposition techniques are chemical vapor deposition (CVD), evaporation and sputtering. Doping is the process that adds specific amounts of dopants to the wafer surface. The dopants can cause the properties of layers to be modified (e.g., change a semiconductor to a conductor). A number of techniques, such as thermal diffusion and ion implantation can be employed for doping. Heat treatments are another basic operation in which a wafer is heated and cooled to achieve specific results. Typically, in heat treatment operations, no additional material is added or removed from the wafer, although contaminates and vapors may evaporate from the wafer. One common heat treatment is annealing, which repairs damage to crystal structure of a wafer/device generally caused by doping operations. Other heat treatments, such as alloying and driving of solvents, are also employed in semiconductor fabrication.
Generally, a memory device includes arrays of memory cells, wherein each memory cell can be accessed or xe2x80x9creadxe2x80x9d, xe2x80x9cwrittenxe2x80x9d, and xe2x80x9cerasedxe2x80x9d with information. The memory cells maintain information in an xe2x80x9coffxe2x80x9d or an xe2x80x9conxe2x80x9d state (e.g., are limited to 2 states), also referred to as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. To store this information, a memory cell includes a capacitor structure having a top electrode, also referred to as a cell plate, a bottom electrode, also referred to as a storage node, and a charge holding material (e.g., oxide, oxide/nitride/oxide (ONO), . . . ) formed in between the top electrode and the bottom electrode. The top electrode and the bottom electrode are formed of a conductive material. This capacitor permits storage of a charge that allows the memory cell to store a single bit of information. Such memory cells typically employ a refresh signal to maintain the charge on the capacitor and thus, their information. Some examples of memory devices that employ such a capacitor are dynamic random access memory (DRAM), double data rate memory (DDR), flash memory, metal oxide semiconductor field effect transistor (MOSFET), and the like.
However, formation of the electrodes, particular the top electrode via conventional semiconductor fabrication processes is problematic. The conventional processes utilized to form the electrodes generally involve high temperatures and/or electroplating. These high temperatures, particularly for some chemistries, can damage previously formed components of the memory devices. Similarly, employing technologies such as electroplating also poses a significant risk of damaging previously formed components of the memory devices. Electroplating is a process for depositing metal by utilizing electrolysis with an aqueous metal salt solution. In a typical electroplating setup, two electrodes are immersed in a plating solution, such as a sample wafer and a counter electrode. Current is then supplied by an external power supply, and positively charged metal ions flow to the negatively charged cathode where they acquire electrons and deposit in the form of a metal film. Thus, when the wafer is charged negatively and the counter electrode positively, electroplating occurs. However, deposition occurs only on electrically contacted areas on a wafer. More importantly, the flow of electrons and ions can easily damage the already formed portions of the memory device. Thus, conventional technologies for forming electrodes can damage memory devices. The forming of the top electrode can be especially problematic because a substantial portion of the device has already been formed.
The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally semiconductor fabrication and, in particular, to systems and methods of forming electrodes at relatively low temperatures.
The present invention facilitates forming electrodes at low temperatures and mitigating memory element decomposition. An electroless plating process is employed that operates at relatively low temperatures, without employing electrical current. The electroless process is utilized to form conductive layers, such as electrodes and the like, from conductive materials. The process includes depositing an activation compound on selected areas and then applying a chemical solution, which contains a reducing agent and metal ions. Then, a chemical reaction occurs reducing the metal ions and thereby plating the metal ions and forming a conductive layer. The conductive layer formed by the present invention (e.g., electrode) can be utilized in organic memory devices. | {
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In the exploration of oil, gas and geothermal energy, drilling operations are used to create boreholes, or wells, in the earth. Modern drilling rigs may have two, three, or even four mast sections for sequential connection and raising above a substructure. The drilling rigs are transported to the locations where drilling activity is to be commenced. Once transported, large rig components are moved from a transport trailer into engagement with the other components located on the drilling pad.
Moving a full-size drilling rig requires significant disassembly and reassembly of the substructure, mast, and related component. Speed of disassembly and reassembly impacts profitability but safety is the primary concern. A reduction in disassembly reduces errors and delay in reassembly.
Transportation constraints and cost limit many of the design opportunities for building drilling rigs that can drill a well faster. Conventional drilling involves having a drill bit on the bottom of the well. A bottom-hole assembly is located immediately above the drill bit where directional sensors and communications equipment, batteries, mud motors, and stabilizing equipment are provided to help guide the drill bit to the desired subterranean target.
A set of drill collars are located above the bottom-hole assembly to provide a non-collapsible source of weight to help the drill bit crush the formation. Heavy weight drill pipe is located above the drill collars for safety. The remainder of the drill string is mostly drill pipe, designed to be under tension. Each drill pipe is roughly 30 feet long, but lengths vary based on the style. It is common to store lengths of drill pipe in “doubles” (two connected lengths) or “triples” (three connected lengths) or even “fourables” (four connected lengths). A “tubular stand” refers to connected sections of drill pipe, drill collars, or casing.
When the drill bit wears out, or when service, repairs or adjustments need to be made to the bottom-hole assembly, the drill string (drill pipe and other components) is removed from the wellbore and setback. When removing the entire drill string from the well, it is typically disconnected and setback in doubles or triples until the drill bit is retrieved and exchanged. This process of pulling everything out of the hole and running it all back in the hole is known as “tripping.”
Tripping is non-drilling time and, therefore, an expense. Efforts have long been made to devise ways to avoid it or at least speed it up. Running triples is faster than running doubles because it reduces the number of threaded connections to be disconnected and then reconnected. Triples are longer and therefore more difficult to handle due to their length and weight and the natural waveforms that occur when moving them around. Manually handling moving pipe in the derrick and at the drill floor level can be dangerous.
It is desirable to have a drilling rig with the capability to increase safety and reduce trip time. It is desirable to have a drilling rig with the capability of handing stands of drilling tubulars to devices alternative to conventional elevators and top drives. It is also desirable to have a system that includes redundancy, such that if an element of the system fails or requires servicing, the task performed by that unit can be taken-up by another unit on the drilling rig.
Most attempts to automate pipe handling are found offshore. However, solutions for pipe delivery on offshore drilling rigs are seldom transferable to onshore land rigs, due to the many differences in economic viability, size, weight, and transportation considerations. | {
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Prior lead wire forming methods of this type may be divided into two types. According to the first method as shown in FIG. 1, the lead wires of an electric part 1 is pushed by a pushing means 2 in a direction indicated by arrow A, so that they are forced into a pair of lead wire grooves 3a and 3b of the forming means 3 and formed and held therein. According to the second method as shown in FIG. 2, a pushing means 2 moves in a direction indicated by arrow B, so that the lead wires of an electric part are forced into lead wire grooves 3a and 3b in a chucking manner between a lever 4 and the pushing means 2 and formed and held therein. Since such methods, however, are forming methods based on the dimensions of the lead wires, in order to bend the lead wires as shown in FIG. 3, an additional length corresponding to the widths W of the contact portions of the pushing means must be provided in addition to the length L of a body member of an electric parts to reach the overall length of the part, thereby increasing the insertion pitch P on a printed circuit board. Therefore, the space required for each part when it is mounted on a printed circuit board must include the widths W, thereby making the printed circuit board larger and more costly than if such widths could be eliminated. Moreover the lead wires may be damaged by chucking between the pushing means 2 and the forming means 3. | {
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The invention relates to a turbine ring assembly for a turbine engine, the assembly comprising a plurality of ring sectors, each made of a single piece of ceramic matrix composite (CMC) material, together with a ring support structure.
The field of application of the invention is in particular that of gas turbine aeroengines. Nevertheless, the invention is applicable to other turbine engines, for example industrial turbines.
In gas turbine aeroengines, improving efficiency and reducing polluting emissions lead to reducing the weight of parts constituting the engine and to operating at ever-higher temperatures.
Ceramic matrix composite (CMC) materials are known for their good mechanical properties, which make them suitable for constituting structural elements, and they are also known for conserving those properties at high temperatures, thus constituting a viable alternative to the traditional use of metal to make parts.
The use of CMC parts in the hot portions of such engines has already been envisaged, for the above-mentioned reasons.
In particular, Document WO 2010/103213 discloses a turbine ring assembly for a turbine engine that comprises a plurality of ring sectors, each made of a single piece of CMC, each ring sector having a first portion forming an annular base with an inside face defining the inside face of the turbine ring and an outside face from which there extend two tab-forming portions having their ends engaged in housings in the ring support structure, the ring sectors possessing a section that is substantially π-shaped, and the ends of the tabs are held without radial clearance by the ring support structure.
In that document, the ring support structure is made of metal and is close to the flow passage for hot gas so that it is subjected to a considerable temperature rise. The metal structures are thus in a danger of being damaged by the high temperature of the gas in the passage.
Furthermore, CMC ring sectors can accept only very low levels of stress, they have high stiffness, and they expand much less than the metal ring support structure. Consequently, since according to the above-mentioned document the ring sectors are held without radial clearance, if ever they are subjected to very high temperatures they are weakened as a result of the mechanical stresses imposed by the differential expansion relative to the ring support structure. | {
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The present invention relates to a semiconductor memory device and more specifically to the circuit arrangement of a semiconductor memory device operations of which are synchronized with a high-frequency clock signal. This application is based on Japanese Patent Application No. 10-364613, filed Dec. 22, 1998, the content of which is incorporated herein by reference.
Such a semiconductor memory device as is synchronized with a high-frequency clock signal is referred hereinafter to as a synchronous memory. The circuit arrangement of a conventional synchronous memory 100 is shown in FIG. 1. The memory 100 is roughly divided into a memory core section 101 and an I/F circuit section.
The I/F circuit section includes right and left shift register sections 102 adjacent to the memory core section 101, right and left input/output (I/O) circuits 106 corresponding to the right and left shift register sections, a delayed locked loop (DLL) circuit 111, and a control logic circuit 112.
The DLL circuit 111 produces an internal write data control clock signal rclk in synchronization with an externally applied write clock signal RXCLK and an internal read data control clock signal tclk in synchronization with an externally applied read clock signal TXCLK.
The control logic circuit 112 performs logical operations on a protocol entered through an external command signal COMMAND to produce control signals for the memory.
The right and left I/O circuits 106 are responsive to the internal write data control signal rclk to take in serial write data DQ less than 0:7 greater than and DQ less than 8:15 greater than , respectively, from external I/O data lines and then output internal serial write data eWrite and oWrite to the shift register sections 102 each consisting of plural shift registers.
Further, the right and left I/O circuits are responsive to the internal read data control signal tclk to take in internal serial read data eRead and oRead from the left and right shift register sections, respectively, and then output serial read data DQ less than 0:7 greater than and DQ less than 8:15 greater than , respectively, onto the external I/O data lines.
Here, less than 0:7 greater than and less than 8:15 greater than represent the low-order eight bits and the high-order eight bits, respectively, of 16-bit data. The letters e and o affixed to Read and Write represent even-numbered and odd-numbered bits of data, respectively.
The shift register sections 102 are each responsive to a control signal to take in internal parallel read data RD less than 0:7 greater than output from the memory core section 101 in a read operation and to write internal parallel write data WD less than 0:7 greater than output therefrom into the memory core section in a write operation.
Thus, the right and left shift registers 102 convert internal parallel read data RD less than 0:7 greater than read from the memory core section 101 into internal serial read data eRead and oRead at read time and convert internal serial write data eWrite and oWrite from the I/O circuits 106 into internal parallel write data WD less than 0:7 greater than at write time.
The memory core section 101 includes, as in a normal DRAM circuit, a memory cell array, a sense amplifier, a row decoder, a column decoder, a redundancy fuse, and a DQ buffer.
In FIG. 2, there is illustrated, in the layout of the conventional synchronous memory, the flow of data from the memory core section 101 to the I/O circuits 106 with conversion from parallel form to serial form by the shift register sections 102. Here, the right and left I/O circuits 106 included in a peripheral circuit section 105 enclosed with dashed lines are consecutively numbered 0 through 7 and 8 through 15.
In writing into the memory core section 101, serial write data from the I/O circuits 106 are entered into the shift register sections 102 for conversion into parallel write data and the resulting parallel write data are written into the memory core section 101.
Thus, the flow of data in a write operation is the reverse of that in a read operation. In FIG. 2, therefore, there is illustrated the flow of data in a read operation by way of example.
In FIG. 2, four memory core sections 101 are placed above and below the peripheral circuit section 105. The left-hand memory core sections 101 are each allocated areas for eight bits in correspondence with the left-hand 8-bit I/O circuit 106 assigned consecutive numbers 0 through 7. Likewise, the right-hand memory core sections 101 are each allocated areas for eight bits in correspondence with the right-hand 8-bit I/O circuit 106 assigned consecutive numbers 8 through 15. As a result, a 16-bit synchronous memory is constituted as a whole.
In this manner, the cell array is allocated areas from (I/O)0 less than 0:7 greater than to (I/O)15 less than 0:7 greater than each of eight bits as shown in FIG. 2. If the synchronous memory is active, then either upper left and lower right memory core sections or lower left and upper right ones will be selected in combination by an address signal.
Data read from each memory core section in a parallel form, eight bits at a time, is converted to 8-bit serial data in the corresponding shift register section 102. The shift register section 102 is illustrated in detail in FIGS. 3A and 3B.
FIG. 3A shows the shift register section 102 in enlarged form. The shift register section 102 has shift registers 102a each corresponding to a respective one of the I/O circuits (I/O)0 through (I/O)7. Odd-numbered bits of data and even-numbered bits of data (hereinafter referred simply as to even and odd data) are shifted in the shift register section in synchronization with rising and falling edges, respectively, of the internal read data control clock tclk.
That is, eight-bit parallel read data of RD0 less than 0:7 greater than to RD7 less than 0:7 greater than read from the memory core section are entered into the shift registers 102a and odd serial read data of oRead0 to oRead7 and even serial read data of eRead0 to eRead7 are read from the shift registers 102a.
Odd serial write data of oWrite0 to oWrite7 and even serial write data of eWrite0 to eWrite7 are entered into the shift registers 102a and 8-bit parallel write data of WD0 less than 0:7 greater than to WD7 less than 0:7 greater than are output from the shift registers.
FIG. 3B shows the circuit arrangement of the shift register 102a, which includes a read register 107 and a write register 108.
The read register 107 includes first and second shift registers. The first shift register includes four cascade-connected flip-flops (FFs) 109 that receive odd parallel read data RD less than 1 greater than , RD less than 3 greater than , RD less than 5 greater than , and RD less than 7 greater than and output serial read data oRead. The second shift register includes four cascade-connected FFs 110 that receive even parallel read data RD less than 0 greater than , RD less than 2 greater than , RD less than 4 greater than , and RD less than 6 greater than and output serial read data eRead.
Likewise, the write register 108 includes first and second shift registers. The first shift register includes four cascade-connected FFs 109 that receive odd serial write data owrite and output odd parallel write data WD less than 1 greater than , WD less than 3 greater than , WD less than 5 greater than and WD less than 7 greater than . The second shift register includes four cascade-connected FFs 110 that receive even serial write data eWrite and output even parallel write data WD less than 0 greater than , WD less than 2 greater than , WD less than 4 greater than and WD less than 6 greater than .
Thus, the read register 107 and the write register 108 provide parallel-to-serial conversion and serial-to-parallel conversion, respectively.
Next, reference will be made to timing diagrams of FIGS. 4 through 7 to describe read and write operations of the synchronous memory in terms of one memory core section 101 and its associated shift register section 102 and I/O circuit 106.
First, an example of a read operation will be described with reference to FIG. 4. Eight-bit parallel read data RD less than 0:7 greater than is output from a memory core section 101 at a fixed time after the entry of a read command signal COMMAND.
The odd bits 1, 3, 5 and 7 of the 8-bit parallel read data RD less than 0:7 greater than are applied to the inputs of the respective FFs 109 in the read register 107 and then clocked out of the read register in synchronization with rising edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data oRead is performed.
On the other hand, the even-numbered bits 0, 2, 4 and 6 of the 8-bit parallel read data RD less than 0:7 greater than are applied to the inputs of the respective FFs 110 in the read register 107 and then clocked out of the read register in synchronization with falling edges of the internal read data control clock signal tclk, whereby conversion into 4-bit serial read data eRead is performed.
These serial read data oRead and eRead are then combined, so that 8-bit serial read data including bits numbered 0 through 7 is output to outside through the associated I/O circuit 106 of FIG. 2. In this manner, 8-bit serial read data is output in four cycles of the clock signal tclk. That is, 4-bit read data oRead and eRead can be alternately output using rising and falling edges of the clock signal tclk.
Another example of a read operation is illustrated in FIG. 5, which is a timing diagram for parallel-to-serial conversion using only rising edges of the internal read data control clock signal tclk. This approach requires eight cycles of the clock signal tclk for parallel-to-serial conversion of 8-bit data unlike the FIG. 4 case where both the rising and falling edges of the clock signal tclk are used.
Next, an example of a write operation will be described with reference to FIG. 6. Eight-bit serial write data is output from an I/O circuit at a fixed time after the entry of a write command signal COMMAND.
The even-numbered bits 0, 2, 4 and 6 of 8-bit serial write data from the I/O circuit are sequentially applied to the input of cascade connection of the FFs 110 in the write register 108 and then clocked into the write register in synchronization with rising edges of the internal write data control clock signal rclk, whereby conversion into 4-bit parallel write data ewrite is performed.
On the other hand, the odd-numbered bits 1, 3, 5 and 7 of the 8-bit serial write data from the I/O circuit are sequentially applied to the input of cascade connection of the FFs 109 in the write register 108 and then clocked into the write register in synchronization with falling edges of the internal write data control clock signal rclk, whereby conversion into 4-bit parallel write data owrite is performed.
By combining the outputs of the FFs 109 and 110 in the write register 108, serial-to-parallel converted write data WD less than 0:7 greater than including bits numbered 0 through 7 is output.
Another example of a write operation is illustrated in FIG. 7, which is a timing diagram for serial-to-parallel conversion based on only rising edges of the internal write data control clock signal rclk. This approach requires eight cycles of the clock signal rclk for serial-to-parallel conversion of 8-bit data unlike the case of FIG. 6 where both the rising and falling edges of the clock signal rclk are used.
Next, the configuration of the conventional synchronous memory will be described with reference to FIGS. 8A and 8B. FIG. 8A shows the pattern layout of the main circuit of the memory. Though not shown, pads connected to input/output terminals are placed in the middle of the chip.
The I/O circuits 106 are placed on the right and left of the DLL circuit 111. The control logic circuit 112 is placed above the DLL circuit. The shift register sections 102 are placed above the control logic circuit 112 and below the DLL circuit 111 and the I/O circuits 106 for data transfer to and from the memory sections 101 as indicated by arrows.
DQ buffers 103 and redundancy fuse circuits 104 are placed adjacent to the shift register sections 102. The redundancy fuse circuits are adapted to improve the manufacturing yield by providing redundancy for the memory core sections 101 and removing failed bits.
By placing each memory core section 101 and its associated shift register section 102 in the upper and lower portions of the chip symmetrically with respect to the central line, data lines and signal lines between each memory core section and its associated shift register section can be made symmetrical with respect to the central line and transfer times of data and signals over the data lines and signal lines in the upper and lower portions can be made equal to each other. The margin of read and write operations can therefore be improved. However, this configuration increases the area of the chip because of need of the two upper and lower shift register sections.
FIG. 8B is a block diagram of the memory core section 101. As with a normal semiconductor memory device, the memory core section 101 includes the DQ buffer 103, the fuse circuit 104, a memory cell array 113, a sense amplifier 114, a column decoder 115, and a row decoder 116. ADD indicates an address signal, RD read data, and WD write data.
The pattern layout can be modified such that the upper and lower memory core sections 101 share one shift register section 102. This conventional example is shown in FIG. 9. With this modified layout, a reduction in the chip area can be expected in comparison with the layout of FIG. 8, but the length of data lines and signal lines between the shared shift register section and the upper memory core section and the length of those between the shift register section and the lower memory core section will become different from each other. For this reason, a disadvantage arises in that the margin of operations of reading from and writing into the memory core section associated with longer and different length interconnections is reduced.
As described above, the conventional synchronous memory has a problem that, in order to make the signal transfer times for the upper and lower memory core sections equal to each other, two upper and lower shift registers are required and as a result the chip area increases.
With another conventional synchronous memory such that the upper and lower memory core sections share one shift register section, a reduction in the chip area can be expected, but the length of data lines and signal lines between the shared shift register section and the upper memory core section and the length of those between the shift register section and the lower memory core section differ from each other. For this reason, a disadvantage arises in that the margin of operations of reading from and writing into the memory core section associated with longer and different length interconnections is reduced and the symmetry of data/signal transmission time is lost.
It is therefore an object of the present invention to provide a synchronous memory having large write/read operation margin by placing memory core and shift register arrangements in the upper right and left portions and the lower right and left portions of a chip so that they are symmetrical not only in the up-and-down direction but in the right-and-left direction to ensure the symmetry of data/signal transmission time between each memory core and its associated shift register without increasing the chip area.
A semiconductor memory device of the present invention is a synchronous memory formed on a rectangular semiconductor chip and characterized in that a horizontally long peripheral circuit section including I/O circuits is placed in the middle of the chip and memory core, shift register arrangements are placed in the upper and lower portions of the chip so that the chip is symmetrical about the peripheral circuit section and the longitudinal line of the shift register section and the longitudinal line of the peripheral circuit section are perpendicular to each other.
The synchronous memory of the present invention in which the pattern layout has the up-and-down symmetry is further characterized by having the right-and-left symmetry.
In addition, the synchronous memory is characterized by optimizing the direction of flow of write/read data in the shift register section in order to reduce the length of interconnections between the peripheral circuit section and the shift register section which are perpendicular to each other on the chip.
In the description below, the right-and-left direction along a side of a rectangular semiconductor chip is referred to as the horizontal direction and the up-and-down direction along another side of the chip is referred to as the vertical direction. The shape of the semiconductor chip may be either square or rectangular.
Specifically, a semiconductor memory device of the present invention is formed on a rectangular semiconductor chip having horizontal and vertical sides and comprises: a peripheral circuit section including a plurality of I/O circuits and placed in the middle in the vertical direction of the chip so that its longitudinal line is oriented parallel to the horizontal direction of the chip; a shift register section placed on the chip symmetrically with respect to the center line of the peripheral circuit section along its longitudinal line so that its longitudinal line is perpendicular to the longitudinal line of the peripheral circuit section; and a memory core section including a memory cell array and placed adjacent to the shift register section along the longitudinal line of the shift register section.
Preferably, in the semiconductor memory device, the memory core section and the shift register section are placed on the chip symmetrically with respect to the vertical center line of the semiconductor chip.
Preferably, in the semiconductor memory device, the memory core section is placed adjacent to one side of the shift register section along its longitudinal line.
Preferably, in the semiconductor memory device, the memory core section is placed adjacent to both sides of the shift register section along its longitudinal line.
Preferably, in the semiconductor memory device, the memory core section comprises first and second memory cores placed adjacent to both sides of the shift register section and the shift register section comprises a first shift register section which operates in association with the first memory core and a second shift register section which operates in association with the second memory core.
Preferably, in the semiconductor memory device, the memory core section comprises first and second memory cores placed adjacent to both sides of the shift register and the shift register section operates in association with the first and second memory cores.
A semiconductor memory device of the present invention is formed on a rectangular semiconductor chip having horizontal and vertical sides and comprises: a peripheral circuit section including a plurality of I/O circuits and placed in the middle in the vertical direction of the chip so that its longitudinal line is oriented parallel to the horizontal direction of the chip; a shift register section placed on the chip symmetrically with respect to the center line of the peripheral circuit section along its longitudinal line so that its longitudinal line is perpendicular to the longitudinal line of the peripheral circuit section; and a memory core section including a memory cell array and placed adjacent to the shift register section along the longitudinal line of the shift register section, the shift register section including a plurality of shift registers which are arranged along the vertical direction of the chip and correspond one for one with the plurality of I/O circuits. The shift registers which correspond one for one with the I/O circuits are described in the sixteenth embodiment of the invention.
In a semiconductor memory device of the present invention, the shift register section includes a plurality of shift registers which are arranged along the vertical direction of the chip and correspond one for one with bits of write/read serial data. Such shift registers are described in the seventeenth embodiment of the present invention.
Preferably, the shift register section comprises a first shift register section having a plurality of shift registers which correspond one for one with even bits of the serial data and a second shift register section having a plurality of shift registers which correspond one for one with odd bits of the serial data, the first and second shift register sections being arranged independently.
Preferably, write/read data is transferred in one of the following transfer modes: a transfer mode in which, at data write time, serial data is transferred from a shift register which is close to the peripheral circuit section to a shift register which is far from the peripheral circuit section; a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register close to the peripheral circuit section; a transfer mode in which, at data write time, serial data is transferred from a shift register close to the peripheral circuit section to a shift register far from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section; and a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register far from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section.
This configuration ensures the symmetry of data lines and signal lines that connect the memory core section and the shift register section. Further, by optimizing the dividing arrangement of the memory core section and the shift register section and the data transfer mode of the shift register section, the length of the data lines and the signal lines is reduced, thus allowing the write/read operation margin to be obtained, the operating speed to be increased, the power dissipation to be reduced, and the chip size to be reduced.
Preferably, in the semiconductor memory device of the present invention, a write register forming a part of the shift register section is arranged such that a latch control signal (WRTLAT in FIG. 20) for a plurality of latch circuits is transferred in synchronization with an internal clock signal, bits of serial write data entered into the write register are taken into the latch circuits in a given order, and the bits of the write data are taken from the latch circuits in parallel, and, in the write data transfer mode of the shift register section, by the latch control signal entered into a shift register in the shift register section which is close to the peripheral circuit section being transferred toward a shift register far from the peripheral circuit section, bits of serial write data entered into a shift register close to the peripheral circuit section are sequentially taken into latch circuits from close to the peripheral circuit section to far from the peripheral circuit section.
In normal shift register-based serial-to-parallel conversion, bits of input serial data are sequentially taken into register blocks starting with the block far from the input of the shift register to the block close to the input of the shift register. In the write register stated above, bits of input serial data are sequentially taken into blocks starting with the block close to the input to the block far from the input.
Using this function, by entering serial write data into the write register block closest to the peripheral circuit section and outputting serial read data subjected to parallel-to-serial conversion in the read register from the read register block closest to the peripheral circuit section, the data lines and signal lines can be reduced in length.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter. | {
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U.S. patent application Ser. No. 10/743,932, filed Dec. 23, 2003, teaches a finished lubricant that has less than 8 weight percent VI improver made having a lubricating base oil made from Fischer Tropsch wax having particularly desired aromatic and cycloparaffinic molecular composition and at least one lubricant additive. This application, however, does not teach a lower ash lubricating oil containing no viscosity index improver that has a low cold cranking simulator viscosity.
U.S. patent application Ser. No. 10/949,779, filed Sep. 23, 2004, teaches a multigrade engine oil comprising: (a) a Fischer-Tropsch base oil characterized by a kinematic viscosity between about 2.5 and about 8 cSt at 100° C., and having a desired composition of cycloparaffin molecules; (b) a pour point depressing base oil blending component; and (c) an additive package designed to meet the specifications for ILSAC GF-3; and (d) no additional pour point depressant additive or viscosity index improver. Nothing is taught about blending lower ash lubricating oil suitable for use in a natural gas engine without any viscosity index improver and having a low cold cranking simulator viscosity.
PCT Applications WO 2004/053030 and PCT Application WO2004/033606 teach finished lubricants made using base oils made from Fischer-Tropsch wax that have high viscosity indexes and low cold cranking simulator viscosities. Nothing is taught about blending lower ash lubricating oils suitable for use in natural gas engines without any viscosity index improver.
Lower ash lubricating oil suitable for use in natural gas engines with improved cold crank properties over current SAE 40 oils is desired. In addition, customers want lower ash lubricating oils with better low temperature properties meeting SAE 15W-40 specifications. Most current natural gas engine oils (NGEO) meeting SAE 15W-40 specifications, for example, require the addition of viscosity index improvers that may shear in use. In addition, some natural gas original equipment manufacturers (OEMs) require that no conventional petroleum derived bright stock be used in the natural gas engine oil, so blends with good viscometric properties without conventional petroleum derived bright stock are preferred. | {
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Coaxial cables are widely used to carry high frequency electrical signals. Coaxial cables enjoy a relatively high bandwidth, low signal losses, are mechanically robust, and are relatively low cost. A coaxial cable typically includes an elongate inner conductor, a tubular outer conductor, and a dielectric separating the inner and outer conductors. For example, the dielectric may be a plastic foam material. An outer insulating jacket may also be applied to surround the outer conductor.
Coaxial cables may advantageously be used to connect to a tap at a ground pedestal or at an overhead line to carry signals from the tap to the customer. The tap is, in turn, connected to a trunk cable that typically serves a number of customers. Fiber optic, and electrical multi-conductor cables may alternately or additionally be so configured for such a customer drop application.
Typically an installer carries one or more relatively large reels of drop cable to an installation site to connect the customer to the trunk cable. The approximate length of cable, and some slack, that is needed for the particular drop installation, is manually pulled and then cut from the larger supply on the reel. Both ends of the cable are prepared by installing respective connectors onto ends of the cable. The connectors at the ends of the cable are then respectively coupled to mating connectors at the tap and also at the customer's interface. Unfortunately, this installation procedure is relatively time consuming and uses field-installed connectors that may not be as good and/or reliable as factory-installed connectors. Sometimes one or more of the connectors may not be installed properly. In addition, a considerable and uncontrolled amount of waste cable may be produced by this conventional installation approach.
Relatively long lengths of cable, such as for trunk applications, are typically designed in advance. Accordingly, a pre-connectorized cable can be made at the manufacturing facility with its attendant advantages. For example, U.S. Pat. No. 4,451,013 to Bedrosian discloses a reel for a pre-connectorized telephone cable.
Unfortunately, for drop cable applications, the labor intensive manual approach is typically used. Pre-connectorized cables are not typically available. In addition, there may be no convenient manner to store slack at the drop installation even if a pre-connectorized cable were used. | {
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There is a known solid state imaging device provided with a photoelectric conversion portion having a plurality of photosensitive regions to generate respective charges according to incidence of light, and a potential gradient forming portion having an electroconductive member arranged opposite to the photosensitive regions (e.g., cf. Patent Literature 1). In the solid state imaging device described in Patent Literature 1, the potential gradient forming portion forms a potential gradient becoming higher along a predetermined direction. The charges are moved by this potential gradient, thereby achieving increase of charge readout speed. | {
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1. The Field of the Invention
The present invention relates to dental bleaching compositions and methods for treating tooth surfaces. More particularly, the present invention is directed to a stable one-component viscous/gelled dental bleaching composition that has a high concentration of bleaching agent. The dental bleaching compositions of the present invention can optionally include a radiant-energy and/or heat-energy absorbing substance which can absorb these forms of energy and cause the bleaching agent to more quickly bleach the tooth surfaces.
2. The Relevant Technology
The use of certain foods and tobacco, the process of aging, diseases, trauma, medications, some congenital conditions, and environmental effects can cause teeth to become discolored. Because white or whitened teeth are usually considered to be aesthetically superior to stained or discolored teeth, there has been a heightened level of interest of late in developing compositions and methods for bleaching teeth.
A tooth is comprised of an inner dentin layer and an outer hard enamel layer that is slightly porous. The natural color of the tooth is opaque to translucent white or off-white.
Some dentrifices, like toothpastes, gels, and powders, contain active oxygen or hydrogen peroxide liberating bleaching agents. Such bleaching agents include peroxides, percarbonates and perborates of the alkali and alkaline earth metals or complex compounds containing hydrogen peroxide. Also, peroxide salts of the alkali or alkaline earth metals are known to be useful in whitening teeth.
The most commonly used dental bleaching agent is carbamide peroxide (CO(NH.sub.2).sub.2.H.sub.2 O.sub.2), also called urea hydrogen peroxide, hydrogen peroxide carbamide, and perhydrol-urea. Carbamide peroxide has been used by dental clinicians for several decades as an oral antiseptic. Tooth bleaching was an observed side effect of extended contact time. Over-the-counter compositions of 10% carbamide peroxide are available as "GLY-OXIDE.RTM." by Marion Laboratories and "PROXIGEL.RTM." by Reed and Carnrick. An extended-contact application of bleaching gel held in a dental tray is available as "OPALESCENCE.RTM." by Ultradent. Other bleaching agents such as peroxyacetic acid (CH.sub.3 C.dbd.OO--OH) and sodium perborate, are also known in the medical, dental and cosmetic arts.
Patients who have desired to have their teeth whitened have typically done so by applying a bleaching composition to the teeth by means of the dental tray for repeated treatments, or they had to submit to conventional in-office bleaching techniques that required from 4 to 10 visits to the dental office before clinically significant results were achieved. Less effective teeth whitening was also done by the use of toothpastes or polishes that were applied by brushing. Clinically significant results are quantifiable such as by measuring gray scale, L*, and as to yellowness or blueness, b*, in the CIE.RTM. system of color measurement or by equivalent methods.
Bleaching compositions have been manufactured in one-part and two-part systems. A one-part system consists of a compound in which the active bleachant is dispersed into inert components to form an emulsion or gel. One-part systems can also further consist of mixtures in which stabilizers are used to prevent premature decomposition of the peroxide in the bleaching composition. The advantage of a one-part system is ease of use and convenience. The main disadvantage is that prior art one-part viscous/gelled bleaching compositions generally contain relatively low concentrations of peroxide. High concentrations in pre-mixed gells have not been stable. Thus, current one-part systems have a low potency and are slow to react. Most one-part systems in the past have included active peroxide in a range of up to about 3.5% by weight. Due to the relatively low concentration of active bleaching agent in one-part systems, about 10 applications on average are necessary for effective bleaching.
In a two-part system, aqueous hydrogen peroxide is mixed with other components to achieve a preferred higher viscosity. These components are mixed just prior to bleaching due to the incompatibility of the other components with hydrogen peroxide. The main advantage of a two-part system is that it allows for much higher concentrations of active peroxide that cannot exist stably as a one-part system for incidental off-the-shelf use. This results in faster bleaching of the patient's teeth due to the higher peroxide concentration. Faster bleaching is desirable, especially where patient compliance with longer bleaching regimens is problematic, or if only one or a few teeth need individual bleaching.
Another example of a two-part system is microencapsulation of the bleaching agent and a stabilizer. The microcapsules would separate the bleaching agent from the carrier and other materials and would rupture only upon physical shear caused by a tooth brush. The dental bleaching effect of the microencapsulation system is only visible after prolonged use due to its low peroxide concentration or low activation rate.
Although positive results using the foregoing techniques have been reported, the effectiveness of the techniques depends upon such factors as type and intensity of the stain, bleaching agent contact time on the teeth, the amount of available active bleachant in the bleaching agent, and the persistence of the individual in applying the treatment until the desired result is accomplished.
Notwithstanding the foregoing advantages, there remain some important disadvantages to current one-part and two-part systems. A disadvantage to the two-part system is that the bleaching composition must be mixed on-site in the operatory immediately before application to the patient's tooth. Mixing requires additional time by the dental professional, which lowers efficiency and represents an extra preparatory procedure. Mixing in proper amounts is also important in order to yield consistent results.
Another disadvantage where high peroxide concentrations are used is that bleaching compositions that must be mixed on-site in the operatory subject the dental professional to the possibility of burns due to mixing splatter. Additionally, high concentrations of hydrogen peroxide are strong oxidizers.
Another disadvantage with two-part bleaching compositions is that, once mixed, the bleaching compositions must be used soon, since they are unstable and tend to decompose through the release of oxygen from the peroxide moieties. Often, the constituents of the bleaching compositions themselves accelerate decomposition rates. While such accelerants are useful in promoting faster bleaching, they yield a composition having a very short lifespan. Because known accelerants are chemical in nature, they cannot be added until bleaching is to commence. Otherwise the premature release of active oxygen will quickly decrease the potency of the bleaching composition. Moreover some accelerant(s) or peroxide indicators are unstable in that they themselves are consumed by the peroxide. The tendency of prior art accelerants or indicators to be themselves consumed has the effect of reducing the concentration of both the peroxide and the accelerant over a short period of time, thus reducing the effectiveness of each.
From the foregoing, it will be appreciated that what is needed in the art are stable, one-part, pre-mixed viscous/gelled bleaching compositions and methods for treating tooth surfaces that allow for greatly increased bleaching rates compared to existing one-part systems.
Additionally, it would be a significant advancement in the art to provide stable, one-part, pre-mixed viscous/gelled dental bleaching compositions for treating tooth surfaces that included means for accelerating the release of active oxygen from the bleaching agent when needed but which do not cause premature decomposition of the active dental bleaching agent or destruction of the bleaching agent activator.
It would still be a further advancement in the art to provide stable, one-part, pre-mixed viscous/gelled dental bleaching compositions that included higher concentrations of bleaching agent compared to existing one-part compositions that are made at the time of manufacture.
Such stable, one-part, pre-mixed dental bleaching compositions and methods for bleaching tooth surfaces are disclosed and claimed herein. | {
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This invention relates to phosphor compositions, and in particular to phosphor compositions excited by ultraviolet radiation to emit in the red region of the visible spectrum.
Europium activated yttrium oxide (YOE) is a well known red emitted phosphor. It is used in many devices such as cathode ray tubes and lamps. This phosphor though is quite expensive for large-scale use, especially in lamps. Other red-emitting phosphors are known, such as, calcium yttrium borate described by the formula CaYBO.sub.4 :Eu as disclosed by G. Blasse in The Journal Of Solid State Chemistry, Vol. 4, page 52, 1972. A problem with this phosphor is that its efficiency of photoluminescence under excitation by 254 nanometer ultraviolet is about 40% of the YOE phosphor, which is insufficient for lamp use. | {
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The present invention relates to a structure in an article for personal care like diapers, training pants, absorbent underpants, adult incontinence products, bandages and feminine hygiene products, which can accept and distribute liquid.
Personal care articles include such items as diapers, training pants, feminine hygiene products such as sanitary napkins, panty-liners and tampons, incontinence garments and devices, bandages and the like. The most basic design of all such articles typically includes a bodyside liner, an outercover and an absorbent core disposed between the bodyside liner and the outercover.
Personal care products must accept fluids quickly and hold them to reduce the possibility of leakage outside the product. The product must be flexible and have a pleasing feel on the skin, and even after liquid insult, must not become tight or bind the user. Unfortunately, while previous products have met many of these criteria to varying degrees, a number have not.
It has been found that continuous flow insults in feminine hygiene products average 1 ml/hr and are not literally continuous or constant, but rather variable in rate and may even pause during a cycle. xe2x80x9cGush flowxe2x80x9d is defined as a sudden heavy flow condition and occurs at flow rates of up to 1 ml/sec. During a gush, 1-5 ml of fluid is released from the body onto the product. The term xe2x80x9ccontinuous flowxe2x80x9d is used to define any flow which falls outside of the definition of gush flow.
Combining continuous and gush flow conditions results in variable flow. Essentially, xe2x80x9cvariable flowxe2x80x9d is defined as continuous flow with intermittent gush flow occurrences. FIG. 1 illustrates the differences between variable flow (diamonds) and continuous flow (squares) over the life of a single product where flow rate volume is on the y-axis in g/hr and time is on the x-axis in hours.
The response to this problem is termed xe2x80x9cvariable flow managementxe2x80x9d and is defined as the ability to absorb and contain continuous and light flow (1-2 ml/hr) as well as multiple gushes or sudden heavy flow insults (1 ml/sec with a total volume of 1-5 ml) over the life of the product.
Many feminine care cover materials, for example, have low z-directional conductivity, low surface energy, low void volume, and provide little separation between the absorbent core and the user due to their two dimensional structure. Consequently, these covers result in slow and incomplete intake, high rewet, and large surface stains. In addition, typical intake or acquisition layers are low density, high void volume structures which are ideal for fast fluid intake, but because these structures typically have low capillarity, fluid is not adequately desorbed from the cover material, resulting in smearing and surface wetness. Materials which enhance cover desorption are typically high density, high capillarity materials, but because these materials have low void volume and low z-directional permeability, they inherently retard fluid intake.
There remains a need to address variable flow management by developing on an intake/distribution material which has the void volume necessary for fast intake and the high capillarity desired for sufficient cover desorption (i.e. surface dryness) while maintaining an appropriate capillary structure for fluid distribution.
An objective of this invention is, therefore, to provide such an intake/distribution material to manage a wide variety of flow conditions including sudden heavy flow insults, or gushes.
The objects of the invention are achieved by a airlaid fabric layer and spunbond nonwoven fabric transfer delay layer which have been joined by aperturing or xe2x80x9cco-aperturedxe2x80x9d. The result is improved multiple intake performance and a clean and dry cover surface during use in a feminine hygiene product. The material technology developments surrounding variable flow management focus on attaining the proper material structure and property balance necessary to achieve fast intake and improve cover desorption, cover staining, and rewet characteristics. These functional properties are provided through improved material technologies and product construction. | {
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The International Organization for Standardization is currently developing a standard specifying the coded representation of video for digital storage media, supporting a continuous data transfer rate of 1.5 Mbits/sec., which standard is described in the document ISO-IEC JTC1/SC2/WG11; CODING OF MOVING PICTURES AND ASSOCIATED AUDIO; MPEG90/176 Rev. 2, Dec. 18, 1990. This format has become known as MPEG. According to this format sequences of frames are divided into groups, and respective frames within each group are encoded according to one of a plurality of coding modes. Typically the coding modes include intraframe coding, (I frames) and two types of interframe predictive coding (P and B frames). In all modes only odd fields are encoded, the even fields being discarded.
The Advanced Television Research Consortium (ATRC) in the United States has modified the MPEG format for transmission of high definition television (HDTV) signals in digital form. Generally, the initial signal coding of this HDTV signal is similar to MPEG except that the pixel resolution, and data rates are increased, and both odd and even frames of each field are coded. In the HDTV system the coded signal is prioritized between a higher and a lower priority channel for transmission. Coded data having apparent greater importance to picture reproduction is transmitted with a given power level and coded data of lesser importance is transmitted with a lesser power level, to minimize cochannel interference.
FIG. 1 is a pictorial representation of the coding format prior to prioritization. The frame sequence is merely representative. The letters I, P, and B above respective frames indicate the coding mode for the respective frame. The frame sequence is divided into groups of frames (GOF) each of which includes the same coding sequence. Each frame of coded data is divided into slices representing, for example, 16 image lines. Each slice is divided into macroblocks each of which represents, for example, a 16.times.16 matrix of pixels. Each macroblock is divided into 6 blocks including four blocks of information relating to luminance signal and two blocks of information relating to chrominance signal. The luminance and chrominance information are coded separately and then combined for transmission. The luminance blocks include data relating to respective 8.times.8 matrices of pixels. Each chrominance block comprises and 8.times.8 matrix of data relating to the entire 16.times.16 matrix of pixels represented by the macroblock.
Blocks of data, encoded according to intraframe coding, consist of matrices of Discrete Cosine Coefficients. That is, respective 8.times.8 blocks of pixels are subjected to a Discrete Cosine Transform (DCT) to provide coded signal. The coefficients are subjected to adaptive quantization, and before being applied to the priority processor are run-length and variable-length encoded. Hence respective blocks of transmitted data may include fewer than an 8.times.8 matrix of codewords. Macro blocks of intraframe encoded data, will include, in addition to the DCT coefficients, information such as the level of quantization employed, a macroblock address or location indicator, and a macroblock type.
Blocks of data encoded according to P or B interframe coding also consist of matrices of Discrete Cosine Coefficients. In this instance however the coefficients represent residues or differences between a predicted 8.times.8 pixel matrix and the actual 8.times.8 pixel matrix. These coefficients are also subjected to quantization and run- and variable-length coding. In the frame sequence I and P frames are designated anchor frames. Each P frame is predicted from the lastmost occurring anchor frame. Each B frame is predicted from one or both of the anchor frames between which it is disposed. The predictive coding process involves generating displacement vectors which indicate which block of an anchor frame most closely matches the block of the predicted frame currently being coded. The pixel data of the matched block in the anchor frame is subtracted, on a pixel-by-pixel basis, from the block of the frame being encoded, to develop the residues. The transformed residues and the vectors comprise the coded data for the predictive frames. As for intraframe coded frames the macroblocks include quantization, address and type information. Note that even though a frame is predictive encoded, if no reasonable block matches can be found, a particular block or macroblock in the predictive frame may be intraframe coded. In addition certain ones of the macroblocks may not be encoded. Macroblocks are skipped by increasing the address of the next coded macroblock.
After the video data is coded, it is arranged according to an MPEG-like protocol. The MPEG hierarchical format includes a plurality of layers each with respective header information as shown in FIG. 2. Nominally each header includes a start code, data related to the respective layer and provision for adding header extensions. Much of the header information (as indicated in the referenced MPEG document) is required for synchronization purposes in an MPEG systems environment. For purposes of providing a compressed video signal for a digital HDTV simulcast system, only descriptive header information is required, that is start codes and optional extensions may be excluded.
When referring to the MPEG-like signal produced by the present system what is meant is that a) successive fields/frames of video signal are encoded according to an I, P, B coding sequence, and b) coded data at the picture level is encoded in MPEG-like slices or group of blocks albeit that the number of slices per field/frame may differ and the number of macro blocks per slice may differ.
The coded output signal of the present system is segmented in groups of fields/frames (GOF) illustrated by the row of boxes L1 (FIG. 2). Each GOF (L2) includes a header followed by segments of picture data. The GOF header includes data related to the horizontal and vertical picture size, the aspect ratio, the field/frame rate, the bit rate, etc.
The picture data (L3) corresponding to respective fields/frames includes a header followed by slice data (L4). The picture header includes a field/frame number and a picture code type. Each slice (L4) includes a header followed by a plurality of blocks of data MBi. The slice header includes a group number and a quantization parameter.
Each block MBi (L5) represents a macroblock and includes a header followed by motion vectors and coded coefficients. The MBi headers include a macroblock address, a macroblock type and a quantization parameter. The coded coefficients are illustrated in layer L6. Note each macroblock is comprised of 6 blocks, including four luminance blocks, one U chrominance block and one V chrominance block.
The block coefficients are provided one block at a time with the DCT, DC coefficient occurring first followed by respective DCT AC coefficients in the order of their relative importance. An end of block code EOB is appended at the end of each successively occurring block of data.
Compressed video data hierarchically formatted as indicated in FIG. 2 is applied to a priority processor, wherein the coded data is parsed between a high priority channel HP and a low priority channel LP. High priority information is that information, the loss or corruption of which, would create the greatest degradation in reproduced images. Stated conversely, it is the least data needed to create an image, albeit less than a perfect image. Low priority information is the remaining information. The high priority information includes substantially all of the header information included in the different hierarchical levels plus the DC coefficients of the respective blocks and a portion of the AC coefficients of the respective blocks (level 6, FIG. 2).
For priority processing purposes, the respective types of encoded data are assigned priority classes or types. For example all information above slice header information (including the slice identifier, slice quantization parameter etc.) are assigned priority type "0". Macroblock header data is assigned priority type "1". Motion vectors are assigned priority type "2". Priority type "3" may be reserved. The coded block pattern is assigned priority type "4". DC DCT coefficients are assigned priority type "5" and successive codewords representing higher order DCT coefficients are assigned priority types "6" to "68". The priority processor determines, according to the relative amounts of higher and lower priority data, the priority types which will be allocated to the high and low priority channels. Note that the priority classification is indicative of the relative importance of the particular types of data with priority type "0" being the most important. The processor in effect determines a priority break point (PBP) which corresponds to the class or type number above which all data is designated to the low priority channel. The remaining type data is allocated to the high priority channel. Refer to FIG. 2 and assume that for a particular macroblock the PBP is determined to be "5", so that the DC coefficients and all hierarchically higher data is to be allocated to the HP channel, and all AC coefficients and the EOB codes are assigned to the LP channel. For transmission purposes all the HP codewords are concatenated in bit-serial form without demarcation of data from respective blocks. In addition, the codewords are variable length encoded and there are no separations between codewords (in order to realize the greatest effective bandwidth in a limited bandwidth channel). The PBP for corresponding macroblocks is transmitted so that the receiver has the requisite information for separating the HP data amongst the respective blocks. In the LP channel, data from respective blocks is separated by EOB codes.
The HP and LP compressed video data are applied to a transport processor which a) segments the HP and LP data streams into respective HP and LP transport blocks, b) performs a parity or cyclic redundancy check on each transport block and appends the appropriate parity check bits thereto, and c) multiplexes the auxiliary data with the HP or LP video data. The parity check bits are utilized by the receiver for isolating errors in conjunction with synchronizing header information and for providing error concealment in the event of uncorrectable bit errors in the received data.
FIG. 3 illustrates the format of the signal provided by the transport processor. Respective transport blocks may include more or less than a slice of data. Thus a particular transport block may include data from the end of one slice and data from the beginning of the next subsequent slice. Transport blocks including video data may be interleaved with transport blocks containing other data, e.g., audio. Each transport block includes a service type header ST which indicates the type of information included in the respective transport block. In this example the ST header is an 8-bit word which indicates whether the data is HP or LP, and whether the information is audio, video or auxiliary data.
Each transport block includes a transport header TH immediately following the ST header. For the LP channel the transport header includes a 7-bit macroblock pointer, an 18-bit identifier and a 7-bit record header (RH) pointer. The transport header of the HP channel includes only an 8-bit record header (RH) pointer. The macroblock pointer is used for segmented macroblock or record header components, and points to the start of the next decodable component. For example, if the particular transport block includes macroblock data associated with the end of slice n and the beginning of slice n+1, the data from slice n is placed adjacent the transport header and the pointer indicates that the next decodable data is adjacent the transport header TH. Conversely, if a record header RH is adjacent the TH, the first pointer indicates the byte position following the record header RH. A zero valued macroblock pointer indicates that the transport block has no macroblock entry point.
The transport block may include none, one or more than one record header. A record header occurs at the beginning of each slice of macroblock data in the HP and LP channel. No record headers are included in transport blocks that include only video data header information. The record header (RH) pointer points to the byte position containing the start of the first record header in the transport block. A zero valued RH pointer indicates that there are no record headers in the transport block. If both the record header pointer and the macroblock pointer are zero valued, this state indicates that the transport block includes only video data header information.
The 18-bit identifier in the LP transport header identifies the current frame type, the frame number (modulo 32), the current slice number, and the first macroblock contained in the transport block.
Following the transport header is either a record header, RH, or data. As indicated in FIG. 3 the record header for the video data in the HP channel includes the following information: A 1-bit FLAG which indicates if a header extension, EXTEND, is present. Following the FLAG is an identifier IDENTITY, which indicates a) the field/frame type I, B or P; b) a field/frame number (modulo 32) FRAME ID; and c) a slice number (modulo 64) SLICE IDENTITY. Following the identifier the record header includes a macroblock priority break point indicator, PBP. The PBP indicates the codeword class, developed by the analyzer 152 of the priority selector, for dividing the codewords between the HP and LP channels. Lastly, an optional header extension may be included in the HP record header.
The record header incorporated in the LP channel includes only an identifier, IDENTITY, similar to the identifier implemented in the HP channel.
Each transport block is terminated with a 16-bit frame check sequence, FCS, which is calculated over all bits in the transport block. The FCS may be generated using a cyclic redundancy code.
The transport blocks of information are applied to respective forward error encoding elements which a) perform REED SOLOMON forward error correction encoding independently to the respective data streams; b) interleave blocks of data to preclude large error bursts from corrupting a large contiguous area of a reproduced image; and c) appends, e.g., Barker codes to the data for synchronizing the data stream at the receiver.
A receiver, responsive to transmitted signals which are formatted as indicated above, includes apparatus for performing inverse prioritization and inverse coding. Inverse prioritization, or recombining of the HP and LP data must be performed before decoding can be accomplished, because the decoder expects to see data in a predetermined format (similar to that shown in FIG. 2). It should readily be appreciated that at least a portion of the received signal will be corrupted by the transmission process. Consider that the PBP code in a HP transport block is lost. Without this PBP code, information corresponding to the respective blocks of a macroblock cannot be separated. As a result a considerable portion of the information contained in the HP transport block may be rendered useless. In addition information in the LP transport block, corresponding to blocks contained in the HP transport block, is also rendered unusable. In fact, the loss of a single PBP codeword contained in a HP transport block can render otherwise valid data for an entire slice useless. A second example is the loss of, for example, the codeword in a picture header which designates the frame coding type. Without this codeword an entire frame of coded data is rendered unusable or at least unreliable. | {
"pile_set_name": "USPTO Backgrounds"
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Field of Disclosure
The present disclosure relates to a vehicle seat. More particularly, the present disclosure relates to a bicycle seat.
Description of Related Art
A bicycle seat is one of the most important parts of a bicycle touching a rider riding the bicycle. The fit of a bicycle seat and the adjustment of a rider's position on the bicycle have close relationships with the rider's overall performance, riding posture and body gravity.
Prior arts attempt to solve this problem of rider's positioning on the bicycle seat. Some manufacturers and designers install a spring support element under the bicycle seat, so that the sore buttocks or tail bone of rider can avoid shock. However, the spring support element will cause resetting shock and pressure to the buttocks or the tail bone of the rider who sitting on the bicycle seat for extended periods of time.
As is known, another bicycle seat is improved by arranging a padding, in which the padding generally is formed from a soft material, and the padding is deformed by a sitting pressure. However, the padding has a large amount of deformation under pressure. The padding is not always suitable to provide a comfortable characteristic to the rider. Furthermore, this kind of “padding” apparatus is usually designed to be softer and thicker. But the padding is too thick to fit the needs of those who need adequate support to finish a long cycling. When the padding has supported a rider for a long time, the padding will increase friction area and prolonged friction to the buttocks or the tail bone of the rider.
On the other hand, if a padding is designed to be hard and thin, the padding will reduce the friction area and cause prolonged friction to the buttocks or the tail bone. However, when the padding has supported a rider for a long time, the padding will cause the pain from concentrated and prolonged pressure to a buttocks or a tail bone of the rider. | {
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Some surgical staplers are operable to clamp down on one or more layers of patient tissue, form staples through the layers of tissue to substantially seal the layers of tissue together near the formed staples, and cut through the layers of tissue for forming severed ends of operatively sealed tissue. An exemplary stapling instrument may include a pair of cooperating elongate jaw members, where each jaw member may be adapted to be inserted into a patient and positioned relative to tissue that is to be stapled and/or incised. One of the jaw members may support a staple cartridge with at least two laterally spaced rows of staples contained therein, and the other jaw member may support an anvil with staple-forming pockets aligned with the rows of staples in the staple cartridge. Generally, the stapling instrument may further include a pusher bar and a knife blade that are slidable relative to the jaw members to sequentially or simultaneously eject the staples from the staple cartridge via camming surfaces on the pusher bar and/or camming surfaces on a wedge sled that is pushed by the pusher bar. The camming surfaces may be configured to activate one or more staple drivers carried by the cartridge and associated with the staples in order to push the staples against the anvil and form laterally spaced rows of deformed staples in the tissue gripped between the jaw members. Such rows may be arranged as linear rows and/or arcuate rows for sequentially or simultaneously stapling and cutting the tissue of the patient in the form of a predetermined pattern. The knife blade may trail the camming surfaces and cut the tissue along a linear or arcuate line between the rows of staples formed in the tissue.
Merely exemplary surgical staplers are disclosed in U.S. Pat. No. 6,988,650, entitled “Retaining Pin Lever Advancement Mechanism for a Curved Cutter Stapler,” issued Jan. 24, 2006; U.S. Pat. No. 7,134,587, entitled “Knife Retraction Arm for a Curved Cutter Stapler,” issued Nov. 14, 2006; U.S. Pat. No. 7,147,139, entitled “Closure Plate Lockout for a Curved Cutter Stapler,” issued Dec. 12, 2006, U.S. Pat. No. 7,147,140, entitled “Cartridge Retainer for a Curved Cutter Stapler,” issued Dec. 12, 2006; U.S. Pat. No. 7,204,404, entitled “Slotted Pins Guiding Knife in a Curved Cutter Stapler,” issued Apr. 17, 2007; and U.S. Pat. No. 7,207,472, entitled “Cartridge with Locking Knife for a Curved Cutter Stapler,” issued Apr. 24, 2007. The disclosure of each of the above-cited U.S. patents is incorporated by reference herein. Additional merely exemplary surgical staplers are disclosed in U.S. Pat. Pub. No. 2005/0139636, entitled “Replaceable Cartridge Module for a Surgical Stapling and Cutting Instrument,” published on Jun. 30, 2005, now abandoned; U.S. Pat. Pub. No. 2005/0143759, entitled “Curved Cutter Stapler Shaped for Male Pelvis,” published on Jun. 30, 2005, now abandoned; and U.S. Pat. Pub. No. 2005/0145672, entitled “Curved Cutter Stapler with Aligned Tissue Retention Feature,” published on Jul. 7, 2005, now abandoned. The disclosure of each of the above-cited U.S. patent Publications is incorporated by reference herein.
A surgical stapler may be inserted into a patient to perform colorectal surgery. Such procedures may include the use of the stapler to operatively seal, sever, and remove the colon of the patient, in whole or in part. For instance, a proctocolectomy may be performed during a lower anterior resection (“LAW”) for treating and inhibiting the spread of colorectal cancer cells. Of course, surgical staplers may be used in various other settings and procedures.
While various kinds of surgical stapling instruments and associated components have been made and used, it is believed that no one prior to the inventor(s) has made or used the invention described in the appended claims.
The drawings are not intended to be limiting in any way, and it is contemplated that various embodiments of the invention may be carried out in a variety of other ways, including those not necessarily depicted in the drawings. The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention; it being understood, however, that this invention is not limited to the precise arrangements shown. | {
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Surgery, whether of the spine or other areas of the body, is often complex and routinely involves the need for highly experienced medical staff, in addition to well-designed and well-manufactured implants, made to exacting specifications. Often the implants take the form of various types of hardware. In the area of spinal fixation, for example, various spinal fixation devices have been developed in the art. Some examples of such fixation devices include spinal rods, plates, corpectomy cages, and intervertebral discs, to name but a few. Spinal fixation rods are fixation devices configured to fix adjacent vertebrae of a spine relative to each other. The rods provide stabilization of the spine till fusion occurs. The spinal fixation rods are often used in spinal surgeries to repair spinal abnormalities, whether related to injury or otherwise. The spinal rods are configured to attach to the vertebrae using, for example, anchoring devices like pedicle screws and hooks.
Patients often experience extreme and debilitating pain because of spinal column injuries or from spinal column disorders such as spondylolisthesis and scoliosis. Pain may be attributed to issues of the spine as related to degeneration, deformity, and/or injury. Often a typical course of treatment involves surgical spinal fixation utilizing spinal fixation rods that mechanically immobilize areas of the spine causing, ideally, the eventual fusion of the treated vertebrae.
Sometimes additional surgical procedures, known as revision surgeries, become necessary. Several causes exist for the need for revision surgeries. For example, pseudarthrosis (failure to achieve solid fusion) may have occurred, which can be due to various causes such as poor tissue healing, improper implant placement or securement, implant failure, or to patient-related factors. Sometimes revision surgeries are indicated even after successful initial surgeries, given that the function and shape of the spine can deteriorate with age. Also, after prolonged use, the spinal fixation rods may move or become dislodged or unstable, or even bend or break.
Revision surgery is also required to treat adjacent segment disease (“ASD”). Spinal fusion recipients may be at risk for developing ASD, a condition in which the motion segments adjacent to the fused vertebral segments experience higher rates of degeneration or deterioration due to an increase in vertebral loading, higher intradiscal pressures, increased range of motion, and increased facet motion. Treatment options for ASD begin with determining whether the primary fusion is intact. If so, then a revision surgery with a revision connector is a likely course of action.
When considering spinal fusion revision surgery options, a few revision connectors are known, such as the “Revere Addition Revision System” and the “Expedium Universal Connector”. However, these connectors suffer from various drawbacks. First, these prior connectors are difficult to connect to the spinal level above the targeted level. This may be due to scar tissue or fusion mass that has developed in the lateral “gutters” across the transverse process. Second, such connectors add significant profile to the implant, both laterally and in height. Increased height can cause problems post-surgery when patients can feel the implants under their skin. Sometimes this leads to deep superficial pain. Third, prior art revision connectors do not achieve adequate stability in-line with the primary rod. Fourth, some prior art connectors are not ideal for minimally invasive surgical implantation techniques.
What is needed is a universal revision connector that is easy to install, with minimal profile, and that can sit in-line, nearly in-line, and/or at desired angles with the primary fusion rod. The connector ideally minimizes the disruption of the previous fusion mass and limposes less violation of the scar tissue. The stabilization may be extended to the next level above or below the fusion. Additional benefit is also achieved with a connector that can be inserted percutaneously. Ideally, a connector is desired that is not only suitable for revision surgeries, but also for primary fusion surgeries. The present connector provides vast improvement over such existing revision connectors. | {
"pile_set_name": "USPTO Backgrounds"
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The instant invention relates to a novel wafer type semiconductor and a forming method therefor. More particularly, this invention relates to a semiconductor including a high resistance layer and wherein resistance layer formation is effected by selective diffusion from one wafer layer to another.
Prior wafer type semiconductor devices generally include a silicon substrate with successive layers of an insulating film and doped polycrystalline silicon deposited thereon. Conventional dopants for the polycrystalline silicon layer are B.sub.2 H.sub.6 and PH.sub.3.
There is a constant and chronic need for wafer type semiconductors with uniformly high resistances of several meg-ohms. cm and specific resistivities of several hundred thousand ohms/cc. Heretofore known doped polycrystalline silicon devices have not exhibited the uniform qualities desired.
Accordingly, this invention provides a wafer type semiconductor including a doped polycrystalline silicon layer which exhibits a uniformly high resistance and specific resistivity. Moreover, these wafer type semiconductors may be mass-produced with minimum variation between wafers and the resistance thereof. | {
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The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to organization of memory arrays for global bit-line architecture in high-performance semiconductor memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
As memory sizes continue to increase, satisfying the demands for high-speed access of memory arrays becomes increasingly difficult. Increasing memory sizes have been made possible in large part by continuing advances in semiconductor fabrication, i.e., placing more transistors and interconnect lines in the same die area. However, reduced dimensions of transistors leads to lower drive while reduced dimensions of interconnect lines leads to increased resistance. Managing this reduced drive and higher resistance through array organization thus becomes an important factor in providing high-speed access in high-performance memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate array architectures for high-performance memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Various embodiments of the invention have architectures suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Memory devices in accordance with the various embodiments of the invention include blocks of memory cells arranged in columns with each column of memory cells coupled to a main bit line. Such memory devices further include sector bit lines having multiple main bit lines coupled to each sector bit line through selective coupling devices with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is coupled to a global bit line through a selective coupling device, with each global bit line coupled to more than one sensing device through the selective coupling devices. For embodiments having multiple sectors, the global bit lines may extend to more than one sector. The global bit lines are multiplexed and input to helper flip-flops for output to the data output registers of the memory device. This array organization permits tight packing of individual memory cells with high-speed access capabilities.
For one embodiment, the invention provides a memory array. The memory array includes a first memory block having columns of memory cells coupled to main bit lines of the first memory block, a second memory block having columns of memory cells coupled to main bit lines of the second memory block, sector bit lines coupled to main bit lines in both memory blocks, sensing devices coupled to the sector bit lines, and at least one global bit line selectively coupled to the sensing devices. Each sector bit line is selectively coupled to at least two main bit lines of each memory block.
For another embodiment, the invention provides a memory bank. The memory bank includes a first number of memory sectors each having a second number of memory blocks, each memory block having a third number of columns of non-volatile memory cells with each column of non-volatile memory cells coupled to a main bit line. The memory bank further includes a fourth number of sector bit lines in each memory sector, wherein each sector bit line extends to each memory block in its associated memory sector and wherein the fourth number is one-half the third number. The memory bank still further includes a plurality of block pass transistors, wherein one block pass transistor is coupled between each main bit line and a sector bit line to selectively couple each main bit line to a sector bit line, and wherein each main bit line is selectively coupled to only one sector bit line and each sector bit line is selectively coupled to two main bit lines in each memory block. The memory bank still further includes a plurality of sense amplifiers in each memory sector, wherein each sense amplifier is coupled to two sector bit lines in its associated memory sector, and a plurality of global bit lines, wherein each output of a sense amplifier is coupled to only one global bit line through a selective coupling device and each global bit line is coupled to an output of more than one sense amplifier in each memory sector of the memory bank through selective coupling devices.
For still another embodiment, the invention provides a memory array. The memory array includes at least one memory bank, each memory bank having at least one memory sector. Each memory sector includes at least two memory blocks, each memory block having columns of non-volatile memory cells coupled to a plurality of main bit lines and a plurality of sector bit lines, wherein each sector bit line extends to each memory block of its associated memory sector. Each memory sector further includes a plurality of block pass transistors coupled between each plurality of main bit lines and the plurality of sector bit lines to selectively couple each main bit line to a sector bit line, wherein each main bit line is selectively coupled to only one sector bit line of its associated memory sector and each sector bit line is selectively coupled to more than one main bit line of its associated memory sector. Each memory sector still further includes a plurality of sense amplifiers coupled to the plurality of sector bit lines, wherein each sense amplifier is coupled to two sector bit lines of its associated memory sector, and a plurality of global bit lines, wherein an output of each sense amplifier is selectively coupled to only one global bit line and each global bit line is selectively coupled to an output of more than one sense amplifier of each memory sector of its associated memory bank.
For a further embodiment, the invention provides a synchronous flash memory device. The memory device includes a plurality of memory banks containing non-volatile flash memory cells and a command execution logic coupled to the plurality of memory banks for receiving at least a system clock input signal and for generating commands to control operations performed on the plurality of memory banks for synchronization to a system clock. Each memory bank includes a first number of memory sectors each having a second number of memory blocks, with each memory block having a third number of columns of non-volatile flash memory cells where each column of non-volatile flash memory cells is coupled to a main bit line. Each memory bank further includes a fourth number of sector bit lines in each memory sector, wherein each sector bit line extends to each memory block in its associated memory sector and wherein the fourth number is one-half the third number. Each sector bit line is selectively coupled to two main bit lines in each memory block while each main bit line is selectively coupled to only one sector bit line. Each memory bank further includes a plurality of sense amplifiers in each memory sector, wherein each sense amplifier is coupled to two sector bit lines in its associated memory sector, and a plurality of global bit lines, wherein an output of each sense amplifier is selectively coupled to only one global bit line and each global bit line is selectively coupled to an output of more than one sense amplifier in each memory sector of the memory bank.
The invention further provides methods and apparatus of varying scope. | {
"pile_set_name": "USPTO Backgrounds"
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The present invention relates to a method of improving the control behavior of an anti-lock and/or traction-slip controlled brake system, wherein the rotational behavior of the individual wheels is measured and evaluated for determining a vehicle reference speed, the wheel slip, the deceleration and acceleration of the individual wheels and, if required, other control quantities, and wherein threshold values of the wheel slip are predefined for the commencement of the control.
Brake systems with electronic anti-lock control (ABS) are nowadays included in the standard equipment of a great number of automotive vehicles. Also, extension of the ABS to traction slip control is no rare occurrence. In systems of this type the rotational behavior of the individual wheels is measured by means of wheel sensors and evaluated by electronic circuits to generate the control quantities and braking pressure control signals. Among these control quantities which result from the wheel rotational behavior are mainly wheel slip, wheel speed, wheel deceleration and wheel acceleration and a so-called vehicle reference speed which is defined by logical combining of the individual wheel speeds.
Identifying the actual control situation from the data provided by the individual wheel sensors and the consistent controlling of the braking pressure for anti-lock control or traction slip control is always difficult when the interpretation of the rotational behavior of the wheels does not permit a definite indication of the instantaneous road situation and the vehicle behavior. Further, it is known that disturbances on the road surface or road surface irregularities of any type may cause misinformation of the controller or the evaluating circuit and undesirable control operations or variations in the control which have adverse effects on the control. This is because deceleration and acceleration actions or slip signals occur on the individual vehicle wheels due to the road disturbances which are interpreted by the controller as instabilities of the wheel run.
Road surface disturbances or irregularities of the abovementioned type impair the ABS function. The ABS may even respond when the brake is not applied as soon as the ABS identification thresholds, which are slip or deceleration thresholds, are exceeded. When the brake is applied subsequently in the current ABS control, relatively great yaw torques may be caused which impair the driving stability of the vehicle. Also, the vehicle deceleration which is achievable in the given situation in an optimal braking operation will not be reached. Similar difficulties or discrepancies from the optimal behavior occur during traction slip control operations.
Therefore, an object of the present invention is to suppress the effects of various types of road irregularities on the control function of an ABS or TCS system and to thereby improve the control behavior of the ABS or TCS system. The objective is to achieve this improvement without disadvantages for the control sensitivity and control quality in other situations. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
The present invention relates to a hinge, and more particularly to a triple positioning hinge that is compact and securely retains a monitor of a portable electronic device at three determined positions permanently.
2. Description of Related Art
A hinge is mounted between a base and a monitor of a portable electronic device and allows the monitor to rotate relative to the base for convenience of use.
Later, the hinges are further designed to have positioning elements that help the monitor of the portable electronic device to hold the monitor at an optimum angle to facilitate users to watch. However, the positioning elements of the conventional hinge normally positions the monitor at a single angle, so if the monitor is required to be position at a folded and an unfolded positions, the conventional hinge has to be provided with extra retaining components. As a result, the conventional hinges are generally constructional complicated and bulky. Moreover, deformation may occur in the components of the conventional hinges after a long-term of use and gradually cause the conventional hinges to lose the ability of securely holding the monitors.
To overcome the shortcomings, the present invention provides a triple positioning hinge to obviate or mitigate the aforementioned problems. | {
"pile_set_name": "USPTO Backgrounds"
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Bone plates can be engaged to adjacent bony portions of a bone or of a bony segment to stabilize the bony portions. Anchors or fasteners, such as bone screws, can be used to engage bone plates to bony portions. To prevent the anchors from backing out of the plate, various retaining devices have been developed for engagement or manipulation relative to the plate adjacent to or around the bone anchors. Measures taken to retain the screws in the bone plate and keep the screws engaged in the bony portion can improve their function and avoid problems associated with bone screw backout.
There can be problems associated with prior retaining devices. For example, in prior retaining devices, the head of one or more of the anchors may interfere with positioning and alignment of the retaining device relative to the anchor. Prior retaining devices may not be employed with one or more of the anchors if the anchors move relative to the plate, or if multiple anchors associated with the retaining device are not at the same position relative to the plate. Other retaining devices include placing a retaining cover plate over the bone plate and anchors, and thus creating a higher profile bone plate that intrudes into adjacent tissue. Also, prior retaining devices can be difficult to handle, install and/or manipulate during surgery.
There remains a need for instruments and methods that can be employed for efficiently and effectively preventing backout of anchors relative to a bone plate and maintaining the engagement between the anchors and a bony segment. | {
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Generally, devices, such as printers and multifunction printers (MFP), perform printing or copying using paper media. However, in order to develop a paperless environment, various means for replacing newspapers, books, and conference materials, which are made of paper, are being studied. Currently, many people tend to own at least one display device. In detail, most homes and companies are furnished with a display device, such as a TV. Further, electronic devices having a display panel, such as smart phones and tablet devices, are widely supplied for various purposes such as personal use or educational use. Accordingly, many studies on printouts that may replace paper are being conducted. | {
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The present disclosure relates generally to imaging members, such as layered photoreceptor devices, and processes for making and using the same. The imaging members can be used in electrophotographic, electrostatographic, xerographic and like devices, including printers, copiers, scanners, facsimiles, and including digital, image-on-image, and like devices. More particularly, the embodiments pertain to an imaging member or a photoreceptor that incorporates specific materials, namely polyols, into the anticurl back coating (ACBC) layer.
Electrophotographic imaging members, e.g., photoreceptors, typically include a photoconductive layer formed on an electrically conductive substrate. The photoconductive layer is an insulator in the substantial absence of light so that electric charges are retained on its surface. Upon exposure to light, charge is generated by the photoactive pigment, and under applied field charge moves through the photoreceptor and the charge is dissipated.
In electrophotography, also known as xerography, electrophotographic imaging or electrostatographic imaging, the surface of an electrophotographic plate, drum, belt or the like (imaging member or photoreceptor) containing a photoconductive insulating layer on a conductive layer is first uniformly electrostatically charged. The imaging member is then exposed to a pattern of activating electromagnetic radiation, such as light. Charge generated by the photoactive pigment move under the force of the applied field. The movement of the charge through the photoreceptor selectively dissipates the charge on the illuminated areas of the photoconductive insulating layer while leaving behind an electrostatic latent image. This electrostatic latent image may then be developed to form a visible image by depositing oppositely charged particles on the surface of the photoconductive insulating layer. The resulting visible image may then be transferred from the imaging member directly or indirectly (such as by a transfer or other member) to a print substrate, such as transparency or paper. The imaging process may be repeated many times with reusable imaging members.
An electrophotographic imaging member may be provided in a number of forms. For example, the imaging member may be a homogeneous layer of a single material such as vitreous selenium or it may be a composite layer containing a photoconductor and another material. In addition, the imaging member may be layered. These layers can be in any order, and sometimes can be combined in a single or mixed layer.
Typical multilayered photoreceptors have at least two layers, and may include a substrate, a conductive layer, an optional charge blocking layer, an optional adhesive layer, a photogenerating layer (sometimes referred to as a “charge generation layer,” “charge generating layer,” or “charge generator layer”), at least one charge transport layer, an optional overcoating layer and, in some belt embodiments, an anticurl backing layer. In the multilayer configuration, the active layers of the photoreceptor are the charge generation layer (CGL) and the charge transport layer (CTL). Enhancement of charge transport across these layers provides better photoreceptor performance.
As more advanced, higher speed electrophotographic copiers, duplicators and printers were developed, however, degradation of image quality was encountered during extended cycling. The complex, highly sophisticated duplicating and printing systems operating at very high speeds have placed stringent requirements, including narrow operating limits, on the imaging members.
In multilayered imaging members, the CTL is usually the last layer to be coated and is applied by solution coating then followed by drying the wet applied coating at elevated temperatures of about 120° C., and finally cooling it down to room ambient temperature of about 25° C. When a production web stock of several thousand feet of coated multilayered photoreceptor material is obtained after finishing application of the CTL coating through drying and cooling processes, exhibition of spontaneous upward curling of the multilayered photoreceptor is observed. This upward curling is a consequence of thermal contraction mismatch between the CTL and the substrate support. Since the CTL in a typical photoreceptor device has a coefficient of thermal contraction approximately 3.7 times greater than that of the flexible substrate support, the CTL does therefore have a larger dimensional shrinkage than that of the substrate support as the imaging member web stock cools down to ambient room temperature. The exhibition of imaging member curling after completion of CTL coating is due to the consequence of the heating/drying/cooling processing.
To offset the curling, an anticurl back coating is then applied to the backside of the flexible substrate support, opposite to the side having the charge transport layer, and render the imaging member web stock with desired flatness. Curling of a photoreceptor web is undesirable because it hinders fabrication of the web into cut sheets and subsequent welding into a belt. An anticurl back coating having a counter curling effect equal to and in the opposite direction to the applied layers is applied to the reverse side of the active imaging member to eliminate the overall curl of the coated device by offsetting the curl effect which is arisen from the mismatch of the thermal contraction coefficient between the substrate and the CTL, resulting in greater CTL dimensional shrinkage than that of the substrate.
Although the anticurl back coating is needed to counteract and balance the curl so as to allow the imaging member web to lay flat, nonetheless, common formulations used for anticurl back coatings have often been found to provide unsatisfying dynamic imaging member belt performance under a normal machine functioning condition; for example, exhibition of excessive anticurl back coating wear and its propensity to cause electrostatic charge buildup are the frequently seen problems that prematurely cut short the service life of the photoreceptor belt and require its frequent costly replacement in the field.
Moreover, high surface contact friction of the anticurl back coating against all these machine subsystems is further been found to cause the development of electrostatic charge buildup problem. In many machines, the electrostatic charge builds up due to high contact friction between the anticurl back coating and the backer bars is seen to significantly increase the frictional force to the point that it requires higher torque from the driving motor to pull the belt for effective cycling motion. In full color electrophotographic machines, using a 10-pitch photoreceptor belt, this electrostatic charge build-up can be extremely high due to large number of backer bars used in the machine.
In an effort to resolve the problems associated with the anticurl back coating, one known wear resistance anticurl back coating formulated for use in the printing apparatuses includes organic particles reinforcement such as the utilization of polytetrafluoroethylene (PTFE) dispersion in the anticurl back coating polymer binder. PTFE particles are commonly incorporated to reduce the friction between the anticurl back coating of the belt and the backer bars. The benefit of using this formulation is, however, outweighed by the instability of the PTFE particle dispersion in the anticurl back coating solution. PTFE, being two times heavier than the coating solution, forms an unstable dispersion in a polymer coating solution, commonly a bisphenol A polycarbonate polymer solution, and tends to settle with particles flocculate themselves into big agglomerates in the mix tanks if not continuously stirred. The difficulty of achieving good PTFE dispersion in the coating solution poses a problem, because it can result in an anticurl back coating with insufficient and variable or inhomogeneous PTFE dispersion along the length of the coated web, and thus, inadequate reduction of friction over the backer bars in the copiers or printers. This causes significant complications in the larger copiers or printers, which often include so many backer bars that the high friction increases the torque needed to drive the belt. Consequently, two driving rollers are included and synchronized to prevent any registration error to occur. The additional components result in high costs for producing and using these larger printing apparatuses. Thus, if the friction could be reduced, the apparatus design in these larger printing apparatuses could be simplified with less components, resulting in significant cost savings.
Some anticurl back coating formulations are disclosed in U.S. Pat. Nos. 5,069,993, 5,021,309, 5,919,590, 4,654,284 and 6,528,226. However, while these formulations serve their intended purposes, further improvement on those formulations are desirable and needed. More particularly, there is a need, which is addressed herein, for a way to create an anticurl back coating formulation that has intrinsic properties to minimize or eliminate charge accumulation in photoreceptors without sacrificing the other electrical properties.
The term “electrostatographic” is generally used interchangeably with the term “electrophotographic.” In addition, the terms “charge blocking layer” and “blocking layer” are generally used interchangeably with the phrase “undercoat layer.” | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
This invention relates to a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
2. Description of the Related Art
Conventionally, a driving force controls system of this kind has been proposed, e.g., by Japanese Laid-Open Patent Publication (Kokai) No. 9-109716, for a four-wheel drive vehicle (hereinafter referred to as he vehicle including rear wheels as main drive wheels, and front wheels as auxiliary drive wheels. This driving force control system controls the engagement forces of variable torque clutches to thereby control torque distributed or allocated to the front wheels, i.e., the auxiliary drive wheels. More specifically, a first front-wheel distribution torque is calculated based on the difference (hereinafter referred to as ear-front wheel speed difference obtained by subtracting the wheel speed of the front wheels from the wheel speed of the rear wheels. A second front-wheel distribution torque is also calculated based on the oil temperature of the variable torque clutches. Further, a third front-wheel distribution torque is calculated based on a throttle opening when the wheel speed of the front wheels is equal to or lower than a predetermined value (i.e., during the start of the vehicle), and set to a value of 0 when the wheel speed of the front wheels is larger than the predetermined value (i.e., after the start of the vehicle), or when the rear-front wheel speed difference assumes a negative value (i.e., during deceleration of the vehicle). Then, the maximum value of the above first to third front-wheel distribution torques is determined to be a final control value, based on which the variable torque clutches are driven to control the engagement forces thereof to thereby control the torque distribution to the front wheels.
According to the proposed prior art driving force control system, the torque distributed to the front wheels is calculated based on the above-mentioned three parameters: the rear-front wheel speed difference, the oil temperature, and the throttle opening. Therefore, it is impossible to perform delicate or fine control of torque distribution to the front wheels based on a state of slippage of the individual rear wheels. As a result, when the vehicle is being started on a road surface having a small frictional resistance xcexc (hereinafter referred to as xe2x80x9clow-xcexc road surfacexe2x80x9d, such as an icy road surface), for instance, only one of the rear wheels might undergo slippage, but the system cannot perform the driving force control such that suitable torque distribution to the front wheels is effected in response to this slipping condition of one rear wheel, which makes it impossible for the vehicle to start smoothly. Further, the throttle opening indicates a driver demand for acceleration, but does not faithfully reflect an actual accelerating condition of the vehicle, so that the torque distribution to the front wheels cannot be properly carried out accordingly to the actual accelerating condition of the vehicle. This sometimes results in an insufficient torque distribution to the front wheels, or inversely, an excessive torque distribution to the same, which leads to decreased response of the vehicle and degraded fuel economy.
It is an object of the invention to provide a driving force control system for a four-wheel drive vehicle, which enables the vehicle to smoothly start on a low-xcexc road surface, and is capable of distributing only the required amounts of driving forces to auxiliary drive wheels depending on an actual accelerating condition of the vehicle, thereby improving the response and fuel economy of the vehicle.
To attain the above object, according to a first aspect of the invention, there is provided a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
The driving force control system according to the first aspect of the invention comprises:
driving force control means for controlling the engagement forces of the clutches such that the driving forces are distributed to the auxiliary drive wheels, on condition that there is satisfied at least one of the following conditions that a wheel speed of one of the main drive wheels is equal to or higher than a first predetermined speed, and at the same time, a wheel speed of another of the main drive wheels is lower than the first predetermined speed, and that an average wheel speed of the main drive wheels is equal to or higher than a second predetermined speed, and at the same time, an average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, until the average wheel speed of the auxiliary drive wheels reaches a third predetermined speed equal to or higher than the second predetermined speed.
According to this driving force control system for a four-wheel drive vehicle, when the wheel speed of one of the main drive wheels is equal to or higher than the first predetermined speed, and at the same time, the wheel speed of another of the main drive wheels is lower than the first predetermined speed, i.e., when one of the main drive wheels is slipping, driving forces are distributed to the auxiliary drive wheels until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. Thus, the control of distribution of the driving forces to the auxiliary drive wheels can be delicately or finely carried out depending on a slipping condition of each of the individual main drive wheels. Further, even when the wheel speeds of the respective main drive wheels are equal to each other, if the average wheel speed of the main drive wheels is equal to or higher than the second predetermined speed, and at the same time, the average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, i.e., when both the main drive wheels are slipping, driving forces are distributed to the auxiliary drive wheels until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. This make it possible to carry out control of distribution of the driving forces to the auxiliary drive wheels delicately or finely depending on a slipping condition of both of the main drive wheels, and hence enables the vehicle to smoothly start even on a low-xcexc road surface.
To attain the above object, according to a second aspect of the invention, there is provided a driving force control system for a four-wheel drive vehicle including a pair of front wheels, and a pair of rear wheels, one of the pairs being main drive wheels, and another of the pairs being auxiliary drive wheels, the driving force control system controlling engagement forces of clutches to thereby control driving forces distributed to the auxiliary drive wheels.
The driving force control system according to the second aspect of the invention comprises:
vehicle acceleration-calculating means for calculating a vehicle acceleration of the vehicle based on a demanded driving force demanded by the main drive wheels; and
driving force-calculating means for calculating the driving forces to be distributed to the auxiliary drive wheels based on the calculate vehicle acceleration.
According to this driving force control system for a four-wheel drive vehicle, the vehicle acceleration of the vehicle is calculated based on a demanded driving force demanded by the main drive wheels. Based on the calculated vehicle acceleration, the driving forces to be distributed to the auxiliary drive wheels are calculated, and the engagement forces of the clutches are controlled such that the calculated driving forces are distributed to the auxiliary drive wheels. Thus, based on the demanded driving force actually demanded by the main drive wheels, the vehicle acceleration is calculated, which can faithfully reflect an actual accelerating condition of the vehicle on the calculated driving forces. Therefore, because the driving forces to be distributed to the auxiliary drive wheels are calculated based the vehicle acceleration calculated as described above, differently from conventional cases where the driving forces are calculated based on the throttle opening, only the required amounts of the driving forces can be distributed to the auxiliary drive wheels while taking the actual accelerating condition of the vehicle into account. This makes it possible to improve the response and fuel economy of the vehicle.
Preferably, the driving force control system further includes driving force-increasing means for increasing the driving forces distributed to the auxiliary drive wheels, on condition that there is satisfied at least one of the following conditions that a wheel speed of one of the main drive wheels is equal to or higher than a first predetermined speed, and at the same time, a wheel speed of another of the main drive wheels is lower than the first predetermined speed, and that an average wheel speed of the main drive wheels is equal to or higher than a second predetermined speed, and at the same time, an average wheel speed of the auxiliary drive wheels is lower than the second predetermined speed, until the average wheel speed of the auxiliary drive wheels reaches a third predetermined speed equal to or higher than the second predetermined speed.
According to this preferred embodiment, when wheel speeds of the respective main drive wheels are different from each other, or the average wheel speed of the main drive wheels is higher than that of the auxiliary drive wheels, i.e. when one or both of the main drive wheels is/are slipping, the driving forces distributed to the auxiliary drive wheels are increased until the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed. Therefore, when the vehicle is starting on an icy road surface, and the vehicle acceleration is small due to a small throttle opening, for instance, if one or both of the main drive wheels is/are slipping, the driving forces distributed to the auxiliary drive wheels are increased, thereby enabling the vehicle to start smoothly. As a result, the startability of the four-wheel drive vehicle can be further improved.
More preferably, the driving force-increasing means includes progressively-increasing means for progressively increasing the driving forces distributed to the auxiliary drive wheels with the lapse of time.
More preferably, the driving force control system further includes driving force-progressively decreasing means for progressively decreasing the driving forces distributed to the auxiliary drive wheels with the lapse of time, after the average wheel speed of the auxiliary drive wheels reaches the third predetermined speed.
Preferably, the driving force control system further includes vehicle speed detection means for detecting a vehicle speed of the vehicle, and correction means for correcting the driving forces for prevention of tight turn, such that the driving forces are made smaller as the vehicle speed detected by the vehicle speed detection means is larger, and at the same time that the driving forces are made larger as the demanded driving force is larger.
Preferably, the demanded driving force is calculated based on a basic driving force calculated based on an engine rotational speed and an intake pipe absolute pressure, by using a coefficient corresponding to a gear ratio of the vehicle, and a correction term corresponding to an inertial force of the vehicle.
Preferably, the vehicle acceleration-calculating means calculates the vehicle acceleration by subtracting a value corresponding to a running resistance of the vehicle from a vehicle acceleration value calculated based on the demanded driving force. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to an apparatus and a method for controlling transportation of a tape medium. In particular, the present invention relates to an apparatus and a method for controlling transportation of a tape medium during data writing to the tape medium.
2. Description of the Related Art
During data writing, some tape drives write data to tape media, such as magnetic tapes, in conformity with LTO (Linear Tape Open), for example, by receiving synchronization commands from a host (an application program) at regular or sporadic time intervals. The synchronization command is a command to forcedly write data accumulated in a buffer in a tape drive to a tape medium. Such regular reception of synchronization commands assures an application program that all data sent to the tape drive by the application program itself is already written to the tape medium and is not left any more in the buffer in the tape drive.
When the tape drive receives a synchronization command, the buffer inside the tape drive becomes empty, and the tape medium is transported idly without data to be written. In order to keep an interval between recorded datasets, the tape drive usually performs “backhitch.” The backhitch is a series of operations including stopping the transportation of the tape medium once by reducing the transport speed of the tape medium, transporting the tape medium in a reversed direction, thereafter transporting the tape medium again in the original direction until a location of the tape medium targeted for writing arrives, and then writing next data to the location. This backhitch usually requires a time of approximately two or three seconds. Since the writing of next data starts after completion of this backhitch, frequent reception of synchronization commands leads to considerable reduction in writing performance.
To address this, there have been heretofore proposed techniques of writing without execution of backhitch (for example, see Japanese Patent Application Publication Nos. 2006-318571, 2004-341925, 2008-533636).
Japanese Patent Application Publication No. 2006-318571 describes an apparatus including a host I/F unit to store a dataset sent from a host into a buffer memory, as well as to take out a dataset stored in the buffer memory and to send the dataset to the host, and a medium I/F unit to take out a dataset stored in the buffer memory and to transfer the dataset to a tape, as well as to store a dataset read from a tape into the buffer memory. The apparatus acquires a transfer rate with the host from the host I/F unit, acquires an error rate in writing to the tape from the medium I/F, determines a tape speed based on the transfer rate and the error rate, and performs control to transport the tape with the determined speed.
Japanese Patent Application Publication No. 2004-341925 describes a storage apparatus to sequentially write multiple sets of write data to a data recording medium in segment units of a predetermined size. For each of sets of write data, the storage apparatus writes the set of write data to at least one segment of the data recording medium when the set of write data is received in association with a write command to write the set of write data to the data recording medium. In the case where the size of one set of write data is smaller than a prescribed size that is determined in advance, the storage apparatus concatenates the one set of write data and multiple sets of write data written after the one set of write data, among the multiple sets of write data sequentially written to the data recording medium, and then writes the concatenated sets of write data to a smaller number of segments than the number of segments originally required to write the sets of write data targeted for the concatenation. In addition, according to Japanese Patent Application Publication No. 2004-341925, the storage apparatus performs backhitchless flush of writing write data to a tape recording medium without executing backhitch, and thereby operates with a higher speed than in the case of executing the backhitch.
Japanese Application Publication No. 2008-533636 describes a helical scan tape recorder including a rotatable scanner, and a transport system for transporting a magnetic tape to a position proximate to the rotatable scanner in such a manner that information can be recorded during a revolution of the scanner. In the helical scan tape recorder, a controller performs, as a pause routine for pausing during a recording operation on the tape, the steps of: determining a tape pause position reference value indicative of a pre-pause last recording position on the tape; recording an erase signal on the tape after the pre-pause last recording position; rewinding the tape; transporting the tape in a forward direction and obtaining a current tape position value; determining when the current tape position value reaches a predetermined value relative to the tape pause position reference value; and at beginning of a next revolution of the scanner, commencing recording of one or more post-pause stripes on the tape.
One conceivable method of backhitchless writing is to idly transport a tape (transport the tape without writing data) after receiving a synchronization command until next data is ready to be written. However, since a time to write data to the tape is proportional to a tape speed, there is a case where a high tape speed is used to reduce the write time. The use of the high tape speed leads to an increase in the idly-transported length, and thereby causes a problem of lowering the performance in reading.
In contrast, in order to achieve a target value of the performance in reading, there is no way but to make the idly-transported length short, and the backhitch is executed for this purpose. Therefore, a time of entire write processing cannot be reduced in consideration of an occurrence frequency of backhitch and a time required for backhitch. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to a DCxe2x80x94DC converter circuit for converting DC voltage to another DC voltage, a power supply selection circuit for selecting one of a plurality of power supplies, and an apparatus provided with such a DCxe2x80x94DC converter circuit.
2. Description of the Related Art
Many of portable type of electronic apparatuses such as a note personal computer and the like are so arranged that they operate from electric power obtained from a commercial power supply and a battery incorporated therein as well.
Usually, such an apparatus incorporates therein a circuit for changing over as to which source of electric power, the commercial power supply or the battery, is used to operate the apparatus (for example, Japanese Patent Laid Open Gazette Hei. 9-182288, and Japanese Patent Laid Open Gazette Hei. 9-308102). According to such type of circuit, when electric power obtained from the commercial power supply is supplied to the apparatus, this electric power takes precedence in use, and when the circuit detects that the supply of power from the commercial power supply stops, the supply of power changes to the supply of power from the battery. As another type of the power supply switching circuit, a circuit is arranged in such a manner that, in view of the fact that electric power obtained from the commercial power supply is generally higher in voltage than that from the battery, the supply of power selected is from the electric power of the highest voltage of the plurality of electric powers.
Incidentally, the voltage of a battery decreases as the battery discharges. Thus, an apparatus is provided with a DCxe2x80x94DC converter circuit for maintaining the voltage of electric power used in the apparatus.
FIG. 7 is a circuit diagram showing a first example of a linear regulator. The linear regulator is one type of a DCxe2x80x94DC converter circuit, and it is generally widely used.
A linear regulator section 10 is loaded on an LSI having an input terminal IN through which electric power of input voltage Vin is applied. The linear regulator section 10 converts the electric power of the input voltage Vin to electric power of output voltage Vout (Vin greater than Vout) lower than the input voltage Vin, and outputs electric power of the output voltage Vout through an output terminal OUT.
Between the input terminal IN and the output terminal OUT, an NPN transistor 11 for output voltage control is disposed, and between the input terminal IN and a base of the NPN transistor 11, a constant current source 12 is disposed. A current outputted from the constant current source 12 flows through the base of the NPN transistor 11 in the form of a base current thereof, and further flows through a collector of an additional NPN transistor 13 in the form of a collector current thereof. An emitter of the NPN transistor 13 is connected to a ground terminal GND, which is grounded. The output voltage Vout of the output terminal OUT is fed to a plus input terminal of a differential amplifier 16 in the form of a potential division by two resistances 14 and 15, while a reference voltage generated by a reference voltage source 17 is fed to a minus input terminal of the differential amplifier 16. An output terminal of the differential amplifier 16 is connected to a base of the NPN transistor 13.
In the event that the output voltage Vout of the output terminal OUT is biased with a voltage higher than a predetermined reference output voltage, the output voltage of the differential amplifier 16 increases, so that a collector current of the NPN transistor 13 increases. That is, of the current outputted from the constant current source 12, one used as the collector current of the NPN transistor 13 increases, and as a result, the base current of the NPN transistor 11 for output voltage control decreases and thereby the output voltage Vout of the output terminal OUT decreases.
Conversely, in the event that the output voltage Vout of the output terminal OUT is biased with a voltage lower than a predetermined reference output voltage, the output voltage of the differential amplifier 16 decreases, so that the collector current of the NPN transistor 13 also decreases. That is, the base current of the NPN transistor 11 increases and thereby the output voltage Vout of the output terminal OUT increases.
In this manner, the electric power of a constant output voltage Vout is outputted from the output terminal OUT.
FIG. 8 is a circuit diagram showing a second example of a linear regulator. The following description sets forth the differences from the first example of the linear regulator shown in FIG. 7, hereinafter.
A linear regulator 10xe2x80x2 shown in FIG. 8 is provided with a PNP transistor 18 for output voltage control, instead of the NPN transistor 11 for output voltage control in the linear regulator 10 shown in FIG. 7. As a result, the output voltage Vout of the output terminal OUT is fed to the minus input terminal of the differential amplifier 16 in form of a potential division by two resistances 14 and 15, while the reference voltage generated by the reference voltage source 17 is fed to the plus input terminal of the differential amplifier 16.
In the event that the output voltage Vout of the output terminal OUT is biased with a voltage higher than a predetermined reference output voltage, the output voltage of the differential amplifier 16 decreases, so that a collector current of the NPN transistor 13 also decreases. That is, of the current outputted from the constant current source 12, one used as the collector current of the NPN transistor 13 decreases, and as a result, the base current of the PNP transistor 18 decreases and thereby the output voltage Vout of the output terminal OUT decreases.
Conversely, in the event that the output voltage Vout of the output terminal OUT is biased with a voltage lower than a predetermined reference output voltage, the output voltage of the differential amplifier 16 increases, so that the collector current of the NPN transistor 13 also increases. That is, the base current of the PNP transistor 18 increases and thereby the output voltage Vout of the output terminal OUT increases.
In this manner, an electric power of a constant output voltage Vout is outputted from the output terminal OUT.
FIG. 9 is a circuit diagram showing a third example of a linear regulator.
A main difference from the second example of the linear regulator shown in FIG. 8 is that the PNP transistor 18 is replaced by P channel MOS transistor 19. With respect to circuit operation, it is the same as that of the second example shown in FIG. 8, and thus a redundant explanation will be omitted.
FIG. 10 is a circuit diagram showing an example of a switching regulator. The switching regulator 20 is also a type of DCxe2x80x94DC converter circuit, and it is generally widely used.
An electric power of voltage Vin is fed through an input terminal IN of the switching regulator, and an electric power of output voltage Vout (here dealing with a step-down type and thus Vin greater than Vout) is outputted from a second output terminal OUT 2, of first and second output terminals OUT 1 and OUT 2. Between the first and second output terminals OUT 1 and OUT 2, an outside coil 31 is connected. Between the second output terminals OUT 2 and the ground, an outside capacitor 32 is connected.
Elements of the switching regulator 20, except outside coil 31 and outside capacitance 32, are loaded on an LSI.
Between the input terminal IN and the output terminal OUT 1, P channel MOS transistor 21 is disposed. An output of a PWM comparator 26 is connected to a gate of the P channel MOS transistor 21. An output of a differential amplifier 24 and an output of a triangle wave generator 27 are fed to the PWM comparator 26. The PWM comparator 26 will be described later.
The voltage Vout of the second output terminal OUT2 is fed to a minus input terminal of the differential amplifier 24 in form of a potential division by two resistances 22 and 23, while a reference voltage generated by a reference voltage source 25 is fed to a plus input terminal of the differential amplifier 24. Between the first output terminal OUT 1 and a ground terminal GND which is grounded, a diode 28 is connected. A cathode of the diode 28 is connected to the first output terminal OUT 1, and an anode of the diode 28 is connected to the ground terminal GND.
The PWM comparator 26 compares an output voltage of the differential amplifier 24 with a triangle wave signal outputted from the triangle wave generator 27. When the output voltage of the differential amplifier 24 is lower in voltage than the triangle wave signal, the PWM comparator 26 generates a pulse signal of xe2x80x98Hxe2x80x99 level. When the output voltage of the differential amplifier 24 is higher in voltage than the triangle wave signal, the PWM comparator 26 generates a pulse signal of xe2x80x98Lxe2x80x99 level. Such a pulse signal is fed to the gate of the MOS transistor 21, so that the MOS transistor 21 turns on or off in accordance with the variation between the xe2x80x98Hxe2x80x99 level and the xe2x80x98Lxe2x80x99 level of the pulse signal. That is, the MOS transistor 21 switches the input voltage Vin at the same repetitive frequency as that of the triangle wave signal.
The diode 28, the coil 31 and the capacitor 32 smooth the input voltage Vin after the switching and generate the output voltage Vout.
When the output voltage Vout slightly exceeds a set up voltage, the output voltage of the differential amplifier 24 decreases, so that a pulse width (a pulse width of the xe2x80x98Lxe2x80x99 level) of the pulse signal generated by the PWM comparator 26 narrows slightly and thereby the output voltage Vout decreases. Conversely, when the output voltage Vout decreases, the output voltage of the differential amplifier 24 increases, so that a pulse width (a pulse width of the xe2x80x98Lxe2x80x99 level) of the pulse signal generated by the PWM comparator 26 expands and thereby the output voltage Vout increases. Thus, the switching regulator 20 controls the electric power of a constant voltage Vout to be outputted.
In an electronic apparatus, for example, a personal computer, there is frequently a case that a plurality of circuit units, operative with mutually different DC voltages, exist in the apparatus. Such an apparatus has a plurality of DCxe2x80x94DC converter circuits which output electric powers of individual voltages, respectively. A DCxe2x80x94DC converter circuit is associated with such disadvantages that a great deal of useless electric power is consumed for conversion of DC voltage, and as a result, the consumption of battery charge is hastened, and also this is associated with a temperature rise of the apparatus. For example, in case of the DCxe2x80x94DC converter circuit of the linear regulator scheme shown in FIGS. 7 to 9, for conversion from the input voltage of 16 volts into the output voltage of 3.3 volts, the conversion efficiency is 20%, and the remaining 80% is a power loss. Particularly, in an apparatus in which a plurality of mutually different DC voltages are used and a plurality of DCxe2x80x94DC converter circuits are needed in order to generate the plurality of mutually different DC voltages, it is a problem as to how the conversion efficiency is improved in the DCxe2x80x94DC converter circuits.
In view of the foregoing, it is an object of the present invention to provide a DCxe2x80x94DC converter circuit improved in conversion efficiency, a power supply selection circuit in which an existing DCxe2x80x94DC converter circuit is used to perform a voltage conversion improved in conversion efficiency, and an apparatus incorporated thereinto such a DCxe2x80x94DC converter circuit improved in conversion efficiency.
To achieve the above-mentioned objects, the present invention provides a first DCxe2x80x94DC converter circuit having a plurality of input terminals connected to a plurality of DC power supplies, respectively, and an output terminal. This DCxe2x80x94DC converter circuit has a power supply selection section for selecting the DC power supply of the lowest voltage on the condition that the voltage is not less than a predetermined voltage. This DCxe2x80x94DC convertor circuit also has a step-down type of regulator section for converting the voltage of the DC power supply selected by the power supply selection section into a predetermined voltage lower than the voltage of the DC power supply selected by the power supply selection section, and outputting the converted voltage through the output terminal.
As mentioned above, in case of the DCxe2x80x94DC converter circuit according to the linear regulator scheme, the conversion efficiency is 20% for a conversion of 16V to 3.3V. Conversely, in a case where a power supply of 5 V exists, the conversion efficiency is 66% for the same conversion. In this manner, when an output voltage is obtained from an input voltage which is close to the output voltage as much as possible, it is possible to greatly improve the conversion efficiency. This is applicable also to the switching regulator scheme as well as the linear regulator scheme.
The first DCxe2x80x94DC converter circuit according to the present invention utilizes this principle as mentioned above.
That is, the power supply selection section selects a DC power supply of the lowest voltage from among a plurality of DC power supplies, and transmits the selected DC power supply to the regulator section. However, in this case, in order to avoid such a situation that the lowest detected voltage is when no power supply is connected, or the connected power supply is not operative, so that the lowest voltage is 0V, there is a requirement that the lowest voltage is not less than a predetermined voltage. The regulator section converts the voltage of the DC power supply thus selected to a DC voltage lower than the voltage of the selected DC power supply. Thus, it is possible to implement high efficiency voltage conversion wherein the optimum power supply is selected in accordance with the state of the power supplies.
To achieve the above-mentioned objects, the present invention provides a second DCxe2x80x94DC converter circuit having a first input terminal connected to a predetermined first DC power supply, a second input terminal connected to a predetermined second DC power supply of a voltage lower than that of the first DC power supply, and an output terminal. This DCxe2x80x94DC converter circuit has a power supply selection section for selecting the first DC power supply connected to the first input terminal and the second DC power supply connected to the second input terminal, the voltage of the second DC power supply being less than a predetermined voltage or is not less than the predetermined voltage, respectively. This DCxe2x80x94DC converter circuit also has a step-down type of regulator section for converting the voltage of the DC power supply selected by the power supply selection section into a predetermined voltage lower than the voltage of the DC power supply selected by the power supply selection section, and outputting the converted voltage through the output terminal.
In the event that it is decided that, as compared with the voltage of the first DC power supply entered through the first input terminal, the voltage of the second DC power supply entered through the second input terminal is lower, or it is arranged in such a manner as mentioned above on a connection basis, it is possible to simplify the power supply selection section in structure taking into account the idea of the first DCxe2x80x94DC converter circuit of the present invention.
In either of the first and second DCxe2x80x94DC converter circuits according to the present invention, it is acceptable that the regulator section have a linear regulator. In this case, it is preferable that the power supply selection section and the regulator section having the linear regulator are arranged in a chip of an integrated circuit. Or alternatively, it is preferable that the power supply selection circuit and portions of the regulator section having the linear regulator, except for an output voltage control transistor, are arranged in a chip of an integrated circuit.
In any of the first and second DCxe2x80x94DC converter circuits according to the present invention, it is acceptable that the regulator section have a switching regulator. In this case, it is preferable that the power supply selection section and portions of the regulator section having the switching regulator, except for a voltage smoothing circuit portion which is to be disposed outside, are arranged in a chip of an integrated circuit.
Arrangement in a chip of an integrated circuit makes possible a more stable operation, cost-reduction, and space saving.
To achieve the above-mentioned objects, there is provided a first power supply selection circuit having a plurality of input terminals connected to a plurality of DC power supplies; a power supply selection section for selecting a DC power supply of the lowest voltage, on the condition that the voltage is not less than a predetermined voltage, from among the plurality of DC power supplies; and an output terminal for outputting the voltage of the DC power supply selected by the power supply selection section.
To achieve the above-mentioned objects, there is provided a second power supply selection circuit having a first input terminal connected to a predetermined first DC power supply; a second input terminal connected to a predetermined second DC power supply of which the voltage is lower than the voltage of the first DC power supply; a power supply selection section for selecting the first DC power supply connected to the first input terminal and the second DC power supply connected to the second input terminal according to the voltage of the second DC power supply being less than a predetermined voltage or is not less than the predetermined voltage, respectively; and an output terminal for outputting the voltage of the DC power supply selected by the power supply selection section.
The first and second power supply selection circuits correspond to the power supply selection sections of the first and second DCxe2x80x94DC converter circuits, respectively. The DCxe2x80x94DC converter circuits corresponding to the regulator sections of the first and second DCxe2x80x94DC converter circuits are connected to the later stages of the first and second power supply selection circuits, respectively. This feature makes it possible to perform a highly efficient DCxe2x80x94DC conversion for the DCxe2x80x94DC converter circuits.
To achieve the above-mentioned objects, there is provided an apparatus operative upon receipt of an electric power having a step-down type of first DCxe2x80x94DC converter for converting a first DC voltage of a predetermined first DC power supply into a predetermined second DC voltage lower than the first DC voltage of the first DC power supply; a first operating circuit operative upon receipt of supply of an electric power of the second DC voltage obtained by the first DCxe2x80x94DC converter; a second DCxe2x80x94DC converter having a step-down type of regulator section for converting a received DC voltage into a predetermined third DC voltage lower than the received DC voltage, and a power supply selection section responsive to both the first DC voltage of the first DC power supply and an output of the first DCxe2x80x94DC converter for selectively transmitting to the regulator section the output of the first DCxe2x80x94DC converter and the first DC voltage of the first DC power supply according as the output of the first DCxe2x80x94DC converter is not less than a predetermined voltage or is less than the predetermined voltage, respectively; and a second operative circuit operative upon receipt of electric power supplied by the third DC voltage obtained by the second DCxe2x80x94DC converter.
The apparatus of the present invention as mentioned above is provided with two DCxe2x80x94DC converters of the first and second DCxe2x80x94DC converters. The second DCxe2x80x94DC converter, which outputs the lower DC voltage, is arranged with the first or second DCxe2x80x94DC converter circuit. This feature makes it possible to perform a DCxe2x80x94DC conversion excellent in efficiency, and also to implement a reduction of the consumed power and a suppression of temperature increase of the apparatus.
Generally, power supply systems are wired within apparatuses beforehand, and therefore the arrangement of the second DCxe2x80x94DC converter circuit of the present invention is generally used as the second DCxe2x80x94DC converter. However, it is acceptable that the first DCxe2x80x94DC converter circuit of the present invention is used as the second DCxe2x80x94DC converter. At that time, the power supply selection section of the second DCxe2x80x94DC converter serves to block both the path for transmitting the output of the first DCxe2x80x94DC converter to the regulator section and the path for transmitting the voltage of the first DC power supply to the regulator section, when the first DC power supply is less than a predetermined voltage, in the event that the output of the first DCxe2x80x94DC converter is less than a predetermined voltage. | {
"pile_set_name": "USPTO Backgrounds"
} |
Asphalt shingles have become a widely used roofing material, giving protection and many years of service. These shingles typically come in longitudinal strips having two transverse slots therein forming three rectangular portions which project downwardly from an upper longitudinal body portion. The first step in applying this type of roofing is to cover the roof with roofing felt. The bottom most row of shingles is then nailed into place along the eaves of the roof and along gable ends. Successive rows of shingles are applied from the eaves upward to the ridge of the roof. Building codes for most jurisdictions are very precise as to the spacing and fastening of the shingles to the roof. The most popular dimension for asphalt shingles is a longitudinal dimension having a nominal value of three feet with a tolerance of plus one-eighth inch and minus zero. The building codes which treat this size asphalt shingle state that the shingles must be positioned on centers which are no greater than three feet and one-eighth inch apart with rows having a width in the upward transverse direction of approximately five inches. It takes great skill and stamina to lay asphalt shingles all day in the hot sun and yet to maintain these stringent dimensions. There have been several attempts in the prior art to provide alignment devices for laying asphalt shingles but they generally are cumbersome to operate and are inefficient to use since they must be repositioned after every row of shingles has been laid down. | {
"pile_set_name": "USPTO Backgrounds"
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Recently, as an element for a head of a magnetic recording medium used in a hard disk drive, floppy disk drive or the like, a magnetoresistive element (hereinafter, referred to as "MR (magnetoresistive) element") has been used widely. In the head using the MR element (hereinafter, referred to as "MR head"), since a reproduction output is stronger than that of a conventional head using a thin film element, the surface recording density of the magnetic recording medium can be improved greatly. Here, in the following description, the MR element means an element which shows a magnetoresistive effect where resistance changes due to application of an external magnetic field. The MR element includes a GMR (giant magnetoresistive) element or a TMR (tunneling magnetoresistive) element, for example.
FIG. 9 is a circuit diagram showing a conventional signal amplifying circuit of the MR element. The signal amplifying circuit shown in FIG. 9 functions as an output detection circuit of the MR element, namely, a read amplifying circuit. In FIG. 9, both terminals T1 and T2 of the MR element MR are connected respectively with input terminals in1 and in2 of a differential amplifying circuit DA1. The terminal T1 of the MR element MR is connected with a resistance R11 in series, and the terminal T2 is connected with an electric current source CS1 again in series. The constant electric current source CS1 discharges a bias electric current Ib from a power source line Vcc at high potential to a power source line Vee at low potential. Therefore, the bias electric current Ib flows in the MR element MR, and thus the MR element MR generates an electric potential difference which is in proportion to a difference in resistance at the terminals T1 and T2.
The differential amplifying circuit DA1 has transistors TR1 and TR2 which compose a differential pair. The collectors of these transistors TR1 and TR2 are connected with collector resistances RC1 and RC2 having a same resistance value Rc. These resistances RC1 and RC2 are connected with the power source line Vcc. Moreover, emitters of the transistors TR1 and TR2 are connected with each other through a capacitor C1, and the emitters of the transistors TR1 and TR2 are connected respectively with electric current sources CS2 and CS2' in series. The electric current sources CS2 and CS2' are connected with the power source line Vee. Bases of the transistors TR1 and TR2 function as input terminals in1 and in2. Collector terminals of the transistors TR1 and TR2 are also connected respectively with output terminals out1 and out2. The emitters of the transistors TR1 and TR2 composing the differential pair are connected with each other by the capacitor C1 in order to cancel a DC potential difference between the terminals T1 and T2 of the MR element MR to be inputted into the differential amplifying circuit DA1.
In this signal amplifying circuit, the resistance value of the MR element MR in which the bias electric current Ib flows changes according to a magnetic signal from the outside, and thus a potential difference between the terminals T1 and T2 of the MR element MR changes Only an AC portion of the changed potential difference is amplified by the differential amplifying circuit DA1 so as to be outputted as a potential difference between the output terminals out1 and out2, namely, an output voltage.
Incidentally, since an input signal from the MR element MR is a weak input signal of less than 1 mvpp, the differential amplifying circuit DA1 should physically be provided in a vicinity of the MR element MR, and hence it is usual to form an integrated circuit.
However, a capacitance of the capacitor C1 which is realized on one semiconductor chip is maximum about several nF.
Since a cut-off frequency f of a low frequency becomes high, i.e., several tens MHz in such a capacitor C1 having such a small capacitance, a capacitance of an external capacitor should be used. As a result, integration of the signal amplifying circuit of the MR element is hindered, and thus promotion of miniaturization and light weight is prevented.
The cut-off frequency f will be described below concretely with reference to FIG. 10. When a base electric current is ignored, a gain Av of the differential amplifying circuit DA1 shown in FIG. 10 becomes: EQU Av=Rc/re=Rc.multidot.Ie/V.sub.T.
Here, "re" is an emitter resistance of the transistors TR1 and TR2, and "V.sub.T " is thermal voltage defined as follows: EQU V.sub.T =kT/q.about.26 mV at 300 K.
where,
q=electric charge, PA1 k=Boltzman's constant, PA1 T=temperature (in K).
In FIG. 9, since the capacitor C1 is connected with the emitter resistances of the transistors TR1 and TR2 in series, when electric currents which flow in the constant electric current sources CS2 and CS2' are Ie as shown in FIG. 9, EQU Av=Rc/(re+1/2j.omega.C)=Rc/(V.sub.T /Ie+1/2j.omega.C).
Here, "C" is a capacitance of the capacitor C1. Accordingly, the cut-off frequency f becomes: EQU f=Ie/(4.pi.V.sub.T.multidot.C).
When Ie=10 mA and C=5 nF, the cut-off frequency f becomes: EQU f=10 mA/(4.times.3.14.times.26 mV.times.5 nF)=6.1 MHz,
and thus it can be understood that the cut-off frequency f is high. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The invention is directed to both a system and a technique for remote chemical analysis. More particularly, the invention provides for the use of a solid-state acousto-optic device in combination with fiber optic technology in order to provide a system for the remote chemical analysis of a species of interest.
2. Description of the Prior Art
It is the conventional practice in the petrochemical industry, to utilize "in-line" sensors to affect chemical analysis. However, in such configurations, the presence of electrical or chemical sensors poses a significant threat to the safety of the area, from either explosions or from chemical contamination. As a result, such "in-line" sensors must be contained in approved explosion-proof enclosures. These enclosures represent an obvious significant cost to the petrochemical industry.
It has been suggested by G. Schmidtke, et al. VDI-Berichte 509,293 (1984) that a fiber optic system can be utilized to provide remote chemical analysis. This prior art system utilizes a diffraction grating and an array of detectors in a location remote from a sampling area.
Acousto-optic tunable filters (AOTF) have previously been used in spectral analysis as an effective device to measure dilute gas mixtures. An example of an automated AOTF infrared analyzer system which is unsable in a variety of industrial and commercial control applications is disclosed in U.S. Pat. No. 4,490,845 to Steinbruegge et al., which patent is assigned to the assignee of the present invention and incorporated herein by reference as if fully set forth.
Concentrated mixtures of gases and especially liquids often have strong, nearly total absorption bands. To analyze these mixtures, one must utilize the weaker overtone absorptions. These overtone bands lie in the near-to-intermediate infrared, where quartz fiber optic attenuation is not prohibitive to the use of such fibers. Using optical fibers eliminates one of the constraints with present detection systems.
It is an object of the present invention to provide a remote system for chemical analysis which utilizes optical fibers to convey an infrared source to a sample and then from the sample toward a detector array. This configuration would allow the use of such a remote chemical analysis system in applications where the presence of electrical or chemical sensors pose a significant threat from, for example, either explosions or from chemical contamination.
It is yet another object of this invention to provide an improved remote chemical analyzer which incorporates an automated acousto-optic infrared analyzer system remotely disposed from the sample site. | {
"pile_set_name": "USPTO Backgrounds"
} |
This invention relates to a power transmission device having a combined arrangement of balls and a screw for converting rotary to linear motion.
A variety of devices of the class have been known as circulatory fixed or other types. Any of the known devices operates to transmit power at a substantially equal reduction ratio in both directions counter to and toward the directions which a load is exerted (hereinafter called "counter-directional and non-counter-directional operation", respectively), so that a fairly great part of the work is rendered ineffective. The disadvantage of a loss of work is obvious particularly when such a transmission device is utilized to transmit power from a source for actuating movable elements in a reclining lounge, a jack or any other like appliances where the movable elements have to be actuated under a different load. | {
"pile_set_name": "USPTO Backgrounds"
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The present invention relates generally to mechanical seals, and more particularly, to rotary end face seals designed for use in severe environments in which the primary seal is formed between mating faces of two metal seal rings of special alloy compositions lying in opposed relation to each other and making contact along a seal band portion formed on parts of the respective radially extending end faces of the seal rings. Seals made according to the present invention are an improvement over known heavy duty grit seals of a similar nature, such as seals of the types shown in U.S. Pat. No. 3,241,843, and other patents.
Seals of this type are commonly used to exclude grit, water and the like from stationary and rotatable members in severe service environments, such as those encountered by earthmoving vehicles where the track rollers, idlers and final drive system may be exposed to mud, dust, sand, or rock at temperatures which may reach the extremes found in either the deserts or the artic regions. Such seals perform their primary sealing function under these conditions, both because the end faces are precisely finished and because the seal rings themselves are accurately positioned and loaded by elastomeric rings of various configurations, with such rings also applying the desired loading forces, forming a secondary seal, and providing sufficient driving torque so that relative rotation occurs only at the primary seal faces of the seal rings and not between the seal rings and the elastomer or between the elastomer and another part of the sealed mechanism.
In order to function successfully under these relatively severe conditions, the seal rings must not only possess strength, corrosion resistance, and abrasion resistance, but also must be able to withstand the shock normally associated with earthmoving operations, even when carried out at subzero temperatures. Accordingly, the metal ring portions of heavy duty seals are normally made of metal alloy compositions containing elements such as cobalt, molybdenum, and vanadium which are relied upon to impart the desired properties to the seals. However, the main disadvantage encountered in the use of these alloys is their relatively high cost. Inasmuch as the service life of the seal rings made from such high cost alloys often exceeds the actual service life of the components associated therewith, many seals using these alloys are prohibitively expensive for many applications.
In view of the need for an improved moderately priced seal and for an alloy composition from which such seals can be made, it is an object of the present invention to provide an improved, inexpensive alloy composition having high strength, high corrosion and abrasion resistance, and high impact strength over a wide range of temperatures.
It is a further object of the present invention to provide a seal ring made from such improved, inexpensive alloy composition.
A still further object of the invention is to provide a track roller having seals made from an improved alloy composition.
Another object is to provide an alloy composition and a track roller having a seal ring made from such composition, with the composition being characterized by a service life which is exceptionally long in relation to the cost of the material from which the metal rings are made.
Yet another object is to provide a metal composition which has outstanding wear resistance but which is sufficiently economical so that seal rings of substantial cross section can be made therefrom without incurring undue expense.
A still further object is to provide a seal ring having a service life which is nearly as long as the service life of the best seal rings heretofore known but which can be made at a fraction of the cost of such seals.
Another object is to provide primary seal rings made from high performance, low cost alloys, which seal rings can be used interchangeably with prior art seal rings, that is, to provide a primary seal ring which may be used with secondary seal rings of existing designs, thereby providing flexibility in the manufacture and inventory control of complete seal assemblies.
It is a further object of the present invention to provide a seal ring comprising, in weight percent, from about 3.0 percent to about 4.0 percent carbon, not more than 1.5 percent manganese, from about 0.5 percent to about 2.0 percent silicon, from about 15.0 percent to about 20.0 percent chromium, from about 0.5 percent to about 2.5 percent vanadium, from about 2.0 percent to about 5.0 percent molybdenum, from about 0.25 percent to about 1.75 percent cobalt, from about 1.5 percent to about 3.5 percent tungsten, the remainder of the composition being iron, with the alloy containing a minimum amount of impurities.
It is a further object of the present invention to provide a seal assembly having seal rings comprised of the improved metal alloy.
It is a further object of the present invention to provide a track roller assembly having seals which include seal rings made from the improved alloy.
The exact manner in which these and other objects of the invention are achieved will become more readily apparent when reference is made to the following detailed description of the preferred embodiments of the invention set forth by way of example and shown in the accompanying drawings in which like reference numbers indicate corresponding parts throughout the several figures. | {
"pile_set_name": "USPTO Backgrounds"
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The present application relates generally to the field of toilets. More specifically, the present application relates to improved systems and methods for installing a toilet (e.g., coupling the toilet to a trap assembly and/or mounting the toilet to the floor).
There is an increasing demand from consumers for toilets having bases or pedestals with smooth exterior surfaces, in part due to their improved aesthetics and cleanability. These toilets with smooth exterior surfaces may include pedestal side walls (or portions thereof) that are spaced a distance outward from the internal trapway of the toilet (hereinafter referred to as “skirted toilets”). In other words, the skirted feature of the toilet is created by the pedestal having a wall with a smooth exterior surface for aesthetic purposes and an interior surface that is separated by a gap (e.g., open space) from the external surfaces of the passageway (e.g., trap passageway). Many conventional non-skirted toilets have pedestals that include externally visible fasteners, indentations or voids (e.g., voids that outline the functional features, such as the trapway, contained within the toilet to transfer the water and waste), and other features that it may be desirable to eliminate for aesthetic and other purposes.
One challenge associated with skirted toilets relates to the manner in which such toilets must be mounted or coupled to the trap assembly and/or to the floor to prevent rotating, twisting, or rocking of the toilet during the user experience. For conventional toilets, a typical mounting method involves inserting a fastener through a horizontal portion (e.g., flange) of the toilet base or pedestal directly into the closet flange, the soil pipe, and/or the floor (i.e., the fastener is arranged perpendicular to the surface of the floor). In skirted toilets, however, such a configuration may not be appropriate or desirable because of the design of the skirted portion (e.g., there may not be a surface of the skirt that is parallel to the floor that would allow a fastener to be driven directly through the toilet and into the closet flange and/or the floor). It would be advantageous to provide a simple and secure method and system for mounting or coupling a skirted toilet to the trap, soil pipe, and/or the floor without having functional issues (e.g., leaking) and/or aesthetic issues (e.g., large openings requiring additional vitreous plastic covers or patches).
Additionally, there is a need to provide a more secure coupling between the toilet and the closet flange and/or the soil pipe, in order to improve the stability of the toilet, such as during use of the toilet, as well as, to reduce the likelihood of leaking, such as between the toilet and the drain pipe (or soil pipe or sanitary sewer system). Current skirted toilet couplings (or installation mountings) only provide either a horizontal force or a vertical force, but not both, to secure the toilet to the soil pipe. It would be advantageous to be able to couple the toilet to the soil pipe in a manner that provides both horizontal and vertical clamping forces to more securely couple the toilet and to reduce the likelihood of leaking, while simultaneously minimizing the aesthetic impact of the coupling (or fastening) system. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
Embodiments of the present invention generally relate to machine learning techniques and computational chemistry. More particularly, embodiments of the invention relate to techniques for estimating the accuracy of a molecular properties model, and for estimating the accuracy of predictions generated by a molecular properties model.
2. Description of the Related Art
Many industries use machine learning techniques to construct software applications that provide a predictive model of relevant phenomena. For example, machine learning applications have been developed to detect fraudulent credit card transactions, predict creditworthiness, or recognize words spoken by an individual. Machine learning techniques have also been applied to create predictive models of chemical and biological systems. Generally, machine learning techniques are used to construct a software application that improves its ability to perform a task as it attribute or quantity from known information (e.g., whether a particular molecule will bind to a protein receptor, based on an evaluation of other molecules known to, or to not, bind to the protein) or to classify an object as belonging to a particular group or class. A machine learning application may improve its performance on the selected task as the number of training examples used to train the model is increased. Each training example may include an example of an object (e.g., a molecule, compound, or substituent group thereof), along with a value for the otherwise unknown classification of the object.
During “training” a selected machine learning algorithm processes thousands, if not millions or billions, of potential models (also referred to as hypotheses). By evaluating how well different possible potential models perform against the training data a trained model is selected. For example, a classification learning algorithm may be configured to process a set of training examples that includes both an object and a classification for the object. In one embodiment, the hypothesis that correctly classifies the greatest number of training examples may be selected by a machine learning algorithm as the molecular properties model. Further, various machine learning algorithms may be configured to tweak or otherwise modify the selected model by also considering minor variations to a promising hypothesis. For example, genetic algorithms may be used to “mate,” and “mutate” hypotheses identified as interesting. The final “learned model” may then be used to predict the classification for other objects supplied to the model.
A molecular properties model, however, is of limited usefulness without an estimation of how well it performs. Thus, the accuracy of the model must be estimated. Often, the accuracy of a molecular properties model is calculated using statistical techniques; thus, the accuracy estimate is a random variable, and does not reflect a direct measurement of the actual accuracy for a specific molecular properties model. Thus, simply estimating that a model is 80% accurate is useful only if one has a minimal confidence in the accuracy of the estimate. It is not, however, currently the practice to expend effort estimating or bounding the statistical confidence or higher moments of estimates of model accuracy generated using statistical techniques. In practice, this has led to many molecular properties models with a very high estimated accuracy that, in fact, perform very poorly (i.e., the predictions or classifications prove to be erroneous). Accordingly, there is a need for improved techniques for generating molecular properties models and for estimating and bounding the accuracy and performance of these models or the predictions made using these models. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to a semiconductor memory device having a shallow trench isolation (STI) structure. In particular, the present invention relates to a semiconductor memory device including a static random access memory cell (SRAM cell).
2. Description of the Related Art
In recent years, SRAMs have a problem of causing a soft error resulting from cosmic rays such as α rays and neutron beams because scale-down of the element pattern and low voltage of the power supply have been advanced. More specifically, the signal charge held by the SRAM cell itself is remarkably smaller than other semiconductor devices, such as DRAM. For this reason, the amount of charge generated by the incidence of the cosmic rays becomes relatively larger than the signal charge held by the SRAM cell. If the charge by the cosmic rays reaches a storage node, data held in the storage node is inverted. The charge of the storage node held by the SRAM cell depends on the area of cell and a power supply voltage. Therefore, the charge held by the storage node is further reduced in accordance with scale-down of the element pattern and low voltage of the power supply. This is a factor of giving a great influence to the foregoing scale-down of the element pattern and low voltage of the power supply in the future technical generation.
For example, there has been conventionally known the following technique disclosed in JPN. PAT. APPLN. KOKAI Publication No. 10-79440 as a means of solving the problem of causing the soft error in the SRAM. According to the technique disclosed in the Publication, a conductive film is buried in a trench for STI, and thereafter, an insulating film is formed thereon. A gate electrode is further formed on the insulating film. In the way, capacitance is secured between the conductive film and the gate electrode; therefore, the capacitance of a storage node of the memory cell is increased.
However, according to the foregoing conventional technique, specific contact and interconnect are required in order to apply an electric potential to the conductive film buried in the trench for STI. As a result, the chip area increases. | {
"pile_set_name": "USPTO Backgrounds"
} |
The present invention relates to a method and apparatus for non-contact temperature measurement of a moving semiconductor wafer employing both a pyrometer and a reflectometer to provide temperature and reflectivity data respectively to a general purpose computer.
During the fabrication of semiconductor wafers, numerous physical parameters, such as temperature, pressure and flow rate are monitored and regulated to achieve a desired crystal growth. Maintenance of a specific temperature during the wafer fabrication process is particularly important in order to achieve a high quality semiconductor crystal. The semiconductor wafers to be grown are often placed on rapidly rotating carousels, or carriers, so as to provide a uniform surface easily accessible to circulating semiconductor gasses within a reactor chamber for the deposition of the semiconductor materials. Therefore, measurement of the wafer temperature during the deposition process is problematic in that a non-contact method of measurement is required which can accurately measure the temperature of the semiconductor wafers rotating at high speeds; often greater than 1,000 RPMs.
Non-contact temperature measurement of objects is presently possible using devices which measure the radiation reflected from a target object. These devices, known as pyrometers, are used to calculate the temperature of a physical body based on emitted radiation power from the body and a physical characteristic of the body known as its emissivity. A body""s emissivity is a measure of the ratio of the emitted radiation from a body to the incident radiation. The body""s temperature can be computed given its emissivity (E) and emitted radiation power (P) according to P = E w 2 π xe2x80x83 C 1 ∫ 0 ∞ 1 ( λ xe2x80x83 T ) 5 ( ⅇ C 2 / λ xe2x80x83 T - 1 ) ⅆ λ ( 1 )
Planck""s equation:
Where
Ew=body emissivity (dependent on body color and surface characteristics)
C1, C2=traceable universal consants (Planck""s Spectral Energy Distribution)
xcex=radiation wavelength
T=body temperature
From the emitted radiation power (P), the corresponding temperature of the body (T) may be accurately determined using the above equation if the emissivity of the body is known.
Often, however, the emissivity of the semiconductor wafers whose temperature is to be determined changes during the course of the semiconductor growth process so as to complicate its temperature determination. Therefore, a real-time time determination of the semiconductor wafer emissivity is necessary, in order to properly calculate the temperature of the semiconductor wafers during all phases of the semiconductor growth process.
Further complicating determination of the semiconductor wafer temperature is the fact that the semiconductor wafers are often placed upon a carousel within a chemical vapor deposition (CVD) chamber. The CVD chamber is a sealed environment that allows infused gases to be deposited upon the wafers to grow the semiconductor layers. Rotation of the semiconductor wafers upon the carousel permits an even deposition of infused gases upon the wafers. The rapidly rotating carousel presents difficulties in accurately measuring the semiconductor wafer temperature by the pyrometer, however, in that the pyrometer is typically fixed over a single point along the radius of the carousel such that sequential temperature measurements may include readings from the semiconductor wafers, the carousel itself, or the boundary between the semiconductor wafers and the carousel.
Several possible approaches may be used to make wafer temperature measurements using a high-speed pyrometer positioned over a rapidly rotating wafer carrier. First, a sequence of temperature measurements using a real-time algorithm to separate wafer and carousel temperatures may be used. The problem with this approach is that modem pyrometers can provide high-speed measurements with single point data acquisition times in the range of 0.1 milliseconds, but they often require a much longer time, e.g., on the order of 20 milliseconds or more, between single measurements to perform calculations and self-calibration. As a result, sequential temperature measurements of the wafer carrier and wafer are not easily obtained so as to obtain reliable temperature measurements from the wafer only.
A second approach employs a triggering function in which the pyrometer measurements are taken at a frequency close to the period of rotation for the wafer carrier. With this approach, the pyrometer provides data measurements scanned across the disk, i.e. a stroboscopic effect, to generate temperature data. The xe2x80x9cdown timexe2x80x9d between temperature measurements is used to achieve the above-mentioned calculations and self-calibration. However, this method also has its shortcomings. In particular, modern pyrometers often initiate an autonomous self-calibration with respect to the ongoing measurements of temperatures. Such autonomous self-calibration necessarily interferes with any periodic gathering of temperature data from the pyrometer and makes such temperature determinations on a periodic basis extremely difficult.
To overcome the difficulties of the above solutions, an encoder may be installed on the carousel spindle to provide a xe2x80x9ctriggerxe2x80x9d for the initiation of pyrometer measurements. This approach, however, requires additional system complexity related to the synchronization between the encoder and the wafer locations. Further, the delay in communications between the encoder and the pyrometer requires complex calibration procedures for each different rotation speed of the carousel and, therefore, requires recalibration when changing speeds.
In sum, the present level of pyrometer development does not allow for the implementation of a simple and reliable method of measuring the temperature of semiconductor wafers on a rapidly rotating carousel, particularly where the emissivity of the semiconductor wafer is varying over the measurement time.
In accordance with the present invention an apparatus has been provided for determining the real-time, non-contact temperature measurement of first and second fast moving entities. The first and second entities have first and second reflectivities, and are disposed in a fixed relationship with respect to each other. Further provided in the apparatus are a pyrometer for providing a series of temperature data related to the temperatures of the first and second entities respectively, each temperature datum having a temperature value, a reflectometer for providing a series of reflectivity data related to the first and second reflectivities, each reflectivity datum having a reflectivity value and correlated with a corresponding temperature datum so as to form a reflectivity-temperature data pair, and a computer having a memory for storing a set of computer instructions. The computer is coupled to the pyrometer and the reflectometer for receiving the series of temperature data and the series of reflectivity data and the set of computer instructions include instructions for creating a data table for storing the reflectivity-temperature data pairs according to a frequency of occurrence of each reflectivity value in the series of reflectivity data, instructions for identifying at least one reflectivity data peak representative of the first reflectivity characteristic within the data table, and instructions for determining at least the temperature of the first entity from the reflectivity data peak based upon the associated reflectivity-temperature data pairs.
In accordance with an embodiment of the present invention, the first entity is a semiconductor wafer and the second entity is a semiconductor wafer carrier, and the first reflectivity of the semiconductor wafer is higher than the second reflectivity of the semiconductor wafer carrier. Similarly, the first reflectivity of the semiconductor wafer is of a specular type and the second reflectivity of the semiconductor wafer carrier is of a diffuse type.
In accordance with another embodiment of the present invention the second entity rotates to at least 100 revolutions per minute and at least one of the series of temperature data and the series of reflectivity data are provided at a rate of at least 15 samples per second when the second entity rotates to at least 1000 revolutions per minute.
In accordance with a preferred embodiment of the present invention the set of computer instructions includes instructions for dividing a range of reflectivity values of the series of reflectivity data into a number of data bins, each data bin having a low index value and a high index value, each datum of the series of reflectivity data being assigned to one of the data bins by the computer instructions according to its reflectivity value. Further, the series of reflectivity data is a continuous series of datum points, and the set of computer instructions maintains a sliding data window including a constant number of data points from the continuous series of datum points by replacing an oldest datum point within the data window with each new datum point of the series of reflectivity data, the set of computer instructions assigning all data points within the data window to the data bins. In addition, the set of computer instructions may include a prefilter for disregarding data points within the series of reflectivity data having reflectivity values outside a given range of reflectivity values. In a further embodiment, the set of computer instructions includes a tracking filter that excludes the reflectivity-temperature data pair if the difference between the reflectivity value of a first reflectivity-temperature data pair and reflectivity values in a group of reflectivity-temperature data pair including the first reflectivity-temperature data pair exceeds a predetermined value. In a final embodiment, the set of computer instructions includes instructions for determining an alternative peak reflectivity value for the reflectivity data peak where the reflectivity peak is not easily identified.
In accordance with another embodiment of the present invention a method is provided for determining the real-time, non-contact temperature measurement of first and second fast moving entities including the steps of: providing a series of temperature data representative of a first temperature and a second temperature of the first and second entities respectively; providing a series of reflectivity data representative of a first reflectivity and a second reflectivity of the first and second entities respectively; correlating each reflectivity datum with a corresponding temperature datum so as to form reflectivity-temperature data pairs; sorting the series of reflectivity data into a data table according to a frequency of occurrence of each reflectivity datum; identifying at least one reflectivity data peak in the data table representative of the first reflectivity; and determining at least the first temperature of the first entity from the identified reflectivity data peak based upon the associated reflectivity-temperature pairs.
In accordance with another embodiment of the method of the present invention steps are provided for steps for dividing a range of reflectivity values of the series of reflectivity data into a number of data bins, each of the data bins representing a portion of the range of reflectivity values, and wherein the step of sorting the series of reflectivity data includes the step of assigning each reflectivity-temperature data pair to one of the data bins and the step of identifying at least one reflectivity data peak includes the step of selecting one of the data bins with the greatest number of reflectivity data values. Additionally, the following steps also optionally may be included: prefiltering the series of reflectivity data so as to remove data points having reflectivity values outside a given range of reflectivity values; tracking said series of temperature data and said series of reflectivity data; and excluding said reflectivity-temperature data pair if the difference between said reflectivity value of a first reflectivity-temperature data pair and the reflectivity values in a group of reflectivity-temperature data pairs including said first reflectivity-temperature data pair exceeds a predetermined value. In another embodiment of the present invention, the step of identifying at least one reflectivity data peak includes the step of determining an alternative peak value as the reflectivity data peak where the reflectivity peak is not easily identified. Finally, the method of the present invention may include the steps of windowing the series of reflectivity data so as to maintain a constant number of reflectivity data points from a continuous series of reflectivity data points for use in the steps of sorting, identifying and correlating. Finally, in a preferred embodiment of the method of the present invention, the step of identifying at least one data peak in the data table representative of the first reflectivity further includes identifying a high-valued reflectivity data peak with a greatest frequency of occurrence of reflectivity datum.
In accordance with yet another embodiment of the present invention a computer-readable medium is provided for storing a set of instructions for controlling a general purpose digital computer, the set of instructions causing the computer to provide a series of temperature data representative of a first temperature and a second temperature of the first and second entities respectively; provide a series of reflectivity data representative of a first reflectivity and a second reflectivity of the first and second entities respectively; correlate each reflectivity datum with a corresponding temperature datum so as to form reflectivity-temperature data pairs; sort the series of reflectivity data into a data table according to a frequency of occurrence of each reflectivity datum; identify at least one reflectivity data peak in the data table representative of the first reflectivity; and determine at least the first temperature of the first entity from the identified reflectivity data peak based upon the associated reflectivity-temperature pairs.
In accordance with yet another embodiment of the present invention a computer-readable medium is provided for storing a set of instructions for controlling a general purpose digital computer, the set of instructions causing the computer to divide a range of reflectivity values of said series of reflectivity data into a number of data bins, each of said data bins representing a portion of said range of reflectivity values, and wherein said instructions causing said computer to sort said series of reflectivity data include instructions causing said computer to assign each reflectivity-temperature data pair to one of said data bins and said instructions for causing said computer to identify at least one reflectivity data peak includes instructions causing said computer to select one of said data bins with the greatest number of reflectivity data values.
In accordance with yet another embodiment of the present invention, a computer-readable medium is provided for storing a set of instructions for controlling a general purpose digital computer, the set of instructions causing the computer to prefilter said series of reflectivity data so as to remove data points having reflectivity values outside a given range of reflectivity values; track said series of temperature data and said series of reflectivity data, and exclude a first reflectivity-temperature data pair if the difference between said reflectivity value of said first reflectivity-temperature data pairs and the reflectivity values in a group of reflectivity-temperature data pairs including said first reflectivity-temperature data pair exceeds a predetermined value. Further, in the instructions provided for causing said computer to identify at least one reflectivity data peak, instructions are provided to determine an alternative peak value when said reflectivity data peak is not easily identified. In addition, instructions are provided for causing said computer to window said series of reflectivity data so as to maintain a constant number of reflectivity data points from a continuous series of reflectivity data points for use in the instructions causing said computer to sort, identify and correlate. Finally, with respect to the instructions provided for causing said computer to identify at least one data peak in said data table representative of said first reflectivity, instructions are further provided for causing said computer to identify a high-valued reflectivity data peak with a greatest frequency of occurrence of reflectivity datum. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention is directed a medical electrode of the type having an insulating sleeve containing at least one electrical conductor, the conductor providing an electrical connection between a pulse generator at a proximal end of the electrode device and an electrode surface of the electrode device disposed remote from the proximal end.
2. Description of the Prior Art
Electrode devices of the type generally described above are employed for connecting, for example, a pacemaker or a defibrillator to cardiac tissue in order to sense the functioning of the heart, or to delivery therapeutic electrical energy in vivo to the heart. Generally, known electrode devices are composed of one or more helically wound metal wire conductors running from a contact at the proximal end, connected to the implantable pacemaker or defibrillator, and to an electrode surface disposed at or near the heart. The electrode surface may, for example, be in the form of a relatively small pacing electrode, a larger intracardiac defibrillation electrode, or an epicardiac patch electrode. The known electrode devices can be equipped with different types of sensors which are connected, via a metallic conductor, to the pacemaker or defibrillator.
Because the heart is in constant motion, electrode devices connected to or near the heart are constantly exposed to changes in load and stress. One or more of the metallic conductor wires can fracture, thereby breaking the electrical connection between the electrode surface or a sensor and the contact at the proximal end. If a plurality of metallic wires, electrically insulated from one another, are used, the insulation may sustain abrasion damage caused by the constantly shifting load, resulting in a short-circuit. Additionally, fabrication of the electrode device becomes more complex as the number of incorporated components increases, such as when a plurality of electrode surfaces and sensors must to be connected to single electrode device. | {
"pile_set_name": "USPTO Backgrounds"
} |
(1) Field of the Invention
This invention relates to integrated circuit (IC) packaging.
(2) Brief Description of Related Art
In the IC packaging art, the IC chip size tends to be smaller as time progresses. In cutting such small dimensions, chemical etching now replaces the mechanical sawing, because the damage caused by sawing propagates toward the IC itself.
FIG. 1 shows a prior art substrate 10 for an array of IC packages. Each package or block, as shown within the dot-dash line boundary, has two metal plates 11 and 12 serving as terminals for an IC chip 15, which is mounted on the metal plate 11. The bottom electrode of the IC chip 15 is coupled to the metal plate 11, and the top electrode of the IC chip 15 is wire-bonded by wire 16 to the metal plate 12. All the metal terminals are originally from a common metal substrate, but are etched through by chemical etching along the orthogonal grooves 14. The grooves are separated by narrow necks 13 to hold the metal in one piece. The necks 13 are later broken off to yield individual blocks.
The width W of the etched groove 14 should be as narrow as possible to increase the packing density of the packages per IC wafer. However, during chemical etching of the grooves 14, the minimum width W is proportional to the thickness of the metal substrate as shown in FIG. 2. In the upper section (A), the metal substrate 11, 12 is thin with thickness of T1 and the minimum separation of the groove is W1, because the etching solution etches both horizontally and vertically. If the metal substrate 11, 12 is thicker with a thickness of T2 as shown in section (B), then the minimum width of the groove W2 must necessarily be wider than W1. Thus, the prior art narrow groove is not compatible with thick metal substrate.
Hence, if the substrate on which the IC chip is mounted is too thin, the substrate is too fragile and tends to break. If the substrate is thick, the chemical etching widens the etched separation between adjacent blocks, as well as the separation W between leads on the same block, and lowers the packing density. | {
"pile_set_name": "USPTO Backgrounds"
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Deep brain stimulation can be useful for treating a variety of conditions including, for example, Parkinson's disease, dystonia, essential tremor, chronic pain, Huntington's Disease, levodopa-induced dyskinesias and rigidity, bradykinesia, epilepsy and seizures, eating disorders, and mood disorders. Typically, a lead with a stimulating electrode at or near a tip of the lead provides the stimulation to target neurons in the brain. Magnetic resonance imaging (MRI) or computerized tomography (CT) scans can provide a starting point for determining where the stimulating electrode should be positioned to provide the desired stimulus to the target neurons. To further refine the position, a recording lead with a recording electrode at or near the tip of the recording lead can be inserted into the brain of the patient to determine a more precise location. Typically, the recording lead is guided to the target location within the brain using a stereotactic frame and microdrive motor system.
As the recording lead is moves through the brain, the recording electrode is observed to determine when the recording electrode is near the target neurons. This observation may include activating the target neurons to generate electrical signals that can be received by the recording electrode. Once the position of the target neurons is determined, the recording lead can be removed and the stimulating lead inserted. The object of this removal of the recording lead and insertion of the stimulating lead is to attempt to precisely locate the target neurons. The precise insertion of the stimulating lead and positioning of the stimulating lead in the precise location indicated by the recording lead can be particularly difficult. In some instances, multiple insertions of the recording lead and stimulating lead may need to occur to properly position the stimulating electrode. | {
"pile_set_name": "USPTO Backgrounds"
} |
The present Application deals with related subject matter in co-pending U.S. patent application entitled METHOD FOR REDUCING TENSILE STRESS ZONES IN THE SURFACE A PART, filed on the same day as the present application and having the same inventor in common.
This invention relates to a method and an apparatus for imparting residual stress in the surface of a part and, more particularly, to a method of inducing a selected compressive residual stress distribution within the surface of a part to improve fatigue and stress corrosion performance of the part and an apparatus for implementing the method. Surface residual stresses are known to have a major effect upon the fatigue and stress corrosion performance of component parts. Tensile residual stresses, which can develop during manufacturing processes such as grinding, turning, or welding are well known to reduce both fatigue life and increase sensitivity to corrosion-fatigue and stress corrosion cracking of the part. Further, many parts that are subjected to high dynamic stresses or have areas where stress concentrations occur, such as blades and the rotor disks of turbo machinery, are prone to crack initiation and relatively rapid crack growth. The blades typically comprise an airfoil portion, a platform for partially defining a surface for fluid flow there over when the blade is mounted to the rotor disk, and a root portion having retention grooves which engage in corresponding axially extending complementary grooves of the disk. During engine operation, the rotor disk and the blade are subjected to large centrifugal loads that produce high dynamic stresses that may cause high cycle fatigue along portions of the rotor disk and the blade causing cracking and possible failure of the part. Further, the leading edge of the airfoil is often subjected to damage caused by the impact of foreign objects in the fluid stream. Such impact often results in cracks forming along the leading edge that may result in failure of the blade.
It is well known that compressive residual stresses induced in the surface of a part can increase fatigue life and reduce susceptibility to corrosion-fatigue and stress corrosion cracking. There are currently several methods used in industry for inducing compressive stress in the surface of a metal part and the particular method selected has been dependent on factors such as the dimensions and shape of the part, its strength and stiffness, the desired quality of the finished surface, the desired physical properties of the finished part, and the expense of performing the operation.
One method commonly used in industry to induce compressive stress in the surface of a part is shot peening, whereby a plurality of metallic or ceramic pellets are projected mechanically or through air pressure to impinge the surface of the part. While such a method is relatively inexpensive and is preferred for many applications, shot peening is unacceptable for parts requiring a superior finish or requiring a greater depth of compressive stress penetration and has also been found to be unacceptable for parts requiring localized or well defined compressive stress regions. Further, for parts such as a rotor disk for use in turbo machinery, the bore surfaces of the rotor disk are subjected to low levels of plastic strain (typically between about 0.2% to about 0.5%) when the rotor disk is accelerated to full speed. If the surfaces have been highly cold worked, such as during shot peening, the cold worked compressive surface material will not yield in tension while the lower yield strength interior material will yield during engine operation. On unloading, such as when the rotor speed is reduced, the surface is driven into tension and will remain in tension, reducing its fatigue life, for the remaining life of the component.
Another method commonly used in industry to induce compressive stress in the surface of a part is laser shock peening, whereby multiple radiation pulses from high power pulsed lasers produce shock waves on the surface of the part to produce a high magnitude localized compressive stress within a particular region. Unfortunately, however, laser shock peening is relatively expensive and time consuming making it unacceptable for many applications.
A method which have been developed and is widely used in industry to improve surface finish, fatigue life, and corrosion resistance by deforming the surface of a part is burnishing whereby a rotary or sliding burnishing member is pressed against the surface of the part in order to compress the microscopic peaks in the surface into adjacent hollows. Burnishing operates to develop compressive stresses within the part by yielding the surface in tension so that it returns to a state of compression following deformation.
The burnishing apparatus utilized for working the surface of a part typically comprise a plurality of cylindrical rollers or balls which contact the surface of the part with sufficient pressure to induce a compressive stress therein. Unfortunately, sharp surface demarcation typically exists along the boundaries of the burnished area often resulting in tensile residual stresses being formed along such boundaries. As disclosed herein, it has been found that gradually reducing the pressure being exerted by the burnishing member to reduce the magnitude of compression at the boundaries will reduce the build up of tensile residual stress. Further, it has been found that by controlling the compressive residual stress distribution and the magnitude of compression, the tensile stress distributions within a part may be offset or distributed in such a manner as to optimize the fatigue and/or stress corrosion performance of the part. Until now, however, a method and apparatus have not been developed that permitted the residual stress distributions and the magnitude of compression to be controlled in such a manner as to optimize fatigue performance for a specific applied stress distribution.
Consequently, a need exists for a relatively inexpensive, relatively time efficient method and apparatus for implementing the method for improving the physical properties of a part by inducing a layer of compressive stress in the surface of the part, which is effective for use with complex shaped surfaces, and which permits the magnitude of compression and the residual stress distributions to be produced on a surface to achieve optimum fatigue performance and stress corrosion performance of the part.
The novel method of the present invention for inducing a layer of compressive residual stress along the surface of a part comprises the steps of selecting a region of the part to be treated; selecting the magnitude of compression and the residual stress distribution to be induced in the surface of the selected region of the part; exerting pressure against the surface of the selected region, the pressure being applied in a selected pattern along the surface to form zones of deformation having a deep layer of compressive stress; and varying the pressure being exerted against the surface to produce the desired residual stress distribution and magnitude of compression within the surface.
In another preferred embodiment of the invention, the step of exerting pressure against the surface of the selected region included performing a burnishing operation using a burnishing apparatus having a burnishing member for exerting pressure against the surface of the selected region of the part to produce a zone of deformation having a deep layer of compression.
In another preferred embodiment of the invention, the pressure being exerted on the surface of the part induces a deep layer of compression within the surface having associated cold working of less than about 5.0%.
In another preferred embodiment of the invention, the pressure being exerted on the surface of the part induces a deep layer of compression within the surface having associated cold working of less than about 3.5%.
In another preferred embodiment of the invention, whereby the step of exerting pressure on the surface of the part is performed by a burnishing operation using a burnishing apparatus having a burnishing member for exerting pressure against the surface of the selected region to induce a deep layer of compression within the surface having associated cold working of less than about 5.0 percent.
In another preferred embodiment of the invention, whereby the step of exerting pressure on the surface of the part is performed by a burnishing operation using a burnishing apparatus having a burnishing member for exerting pressure against the surface of the selected region to induce a deep layer of compression within the surface having associated cold working of less than about 3.5 percent.
In another preferred embodiment of the invention, whereby the selected pattern operates to vary the spacing between the zones of deformation to produce the desired residual stress distribution.
In another preferred embodiment of the invention, the step of selecting the magnitude of compression includes the step of programming a control unit to automatically adjust the pressure being exerted against the surface of the part.
In another preferred embodiment of the invention, the step of exerting pressure against the surface of the selected region includes performing a burnishing operation and the step of programming a control unit to control the direction of movement of a burnishing member to produce the desired stress distribution.
In another preferred embodiment of the present invention the step of varying the pressure being exerted against the surface of a part includes the steps of programming a control unit to adjust the pressure being exerted by a burnishing member against the surface of the part, and programming the control unit to direct the burnishing member over the part in a selected pattern to obtain the desired residual stress distribution.
In another preferred embodiment of the present invention, the step of varying the pressure being exerted against the surface of a part includes the step of gradually varying the magnitude of compressive stress in the areas immediately adjacent to the boundaries of the selected region.
In another preferred embodiment of the present invention, a method of inducing a layer of compressive stress in the surface of a part comprises the steps of inducing a deep layer of compression within the surface and inducing a more shallow layer of compressive stress within the surface of the selected region.
In another preferred embodiment of the present invention, a method of inducing a layer of compressive stress in the surface of a part comprises the steps of inducing a deep layer of compression within the surface and removing a layer of material along the surface being in low compression or tension.
In another preferred embodiment of the present invention, the method of inducing a layer of compressive stress in the surface of a part comprises the steps of programming a control unit to adjust the pressure being applied by the burnishing member against the surface of the part; programming the control unit to direct the burnishing member over the part in a predetermined pattern to induce a layer of compressive stress in the surface of the part; and applying a secondary process to impart a relatively shallow layer of compressive residual stress along the surface of the part to produce the desired residual stress distribution.
The novel apparatus for implementing the method of the present invention utilizes a burnishing process for inducing a layer of compressive residual stress having a preselected magnitude of compression and a desired stress distribution. In particular, the burnishing apparatus comprises a burnishing member for applying pressure against the surface of the selected region of the part to produce a zone of deformation having a deep layer of compression and a preselected magnitude within the surface. The burnishing apparatus further comprises means for moving the burnishing member in a predetermined pattern across the selected region to produce a desired residual stress distribution.
In another preferred embodiment of the invention the burnishing apparatus for implementing the burnishing method of the subject invention comprises a burnishing member for applying pressure against the surface of a part to induce a layer of compressive stress therein; means for adjusting the pressure being applied against the surface of the part by the burnishing member; and means for directing the burnishing member over the surface of the part in a predetermined pattern to provide the desired residual stress distribution.
In another preferred embodiment of the invention, the burnishing apparatus for implementing the burnishing method of the subject invention is coupled to a control unit for automatically controlling the movement, position, and application pressure of the burnishing member.
In another preferred embodiment of the invention, the burnishing apparatus for implementing the burnishing method of the subject invention comprises means for supplying a constant flow of fluid to support the burnishing member.
In another preferred embodiment of the invention, the burnishing apparatus for implementing the burnishing method of the subject invention comprises magnetic means for maintaining the burnishing member within the socket.
Another preferred embodiment of the invention is a blade for use in turbo machinery having a desired stress distribution.
Another preferred embodiment of the invention is a rotor disk for use in turbo machinery comprising selected regions having desired stress distributions.
Another preferred embodiment of the invention, a part selected from the group consisting of automotive parts, aircraft parts, marine parts, engine parts, motor parts, machine parts, drilling parts, construction parts, pump parts, and the like comprises regions of compressive residual stresses having predetermined stress distributions.
Another preferred embodiment of the invention, a part selected from the group consisting of automotive parts, aircraft parts, marine parts, engine parts, motor parts, machine parts, drilling parts, construction parts, pump parts, and the like treated by the method comprising the step, or a combination of steps, of the present invention.
A primary object of this invention, therefore, is to provide a method and an apparatus for implementing the method of providing a part with an improved finish and with improved physical properties.
These and other objects and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
This invention relates generally to a radio communication apparatus comprising part of a radio communication system such as a code division multiple access (CDMA) communication system. More specifically, it relates to a radio communication apparatus employing a rake receiver which combines the useful multipath components of a spread spectrum signal.
2. Description of the Background Art
The CDMA communication system has been standardized by the Telecommunications Industry Association (TIA) for use in North America and has adapted spread spectrum communication technology. The mobile station used in this system is described in the TIA/EIA Interim Standard xe2x80x98Mobile Station-Base station Compatibility Standard For Dual-Mode Wide Band Spread Spectrum Cellular Systemxe2x80x99 (Interim Standard IS-95 Section 6.2.2.1).
In accordance with this standard, each mobile station is provided with a rake receiver, having at least one searcher for independent pilot channel acquisition and at least three fingers for data acquisition. The searcher searches for a pilot channel transmitted by a base station sending a pseudo-random number (PN) binary code reference sequence with no modulation of information bits thereon. Reception of the pilot channel makes it possible for each mobile station to synchronize with any other channel and to select the paths/delays for which the energy of a received signal on the traffic channel is greatest. Based on the pilot channel received by the searcher, each finger receives a useful multipath component of a received signal at a different timing. A receiver of this type is described by Wang et al. in a paper titled xe2x80x98Portable Telephone for CDMA Cellular Systemxe2x80x99, Oki Technical Review, 150 Vol. 60 (August 1994).
In the CDMA communication system, for example, a conventional mobile station pursuant to the Interim Standard IS-95 includes generally one searcher and three fingers. The number of searchers and the number of fingers is fixed in conventional CDMA systems and does not change in response to transmission characteristics.
However, in the field of mobile radio communications employing a CDMA communication system, the transmission characteristics existing between the base stations and the mobile stations change continuously because, in general, the location of each mobile station relative to a base station changes. Thus, the strength of the signal received by a mobile station may be reduced and therefore searchers in excess of the predetermined number are required if all pilot channels of neighboring base stations are to be searched quickly.
As one solution to this problem, mobile stations have been provided with one or more additional searchers. However, this is inefficient because the additional searchers make it necessary to increase the size of the receiver, add components which are used during only a portion of the time the receiver is in operation, and increase the power consumed by the receiver.
Therefore, it is an object of the present invention to provide a radio communication apparatus including a rake receiver which adaptively assigns a searcher operation and a finger operation in response to the characteristics of the transmission path existing at a given time between the base and mobile stations.
To accomplish these objectives, a radio communication apparatus is provided which comprises:
at least one combination searcher/finger unit operable to perform (1) a searcher operation for detecting signals on the reception paths and (2) estimating the strength of each of the signals, and a finger operation for outputting a demodulated symbol in response to a command signal. The radio communication apparatus is further provided with an assignment unit for generating the command signal to assign either the searcher operation or the finger operation of a combination searcher/finger unit based on at least one of the following conditions:
(1) the number of useful information containing reception paths which can be demodulated; or
(2) the number of neighboring base stations; or
(3) the total signal strength of the useful reception paths; or
(4) the reception error rate of the combined signal; or
(5) the reception modes having an initial synchronizing mode for synchronizing with one of the base stations, a call waiting-mode for waiting for a call from the synchronized base station and a communication mode for communicating to the synchronized base station. | {
"pile_set_name": "USPTO Backgrounds"
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The leukocyte differentiation antigen CD33 is a 364 amino acid transmembrane glycoprotein with sequence homology to members of the sialoadhesin family, including myelin-associated glycoprotein and CD22, as well as sialoadhesin itself (S. Peiper, 2002, Leucocyte Typing VII, White Cell Differentiation, Antigens, Proceedings of the Seventh International Workshop and Conference, Oxford University Press, p. 777).
Expression of CD33 appears to be highly specific to the hematopoietic compartment, with strong expression by myeloid precursor cells (S. Peiper, 2002). It is expressed by myeloid progenitor cells such as CFU-GEMM, CFU-GM, CFU-G and BFU-E, monocytes/macrophages, granulocyte precursors such as promyelocytes and myelocytes although with decreased expression upon maturation and differentiation, and mature granulocytes though with a low level of expression (S. Peiper, 2002).
In contrast, pluripotent hematopoietic stem cells that give rise to “blast colonies” in vitro (Leary, A. G. et al., 1987, Blood 69:953) and that induce hematopoietic long-term marrow cultures (Andrews R. G. et al., 1989, J. Exp. Med. 169:1721; Sutherland, H. J. et al., 1989, Blood 74:1563) appear to lack expression of CD33.
While the specific function of CD33 is unknown, its homology to sialoadhesin suggested a role in carbohydrate binding characteristic of the lectin family, a role later confirmed (S. Peiper, 2002).
Importantly, anti-CD33 monoclonal antibodies have shown that CD33 is expressed by clonogenic, acute myelogenous leukemia (AML) cells in greater than 80% of human cases (LaRussa, V. F. et al., 1992, Exp. Hematol. 20:442-448).
Due to the selective expression of CD33, immunoconjugates that combine cytotoxic drugs with monoclonal antibodies that specifically recognize and bind CD33 have been proposed for use in selective targeting of AML cells. Such therapies are expected to leave stem cells and primitive hematopoietic progenitors unaffected. Immunoconjugates that utilize anti-CD33 antibodies include anti-CD33-ricin immunoconjugates that have been shown to be highly lethal to AML cells (Roy, D. C. et al., 1991, Blood 77:2404; Lambert, J. M. et al., 1991, Biochemistry 30:3234), yet spare the stem cells that support normal hematopoiesis and hematopoietic reconstitution (LaRussa, V. F. et al., 1992, Exp. Hematol. 20:442-448).
Additional studies using immunoconjugates have shown rapid targeting of radiolabeled anti-CD33 antibodies to leukemic blast cells in peripheral blood and marrow when administered i.v. (Scheinberg, D. A. et al., 1991, J. Clin. Oncol. 9: 478-490; Schwartz, M. A. et al., 1993, J. Clin. Oncol. 11:294-303). Rapid internalization of the antibody by the target cell was also observed in in vitro studies (Tanimot, M. et al., 1989, Leukemia 3: 339-348; Divgi, C. R. et al., 1989, Cancer Res. Suppl. Vol. 30: 404a). Evaluation of a humanized anti-CD33 antibody conjugated to the potent antitumor antibiotic calicheamicin (Gemtuzumab ozogamicin) in pre-clinical studies demonstrated specific killing of leukemia cells in HL-60 cell cultures, HL-60 tumor xenografts in mice, and marrow samples from AML patients (Hamann, P. R. et al., 2002, Bioconjugate Chem. 13: 47-58).
Based on the positive results of these pre-clinical studies, Gemtuzumab ozogamicin was evaluated in phase I and II clinical studies. In Phase I studies, the major toxicity observed was myelosuppression due to the expression of CD33 on myeloid progenitor cells (Sievers, E. L. et al. 1999, Blood 93: 3678-3684; Sievers E. L. et al., 2001, J. Clin. Oncol. 19: 3244-3254.). Phase II studies with a dose of 9 mg/m2 i.v. over 4 hours, repeated after 14 days, yielded a response rate of 30%. Marketing approval of Gemtuzumab ozogamicin was granted by the FDA in May 2000 with indication for the treatment of patients with CD33 positive AML in first relapse who are 60 years of age or older and who are not considered candidates for cytotoxic chemotherapy. Post-marketing reports have indicated the potential for significant toxicity, especially venoocclusive disease (VOD), which has led to labeling revisions and initiation of a patient surveillance program. Much of this toxicity may be related to the drug component calicheamicin, which was shown to cause hepatotoxicity in pre-clinical models, and therefore may not be a direct result of targeting CD33.
While the results discussed above suggest that immunoconjugates comprising an anti-CD33 antibody and a cytotoxic drug may be successfully used in the treatment of AML, there is a need for immunoconjugates that are both safe and effective. The present invention is directed to these and other important ends. | {
"pile_set_name": "USPTO Backgrounds"
} |
Naturally occurring signals, such as speech, geophysical signals, images, etc., have a great deal of inherent redundancies. Such signals lend themselves to compact representation for improved storage, transmission and extraction of information. Efficient representation of one and multidimensional signals, employing a variety of techniques has received considerable attention and many excellent contributions have been reported.
Vector Quantization is a powerful technique for efficient representation of one and multidimensional signals [see Gersho A.; Gray R. M. Vector Quantization and Signal Compression, Kluwer Academic Publishers, 1991.] It can also be viewed as a front end to a variety of complex signal processing tasks, including classification and linear transformation. It has been shown that if an optimal Vector Quantizer is obtained, under certain design constraints and for a given performance objective, no other coding system can achieve a better performance. An n dimensional Vector Quantizer V of size K uniquely maps a vector x in an n dimensional Euclidean space to an element in the set S that contains K representative points i.e.,V:xεRn→C(x)εS
Vector Quantization techniques have been successfully applied to various signal classes, particularly sampled speech, images, video etc. Vectors are formed either directly from the signal waveform (Waveform Vector Quantizers) or from the LP model parameters extracted from the signal (Mode based Vector Quantizers). Waveform vector quantizers often encode linear transform, domain representations of the signal vector or their representations using Multiresolution wavelet analysis. The premise of a model based signal characterization is that a broadband, spectrally flat excitation is processed by an all pole filter to generate the signal. Such a representation has useful applications including signal compression and recognition, particularly when Vector Quantization is used to encode the model parameters.
Recently, it has been shown that representation of signals in multiple nonorthogonal domains of representation reveals unique signal characteristics that may be exploited for encoding signals efficiently. See: Mikhael, W. B., and Spanias, A., “Accurate Representation of Time Varying Signals Using Mixed Transforms with Applications to Speech,” IEEE Trans. Circ. and Syst., vol. CAS-36, no: 2, pp. 329, February 1989; Mikhael, W. B., and Ramaswamy, A., “An efficient representation of nonstationary signals using mixed-transforms with applications to speech,” IEEE Trans. Circ. and Syst. II: Analog and Digital Signal Processing, vol: 42 Issue: 6, pp: 393-401, June 1995; Mikhael, W. B., and Ramaswamy, A, “Application of Multitransforms for lossy Image Representation,” IEEE Trans. Circ. and Syst. II: Analog and Digital Signal Processing, vol: 41 Issue: 6, pp. 431-434 June 1994; Berg, A. P., and Mikhael, W. B., “A survey of mixed transform techniques for speech and image coding,” Proc. of the 1999 IEEE International Symposium Circ. and Syst., ISCAS '99, vol. 4, 1999; Berg, A. P., and Mikhael, W. B., “An efficient structure and algorithm for image representation using nonorthogonal basis images,” IEEE Trans. Circ. and Syst. II, pp: 818-828 vol. 44 Issue: 10, October 1997; Berg, A. P., and Mikhael, W. B., “Formal development and convergence analysis of the parallel adaptive mixed transform algorithm,” Proc. of 1997 IEEE International Symposium Circ. and Syst., Vol. 4,1997 pp. 2280-2283; Ramaswamy, A., and Mikhael, W. B., “A mixed transform approach for efficient compression of medical images,” IEEE Trans. Medical Imaging, pp. 343-352, vol 15 Issue: 3, June 1996; Ramaswamy, A., and Mikhael, W. B., “Multitransform applications for representing 3-D spatial and spatio-temporal signals,” Conference Record of the Twenty-Ninth Asilomar Conference on Signals, Syst. and Computers, vol: 2, 1996; Mikhael, W. B., and Ramaswamy, A., “Resolving Images in Multiple Transform Domains with Applications,” Digital Signal Processing—A Review, pp. 81-90, 1995; Ramaswamy, A., Zhou, W., and Mikhael, W. B., “Subband Image Representation Employing Wavelets and Multi-Transforms,” Proc. of the 40th Midwest Symposium Circ. and Syst., vol: 2, pp: 949-952, 1998;. Mikhael, W. B., and Berg, A. P., “Image representation using nonorthogonal basis images with adaptive weight optimization,” IEEE Signal Processing Letters, vol: 3 Issue: 6, pp: 165-167, June 1996; and Berg, A. P., and Mikhael, W. B., “Fidelity enhancement of transform based image coding using nonorthogonal basis images,” 1996 IEEE International Symposium Circ. and Syst., pp. 437-440 vol. 2, 1996.]
A search was carried out which encompassed a novel software system which overcame the problem of transmitting different types of data such as speech, image, video data within a limited bandwidth. The searched system of the invention hereafter disclosed initially passes data separately through various transform domains such as Fourier Transform, Discrete Cosine Transform (DCT), Haar Transform, Wavelet Transform, etc. In a learning mode the invention represents the data signal transmissions in each domain using a coding scheme (e.g. bits) for data compression such as a split vector quantization scheme with a novel algorithm. Next, the invention evaluates each of the different domains and picks out which domain move accurately represents the transmitted data by measuring distortion. The dynamic system automatically picks which domain is better for the particular signal being transmitted.
The search produced the following nine patents:
U.S. Pat. No. 4,751,742 to Meeker proposes methods for prioritization of transform domain coefficients and is applicable to pyramidal transform coefficients and deals only with a single transform domain coefficient that is arranged according to a priority criterion;
U.S. Pat. No. 5,402,185 to De With, et al discloses a motion detector which is specifically applicable to encoding video frames where different transform coding techniques are selected on the determination of motion;
U.S. Pat. No. 5,513,128 to Rao proposes multispectral data compression using inter-band prediction wherein multiple spectral bands are selected from a single transform domain representation of an image for compression;
U.S. Pat. No. 5,563,661 to Takahashi, et al. discloses a method specifically applicable to image compression where a selector circuits picks up one of many photographic modes and uses multiple nonorthogonal domain representations for signal frames with an encoder that picks up a domain of representation that meets a specific criterion;
U.S. Pat. No. 5,703,704 to Nakagawa, et al. discloses a stereoscopic image transmission system which does not employ signal representation in multiple domains;
U.S. Pat. No. 5,870,145 to Yada, et al. discusses a quantization technique for video signals using a single transform domain although a multiple nonorthogonal domain Vector Quantization is proposed;
U.S. Pat. No. 5,901,178 to Lee, et al. describes a post-compression hidden data transport for video signals in which they extract video transform samples in a single transform domain from a compressed packetized data stream and use spread spectrum techniques to conceal the video data;
U.S. Pat. No. 6,024,287 to Takai, et al. discloses a Fourier Transform based technique for a card type recording medium where only a single domain of representation of information is employed: and,
U.S. Pat. No. 6,067,515 to Cong, et al. discloses a speech recognition system based upon both split Vector Quantization and split matrix quantization which materially differs from a multiple domain vector quantization where vectors formed from a signal are represented using codebooks in multiple redundant domains.
It would be highly desirable to provide a vector quantization approach in multiple nonorthogonal domains for both waveform and model based signal characterization. | {
"pile_set_name": "USPTO Backgrounds"
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Given that volatile memory (also sometimes referred to as “main memory”) is becoming cheaper and larger, more data can be cached from disk storage to volatile memory. Such caching allows the data to be accessible faster, and for the application that uses the data, to perform work in a speedier fashion.
However, a number of challenges still remain with making data accessible in volatile memory. Firstly, the amount of data that is typically used by applications has also significantly increased. Particularly, to completely cache larger amounts of data (colloquially referred as “big data”) in volatile memory would require an exuberant amount of volatile memory. Thus, regardless of the size of volatile memory, there may still exist data (and in some cases a signification portion of data) that could not be concurrently cached in the volatile memory. Such data would to be accessed from disk storage and loaded into cache on an as-needed basis (replacing other data in the cache).
When a database system needs to perform operations on non-cached data, the data in the disk storage needs to be first read from the disk storage into the volatile memory of the database system. Once loaded into volatile memory, the database system can perform the operations on the data. However, reading data from the disk storage generally incurs a significant performance penalty compared to obtaining data that already resides in volatile memory. Thus, when a database system needs to perform operations on non-cached data, the database system fails to experience significant performance gains from the fact that the database system has a large amount of volatile memory.
One approach to fit more data onto volatile memory is to compress the data before storing the data into the volatile memory. Once compressed, the data would be resized to occupy less space in the volatile memory. However, not all data can be significantly compressed. Furthermore, if the compressed data is frequently accessed for operations, the data would need to be frequently decompressed to be used. Such frequent decompressions use compute resources that otherwise could have been used for data operations, slowing the data operations and consequently, the applications that requested the data operations. Accordingly, there is a significant drawback in indiscriminate data compression for data cached in volatile memory.
Furthermore, no matter at what level of compression data is copied into volatile memory, at some point the database system would still run out of space in volatile memory to store more data. Thus, when the volatile memory is at full capacity and a the database system needs to perform an operation on data that is solely stored on disk storage, some of data already in the volatile memory would need to be replaced to make room for the data from the disk storage. The more frequent such replacements, the more compute resources are wastefully spent on shuffling data in and out of the volatile memory. Thus, minimizing the frequency of data replacement would contribute to efficient performance of the database system.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
This invention relates to the field of consumer devices, and in particular to the field of automated home control systems.
2. Description of Related Art
Home automation is becoming increasingly popular. Standards continue to be developed which will allow devices of varying types and varying vendors to be controlled by a common controller. Such standards include IEEE 1394, X-10, HAVi, HomeAPI, Jini, and the like. IEEE 1394 and X-10 are communication protocols; HAVi is a software architecture using IEEE 1394; Home API is an open industry specification that defines a standard set of software services and application programming interfaces which enable software applications to monitor and control home device. Jini is a distributed software architecture (network) wherein clients see devices and services as objects.
Some home automation systems may include a monitoring and reporting system that maintains a record of selected events. For example, U.S. Pat. No. 4,644,320, “HOME ENERGY MONITORING AND CONTROL SYSTEM”, issued Feb. 17, 1987 for Carr et al, incorporated by reference herein, presents a system that periodically records the temperature inside and outside the home, and a cumulative energy usage, measured via energy measuring devices that are attached to appliances such as furnaces, air conditioners, and the like. Statistics are also provided and presented as text or graphic displays to facilitate a user's assessment of the energy usage, and potentially effect a change of habit to reduce such usage.
Typical home automation systems are configured to provide a central control station and a number of remote controllers. For example, the central control station may be a home computer, and the remote controllers may be sub-controllers located in particular areas of the home, such as in a master bedroom, entry foyer, and the like. Typical home automation systems may also include remote sensors that are used, for example, to automatically turn lights on or off when motion is detected, or to turn a television set on or off in response to a particular sound or voice command. Some home automation systems allow the desired operations to be preprogrammed, so that, for example, lights or appliances are turned on or off at different preset times, televisions are tuned to different channels at different times, and so on.
As detailed above, most home automation systems are fundamentally “unidirectional”: information flows from the user to the appliance. The user provides commands to appliances, either directly or indirectly, and the appliance is controlled to effect the command. Some appliances are available that contain a degree of “intelligence” to effect a “bidirectional” information flow by communicating information to the user regarding their status, available options, and so on. Such a bidirectional information flow capability, however, is typically available only from fairly sophisticated appliances, such as home-entertainment systems, wherein the additional cost associated with providing the “intelligence” required is insubstantial, or deemed to be worthwhile to effect a product differentiation. Also, even if a majority of future appliances contain sufficient intelligence to communicate their status to a home automation system, the cost of replacing every legacy appliance in one's home to obtain such intelligent appliances will be cost-prohibitive to most users. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
The present invention relates to a method of depositing rare earth oxide thin films. In particular, the invention concerns a method of growing yttrium, gadolinium and lanthanum oxide thin films by Atomic Layer Deposition (referred to as ALD hereinafter).
ALD has previously been known as Atomic Layer Epitaxy (ALE) and later more specifically as Atomic Layer Chemical Vapour Deposition (Atomic Layer CVD™ and ALCVD™) process which are trademarks of ASMI®. ALD has been adopted as a general name of the method to avoid possible confusion when discussing about polycrystalline and amorphous thin films. Other names used in the literature for ALD are digital epitaxy, digital layer epitaxy (DLE), atomic layer growth, atomic layer processing, deposition layer by layer, sequential CVD, cycle CVD, cyclic CVD and pulsed CVD. The ALD method is based on sequential self-saturated surface reactions.
2. Description of Related Art
According to N. N. Greenwood et al. (Chemistry of the Elements, 1st edition, Pergamon Press Ltd., U.K., 1986, page 1423) “rare-earth elements” comprise Sc, Y, La and lanthanide series from Ce to Lu. These elements belong to metals. Oxides of rare earth elements are called rare earth oxides, REOx. A general symbol Ln is often used in the literature to refer to the fourteen lanthanide elements cerium to lutetium inclusive. Sometimes lanthanides are also called as “lanthanons” or “lanthanoids”. REOx thin films have potential applications in compound semiconductor and/or silicon based microelectronics. Compound semiconductors have several advantages compared to silicon. Especially, electron mobility is remarkably higher in compound semiconductors than in silicon. Therefore, it is possible to produce faster components from compound semiconductors. Furthermore, compound semiconductors are efficient light emitters enabling easy integration to light emitting components.
One remarkable problem related to compound semiconductors is lack of passivating and dielectric native oxide (compare SiO2 on silicon). So far, no other oxide has worked successfully in compound semiconductor MOSFETs (metal-oxide-semiconductor filed effect transistors) resulting in low space densities on semiconductor-insulator interface. In 1999 M. Hong et al. (Science 283 (1999) 1897) showed that the requirements for MOSFET insulator could be fulfilled by growing an epitaxial layer of Gd2O3 on GaAs surface. At the same time, it was disclosed that other rare earth oxides would work similarly.
In silicon based integrated circuits, REOx is a potential material to replace SiO2 as the gate oxide in MOSFETs. To reach the required capacitance, the thickness of SiO2 should be reduced to a level where the tunneling of the charge through the insulator becomes evident. Therefore, to avoid the problem, SiO2 must be replaced with material that has higher dielectric constant than SiO2, is thermally stable in contact with silicon and which can be formed on silicon in a controlled manner SiO2 layer or electrically active defects must not be formed at the interface between silicon and the insulator and the thickness of the dielectric layer should be carefully controlled.
SiO2 may be formed to an interface between silicon and the dielectric because of interaction between silicon and the dielectric or because of oxidation that takes place during depositing the dielectric layer or during a high-temperature anneal. Favorably, the deposition process of the dielectric is carried out at low temperature, where the formation of SiO2 is kinetically hindered.
REOx are thermodynamically stable when contacted with silicon oxide. Therefore, REOx are suitable dielectrics on silicon.
Yttrium oxide and lanthanum oxide are interesting thin film materials especially in the point of view of the semiconductor industry. Y2O3 thin films have been produced by many different processes, whereas considerably less research has been focused on La2O3. The production of Y2O3 and La2O3 thin films by different methods and their applications are surveyed in the literature. The production methods of the thin films are roughly divided into physical and chemical processes including both gas phase and liquid phase methods.
Because of the physical properties of Y2O3 such as the crystallographic stability up to 2330° C., high mechanical strength, high dielectric constant and the value of the refractive index, Y2O3 thin films have many potential applications (Gabordiaud, R. J. et al., Appl. Phys. A 71 (2000) 675-680). Especially interesting feature, from point of view of electronic applications, is quite good compatibility of the lattice constant of Y2O3 with silicon: a(Y2O3)=10.60 Å and a (Si)·2=10.86 Å (Cho M.-H. et al., J. Appl. Phys. 85 (1999) 2909-291).
Perhaps the most important application of Y2O3 thin films is to use them in transistors as an alternative gate oxide material having a high dielectric constant. The significance and use of an alternative gate oxide material is described in more detail later. Another application for the dielectric thin film in silicon technology is capacitor dielectric in DRAM-memories (dynamic random-access memory) (Kingon et al, Nature 406 (2000) 1032-1038).
Y2O3 thin films have been used as buffer layers for example for ferroelectrics and new high temperature superconductors. Y2O3 is also an important material in optical applications. For example, Y2O3 thin films have been used as dielectric layer in electroluminescent displays. Y2O3 matrix activated with europium has red luminescence and can be used, e.g., in fluorescent lamps and CRT tubes. Y2O3 has proved to be useful as a protective coating.
Despite the interesting properties of La2O3, possible applications of the La2O3 thin films have been studied rather little for the time being. La2O3 thin films have been used as optical and protective coatings. La2O3 coatings have been used also in gas sensor and catalytic applications. However, because of the high dielectric constant and compatibility with silicon, La2O3 is a possible gate oxide material in the future. Promising results have been recently reported by replacing SiO2 with La2O3 as a gate oxide.
Continuous decrease of the size of the electronic components has set severe restrictions on the performance of the SiO2 gate oxide. Thickness of the gate oxide approaches the quantum tunneling junction of 10 Å for SiO2. An alternative solution is to find a new dielectric material having a dielectric constant κ essentially higher than 3.9 for SiO2. The substituting alternative dielectric material has to be thermally stable at temperatures even over 1000 K, due to high-temperature anneals required in modern silicon processes. Equivalent thickness of SiO2 teq has to be below 15 Å. Equivalent thickness of SiO2 is defined with an equation: t eq = t ox ( κ SiO 2 κ ox ) , ( 1 ) wherein tox is the actual thickness of the alternative dielectric material, κSiO1 is the dielectric constant 3.9 of SiO2 and κox is the dielectric constant of the alternative dielectric material.
The principle and applications of atomic layer deposition (ALD) are described extensively below. Since the deposition temperature is considerably high in most thin film deposition methods, ALD opens new possibilities to use low deposition temperature. According to literature, the Y2O3 thin films have been deposited for time being only by using Y(thd)3 or derivatives thereof as the ALD source material.
In the atomic layer deposition method the principle is to feed source materials by alternately pulsing them into the reactor space. During each source material pulse excess source material is present in the gas phase of the reaction space in order to saturate the substrate surface. The excess of the source material that is physi-sorbed on a surface or which is in a gas phase inside the reactor is purged away with an inert gas flow during the time interval between different source chemical pulses. In an ideal case only one atom layer or a specific fraction thereof is chemisorbed onto the substrate. Another source material pulsed subsequently reacts with the chemisorbed layer. The growth of film is controlled by the surface reactions, so the duration of the source material pulses does not need to be controlled as precisely as in other CVD methods.
In an ideal case, a single atomic or molecular layer is grown during one source material pulse, but in practice the growth rate remains considerably lower. Reason to this is most commonly steric hindrances due to the size of the source material molecules.
An ALD type process is controlled by surface reactions, which can often be controlled by process temperatures and gas flowing rates. An appropriate temperature range is called ALD (or ALE) window. Parameters preventing the ALD growth outside the ALD window are shown in FIG. 1 (Niinistö et al., Proc. Int. Semicond. Conf. (2000) 33-42).
Mölsä et al. (Adv. Mater. Opt. Electron. 4 (1994) 389-400) have grown Y2O3 thin films in a flow-type ALD reactor using Y(thd)3 and oxygen or ozone as the source materials. The aim of the study was to produce a Y2O3 buffer layer for high temperature superconductor films. The effect of the substrate material, pressure and pulsing time on the properties of the thin film was examined. The tested growth temperature range was from 425 to 600° C., which is too high for many applications. The growth rate was determined to be about 0.8 Å/cycle, but the growth rate was observed to increase with the increasing temperature. This indicates the lack of so called ALD window, which was the basic starting point for further studies of Putkonen et al. (Chem. Vap. Deposition 7 (2001) 44-50).
Putkonen et al. studied the ALD deposition of the Y2O3 thin films in the temperature range of 200-425° C. by using Y(thd)3-, Y(thd)3(bipyridyl)- or Y(thd)3(1,10-fenantroline) compounds as the metal source and ozone as the oxygen source. A constant growth rate of 0.22-0.23 Å/cycle was observed in the temperature range of 250-350° C. for all source materials. The ALD window representing the observed controlled growth is shown in FIG. 2. This temperature range is considerably lower than temperatures used previously in CVD depositions of the Y2O3 thin films. However, the growth rate remained unpractically low. Also the hydrogen and carbon impurity levels were rather high. FIG. 2 depicts carbon and hydrogen content as a function of the deposition temperature.
Crystallinity and orientation of the films depended on the deposition temperature. Crystallinity increased strongly as the deposition temperature was elevated over 375° C. The films grown onto Si(100) and soda lime glass substrates at the deposition temperature of 350° C. were polycrystalline with (400) and (440) reflections being dominant (FIG. 3).
Despite the application possibilities of La2O3, only few articles have been published in literature on the deposition of the La2O3 thin films. Electron spray evaporation, different thermal vaporizing processes, pulsating laser deposition and atom spray deposition amongst physical methods have been used. Only pyrolysis, CVD, and ALD (Seim H. et al., Appl. Surf. Sci. 112 (1997) 243-250, Seim H. et al., J. Mater. Chem. 7 (1997) 449-454 and Nieminen N. et al. Appl. Surf. Sci., in press) represent the chemical deposition methods.
Nieminen et al. studied ALD depositions of La2O3 using La(thd)3 as a lanthanum source in order to find an ALD window. A temperature range from 180 to 425° C. was examined. Si(100) and soda lime glass were used as substrates. The growth rate of the films as a function of temperature is shown in FIG. 4. The pulsing time for La(thd)3 was 0.8 s and for ozone 2 s. A constant growth rate of 0.36 Å/cycle was detected for the temperature range from 225 to 275° C. Therefore a self-controlling deposition process typical to ALD was observed at this temperature range. X-ray diffraction (XRD) measurements on films showed to be comparable with the data presented by Seim et al. Stoichiometry and carbon content of the films were determined by TOF-ERDA (Time-of-Flight Elastic Recoil Detection Analysis) and RBS (Rutherford Backscattering Spectrometry). The carbon content depended on the deposition temperature (FIG. 4). However, in the range of the self controlled growth the elemental contents correspond to those of La2O2CO3, indicating very poor quality of the resultant film because of the carbonate incorporation. Bending vibrations were observed in the IR-measurements of films grown over 350° C. because of the hydroxyl groups present in the film. | {
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This invention relates generally to angle measurement devices and more particularly to such devices in which the measurement is made with respect to gravity using a resistive sensor in conjuction with lead circuitry.
Several angle measurement devices are known in the prior art, of which U.S. Pat. Nos. 4,503,622, 4,707,927, 4,547,972, 4,866,850, and 5,083,383 are exemplary. These prior art angle measurement devices typically employ an angle sensor that is physically separated from the electronics employed in the devices. The angle sensors are generally of the resistive type employing a potentiometer having an attached pendulum to reference gravity or of the resistive type employing a liquid-filled glass vial. The resistive type prior art sensors suffer inaccuracies due to friction in the pivot joint, while the resistive type sensors employing glass vials are expensive to produce. The physical separation of either type of sensor from its associated electronics is disadvantageous, particularly in the case of capacitive sensors in which the length of leads connecting the electronics to a remotely located sensor or the movement of those leads affects the capacitance of the sensor.
U.S. Pat. No. 4,644,662 is directed to a capacitive type angle sensor that employs a teflon coating on the sensor plates to insulate them from the fluid contained within the sensor and to serve as part of the sealing mechanism. These sensors are also taught to be remotely mounted. The coating on the sensor plates, in conjunction with rings machined into the sensor housing, serves to seal the fluid inside the sensor. However, this sealing arrangement is prone to leakage if the housing screws are not precisely torqued. In addition, the maximum temperature at which these prior art sensors can operate is limited because at higher temperatures the vapor pressure inside the fluid vessel increases to a point beyond which the sealing rings are not effective, thereby permitting the undesirable loss of fluid. Also, the types of sensors that incorporate a fluid as the sensing medium are generally desigend for static applications because, as the sensor is rotated, acceleration forces acting upon the fluid will cause the fluid to slosh, resulting in inaccurate indications. The rate at which the fluid will slosh is determined by the rate of accleration to which the user subjects the sensor.
It is therefore a principal object of the present invention to provide an improved angle measurement device in which the angle sensor and associated electronics are an integral unit, thereby eliminating the problems associated with prior art angle measurement devices in which those components are physically separated.
It is a further object of the present invention to provide an improved angle measurement device in which the containment of the sensor fluid is accomplished in a way that permits operation at higher temperatures than was previously possible.
It is yet another object of the present invention to provide an improved angle measurement device in which the user may remotely control the operation of an internal lead circuit that serves to compensate for acceleration to which the sensor is subjected.
It is yet another object of the present invention to provide an improved angle measurement device that incorporates a partial barrier inside a fluid vessel to dampen the fluid movement as the sensor is rotated, thereby reducing the sensor's sensitivity to motion transients.
These and other objects are accomplished in accordance with the illustrated preferred embodiment of the present invention by providing a printed circuit board having electronic components mounted on the front surface thereof and having a pair of sensor plates etched into the back surface thereof. Containment of the sensor fluid adjacent the sensor plates and a partial web is accomplished by soldering a sensor cover to an etched sealing ring on the back of the circuit board. The sensor plates etched into the back of the printed circuit board, in combination with the sensor fluid, act as variable resistors whose resistance changes as a function of their angle of rotation from a reference position. An output signal across these variable resistors is in or out of phase with an applied reference signal. The output signal is demodulated with the same reference signal and then filtered to a DC level that corresponds to the angle of rotation. An output stage serves as a driver and electronic lead circuit and also as a means for permitting the user to remotely control the application of the electronic lead circuit in the angle measurement device. | {
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From our French patent application No. 7803475, U.S. patent application Ser. No. 3,414 filed Jan. 15, 1979, now U.S. Pat. No. 4,288,263 it is known that the reservoir front and rear walls are made from plates and that the side walls consist of lateral moving bands which move with the conveyor and which bear against the side edges of the front and rear plates. The reservoir is fed through nozzles which pass through the front plate, discharging into the reservoir and produce nearly horizontal mixing streams, oriented in the opposite direction from the direction of advance of the conveyor. The front plate is slightly raised so as to form a pouring slot between its lower edge and the conveyor. In order to prevent massive setting within the product contained in the reservoir and on the walls of said reservoir, the mixture is introduced through the feed nozzles at a given rate, fast enough to provide stirring inside the reservoir, and the front and rear plates are caused to vibrate with the help of vibrators mounted on these plates. When reinforcements are placed inside the product manufactured, under certain circumstances these reinforcements are introduced in such a way that they rub against one and/or the other of the front and rear plates of the reservoir, or at least against their lower edges. To the extent that the height of the feed nozzles, the flow rate of the mixture, and the spacing between the front and rear plates of the reservoir, are set to correspond to the description in the aforementioned patent application U.S. Ser. No. 3,414, submerged streams cause stir lines which are visible on the surface, and these stir lines follow at least a trajectory from the front plate to the rear plate, and a return flow to the front plate, forming interlocking loops covering the whole surface of the reservoir, to the extent, that the front and rear plates are vibrated, deposits do not form which may entail massive setting, and the pouring device (henceforth called the pouring head) functions without assistance. However, if the pouring head is not adjusted precisely, splashing takes place and deposits may form, especially upon the rear plate, near the surface above the mixture, especially between the stir loops and in the corners of the reservoir. These deposits require occasional cleaning without nevertheless requiring the pouring to be stopped, the more frequently the worse the adjustment, for example, every two to three hours.
The pouring heads, even with the inconvenience of careful adjustment of the inconvenience of periodical cleaning of the rear plate, function satisfactorily up to a width of about sixty centimeters. But as the dimensions increase, the main problem becomes how to maintain the plates vibrating, especially the rear plate upon which the deposits principally form. | {
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Defibrillators are implanted in patients susceptible to cardiac arrhythmias or fibrillation. Such devices provide cardioversion or defibrillation by delivering a high voltage shock to the patient's heart, typically about 500-750V. High voltage capacitors are used in defibrillators to accumulate the high voltage charge following detection of a tachyarrhythmia. In the effort to make implantable devices as small and thin as possible, flat aluminum electrolytic capacitors are used.
Such a flat capacitor is disclosed in U.S. Pat. No. 5,131,388 to Pless et al., which is incorporated herein by reference. Flat capacitors include a plurality of aluminum layers laminarly arranged in a stack. Each layer includes an anode and a cathode, with all of the anode layers and all of the cathode layers being commonly connected to respective connectors. The layers may be cut in nearly any shape, to fit within a similarly shaped aluminum housing designed for a particular application. Normally, the cathode layers are together connected to the housing, while the anodes are together connected to a feed-through post that tightly passes through a hole in the housing, but which is electrically insulated from the housing. The feed-through post serves as an external connector for interfacing with other components.
Flat capacitors may be provided with polymeric housings that eliminate the need for additional insulating layers to insulate conductive layers from the housing, reducing total size and increasing energy density (measured in Joules/cc). Such a housing is disclosed in U.S. patent application Ser. No. 09/130,812, filed Aug. 7, 1998, by inventor D. Carson, which is incorporated herein by reference. This device uses an injection molded two-part plastic "dish-and lid" housing that is ultrasonically welded about its periphery. Electrical feedthrough wires pass from the interior to the exterior through holes provided at the weld line. While effective, this housing requires sidewalls that are wide enough to include mating grooves and ridges for ultrasonic welding. In addition, injection molding requires more than a minimum wall thickness for the major panels to allow molten plastic material to flow through the mold. These thicknesses add to the total capacitor volume, decreasing the energy density from what would otherwise be ideal. In addition, the ultrasonic welding process may be sensitive to out-of-tolerance part dimensions, and requires significant operator care and skill, adding to manufacturing costs. | {
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The invention relates to a device for packaging comprising a forwardly transported foil web, two sealing jaws for welding of the foil web, whereby the shaped foil web is clamped between the sealing jaws and is welded in this manner, and the first sealing jaw can be moved toward the foil web, with the foil web and away from said foil web, and comprising a cutting device for cutting the welded foil web.
It is known in tubular bagging machines that two sealing jaws are moved toward one another in order to weld a tubular or lengthwise folded foil web transversely with respect to its transport direction. Such welded areas of the foil web can be filled and can be welded lengthwise with respect to the transport direction by means of a further welding device, or it is possible to create bag areas open on one side. The areas are cut off from the foil by means of the cutting device so that bags are created. These bags can be filled and welded bags, or empty bags open on one side.
Two sealing jaws of a vertical tubular bagging machine are known from EP 0 469 105, which sealing jaws rotate in opposite direction each about axes, and which each describe a D-shaped path, and which along the straight section of the path in a co-moving manner weld a continuously forwardly moved foil web transversely with respect to its transport direction in order to create in this manner a head seam of a bag and a bottom seam of a following bag in the longitudinally welded foil web. The foil web is cut between these seams.
Furthermore a horizontal tubular bagging machine is known, in which a foil web is folded lengthwise and along its centerline. The foil web is moved forwardly in cycles. Two vertically aligned sealing jaws are moved toward one another during each foil standstill in order to create during one welding operation a side seam of a bag and one side seam of a following bag. The foil web is cut between these side seams in order to separate a created bag from the foil web.
The known devices for packaging have the disadvantage that the mechanics for pressing the sealing jaws against one another is relatively complicated since both sealing jaws are moved away from the foil web and thereafter again toward said foil web. This mechanics is even more complicated when the sealing jaws are over stretches co-moved with the moved foil web in order to weld the foil web during the foil transport.
The basic purpose of the invention is to reduce in the above-described device the technical requirements for effecting a welding of a moving foil web.
The purpose is attained by supporting the second sealing jaw for a co-movement with the first sealing jaw, the path of co-movement extending coextensively with the foil web, and the second sealing jaw can be moved back against the transport direction of the foil web.
The device of the invention has the advantage that the technical requirement for welding a moving foil web is reduced since merely the first sealing jaw must be moved by means of a jaw drive and by a relatively uncomplicated set of mechanics initially along a sealing stretch with the foil web and must thereafter be removed from the foil web and returned into its initial position. The second sealing jaw is merely co-moved along the sealing stretch on a path synchronously with the first sealing jaw and hereby fulfills its purpose to apply together with the first sealing jaw a sealing pressure onto the foil and to bring heat into two foil areas which lie one on top of the other in order to weld these together. While the first sealing jaw is, at the end of the sealing stretch, removed from the foil web perpendicularly with respect to the transport direction and is thereafter again moved back toward the foil web into its original position in order to act there again against the foil web, the second sealing jaw is moved back by means of a simple set of mechanics against the transport direction of the foil web. Thus, while the first sealing jaw rotates in a plane, the second sealing jaw performs, for example, only a back and forth movement, whereby the latter is moved parallel with respect to the first sealing jaw during the sealing operation.
When the path extends parallel with respect to the transport direction, then the tension in the foil web is constant during the sealing operation. In addition a straight web can be realized in a simple manner. The second sealing jaw can extend on the centerline of the foil web. A welding of the foil takes place only when together with the first sealing jaw a sealing pressure is applied to the foil. However, in order not to influence the foil transport too much during the moving back of the second sealing jaw, a spacing is provided between the sealing surface of the second sealing jaw and the centerline, which spacing is preferably 1 to 4 mm. A good sealing result with a secure foil path is achieved with this spacing. A path can be defined by a rail, along which a carriage is moved, on which the second sealing jaw is fastened. The rail can be straight and can extend parallel to the centerline, however, it could also be curved or circular. In the case of a circular path, the second sealing jaw carries out a circular movement.
The second sealing jaw does not need a separate drive but is co-moved with the movement of the first sealing jaw when a carrier connection is provided between the sealing jaws, which connection takes along the second sealing jaw in correspondence with the movement of the first sealing jaw, which movement occurs in transport direction and opposite thereto. In principle only one carrier would be sufficient. The second sealing jaw could then be moved back into its initial position by means of spring force.
When the transport direction extends horizontally, then it is possible for the foil web to be folded along its centerline and to be sealed in this manner transversely with respect to the transport direction. It is hereby possible to place the second sealing jaw relatively close to the centerline without interfering with the foil pathway.
Relatively high packaging speeds can be achieved when the first sealing jaw rotates about an axis. Whereas if a circular path is not chosen for the first sealing jaw, but a D-shaped one, then a relatively long path with closed sealing jaws is available along the straight D-section in order to carry out a foil welding. A D-shaped circular path is achieved, for example, when the first sealing jaw rotates about two axes of rotation, which are arranged parallel to one another, by means of a four-bar mechanism, whereby the sealing surface is held parallel with respect to the transport direction during the sealing operation by said mechanism. The straight section of the D-shaped circular path is achieved by a cushioning of the first sealing jaw perpendicular with respect to the transport direction.
A relatively high packaging speed is in addition achieved by the first sealing jaw rotating continuously. A servomotor is used for this purpose and also for the purpose that the rotational speed of this sealing jaw must not be constant. The packaging speed is further increased when the first sealing jaw is moved back faster than the sealing jaws are moved during the welding operation. | {
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Prior to this invention, when continuous lengths of filament from an extrusion operation or from another source have been cut, substantial difficulties have been encountered in handling and removing the cut filament. The incoming uncut filament travels at relatively high rates of linear speed. When cut, the filament tends to be scattered in random directions because the impact from cutting tends to throw one end of the filament ahead of the other. At the same time the cut filament tends to interfere with incoming filament.
It is, therefore, an object of this invention to provide a method of and apparatus for cutting and handling filament which overcome the described problems.
Among the other objects of this invention are to provide a method and apparatus which limit and control the erratic movement of cut filament and which remove such filament from the path of filament to be cut.
Additional objects and advantages will be set forth in part hereinafter and in part will be obvious herefrom or may be learned with the practice of the invention, the same being realized and obtained by means of the apparatus recited in the appended claims. | {
"pile_set_name": "USPTO Backgrounds"
} |
The present invention relates to a fuel cap that can be inserted into an open end of a fuel tank filler neck, and particularly, to a fuel cap that can be locked after insertion into the filler neck to prevent removal of the fuel cap from the filler neck. More particularly, the present invention relates to a lockable fuel cap having a key-operated lock cylinder that unlocks the fuel cap relative to the filler neck when a key is inserted into the lock cylinder and turned.
Fuel caps that couple to open ends of vehicle filler necks to close the open end of the filler neck are known. See for example U.S. Pat. Nos. 4,280,347 to Evans and 5,520,300 to Griffin. Some fuel caps have key-operated locking mechanisms that are operable to lock the fuel cap in the filler neck. During refueling of vehicles having key-operated locking mechanisms, a key is used to unlock the fuel cap allowing the fuel cap to be removed from the filler neck.
According to the present invention, a lockable fuel cap is provided for mounting in an open end of a vehicle filler neck. The fuel cap includes a closure member adapted to mate with the open end of the vehicle filler neck. The closure member is formed to include an interior region and a drive tooth positioned to lie in the interior region. The lockable fuel cap also includes a removal hub positioned to lie within the interior region of the closure member. The removal hub is formed to include a drive lug and is movable between a locking position in which the drive lug is spaced apart from the drive tooth of the closure member and a releasing position in which the drive lug engages the drive tooth. The lockable fuel cap further includes an outer shell having an interior wall. The interior wall of the outer shell defines a guide slot for receiving the drive lug of the removal hub in order to guide the movement of the removal hub between the locking and releasing positions. The outer shell is also rotatable relative to the closure member while being drivingly coupled to the removal hub so that the closure member remains stationary upon rotation of the outer shell in a cap-removal direction when the drive lug of the removal hub is in the locking position. Alternately, the closure member rotates in the cap-removal direction upon rotation of the outer shell in the cap-removal direction when the drive lug is in the releasing position.
In preferred embodiments, the removal hub includes an arcuate front wall and an arcuate rear wall. The arcuate front and rear walls are spaced apart such that an inner region is defined therebetween. The guide slot of the removal hub is formed in the front wall. The fuel cap of the present invention further comprises a lock cylinder rotatable relative to the outer shell. The lock cylinder includes a throw member being positioned to lie within the inner region of the removal hub. The removal hub additionally includes a drive post such that during rotation of the lock cylinder to move the removal hub from the locking position to the releasing position, the throw member engages the drive post.
Further, the lockable fuel cap includes an installation hub drivingly coupled to the outer shell to transmit rotation of the outer shell in a cap-installation direction to the closure member. The installation hub includes a ring and a driven portion extending upwardly from the ring and into a cavity formed within the outer shell. The installation hub further includes flexible fingers appended to the ring and coupled to a torque-override ring that has radial drive teeth. The torque override ring is coupled to the closure member so that continued rotation of the outer shell in a cap installation direction after the closure member is adequately sealed within the filler neck, results in continued rotation of the installation hub and the torque-override ring without continued rotation of the closure member.
Additional features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following detailed description of preferred embodiments exemplifying the best mode of carrying out the invention as presently perceived. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field
Example embodiments of the following description relate to a method and apparatus for processing a virtual world, and more particularly, to a method and apparatus for applying information of a real world to a virtual world.
2. Description of the Related Art
Currently, an interest in experience-type games has been increasing. MICROSOFT CORPORATION introduced “Project Natal” at the “E3 2009” Press Conference. “Project Natal” may provide a user body motion capturing function, a face recognition function, and a voice recognition function by combining MICROSOFT's XBOX 360 game console with a separate sensor device consisting of a depth/color camera and a microphone array, thereby enabling a user to interact with a virtual world without a dedicated controller. In addition, SONY CORPORATION introduced “Wand” which is an experience-type game motion controller. The “Wand” enables interaction with a virtual world through input of a motion trajectory of a controller by applying, to the PLAYSTATION 3 game console, a location/direction sensing technology obtained by combining a color camera, a marker, and an ultrasonic sensor.
The interaction between a real world and a virtual world has two directions. In one direction, data information obtained by a sensor of the real world may be reflected to the virtual world. In the other direction, data information, obtained from the virtual world may be reflected to the real world using an actuator. Embodiments suggest a virtual world processing apparatus and method to apply information obtained through the sensor of the real world to the virtual world in order to achieve the interaction between the real world and the virtual world. | {
"pile_set_name": "USPTO Backgrounds"
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Electronic devices having touch screens are increasingly favored by consumers, for example, devices such as a smartphone, a tablet computer, and a personal digital assistant (PDA). Usually a user performs slide and touch operations on a touch screen to perform zooming processing on a browsed page. For multi-touch of a smartphone, a relative sliding distance of two fingers on a touch screen is sensed in order to control zooming out or zooming in of a page.
In some other approaches, although various page display control technologies are available, two fingers always need to be used to operate a touch screen to realize zooming of a page. Usually, one hand holds an electronic device, and the other hand performs zooming control. It is difficult to hold an electronic device and at the same time perform a zooming operation using a single hand. | {
"pile_set_name": "USPTO Backgrounds"
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Advances in semiconductor manufacturing technology have resulted in ever decreasing physical dimensions for the various circuit elements, such as, for example, field effect transistors, which are used in forming integrated circuits. In turn, the smaller dimensions of such circuit elements have allowed the integration onto a single chip of many more transistors than was possible in the past.
As is well-known in the field of integrated circuits, reducing the dimensions of circuit elements generally, and of the field effect transistor (FET) in particular, requires a corresponding reduction in the power supply voltage in order to avoid electric field strengths within the integrated circuit which might result in dielectric breakdown, or other adverse effects. Additionally, transistors of such small dimensions tend to have significant leakage current, or subthreshold conduction, Therefore to maintain the power consumption of integrated circuits having a large number of small, i.e., “leaky” transistors at a reasonable level, it has become common to reduce the power supply voltage.
Even in circumstances where leakage and dielectric breakdown are not issues, those skilled in the art of integrated circuit design recognize that lowering the supply voltage to a circuit is a significant factor in reducing power consumption.
In response to various motivations, such as those mentioned above, there has been an on-going trend to reduce power supply voltages. One consequence of this trend is that many systems or applications have various circuits with different voltage supply requirements. For example, a system may have some components that operate at 5 volts, and others that operate at 3.3 volts. Similarly, a single integrated circuit may have portions therein which operate at different voltages, for example, 3.3 volts and 1.8 volts. It will be appreciated that a signal that is generated in one voltage supply domain, may need to be level-shifted in order to properly interact with circuits that operate in a different power supply domain.
Various level-shifting circuits have been developed in order to provide the level-shifting functionality mentioned above. Unfortunately, one drawback of conventional level-shifters of the H-bridge configuration with capacitively coupled input signals, is that the performance of such level-shifters is dependent upon the duty cycle of the input signals.
What is needed are methods and apparatus for providing level shifters with capacitively coupled inputs that have performance characteristics which are substantially independent of the duty cycle of the input signals. | {
"pile_set_name": "USPTO Backgrounds"
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(1) Field of the Invention
The present invention relates to X-ray imaging apparatuses and methods, or more particularly, to an apparatus and method for non-destructively examining the inside of an entity.
(2) Description of the Related Art
Imaging apparatuses to be used to non-destructively observe the inside of a sample using X-rays include an absorption contract X-ray imaging apparatus that utilizes a change in the intensity of X-rays caused by the sample and a phase contrast X-ray imaging apparatus that utilizes a change in the phase (phase shift) of X-rays.
The former absorption contrast X-ray imaging apparatus is composed mainly of an X-ray source, a sample positioning mechanism, and a detector. X-rays emitted from the X-ray source are irradiated to a sample positioned by the sample positioning mechanism, and X-rays transmitted the sample are detected by the detector. The absorption contrast X-ray imaging apparatus produces an image in which a change in the intensity of X-rays caused by absorption of the sample is shown as an image contrast. Since the principles of measurement and the configuration of the apparatus are relatively simple, the absorption contrast X-ray imaging apparatus is widely used in many fields including a field of medical diagnosis by the name of an X-ray system in which projection data is acquired for two-dimensional observation and by the name of an X-ray CT system in which computed tomography (CT) is performed for three-dimensional observation.
On the other hand, the latter phase contrast X-ray imaging apparatus requires, in addition to the above components, a means for detecting a phase shift. Compared with the absorption contrast X-ray imaging apparatus, the phase contrast X-ray imaging apparatus offers very high sensitivity. Therefore, the phase contrast X-ray imaging enables observations of biological soft tissues without usage of contrast agents and without harmful X-ray exposure. This is because phase shift cross section of a light element is approximately one thousand times larger than absorption cross section
Means for detecting a phase shift include, as described in Physics Today (vol. 53, 2000, 23), (1) a method that is disclosed to employ an X-ray interferometer in Japanese Patent Application Laid-Open Nos. 4-348262 and 10-248833, (2) a method that is described to detect an angle of refraction of X-rays using an analyzer crystal in the brochure for the PCT International Publication WO95/05725 and Japanese Patent Application Laid-Open No. 9-187455, and (3) a method utilizing Fresnel diffraction. Among the methods, the method (1) directly detects a phase shift and therefore offers the highest sensitivity. The method (1) having relation to the present invention will be described below.
Japanese Patent Application Laid-Open No. 4-348262 describes a configuration including an X-ray source, a sample positioning mechanism, a detector, and an X-ray interferometer such as a Bonse-Hart interferometer (described in Appl. Phys. Lett. (vol. 6, pp. 155, 1965)) or an interferometer having the Bonse-Hart interferometer divided into multiple crystal blocks (described in J. Appl. Cryst. (vol. 7, pp. 593, 1974)).
FIG. 1 is a perspective view schematically showing the configuration of a Bonse-Hart interferometer. The Bonse-Hart interferometer is formed as one crystal block cut out from a single-crystal ingot monolithically, and that has three wafers equidistantly juxtaposed in parallel with one another (serving as a beam splitter 1, a mirror 2, and an analyzer 3). Incident X-rays 4 are split into two beams of a beam 5 and a beam 6 by the first wafer (beam splitter 1), reflected from the second wafer (mirror 2), and recombined by the third wafer (analyzer 3). Consequently, two interference beams 7 and 8 are formed. If a sample 9 is positioned in the path of the beam 5 or 6, a change in the phase of the beam caused by the sample changes in the intensities of the interference beams 7 and 8 due to superposition (interference) of the waves. By taking advantage of the principle, an image showing a change in a phase (a phase contrast image) can be obtained by the changes in the intensities of the interference beams 7 and 8 are detected by an image detector or the like.
Imaging apparatuses in which the phase contrast imaging method and an ordinary X-ray CT technique are combined in order to enable three-dimensional non-destructive observation, include an imaging apparatus described in Japanese Patent Application Laid-Open No. 4-348262. Similarly to ordinary X-ray CT, X-rays are irradiated to a sample in multiple directions, and a phase contrast tomographic image of the sample is reproduced by computing using respective projection data sets.
Light elements, such as oxygen or carbon, are nearly transparent to X-rays, and almost incident X-rays are not absorbed by the light element. Therefore, a change in an intensity derived from absorption by a subject is very small, and observation with high sensitivity of biological soft tissues or organic materials are difficult by using absorption contrast X-ray imaging method. In efforts to compensate insufficient sensitivity, a contrast agents is used or an exposure time is extended. However, this induces a problem in that a region capable of being imaged is limited or an exposure increases.
On the other hand, the sensitivity of phase contrast X-ray image is sufficiently high, but complex computation called phase unwrapping is needed to obtain phase contrast images. As shown in FIG. 2, a change α in a phase caused by a sample is detected as a value α′ rounded off (wrapped) to fall within 0 to 2π (α′=α−Int(α/2π)×2π). Therefore, it is required a process for restoring the true change a in a phase (phase unwrapping) using a calculation method described in, for example, Japanese Patent Application Laid-Open No. 2001-153797. Furthermore, X-rays are refracted in a region of a sample in which the density is spatially abruptly varied caused by the complex shape or the internal structure of the sample. The X-rays are deviated from their original optical path, and superposed on a beam other than a reference beam as described later with reference to FIG. 4B and FIG. 4C. Since the coherence length of X-rays is so short as to range from several micrometers to several tens of micrometers, this deviation induces a decrease in sharpness (visibility) of an interference pattern or disappearance of interference fringes. And the unwrapping cannot be performed normally, and the change α cannot be accurately restored.
In efforts to avoid the foregoing problem, an example like the one described in Japanese Patent Application Laid-Open No. 7-209212 may be immersed in a liquid in order to decrease the difference in density between the sample and its surroundings. In this case, the influence of a shape can be minimized but an rapid change in density inside the sample cannot be coped with. Moreover, an object to be measured is limited to a specific one.
FIG. 3 is an explanatory diagram of observable regions of the conventional absorption, phase contrast X-ray imaging methods, and the present invention. According to the conventional absorption and phase contrast X-ray imaging methods, a region of a density change in a sample to which each of the X-ray imaging methods is sensitive is limited to an extreme region of large or small values. This indicates that the X-ray imaging methods cannot enable observation at a high density resolution of a sample in which a region exhibiting a large density change, for example, bones and lungs, and a region exhibiting a small density change, such as, biological soft tissues are mixed. | {
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Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Smaller feature sizes have resulted in the presence of increased aspect ratio gaps for some applications, for example, between adjacent conductive lines or in etched trenches. The aspect ratio of a gap is defined by the ratio of the gap's height or depth to its width. These spaces are difficult to fill using conventional methods. A film's ability to completely fill such gaps is referred to as the film's “gap-filling” ability. Silicon oxide is one type of insulation film that is commonly used to fill the gaps in intermetal dielectric (IMD) applications, premetal dielectric (PMD) applications and shallow trench isolation (STI) applications among others. Such a silicon oxide film is often referred to as a gap-fill film or a gap-fill layer.
Some integrated circuit manufacturers have turned to the use of high density plasma CVD (HDP-CVD) systems to deposit silicon oxide gap-fill layers. HDP-CVD systems form a plasma that is approximately two orders of magnitude or greater than the density of a standard, capacitively-coupled plasma CVD system. Examples of HDP-CVD systems include inductively-coupled plasma systems and electron cyclotron resonance (ECR) plasma systems among others. HDP-CVD systems generally operate at lower pressure ranges than low density plasma systems. The low chamber pressure employed in HDP-CVD systems provides active species having a long mean-free-path and reduced angular distribution. These factors, in combination with the plasma's density, contribute to a significant number of constituents from the plasma reaching even the deepest portions of closely spaced gaps, providing a film with improved gap-fill capabilities as compared to films deposited in a low density plasma CVD system.
Another factor that allows films deposited by HDP-CVD techniques to have improved gap-fill characteristics as compared to films deposited by other CVD techniques is the occurrence of sputtering, promoted by the plasma's high density, simultaneous with film deposition. The sputtering element of HDP deposition slows deposition on certain features, such as the corners of raised surfaces, thereby contributing to the increased gap-fill ability of HDP deposited films. Some HDP-CVD systems introduce argon or a similar heavy gas to further promote the sputtering effect. These HDP-CVD systems typically employ an electrode within the substrate support pedestal that enables the creation of an electric field to bias the plasma toward the substrate. The electric field can be applied throughout the HDP deposition process to generate sputtering and provide better gap-fill characteristics for a given film.
One HDP-CVD process commonly used to deposit a silicon oxide film forms a plasma from a process gas that includes silane (SiH4), molecular oxygen (O2) and argon (Ar). This silicon oxide film has improved gap-fill characteristics as opposed to some silicon oxide films deposited by other non-HDP-CVD plasma techniques and is useful for a variety of applications. Despite the improvement in gap-fill capability provided by HDP-CVD systems and the relatively good gap-fill characteristics of HDP-CVD silicon oxide films in particular, the development of film deposition techniques that enable the deposition of silicon oxide layers having even further improved gap-fill characteristics are desirable. Such improved silicon oxide film depositions are particularly desirable in light of the aggressive gap-fill challenges presented by integrated circuit designs employing minimum feature sizes of 0.18 microns and less.
One known way to improve the gap-fill capability of silicon oxide films is to add a fluorine-containing source gas to the process gas. Fluorine atoms are known to etch silicon oxide and it is known that the inclusion of fluorine into a silicon oxide deposition process results in etching simultaneous with deposition which in turn can improve the deposited film's gap-fill capability. The incorporation of fluorine into a silicon oxide film also has a primary benefit of reducing the dielectric constant of the deposited film. A silicon oxide film (also referred to as a silicate glass layer) that includes fluorine is often referred to in the industry as a fluorine-doped silicon oxide film or as a fluorosilicate glass (FSG) layer.
Because of stability and other issues, FSG films are generally not used for PMD or STI applications and have been primarily limited to intermetal dielectric (IMD) applications.
Semiconductor manufacturers are often particularly hesitant to include fluorine in PMD and STI layers because such layers are likely to be subject to relatively high temperatures (e.g., above 450° C. and often above 700° C.) either during deposition of the layer or during a process step that is subsequent to deposition of the layer. At such high temperatures, fluorine is more likely to outgas from FSG layers and migrate into an adjacent layer. Thus, many semiconductor manufacturers prefer that PMD or STI layers have less than 1.0 atomic percent (at. %) fluorine. IMM layers, on the other hand, are typically deposited after the first metal layer and thus never subject temperatures above 450° C.
Typically, undoped silicate glass (USG) or other silicon oxide family members including BPSG (borophosphosilicate glass) and PSG (phosphosilicate glass) are used for PMD layers, and USG is used for STI applications. However, USG exhibits high compressive stress, e.g., greater than 220 MPa. For many applications, a lower compressive stress STI film with adequate gap fill performance is desirable.
In view of the above, additional methods of depositing low compressive stress STI silicon oxide films having sufficient gap-fill capabilities are desirable. | {
"pile_set_name": "USPTO Backgrounds"
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The process by which the mammalian immune system recognizes and reacts to foreign or alien materials is a complex one. An important facet of the system is the T lymphocyte, or "T cell" response. This response requires that T cells recognize and interact with complexes of cell surface molecules, referred to as human leukocyte antigens ("HLA"), or major histocompatibilty complexes ("MHCs"), and peptides, The peptides are derived from larger molecules which are processed by the cells which also present the HLA/MHC molecule. See in this regard Male et al., Advanced Immunology (J. P. Lippincott Company, 1987), especially chapters 6-10. The interaction of T cells and HLA/peptide complexes is restricted, requiring a T cell specific for a particular combination of an HLA molecule and a peptide, If a specific T cell is not present, there is no T cell response even if its partner complex is present. Similarly, there is no response if the specific complex is absent, but the T cell is present. This mechanism is involved in the immune system's response to foreign materials, in autoimmune pathologies, and in responses to cellular abnormalities. Much work has focused on the mechanisms by which proteins are processed into the HLA binding peptides. See, in this regard, Barinaga, Science 257:880 (1992); Fremont et al., Science 257:919 (1992); Matsumura et al,m Science 257:927 (1992); Latron et al., Science 257:964 (1992).
The mechanism by which T cells recognize cellular abnormalities has also been implicated in cancer, For example, in PCT application PCT/US92/04354, filed May 22, 1992, published on Nov. 26, 1992, and incorporated by reference, a family of genes is disclosed, which are processed into peptides which, in turn, are expressed on cell surfaces, which can lead to lysis of the tumor cells by specific CTLs cytolytic T lymphocytes, or "CTLs" hereafter. The genes are said to code for "tumor rejection antigen precursors" or "TRAP" molecules, and the peptides derived therefrom are referred to as "tumor rejection antigens" or "TRAs". See Traversari et al., Immunogenetics 35:145 (1992); van der Bruggen et al., Science 254:1643 (1991), for further information on this family of genes. Also, see U.S. patent application Ser. No. 807,043, filed Dec. 12, 1991, now U.S. Pat. No. 5,342,774, incorporated by reference in its entirety. The "MAGE" family of tumor rejection antigen precursors is disclosed in this patent.
In U.S. patent application Ser. No. 938,334, now U.S. Pat. No. 5,405,940 Apr. 15, 1995, the disclosure of which is incorporated by reference, it is explained that the MAGE-1 gene codes for a tumor rejection antigen precursor which is processed to nonapeptides which are presented by the HLA-A1 molecule. The nonapeptides which bind to HLA-A1 follow a "rule" for binding in that a motif is satisfied. In this regard, see e.g. PCT/US93/07421; Falk et al., Nature 351: 290-296 (1991); Engelhard, Ann Rev. Immunol. 12: 181-207 (1994); Ruppert et al., Cell 74: 929-937 (1993); Rotzchke et al, Nature 348: 252-254 (1990); Bjorkman et al., Nature 329: 512-518 (1987); Traversari et al., J. Exp. Med. 176: 1453-1457 (1992). The references teach that given the known specificity of particular peptides for particular HLA molecules, one should expect a particular peptide to bind to one HLA molecule, but not to others. This is important, because different individuals possess different HLA phenotypes. As a result, while identification of a particular peptide as being a partner for a specific HLA molecule has diagnostic and therapeutic ramifications, these are only relevant for individuals with that particular HLA phenotype. There is a need for further work in the area, because cellular abnormalities are not restricted to one particular HLA phenotype, and targeted therapy requires some knowledge fo the phenotype of the abnormal cells at issue.
In U.S. Pat. application Ser. No. 008,446, filed Jan. 22, 1993 now U.S. Pat. No. 5,885,165, and incorporated by reference, the fact that the MAGE-1 expression product is processed to a second TRA is disclosed. This second TRA is present by HLA-Cw*1601 molecules. The disclosure shows that a given TRAP can yield a plurality of TRAs, each of which will satisfy a motif rule for binding to an MHC molecule.
In U.S. Pat. application Ser. No. 994,928, filed Dec. 22, 1992, now abandoned, and incorporated by reference herein teaches that tyrosinase, a molecule which is produced by some normal cells (e.g., melanocytes), is processed in tumor cells to yield peptides presented by HLA-A2 molecules.
In U.S. patent applciation Ser. No. 08/032,978, filed Mar. 18, 1993, now U.S. Pat. No. 5,620,886, and incorporated by reference in its entirety, a second TRA, not derived from tyrosinase is taught to be presented by HLA-A2 molecules. The TRA is derived from a TRAP, but is coded for by a non-MAGE gene. This disclosure shows that a particular HLA molecule may present TRAs derived from different sources.
In U.S. patent application Ser. No. 08/079,110, now U.S. Pat. No. 5,571,711, filed Jun. 17, 1993 and incorporated by reference herein, an unrelated tumor rejection antigen precursor, the so-called "BAGE" precursor is described. The BAGE precursor is not related to the MAGE family.
In U.S. patent applications Ser. No. 08/096,039, now abandoned, and Ser. No. 08/250,162, now U.S. Pat. No. 5,610,013, both of which are incorporated by reference, non-related TRAP precursor GAGE is also disclosed.
The work which is presented by the papers, patent, and patent applications cited supra deal, in large part, with the MAGE family of genes, and the unrelated BAGE, GAGE and DAGE genes, showing that there are different, additional tumor rejection antigen precursors expressed by cells.
It has now been found that there is yet another family of tumor rejection antigen precursor genes. These nucleic acid molecules show homology to the MAGE family of genes, but this homology is insufficient to identify the members of the MAGE-B family by hybridization with the members of the MAGE-A family, as set forth in, e.g., PCT Application PCT/US92/04354 and U.S. Pat. No. 5,342,774, under the conditions of stringency set forth therein. Further, the isolated nucleic acid molecules of the invention were all found on the Xp arm of the X chromosome, as contrasted to the previously identified members of the MAGE-A family, all of which were found on the Xq are, Thus, the invention relates to isolated nucleic acid molecules which encode for MAGE-B tumor rejection antigen precursors and the uses thereof.
The invention is explained in further detail in the disclosure which follows. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention is directed to a method and system for coordinating multiple software components to communicate and share a portion of a computer monitor or display.
2. Discussion of the Background
Numerous program display control systems have been used to coordinate the display of some number of programs on a single (virtual or real) display/monitor. In the X Windows environment, such a control system is called a windows manager. Examples of known windows managers include: FVWM, FVWM95, TWM/VTWM, MWM, CTWM, OLWM/OLVWM, wm2/wmx, AfterStep, AmiWM, Enlightenment, WindowMaker, SCWM, IceWM, Sawfish, and Blackbox. Using configuration files for the applications run under the X Windows window managers, certain windowing parameters (e.g., windows locations and colors) can be set at application start-up time.
In X Windows, libraries of various re-usable components have been built to standardize the look and feel of various components within a graphical user interface. Such libraries include OpenLook and Motif and implement “widgets” having a variety of functions (e.g., buttons and menus).
A consortium of participants in the health care industry have combined to form the Clinical Context Object Workgroup (CCOW), which, according to its 1998 White Paper, “publishes standards for the visual integration of cooperative interaction among independently authored healthcare applications at the point of use.” As further stated therein “Version 1 of the standard [ratified in April 1999], the Patient Link, supports synchronizing the applications for a selected patient. When the user of an application changes the selected patient, the other applications on the workstation follow the change. The cooperation frees the user from the tedium of repeating the action in more than one application.” Subsequently versions 1.1 and 1.2 were ratified in January and May, 2000, respectively. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field
Exemplary embodiments of the inventive concept are directed to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, exemplary embodiments of the inventive concept are directed to a semiconductor device including a through-electrode for an electrical connection and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As device speeds and device integration increase, signal delays may also increase, for example, due to parasitic capacitance introduced by interconnection structures. Advances in integration technology have led to the development of three-dimensional integration, where wafers may be stacked three-dimensionally, in contrast to the conventional two-dimensional approach.
In a three-dimensional wafer stack package (WSP), a structure called a through-silicon via (TSV) can be used to extend the via hole through a substrate so that a conductive via may be formed to vertically extend and completely penetrate through the substrate. Such a TSV structure may provide higher speeds, higher integration, and improved functionality in comparison to a long wire pattern interconnection. For example, the conductive via may be formed using copper (Cu) having a low resistance. However, copper is known to have high diffusivity in silicon.
A conventional TSV may be formed through the substrate before back end processing. In particular, the TSV structure may be formed by forming an opening or hole in a substrate, such as a silicon substrate. An insulation layer may be formed on the substrate and in the opening. A conductive metal layer, such as a copper (Cu) layer, may be formed in the opening, for example, by a plating process or a deposition process. A backside of the substrate may then be recessed to expose at least a portion of the conductive metal layer, thereby forming a conductive via extending through the substrate. In this case, the substrate including the conductive via may be repeatedly exposed during processes such as an etch process. In particular, when a portion of the conductive metal layer is exposed during an etch process, the metal of the conductive metal layer such as copper may diffuse into the substrate to thereby deteriorate a semiconductor device such as a semiconductor chip. | {
"pile_set_name": "USPTO Backgrounds"
} |
White light emitting LEDs (“white LEDs”) include one or more photoluminescence materials (typically inorganic phosphor materials), which absorb a portion of the blue light emitted by the LED and re-emit light of a different color (wavelength). The portion of the blue light generated by the LED that is not absorbed by the phosphor material combined with the light emitted by the phosphor provides light which appears to the eye as being white in color. Due to their long operating life expectancy (>50,000 hours) and high luminous efficacy (100 lm/W and higher) white LEDs are rapidly being used to replace conventional fluorescent, compact fluorescent and incandescent lamps. LED lamps (bulbs) are typically constructed from a small number of high-intensity white LEDs.
Recently, LED-filament lamps have been developed that comprise LED-filaments that closely resemble the filament of a traditional incandescent lamp. The LED-filaments, which are typically about an inch long, comprise COG (Chip-On-Glass) devices having a plurality of low-power LED chips mounted on a transparent glass substrate. The LED-filaments are encased in a phosphor-impregnated encapsulant, such as silicone. Typically, LED-filament lamps are configured to generate “warm white” light with a CCT (Correlated Color Temperature) of 2700 K to 3000 K with a General Color Rendering Index (CRI Ra) of up to about 80.
While the CRI Ra of packaged white LEDs can be increased by including a longer wavelength red emitting phosphor while experiencing only a small reduction in performance, when a longer wavelength red emitting phosphor is included in a LED-filament to increase CRI Ra from 80 to 90 this results in a substantial reduction in performance, in particular luminous efficacy, of the LED-filament in a range from 15% to 20%. The reduction in efficacy results in greater heat generation within the LED-filament. Since there is no way of readily managing an increase in heat in an LED-filament, this makes it impractical to produce high lumen (>800 lm) CRI Ra 90 LED-filaments with an acceptable luminous efficacy. There is thus a need to provide LED-Filaments and LED-filament lamps that have a CRI Ra of at least about 90 and which have substantially the same performance as a CRI Ra 80 LED-filament. | {
"pile_set_name": "USPTO Backgrounds"
} |
The invention described herein may be manufactured and used by or for the United States Government for Governmental purposes without the payment of any royalties.
The present invention generally relates to magnetic sensors. The present invention also relates generally to the tracking of magnetic objects, and more particularly, to a computer-implemented algorithm that permits tracking of magnetic objects.
Numerous opportunities exist for tracking objects that generate magnetic fields. All types of land vehicles, ships, and aircraft have structural and power systems capable of generating substantial magnetic signatures. Even small inert objects may exhibit sufficient magnetization to be observed from a distance. For example, the ability to determine the location of a metallic object on a person can be crucial. These applications include covert handgun detection to protect buildings and their occupants; pinpointing unexploded ordnance at converted military bases; and locating the position and depth of underground pipes prior to construction activities. The ability to track magnetic objects is also crucially important in other areas, such as medicine. For example, in the field of surgery, there exists a continuing need to control the orientation, forces, and/or motion of internally implanted devices. Clearly, both operation time and risk to a patient could be reduced if an apparatus and method were available to more accurately and rapidly guide or move a magnetic surgical implant.
A variety of magnetic sensor data processing algorithms, methods, systems and devices thereof capable of localizing, quantifying, and classifying objects based on their magnetic fields and magnetic signatures have been developed. To date, the prior art has been primarily concerned with detecting, locating, and classifying magnetic objects based on a large set of measurements distributed over space and/or time. Some techniques involve using measurements of an object""s magnetic dipole moment. Metal objects such as firearms, automobiles, ships, submarines, and airplanes, for example, have magnetic dipole moments that can be utilized in their detection.
These techniques are based on dipole detection and localization algorithms, which assume that the field of a magnetic source object is well represented as the field of a magnetic dipole moment at distances far removed from the source. The location of the dipole is determined by maximizing an objective function over a grid of search points that spans the search volume. Two known limitations of this method are the assumption of a linear array of sensors and the need to search over all possible dipole orientations if the orientation is unknown.
Several other magnetic object tracking methods, systems and algorithms and devices thereof are also known in the art. For example, some magnetic object tracking techniques are based on electromagnetic anomaly detection technology, which senses an electromagnetic anomaly and pinpoints it at close to real time. Such a technique can measure how close a target is located to a sensor head, while locating the target or magnetic object in three dimensions and thereafter evaluating its orientation.
One of the problems associated with such prior art techniques for tracking magnetic objects is that they are generally based on the utilization of three components of a detected magnetic field. If measurements of the vector magnetic field are made, great care must be taken to minimize rotational vibrations. Because the earth""s magnetic field is so large (i.e., on an order 50,000 nT), it is difficult to differentiate rotational vibrations from signals from an object.
Programs and algorithms based on such techniques require the inversion of a matrix and additionally require a great deal of processing time. Such programs and algorithms also usually require obtaining measurements from several sensors simultaneously. In order to perform several measurements on nearby weak sources and to avoid rotational vibrations, the sensors should be placed close to one another on a rigid frame. If the sensors are configured in this manner, the difference between the signals from strong distant sources is generally small. Additionally, obtaining accurate measurements of these small differences requires expensive sensors and the use of gradiometer algorithms. Such techniques are time consuming and also inefficient.
The present inventor has concluded that a need exists for improved methods and systems for tracking magnetic objects, which not only provider greater efficiency than prior art magnetic tracking techniques but can also process much more quickly and also in near real time on a fairly simple computer. Further, such sensing techniques should be able to utilize less accurate and lower cost sensors.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is, therefore, one aspect of the present invention to provide methods and systems for detecting magnetic objects.
It is another aspect of the present invention to provide methods and systems for tracking magnetic objects.
It is yet another aspect of the present invention to provide improved methods and systems for detecting and tracking magnetic objects based on data collected from one or more magnetic sensors.
It is still another aspect of the present invention to provide methods and systems for tracking magnetic objects based on the total magnetic field measured at a position of closest approach to a magnetic sensor.
The above and other aspects can be achieved as will now be summarized. Methods and systems for tracking a magnetic object are disclosed herein. A plurality of line segments can be compiled based on data received from a plurality of magnetic sensors. The line segment that minimizes an error thereof can then be determined. The path of a magnetic object can then be established based on the compiled line segments and calculated error thereof, thereby permitting the magnetic object to be tracked according to the data received from the magnetic sensors, which can be based on a measurement performed at the point of closest approach of one or more magnetic sensors to the magnetic object. The aforementioned error can be calculated, wherein the variable Er represents such an error. The error Er is generally determined according to following mathematical formula: E r = ∑ i xe2x80x83 xe2x80x83 ( S i S imax - C i C imax ) 2
In this mathematical formulation, the variable Si represents the total magnetic field measured by the ith magnetic sensor among the plurality of magnetic sensors, while the variable Simax represents a maximum of Si. The variable Ci represents the total magnetic field calculated at a position of the ith magnetic sensor based on a set of assumptions regarding the magnetic object, which are described in greater detail herein. Finally, the variable Cimax represents the total magnetic field calculated at a position of a magnetic sensor among a group of magnetic sensors at which the variable Si attains a maximum value.
As indicated herein, the present invention can thus permit a magnetic object to be tracked utlizing the total magnetic field measured at the position of closest approach by the magnetic object to at least one magnetic sensor from among a group of magnetic sensors. These measurements do not have to be performed simultaneously. Generally, the field measured at different sensors will be different in magnitude. Thus, less accurate, lower cost sensors can be utilized in accordance with the invention described herein. | {
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Indoleamine 2,3-dioxygenase (IDO; also known as IDO1) is an IFN-γ target gene that plays a role in immunomodulation. IDO is an oxidoreductase and one of two enzymes that catalyze the first and rate-limiting step in the conversion of tryptophan to N-formyl-kynurenine. It exists as a 41 kD monomer that is found in several cell populations, including immune cells, endothelial cells, and fibroblasts. IDO is relatively well-conserved between species, with mouse and human sharing 63% sequence identity at the amino acid level. Data derived from its crystal structure and site-directed mutagenesis show that both substrate binding and the relationship between the substrate and iron-bound dioxygenase are necessary for activity. A homolog to IDO (IDO2) has been identified that shares 44% amino acid sequence homology with IDO, but its function is largely distinct from that of IDO. (See, e.g., Serafini, P. et al., Semin. Cancer Biol., 16(1):53-65 (February 2006) and Ball, H. J. et al., Gene, 396(1):203-213 (Jul. 1, 2007)).
IDO plays a major role in immune regulation, and its immunosuppressive function manifests in several manners. Importantly, IDO regulates immunity at the T cell level, and a nexus exists between IDO and cytokine production. In addition, tumors frequently manipulate immune function by upregulation of IDO. Thus, modulation of IDO can have a therapeutic impact on a number of diseases, disorders and conditions.
A pathophysiological link exists between IDO and cancer. Disruption of immune homeostasis is intimately involved with tumor growth and progression, and the production of IDO in the tumor microenvironment appears to aid in tumor growth and metastasis. Moreover, increased levels of IDO activity are associated with a variety of different tumors (Brandacher, G. et al., Clin. Cancer Res., 12(4):1144-1151 (Feb. 15, 2006)).
Treatment of cancer commonly entails surgical resection followed by chemotherapy and radiotherapy. The standard treatment regimens show highly variable degrees of long-term success because of the ability of tumor cells to essentially escape by regenerating primary tumor growth and, often more importantly, seeding distant metastasis. Recent advances in the treatment of cancer and cancer-related diseases, disorders and conditions comprise the use of combination therapy incorporating immunotherapy with more traditional chemotherapy and radiotherapy. Under most scenarios, immunotherapy is associated with less toxicity than traditional chemotherapy because it utilizes the patient's own immune system to identify and eliminate tumor cells.
In addition to cancer, IDO has been implicated in, among other conditions, immunosuppression, chronic infections, and autoimmune diseases or disorders (e.g., rheumatoid arthritis). Thus, suppression of tryptophan degradation by inhibition of IDO activity has tremendous therapeutic value. Moreover, inhibitors of IDO can be used to enhance T cell activation when the T cells are suppressed by pregnancy, malignancy, or a virus (e.g., HIV). Although their roles are not as well defined, IDO inhibitors may also find use in the treatment of patients with neurological or neuropsychiatric diseases or disorders (e.g., depression).
Small molecule inhibitors of IDO have been developed to treat or prevent IDO-related diseases. For example, the IDO inhibitors 1-methyl-DL-tryptophan; p-(3-benzofuranyl)-DL-alanine; p-[3-benzo(b)thienyl]-DL-alanine; and 6-nitro-L-tryptophan have been used to modulate T cell-mediated immunity by altering local extracellular concentrations of tryptophan and tryptophan metabolites (WO 99/29310). Compounds having IDO inhibitory activity are further reported in PCT Publication No. WO 2004/094409.
In view of the role played by indoleamine 2,3-dioxygenase in a diverse array of diseases, disorders and conditions, and the limitations (e.g., efficacy) of current IDO inhibitors, new IDO modulators, and compositions and methods associated therewith, are needed. | {
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1. Field of the Invention
The present invention relates to pressure transmitters. More specifically, the present invention is directed to a pressure transmitter using a sealed pressure transmitting system including a barrier diaphragm facing a fluid being monitored.
2. Description of the Prior Art
Pressure transmitters utilizing a pressure sensor, e.g., a semiconductor chip, arranged in a sealed fill fluid system with a barrier diaphragm facing a fluid being monitored are well-known in the art, e.g., the differential pressure transmitter shown in U.S. Pat. No. 3,559,488. In order to facilitate the connection of such a pressure transmitter to a fluid being monitored the use of a remote connection between the barrier diaphragm at the fluid being monitored and the pressure sensor has used a fluid filled capillary transmitting the pressure from the barrier diaphragm to the sensor, e.g., the pressure transmitter shown in U.S. Pat. Nos. 2,906,095 and 3,999,435. However, in those differential pressure transmitters there was no provision for enabling the barrier diaphragm to be selectively positioned within a container or housing containing the fluid being monitored whereby the barrier diaphragm is located at a desired location with respect to the internal wall surface of the container containing the monitored fluid, e.g., flush with the internal wall surface. In order to provide such a capability in a limited fashion the pressure transmitter has been supplied with a barrier diaphragm located on one end of a projecting tube with a pressure transmitter and a mounting flange attached to the other and of the tube. By providing a plurality of different lengths of the tube between the attached transmitter and the flange, the corresponding location of the diaphragm in the container containing the fluid being monitored is achieved. However, such a structure has necessitated the manufacture, storage and use of a plurality of pressure transmitters with corresponding tube lengths to satisfy the various requirements of the industry for the location of the barrier in the monitored fluid. Accordingly, in order to provide a universal and adaptable pressure transmitter capable of affording an infinite number of tube lengths for selectively locating the barrier diaphragm in the fluid, it is desirable to provide a pressure transmitter having a selectively variable location of the diaphragm with respect to the mounting flange at a distanc defining the location of the barrier diaphragm in the monitored fluid. | {
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Additive Manufacturing (AM) is a technique to repeat layering of material in order to create structural components. Selective Laser Sintering (SLS) and Selective Laser Melting (SLM) are two excellent ways in the art. As to fabricate a targeted object, a powder is deposited onto a work surface first. Then, laser irradiated the powder and molten or sintered layer by layer to form the object.
In the process of Selective Laser Melting, the solidification is restricted by the optimized parameters to get the fully dense object. Thus the material microstructure and property is difficult to be optionally controlled in the object. Therefore, it is in need to develop a new technique to control the selective powder melting/sintering process. | {
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Technical Field
The present invention relates to a breakwater, particularly relates to a quickly-detachable airbag-type floating breakwater, and belongs to the field of breakwaters.
Background Art
A breakwater system is one of important technical measures for guaranteeing offshore and ocean platform safety operations. For ocean structures, a breakwater can be protected by attenuating wave energy in a manner of reflecting wave, destroying wave water particle motion, performing resonance or the like, so as to provide a relatively steady ocean environment for the ocean structures, thereby improving the working efficiency and safety thereof, and reducing the economic loss. For offshore engineering such as ports, breakwaters are used not only for stabilizing a water area, but also for reducing sediment accumulation in the ports.
The breakwaters are divided into a fixed breakwater and a floating breakwater. Compared with the conventional fixed breakwater, the floating breakwater has many advantages as follows: (1) since the floating breakwater floats on water generally, seawater flowing cannot be affected, so that the exchange capacity of the seawater is strong, and therefore seawater pollution can be prevented, thereby avoiding influence on the ocean environment; (2) the cost of the floating breakwater is lower than that of the conventional fixed breakwater, the floating breakwater can better adapt to different working water depths and cannot affect the normal working thereof, and the construction cost cannot be sharply increased with the increase of water depths; (3) the floating breakwater can be applied to various geological conditions without being affected by terrain; (4) when a breakwater system with an earth-stone base is constructed, raw materials must face the problems of long-distance sea transportation, high cost, long construction cycle, complex environment and the like, but if the floating breakwater is adopted, these problems can be effectively avoided; (5) the floating breakwater is short in construction cycle, high in speed and convenient to install and remove, and compared with the fixed breakwater, the floating breakwater is convenient for post-maintenance, and low in cost; and (6) it can be adaptive to the cases of large water depth, soft foundation, spring tide range, and water exchange introduction for improving water quality in the ports.
However, most of the existing floating breakwaters are used for temporary construction coverage, there is a lack of breakwater systems designed for heavy storm waves, and the current floating breakwater connecting structure is complex in design, complicated in installation, very time-consuming, and high in post-maintenance cost. | {
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The present invention relates to a method of making an optical beam switching device described herein and which is claimed in co-pending application 09/714,253 filed on the same day as this invention namely Nov. 16, 2000.
The growing demand for increased data rate transmission throughout communication networks has recently created tremendous interest in the field of fiber optic telecommunication. With the deployment of fiber optic cables and the use of dense wave division multiplexing (DWDM), optical data transmission has allowed much greater transmission rates in comparison to its electrical counterpart. Fiber optic cables, each carrying multiple wavelengths of light, are replacing metallic cables. Each wavelength of light denotes a data channel in similar fashion to the multiplexed frequencies that denote television channels traveling through an electrical coaxial cable. Transmission of each optical signal begins with a wavelength-tuned light source at the entrance of the fiber optic cable. Each data channel or wavelength requires a light source emitting at the appropriate wavelength. The optical signals then travel throughout the network and are eventually delivered to the proper destination.
For each data stream to reach its destination, several different components located at junctions throughout the optical network are required. At these junctions, the components must perform tasks such as adding and dropping data from the optical stream, multiplexing and de-multiplexing of the data into and out of the fiber carrier, and switching and routing each data signal between optical fibers to reach its intended destination. In current fiber optic networks, many of these tasks are performed by opto-electronic components such that incoming photonic signals are converted to electrical signals before being manipulated at these junctions. For example, as an optical data stream arrives at a switching node to be switched onto another fiber, each optical signal is first converted into an electrical signal, which is then transmitted through an electrical circuit. The signals are then directed throughout the electrical circuit to the entrance of the appropriate fiber. The electrical signals must then be converted back to their optical forms before being passed along to the targeted fiber. The optical signals continue to travel throughout the optical network, transforming between optical and electrical states until the intended destination is reached.
As the demand for bandwidth increases, more opto-electronic components will be necessary to handle the increased data traffic. Additionally, existing opto-electronic interfaces currently being used cannot be utilized as advances in optical transmission are achieved. Therefore, as light sources develop and more wavelengths are transmitted along a fiber, existing opto-electronic components will need to be replaced. Furthermore, as more opto-electronic devices are deployed, more electrical power is consumed. The added cost of power consumption and the cost and time needed for device replacement has created a demand for alternative methods of photonic signal direction throughout fiber optic networks. The inherent non-scalability of existing opto-electronic interfaces presents a bottleneck in the progression of next-generation telecommunications.
One proposed remedy is the use of optical devices that maintain the transmitting signals in the optical domain while switching and cross connecting from fiber to fiber such that no opto-electronic conversions are required. A method currently being market tested and also being proposed in the present invention is the use of micromirror arrays to reflect light from a fiber entering the junction to a targeted fiber for continuation of the signal to its appropriate destination. Through the use of micro-electromechanical systems (MEMS) techniques, micromirror arrays containing individually movable mirrors can be accurately manufactured.
Current MEMS micromirror arrays developed and being tested for fiber optic switching are actuated via either electrostatic or electromagnetic forces. The most common method of actuation in MEMS-based devices is currently electrostatic actuation. Such devices typically take the form of air-gap capacitors comprising a movable top electrode, a fixed bottom electrode, and air as the dielectric between the electrodes. Electrostatic forces between the electrodes causes motion in the freely movable top electrode. One limitation of electrostatic devices is the air-gap thickness, which dictates the range of motion for the top electrode. Furthermore as the air gap increases, greater voltage is required for actuation. Since it is an air gap the problem of stiction arises where the top mirror can be stuck to the bottom electrode, hence making the device useless. This problem known as xe2x80x9cstictionxe2x80x9d is common to these types of devices. This can occur even during the fabrication process which results in lowered yields.
Electromagnetic MEMS-based devices utilize magnetic materials co-deposited onto the device along with coils external to the device for magnetic field generation. Such devices present a solution to the air-gap restrictions of electrostatic devices, although low voltage operation is still a challenge. Furthermore, the added need for external coils creates a larger device profile.
Therefore, there is still a demand for small form factor, low voltage operating optical switches for enabling all-optical networking. Such a device is a piezoelectrically actuated micromirror. An applied voltage across a piezoelectric material, such as quartz, barium titanate, and lead zirconium titanate, deforms the material proportionally to the voltage being applied. This deformation can be used as an actuating mechanism. Piezoelectric materials are widely used in applications where precise actuation is required such as atomic force microscopy and linear micro-positioning for electron beam lithography. Until recently, most applications have used bulk piezoelectric ceramics that required high voltage for operation. To take advantage of the precise positioning of piezoelectric actuation in MEMS devices, thin film piezoelectric materials have been developed utilizing deposition techniques such as sol-gel, metal organic chemical vapor deposition (MOCVD), and sputtering. With the use of thin film piezoelectric materials, much lower operating voltages can be utilized in comparison to bulk piezoelectric materials.
In contrast with the following prior art, the present invention uses a coplanar arrangement of extremely thin, very low voltage operated cantilevered actuators and mirrors such that one or more actuators are located on each side of each mirror enabling highly precise multi-axial motion of each mirror, often in push-pull mode.
Examples of MEMS micro-actuators utilizing piezoelectric elements can be found outlined by Furuhata and Hirano, U.S. Pat. Nos. 5,351,412, 5,489,812, and 5,709,802 and by Motamedi et al. in U.S. Pat. No. 5903380. The inventions proposed by Furuhata and Hirano incorporate a laminated structure formed by bonding metalized piezoelectric elements to the MEMS fabricated structure. A shortcoming of this device and method is the process of bonding a piezoelectric element to another substrate. The said method must utilize piezoelectric elements that can be adequately handled and positioned, this implies a larger operating voltage than the use of a deposited thin piezoelectric film which can be on the order of several microns thick or less. Furthermore, the efficiency of actuation is dependent upon the placement accuracy and bonding efficacy between the piezoelectric element and the MEMS structure. These shortcomings are resolved in the present invention by utilizing thin film deposition techniques and accurate photolithography. Motamedi at al. outline in their invention a low voltage optical resonator comprising sputtered zinc oxide (ZnO) as the piezoelectric material and claim operating voltages of 2 volts AC. Piezoelectric materials such as PZT have higher piezoelectric coefficients in comparison to ZnO, which provide larger actuation for a given applied voltage as claimed in the present invention.
U.S. Pat. No. 3,758,199: Thaxter, xe2x80x9cPiezoelectrically Actuated Light Deflectorxe2x80x9d
This is a bulk device. We employ thin films and microfabrication methods for manufacturing, enabling high volume, precision manufacturing. Column 3 (line 35) mentions the use of epoxy for bonding the various parts together, which implies bulk materials. In addition, the use of microfabrication methods with our invention enables the manufacture of devices with much smaller form factor than this invention. A smaller device will have higher resonance frequency enabling faster switching and a much lower operating voltage. Column 2 (line 31) describes the cantilever actuator motion; the device is utilizing the extension mode of operation. One cantilever pushes up on the mirror while the other cantilever pulls down. Our design uses coplanar cantilevers utilizing a flexural mode of operation. This again enables the manufacture of a small form factor device and lends itself to microfabrication methods. Also, in column 2 (line 42), hinges are mentioned. The hinges link the cantilevers to the underside of the mirror at 90-degree angles and articulate when the cantilevers are actuated. This configuration will concentrate the stress directly at the 90-degree elbow in the hinge, which could cause premature fatigue failure. Our design uses a coplanar configuration of the hinge, cantilevers, and mirror creating no stress concentrations. Furthermore, the hinges and supporting structure located underneath the mirror and actuators for our design are fabricated of the same material, which again enables the use of microfabrication methods. Again in Column 2 (line 35) and FIG. 1, the author discloses a mirror that is at right angles to the PZT material. In other words as the PZT material flexes the mirror is rotated. In our case the cantilever are coplanar to the mirror surface and attached through hinges in the coplanar geometry. So not only is our form factor smaller as mentioned above but the entire geometry is different.
U.S. Pat. No. 3,981,566: Frank et al., xe2x80x9cLever-action Mountings for Beam Steerer Mirrorsxe2x80x9d
This is another bulk device having similar disadvantages as Thaxter mentioned above. As in Thaxter, Frank""s hinge arrangement concentrates the stress at the elbow.
U.S. Pat. No. 5,367,584: Ghetto et al., xe2x80x9cIntegrated Microelectromechanical Polymeric Photonic Switching Arraysxe2x80x9d
Waveguide arrays are fabricated and switching between the waveguides occurs by actuating a portion of one waveguide causing it to come into contact with an adjacent waveguide. Light propagating through the first waveguide is then transferred to the adjacent waveguide. Some loss will occur with this approach as the light passes through the electrodes located between the waveguides. In addition, sacrificial etching is used to creating air gaps, which pose stiction problems during fabrication.
U.S. Pat. No. 5,761,350: Koh, xe2x80x9cMethod and Apparatus for Providing a Seamless Electrical/optical Multilayer Micro-optico-elettro-mechanical System Assemblyxe2x80x9d
This patent discloses the use of flip chip bonding and, wafer bonding to form multichip modules. Firstly, the mirrors in this case are fixed; they are only used to direct incoming light to a photodetector located above the mirror. This is essentially a compact optoelectronic device. However, the patent uses a couple of low temperature materials, optical epoxy and polyimide, in their structure. The flip chip bonding technique mentioned is C4 bonding which is a solder reflow type and typically occurs around 250 deg. C. This temperature could also cause reflow in the polyimide and optical epoxy rendering their device useless. The device of the present invention does not have such temperature constraints and we employ a polymer flip chip approach, which utilizes a lower temperature.
U.S. Pat. No. 5,771,321: Stern, xe2x80x9cMicromechanical Optical Switch and Flat Panel Displayxe2x80x9d
This invention depicts a different optical switch primarily for display applications utilizing electrostatic actuation. Display applications require less speed and have little or no positioning stringency for the actuated mirror. Typically, the mirror needs to move at frame rate (30 Hz) and deflects light such that the pixel attributed to the mirror is either on or off. For our device, the optical switch must be switchable at higher speeds (1 kHz) and have accurate positioning for directing optical traffic to the appropriate fiber. Although, flip chip bonding is mentioned, but no details are described. There are several different methods of flip chip bonding and furthermore, Stern mentions the possible use of polymeric materials in their device which could pose problems when flip chip bonding as previously mentioned in connection with the Koh patent.
U.S. Pat. No. 5,808,780: McDonald, xe2x80x9cNon-contacting Micromechanical Optical Switchxe2x80x9d
This invention depicts an electrostatic mirror for optical switching. This device is only utilized in one dimension, up and down with respect to the substrate. The arrangement of the cantilevers shown in FIG. 1b could allow for tilting action perhaps somewhat similar to our device, however, the axis of rotation will not be through the center of the mirror. The axis of rotation for this device if used for tilting would be located along the imaginary line through the mirror formed by connecting opposing cantilevers at points where they are attached to the mirror. This motion would cause an elongating stress to the other 2 cantilevers not being used for actuation as the mirror will pull away from these remaining 2 cantilevers. The design of the preferred embodiment of the present invention, places each cantilever at the center of each edge, so that when 2 opposing cantilevers are actuated, the remaining 2 non-actuated mirrors are only slightly torsionally rotated. This motion induces much less stress than elongation, which can produce premature creep in a material. FIG. 2 and the middle of column 3 suggest that the device can be run in a tilting mode. The tilting is describes as more of a xe2x80x9ctorqueingxe2x80x9d of the mirror surface than actually tilting the mirror. With this torqueing, much stress will be induced with this geometry and thus the xe2x80x9ctorqueingxe2x80x9d provides very limited angular motion. The electrode structures suggested in FIG. 3a-c are used for fine tuning of the mirror location. More electrodes provide for finer tuning which is necessary for accurate optical switching between fibers. However, each electrode must have an electrical connection and, therefore, more electrodes require more connections which make the overall size of the device larger. Our preferred design of the present invention utilizing piezoelectric actuation, has fine tuning through the use of only varying the driving voltage; piezoelectric actuators inherently provide precise positioning. Finally, the reference xe2x80x9cTo CMOSxe2x80x9d in FIG. 1a refers to the MEMS device which was fabricated on the top of a CMOS-processed silicon wafer. Essentially the MEMS device was built up on the silicon substrate, which already had the CMOS, patterned. Flip chip bonding is not implied here. Note that for this device to work, it is required that the reflective surfaces be aligned with the device. In other words the reflective surfaces shown in the cover page figure (number 32 in the figure) are an intrinsic part of the device. Our device will tilt via the actuators, they will not just move up and down. Also a fundamental difference is that this is essentially an air gap capacitor so that there is a limit to the distance of motion (that of the air gap). In our invention, with a cantilever driving structure there is no air gap and hence no problems with stiction (the mirror sticking on the bottom) or limitations in depth due to air gap size.
U.S. Pat. No. 5,870,007: Carr et al., xe2x80x9cMulti-dimensional Physical Actuation of Microstructuresxe2x80x9d
This invention describes several actuation structures and mechanism. The invention mostly concentrates on thermal actuation, the use of a bimorph structure with 2 materials of different TCEs (thermal coefficients of expansion), essentially a thermocouple. Such thermal actuation methods can provide large motion, but at the sacrifice of speed. The material must heat up and cool down which is much slower than the motion of an electron (electrostatic actuation) or dipole switching (piezoelectric actuation). This invention has a few piezoelectric and electrostrictive references, however, the author seems to interchange the two terms. Piezoelectric materials are not the same as electrostrictive (see column 5, line 25). They are classified by crystal structure; piezoelectrics are asymmetrical whereas electrostrictive materials are symmetrical. A piezoelectric material, such as PZT, is first poled to align the dipoles allowing for actuation. An electrostrictive material, such as PMN, is actuated by continuously applying a DC voltage to the material and then varying the voltage amplitude. Furthermore, the motion induced by either piezoelectric or electrostrictive means is created from the transferal of stress from the actuating material to the underlying structure and not by xe2x80x9cdifferential stressxe2x80x9d typical of thermal actuation as mentioned in column 5, line 39. This particular invention seems more concerned with larger actuation than on precise, fast actuation that we are proposing for the optical switch of the present invention. The preferred embodiment is detailed in FIG. 3 (see column 3, line 15 reference) as with all of the descriptions this is a cantilever structure that does not rely on hinging but instead places the cantilever directly under the mirror structure and relies on the bending of the cantilever. Ours is a hinged device. Furthermore they do not have the two dimensional push-pull action disclosed in our invention.
In comparison to the cross connect optical switch proposed by Solgaard et al. (U.S. Pat. No. 6,097,859), several improvements are rendered with our invention. The switch by Solgaard utilizes polysilicon micromachining technology, a subset of MEMS technology. In polysilicon micromachining, the structural material is polysilicon and sacrificial etches are used to create freestanding structures. One inherent problem with polysilicon is the intrinsic stress of the deposited thin film. The intrinsic stress can be great enough to cause buckling or even fracturing of the freestanding structure. Additionally, the use of sacrificial etching to remove the sacrificial layer from underneath the polysilicon can create stiction problems. Stiction can occur after the sacrificial etch causing the polysilicon structure to become permanently stuck to the substrate, thus no longer achieving a freestanding structure. Furthermore, the invention utilizes a landing electrode, which stops the mirror at the appropriate location. This mechanism is typically used in electrostatic actuation due to the inherent flutter that can occur with this type of actuation. The use of a landing electrode can pose problems with contact wear after numerous cycles of the actuators and mirrors hitting the landing electrode. Finally, the said invention utilizes electrostatic torsional actuation, which calls for complex driving circuitry. In order to achieve precise control of the mirror, the location of the rotation axis must be also controlled. Due to the mirror being a floating structure, the axis of rotation can move as the mirror is moved. Such action can produce a wobbling effect unless proper control of the rotation axis is achieved.
Our present invention addresses and improves upon the above short falls of the Solgaard invention. Firstly, our structural material is low stress silicon nitride. Much lower intrinsic stress is observed in this material in comparison to polysilicon. Therefore, flatter structures can be manufactured. Secondly, sacrificial etching is not used in our invention to create freestanding structures. Deep reactive ion etching (DRIE) of the substrate is used to completely remove the substrate material from beneath the mirrors and actuators of our invention. Therefore, stiction will not be a problem, as no substrate will remain underneath any of the moving structures. Thirdly, our optical switch uses piezoelectric actuation. With piezoelectric actuation, no landing electrode is necessary. Therefore, contact wear will not be a problem. Finally, the piezoelectric actuators are used in a flexural mode, therefore, with the inherent linearity of piezoelectric materials, much simpler driving circuitry can be used.
In comparison to the optical matrix switch proposed by Laor (U.S. Pat. No. 6,097,860), the Solgaard patent proposes electromagnetic actuation for each of the mirrors in the optical matrix. The mirror itself is a gimbal mounted structure allowing 2-axis motion. Several issues can be foreseen with such a design. Firstly, to achieve electromagnetic actuation, chip mounted electromagnetic elements (such as coils) must be located around each mirror. This entails a manufacturing challenge due to the necessary placement and mounting of each electromagnetic element around each mirror. Such elements are difficult, if not, impossible to fabricate with current MEMS-compatible processes. Therefore, such fabrication and placement of said electromagnetic elements involves additional processes, further complicating the manufacturing process. Secondly, the overall size of each packaged mirror must be adequately large enough in order to accurately place each said electromagnetic element. Therefore, larger mirror chips are typically required when compared to mirrors that are electrostatically or piezoelectrically actuated. Finally, each mirror must be adequately spaced apart so that fringe field effects are minimized from each of the electromagnetic elements. If mirror spacing is not large enough, the magnetic fields emanating from electromagnetic elements surrounding one particular mirror may induce unwanted magnetic effects in other surrounding mirrors. To finalize the critique of electromagnetic mirror arrays, one can see that as the mirror array contains more mirrors, the overall size of the unit containing the whole mirror array can become quite large in comparison to electrostatic or piezoelectric devices.
Our present invention greatly improves on the size requirements for electromagnetic mirror arrays by using both piezoelectric actuation and CMOS driving circuitry, which is packaged with each mirror array. The use of piezoelectric actuation enables all materials and structures required to be fabricated utilizing existing MEMS processes and takes advantage of the manufacturing capabilities thereof. Furthermore, the actuators for each mirror are spatially and accurately located within microns of the mirror. This is again achievable due to the use of existing photolithographic processes currently available in the MEMS and semiconductor industries. Finally, the use of extremely thin film piezoelectric material requires less than 5V DC for full actuation which enables each mirror array to be packaged with its own CMOS-compatible driving circuitry creating a small form factor module.
Min et al. (U.S. Pat. No. 6,030,083), proposes similar thin film piezoelectric actuation. However, each actuated mirror is located above its respective cantilever actuator enabling only single axis motion. Our present invention uses a coplanar arrangement of the actuators and mirrors such that one or more actuators are located on each side of each mirror enabling multi-axial motion of each mirror. Furthermore, the said invention is proposed for the purpose of image projection and is concerned only with frame rate oscillations, which typically occur at a cycle rate of 30 Hz. The purpose of our present invention is for the redirection of light from fiber optic cables which will require accurate positioning and much faster response times on the order of 1 millisecond (1000 Hz).
The present invention involves a method of making the novel micro-mirror light beam switch described herein, and claimed in the aforesaid copending application, the switch having a thin flexible movable support member for supporting a thin central reflective mirror surface thereon and for supporting a plurality of thin unimorph or bimorph piezoelectric cantilevered mirror actuators, mechanically coupled between a fixed substrate and movable hinging portions of the thin movable support member. The method employs thin film deposition techniques and photolithography for readily forming the extremely thin switch, whereby the components thereof are substantially co-planar. A silicon nitride or silicon dioxide support member layer is deposited over a silicon substrate and two metallic electrode layers and a piezoelectric layer are thereafter deposited upon the support member layer. Then, these layers are etched away to form extremely thin piezoelectric actuators that can be driven by low voltage CMOS driver circuitry. The support member layer is also etched away to form a flexible actuator support member, and finally a reflective mirror surface is deposited on the underside of the flexible actuator support member.
The micro-optical switch made in accordance with the method claimed herein below utilizes a piezoelectric material, preferably PZT for low voltage micro-mirror actuation with highly accurate positioning, and greatly improves on the size requirements for electromagnetic mirror arrays by using both piezoelectric actuation and CMOS driving circuitry, which is packaged with each mirror array. In other words the drive voltage can be analog, digital or binary as required. The use of piezoelectric actuation enables all materials and structures required to be fabricated utilizing existing MEMS processes and takes advantage of the manufacturing capabilities thereof.
Furthermore, the actuators for each mirror are spatially and accurately located within microns of the mirror. This is again achievable due to the use of existing photo-lithographic processes currently available in the MEMS and semiconductor industries. Finally, the use of extremely thin film non-bulk piezoelectric material only requires less than 5V DC for full actuation which enables each mirror array to be packaged with its own CMOS-compatible driving circuitry creating a small form factor module.
The novel micro-optical switch comprises a MEMS (Micro-Electromechanical Systems) micromirror array with packaged CMOS driving circuitry. Extremely thin micro-mirrors and PZT actuators are employed so that these components are substantially co-planar. The low operating voltage of the MEMS non-bulk extremely thin mirror actuators enable the use of typical 5-volt or less CMOS circuitry. The appropriate driving circuitry can be processed separate from the MEMS fabrication with the final device being a hybrid of a MEMS chip and a CMOS chip bonded together. In the currently most preferred embodiment of the switch, each square micro-mirror in the array is comprised of a centrally located, highly reflective material of known composition and thickness, coupled around its periphery to the movable ends of four orthogonal cantilever structures. The movable end of each actuator is coupled to the mirror periphery via flexible hinge portions of the silicon-based support sheet member. The silicon substrate is preferentially removed from beneath each central mirror area to enable forming this thin flexible mirror and actuator silicon-based support sheet member for supporting a reflective mirror surface and the movable portions of the actuators. The four orthogonal extremely thin cantilever actuators are thus coupled to each reflective mirror surface via hinging portions of the flexing support sheet, to form a floating device for each mirror. Each cantilevered actuator is attached to the fixed array substrate only at its fixed end. Furthermore, each cantilever actuator structure is of a unimorph or bimorph construction consisting of a patterned thin film of known thickness such as silicon nitride or silicon dioxide for structural support and a PZT capacitor as the actuator.
By applying a low voltage to each extremely thin PZT actuator capacitor, the stress induced in the PZT material creates a stress in the attached support material. The transferal of stress to the support material, which is anchored to the substrate at one end in similar fashion to a diving board, causes upward or downward motion to occur at the opposite movable end of the cantilever, dependent upon on the polarity of the applied voltage. Additionally, the amount of motion can be precisely controlled through control of the applied voltage. Each cantilever structure, coupled to each side of the square micro-mirror via a hinge member, is individually addressable, allowing multi-axial movement of each micro-mirror. Thin and flexible support sheet portions adjacent movable terminal portions of the cantilevered actuators, act as stress relieving hinge flexing areas, relieving stress from the stiffer actuators.
To achieve a tilting motion about an axis, the PZT actuators located perpendicular to the desired axis of rotary mirror motion, are addressed with opposing potentials such that one cantilever moves upward while the opposing cantilever moves downward. This in turn tilts the mirror about the desired axis. Also, by applying opposing potentials to the remaining two cantilevers in similar fashion, 2-axis motion is realized. Finally, through the application of equal polarity to all actuators, a parallel motion with respect to the substrate can be achieved. This precisely controlled, multi-axial motion of each micro-mirror provides the accuracy and low voltage operation necessary for the rapid switching of optical traffic from fiber to fiber in the next-generation optical networks. | {
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Benefits of medical data display systems include rapid presentations and storage of data of monitored health conditions for a patient. At least some of this information may be generated by electronic sensors configured to detect at least one medical condition of a patient and produce an electronic signal based on that medical condition. The electronic signal may be collected over time in at least one standard metric used in the care of the patient may be determined for analysis by a medical care provider. Examples of a standard metric may include heart rates and electrocardiogram data. Data for the standard metric can be collected over extended timeframes, for example, in some cases twenty-four hours or more to monitor the health of the patient and to identify abnormalities which may occur with frequencies that may vary on a patient-to-patient basis. The abnormalities may be observable as changes in the standard metric occurring at occurrences that are predictable or still being understood. The abnormalities may be used by the medical care provider to provide long term care to the patient, predict future medical events, or to diagnose medical conditions of the patient.
As the amount of medical data in the form of electrical signals from the patient becomes more readily available and the time demands on the medical caregiver continue to increase, there is a need to more efficiently provide assistance to the care provider to provide convenient access to the at least one standard metric. In some cases, the at least one standard metric may conventionally be generated as an electrocardiogram hardcopy data printout and the caregiver must meticulously review the long hardcopy strip which may include twenty-four hours or more of data to determine abnormalities in a time consuming process. Further, in some cases the care provider often correlates that at least one standard metric to other data, for example, a second standard metric in the form of heat rates to monitor the health of the patient. Correlating multiple metrics can also be a time consuming endeavor and prone to errors as the large quantities of data are often difficult to analyze and compare particularly under the stressful environment of a care provider facility where medical care decisions may necessarily need to be made very quickly to ensure that the patient receives accurate and timely care. New approaches are needed to enable care providers to more easily recognize and understand the occurrence and identities of health events experienced by patients, so that care providers may be better informed to provide more effective treatments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. | {
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The basestations used by the providers of current day multiple channel wireless communication services, such as cellular mobile telephone (CMT) and personal communication systems (PCS), typically designate signal processing equipment for each single receiver channel. This is probably a result of the fact that each basestation is configured to provide communication capability for only a limited predetermined number of channels in the overall frequency spectrum that is available to the service provider.
A typical basestation may thus contain several racks of equipment which house multiple sets of receiver and transmitter signal processing components that service a prescribed subset of the available channels. For example, in an IS-136 TDMA cellular system, a typical basestation may service a pre-selected number of RF channels, such as 12, simultaneously supporting a total number of 36 mobile units, of the total number, such as 416, of the RF channels available to the service provider.
Wireless service providers would prefer, however, to employ equipment that would be more flexible, both in terms of where it can be located, as well as in the extent of the available bandwidth coverage provided by a particular transceiver site. This is particularly true where relatively large, secure, and protective structures for multiple racks of equipment are not necessarily available or cost effective. Additionally, service providers desire equipment that can accommodate subscriber growth with features making more efficient use of the available RF spectrum, such as for PCS applications.
One way to resolve this difficulty is to implement a basestation transceiver using a high speed analog-to-digital (A/D) converter and equipment which makes use of efficient digital filtering algorithms such as the Fast Fourier Transform (FFT) to separate the incoming signal energy into multiple baseband channels. On the transmit side, this implementation includes an inverse FFT processing combiner which outputs a combined signal representative of the contents of the baseband signal provided to it.
U.S. Pat. No. 5,940,384 assigned to the same assignee as the present invention and hereby incorporated by reference describes a method of flexibly allocating modulators and demodulators (in the form of digital signal processors or DSPs) to ones of these baseband channels as additional resources are needed, for example, during times of high message traffic. By making the basestation's implementation of call processing resources modular, the basestation can initially be configured to support a limited number of channels. Then, as the demand for services grows, additional channels can be supported by the addition of additional DSPs. The DSPs allow a change or expansion in the type of service, for example, into one of several air interface standards such as code division multiple access (CDMA) as well as time division multiple access (TDMA).
To ensure non-interfering coverage among dispersed basestations, each basestation uses only a subset of the available RF channels, so that mutual interference among any of the channels of the network is reduced. To further reduce interference, frequency hopping can be used. Frequency hopping can significantly reduce the average interference on a given RF channel compared to statically tuned channels. With reduced interference, higher frequency reuse is possible allowing more efficient use of the available RF spectrum, thus enabling higher capacity within the network. | {
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The invention relates to a method for the production of cement clinker from raw cement meal which is preheated in at least one heat exchanger string, through which the exhaust gas from a rotary tubular kiln flows, and is burnt in the sintering zone of the rotary tubular kiln to form cement clinker which is cooled in a following cooler, comprising the removal of a partial hot flow (bypass gas flow) of the rotary kiln exhaust gas, said partial flow being laden with dust loads and/or gaseous/vaporous harmful substances inclined to cause cakings, comprising the cooling of the bypass gas flow in a mixing chamber and comprising the following separation of dust containing harmful substances from the cooled bypass gas flow. The invention relates, moreover, to a plant for carrying out the method.
In the production of cement clinker from raw cement meal, it is known that many batch materials, such as raw cement meals, but also many fossil fuels used, contain secondary constituents, such as, for example, alkali compounds, chlorine, sulfur compounds, heavy metals, etc., which, in the region of the sintering zone of the rotary tubular kiln, evaporate, for example, as alkali chloride compounds and alkali sulfate compounds, condense/crystallize again in the preheater region of the cement clinker production line and thus build up circulations, with the result that both the quality of the cement clinker may be adversely influenced and the combustion process itself may be disturbed considerably.
To suppress such circulations in a cement clinker production line and to reduce the content of circulation-forming materials in the clinker production process, it is known, for example from the pamphlet “Drehrohrofenanlagen” [“Rotary tubular kiln plants”], No 8-100d of K H D Humboldt Wedag A G, pages 10/11, of May 1984, by means of what is known as bypass gas removal, to branch off part of the hot dust-laden kiln exhaust gases containing the volatile compounds out of the lower region of the rotary kiln exhaust gas riser line or directly out of the rotary kiln entry chamber, to cool them in a mixing chamber by the introduction of external air, to cause the vaporous harmful substances contained in the bypass gas flow to condense on the entrained solid particles and then to clean the cooled bypass gas flow by the separation of the dust containing harmful substances in a specific dust separator. In order to ensure that the volumes of the bypass gas flow that are to be treated and its dedusting devices do not become too large, it is also known not only to mix external air as a cooling medium into the bypass gas flow, having a temperature of, for example, 1150° C., but also to inject water which is intended to assist the shock cooling of the bypass gas flow.
Furthermore, DE-C-27 24 372 discloses a cement clinker production line comprising the removal of a bypass gas flow which is cooled in a mixing chamber, apart from injected water, not in this case by means of fresh air, but by means of a partial flow of the production exhaust gas or system exhaust gas which has already been cleaned in an electric separator. This partial exhaust gas flow already cleaned in the system filter, however, is laden with dust again in the mixing chamber of the bypass gas flow, at least this partial exhaust gas flow then having to be cleaned a second time in the separate bypass gas flow dust filter, so that the known cement clinker production comprising bypass gas removal takes up relatively large filter volumes, along with the associated high investment and operating costs.
In cement clinker production, there are increasing bypass problems, because, in cement clinker production, both Western industrial nations and emerging and developing countries increasingly use chlorine-laden and sulfur-laden waste fuels and residual materials as what are known as secondary fuels. Many operators of cement clinker production lines therefore attempt to lower the circulation level of volatile components (in particular, chlorine and sulfur) to a tolerable level by locking out the system filter dust. However, they shy away from installing a separate bypass system which incurs considerable investment and operating costs for additional dedusting devices, mostly electrostatic dust separators, dust transports and fans. To be precise, as a rule, the mixed bypass gas flows occurring as a result of the supply of large bypass cooling air quantities are so great that they cannot be treated in already existing electrostatic dust separators in addition to the already existing quantities of system exhaust gases. | {
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Endoscopic surgical techniques allow a surgical procedure to be performed on a patient's body through a relatively small incision in the body and with a limited amount of body tissue disruption. Endoscopic surgery typically utilizes a tubular structure known as a cannula which is inserted into a small incision in the body. The cannula holds the incision open and serves as a conduit extending between the exterior of the body and the local area inside the body where the surgery is to be performed.
Due to the relatively small size of the passage into the body which is defined by the cannula, certain surgical procedures, such as posterior disectomies and procedures using steerable surgical instruments, have been difficult to perform using endoscopic techniques. | {
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There are many types of computer data storage devices. One type of computer data storage device is random access memory (RAM). RAM is used to temporarily store data while a computing device is powered on. RAM may be implemented using integrated circuits in the form of a memory module, such as a dual-inline memory module (DIMM). | {
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1. Technical Field
The present invention relates generally to computer graphics, and more particularly to a method and apparatus for efficiently rasterizing polygons in two dimensions.
2. Description of the Related Art
Computer graphics designers commonly model objects with polygons defined by a fixed set of vertices and edges joining those vertices. The polygon's vertices are typically stored in the application data structure. The scene designer will construct an object one polygon at a time, and then define the various attributes for that polygon at each of its vertices. Any number of attributes may be defined at a vertex including color, specular color, alpha (translucency), fog, surface texture and z (depth). The vertex attributes must eventually be interpolated to each pixel contained in the polygon in a process commonly referred to as scan conversion or rasterization. Currently, available rasterizers use a windower in conjunction with either an interpolator, multiplier or incrementer for interpolating all of the polygon vertex attributes to generate the attribute values at each pixel contained within the polygon. The function of the windower is to traverse the area of the polygon in a way that is guaranteed to visit all the pixels internal to it. Being assured that all the pixels inside the polygon will be visited by the windower, attribute values defined at the vertices are then interpolated to each pixel in the polygon. The polygon can be traversed by any algorithm that is guaranteed to cover all the pixels, and many techniques have been suggested in the prior art, however, most suffer from the limitation of being inefficient in their approach thereby necessitating excessive computational time. An additional drawback associated with inefficient traversal algorithms is the requirement that the interpolation hardware carry additional precision to compensate for overshoot and retrace of the graphics primitive. Representative examples of prior art traversal algorithms can be found in A Parallel Algorithm for Polygon Rasterization, Juan Pineda, Apollo Computer Inc., Siggraph '88 Atlanta, Computer Graphics, Volume 22, Number 4, August 1988. A further drawback associated with conventional interpolation methods involves the added costs associated with using interpolators that have the capability of multiplying. Conventional interpolation methods sometimes require that during the process of traversing or walking the face of a polygon a jump may be required to some random location on the face. To execute the required jumps, a multiplication operation is required of the interpolator. The hardware costs of multiply capable interpolators is greater than the cost of interpolators without such a feature.
Accordingly, there is a need to provide an efficient, accurate and inexpensive method and apparatus for rasterizing triangle primitives from descriptions that define x, y coordinates of three vertices, and several attributes per vertex such as color, specular color, depth, and texture coordinates. | {
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This invention relates to a novel class of cephalosporin antibiotics. In particular it relates to 3-halo cephalosporins represented by the following generalized formula ##STR1## wherein R is hydrogen or an acyl group derived from a carboxylic acid, R.sub.1 is hydrogen, a carboxylic acid protecting ester group or a pharmaceutically acceptable ester or salt, and X represents fluoro, chloro, bromo, or iodo.
The compounds of the invention possess the unique structural characteric of a halogen atom directly bonded to the carbon atom in the 3-position of the dihydrothiazine ring. According to the cepham nomenclature system the above depicted compounds are named as 7-amino- or 7-acylamido-3-halo-3-cepho-4-carboxylic acids, salts and esters.
Prior to this invention 3-bromomethyl-3-cephem-4-carboxylic acid esters, U.S. Pat. Nos. 3,647,788 and 3,688,203, and 3-bromomethyl-2-cephem-4-carboxylic acid ester U.S. Pat. No. 3,637,678 were described. These known 3-bromomethyl compounds are described as useful intermediates for preparing cephalosporin antibiotics. In contrast with these intermediates, the 3-halo-3-cephem-4-carboxylic acids described herein are especially valuable antibiotics. | {
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This invention relates generally to systems for identifying military vehicles as friendly or hostile and, more particularly, to identification systems that rely on infrared emissions of the military vehicles.
Friend or foe identification systems used by military aircraft are generally radar-based systems, which operate in the microwave portion of the electromagnetic spectrum. Because the basic radar return from an aircraft is highly diffracted, the basic return cannot be used to positively identify the shape and, therefore, the type of aircraft. However, other portions of the radar return can be used to identify the type of aircraft. For example, a jet engine modulation (JEM) system analyzes the doppler shift of the radar return to determine the number and rotational velocities of the turbine blades in an aircraft""s jet engine. From this, the type of jet engine can be identified and, once the jet engine has been identified, it is usually a simple matter to identify the type of aircraft. However, this system is not reliable as the enemy may be operating the same type of aircraft.
Another friend or foe identification system used by military aircraft utilizes a transponder to encode the radar return with the identity of the vehicle. However, this radar system can also be jammed and, in addition, can be intercepted or mimicked by the enemy. Accordingly, there has been a need for an improved identification system providing rapid and positive friend or foe identification of land, sea and air vehicles at long ranges without the possibility of being jammed, intercepted or mimicked. The present invention clearly fulfills this need.
The present invention resides in an infrared identification system for identifying military vehicles as friendly or hostile. Briefly, and in general terms, the present invention includes a seed introduction system, in each friendly vehicle, that introduces trace quantities of a particular seed formulation into the vehicle""s exhaust. An infrared detection system, also in each friendly vehicle, detects the spectrally-discrete thermal emissions of the seed formulation to identify those vehicles having the thermal emissions as friendly.
More specifically, in a presently preferred embodiment of the invention, the seed introduction system introduces trace quantities of a particular seed formulation, which is changed preferably on a daily basis, into the vehicle""s exhaust. The seed formulation can be introduced either continuously or upon interrogation by another friendly vehicle or other friendly source, such as a ground-based radar installation. When thermally excited, the seed formulation emits infrared radiation at known spectrally-discrete wavelengths. The infrared detection system can detect the faint infrared radiation all but buried in atmospheric and exhaust background noise, but only by knowing the particular seed formulation in use for that day. Detection of the infrared radiation confirms that the vehicle is friendly.
The seed introduction system includes a pressurized tank for storing the seed formulation of the day and a control system for injecting trace quantities of the seed formulation into the vehicle""s exhaust. The control system includes a valve for releasing the seed formulation from the pressurized tank and a receiver for opening the valve when interrogated by a friendly source. Seed formulations that have been found to have suitable emissions within the infrared spectrum include the following halides:
hydrogen chloride (HCl)
hydrogen bromide (HBr)
hydrogen iodide (HI)
hydrogen fluoride (HF),
the following hydrides:
sodium hydride (NaH)
calcium hydride (CaH)
potassium hydride (KH),
and the following oxides:
beryllium oxide (BeO)
germanium oxide (GeO)
magnesium oxide (MgO)
selenium oxide (SeO)
aluminum oxide (AlO).
The infrared detection system includes a wide angle, optical lens and a standard, off-the-shelf infrared detector having a high sensitivity in the spectral region of interest. Because the infrared and visible spectrums are so close in frequency, an optical lens may be used to collect the observed radiation and concentrate it onto the sensitive infrared detector. The output of the infrared detector is filtered with a high-resolution bandpass filter that is centered at a frequency of one of the spectrally-discrete infrared emissions of the seed formulation of the day. The output of the bandpass filter is applied to a threshold trigger, which activates an indicator light when the total energy output by the bandpass filter exceeds a predetermined value, indicating that the interrogated vehicle is friendly. | {
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Certain devices within distributed power systems can operate on different types (e.g., direct current (DC), alternating current (AC)) and/or amounts (e.g., 24V, 2 A, 120V, 50 mA) of power relative to the type and amount of power that feeds the distributed power system. Further, the devices receiving power from the device distributing the power within the distributed power system can be located relatively close. In some cases, distributed low voltage power systems use one or more power distribution circuit modules. | {
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The purpose of cross-system analytics is to consolidate, transform and clean data from source systems and thereby provide a central and consistent view for reporting and analyzing data within an organization.
When data is exchanged among several source systems, it is very likely that the data does not fit together from a business or technical context. When the data is exchanged, functionality is needed to bring the different data sets together to create one common data foundation (i.e. core data model).
Very often a core data model is defined numerous times for different purposes. In many cases, this is because minor metadata must be added. For example technology solutions for integration, user interface, analytics or transactions unnecessarily require their own data models. This increases the total cost of ownership (TCO) as the same content must be provided several times. Due to the incompatible meta-models, cross topics like user interface integration, extensibility or authorization, must be solved various times. This results in high TCO and encounters consumption of solutions by customers.
In case of cross-system analytics, application data from one or more source systems is replicated into separate database schemas in a target system, one schema for each source system. Local views may be defined on top of those external application database tables. Local views of different source systems may be combined into cross views for implementation of cross-system analytics scenarios
Although there may be cross-system analytics scenarios where the number of the involved systems of same type is already known during design time (e.g. exactly one SAP enterprise resource planning (ERP) system and one SAP customer relationship management (CRM) system are relevant), other scenarios exist where the role of the involved systems is known in advance (e.g. SAP ERP) but not the number of each type of system. This may be because the number of systems of a particular system type may depend on the explicit customer system landscapes (e.g. n×SAP ERP). However this information is necessary for the definition of cross CDS views in order to provide cross-system scenarios that must be applicable for different customer environments without the knowledge of explicit customer system landscapes.
Different options exist to master the challenge of not having any knowledge about the explicit customer system landscape while still needing to define cross views. For cross-system scenarios, respective cross views could be defined and subsequently extended by customer to their specific system landscapes. However, the extensibility concept of an involved database environment is not powerful enough to allow enhancements of cross views by customers or partners. Customers could also copy or modify delivered cross views, however the customer would then be cut off from bug-fixes or new releases of the views delivered by the service provider.
Therefore, the inventors perceive a need to develop a solution for defining cross views when the system landscape is not known without sacrificing any of the flexibility of having a virtual data model. | {
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The present invention relates to a method of manufacturing a filter element for use in a dust collector such as those used in, for example, a factory for separating particles contained in gas kept at a temperature from room temperature up to 160.degree. C., for collecting powder products or environmental safety or used to remove dust contained in exhaust gas of a drier, a boiler or an incinerator.
A filter bag made by sewing a filter cloth or a filter element such as sintered plastic material having intercommunicating porosity has been used for collecting dust particles produced in a factory for product collection or dust removal. As the porous plastic filter element having been produced by sintering synthetic resin particles, a self-supporting member produced by sintering polyethylene particles, polypropylene particles or a mixture of these particles is disclosed in Japanese Patent Gazette 5934/1989 and the same member coated with adhesive containing tetrafluoroethylene is disclosed in Japanese Patent Application Laid Open No. 502381/1986.
On the other hand, for collection of dust contained in exhaust gas of a drier, a boiler or an incinerator, a dust collector or an electric dust collector using a filter element has been used widely, a heat durable filter cloth of glass fiber or heat resistive synthetic resin fiber or a sintered ceramic filter when gas temperature exceeds 300.degree. C. being incorporated in the filter element.
It has been known, however, that, although the sintered porous synthetic resin material filter bag or filter element is effective at around room temperature, it is easily deformed and thereby rendered unsuitable for normal use at a temperature above about 70.degree. C.
The filter bag incorporating glass fiber or heat resistive synthetic resin fiber cloth has been used to separate particles from gas at a temperature of 160.degree. C. or lower. However, since texture thereof is usually rough, there may be leakage of dust therethrough or, when a felt cloth made of such fiber is used, the felt cloth may be clogged gradually with dust particles layered thereon, causing flow resistance of air therethrough to be increased which means that a higher power is required for a blower. Further, in the case of filter bag, pressurized air is supplied intermittently in an opposite direction to dust containing gas flow to blow away particles accumulated on the filter surface. This causes friction between an insert for the bag for maintaining the shape thereof and the filter cloth to occur, frequently damaging the latter.
When, in order to separate particles from gas at 160.degree. C. or lower, a dust collector using the sintered ceramic filter member or an electric dust collector is used, the cost thereof becomes high, as the sintered ceramic filter member or the eletric dust collector itself is expensive. | {
"pile_set_name": "USPTO Backgrounds"
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The present invention relates to an electronic circuit that can be applied to a pixel circuit and a sensing circuit, and electronic device such as an electro-optical device and a detection device, and electronic apparatus.
Recently, interest has arisen for electro-optical device having an electro-optical element such as organic EL element since it excels in low power consumption, wide view angle, and higher contrast ratio. Transistor is often used for driving such a electro-optical element. Variation or change of characteristic of transistor has a significant affect on performance of electro-optical element. Compensation or reduction of the variation or change is an important subject to improve performance of an electronic device. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
This invention relates to integrated circuits in general and, more particularly, to a computer chip including a programmable input/output processor.
2. Description of Related Art
The concepts of integrated circuits and computer systems are generally well known. A typical computer system is made up of a multitude of different, specialized computer chips. Chip makers can now place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place up to ten million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place one billion transistors on a single chip. Thus, computer systems are evolving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. Economies of scale in manufacturing require that start-up costs be amortized over as many pieces of product as possible to keep per-unit costs low. Custom integrated circuits are usually only produced in limited numbers, making the per-unit costs much higher than standard integrated circuits. This makes many custom integrated circuits uncompetitive in the marketplace. Therefore, an improved system is desired which allows a variety of custom integrated circuits to be designed and manufactured as a single integrated circuit, so that start-up costs can be amortized over a plurality of different integrated circuit products. Even better would be a way to allow custom integrated circuits to replace a standard integrated circuit without requiring a complete redesign of the motherboard layout. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to a method for fabricating an integrated circuit or more concretely to a semiconductor circuit having a matrix device (including an electro-optic display and semiconductor memory) having a matrix structure and a MOS or MIS (metal-insulator-semiconductor) type field effect element (hereinafter generally referred to as a MOS type element) as a switching element and characterized in its dynamic operation such as a liquid crystal display device and dynamic RAM (DRAM) and a driving circuit therefor or an integrated driving circuit like an image sensor. The present invention particularly relates to a device employing a thin film semiconductor element such as a thin film semiconductor transistor or the like which is formed on an insulating surface as a MOS type element and to a device having a thin film transistor whose active layer is formed by crystal silicon.
2. Description of the Related Art
Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate type field effect transistor (TFT) has been fabricated by crystallizing an amorphous silicon film formed by a plasma CVD or thermal CVD method within such an apparatus as an electric furnace for many hours of more than 24 hours at a temperature more than 600xc2x0 C. The many hours of heat treatment has been required in order to obtain sufficient characteristics such as a high field mobility and high reliability.
However, such conventional method has many problems. One of the problems is that its throughput is low and accordingly, a product cast becomes high. For example, if it takes 24 hours for the crystallization process and if it takes two minutes of processing time per sheet of substrate, 720 substrates must be processed in the same time. However, a tube furnace normally used can process 50 sheets of substrates at most in one time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per sheet. That is, in order to process one sheet in 2 minutes, 15 reaction tubes must be used. It means that a scale of investment must be increased and that because the investment is greatly depreciated, it cannot but be reflected in the product cost.
Another problem lies in the temperature of the heat treatment. Normally, substrates used for fabricating a TFT are roughly divided into those composed of pure silicon oxide such as silica glass and non-alkaline boro-silicated glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among them, the former has no problem in terms of temperature because it has an excellent heat resistance and can be handled in the same manner with the wafer process of normal semiconductor integrated circuits. However its cost is high and increases exponentially as the substrate area increases. Accordingly, it is used only for TFT integrated circuits having a relatively small area.
On the other hand, non-alkaline glass has a problem in terms of heat resistance, though its cost is sufficiently low as compare to that of silica glass. Because its strain point is generally around 550 to 650xc2x0 C., or less than 600xc2x0 C. in case of a readily available material, such problems as irreversible shrinkage and warp are caused on the substrate in a heat treatment at 600xc2x0 C. and it is remarkable in such a substrate whose diagonal distance exceeds 10 cm. From above reasons, it has been considered to be indispensable to keep the heat treatment conditions under 550xc2x0 C. and within 4 hours to reduce the cost in crystallizing silicon semiconductor films. It is then an object of the present invention to provide a semiconductor fabricating method that clears such conditions and a semiconductor device fabricating method using such a semiconductor.
Lately, a study on an insulated gate type semiconductor device having a thin film active layer (or called as an active region) has been conducted. Especially, a thin film insulated gate transistor or so-called a thin film transistor (TFT) has been fervently studied. They are formed an a transparent insulating substrate to use to control each picture element and to drive its matrix in a display device such as a liquid crystal display having a matrix structure or to use as a driving circuit of an image sensor formed similarly on an insulating substrate. They are categorized as an amorphous silicon TFT or crystalline silicon (or called as polycrystalline silicon) TFT depending on a material and crystal state of a semiconductor used.
Lately, a study to use a material which presents an intermediate state between crystalline silicon and amorphous is also being conducted. Although the intermediate state is being discussed, all those which reached to some crystal state by any thermal process (such as by annealing at a temperature more than 450xc2x0 C. by irradiating strong energy such as laser light) shall be called as crystalline silicon in this specification.
A crystalline silicon TFT is used also in a monocrystal silicon integrated circuit as a so-called SOI technology and it is used as a load transistor for example in a highly integrated SRAM. In this case, however, an amorphous silicon TFT is rarely used.
Further, a very high speed operation is possible in a semiconductor circuit on an insulating substrate because there is no capacitive coupling between the substrate and wires, so that a technology to use it as a very high speed microprocessor or very high speed memory is being proposed.
Generally, a field mobility of a semiconductor in an amorphous state is small and accordingly, it cannot be used for a TFT requiring a high speed operation. Furthermore, because a field mobility of P-type is remarkably small in an amorphous silicon, a P-channel type TFT (a TFT of PMOS) cannot be fabricated and accordingly, a complementary MOS circuit (CMOS) cannot be formed by combining with a N-channel type TFT (a TFT of NMOS).
However, a TFT formed by an amorphous semiconductor has an advantage that OFF current is small. Then it is utilized in the use in which a very high speed operation is not required, only one conductive type will do and a TFT having a high charge retaining ability is required such as transistors of an active matrix of a liquid crystal display having a small matrix scale. However, it has been difficult to use the amorphous silicon TFT for an advanced application such as a liquid crystal display having a large scale matrix. Further, it could not be used naturally for peripheral circuits of a display and for a driving circuit of an image sensor which require a high speed operation.
On the other hand, a crystalline semiconductor has a field mobility larger than that of the amorphous semiconductor and accordingly, a high speed operation is possible. For example, such a large value as 300 cm2/Vs has been obtained as a field mobility in a TFT using a silicon film re-crystallized by laser annealing. It is an extremely large value considering that a field mobility of a MOS transistor formed on a normal monocrystal silicon substrate is around 500 cm2/Vs. Whereas an operation speed of the MOS circuit on the monocrystal silicon is limited by a parasitic capacity between the substrate and wires, there is no such limit in terms of the TFT using crystallized silicon film because it is formed on the insulating substrate. Accordingly, a remarkable high speed operation is being expected to be achieved in such TFT.
Further, it is possible to form a CMOS circuit by the crystalline silicon because not only a NMOS TFT but also a PMOS TFT can be similarly obtained. For example, among liquid crystal displays in an active matrix system, one having a so-called monolithic structure in which not only the active matrix section but also peripheral circuits (such as a driver) are constructed by a CMOS crystalline silicon TFT is known. The TFT used in the aforementioned SRAM is what this point is noticed, wherein the PMOS is constructed by the TFT as a load transistor.
Furthermore, whereas it is difficult to form a source/drain region by such a self-aligning process as those used in monocrystal IC technology in a normal amorphous TFT and a parasitic capacity caused by the geometrical overlap of a gate electrode and the source/drain region causes a problem, the crystalline silicon TFT has such an advantage that a parasitic capacity can be remarkably suppressed because the self-aligning process can be adopted.
However, a leak current of the crystalline silicon TFT when no voltage is applied to the gate (non-selection time) is great as compare to that of the amorphous silicon TFT, and such countermeasures have been taken that an auxiliary capacity is provided to compensate the leak current and that two TFTs are connected in series to reduce the leak current when it is used in a liquid crystal display.
For example, a method to form an amorphous silicon and to irradiate laser selectively on it to crystallize only a peripheral circuit has been proposed for forming the peripheral circuit of polysilicon TFTs having a high mobility monolithically on the same substrate while utilizing a high OFF resistance of the amorphous silicon TFT.
Presently, however, its yield is low due to a problem of reliability of the laser irradiating process (such as a bad homogeneity of the irradiated energy within the irradiated surface), so that a method to construct a matrix by amorphous silicon TFTs and to construct driving circuits by connecting monocrystal integrated circuits by a TAB method or the like is being adopted in the end. However, this method requires a more than 0.1 mm of pixel pitch from the physical restriction in the connection and its cost becomes high.
The present invention is intended to solve such difficult problems, but it is not desirable to complicate the process and to lower its yield or to increase its cost for that end. What the present invention intends is to fabricate two kinds of TFTs, i.e. a TFT in which a high mobility is required and a TFT in which a leak current is required to be low, readily and discriminately while keeping mass-producibility and while minimizing changes of its process.
Further, it is another object of the present invention to reduce a difference between the mobility of the NMOS and of the PMOS in the CMOS circuit. The reduced difference between the NMOS and PMOS allows to increase a degree of freedom in designing the circuit.
Semiconductor circuits to which the present invention is applied are not universal. That is, the present invention is suited for an active matrix circuit for displaying images by utilizing such materials which change transmittivity or reflectivity of light by an effect of electric field, by sandwiching those materials between electrodes facing to each other and by applying the electric field between those electrodes such as a liquid crystal display; a memory device for holding memory by storing charge in capacitors such as DRAM; a circuit having a dynamic circuit such as a dynamic shift register which drives the next circuit by capacitors of MOS structure portion of MOS transistors or other capacitors; and a circuit having a digital circuit and a circuit for controlling analog signal outputs such as a driving circuit of an image sensor. The present invention is suited especially to a circuit in which dynamic circuits and static circuits are mixedly mounted.
The present invention is characterized in that a crystalline silicon film is obtained by forming island film, dots, particles, clusters or lines containing a material selected from the group consisting of nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold and silver and a combination thereof on or under the silicon film which is in an amorphous state or in a random crystal state (e.g. a state in which portions having a good crystallinity and amorphous portions are mixed) which can be said substantially as being in an amorphous state, and by annealing it at a temperature lower than a crystallization temperature in a mere heat treatment of normal amorphous silicon for a shorter time. This annealing may be carried out in a hydrogen, oxygen or nitrogen atmosphere. This annealing can be carried out by (1) heating for A hours in an atmosphere containing oxygen and then heating for B hours in an atmosphere containing hydrogen: (2) heating for C hours in an atmosphere containing oxygen and then heating for D hours in an atmosphere containing nitrogen: (3) heating for E hours in an atmosphere containing hydrogen and then heating for F hours in an atmosphere containing oxygen: (4) heating for G hours in an atmosphere containing hydrogen and then heating for H hours in an atmosphere containing nitrogen: (5) heating for I hours in an atmosphere containing nitrogen and then heating for J hours in an atmosphere containing oxygen: (6) heating for K hours in an atmosphere containing nitrogen and then heating for L hours in an atmosphere containing hydrogen: (7) heating for M hours in an atmosphere containing oxygen, heating for N hours in an atmosphere containing hydrogen and then heating for P hours in an atmosphere containing nitrogen: (8) heating for Q hours in an atmosphere containing oxygen, heating for R hours in an atmosphere containing nitrogen and then heating for S hours in an atmosphere containing hydrogen: (9) heating for T hours in an atmosphere containing hydrogen, heating for U hours in an atmosphere containing oxygen and then heating for V hours in an atmosphere containing nitrogen: (10) heating for W hours in an atmosphere containing hydrogen, heating for X hours in an atmosphere containing hydrogen and then heating for Y hours in an atmosphere containing oxygen (11) heating for Z hours in an atmosphere containing nitrogen, heating for Axe2x80x2 hours in an atmosphere containing oxygen and then heating for Bxe2x80x2 hours in an atmosphere containing hydrogen: or (12) heating for Cxe2x80x2 hours in an atmosphere containing nitrogen, heating for Dxe2x80x2 hours in an atmosphere containing hydrogen and then heating for Exe2x80x2 hours in an atmosphere containing oxygen.
Concerning to the crystallization of silicon film, a method to form a crystalline island film as a nucleus or seed crystal and to grow it epitaxially in solid phase (for example Japanese Patent Laid-Open No. 1-214110) has been proposed in the past. However, crystal barely grew under 600xc2x0 C. of temperature by such method. Generally silicon undergoes a process when it transfers from an amorphous state to a crystal state that molecular chains in the amorphous state are parted and after putting the parted molecules into a state that they would not couple with other molecules again, molecules are recombined into a portion of a crystal in combination with some crystalline molecules. However, energy for parting the initial molecular chains and for keeping them in the state not to couple with other molecules is great in this process and it has been blocking the crystallization reaction. In order to supply this energy, it takes several minutes with about 1000xc2x0 C. of temperature or several tens of hours with about 600xc2x0 C. of temperature. Because the time exponentially depends on the temperature (=energy), an advancement of the crystallization reaction could not be observed almost at all at less than 600xc2x0 C. or at 550xc2x0 C. for example. The concept of epitaxial crystallization in solid phase also could not give any solution to this problem.
Then the inventor of the present invention thought of lowering the blocking energy in the aforementioned process by some catalytic action which is totally different from the concept of conventional solid phase crystallization. The inventor noticed on that nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), paradium (Pd), osmium (Os), iridium (Ir), platinum (Pt), scandium (Sc), titanium (Ti), vanadium (V), chrome (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au) and silver (Ag) readily couple with silicon.
For example, the inventor noticed an that in a case of nickel, it readily turns out to be nickel silicide (NiSix, 0.4xe2x89xa6xc3x97xe2x89xa62.5) and a lattice constant of nickel silicide is close to that of silicon crystal. Then, when energy and other were simulated in a ternary system of crystal silicon-nickel silicide-amorphous silicon, it was found that amorphous silicon readily reacts at the boundary with the nickel silicide and that the following reaction is brought about:
amorphous silicon (silicon A)+nickel silicide (silicon B)xe2x88x92 greater than nickel silicide (silicon A)+crystal silicon (silicon B) (silicon A and B indicate positions of silicon)
A potential of the block off this reaction is fully low and a reaction temperature is also low. This reaction formula indicates that the reaction proceeds while converting amorphous silicon into crystal silicon by nickel. It was found that the reaction actually started at less than 580xc2x0 C. and that the reaction could be observed even at 450xc2x0 C. Though it is a matter of course, the higher the temperature, the faster the speed of the advancement of reaction was. The same effect was also recognized with other metal elements described above.
According to the present invention, a crystal silicon region is expanded by forming a film, particle or cluster containing at least one of Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag such as island, stripe, line, dot or film of nickel or other simple metal substances described above or their silicide as a starting point and by developing those metal elements from the point to surroundings along the reaction described above. By the way, oxide is not preferable as a material containing those metal elements, because oxide is a stable compound and cannot start the aforementioned reaction.
The crystal silicon expanded from a specific point has a structure close to monocrystal with good continuity of crystallinity, though it differs from the conventional solid phase epitaxial growth, so that it is convenient in using for semiconductor devices such as a TFT. However, an infinite number of crystallization starting points existed when a material containing the aforementioned metals for accelerating the crystallization such as nickel was provided homogeneously on a substrate and due to that, it was difficult to obtain a film having a good crystallinity.
A better result was obtained when a concentration of hydrogen was less in the amorphous silicon film as the starting material of this crystallization. However, because hydrogen was released as the crystallization advanced, no such a clear correlation was seen between a concentration of hydrogen within a silicon film obtained and that in the amorphous silicon film as the starting material. The concentration of hydrogen within the crystal silicon of the present invention was typically more than 0.01 atomic percent and less than 5 atomic percent.
Although Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag are used in the present invention, these materials are not generally preferable for silicon as a semiconductor material and it is necessary to remove them. In terms of nickel, because nickel silicide which reached the end of the crystallization as a result of the aforementioned reaction is easily resolved in hydrofluoric acid or hydrochloric acid or dilution of them, nickel can be reduced from the substrate by means of a treatment by those acids. Further, those metal elements can be positively reduced by treating at 400 to 600xc2x0 C. in an atmosphere containing chlorine such as hydrogen chloride, various methane chlorides (CH3Cl, CH2Cl2, CHCl3), various ethane chlorides (C2H5Cl, C2H4Cl2, C2H3Cl3, C2H2Cl4, C2HCl5) or various ethylene chlorides (C2H3Cl, C2H2Cl2, C2HCl3) after the end of the crystallization process. Especially, trichloroethylene (C2HCl3) is a material which can be easily used. A concentration of Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au and Ag in the silicon film of the present invention was typically more than 0.005 atomic percent and less than 1 atomic percent.
In using the crystal silicon film fabricated according to the present invention for a semiconductor element such as a TFT, it is not preferable to provide the semiconductor element on the end of the crystallization (it is also a portion where the crystallization started from a plurality of starting points hit each other) because a large grain boundary (a portion where crystallinity is discontinued) exists and the concentration of metal elements which accelerate the crystallization such as nickel is high there as it is obvious from the description above. Accordingly, a pattern of a coating film containing the metal elements which become the starting point of the crystallization and accelerate it such as nickel and a pattern of the semiconductor element must be optimized in forming the semiconductor element utilizing the present invention.
In the present invention, roughly there are two methods for patterning the metal elements which accelerate the crystallization. A first method is to selectively form a film or the like of those metals before forming an amorphous silicon film and a second method is to selectively form a film or the like of those metals after forming the amorphous silicon film.
The first method can be implemented by using a normal photolithographic means or lift-off means. The second method is complicated more or less. That is, if the film or the like of the metals which accelerate the crystallization is formed adhering to the amorphous silicon film, the metal and the amorphous silicon partially react each other producing silicide when forming the film. Therefore, It is necessary to fully etch such silicide layer when patterning after forming the metal film or the like.
In the second method, the lift-off method is relatively easily carried out. In this case, organic materials such as photoresist or non-organic materials such as silicon oxide or silicon nitride may be used as a masking material. A processing temperature must be taken into consideration in selecting the masking material. Further, because a masking action differs depending on materials, a full attention needs to be paid on it. Especially, a film of silicon oxide or silicon nitride formed by various CVD methods has many pinholes and the crystallization may advance from an unexpected section if the film is not fully thick.
Generally, patterning is implemented after forming the coating film using those masking materials to selectively expose the surface of amorphous silicon. Then the metal film or the like which accelerates the crystallization is formed.
What must be taken care of in the present invention is the concentration of metal elements within the silicon film. Although nothing is better than that its amount is small, it is also important for the amount to be always kept constant. It is because a considerable fluctuation in the degree of crystallization is brought about per lot in the manufacturing site if the amount of the metal element fluctuates significantly. It becomes more difficult to reduce the fluctuation of the amount especially when the amount of the metal element is required to be less.
In the first method, because the metal film or the like selectively formed is coated by the amorphous silicon film, it cannot be taken out later to adjust its amount. In terms of the amount of metal element required in the present invention, the thickness of the metal film or the like is so thin as several to several tens angstrom, so that it is difficult to form the film with a good reproducibility.
The same also applies to the second method. However, there is a room of improvement in the second method as compare to the first method because the metal film or the like which accelerate the crystallization exists on the surface in this method. That is, a fully thick metal film is formed and a heat treatment (pre-annealing) is implemented at a temperature lower than an annealing temperature before annealing to react a part of the amorphous silicon film and the metal film and to produce silicide. Then the metal film which did not react is etched. Although it depends on a metal used, there is no problem particularly in terms of Ni, Fe, Co, Ti and Cr because there is an etchant in which an etching rate of the metal film and the silicide is fully large.
In this case, a thickness of the silicide layer obtained is determined by the temperature and time of the heat treatment (pre-annealing) and the thickness of the metal layer has almost nothing to do with it. Due to that, the very small amount of metal element introduced in the amorphous silicon film can be controlled.
The present invention also utilizes that there is a difference in degrees of crystallization when the surface of semiconductor is covered by a coating film (cover film) of silicon oxide or silicon nitride and when not covered when crystallizing a crystalline silicon TFT in a temperature at 450 to 1000xc2x0 C. or preferably at 500 to 800xc2x0 C. in an atmosphere containing oxygen, hydrogen or nitrogen. Such atmosphere can be an atmosphere containing oxygen, atmosphere containing hydrogen, atmosphere containing nitrogen, atmosphere containing oxygen and hydrogen, atmosphere containing oxygen and nitrogen, atmosphere containing hydrogen and nitrogen or atmosphere containing oxygen, hydrogen and nitrogen. The aforementioned crystallization can be carried out by (1) heating for A hours in the atmosphere containing oxygen and then heating for B hours in the atmosphere containing hydrogen: (2) heating for C hours in the atmosphere containing oxygen and then heating for D hours in the atmosphere containing nitrogen: (3) heating for E hours in the atmosphere containing hydrogen and then heating for F hours in the atmosphere containing oxygen: (4) heating for G hours in the atmosphere containing hydrogen and then heating for H hours in the atmosphere containing nitrogen: (5) heating for I hours in the atmosphere containing nitrogen and then heating for J hours in the atmosphere containing oxygen: (6) heating for K hours in the atmosphere containing nitrogen and then heating for L hours in the atmosphere containing hydrogen: (7) heating for M hours in the atmosphere containing oxygen, heating for N hours in the atmosphere containing hydrogen and then heating for P hours in the atmosphere containing nitrogen: (8) heating for Q hours in the atmosphere containing oxygen, heating for R hours in the atmosphere containing nitrogen and then heating for S hours in the atmosphere containing hydrogen: (9) heating for T hours in the atmosphere containing hydrogen, heating for U hours in the atmosphere containing oxygen and then heating for V hours in the atmosphere containing nitrogen: (10) heating for W hours in the atmosphere containing hydrogen, heating for X hours in the atmosphere containing nitrogen and then heating for Y hours in the atmosphere containing oxygen: (11) heating for Z hours in the atmosphere containing nitrogen, heating for Axe2x80x2 hours in the atmosphere containing oxygen and then heating for Bxe2x80x2 hours in the atmosphere containing hydrogen: or (12) heating for Cxe2x80x2 hours in the atmosphere containing nitrogen, heating for Dxe2x80x2 hours in the atmosphere containing hydrogen and then heating for Exe2x80x2 hours in the atmosphere containing oxygen. It is particularly preferable (4) to heat for G hours in the atmosphere containing hydrogen and then to heat for E hours in the atmosphere containing nitrogen, (5) to heat for I hours (4 hours for example) in the atmosphere containing nitrogen and then to heat for J hours (1 hour for example) in the atmosphere containing oxygen, or (6) to heat for K hours (4 hours for example) in the atmosphere containing nitrogen and then to heat for L hours (1 hour for example) in the atmosphere containing hydrogen. Generally the crystallinity is good and as a natural consequence, a TFT having a high mobility can be obtained when the cover film exists. However, generally its leak current becomes significant. On the other hand, the one having no cover film has an advantage that the leak current is low, though the crystallinity is not good and its mobility is low because it turns out be amorphous state depending on temperature.
This characteristic is considered to be governed by the existence of hydrogen, oxygen or nitrogen within the atmosphere infiltrated to the active layer. This crystallization may be carried out by implementing it in nitrogen for example and then in hydrogen or oxygen. Thus TFTs having different characteristics may be formed on the same substrate in the same time and in the same process. For example, the former high mobility TFT can be used as a driving circuit of a matrix and the latter low leak current TFTs can be used as TFTs in the matrix portion.
Or a mobility in the NMOS can be relatively reduced as compare to that in the PMOS and a difference between the both can be almost eliminated in the optimum condition by not providing the cover film on the NMOS region and providing it on the PMOS region in the CMOS circuit.
The temperature of the thermal crystallization is an important parameter and the crystallinity of a TFT is determined by the temperature in the present invention. Generally, the temperature of thermal annealing is restricted by a substrate and other materials. As far as the restriction of a substrate material is concerned, a thermal annealing of up to 1100xc2x0 C. is possible when silicon and silica are used as a substrate. However, it is desirable to anneal at less than 650xc2x0 C. of temperature in a case of Corning 7059 glass which is a typical non-alkaline glass. However, it must be set considering characteristics required for each TFT, other than the substrate, in the present invention from the aforementioned reasons. When the annealing temperature is high, generally a growth of crystal of TFT advances, the mobility is increased and the leak current increases. Accordingly, the annealing temperature should be 450 to 1000xc2x0 C. or preferably 500 to 800xc2x0 C. in order to obtain TFTs having different characteristics on the same substrate like the present invention.
One such example of the present invention is that in a display section of an active matrix circuit of a liquid crystal display or the like, polysilicon TFTs are used as switching transistors and that no cover film is provided in the active matrix region when crystallizing an active layer and on the other hand the cover film is provided on the peripheral circuit region to turn the former into low leak current TFTs and the latter into high mobility TFTs.
FIG. 8(A) shows a conceptual drawing of a device having a display circuit section (active matrix) and a driving circuit (peripheral circuit) therefor as described above. In the figure, a display device is shown in which a data driver 101 and gate driver 102 are arranged, an active matrix 103 having TFTs is arranged in the middle and those driver sections and the active matrix are connected through gate lines 105 and data lines 106 an an insulating substrate 107. The active matrix 103 is an aggregate of picture element cells 104 having a NMOS or PMOS TFT (PMOS in the figure).
For a CMOS circuit of the driver section, a concentration of impurities such as oxygen, nitrogen and carbon in the active layer is desirable to be less than 1018 cmxe2x88x923 or preferably less than 1017 cmxe2x88x923 in order to obtain a high mobility. As a result, a threshold voltage of the TFT was 0.5 to 2 V in the NMOS and xe2x88x920.5 to xe2x88x923 V in the PMOS for example and a mobility was 30 to 150 cm2/Vs in the NMOS and 20 to 100 cm2/Vs in the PMOS.
On the other hand, an auxiliary capacity could be reduced and further be totally eliminated in the active matrix section by using single or a plurality of elements in series having as low as about 1 pA of leak current with 1 V of drain voltage.
A second example of the present invention relates to a semiconductor memory. A semiconductor memory device by means of monocrystal ICs has already reached to its limit in terms of speed. Although it is necessary to increase a current capacity of transistors in order to operate it in a higher speed, it causes a further increase of power consumption and it cannot but be dealt by increasing driving voltage so long as a capacity of capacitors cannot be increased further for a DRAM which carries out memory operations by storing charge in the capacitors.
One reason why it is said that monocrystal ICs have reached its speed limit is because a large loss is brought about by a capacity of the substrate and wires. It is possible to drive in fully high speed without increasing power consumption if an insulator is used for the substrate. From such a reason, an IC having a SOI (semiconductor on insulator) structure has been proposed.
A circuit arrangement of the DRAM is almost the same with that of the aforementioned liquid crystal display device in a case of 1 Tr/cell structure and in a DRAM having a structure other than that (for example 3 Tr/cell structure), no cover film is provided in a memory bit section when crystallizing an active layer and on the other hand, a cover film is provided on a region of a driving circuit because it is required to operate in fully high speed in the same manner with the case of the aforementioned liquid crystal display device to turn the former into low leak current TFTs and the later into high leak current TFTs.
The basic block structure of such semiconductor memory device is the same with that shown in FIG. 8A. For example, in the DRAM, the reference numeral (101) can be a column decoder, (102) a row decoder, (103) a memory elements section, (104) a unit memory bit, (105) bit lines, (106) word lines, and (107) an (insulating) substrate.
A third application example of the present invention is a driving circuit for an image sensor or the like. FIG. 8(B) shows an example of a one bit circuit of an image sensor, wherein a flip-flop circuit 108 and a buffer circuit 109 are normally constructed by a CMOS circuit and are required to respond in such high speed that they can follow up high speed pulses applied to a scan line. On the other hand, a TFT 110 in a signal output stage plays a role of a dam that discharges a charge accumulated in a capacitor by a photodiode to a data line by receiving a signal from the shift register sections 108 and 109.
Such TFT 110 is required not only to respond in high speed but also to have less leak current. Accordingly, the region of the circuits 108 and 109 is crystallized by providing a cover film to turn it into a high mobility TFT and the region of the TFT 110 on the other hand is crystallized without providing cover film to turn it into a low leak current TFT in such a circuit.
In the present invention, silicon oxide, silicon nitride or silicon oxinitride (SiNxOy) may be used as the cover film. Although the thicker the cover film, the better the covering ability is, the thickness must be determined considering a mass-producibility and covering ability thereof because it takes a time to form a thick film. Though the covering ability differs depending on a quality of film, typically the thickness must be more than 20 nm for a silicon oxide film and more than 10 nm for a silicon nitride film. The thickness is desired to be 20 to 200 nm for both of the silicon oxide film and the silicon nitride film when considering mass-producibility and reliability.
The above and other advantages of the present invention will become more apparent in the following description and the accompanying drawings in which like reference numerals refer to like parts throughout several views. | {
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1. Field of the Invention
The present invention relates to techniques for communicating optical signals. More specifically, the present invention relates to an optical device with a thermally tunable optical waveguide.
2. Related Art
Wavelength division multiplexing (WDM) is widely used to communicate modulated data at different carrier wavelengths on a common optical waveguide. WDM can overcome optical-fiber congestion, which is a potential problem in optical modules that include parallel optical transceivers with one channel per optical fiber. In particular, by significantly reducing the number of optical fibers per optical module, WDM multiplexing can simplify optical modules, thereby reducing their cost and size.
In dense WDM (DWDM), a narrow spacing between adjacent wavelengths is used. This is typically achieved by modulating data directly onto a highly stable optical carrier, and then combining multiple carriers in an optical fiber. DWDM allows a large number of channels to be accommodated within a given wavelength band, and thus offers high performance.
In DWDM a variety of optical devices are used as: modulators, multiplexers (such as add filters), de-multiplexers (such as drop filters), filters and switches. In order to compensate for fabrication variation, temperature variation and/or laser wavelength drift, these optical devices are typically phase-tuned to a particular wavelength for a given channel. Depending on the system requirements, a tuning range of at least 180° may be needed.
Thermal tuning is a popular tuning technique because it provides the ability to produce large phase shifts. Existing thermal tuning techniques include direct heating (which is implemented by doping in an optical waveguide) and indirect heating (in which a heater is proximate to the optical waveguide). Typically, the direct-heating technique is more energy-efficient than indirect heating, but it can prevent the optical waveguide from performing additional functions (because of the constraint on the doping density), and it can introduce additional optical losses due to free-carrier absorption (which can degrade the quality factor of an optical resonator).
In principle, optical devices can be made on silicon substrates, because silicon provides many benefits for optical communication. For example, the high index-of-refraction contrast between silicon and silicon dioxide can be used to create sub-micron waveguides to confine light with spatial densities that are up to 100× larger than in a single-mode optical fiber. Furthermore, by using a silicon-on-insulator (SOI) technology, a silicon waveguide can be surrounded by silicon dioxide on all four sides, which facilitates low-loss, on-chip waveguides and active devices (such as detectors and modulators). Silicon-based optical devices can be used to implement a wide variety of optical components for use in WDM communication. These silicon-based optical devices offer numerous advantages, including: miniaturization, low-energy modulation, the ability to integrate with other devices in silicon, and/or the ability to leverage the large, existing silicon manufacturing infrastructure.
Unfortunately, there are problems associated with silicon-based optical devices. A notable problem is the high thermal conductivity of silicon. While this helps remove the heat dissipated by electrical circuits, it can make it more difficult to thermally tune a silicon-based optical device. In particular, because the operating wavelength of a silicon-based optical device (such as the resonant wavelength of an optical resonator) strongly depends on temperature, the operating wavelength is typically tuned using either direct or indirect heating to change the operating temperature of the silicon-based optical device. However, the high thermal conductivity of silicon results in excessive thermal coupling to the surrounding environment. Consequently, thermal tuning of silicon-based optical devices often consumes a disproportionately large amount of energy (typically, 50-100 mW for a phase shift of 180°). This high power consumption can offset the advantages provided by silicon, and makes it more difficult to use silicon-based optical devices to implement optical communication (such as WDM) in computing systems (especially in systems that have multiple instances of the optical devices).
Hence, what is needed is an optical device that can be thermally tuned without the above-described problems. | {
"pile_set_name": "USPTO Backgrounds"
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As semiconductor technology continues to inch closer to practical limitations in terms of increases in clock speed, architects are increasingly focusing on parallelism in processor architectures to obtain performance improvements. At the chip level, multiple processing cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations. Pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
These various techniques for improving execution unit performance, however, do not come without a cost. Parallelism adds complexity, often requiring a greater number of logic gates, which increases both the size and the power consumption of such execution units. Coupling these techniques with the general desire to increase performance through other techniques, such as increased switching frequency, the power consumption of complex, high performance execution units continues to increase, despite efforts to reduce such power consumption through process improvements. Excessive power consumption can present issues for portable or battery powered devices, but more typically, excessive power consumption presents issues for nearly all electronic circuits due to the generation of heat, which often requires elaborate cooling systems to ensure that a circuit does not overheat and fail.
Chip-wide control over power consumption is often used in electronic circuits such as those used in laptop computers or other portable devices, typically by throttling down the clock rate or frequency of the circuit to reduce power consumption and the generation of heat. In addition, power consumption may also be reduced in some instances by temporarily shutting down unused circuits on a chip, including, for example, entire execution units. In all of these instances, however, throttling back the power consumption of the circuit usually results in lower performance in the chip. Furthermore, the circuit characteristics that define the overall power consumption of such circuits, e.g., cycle time, voltage, logic area, capacitance, etc., are most often designed to meet a maximum performance target.
Particularly for complex System on Chip (SOC) designs, increasingly complex logic circuitry is being incorporated into individual chips, and in many instances, it costs more power per bit to move the bit from memory to the central processing unit (CPU), than it does to perform the desired computation. As a result, improved power reduction mechanisms are required for moving data around on, and off, chip. Additionally, many features once unique to digital signal processors (DSPs) are increasingly being implemented on general purpose processors to reduce cost by eliminating the need for separate DSP chips in a system and to increase performance by eliminating the need to move data between a DSP chip and the CPU.
However, many algorithms more traditionally performed by DSPs, e.g., Fast Fourier Transforms (FFT), do not perform as well using traditional general purpose processors or CPUs. Although some features added to more recent general purpose processor designs, e.g., SIMD execution units and predication, have significantly improved performance, the power consumption of general purpose processing units performing these algorithms is still typically much higher than that of DSP chips specifically tailored for those algorithms. This is primarily because general purpose processing units typically incorporate large blocks of logic such as multiple cache memories, multiple threads of execution, multiple execution units, etc. that are intended to improve performance generally for most workloads. However, for many DSP algorithms, this logic does very little to improve performance, and thus the additional power consumption of this logic is often effectively wasted when executing such DSP algorithms in a general purpose processor.
Therefore, a continuing need exists in the art for improved manners of reducing power consumption in an integrated circuit, particularly in connection with executing DSP algorithms and the like. | {
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The present invention relates to an improved carrier particle for use with a toner in an electrostatic copying process. Such processes are now commonly used by laser printers and photocopy machines.
Electrostatic processes typically use developers that have two components: toner particles and carrier particles. The carrier particles impart a triboelectric charge to the toner particles with a proper polarity and magnitude to insure that the toner particles are preferentially attracted to desired image areas on a latent image field. The magnitude of the triboelectric charge is important. If the charge is too low, the attractive force between the carrier particles and the toner particles will be too weak, resulting in "background," that is, the transfer of too much toner from the carrier. If the charge is too high, not enough toner is transferred from the carrier, resulting in low print density.
Additionally, it is important for the carrier particles to have low surface energy. Low surface energy makes it difficult for the toner particles to permanently adhere to the carrier particles. Permanent adhesion of toner particles to carrier particles impairs the normal triboelectric charging of the remaining toner particles, resulting in decreased output quality and shortened developer life.
Therefore, it is desirable for carrier particles to have a strong triboelectric charge so that toner particles can be attracted and deposited in sufficient quantities to achieve high print density while at the same time resisting the permanent adhesion of toner particles so that developer life is increased and output quality remains stable and good over the life of the developer.
The present invention provides the aforementioned desirable characteristics while avoiding the undesirable characteristics of prior art carrier particles. | {
"pile_set_name": "USPTO Backgrounds"
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Highwall mining is a form of surface mining, in which spaced apart tunnels (sometimes called holes or entries) are cut into an exposed face of the seam at predetermined intervals to create the pillars for supporting the overburden. A typical highwall mining system is comprised of a cutter (or miner module), a conveying system and a main miner (or launch module). The cutter cuts into a mineral seam and is forced into the cut by pushing a series of conveyor sections, also called “push beams” or “conveyor pans.”
It is common in the art of highwall mining to use push beams to form a part of a highwall mining system. Generally, push beams are essentially boxes that contain a type of conveying mechanism, such as augers, that move the minerals out of the mine. The basic approach is shown and described in U.S. Pat. No. 4,014,574 to Todd.
To provide an efficient and effective highwall mining system, the push beams must interconnect in such a way as to withstand the substantial forces present during a typical mining operation. Specifically, the push beams must be rigid in the horizontal plane to prevent the cutter from going off target and breaking through into the last cut. This is normally accomplished by interconnecting the push beams together using “dog-bone” couplers that were retained using separate removable pins as shown in U.S. Pat. No. 6,035,997 to Heninger et al. or like mechanisms, such as nut and bolt combinations.
Although removable pins or like mechanisms may be used to retain the dog-bone shaped couplers interconnecting the push beams, limitations remain. Specifically, in the harsh conditions often encountered in the mining operation, these types of arrangements are susceptible to becoming damaged. Further, the removable pins or like mechanisms are easily lost or misplaced, which is troublesome to the mining operation for obvious reasons, such as cost and delay.
Past push beams used in highwall miners are also typically interconnected with abutting vertical faces such that relative articulation was not possible (or was only possible to a very limited extent, such as the result of part tolerances). Even when such limited articulation was possible, the abutting ends of the push beams were generally square and thus prevented any articulation when under compressive loading (see the '574 patent to Todd; col. 14, line 68 to col. 15, line 1, which states that the gap between the push beam couplers “allows for a slight flexing movement between the modules . . . when they are not under a longitudinal compressive load.”) (emphasis added). This inability to freely articulate, especially during the application of a longitudinal compressive load, may create a significant problem when the entry is uneven or undulating, since the push beams may “bind up” and become stuck.
Accordingly, the art of mining has a need for an improved arrangements for coupling conveyor sections. Specifically, a need exists for improved latching mechanisms for interconnecting the conveyor sections that minimizes damage in harsh mining conditions and reduces costs and delays due to lost or misplaced parts. A further need exists for a coupling that permits adjacent conveyor sections to articulate in a smooth and controlled manner. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
The present invention pertains to lighting, and more particularly to fluorescent bench worklights.
2. Description of the Related Art
Fluorescent bulb-type lamps that include a threaded connector that screw into a complimentary-shaped threaded connector are relatively common. Such lamps, called mogul based lamps, have an advantage over standard incandescent bulbs because they are more energy efficient.
Heretofore, fluorescent bench lights use two to four 25 to 40 watt fluorescent tubes. The ends of the tubes connect to the slot connectors located near the opposite ends of the light's housing. Depending on the number of tubes used in the fixture, one or more electrical ballasts may be used that provides sufficiently high starting currents to initially illuminate the bulbs.
The main drawback with standard fluorescent tubes is that they are insufficiently bright for illuminating a workbench. Another drawback with such tubes is that when one of the tubes or ballasts break or malfunction, the entire light no longer operates.
What is needed is a workbench light fixture that uses low energy fluorescent light with greater brightness that does not stop operating when one of the lights breaks or malfunctions. | {
"pile_set_name": "USPTO Backgrounds"
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In an era when lower data rates and smaller data volumes (or sizes) were required by users, a single storage unit may have been sufficient to accommodate all of a user's data needs. But, in recent years, reducing data reading/writing periods and/or securing larger-capacity storage spaces have become important, for instance, in order to process larges quantities of multimedia data and/or real-time data. In particular, the physical limitations of storage materials may make it difficult to achieve high frequency operations and/or larger capacities for single storage units. To overcome such limitations, multi-channel memory systems have been proposed, which include a plurality of similar and/or different memory devices coupled to one another.
Today, various kinds of memory devices may be used as storage units, e.g., hard disk drives (HDDs) configured to store and read data by rotating aluminum disks coated with magnetic materials, optical disks, such as CD-ROMs or digital versatile disks (DVDs) configured to store information such as voice, images, or characters, and/or nonvolatile memories, such as flash memories.
Some such memory devices may frequently encounter errors or malfunctions while reading data, for example, due to the physical limitations thereof. For example, in hard disk drives, closer track spacing, the use of weaker signals to avoid interference, and/or increased rotation speeds may be used to meet ever-increasing storage demands. However, as the limits of such technologies are pushed, errors may occur more frequently. Furthermore, errors and/or failures in the hard disks may be caused by particles floating therein, electrostatic discharge (ESD), temperature, and/or humidity related effects while reading data therefrom.
Flash memories are nonvolatile devices that may retain data even without a power supply. Although not as fast as dynamic memories that may be used as main memories in personal computers, flash memory devices may offer advantages over hard disks in reading rate and/or resistance to external impact. As such, flash memories may be employed in mobile or portable devices that are operated by batteries. Another advantage of flash memory may be durability.
Flash memory may be used as nonvolatile storage units for computing systems, and may be capable of electrically erasing and rewriting data. In contrast to electrically erasable and programmable read-only memories (EEPROMs), flash memories may erase and/or write data in units of blocks and/or sectors. Due to lower costs than EEPROMs, flash memory may be used in applications that require large-capacity, nonvolatile, solid-state storage units. Typically, flash memory may be used in digital music players, digital cameras, and/or mobile phones. Moreover, flash memory may be used in universal serial bus (USB) drives for storing and transferring data between computing systems.
In a flash memory device, data may be retained in a memory cell array formed of floating gate transistors called memory cells, each of which stores bit information. For a single-level-cell (SLC) flash memory device, data stored in a unit memory cell may be sensed based on threshold voltage distributions corresponding to respective data states ‘1’ and ‘0’. For example, when a reference voltage is applied to a control gate of the memory cell, the data (‘1’ or ‘0’) stored in the cell may be determined based on current flow through the memory cell. However, since the actual threshold voltage distributions of the memory cells may not be within designed voltage ranges, errors may result from data readings. This phenomenon may become more serious, for example, due to charge loss or leakage, time lapse, temperature elevation, capacitive coupling by programming adjacent memory cells, reading adjacent memory cells, cell defects, and so forth. | {
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This invention relates to the field of data processing systems. More particularly, this invention relates to the field of data processing systems having a plurality of execution mechanism for executing program instructions and between which a selection may be made as to which execution mechanism is active to execute the stream of program instructions at a given time.
It is known to provide data processing systems, such as those employing the techniques of the big.LITTLE processors designed by ARM Limited of Cambridge, England which incorporate multiple execution mechanisms among which an active execution mechanism is selected. These processors typically include a low performance and low power processor core together with a high performance and high power processor core. When the processing workload is such that a high performance is not required, then the processing is switched so as to be performed by the more energy efficient low power processor core. Conversely, when the processing workload is such that high performance is necessary, then the workload is switched to the high performance processor core. The granularity with which the switching is performed in such systems is large as it can take many hundreds and thousands of processing cycles to move the processor state between the small lower powered processor core and the large high performance processor core.
While the above systems may be used with advantage, it has been noted that in many real life processing loads the changes between a requirement for high performance versus low power occur at a finer level of granularity than may be dealt with in a system in which when one of the cores shut down, the entire processor state is transferred to the other processor core and then that other processor core started. This restricts the benefit which can be achieved. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
The present invention relates to a displaying apparatus, and more particularly to a liquid crystal display and driving method thereof.
2. Background of the Related Art
Generally, a liquid crystal display (LCD) includes a thin film transistor (TFT) liquid crystal display (TFT-LCD) panel, a backlight unit, and a driver. The TFT-LCD panel may have degradations as follows: first, degradation of characteristic values from standard design due to process deviations; second, degradation due to dust, poor cleaning at a film surface, and the like; and, third, degradation of characteristic variations due to static electricity and breakdown of thin film transistors or liquid crystal cells.
One of the degradations occurring in a TFT-LCD panel is the irregularity of combining a first substrate with an opposed second substrate, which results in reducing the sharpness of a displayed video or in leaking light when failing to meet the design margin.
Reference will now be made in detail to an LCD according to a related art, examples of which are illustrated in the accompanying drawings.
FIG. 1 shows a layout of an LCD according to a related art.
Referring to FIG. 1, a liquid crystal display generally comprises a number of ‘m’ gate lines G1 to Gm arranged in a first direction with a constant interval between the gate lines; a number of ‘n’ data lines D1 to Dn arranged in a second direction perpendicular to the respective gate lines G1 to Gm with a constant interval between the data lines; a plurality of pixel electrodes (not shown in the drawing) formed as a matrix in pixel areas defined by the crossing gate and data lines respectively; and a plurality of thin film transistors for applying data signals supplied through the respective data lines to the respective pixel electrodes by being switched according to signals of the gate lines.
Further, a pair of driver integrated circuits (ICs) 14 and 15 are installed at the sides of the gate and data lines, respectively, so as to supply gate and data driving signals thereto. Namely, a pair of pads (not shown in the drawing) are formed at the ends of the gate and data lines to which the driver ICs are connected.
FIG. 2 shows cross-sectional views of the LCD taken along a line I–I′ in FIG. 1.
Referring to FIG. 2, a gate insulating layer 22 is formed on a first substrate 21. An nth data line 23 is patterned on the gate insulating layer 22. A passivation layer 24 made of an insulator is formed over an entire surface of the substrate including the nth data line 23. A transparent conductive layer of indium tin oxide (ITO) 25 for applying a voltage to the liquid crystal display is patterned on the passivation layer 24.
A black matrix 27 having predetermined spaces therein, is formed on an upper insulating substrate 26. A color filter layer 28 fills the spaces in the black matrix 27.
Unfortunately, the LCD according to the related art has some problems as follows.
The degree of alignment for the TFT and color filter substrates depends on the alignment tolerance (or margin) for combining (or assembling) the upper and lower substrates. Such combining margin is determined by the design of the respective substrates, for which precision of about several micrometers is required. Light leakage occurs at both lateral sides of the panel when the alignment between two substrates is deviated from the combining margin, thereby failing to provide desirable driving characteristics.
Namely, as shown in FIG. 2, there is no structure to block the light leakage at the right side of the nth data line 23. Therefore, light leakage occurs due to the transmitting light reaching the color filter layer. | {
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The present disclosure relates to a rotary changer for welding torches configured to automatically replace a torch component such as a cylindrical nozzle or a contact tip bar to be screwed on, and coupled to, a tip portion of the body of a welding torch for use in arc welding.
Changer assemblies for replacing torch components automatically and efficiently have been known in the art. Examples of such torch components include cylindrical nozzles and contact tip bars to be screwed on, and coupled to, a tip portion of the body of a welding torch for use in arc welding. A changer assembly of this type is disclosed, for example, in Japanese Unexamined Patent Publication No. 2002-192345.
The assembly includes a plurality of changers, each having a recess that opens at the top. Each of those changers is designed to rotate on a rotational axis to be displaced vertically by a drive motor and a gear meshing mechanism. To remove the torch component from the torch body, the welding torch is inserted into the recess with the changer kept rotating, thereby getting the recess interlocked with the torch component and rotating the torch component along with the changer to allow the torch component to get removed from the torch body. Meanwhile, to attach the torch component to the torch body, the torch component is placed in the changer such that its tip end faces downward and the torch body is gradually lowered with the changer kept rotating. In this manner, the torch component is attached onto the torch body so as to be screwed onto the tip portion of the torch body.
The changer assembly of Japanese Unexamined Patent Publication No. 2002-192345 fails to specify exactly how the recess of the changer needs to be interlocked with the torch component in order to attach and remove the component onto/from the torch body. For example, misalignment of the center axis of the torch component to be inserted into the recess with the rotational axis of the changer would allow the torch component to unintentionally contact with a portion of the changer's recess to get interlocked with the torch component, which would possibly cause deformation or damage to the recess of the changer.
In view of the foregoing background, it is therefore an object of the present disclosure to provide a rotary changer for welding torches configured to prevent a portion of the changer interlockable with the torch component from being significantly deformed or damaged while the torch component is repeatedly attached to, or removed from, the torch body. | {
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The present invention relates generally to operations performed and equipment utilized in conjunction with a subterranean well and, in an embodiment described herein, more particularly provides an electrically operated deep set safety valve.
It is sometimes desirable to set a safety valve relatively deep in a well. For example, a safety valve may be set at a depth of 10,000 ft or more. However, operating a safety valve at such depths present a variety of problems which tend to be expensive to overcome. Most offshore hydrocarbon producing wells are required by law to include a surface controlled subsurface safety valve (SCSSV) located downhole in the production string to shut off the flow of hydrocarbons in an emergency. These SCSSV's are usually set below the mudline in offshore wells. Since offshore wells are being drilled at ever increasing water depths and in environmentally sensitive waters, it has become very desirable to electrically control these safety valves to eliminate the use of hydraulic fluids and be able to set the safety valves at virtually unlimited water depths. However, because of the depth, it is difficult to deliver the electric power to operate these valves. One or more wires can be run down the well to the valves, although the number is limited by space and design considerations. Moreover, a number of downhole tools, instruments, etc. compete for the limited amount of power available through the lines.
In addition, once a valve or other device is installed downhole it is difficult to remove and replace. Should it be desired to add or modify the functionality of the downhole components, it is difficult and expensive to effect the desired change.
Moreover, in a well environment, typical pressures, temperatures, salinity, pH levels, vibration levels, etc., downhole vary and are demanding Moreover, the environment is often corrosive, including chemicals dissolved in, or otherwise carried by, the hydrocarbons or injected chemicals, such as hydrogen sulfide, carbon dioxide, etc. Thus, downhole components must be designed to withstand these conditions or isolated from the environment, such as by a sealed chamber. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field
The present disclosure generally relates to composite columnar structures, and deals more particularly with a composite tubular strut internally stiffened to maximize the strut's strength-to-weight ratio.
2. Background
Columnar structures formed of composites are used in a variety of applications because of their favorable strength to weight ratio. For example, composite tubular struts may be used in the aerospace industry as a support or brace for transferring loads in either direction along the longitudinal axis of the strut, thus placing the strut in either compression or tension. Fittings on the ends of the strut provide additional strength at the points of attachment of the strut to a structure.
Composite struts are known in which the end fittings, often fabricated from metal, are attached to a tubular composite body by bonds rather than by fasteners. The tubular bodies have a substantially constant cross section and a relatively thick wall in order to meet design load criteria. The fittings may be attached to the ends of the tubular body by double step joints which may result in greater than desired peel forces being applied to inner and outer plies of the tube wall. Fabrication of these types of composite struts is both labor intensive and time consuming because of the need for precise hand layup of plies, as well as the need for two autoclave cure cycles for separately curing the inner and outer plies of the joint.
Accordingly, there is a need for a tubular composite strut that may be more quickly fabricated and using less skilled hand labor. There is also a need for a composite strut as described above which has an improved strength-to-weight ratio. | {
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The present invention relates to a recombinant yeast cell having the ability to produce a desired fermentation product, to the construction of said yeast cell by genetic modification and to a process for producing a fermentation product wherein said yeast cell is used.
Ethanol production by Saccharomyces cerevisiae is currently, by volume, the single largest fermentation process in industrial biotechnology. A global research effort is underway to expand the substrate range of S. cerevisiae to include lignocellulosic hydrolysates, in particular hydrolysed lignocellulosic biomass from non-food feedstocks (e.g. energy crops and agricultural residues, forestry residues or industrial/consumer waste materials that are rich in cellulose, hemicellulose and/or pectin) and to increase productivity, robustness and product yield.
Lignocellulosic biomass is abundant, however is in general not readily fermented by wild-type ethanol producing micro-organisms, such as S. cerevisiae. The biomass has to be hydrolysed. The resultant hydrolysate is often a mixture of various monosaccharides and oligosaccharides, which may not all be suitable substrates for the wild-type micro-organism. Further, the hydrolysates typically comprise acetic acid, formed as a by-product in particular when hydrolysing pectin or hemicellulose, and—dependent on the type of hydrolysis—one or more other by-products or residual reagents that may adversely affect the fermentation. In particular, acetic acid has been reported to negatively affect the kinetics and/or stoichiometry of sugar fermentation by wild-type and genetically modified S. cerevisiae strains and its toxicity is strongly augmented at low culture pH (Helle et al. Enzyme Microb Technol 33 (2003) 786-792; Bellissimi et al. FEMS Yeast Res 9 (2009) 358-364).
Various approaches have been proposed to improve the fermentative properties of ethanol producing organisms by genetic modification, and to improve the hydrolysis process of the biomass. E.g. an overview of developments in the fermentative production of ethanol from biomass hydrolysates is given in a review by A. van Maris et al. (Antonie van Leeuwenhoek (2006) 90:391-418). Reference is made to various ways in which S. cerevisiae may be modified and to various methods of hydrolysing lignocellulosic biomass.
A major challenge relating to the stoichiometry of yeast-based ethanol production is that substantial amounts of glycerol are invariably formed as a by-product. It has been estimated that, in typical industrial ethanol processes, up to about 4 wt. % of the sugar feedstock is converted into glycerol (Nissen et al. Yeast 16 (2000) 463-474). Under conditions that are ideal for anaerobic growth, the conversion into glycerol may even be higher, up to about 10%.
Glycerol production under anaerobic conditions is primarily linked to redox metabolism. During anaerobic growth of S. cerevisiae, sugar dissimilation occurs via alcoholic fermentation. In this process, the NADH formed in the glycolytic glyceraldehyde-3-phosphate dehydrogenase reaction is reoxidized by converting acetaldehyde, formed by decarboxylation of pyruvate to ethanol via NAD+-dependent alcohol dehydrogenase. The fixed stoichiometry of this redox-neutral dissimilatory pathway causes problems when a net reduction of NAD to NADH occurs elsewhere in metabolism. Under anaerobic conditions, NADH reoxidation in S. cerevisiae is strictly dependent on reduction of sugar to glycerol. Glycerol formation is initiated by reduction of the glycolytic intermediate dihydroxyacetone phosphate to glycerol 3-phosphate, a reaction catalyzed by NAD+-dependent glycerol 3-phosphate dehydrogenase. Subsequently, the glycerol 3-phosphate formed in this reaction is hydrolysed by glycerol-3-phosphatase to yield glycerol and inorganic phosphate. Consequently, glycerol is a major by-product during anaerobic production of ethanol by S. cerevisiae, which is undesired as it reduces overall conversion of sugar to ethanol. Further, the presence of glycerol in effluents of ethanol production plants may impose costs for waste-water treatment.
It is an object of the invention to provide a novel recombinant cell, which is suitable for the anaerobic, fermentative production of ethanol from a carbohydrate, in particular a carbohydrate obtained from lignocellulosic biomass, which has a reduced glycerol production compared to its corresponding wild-type organism or which lacks glycerol production if the cell is used for the fermentative preparation of ethanol.
It is further an object to provide a novel method for fermentatively preparing ethanol in anaerobic yeast cultures, in which method no glycerol is formed, or at least wherein less glycerol is formed than in a method making use of known strains of S. cerevisiae.
One or more further objects that may be met are apparent from the description and/or claims.
The inventors have realized that it is possible to meet one or more of these objectives by providing a specific recombinant cell wherein a specific other enzymatic activity has been incorporated, which allows re-oxidation of NADH formed in the fermentation of a carbohydrate, also in the absence of enzymatic activity needed for the NADH-dependent glycerol synthesis.
Accordingly the present invention relates to a recombinant yeast cell, the cell comprising one or more recombinant, in particular one or more heterologous, nucleic acid sequences encoding an NAD+-dependent acetylating acetaldehyde dehydrogenase (EC 1.2.1.10) activity.
The inventors have in particular realized that it is advantageous to provide a cell without enzymatic activity needed for the NADH-dependent glycerol synthesis or a cell with reduced enzymatic activity needed for the NADH-dependent glycerol synthesis.
Accordingly, the invention in particular relates to a recombinant yeast cell comprising one or more heterologous nucleic acid sequences encoding an NAD+-dependent acetylating acetaldehyde dehydrogenase activity, wherein the cell lacks enzymatic activity needed for the NADH-dependent glycerol synthesis (i.e. is free of such activity), or wherein the cell has a reduced enzymatic activity with respect to NADH-dependent glycerol synthesis compared to its corresponding wild-type yeast cell.
The invention is further directed to the use of a cell according to the invention for the preparation of ethanol.
In particular, the invention is further directed to a method for preparing ethanol, comprising preparing ethanol from a fermentable carbohydrate and from acetate, which preparation is carried out under anaerobic fermentative conditions using a yeast cell, said cell expressing acetyl-Coenzyme A synthetase activity and NAD+-dependent acetylating acetaldehyde dehydrogenase activity, said cell preferably lacking enzymatic activity needed for the biochemical pathway for glycerol synthesis from a carbohydrate or having a reduced enzymatic activity with respect to the biochemical pathway for glycerol synthesis from a carbohydrate compared to a wild-type S. cerevisiae cell.
Advantageously, in accordance with the invention ethanol is produced in a molar ratio of glycerol:ethanol of less than 0.04:1, in particular of less than 0.02:1, preferably of less than 0.01:1. Glycerol production may be absent (undetectable), although at least in some embodiments (wherein NADH-dependent glycerol synthesis is reduced yet not completely prohibited) some glycerol may be produced as a side-product, e.g. in a ratio glycerol to ethanol of 0.001:1 or more. | {
"pile_set_name": "USPTO Backgrounds"
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1. Field of the Invention
This invention pertains to improvements in memory cell array layouts and designs, and more particularly to improvements in memory cell bit line structures, and still more particularly to improvements in twisted bit line structures and methods for making same.
2. Relevant Background
An electrical schematic diagram of a portion 10 of a memory array in which the bit line structure and method for making it in which the invention may be practiced is shown in FIG. 1. As is well known, the memory array includes a number of word lines w1 . . . w6, and complementary bit line pairs b1, b2, b2, b3, and so on.
Sensing amplifiers 12, 12xe2x80x2, 12xe2x80x3, . . . are provided in association with each bit line pair. As is known, when noise, denoted by the arrows 14xe2x80x9414 appears across a pair of bit of lines, such as bit lines b2 and b2, the noise may be conducted to the sensing amplifier 12xe2x80x2, and may erroneously be interpreted as data, lack of data, or undesirably modified data.
It is well known that by twisting bit line structures in integrated circuits, such as memory cells, or the like, noise that may be induced into the bit line structure can be effectively canceled. Various bit line layouts are shown in FIG. 2. For example, in FIG. 2a, a bit line arrangement is shown in which no twist exists within the bit line pairs. This is similar to the bit line arrangement of the memory array of FIG. 1. In FIG. 2b, a bit line arrangement is shown in which the twist is provided in a bit line pair located between two untwisted bit line pairs. This twist arrangement results in significantly better noise cancellation than the untwisted layout of FIG. 2a, but does not provide perfect noise cancellation. In FIG. 2c, a bit line arrangement is shown in which the twist is provided in each bit line pair, with the twist arranged in a staggered relationship with respect to each other. This bit line arrangement provides the best noise cancellation of the three examples shown in FIG. 2.
More particularly, the physical layout of a typical bit line twist structure is shown in FIG. 3. As shown, bit line b1 and b3 are continuous, but complementary bit lines b2 and b2 are interconnected with a twist structure 18. In order to accomplish the twist, bit lines b2 and b2 are made discontinuous so that the respective ends of the bit line b2 and bit line b2 can be interconnected.
Thus, a diagonal conducting trace 20 is provided between bit line b2 on the right and bit line b2 on the left in a continuous pattern. All of the bit lines and the diagonal interconnect 20 are formed on a single level, for example, on a dielectric layer of an underlying substrate (not shown). In order to connect the left side of bit line b2 to the right side of bit line b2, an upper or lower level diagonal interconnect 22 is employed. The interconnect 22 is connected to the associated bit line segments of b2 and b2 through vias 24 and 26, and is formed in a vertical location separated from the bit line segments by a dielectric layer (not shown). Typically the interconnect 22 is formed above the level of the bit line traces, but, as mentioned, can be formed at a lower level.
Thus, conventionally, bit line structures are laid out on a semiconductor substrate by a number of parallel conductive traces. At pre-determined locations, the traces are formed in a discontinuous manner, with a diagonal interconnection made between the first set of the conductive traces and, on a different integrated circuit level, with a second diagonal interconnection between the second trace portions, with connections made to the traces by vias or other inter-level interconnections.
Thus, in the past, bit line construction has been accomplished by depositing a number of the conductive traces onto a semiconductor substrate, with spaced apart diagonal conductors formed between selected adjacent bit lines and with discontinuities in the respective lines that will subsequently be interconnected. After an insulating layer has been formed over the bit line structure, vias are formed through the insulating layer to the surfaces of the discontinuous bit lines. Thereafter, a diagonal conductor segment is formed to interconnect the discontinuous bit lines through the vias. Of course, the vertical order and placement of the diagonal interconnection may be varied, with the diagonal interconnection being first formed and the bit line structure being formed over an insulating layer in which are properly located vias may have been formed.
Thus, in order to construct twisted bit lines, a first bit line is typically constructed at an original level, and portions or segments of a second bitline are constructed parallel to the first bit line. However, in order for the second and bit line to be constructed without shorting to the first as it crosses thereover, an interconnection must be provided that is insulated from the first bit line. Such interconnection is generally constructed to be located either over or under the first and separated therefrom by a suitable insulation layer; typically, the interconnections of the second bit line are located at an upper level that is separated and insulated from the first bit line.
It should be noted that in the past, in the formation of the bitlines, a reticle has been used in which a number of opaque parallel line segments are formed on a glass substrate. The opaque parallel line segments may be formed, for example, of chromium or other material on the glass or other transparent substrate. The reticle is placed on or adjacent a surface of a substrate on which a photosensitive material has been deposited. Light is passed through the reticle, and is masked by the opaque line segments formed thereon but allowed to pass by the adjacent transparent line segments, to expose unmasked portions of the photosensitive material to the light. This causes a chemical change in the material that allows selected portions (for example, the light exposed portions) of the material to be removed.
However, since the typical scales patterned on wafers are comparable to the wave length of the light used in lithography equipment, the resulting pattern on the photosensitive material on the substrate therefore may have blurred or fuzzy edge definitions. When the photo sensitive material is removed during subsequent processing steps, the blurred or fuzzy edge definition may result in an inaccurate patterning, which, in turn, may result in unintended contact between adjacent memory array structures, such as the bit lines of concern herein.
To address this problem, a so-called xe2x80x9cLevensonxe2x80x9d reticle has been proposed in which selected portions of the glass substrate between masked elements are etched. The etched regions are, referred to as xe2x80x9cxcfx80xe2x80x9d regions, or xe2x80x9cphases,xe2x80x9d and the unetched regions are referred to as xe2x80x9c0xe2x80x9d regions, or xe2x80x9cphasesxe2x80x9d. By careful selection of the xe2x80x9cxcfx80xe2x80x9d and xe2x80x9c0xe2x80x9d regions, a pattern can be produced onto a semiconductor device having known semiconductor processing layers thereon which have sharply defined edges. Since the etched portions of the reticle are lower than the unetched portions, light passing through the reticle has a smaller light path, and therefore causing interference patterns, on the photo resist or substrate being patterned. This results in significantly better integrated circuit structure formation. In fact, it has been estimated that a Levenson reticle can produce line patterns with approximately twice the resolution of that of a conventional reticle.
The process by which the bit lines are formed includes the exposure of a photo sensitive layer (not shown) that has been deposited or formed onto the surface of the substrate on which the bit lines are to be constructed. In the past, a reticle mask 30 has been provided, as shown in FIG. 4a. The reticle mask includes a number of mask elements 32 formed on a surface 30 of a glass substrate 36. The mask elements 32 may be, for example, metal, such as chromium or the like. Typical scales on wafers are comparable to the wave length of the light used in lithography equipment. As a result, light that passes through the inter-spaces between the mask elements 32 produces interference patterns on the photo sensitive substrate when it is exposed. A typical pattern from a conventional reticle mask is shown in FIG. 4b. This results in imprecise line patterns, which can lead to shorting between adjacent bit line structures, especially as feature sizes in integrated circuit devices becomes smaller and smaller.
In light of the above, it is, therefore, an object of the invention to provide an improved method for making an improved twisted bit line.
It is another object of the invention to provide a method for constructing twisted bit lines using a xe2x80x9cLevensonxe2x80x9d mask, in which bit line diagonal connections can be made between bit line structures according to the Levenson phase shift layout rules.
It is yet another object of the invention to provide an improved bit line structure.
It is still another object of the invention to provide an improved bit line structure of the type described that may be more reliably constructed to avoid inadvertent shorts or contacts to adjoining integrated circuit structures.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
Thus, according tot present invention, a method is presented for making twisted bit line structures in an integrated circuit, such as an integrated circuit memory chip, or the like, using two Levenson phase shift rules: 1) structures with different phase must not touch; 2) and geometries, separated by the minimum design rule for the integrated circuit under consideration, should be constructed with different phases, Following these rules, thereover, and in accordance with a preferred embodiment of the present invention, a method is presented for interconnecting selected bit lines to accomplish a twisted bit line structure, by providing an interconnection between bit line segments that are untwisted in locations adjacent to locations at which the twist is provided in an adjacent bit line pair. Thus, if a series of bit line traces are formed with alternate xe2x80x9cxcfx80xe2x80x9d and xe2x80x9c0xe2x80x9d phases, interconnections can be made at upper or lower integrated circuit structural levels of both the twisted and untwisted bit line traces, to accomplish the twisted bit line structure.
In accordance with a broad aspect of the invention, therefore, a method for constructing a twisted bit line structure in an integrated memory circuit is presented. The method includes forming bit line traces on an integrated circuit substrate using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit line trace segments with discontinuous regions between segments of an interior pair of traces, with each xe2x80x9cphase xcfx80xe2x80x9d bit line trace being adjacent a xe2x80x9cphase 0xe2x80x9d bit line trace along two perpendicular axes. Twist connections are formed between first and second segments of a center pair of said bit line trace segments with each interconnection being formed at a different level from a level at which the bit line traces are formed.
According to another broad aspect of the invention, a twisted bit line structure for an integrated memory circuit is presented. The structure includes a plurality of bit line trace segments. At least a pair of the untwisted bit line trace segments are located adjacent and substantially parallel to an adjacent twisted bit line pair of bit line trace segments. Interconnections are established between discontinuous portions of the bit lines segments of the twisted bit line segments, the interconnection being contained on different levels from a level on which the bit line segments are contained. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to a mechanical timepiece comprising an oscillator, the oscillating motion of which is maintained by a mainspring, in which a periodic energy storage device is disposed between this mainspring and an escapement associated with said oscillator.
2. Description of Related Art
The energy source for said mechanical timepieces is constituted by a mainspring constituted by a leaf spring wound in a barrel, its outer end being fixedly connected to the barrel drum, whereas its inner end is fixedly connected to the arbor of this barrel. Upon slackening, the mainspring drives the barrel drum. The latter has an external toothing engaging with the train of the timepiece, which toothing ends at the escapement intended to transmit the force of the mainspring to the regulator. With each turn of the hairspring, the latter trips a tooth of the escapement wheel, which, under the pressure exerted upon the train by the barrel spring, transmits to it an impulse serving to maintain the oscillation of the hairspring.
The force exerted by this mainspring upon the train is clearly not the same when this spring is fully wound or at the end of its winding. Consequently, the force transmitted by the escapement to the hairspring is not constant and the amplitude of the balance wheel varies, affecting its isochronism. Its period of oscillation will be shorter when the force is greater, whereas it will lengthen once this force diminishes.
Indeed, it has already been proposed to store energy temporarily between the barrel and the escapement in order to deliver a constant energy to the regulator system. The known devices to this effect can no longer be operated once the spring has been fully unwound, such that means have to be provided to stop the timepiece prior to complete unwinding of the mainspring so as to allow restarting of this timepiece after it has been rewound.
Moreover, these devices are not designed to be able to be housed in a watch, especially in a wrist watch, but are rather intended for clocks in which the problem of bulk does not have the same importance as in watches and particularly in wrist watches. | {
"pile_set_name": "USPTO Backgrounds"
} |
The following methods are conventionally used to control or determine a light emission amount when an image is sensed by using a flash of an image sensing apparatus.
First method: Flash light is emitted toward an object to receive the reflected light from the object by a sensor. When the obtained integral value has reached a defined value, the light emission is stopped.
Second method: Preemission is performed once, and the brightness of an object at that time is loaded by an image sensor. On the basis of this loaded condition, the light amount for image sensing is determined.
Third method: Preemission is repeated a number of times, and the light emission amount for image sensing is determined by integrating the brightness.
In the first method, however, the sensor for receiving the reflected light from an object is necessary in addition to the image sensor. This is disadvantageous in making the image sensing apparatus compact and reducing the cost. Also, no correct light amount can be obtained by the sensor depending on the reflectance or position of an object.
In the second method, no correct light amount can be determined unless the object's brightness indicated by the reflected light obtained by preemission is appropriate (not too bright or not too dark).
To solve these problems, the light amount of preemission can be selected on the basis of distance information. However, the determined light amount for image sensing can be inappropriate in some cases owing to calculation errors of the distance information. Also, this method cannot be performed if a distance information collecting means such as auto-focusing is omitted in order to make the image sensing apparatus compact or reduce the cost.
In the third method, electricity and time are wasted by a number of times of preemission. Time is wasted especially when a light emitting device (e.g., a light emitting device using an LED as a light emitting means) which emits weak light and requires a long irradiation time is used.
The present invention relates to a light emitting device for an image sensing apparatus, an image sensing apparatus with a light emitting device, and an image sensing method which have been made to solve the above conventional problems. | {
"pile_set_name": "USPTO Backgrounds"
} |
1. Field of the Invention
The present invention relates to a method for preparing a catalyst used in producing methacrolein and methacrylic acid by the gas-phase catalytic oxidation of isobutylene or tert-butanol.
2. Description of the Prior Art
A large number of catalysts are known in regard to the production of methacrolein and methacrylic acid by the gas-phase catalytic oxidation of isobutylene or tert-butanol. Also, a large number of methods for producing the catalysts have been proposed. For example, Japanese Patent Application Kokai No. 57 12827 discloses that, in producing a multicomponent catalyst comprising molybdenum, bismuth, lead and antimony used in the ammoxidation of propylene, an aqueous slurry is adjusted to a pH of 7 or less. Further, U.S. Pat. No. 4,224,193 discloses that, in producing a multicomponent catalyst comprising molybdenum, bismuth, iron and an alkali metal (e.g. potassium, rubidium) used in the oxidation of propylene or isobutylene, it is preferred to finally adjust the pH of an aqueous slurry to 1 to 5. However, the above methods are complicated and expensive in producing a catalyst industrially. Further, since these methods require nitric acid or ammonia as a pH controlling agent, they have a problem that a large amount of NOx is generated when drying and baking the catalyst. | {
"pile_set_name": "USPTO Backgrounds"
} |
Embodiments of the inventive subject matter generally relate to the field of communication systems and, more particularly, to a coordinated back-off mechanism for path selection in a hybrid communication network.
Hybrid communication networks typically comprise multiple networking technologies (e.g., wireless local area network (WLAN) technologies, powerline communication technologies, Ethernet, etc.). The multiple networking technologies are typically interconnected using bridging-capable devices that forward packets between the different network technologies and media to form a single, extended communication network. Typically, the communication mechanisms, and protocol specifics (e.g., device and topology discovery, bridging to other networks, etc.) are unique to each networking technology. | {
"pile_set_name": "USPTO Backgrounds"
} |
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